diff -urNa -x .git original/u-boot-linaro-stable/Makefile u-boot/Makefile
--- original/u-boot-linaro-stable/Makefile 2016-08-02 12:12:08.623773665 +0900
+++ u-boot/Makefile 2016-08-02 14:19:39.729734088 +0900
@@ -21,9 +21,9 @@
# MA 02111-1307 USA
#
-VERSION = 2013
-PATCHLEVEL = 01
-SUBLEVEL = -rc1
+VERSION = 2016
+PATCHLEVEL = 02
+SUBLEVEL = 2
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
@@ -270,7 +270,8 @@
fs/reiserfs/libreiserfs.o \
fs/ubifs/libubifs.o \
fs/yaffs2/libyaffs2.o \
- fs/zfs/libzfs.o
+ fs/zfs/libzfs.o \
+ fs/romfs/libromfs.o
LIBS-y += net/libnet.o
LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/Makefile u-boot/arch/arm/cpu/armv7/mb86s7x/Makefile
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/Makefile 2016-08-02 14:19:39.766733929 +0900
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+
+COBJS += timer.o
+COBJS += soc.o
+COBJS += mb86s7x-mhu.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/config.mk u-boot/arch/arm/cpu/armv7/mb86s7x/config.mk
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/config.mk 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/config.mk 2016-08-02 14:19:39.766733929 +0900
@@ -0,0 +1 @@
+PLATFORM_CPPFLAGS += -march=armv7-a -mno-unaligned-access
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/lowlevel_init.S u-boot/arch/arm/cpu/armv7/mb86s7x/lowlevel_init.S
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/lowlevel_init.S 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/lowlevel_init.S 2016-08-02 14:19:39.766733929 +0900
@@ -0,0 +1,189 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb86s7x/lowlevel_init.S
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+
+/*
+ * lowlevel_init
+ */
+.globl lowlevel_init
+lowlevel_init:
+ /* STEP1 : CPU1 Sleeped */
+ /*
+ * read MultiProcessor ID register(MPIDR)
+ */
+ mrc p15,0,r0,c0,c0,5
+ and r0, r0, #0x3 @ extract CPUID,bits
+ cmp r0, #1 @ 0x0 : processor is CPU0
+ @ 0x1 : processor is CPU1
+ bleq CA9_1_SLEEP @ CPU1 Sleeped
+
+#if 0 /* skip PLL operation, it should be done by Cortex-M3 */
+ /* STEP2 : check PLL Locked */
+ ldr r0, =CRG_BASE @ 0xfff60000
+PLL_LOCKED_CHECK:
+ ldr r1, [r0, #CRG_PLLRDY]
+ and r1, r1, #0x7
+ cmp r1, #0x7 @ bit0:MAIN_CRG11 PLLRDY status
+ @ bit1:DMC_CRG11 PLLRDY status
+ @ bit2:GMAC_CRG11 PLLRDY status
+ @ 0 -> Unlocked.
+ @ 1 -> Locked.
+ bne PLL_LOCKED_CHECK
+#endif
+
+ /* STEP3 : Initialize Core */
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SDRAM_STACK_0 @ AP Trusted RAM
+
+#if 0
+ /* STEP4 : Initialize MEMC */
+ push {ip, lr}
+ bl init_memc @ Call external function
+ pop {ip, lr}
+
+ /* STEP5 : Initialize Data bahn */
+ push {ip, lr}
+ bl init_ddr3c @ Call external function
+ pop {ip, lr}
+
+ /* STEP6 : Initialize Peripheral Macro */
+ /*
+ * CRG11
+ * CRRRS : Deasserting Request for RRESETn
+ */
+ ldr r0, =CRG_BASE @ 0xfff60000
+ ldr r1, = 0x000000ff
+ str r1, [r0, #CRG_CRRRS]
+
+ /*
+ * CRG11 Frequency Setting
+ */
+ ldr r0, =CRG_BASE @ 0xfff60000
+
+ /* CLK0 1/1 (500MHz) */
+ ldr r1, =0x00000000
+ str r1, [r0, #CRG_CRDM0]
+
+ /* CLK1,2 1/2 (250MHz) */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRDM1]
+ str r1, [r0, #CRG_CRDM2]
+
+ /* CLK3 1/4 (125MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDM3]
+
+ /* CLK4,5,6 1/8 (62.5MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDM4]
+ str r1, [r0, #CRG_CRDM5]
+ str r1, [r0, #CRG_CRDM6]
+
+ /* CLK7,8 1/4 (125MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDM7]
+ str r1, [r0, #CRG_CRDM8]
+
+ /* CLK9,A,B 1/2 (250MHz) */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRDM9]
+ str r1, [r0, #CRG_CRDMA]
+ str r1, [r0, #CRG_CRDMB]
+
+ /* CLKC 1/4 (125MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDMC]
+
+ /* CLKD 1/8 (62.5MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDMD]
+
+ /* CLKE 1/16 (31.25MHz) */
+ ldr r1, =0x0000000f
+ str r1, [r0, #CRG_CRDME]
+
+ /* CLKF 1/8 (62.5MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDMF]
+
+ /* update clock divider mode */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRCDC]
+
+CLOCK_DIVIDER_UPDATE_CHECK:
+ ldr r1, [r0, #CRG_CRCDC]
+ tst r1, #0x1 @ bit0:DCHREQ
+ @ 0 -> The divider mode are updated.
+ @ 1 -> The divider mode are not updated.
+ bne CLOCK_DIVIDER_UPDATE_CHECK
+#endif
+
+ /* STEP7 : Initialize Memory System */
+ /*
+ * Invalidate L1/L2 icache
+ */
+ push {ip, lr}
+ bl invalidate_dcache_all @ Call external function
+ pop {ip, lr}
+
+ mov pc, lr
+
+CA9_1_SLEEP:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SDRAM_STACK_1 @ AP Trusted RAM
+
+ /*
+ * Invalidate L1/L2 icache
+ */
+ push {ip, lr}
+ bl invalidate_dcache_all @ Call external function
+ pop {ip, lr}
+
+#if 0
+ ldr r0, =MRBC_BASE
+ ldr r1, =0x0
+ str r1, [r0, #MRBC_GPREG0]
+#endif
+
+ /*
+ * Enable GICC irq
+ */
+ ldr r0, =GIC_IC_PHY_BASE
+ ldr r1, =0xff
+ str r1, [r0, #GICC_PRIMASK]
+ ldr r1, =0x1
+ str r1, [r0, #GICC_CTL]
+
+BACK_TO_SLEEP:
+ wfi @ sleep
+
+ /*
+ * read GICC_IAR
+ */
+ ldr r1, [r0, #GICC_INTACK]
+
+ /*
+ * set EOI
+ */
+ str r1, [r0, #GICC_EOI]
+
+ B BACK_TO_SLEEP
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/mb86s7x-mhu.c u-boot/arch/arm/cpu/armv7/mb86s7x/mb86s7x-mhu.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/mb86s7x-mhu.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/mb86s7x-mhu.c 2016-08-02 14:19:39.767733925 +0900
@@ -0,0 +1,308 @@
+/*
+ * mb86s7x MHU support
+ * Copyright (C) 2014 Linaro, Ltd
+ * Andy Green
+ */
+
+#include
+#include
+#include
+
+
+#ifdef CONFIG_MB86S7X_MHU
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#ifndef MB86S7X_MHU_PHYS
+#error MHU Address not specified
+#endif
+
+#include "mhu.h"
+#include
+#include "scb_mhu_api.h"
+
+#define RX_CHAN 0x20 // shared-mem offset: non-secure high priority ch region for SCP to AP
+#define TX_CHAN 0x120 // shared-mem offset: non-secure high priority ch region for AP to SCP
+
+
+int mhu_send(u32 ch)
+{
+ u32 val, count = 10000000;
+
+ /* defeat any pending traffic */
+ writel(readl(MB86S7X_MHU_PHYS + TX_CHAN + INTR_STAT_OFS),
+ MB86S7X_MHU_PHYS + TX_CHAN + INTR_CLR_OFS);
+ writel(readl(MB86S7X_MHU_PHYS + RX_CHAN + INTR_STAT_OFS),
+ MB86S7X_MHU_PHYS + RX_CHAN + INTR_CLR_OFS);
+
+ /* notify scb we're sending this command */
+ writel(ch, MB86S7X_MHU_PHYS + TX_CHAN + INTR_SET_OFS);
+
+ /* wait for command taken */
+ do {
+ val = readl(MB86S7X_MHU_PHYS + TX_CHAN + INTR_STAT_OFS);
+ } while (--count && val);
+ if (val)
+ return val;
+
+ /* wait for reply */
+
+ count = 10000000;
+ do {
+ val = readl(MB86S7X_MHU_PHYS + RX_CHAN + INTR_STAT_OFS);
+ } while (--count && !val);
+
+ writel(readl(MB86S7X_MHU_PHYS + RX_CHAN + INTR_STAT_OFS),
+ MB86S7X_MHU_PHYS + RX_CHAN + INTR_CLR_OFS);
+
+ return !val;
+}
+
+
+int mhu_send_norep(u32 ch)
+{
+ u32 val, count = 1000000;
+
+ /* defeat any pending traffic */
+ writel(readl(MB86S7X_MHU_PHYS + TX_CHAN + INTR_STAT_OFS),
+ MB86S7X_MHU_PHYS + TX_CHAN + INTR_CLR_OFS);
+ writel(readl(MB86S7X_MHU_PHYS + RX_CHAN + INTR_STAT_OFS),
+ MB86S7X_MHU_PHYS + RX_CHAN + INTR_CLR_OFS);
+
+ /* notify scb we're sending this command */
+ writel(ch, MB86S7X_MHU_PHYS + TX_CHAN + INTR_SET_OFS);
+
+ /* wait for command taken */
+ do {
+ val = readl(MB86S7X_MHU_PHYS + TX_CHAN + INTR_STAT_OFS);
+ } while (--count && val);
+ if (!count) {
+ puts(" TIMEOUT 1\n");
+ return 1;
+ }
+ if (val)
+ return val;
+}
+
+u32 get_scb_version(void)
+{
+ struct cmd_scb_version *cmd;
+ u32 ret;
+
+ cmd = cmd_to_scb;
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_GET_SCB_CAPABILITY, UBOOT_ID, 0);
+ cmd->header.status = 0;
+
+ ret = mhu_send(AP_REQ);
+
+ if(!ret) {
+ cmd = rsp_from_scb;
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ return -1;
+ }
+ return cmd->payload.version;
+ }
+
+ return 0;
+}
+
+u32 get_sys_flash_size(void)
+{
+ switch(get_scb_version() & MB86S7X_SYS_FLASH_SIZE_MASK) {
+ case MB86S7X_SYS_FLASH_SIZE_8MB:
+ return 0x00800001;
+ case MB86S7X_SYS_FLASH_SIZE_2MB:
+ return 0x00200000;
+ case MB86S7X_SYS_FLASH_SIZE_4MB:
+ default:
+ return 0x00400000;
+ }
+}
+
+int set_power_state(u32 pd_index, u32 state)
+{
+ struct cmd_powerdomain_set volatile *cmd = cmd_to_scb;
+ u8 len;
+ len = sizeof(cmd->payload);
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_SET_POWER_SUPPLY, UBOOT_ID, len);
+ cmd->header.status = 0;
+
+ cmd->payload.power_supply_id = pd_index;
+ cmd->payload.voltage = state;
+
+ if (mhu_send(AP_REQ)) {
+ //debug(" Failed to set power domain state\n");
+ return -1;
+ }
+
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ printf("power domain id = %x\n",pd_index);
+ return -1;
+ }
+
+ return 0;
+}
+
+int get_power_state(u32 pd_index)
+{
+ struct cmd_powerdomain_get volatile *cmd = cmd_to_scb;
+
+ u8 len;
+ len = sizeof(cmd->payload);
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_GET_POWER_SUPPLY, UBOOT_ID, len);
+ cmd->header.status = 0;
+
+ cmd->payload.power_supply_id = pd_index;
+
+ if (mhu_send(AP_REQ)) {
+ //debug(" Failed to get power domain state\n");
+ //return PHYS_SDRAM_SIZE;
+ return 0;
+ }
+
+ cmd = rsp_from_scb;
+
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ printf("power domain id = %x\n",pd_index);
+ return 0;
+ }
+
+ return cmd->payload.voltage;
+}
+
+int set_clk_state(u32 cntrlr, u32 domain, u32 port, u32 en)
+{
+ struct cmd_periclk_control *cmd = cmd_to_scb;
+
+ u8 len;
+ u32 id;
+ len = sizeof(cmd->payload);
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_SET_CLOCK_VALUE, UBOOT_ID, len);
+ cmd->header.status = 0;
+
+ id = (u32)( cntrlr << 8 | domain << 4 | port );
+ cmd->payload.id = id;
+ cmd->payload.frequency = en;
+
+ if(!mhu_send(AP_REQ)) {
+ cmd = rsp_from_scb;
+
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ printf("clock id = %x\n",id);
+ return -1;
+ }
+
+ }
+ return 0;
+}
+
+int get_memory_layout(void)
+{
+ int m = 0;
+ int ret = 0;
+ struct cmd_memory_layout *cmd = cmd_to_scb;
+ u8 len;
+ //len = sizeof(cmd->payload);
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_GET_MEMORY_LAYOUT, UBOOT_ID, 0);
+ cmd->header.status = 0;
+
+ ret = mhu_send(AP_REQ);
+
+ if (!ret) {
+ cmd = rsp_from_scb;
+ /*
+ cmd->payload.count_regions = 2;
+ cmd->payload.regions[0].start = 0x80000000LLU;
+ cmd->payload.regions[0].length = 0x800LLU * 0x100000LLU;
+ cmd->payload.regions[1].start = 0x880000000LLU;
+ cmd->payload.regions[1].length = (0x800LLU - 0x800LLU) * 0x100000LLU;
+ */
+
+ for (m = 0; m < cmd->payload.count_regions; m++) {
+#if defined(CONFIG_MB86S7X)
+ gd->bd->bi_dram[m].start_high =
+ (ulong)(cmd->payload.regions[m].start >> 32);
+ gd->bd->bi_dram[m].start =
+ (ulong)(cmd->payload.regions[m].start & 0xFFFFFFFF);
+ gd->bd->bi_dram[m].size_high =
+ (ulong)(cmd->payload.regions[m].length >> 32);
+ gd->bd->bi_dram[m].size = (ulong)
+ (cmd->payload.regions[m].length & 0xFFFFFFFF);
+#else
+ gd->bd->bi_dram[m].start = cmd->payload.regions[m].start;
+ gd->bd->bi_dram[m].size = cmd->payload.regions[m].length;
+#endif
+ }
+ }
+
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ return cmd->header.status ;
+ }
+ else
+ return ret;
+}
+
+int mhu_check_pcie_capability(void)
+{
+ struct cmd_scb_version volatile *cmd = cmd_to_scb;
+
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_GET_SCB_CAPABILITY, UBOOT_ID, 0);
+ cmd->header.status = 0;
+
+ if (mhu_send(AP_REQ))
+ return 0;
+ else {
+ cmd = rsp_from_scb;
+
+
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ return 0;
+ }
+ /* older version scb don't have capabilities field */
+ if (cmd->header.cmd_e.payload_size < 12)
+ return 0;
+
+ return (cmd->payload.capabilities[0] & S7X_SCB_CAPABILITY0_PCIE) > 0;
+ }
+}
+
+int mhu_check_video_out_capability(void)
+{
+ struct cmd_scb_version volatile *cmd = cmd_to_scb;
+
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_GET_SCB_CAPABILITY, UBOOT_ID, 0);
+ cmd->header.status = 0;
+
+ if (mhu_send(AP_REQ))
+ return 0;
+ else {
+ cmd = rsp_from_scb;
+
+ /* check SCPI status field */
+ if (cmd->header.status > 0)
+ {
+ printf("Error header.status: %s\n",cmd->header.status);
+ return 0;
+ }
+ /* older version scb don't have capabilities field */
+ if (cmd->header.cmd_e.payload_size < 12)
+ return 0;
+ return (cmd->payload.capabilities[0] & S7X_SCB_CAPABILITY0_VIDEO_OUT) > 0;
+ }
+
+}
+
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/soc.c u-boot/arch/arm/cpu/armv7/mb86s7x/soc.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/soc.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/soc.c 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,136 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb86s7x/soc.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_MB86S7X_MHU
+#include
+#include
+#endif
+
+#ifdef CONFIG_MB86S7X_HS_SPI
+extern void hs_spi_cleanup(void);
+#endif
+
+void reset_cpu(ulong ignored)
+{
+ /* Use MHU command to do hard reset */
+
+#ifdef CONFIG_MB86S7X_MHU
+
+ struct cmd_system_set_state volatile *cmd = cmd_to_scb;
+
+ cmd->header.cmd = PACK_SCPI_CMD(CMD_SET_SYSTEM_POWER_STATE, UBOOT_ID, 1);
+ cmd->header.status = 0;
+ cmd->state = CPU_RESET;
+
+ if (mhu_send_norep(AP_REQ)) {
+ puts(" Failed do hard reset\n");
+ }
+ else {
+ /* going to reset */
+ }
+
+#endif
+ puts("Fail to restart.\n");
+
+ while (1);
+
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+#if defined(CONFIG_MB86S70)
+ printf("CPU: MB86S70:Cortex-A15/A7 big.LITTLE\n");
+#elif defined(CONFIG_MB86S72)
+ printf("CPU: MB86S72:Cortex-A15/A7 big.LITTLE\n");
+#elif defined(CONFIG_MB86S71)
+ printf("CPU: MB86S71:Cortex-A15/A7 big.LITTLE\n");
+#elif defined(CONFIG_MB86S73)
+ printf("CPU: MB86S73:Cortex-A7x2\n");
+#else
+#error Undefined Board
+#endif
+ return 0;
+}
+#endif
+
+#if CONFIG_DRIVER_FGMAC4
+int cpu_eth_init(bd_t *bis)
+{
+ return fgmac4_initialize(bis);
+}
+#endif
+
+#if defined(CONFIG_DRIVER_OGMA)
+int cpu_eth_init(bd_t *bis)
+{
+ return ogma_initialize(bis);
+}
+#endif
+
+#if defined(CONFIG_F_SDH30_SDHCI)
+extern
+int f_sdh30_sdhci_init(int regbase, int tmclk, int max_clk, int min_clk, int quirks);
+extern void f_sdh30_reset(void);
+
+int cpu_mmc_init(bd_t *bd)
+{
+ int err_sd = -1, err_emmc = -1;
+ int emmc_max_clk = 0;
+ int quirks = 0;
+
+#if defined(CONFIG_EMMC_MAX_CLOCK)
+ emmc_max_clk = CONFIG_EMMC_MAX_CLOCK;
+#endif
+#if defined(CONFIG_MMC_ADMA) && defined(CONFIG_SDHCI_AUTO_CMD23)
+ quirks = SDHCI_QUIRK_AUTO_CMD23;
+#elif defined(CONFIG_SDHCI_AUTO_CMD12)
+ quirks = SDHCI_QUIRK_AUTO_CMD12;
+#endif
+#if F_EMMC_BASE
+ err_emmc = f_sdh30_sdhci_init(F_EMMC_BASE, CONFIG_EMMC_CLOCK, emmc_max_clk, 400000, quirks);
+#endif
+ err_sd = f_sdh30_sdhci_init(F_SDH30_BASE, CONFIG_SD_CLOCK, 0, 400000, SDHCI_QUIRK_WAIT_SEND_CMD);
+ /* if both sd and emmc is not found, return error*/
+ if(err_sd && err_emmc)
+ return -1;
+ else
+ return 0;
+}
+
+void arch_preboot_os(void)
+{
+#ifdef CONFIG_MB86S7X_HS_SPI
+ hs_spi_cleanup();
+#endif
+ f_sdh30_reset();
+}
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/timer.c u-boot/arch/arm/cpu/armv7/mb86s7x/timer.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb86s7x/timer.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb86s7x/timer.c 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,133 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb86s7x/timer.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+
+/* Global Timer Register */
+#define TIMER_REG_LOAD (CONFIG_SYS_TIMERBASE + 0x00)
+#define TIMER_REG_VALUE (CONFIG_SYS_TIMERBASE + 0x04)
+#define TIMER_REG_CONTROL (CONFIG_SYS_TIMERBASE + 0x08)
+
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_FREQ (CONFIG_TIMER_CLK / 16) /* Peripheral clock is divided by 16 */
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastdec (gd->lastinc)
+
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, TIMER_FREQ);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= TIMER_FREQ;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+ writel(TIMER_LOAD_VAL, TIMER_REG_LOAD); /* decrement counter */
+
+ writel(0x86, TIMER_REG_CONTROL);
+ /* bit0: OnShot -> 0 = wrapping mode (default) */
+ /* bit1: TimerSize -> 1 = 32-bit counter. */
+ /* bit2-3: TimerPre -> 01 = 4 stages of prescale, clock is divided by 16 */
+ /* bit4: Reserved */
+ /* bit5: IntEnable -> 0 = Timer module Interrupt disabled */
+ /* bit6: TimerMode -> 0 = Timer module is in free-running mode (default) */
+ /* bit7: TimerEn -> 1 = Timer module enabled. */
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+ ulong now = readl(TIMER_REG_VALUE);
+
+ if (now <= lastdec) { /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (lastdec - now);
+ }
+ else {/* we have rollover of incrementer */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+ return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = readl(TIMER_REG_VALUE);
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return TIMER_FREQ;
+}
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/Makefile u-boot/arch/arm/cpu/armv7/mb8ac0300/Makefile
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/Makefile 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+SOBJS += memc_init.o
+
+COBJS := ddr3c_init.o
+COBJS += timer.o
+COBJS += soc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/config.mk u-boot/arch/arm/cpu/armv7/mb8ac0300/config.mk
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/config.mk 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/config.mk 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1 @@
+PLATFORM_CPPFLAGS += -march=armv7-a -mno-unaligned-access
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/ddr3c_init.c u-boot/arch/arm/cpu/armv7/mb8ac0300/ddr3c_init.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/ddr3c_init.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/ddr3c_init.c 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,743 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb8ac0300/ddr3c_init.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+
+void wait(u32 count)
+{
+ u32 i;
+
+ for(i=0; iCTL000 & START1) == START1)
+ {
+ /* Finished DDRC initialize */
+ return 0;
+ }
+
+/*
+ * Initialization procedure
+ */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x41C) = 0x00FF0F01;
+ *(volatile u32 *)((u32)DDR3C_BASE+0x420) = 0x01882222;
+
+ wait(10);
+
+ DATABAHN->CTL000 = DRAM_CLASS
+ | START0;
+
+ DATABAHN->CTL001 = MAX_CS_REG
+ | MAX_COL_REG
+ | MAX_ROW_REG;
+
+ DATABAHN->CTL002 = TINIT;
+
+ DATABAHN->CTL003 = TRST_PWRON;
+
+ DATABAHN->CTL004 = CKE_INACTIVE;
+
+ DATABAHN->CTL005 = TBST_INT_INTERVAL
+ | WRLAT
+ | CASLAT_LIN
+ | INITAREF;
+
+ DATABAHN->CTL006 = TRAS_MIN
+ | TRC
+ | TRRD
+ | TCCD;
+
+ DATABAHN->CTL007 = TMRD
+ | TRTP
+ | TRP
+ | TWTR;
+
+ DATABAHN->CTL008 = TRAS_MAX
+ | TMOD;
+
+ DATABAHN->CTL009 = AP
+ | WRITEINTERP
+ | TCKESR
+ | TCKE;
+
+ DATABAHN->CTL010 = TWR_INT
+ | TRCD_INT
+ | TRAS_LOCKOUT
+ | CONCURRENTAP;
+
+ DATABAHN->CTL011 = NO_CMD_INIT
+ | TDLL
+ | TDAL;
+
+ DATABAHN->CTL012 = TCPD
+ | TFAW
+ | BSTLEN;
+
+ DATABAHN->CTL013 = ADDRESS_MIRRORING
+ | REG_DIMM_ENABLE
+ | TRP_AB;
+
+ DATABAHN->CTL014 = RDIMM_CTL_0_31_0;
+
+ DATABAHN->CTL015 = RDIMM_CTL_0_63_32;
+
+ DATABAHN->CTL016 = RDIMM_CW_HOLD_CKE_EN
+ | RDIMM_CWW_REQ
+ | RDIMM_CWW_MAP;
+
+ DATABAHN->CTL017 = RDIMM_TSTAB
+ | RDIMM_TMRD;
+
+ DATABAHN->CTL018 = TREF_ENABLE
+ | AUTO_REFRESH_MODE
+ | AREFRESH
+ | REG_DIMM_PARITY_ERROR;
+
+ DATABAHN->CTL019 = TREF
+ | TRFC;
+
+ DATABAHN->CTL020 = POWER_DOWN
+ | TREF_INTERVAL;
+
+ DATABAHN->CTL021 = TXPDLL
+ | TPDEX;
+
+ DATABAHN->CTL022 = TXSNR
+ | TXSR;
+
+ DATABAHN->CTL023 = ENABLE_QUICK_SREFRESH
+ | SREFRESH_EXIT_NO_REFRESH
+ | PWRUP_SREFRESH_EXIT
+ | SREFRESH;
+
+ DATABAHN->CTL024 = PWRDN_SHIFT_DELAY
+ | CKE_DELAY;
+
+ DATABAHN->CTL025 = WRITE_MODEREG;
+
+ DATABAHN->CTL026 = MR0_DATA_0
+ | MRW_STATUS;
+
+ DATABAHN->CTL027 = MR2_DATA_0
+ | MR1_DATA_0;
+
+ DATABAHN->CTL028 = MR3_DATA_0
+ | MRSINGLE_DATA_0;
+
+ DATABAHN->CTL029 = MR1_DATA_1
+ | MR0_DATA_1;
+
+ DATABAHN->CTL030 = MRSINGLE_DATA_1
+ | MR2_DATA_1;
+
+ DATABAHN->CTL031 = ZQINIT
+ | MR3_DATA_1;
+
+ DATABAHN->CTL032 = ZQCS
+ | ZQCL;
+
+ DATABAHN->CTL033 = ZQ_IN_PROGRESS
+ | REFRESH_PER_ZQ
+ | ZQ_ON_SREF_EXIT
+ | ZQ_REQ;
+
+ DATABAHN->CTL034 = COLUMN_SIZE
+ | ADDR_PINS
+ | EIGHT_BANK_MODE
+ | ZQCS_ROTATE;
+
+ DATABAHN->CTL035 = ADDR_CMP_EN
+ | COMMAND_AGE_COUNT
+ | AGE_COUNT
+ | APREBIT;
+
+ DATABAHN->CTL036 = RW_SAME_EN
+ | PRIORITY_EN
+ | PLACEMENT_EN
+ | BANK_SPLIT_EN;
+
+ DATABAHN->CTL037 = CS_MAP
+ | INHIBIT_DRAM_CMD
+ | SWAP_PORT_RW_SAME_EN
+ | SWAP_EN;
+
+ DATABAHN->CTL038 = Q_FULLENESS
+ | FAST_WRITE
+ | REDUCT
+ | BURST_ON_FLY_BIT;
+
+ DATABAHN->CTL039 = RESYNC_DLL_PER_AREF_EN
+ | RESYNC_DLL
+ | CONTROLLER_BUSY;
+
+ DATABAHN->CTL040 = INT_STATUS;
+
+ DATABAHN->CTL041 = INT_ACK;
+
+ DATABAHN->CTL042 = INT_MASK;
+
+ DATABAHN->CTL043 = OUT_OF_RANGE_ADDR;
+
+ DATABAHN->CTL044 = OUT_OF_RANGE_TYPE
+ | OUT_OF_RANGE_LENGTH
+ | OUT_OF_RANGE_ADDR_33_32;
+
+ DATABAHN->CTL045 = OUT_OF_RANGE_SOURCE_ID;
+
+ DATABAHN->CTL046 = PORT_CMD_ERROR_ADDR;
+
+ DATABAHN->CTL047 = PORT_CMD_ERROR_TYPE
+ | PORT_CMD_ERROR_ID
+ | PORT_CMD_ERROR_ADDR_33_32;
+
+ DATABAHN->CTL048 = ODT_WR_MAP_CS0
+ | ODT_RD_MAP_CS0
+ | PORT_DATA_ERROR_ID;
+
+ DATABAHN->CTL049 = ADD_ODT_CLK_W2R_SAMECS
+ | ADD_ODT_CLK_R2W_SAMECS
+ | OUT_WR_MAP_CS1
+ | OUT_RD_MAP_CS1;
+
+ DATABAHN->CTL050 = R2W_DIFFCS_DLY
+ | R2R_DIFFCS_DLY
+ | ADD_ODT_CLK_SAMETYPE_DIFFCS
+ | ADD_ODT_CLK_DIFFTYPE_DIFFCS;
+
+ DATABAHN->CTL051 = R2W_SAMECS_DLY
+ | R2R_SAMECS_DLY
+ | W2W_DIFFCS_DLY
+ | W2R_DIFFCS_DLY;
+
+ DATABAHN->CTL052 = OCD_ADJUST_PUP_CS_0
+ | OCD_ADJUST_PDN_CS_0
+ | W2W_SAMECS_DLY
+ | W2R_SAMECS_DLY;
+
+ DATABAHN->CTL053 = SWLVL_EXIT
+ | SWLVL_START
+ | SWLVL_LOAD
+ | SWLVL_LEVELING_MODE;
+
+ DATABAHN->CTL054 = SWLVL_RESP_1
+ | SWLVL_RESP_0
+ | LVL_STATUS
+ | SWLVL_OP_DONE;
+
+ DATABAHN->CTL055 = WRLVL_CS
+ | WRLVL_REQ
+ | SWLVL_RESP_3
+ | SWLVL_RESP_2;
+
+ DATABAHN->CTL056 = WRLVL_EN
+ | WLMRD
+ | WLDQSEN;
+
+ DATABAHN->CTL057 = WRLVL_ERROR_STATUS
+ | WRLVL_REFRESH_INTERVAL;
+
+ DATABAHN->CTL058 = WRLVL_DELAY_0
+ | WRLVL_REG_EN;
+
+ DATABAHN->CTL059 = WRLVL_DELAY_2
+ | WRLVL_DELAY_1;
+
+ DATABAHN->CTL060 = RDLVL_GATE_REQ
+ | RDLVL_REQ
+ | WRLVL_DELAY_3;
+
+ DATABAHN->CTL061 = RDLVL_REG_EN
+ | RDLVL_BEGIN_DELAY_EN
+ | RDLVL_EDGE
+ | RDLVL_CS;
+
+ DATABAHN->CTL062 = RDLVL_BEGIN_DELAY_0
+ | RDLVL_GATE_REG_EN;
+
+ DATABAHN->CTL063 = RDLVL_MIDPOINT_DELAY_0
+ | RDLVL_END_DELAY_0;
+
+ DATABAHN->CTL064 = RDLVL_OFFSET_DIR_0
+ | RDLVL_OFFSET_DELAY_0;
+
+ DATABAHN->CTL065 = RDLVL_GATE_DELAY_0
+ | RDLVL_DELAY_0;
+
+ DATABAHN->CTL066 = RDLVL_END_DELAY_1
+ | RDLVL_BEGIN_DLEAY_1;
+
+ DATABAHN->CTL067 = RDLVL_OFFSET_DELAY_1
+ | RDLVL_MIDPOINT_DELAY_1;
+
+ DATABAHN->CTL068 = RDLVL_DELAY_1
+ | RDLVL_OFFSET_DIR_1;
+
+ DATABAHN->CTL069 = RDLVL_BEGIN_DELAY_2
+ | RDLVL_GATE_DELAY_1;
+
+ DATABAHN->CTL070 = RDLVL_MIDPOINT_DELAY_2
+ | RDLVL_END_DELAY_2;
+
+ DATABAHN->CTL071 = RDLVL_OFFSET_DIR_2
+ | RDLVL_OFFSET_DELAY_2;
+
+ DATABAHN->CTL072 = RDLVL_GATE_DELAY_2
+ | RDLVL_DELAY_2;
+
+ DATABAHN->CTL073 = RDLVL_END_DELAY_3
+ | RDLVL_BEGIN_DELAY_3;
+
+ DATABAHN->CTL074 = RDLVL_OFFSET_DELAY_3
+ | RDLVL_MIDPOINT_DELAY_3;
+
+ DATABAHN->CTL075 = RDLVL_DELAY_3
+ | RDLVL_OFFSET_DIR_3;
+
+ DATABAHN->CTL076 = AXI0_EN_SIZE_LT_WIDTH_INSTR
+ | RDLVL_GATE_DELAY_3;
+
+ DATABAHN->CTL077 = AXI0_FIFO_TYPE_REG;
+
+ DATABAHN->CTL078 = AXI1_EN_SIZE_LT_WIDTH_INSTR;
+
+ DATABAHN->CTL079 = AXI2_EN_SIZE_LT_WIDTH_INSTR
+ | AXI1_FIFO_TYPE_REG;
+
+ DATABAHN->CTL080 = AXI3_EN_SIZE_LT_WIDTH_INSTR
+ | AXI2_FIFO_TYPE_REG;
+
+ DATABAHN->CTL081 = AXI3_FIFO_TYPE_REG;
+
+ DATABAHN->CTL082 = AXI0_PRIORITY0_RELATIVE_PRIORITY
+ | WRR_PARAM_VALUE_ERR
+ | WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING
+ | WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL;
+
+ DATABAHN->CTL083 = AXI0_PORT_ORDERING
+ | AXI0_PRIORITY3_RELATIVE_PRIORITY
+ | AXI0_PRIORITY2_RELATIVE_PRIORITY
+ | AXI0_PRIORITY1_RELATIVE_PRIORITY;
+
+ DATABAHN->CTL084 = AXI1_PRIORITY1_RELATIVE_PRIORITY
+ | AXI1_PRIORITY0_RELATIVE_PRIORITY
+ | AXI0_PRIORITY_RELAX;
+
+ DATABAHN->CTL085 = AXI1_PORT_ORDERING
+ | AXI1_RPIORITY3_RELATIVE_PRIORITY
+ | AXI1_RPIORITY2_RELATIVE_PRIORITY;
+
+ DATABAHN->CTL086 = AXI2_PRIORITY1_RELATIVE_PRIORITY
+ | AXI2_PRIORITY0_RELATIVE_PRIORITY
+ | AXI1_PRIORITY_RELAX;
+
+ DATABAHN->CTL087 = AXI2_PORT_ORDERING
+ | AXI2_PRIORITY3_RELATIVE_PRIORITY
+ | AXI2_PRIORITY2_RELATIVE_PRIORITY;
+
+ DATABAHN->CTL088 = AXI3_PRIORITY1_RELATIVE_PRIORITY
+ | AXI3_PRIORITY0_RELATIVE_PRIORITY
+ | AXI2_PRIORITY_RELAX;
+
+ DATABAHN->CTL089 = AXI3_PORT_ORDERING
+ | AXI3_PRIORITY3_RELATIVE_PRIORITY
+ | AXI3_PRIORITY2_RELATIVE_PRIORITY;
+
+ DATABAHN->CTL090 = MEM_RST_VALID
+ | CKE_STATUS
+ | AXI3_PRIORITY_RELAX;
+
+ DATABAHN->CTL091 = TDFI_PHY_WRLAT
+ | DLL_RST_ADJ_DLY
+ | DLL_RST_DELAY;
+
+ DATABAHN->CTL092 = DRAM_CLK_DISABLE
+ | TDFI_RDDATA_EN
+ | TDFI_PHY_RDLAT
+ | UPDATE_ERROR_STATUS;
+
+ DATABAHN->CTL093 = TDFI_CTRLUPD_MAX
+ | TDFI_CTRLUPD_MIN;
+
+ DATABAHN->CTL094 = TDFI_PHYUPD_TYPE1
+ | TDFI_PHYUPD_TYPE0;
+
+ DATABAHN->CTL095 = TDFI_PHYUPD_TYPE3
+ | TDFI_PHYUPD_TYPE2;
+
+ DATABAHN->CTL096 = TDFI_PHYUPD_RESP;
+
+ DATABAHN->CTL097 = TDFI_CTRLUPD_INTERVAL;
+
+ DATABAHN->CTL098 = DFI_WRLVL_MAX_DELAY
+ | WRLAT_ADJ
+ | RDLAT_ADJ;
+
+ DATABAHN->CTL099 = TDFI_WRLVL_RESPLAT
+ | TDFI_WRLVL_LOAD
+ | TDFI_WRLVL_DLL
+ | TDFI_WRLVL_EN;
+
+ DATABAHN->CTL100 = TDFI_WRLVL_WW;
+
+ DATABAHN->CTL101 = TDFI_WRLVL_RESP;
+
+ DATABAHN->CTL102 = TDFI_WRLVL_MAX;
+
+ DATABAHN->CTL103 = RDLVL_GATE_MAX_DELAY
+ | RDLVL_MAX_DELAY;
+
+ DATABAHN->CTL104 = TDFI_RDLVL_RESPLAT
+ | TDFI_RDLVL_LOAD
+ | TDFI_RDLVL_DLL
+ | TDFI_RDLVL_EN;
+
+ DATABAHN->CTL105 = TDFI_RDLVL_RR;
+
+ DATABAHN->CTL106 = TDFI_RDLVL_RESP;
+
+ DATABAHN->CTL107 = RDLVL_RESP_MASK;
+
+ DATABAHN->CTL108 = RDLVL_GATE_RESP_MASK;
+
+ DATABAHN->CTL109 = RDLVL_GATE_PREAMBLE_CHECK_EN
+ | RDLVL_GATE_EN
+ | RDLVL_EN;
+
+ DATABAHN->CTL110 = TDFI_RDLVL_MAX;
+
+ DATABAHN->CTL111 = RDLVL_GATE_DQ_ZERO_COUNT
+ | RDLVL_DQ_ZERO_COUNT;
+
+ DATABAHN->CTL112 = RDLVL_ERROR_STATUS;
+ DATABAHN->CTL113 = RDLVL_GATE_REFRESH_INTERVAL
+ | RDLVL_REFRESH_INTERVAL;
+
+ DATABAHN->CTL114 = ODT_ALT_EN;
+
+ wait(10);
+
+/*
+ * Reset sequence
+ */
+
+ /* IRSTX 0->1 */
+ *(volatile u32 *)((u32)DDR3C_BASE+0x408) = 0x0000000F;
+
+ wait(1);
+
+ /* IDLLRSTX,IPZQRSTX 0->1 */
+ *(volatile u32 *)((u32)DDR3C_BASE+0x408) = 0x0003000F;
+
+ wait(11000); /* wait DLL Lock about 73us */
+
+ /* ISOFTRSTX 0->1 */
+ *(volatile u32 *)((u32)DDR3C_BASE+0x408) = 0x0007000F;
+
+/*
+ * PZQ initial calibration
+ */
+ wait(225000); /* wait PZQ_INIT about 1500us */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x440) = 0x00000000;
+
+ wait(10);
+
+ /* dfi_init_complete 0->1 */
+ *(volatile u32 *)((u32)DDR3C_BASE+0x404) = 0x00000001;
+
+ wait(20);
+
+ DATABAHN->CTL000 = DRAM_CLASS
+ | START1;
+
+ wait(20);
+
+/*
+ * Initial Setting End
+ */
+
+/* =================================================== */
+
+/*
+ * Write Leveling
+ */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x18C) = 0x141F0F10;
+ /* TDFI_WRLVL_DLL = 0xF */
+ /* TDFI_WRLVL_LOAD = 0x1F */
+ /* TDFI_WRLVL_RESPLAT = 0x14 */
+ /* TDFI_WRLVL_EN = 0x10 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x194) = 0x00000000;
+ /* TDFI_WRLVL_RESP = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x190) = 0x0000001A;
+ /* TDFI_WRLVL_WW = 0x1A */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x020) = 0x06DB000C;
+ /* TMOD = 0xC */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0E0) = 0x00002819;
+ /* WLDQSEN = 0x19 */
+ /* WLMRD = 0x28 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0DC) = 0x00000000;
+ /* WRLVL_CS = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00010001;
+ /* SW_LEVELING_MODE = 0x1 */
+ /* SWLVL_START = 0x1 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x06C) = 0x000010C0;
+ /* CS0 MRS(DRAM write leveling entry) */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0E8) = 0x00001E00;
+ /* WRLVL_DELAY_0 = 0x1E */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0EC) = 0x001A001C;
+ /* WRLVL_DELAY_1 = 0x1C */
+ /* WRLVL_DELAY_2 = 0x1A */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0F0) = 0x00000017;
+ /* WRLVL_DELAY_3 = 0x17 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x42C) = 0x000A3004;
+ /* r_txdq_sft_0,r_rxdqs_sft_0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x430) = 0x000A2F04;
+ /* r_txdq_sft_1,r_rxdqs_sft_1 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x434) = 0x000A2C04;
+ /* r_txdq_sft_2,r_rxdqs_sft_2 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x438) = 0x000A2A04;
+ /* r_txdq_sft_3,r_rxdqs_sft_3 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00000101;
+ /* SWLVL_LOAD = 0x1 */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ vSWLVL_RESP_0 = *((volatile unsigned long *)0xFFF4A0D8) & 0x00FF0000;
+ /* SWLVL_RESP_0 check */
+
+ vSWLVL_RESP_1 = *((volatile unsigned long *)0xFFF4A0D8) & 0xFF000000;
+ /* SWLVL_RESP_1 check */
+
+ vSWLVL_RESP_2 = *((volatile unsigned long *)0xFFF4A0DC) & 0x0000FF00;
+ /* SWLVL_RESP_2 check */
+
+ vSWLVL_RESP_3 = *((volatile unsigned long *)0xFFF4A0DC) & 0x000000FF;
+ /* SWLVL_RESP_3 check */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x01000001;
+ /* SWLVL_EXIT = 0x1 */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x06C) = 0x00001040;
+ /* CS0 MRS(DRAM write leveling exit) */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x18C) = 0x00000000;
+ /* TDFI_WRLVL_DLL = 0x0 */
+ /* TDFI_WRLVL_LOAD = 0x0 */
+ /* TDFI_WRLVL_RESPLAT = 0x0 */
+ /* TDFI_WRLVL_EN = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A4) = 0x00000000;
+ /* TDFI_RDLVL_RR = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00000000;
+ /* SW_LEVELING_MODE = 0x0 */
+
+ vINT_STATUS = *((volatile unsigned long *)0xFFF4A0A0);
+ vUPDATE_ERROR_STATUS = *((volatile unsigned long *)0xFFF4A170);
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0A4) = vINT_STATUS;
+
+
+/* =================================================== */
+
+/*
+ * Gate Training
+ */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A0) = 0x0D0F0F0F;
+ /* TDFI_RDLVL_DLL = 0xF */
+ /* TDFI_RDLVL_LOAD = 0x0F */
+ /* TDFI_RDLVL_RESPLAT = 0xD */
+ /* TDFI_RDLVL_EN = 0xF */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A8) = 0x00000000;
+ /* TDFI_RDLVL_RESP = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A4) = 0x0000001A;
+ /* TDFI_RDLVL_RR = 0x1A */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0F4) = 0x00000000;
+ /* RDLVL_CS = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00010003;
+ /* SW_LEVELING_MODE = 0x3 */
+ /* SWLVL_START = 0x1 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x070) = 0x00040000;
+ /* CS0 MRS DRAM MPR entry) */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0E8) = 0x00320000;
+ /* RDLVL_GATE_DELAY_0 = 0x32 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x114) = 0x00000030;
+ /* RDLVL_GATE_DELAY_1 = 0x30 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x120) = 0x002D0000;
+ /* RDLVL_GATE_DELAY_2 = 0x2D */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x130) = 0x0000002B;
+ /* RDLVL_GATE_DELAY_3 = 0x2B */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x42C) = 0x000A3004;
+ /* r_txdq_sft_0,r_rxdqs_sft_0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x430) = 0x000A2F04;
+ /* r_txdq_sft_1,r_rxdqs_sft_1 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x434) = 0x000A2C04;
+ /* r_txdq_sft_2,r_rxdqs_sft_2 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x438) = 0x000A2A04;
+ /* r_txdq_sft_3,r_rxdqs_sft_3 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00000103;
+ /* SWLVL_LOAD = 0x1 */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ vSWLVL_RESP_0 = *((volatile unsigned long *)0xFFF4A0D8) & 0x00FF0000;
+ /* SWLVL_RESP_0 check */
+
+ vSWLVL_RESP_1 = *((volatile unsigned long *)0xFFF4A0D8) & 0xFF000000;
+ /* SWLVL_RESP_1 check */
+
+ vSWLVL_RESP_2 = *((volatile unsigned long *)0xFFF4A0DC) & 0x0000FF00;
+ /* SWLVL_RESP_2 check */
+
+ vSWLVL_RESP_3 = *((volatile unsigned long *)0xFFF4A0DC) & 0x000000FF;
+ /* SWLVL_RESP_3 check */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x01000003;
+ /* SWLVL_EXIT = 0x1 */
+
+ while (1)
+ {
+ vSWLVL_OP_DONE = *((volatile unsigned long *)0xFFF4A0D8);
+ /* SWLVL_OP_DONE == 0x1 */
+ if((vSWLVL_OP_DONE & 0x00000001) == 0x00000001)
+ {
+ break;
+ }
+ }
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x070) = 0x00000000;
+ /* CS0 MRS DRAM MPR end) */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A0) = 0x00000000;
+ /* TDFI_RDLVL_DLL = 0x0 */
+ /* TDFI_RDLVL_LOAD = 0x0 */
+ /* TDFI_RDLVL_RESPLAT = 0x0 */
+ /* TDFI_RDLVL_EN = 0x0 */
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A8) = 0x00000000;
+ /* TDFI_RDLVL_RESP = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x1A4) = 0x00000000;
+ /* TDFI_RDLVL_RR = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0F4) = 0x00000000;
+ /* RDLVL_CS = 0x0 */
+
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0D4) = 0x00000000;
+ /* SW_LEVELING_MODE = 0x0 */
+ /* SWLVL_START = 0x0 */
+
+ vINT_STATUS = *((volatile unsigned long *)0xFFF4A0A0);
+ vUPDATE_ERROR_STATUS = *((volatile unsigned long *)0xFFF4A170);
+ *(volatile u32 *)((u32)DDR3C_BASE+0x0A4) = vINT_STATUS;
+
+ return 0;
+
+}
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/lowlevel_init.S u-boot/arch/arm/cpu/armv7/mb8ac0300/lowlevel_init.S
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/lowlevel_init.S 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/lowlevel_init.S 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,202 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb8ac0300/lowlevel_init.S
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+
+/*
+ * lowlevel_init
+ */
+.globl lowlevel_init
+lowlevel_init:
+ /* STEP1 : CPU1 Sleeped */
+ /*
+ * read MultiProcessor ID register(MPIDR)
+ */
+ mrc p15,0,r0,c0,c0,5
+ and r0, r0, #0x3 @ extract CPUID,bits
+ cmp r0, #1 @ 0x0 : processor is CPU0
+ @ 0x1 : processor is CPU1
+ bleq CA9_1_SLEEP @ CPU1 Sleeped
+
+ /* STEP2 : check PLL Locked */
+ ldr r0, =CRG_BASE @ 0xfff60000
+PLL_LOCKED_CHECK:
+ ldr r1, [r0, #CRG_PLLRDY]
+ and r1, r1, #0x7
+ cmp r1, #0x7 @ bit0:MAIN_CRG11 PLLRDY status
+ @ bit1:DMC_CRG11 PLLRDY status
+ @ bit2:GMAC_CRG11 PLLRDY status
+ @ 0 -> Unlocked.
+ @ 1 -> Locked.
+ bne PLL_LOCKED_CHECK
+
+ /* STEP3 : Initialize Core */
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK_0 @ 0x01008000
+
+ /* STEP4 : Initialize MEMC */
+ push {ip, lr}
+ bl init_memc @ Call external function
+ pop {ip, lr}
+
+ /* STEP5 : Initialize Data bahn */
+ push {ip, lr}
+ bl init_ddr3c @ Call external function
+ pop {ip, lr}
+
+ /* STEP6 : Initialize Peripheral Macro */
+ /*
+ * CRG11
+ * CRRRS : Deasserting Request for RRESETn
+ */
+ ldr r0, =CRG_BASE @ 0xfff60000
+ ldr r1, = 0x000000ff
+ str r1, [r0, #CRG_CRRRS]
+
+ /*
+ * CRG11 Frequency Setting
+ */
+ ldr r0, =CRG_BASE @ 0xfff60000
+
+ /* CLK0 1/1 (662.5MHz) */
+ ldr r1, =0x00000000
+ str r1, [r0, #CRG_CRDM0]
+
+ /* CLK1,2 1/2 (331.25MHz) */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRDM1]
+ str r1, [r0, #CRG_CRDM2]
+
+ /* CLK3 1/4 (165.625MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDM3]
+
+ /* CLK4,5,6 1/8 (82.8125MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDM4]
+ str r1, [r0, #CRG_CRDM5]
+ str r1, [r0, #CRG_CRDM6]
+
+ /* CLK7,8 1/4 (165.625MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDM7]
+ str r1, [r0, #CRG_CRDM8]
+
+ /* CLK9,A,B 1/2 (331.25MHz) */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRDM9]
+ str r1, [r0, #CRG_CRDMA]
+ str r1, [r0, #CRG_CRDMB]
+
+ /* CLKC 1/4 (165.625MHz) */
+ ldr r1, =0x00000003
+ str r1, [r0, #CRG_CRDMC]
+
+ /* CLKD 1/8 (82.8125MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDMD]
+
+ /* CLKE 1/16 (41.40625MHz) */
+ ldr r1, =0x0000000f
+ str r1, [r0, #CRG_CRDME]
+
+ /* CLKF 1/8 (82.8125MHz) */
+ ldr r1, =0x00000007
+ str r1, [r0, #CRG_CRDMF]
+
+ /* update clock divider mode */
+ ldr r1, =0x00000001
+ str r1, [r0, #CRG_CRCDC]
+
+ /* MAIN CRG11 PLL(662.5MHz) */
+ ldr r1, =0x00060235
+ str r1, [r0, #CRG_CRPLC]
+PLL_READY_CHECK:
+ ldr r1, [r0, #CRG_CRRDY]
+ and r1, r1, #0x1
+ cmp r1, #0x1
+ bne PLL_READY_CHECK
+
+CLOCK_DIVIDER_UPDATE_CHECK:
+ ldr r1, [r0, #CRG_CRCDC]
+ tst r1, #0x1 @ bit0:DCHREQ
+ @ 0 -> The divider mode are updated.
+ @ 1 -> The divider mode are not updated.
+ bne CLOCK_DIVIDER_UPDATE_CHECK
+
+ /* STEP7 : Initialize Memory System */
+ /*
+ * Invalidate L1/L2 dcache
+ */
+ push {ip, lr}
+ bl invalidate_dcache_all @ Call external function
+ pop {ip, lr}
+
+ mov pc, lr
+
+CA9_1_SLEEP:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK_1 @ 0x01018000
+
+ /*
+ * Invalidate L1/L2 dcache
+ */
+ push {ip, lr}
+ bl invalidate_dcache_all @ Call external function
+ pop {ip, lr}
+
+ ldr r0, =MRBC_BASE
+ ldr r1, =0x0
+ str r1, [r0, #MRBC_GPREG0]
+
+ /*
+ * Enable GICC irq
+ */
+ ldr r0, =GICC_BASE
+ ldr r1, =0xff
+ str r1, [r0, #GICC_PMR]
+ ldr r1, =0x1
+ str r1, [r0, #GICC_CTRL]
+
+ wfi @ sleep
+
+ /*
+ * read GICC_IAR
+ */
+ ldr r1, [r0, #GICC_IAR]
+
+ /*
+ * set EOI
+ */
+ str r1, [r0, #GICC_EOIR]
+ /*
+ * disable irq
+ */
+ ldr r1, =0x0
+ str r1, [r0, #GICC_PMR]
+ str r1, [r0, #GICC_CTRL]
+CA9_1_WAKEUP_CHECK:
+ ldr r0, =MRBC_BASE
+ ldr r1, [r0, #MRBC_GPREG0]
+ cmp r1, #0
+ beq CA9_1_WAKEUP_CHECK @ continue
+
+ mov pc, r1 @ wakeup
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/memc_init.S u-boot/arch/arm/cpu/armv7/mb8ac0300/memc_init.S
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/memc_init.S 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/memc_init.S 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,217 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb8ac0300/memc_init.S
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+
+/*
+ * init_memc : Initialization of the Registers of MEMC
+ */
+.globl init_memc
+init_memc:
+ /*
+ * Mode Register0-7
+ */
+ @ Bit1-0 WDT(Data Width)
+ @ 0:8bits(initial value)
+ @ 1:16bits
+ @ 2:32bits
+ @ 3:Reserved
+ @ Bit2 RBMON(Read Byte Mask ON)
+ @ 0:Disabled(initial value)
+ @ 1:Enabled
+ @ Bit3 WEOFF(WEX OFF) Write Enable OFF
+ @ 0:Disabled(initial value)
+ @ 1:Enabled
+ @ Bit4 NAND(NAND flash mode)
+ @ 0:NAND flash mode OFF(initial value)
+ @ 1:NAND flash mode ON
+ @ Bit5 PAGE(PAGE access mode) NOR flash page access mode
+ @ 0:NOR flash page access OFF(initial value)
+ @ 1:NOR flash page access ON
+ @ Bit6 RDY(READY MODE)
+ @ 0:READY mode OFF(initial value)
+ @ 1:READY mode ON
+
+ ldr r0, =MEMC_MODE0 @ MODE0 address
+ ldr r1, = 0x00000020 @ x8 NOR flash, pagemode
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE1 @ MODE1 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE2 @ MODE2 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE3 @ MODE3 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE4 @ MODE4 address
+ ldr r1, = 0x00000022 @ x32 NOR Flash, pagemode
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE5 @ MODE5 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE6 @ MODE6 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_MODE7 @ MODE7 address
+ ldr r1, = 0x00000000 @ N.C
+ str r1, [r0]
+
+ /*
+ * Timing Register0-7
+ */
+ @ Bit3-0 RACC (Read Access Cycle)
+ @ 0:1cycle
+ @ 1:2cycles
+ @ ...
+ @ 15:16cycle(initial value)
+ @ Bit7-4 RADC (Read Address Setup Cycle)
+ @ 0:1cycle
+ @ 1:2cycles
+ @ ...
+ @ 15:16cycle(initial value)
+ @ Bit11-8 FRADC (First Read Address Cycle)
+ @ 0:1cycle(initial value)
+ @ 1:2cycles
+ @ ...
+ @ 15:16cycles
+ @ Bit15-12 RIDLC (Read Idle Cycle)
+ @ 0:1cycle
+ @ 1:2cycles
+ @ ...
+ @ 15:16cycles(initial value)
+ @ Bit19-16 WACC (Write Access Cycle)
+ @ 0:Reserved
+ @ 1:Reserved
+ @ 2:3cycles
+ @ 3:4cycles
+ @ ...
+ @ 15:16cycles(initial value)
+ @ Bit23-20 WADC (Write Address Setup cycle)
+ @ 0:1cycle
+ @ ...
+ @ 5:6cycles(initial value)
+ @ ...
+ @ 14:15cycles
+ @ 15:Reserved
+ @ Bit27-24 WWEC (Write Enable Cycle)
+ @ 0:1cycle
+ @ ...
+ @ 5:6cycles(initial value)
+ @ ...
+ @ 14:15cycles
+ @ 15:Reserved
+ @ Bit31-28 WIDLC (Write Idle Cycle)
+ @ 0:1cycle
+ @ 1:2cycles
+ @ ...
+ @ 15:16cycles(initial value)
+
+ ldr r0, =MEMC_TIM0 @ TIM0 address
+ ldr r1, =0x144c100a @ x8 NOR flash
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM1 @ TIM1 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM2 @ TIM2 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM3 @ TIM3 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM4 @ TIM4 address
+ ldr r1, =0x144c100a @ x32 NOR Flash
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM5 @ TIM5 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM6 @ TIM6 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_TIM7 @ TIM7 address
+ ldr r1, =0x055ff00f @ N.C
+ str r1, [r0]
+
+ /*
+ * Area Register
+ */
+ @ Bit7-0 ADDR (Address)
+ @ These bits specify addresses
+ @ to set the corresponding MCSX region.
+ @ Bit23-16 MASK (address mask)
+ @ These bits set the mask value of the value set in ADDR.
+
+ ldr r0, =MEMC_AREA0 @ AREA0 address
+#ifdef CONFIG_MB8AC0300_XCS0_MODE
+/* XCS0 boot */
+ ldr r1, = 0x001f0000 @ x32 NOR Flash 32MByte 0x04000000
+#else
+/* XCS4 boot */
+ ldr r1, = 0x001f0040 @ x8 NOR flash 16MByte 0x04000000
+#endif
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA1 @ AREA1 address
+ ldr r1, = 0x000f0090 @ N.C 16M +0x09000000
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA2 @ AREA2 address
+ ldr r1, = 0x000f0020 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA3 @ AREA3 address
+ ldr r1, = 0x000f0030 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA4 @ AREA4 address
+#ifdef CONFIG_MB8AC0300_XCS0_MODE
+/* XCS0 boot */
+ ldr r1, = 0x001f0040 @ x8 NOR flash 16MByte 0x11000000
+#else
+/* XCS4 boot */
+ ldr r1, = 0x001f0000 @ x32 NOR Flash 32 MByte 0x10000000
+#endif
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA5 @ AREA5 address
+ ldr r1, = 0x000f0080 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA6 @ AREA6 address
+ ldr r1, = 0x000f0060 @ N.C
+ str r1, [r0]
+
+ ldr r0, =MEMC_AREA7 @ AREA7 address
+ ldr r1, = 0x00000070 @ N.C
+ str r1, [r0]
+
+ mov pc, lr
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/soc.c u-boot/arch/arm/cpu/armv7/mb8ac0300/soc.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/soc.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/soc.c 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,102 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb8ac0300/soc.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct pl310_regs *const pl310reg = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+/*
+ * Reset the cpu by setting software reset request bit
+ */
+void reset_cpu(ulong ignored)
+{
+ /*
+ * CRG11
+ */
+
+ /* CRRRS : Asserting Request for RRESETn */
+ writel(0x0, CRG_BASE + CRG_CRRRS);
+
+ /* CRRSC : Software reset mode */
+ writel(0x100, CRG_BASE + CRG_CRRSC);
+
+ /* CRSWR : Software reset request */
+ writel(0x1, CRG_BASE + CRG_CRSWR);
+
+ while (1);
+
+}
+
+#ifdef CONFIG_SYS_L2_PL310
+/*
+ * L2(PL310) dcache function
+ */
+void v7_outer_cache_enable(void)
+{
+ writel(0x1, &pl310reg->pl310_ctrl); /* reg1_control Register */
+}
+
+void v7_outer_cache_disable(void)
+{
+ writel(0x0, &pl310reg->pl310_ctrl); /* reg1_control Register */
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+ printf("CPU: MB8AC0300:Cortex-A9 Dual Core %d MHz\n",
+ (CONFIG_MB8AC0300_IOCLK/1000000));
+ return 0;
+}
+#endif
+
+#if CONFIG_DRIVER_FGMAC4
+int cpu_eth_init(bd_t *bis)
+{
+ return fgmac4_initialize(bis);
+}
+#endif
+
+#if defined(CONFIG_F_SDH30_SDHCI)
+extern
+int f_sdh30_sdhci_init(int regbase, int max_clk, int min_clk, int quirks);
+extern void f_sdh30_reset(void);
+
+int cpu_mmc_init(bd_t *bd)
+{
+ return f_sdh30_sdhci_init(F_SDH30_BASE, 0, 400000, 0);
+}
+
+void arch_preboot_os(void)
+{
+ f_sdh30_reset();
+}
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/timer.c u-boot/arch/arm/cpu/armv7/mb8ac0300/timer.c
--- original/u-boot-linaro-stable/arch/arm/cpu/armv7/mb8ac0300/timer.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/cpu/armv7/mb8ac0300/timer.c 2016-08-02 14:19:39.778733877 +0900
@@ -0,0 +1,133 @@
+/*
+ * u-boot/arch/arm/cpu/armv7/mb8ac0300/timer.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+
+/* Global Timer Register */
+#define TIMER_REG_LOAD (CONFIG_SYS_TIMERBASE + 0x00)
+#define TIMER_REG_VALUE (CONFIG_SYS_TIMERBASE + 0x04)
+#define TIMER_REG_CONTROL (CONFIG_SYS_TIMERBASE + 0x08)
+
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_FREQ (CONFIG_TIMER_CLK / 16) /* Peripheral clock is divided by 16 */
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastdec (gd->lastinc)
+
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, TIMER_FREQ);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= TIMER_FREQ;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+ writel(TIMER_LOAD_VAL, TIMER_REG_LOAD); /* decrement counter */
+
+ writel(0x86, TIMER_REG_CONTROL);
+ /* bit0: OnShot -> 0 = wrapping mode (default) */
+ /* bit1: TimerSize -> 1 = 32-bit counter. */
+ /* bit2-3: TimerPre -> 01 = 4 stages of prescale, clock is divided by 16 */
+ /* bit4: Reserved */
+ /* bit5: IntEnable -> 0 = Timer module Interrupt disabled */
+ /* bit6: TimerMode -> 0 = Timer module is in free-running mode (default) */
+ /* bit7: TimerEn -> 1 = Timer module enabled. */
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+ ulong now = readl(TIMER_REG_VALUE);
+
+ if (now <= lastdec) { /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (lastdec - now);
+ }
+ else {/* we have rollover of incrementer */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+ return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = readl(TIMER_REG_VALUE);
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return TIMER_FREQ;
+}
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb86s7x/hardware.h u-boot/arch/arm/include/asm/arch-mb86s7x/hardware.h
--- original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb86s7x/hardware.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/include/asm/arch-mb86s7x/hardware.h 2016-08-02 14:19:39.809733744 +0900
@@ -0,0 +1,93 @@
+/*
+ * u-boot/arch/arm/include/asm/arch-mb86s7x/hardware.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/* stack of lowlevel_init */
+/* Use SDRAM for stack since it is initialized before AP bootloader is running */
+#define LOW_LEVEL_SDRAM_STACK_0 (0x89000000) /* stack for CPU0 */
+#define LOW_LEVEL_SDRAM_STACK_1 (0x8a000000) /* Stack for CPU1 */
+
+/*
+ * Address of Registers
+ */
+
+/* MRBC (Multi-core Remap and Boot Controller) */
+#define MRBC_BASE (0x2A4C0000)
+
+#define MRBC_GPREG0 (0x30) /* offset address */
+
+/* GIC */
+#define GIC_ID_PHY_BASE 0x2C001000 /* Physical Distributor */
+#define GIC_IC_PHY_BASE 0x2C002000 /* Physical CPU interface */
+
+/* Distributor interface registers */
+#define GICD_CTL 0x0
+#define GICD_CTR 0x4
+#define GICD_SEC 0x80
+#define GICD_ENABLESET 0x100
+#define GICD_ENABLECLEAR 0x180
+#define GICD_PENDINGSET 0x200
+#define GICD_PENDINGCLEAR 0x280
+#define GICD_ACTIVESET 0x300
+#define GICD_ACTIVECLEAR 0x380
+#define GICD_PRI 0x400
+#define GICD_CPUS 0x800
+#define GICD_CONFIG 0xC00
+#define GICD_SW 0xF00
+#define GICD_CPENDSGIR 0xF10
+#define GICD_SPENDSGIR 0xF20
+
+/* Physical CPU Interface registers */
+#define GICC_CTL 0x0
+#define GICC_PRIMASK 0x4
+#define GICC_BP 0x8
+#define GICC_INTACK 0xC
+#define GICC_EOI 0x10
+#define GICC_RUNNINGPRI 0x14
+#define GICC_HIGHESTPEND 0x18
+#define GICC_DEACTIVATE 0x1000
+#define GICC_PRIODROP GICC_EOI
+
+/* FGMAC4 */
+#define FGMAC4_BASE (0x31400000)
+
+/* F_ATIKI */
+#define F_TAIKI_BASE (0x31600000)
+
+/* F_SDH30 */
+#define F_EMMC_BASE (0x300C0000)
+#define F_SDH30_BASE (0x36600000)
+
+/* mhu */
+#define MB86S7X_MHU_PHYS 0x2b1f0000
+#define MB86S7X_SHM_FROM_SCB 0x2e003000
+
+/* USB 2.0 Host controller LAP, only on mb86s73 */
+#define F_USB20HO_LAP_BASE 0x34200000
+#define F_USB20HO_LAP_EHCI_BASE (F_USB20HO_LAP_BASE + 0x40000)
+
+#define F_SPI_BASE (0x48000000)
+#define F_SPI_IP_BASE (0x30010000)
+#define F_SYSOC_SPI (0x37300000)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb8ac0300/ddr3c.h u-boot/arch/arm/include/asm/arch-mb8ac0300/ddr3c.h
--- original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb8ac0300/ddr3c.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/include/asm/arch-mb8ac0300/ddr3c.h 2016-08-02 14:19:39.809733744 +0900
@@ -0,0 +1,651 @@
+/*
+ * u-boot/arch/arm/include/asm/arch-mb8ac0300/ddr3c.h
+ *
+ * Copyright (C) 2010-2011 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef _DDR3C_H
+#define _DDR3C_H
+
+typedef volatile struct{
+ volatile u32 CTL000;
+ volatile u32 CTL001;
+ volatile u32 CTL002;
+ volatile u32 CTL003;
+ volatile u32 CTL004;
+ volatile u32 CTL005;
+ volatile u32 CTL006;
+ volatile u32 CTL007;
+ volatile u32 CTL008;
+ volatile u32 CTL009;
+ volatile u32 CTL010;
+ volatile u32 CTL011;
+ volatile u32 CTL012;
+ volatile u32 CTL013;
+ volatile u32 CTL014;
+ volatile u32 CTL015;
+ volatile u32 CTL016;
+ volatile u32 CTL017;
+ volatile u32 CTL018;
+ volatile u32 CTL019;
+ volatile u32 CTL020;
+ volatile u32 CTL021;
+ volatile u32 CTL022;
+ volatile u32 CTL023;
+ volatile u32 CTL024;
+ volatile u32 CTL025;
+ volatile u32 CTL026;
+ volatile u32 CTL027;
+ volatile u32 CTL028;
+ volatile u32 CTL029;
+ volatile u32 CTL030;
+ volatile u32 CTL031;
+ volatile u32 CTL032;
+ volatile u32 CTL033;
+ volatile u32 CTL034;
+ volatile u32 CTL035;
+ volatile u32 CTL036;
+ volatile u32 CTL037;
+ volatile u32 CTL038;
+ volatile u32 CTL039;
+ volatile u32 CTL040;
+ volatile u32 CTL041;
+ volatile u32 CTL042;
+ volatile u32 CTL043;
+ volatile u32 CTL044;
+ volatile u32 CTL045;
+ volatile u32 CTL046;
+ volatile u32 CTL047;
+ volatile u32 CTL048;
+ volatile u32 CTL049;
+ volatile u32 CTL050;
+ volatile u32 CTL051;
+ volatile u32 CTL052;
+ volatile u32 CTL053;
+ volatile u32 CTL054;
+ volatile u32 CTL055;
+ volatile u32 CTL056;
+ volatile u32 CTL057;
+ volatile u32 CTL058;
+ volatile u32 CTL059;
+ volatile u32 CTL060;
+ volatile u32 CTL061;
+ volatile u32 CTL062;
+ volatile u32 CTL063;
+ volatile u32 CTL064;
+ volatile u32 CTL065;
+ volatile u32 CTL066;
+ volatile u32 CTL067;
+ volatile u32 CTL068;
+ volatile u32 CTL069;
+ volatile u32 CTL070;
+ volatile u32 CTL071;
+ volatile u32 CTL072;
+ volatile u32 CTL073;
+ volatile u32 CTL074;
+ volatile u32 CTL075;
+ volatile u32 CTL076;
+ volatile u32 CTL077;
+ volatile u32 CTL078;
+ volatile u32 CTL079;
+ volatile u32 CTL080;
+ volatile u32 CTL081;
+ volatile u32 CTL082;
+ volatile u32 CTL083;
+ volatile u32 CTL084;
+ volatile u32 CTL085;
+ volatile u32 CTL086;
+ volatile u32 CTL087;
+ volatile u32 CTL088;
+ volatile u32 CTL089;
+ volatile u32 CTL090;
+ volatile u32 CTL091;
+ volatile u32 CTL092;
+ volatile u32 CTL093;
+ volatile u32 CTL094;
+ volatile u32 CTL095;
+ volatile u32 CTL096;
+ volatile u32 CTL097;
+ volatile u32 CTL098;
+ volatile u32 CTL099;
+ volatile u32 CTL100;
+ volatile u32 CTL101;
+ volatile u32 CTL102;
+ volatile u32 CTL103;
+ volatile u32 CTL104;
+ volatile u32 CTL105;
+ volatile u32 CTL106;
+ volatile u32 CTL107;
+ volatile u32 CTL108;
+ volatile u32 CTL109;
+ volatile u32 CTL110;
+ volatile u32 CTL111;
+ volatile u32 CTL112;
+ volatile u32 CTL113;
+ volatile u32 CTL114;
+} DATABAHN_type;
+
+#define DATABAHN ((DATABAHN_type *) DDR3C_BASE)
+
+/* CTL000 */
+#define DRAM_CLASS ((u32)((u32)0x6 << 8))
+#define START0 ((u32)((u32)0x0 << 0))
+#define START1 ((u32)((u32)0x1 << 0))
+
+/* CTL001 */
+#define MAX_CS_REG ((u32)((u32)0x0 << 16))
+#define MAX_COL_REG ((u32)((u32)0x0 << 8))
+#define MAX_ROW_REG ((u32)((u32)0x0 << 0))
+
+/* CTL002 */
+#define TINIT ((u32)((u32)0xF << 0))
+
+/* CTL003 */
+#define TRST_PWRON ((u32)((u32)0x50 << 0))
+
+/* CTL004 */
+#define CKE_INACTIVE ((u32)((u32)0xC8 << 0))
+
+/* CTL005 */
+#define TBST_INT_INTERVAL ((u32)((u32)0x4 << 24))
+#define WRLAT ((u32)((u32)0x5 << 16))
+#define CASLAT_LIN ((u32)((u32)0xA << 8))
+#define INITAREF ((u32)((u32)0x0 << 0))
+
+/* CTL006 */
+#define TRAS_MIN ((u32)((u32)0xF << 24))
+#define TRC ((u32)((u32)0x15 << 16))
+#define TRRD ((u32)((u32)0x4 << 8))
+#define TCCD ((u32)((u32)0x4 << 0))
+
+/* CTL007 */
+#define TMRD ((u32)((u32)0x6 << 24))
+#define TRTP ((u32)((u32)0x4 << 16))
+#define TRP ((u32)((u32)0x6 << 8))
+#define TWTR ((u32)((u32)0x4 << 0))
+
+/* CTL008 */
+#define TRAS_MAX ((u32)((u32)0x6DB0 << 8))
+#define TMOD ((u32)((u32)0xC << 0))
+
+/* CTL009 */
+#define AP ((u32)((u32)0x0 << 24))
+#define WRITEINTERP ((u32)((u32)0x0 << 16))
+#define TCKESR ((u32)((u32)0x4 << 8))
+#define TCKE ((u32)((u32)0x3 << 0))
+
+/* CTL010 */
+#define TWR_INT ((u32)((u32)0x6 << 24))
+#define TRCD_INT ((u32)((u32)0x6 << 16))
+#define TRAS_LOCKOUT ((u32)((u32)0x1 << 8))
+#define CONCURRENTAP ((u32)((u32)0x1 << 0))
+
+/* CTL011 */
+#define NO_CMD_INIT ((u32)((u32)0x0 << 24))
+#define TDLL ((u32)((u32)0x200 << 8))
+#define TDAL ((u32)((u32)0xC << 0))
+
+/* CTL012 */
+#define TCPD ((u32)((u32)0x0 << 16))
+#define TFAW ((u32)((u32)0x10 << 8))
+#define BSTLEN ((u32)((u32)0x3 << 0))
+
+/* CTL013 */
+#define ADDRESS_MIRRORING ((u32)((u32)0x0 << 16))
+#define REG_DIMM_ENABLE ((u32)((u32)0x0 << 8))
+#define TRP_AB ((u32)((u32)0x7 << 0))
+
+/* CTL014 */
+#define RDIMM_CTL_0_31_0 ((u32)((u32)0x24101065 << 0))
+
+/* CTL015 */
+#define RDIMM_CTL_0_63_32 ((u32)((u32)0x00001070 << 0))
+
+/* CTL016 */
+#define RDIMM_CW_HOLD_CKE_EN ((u32)((u32)0x0 << 24))
+#define RDIMM_CWW_REQ ((u32)((u32)0x0 << 16))
+#define RDIMM_CWW_MAP ((u32)((u32)0xFFF << 0))
+
+/* CTL017 */
+#define RDIMM_TSTAB ((u32)((u32)0x960 << 8))
+#define RDIMM_TMRD ((u32)((u32)0x8 << 0))
+
+/* CTL018 */
+#define TREF_ENABLE ((u32)((u32)0x1 << 24))
+#define AUTO_REFRESH_MODE ((u32)((u32)0x0 << 16))
+#define AREFRESH ((u32)((u32)0x0 << 8))
+#define REG_DIMM_PARITY_ERROR ((u32)((u32)0x0 << 0))
+
+/* CTL019 */
+#define TREF ((u32)((u32)0xC2D << 16))
+#define TRFC ((u32)((u32)0x78 << 0))
+
+/* CTL020 */
+#define POWER_DOWN ((u32)((u32)0x0 << 24))
+#define TREF_INTERVAL ((u32)((u32)0x78 << 0))
+
+/* CTL021 */
+#define TXPDLL ((u32)((u32)0xA << 16))
+#define TPDEX ((u32)((u32)0x3 << 0))
+
+/* CTL022 */
+#define TXSNR ((u32)((u32)0x7C << 16))
+#define TXSR ((u32)((u32)0x200 << 0))
+
+/* CTL023 */
+#define ENABLE_QUICK_SREFRESH ((u32)((u32)0x1 << 24))
+#define SREFRESH_EXIT_NO_REFRESH ((u32)((u32)0x0 << 16))
+#define PWRUP_SREFRESH_EXIT ((u32)((u32)0x0 << 8))
+#define SREFRESH ((u32)((u32)0x0 << 0))
+
+/* CTL024 */
+#define PWRDN_SHIFT_DELAY ((u32)((u32)0x0 << 8 ))
+#define CKE_DELAY ((u32)((u32)0x0 << 0))
+
+/* CTL025 */
+#define WRITE_MODEREG ((u32)((u32)0x0 << 0))
+
+/* CTL026 */
+#define MR0_DATA_0 ((u32)((u32)0x410 << 8))
+#define MRW_STATUS ((u32)((u32)0x0 << 0))
+
+/* CTL027 */
+#define MR2_DATA_0 ((u32)((u32)0x0 << 16))
+#define MR1_DATA_0 ((u32)((u32)0x9042 << 0))
+
+/* CTL028 */
+#define MR3_DATA_0 ((u32)((u32)0x0 << 16))
+#define MRSINGLE_DATA_0 ((u32)((u32)0x0 << 0))
+
+/* CTL029 */
+#define MR1_DATA_1 ((u32)((u32)0x9042 << 16 ))
+#define MR0_DATA_1 ((u32)((u32)0x410 << 0 ))
+
+/* CTL030 */
+#define MRSINGLE_DATA_1 ((u32)((u32)0x0 << 16))
+#define MR2_DATA_1 ((u32)((u32)0x0 << 0))
+
+/* CTL031 */
+#define ZQINIT ((u32)((u32)0x200 << 16))
+#define MR3_DATA_1 ((u32)((u32)0x0 << 0))
+
+/* CTL032 */
+#define ZQCS ((u32)((u32)0x40 << 16 ))
+#define ZQCL ((u32)((u32)0x100 << 0))
+
+/* CTL033 */
+#define ZQ_IN_PROGRESS ((u32)((u32)0x0 << 24 ))
+#define REFRESH_PER_ZQ ((u32)((u32)0x40 << 16))
+#define ZQ_ON_SREF_EXIT ((u32)((u32)0x2 << 8))
+#define ZQ_REQ ((u32)((u32)0x0 << 0))
+
+/* CTL034 */
+#define COLUMN_SIZE ((u32)((u32)0x2 << 24 ))
+#define ADDR_PINS ((u32)((u32)0x1 << 16 ))
+#define EIGHT_BANK_MODE ((u32)((u32)0x1 << 8 ))
+#define ZQCS_ROTATE ((u32)((u32)0x1 << 0 ))
+
+/* CTL035 */
+#define ADDR_CMP_EN ((u32)((u32)0x1 << 24 ))
+#define COMMAND_AGE_COUNT ((u32)((u32)0xFF << 16 ))
+#define AGE_COUNT ((u32)((u32)0xFF << 8 ))
+#define APREBIT ((u32)((u32)0xA << 0 ))
+
+/* CTL036 */
+#define RW_SAME_EN ((u32)((u32)0x1 << 24 ))
+#define PRIORITY_EN ((u32)((u32)0x1 << 16 ))
+#define PLACEMENT_EN ((u32)((u32)0x1 << 8 ))
+#define BANK_SPLIT_EN ((u32)((u32)0x1 << 0 ))
+
+/* CTL037 */
+#define CS_MAP ((u32)((u32)0x3 << 24 ))
+#define INHIBIT_DRAM_CMD ((u32)((u32)0x0 << 16 ))
+#define SWAP_PORT_RW_SAME_EN ((u32)((u32)0x1 << 8 ))
+#define SWAP_EN ((u32)((u32)0x1 << 0 ))
+
+/* CTL038 */
+#define Q_FULLENESS ((u32)((u32)0x0 << 24 ))
+#define FAST_WRITE ((u32)((u32)0x0 << 16 ))
+#define REDUCT ((u32)((u32)0x0 << 8 ))
+#define BURST_ON_FLY_BIT ((u32)((u32)0xC << 0 ))
+
+/* CTL039 */
+#define RESYNC_DLL_PER_AREF_EN ((u32)((u32)0x1 << 16 ))
+#define RESYNC_DLL ((u32)((u32)0x0 << 8 ))
+#define CONTROLLER_BUSY ((u32)((u32)0x0 << 0 ))
+
+/* CTL040 */
+#define INT_STATUS ((u32)((u32)0x0 << 0 ))
+
+/* CTL041 */
+#define INT_ACK ((u32)((u32)0x0 << 0 ))
+
+/* CTL042 */
+#define INT_MASK ((u32)((u32)0x20 << 0 ))
+
+/* CTL043 */
+#define OUT_OF_RANGE_ADDR ((u32)((u32)0x0 << 0 ))
+
+/* CTL044 */
+#define OUT_OF_RANGE_TYPE ((u32)((u32)0x0 << 16 ))
+#define OUT_OF_RANGE_LENGTH ((u32)((u32)0x0 << 8 ))
+#define OUT_OF_RANGE_ADDR_33_32 ((u32)((u32)0x0 << 0 ))
+
+/* CTL045 */
+#define OUT_OF_RANGE_SOURCE_ID ((u32)((u32)0x0 << 0 ))
+
+/* CTL046 */
+#define PORT_CMD_ERROR_ADDR ((u32)((u32)0x0 << 0 ))
+
+/* CTL047 */
+#define PORT_CMD_ERROR_TYPE ((u32)((u32)0x0 << 24 ))
+#define PORT_CMD_ERROR_ID ((u32)((u32)0x0 << 8 ))
+#define PORT_CMD_ERROR_ADDR_33_32 ((u32)((u32)0x0 << 0 ))
+
+/* CTL048 */
+#define ODT_WR_MAP_CS0 ((u32)((u32)0x1 << 24 ))
+#define ODT_RD_MAP_CS0 ((u32)((u32)0x2 << 16 ))
+#define PORT_DATA_ERROR_ID ((u32)((u32)0x0 << 0 ))
+
+/* CTL049 */
+#define ADD_ODT_CLK_W2R_SAMECS ((u32)((u32)0x0 << 24 ))
+#define ADD_ODT_CLK_R2W_SAMECS ((u32)((u32)0x1 << 16 ))
+#define OUT_WR_MAP_CS1 ((u32)((u32)0x2 << 8 ))
+#define OUT_RD_MAP_CS1 ((u32)((u32)0x1 << 0 ))
+
+/* CTL050 */
+#define R2W_DIFFCS_DLY ((u32)((u32)0x6 << 24 ))
+#define R2R_DIFFCS_DLY ((u32)((u32)0x1 << 16 ))
+#define ADD_ODT_CLK_SAMETYPE_DIFFCS ((u32)((u32)0x2 << 8 ))
+#define ADD_ODT_CLK_DIFFTYPE_DIFFCS ((u32)((u32)0x2 << 0 ))
+
+/* CTL051 */
+#define R2W_SAMECS_DLY ((u32)((u32)0x6 << 24 ))
+#define R2R_SAMECS_DLY ((u32)((u32)0x0 << 16 ))
+#define W2W_DIFFCS_DLY ((u32)((u32)0x1 << 8 ))
+#define W2R_DIFFCS_DLY ((u32)((u32)0x6 << 0 ))
+
+/* CTL052 */
+#define OCD_ADJUST_PUP_CS_0 ((u32)((u32)0x0 << 24 ))
+#define OCD_ADJUST_PDN_CS_0 ((u32)((u32)0x0 << 16 ))
+#define W2W_SAMECS_DLY ((u32)((u32)0x0 << 8 ))
+#define W2R_SAMECS_DLY ((u32)((u32)0x0 << 0 ))
+
+/* CTL053 */
+#define SWLVL_EXIT ((u32)((u32)0x0 << 24 ))
+#define SWLVL_START ((u32)((u32)0x0 << 16 ))
+#define SWLVL_LOAD ((u32)((u32)0x0 << 8 ))
+#define SWLVL_LEVELING_MODE ((u32)((u32)0x0 << 0 ))
+
+/* CTL054 */
+#define SWLVL_RESP_1 ((u32)((u32)0x0 << 24 ))
+#define SWLVL_RESP_0 ((u32)((u32)0x0 << 16 ))
+#define LVL_STATUS ((u32)((u32)0x0 << 8 ))
+#define SWLVL_OP_DONE ((u32)((u32)0x0 << 0 ))
+
+/* CTL055 */
+#define WRLVL_CS ((u32)((u32)0x0 << 24 ))
+#define WRLVL_REQ ((u32)((u32)0x0 << 16 ))
+#define SWLVL_RESP_3 ((u32)((u32)0x0 << 8 ))
+#define SWLVL_RESP_2 ((u32)((u32)0x0 << 0 ))
+
+/* CTL056 */
+#define WRLVL_EN ((u32)((u32)0x0 << 16 ))
+#define WLMRD ((u32)((u32)0x28 << 8 ))
+#define WLDQSEN ((u32)((u32)0x19 << 0 ))
+
+/* CTL057 */
+#define WRLVL_ERROR_STATUS ((u32)((u32)0x0 << 16 ))
+#define WRLVL_REFRESH_INTERVAL ((u32)((u32)0x0 << 0 ))
+
+/* CTL058 */
+#define WRLVL_DELAY_0 ((u32)((u32)0x1E << 8 ))
+#define WRLVL_REG_EN ((u32)((u32)0x0 << 0 ))
+
+/* CTL059 */
+#define WRLVL_DELAY_2 ((u32)((u32)0x1A << 16 ))
+#define WRLVL_DELAY_1 ((u32)((u32)0x1C << 0 ))
+
+/* CTL060 */
+#define RDLVL_GATE_REQ ((u32)((u32)0x0 << 24 ))
+#define RDLVL_REQ ((u32)((u32)0x0 << 16 ))
+#define WRLVL_DELAY_3 ((u32)((u32)0x17 << 0 ))
+
+/* CTL061 */
+#define RDLVL_REG_EN ((u32)((u32)0x0 << 24 ))
+#define RDLVL_BEGIN_DELAY_EN ((u32)((u32)0x0 << 16 ))
+#define RDLVL_EDGE ((u32)((u32)0x0 << 8 ))
+#define RDLVL_CS ((u32)((u32)0x0 << 0 ))
+
+/* CTL062 */
+#define RDLVL_BEGIN_DELAY_0 ((u32)((u32)0x0 << 8 ))
+#define RDLVL_GATE_REG_EN ((u32)((u32)0x0 << 0 ))
+
+/* CTL063 */
+#define RDLVL_MIDPOINT_DELAY_0 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_END_DELAY_0 ((u32)((u32)0x0 << 0 ))
+
+/* CTL064 */
+#define RDLVL_OFFSET_DIR_0 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_OFFSET_DELAY_0 ((u32)((u32)0x0 << 0 ))
+
+/* CTL065 */
+#define RDLVL_GATE_DELAY_0 ((u32)((u32)0x32 << 16 ))
+#define RDLVL_DELAY_0 ((u32)((u32)0x2323 << 0 ))
+
+/* CTL066 */
+#define RDLVL_END_DELAY_1 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_BEGIN_DLEAY_1 ((u32)((u32)0x0 << 0 ))
+
+/* CTL067 */
+#define RDLVL_OFFSET_DELAY_1 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_MIDPOINT_DELAY_1 ((u32)((u32)0x0 << 0 ))
+
+/* CTL068 */
+#define RDLVL_DELAY_1 ((u32)((u32)0x2323 << 8 ))
+#define RDLVL_OFFSET_DIR_1 ((u32)((u32)0x0 << 0 ))
+
+/* CTL069 */
+#define RDLVL_BEGIN_DELAY_2 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_GATE_DELAY_1 ((u32)((u32)0x30 << 0 ))
+
+/* CTL070 */
+#define RDLVL_MIDPOINT_DELAY_2 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_END_DELAY_2 ((u32)((u32)0x0 << 0 ))
+
+/* CTL071 */
+#define RDLVL_OFFSET_DIR_2 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_OFFSET_DELAY_2 ((u32)((u32)0x0 << 0 ))
+
+/* CTL072 */
+#define RDLVL_GATE_DELAY_2 ((u32)((u32)0x2D << 16 ))
+#define RDLVL_DELAY_2 ((u32)((u32)0x2323 << 0 ))
+
+/* CTL073 */
+#define RDLVL_END_DELAY_3 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_BEGIN_DELAY_3 ((u32)((u32)0x0 << 0 ))
+
+/* CTL074 */
+#define RDLVL_OFFSET_DELAY_3 ((u32)((u32)0x0 << 16 ))
+#define RDLVL_MIDPOINT_DELAY_3 ((u32)((u32)0x0 << 0 ))
+
+/* CTL075 */
+#define RDLVL_DELAY_3 ((u32)((u32)0x2323 << 8 ))
+#define RDLVL_OFFSET_DIR_3 ((u32)((u32)0x0 << 0 ))
+
+/* CTL076 */
+#define AXI0_EN_SIZE_LT_WIDTH_INSTR ((u32)((u32)0xFFFF << 16 ))
+#define RDLVL_GATE_DELAY_3 ((u32)((u32)0x2B << 0 ))
+
+/* CTL077 */
+#define AXI0_FIFO_TYPE_REG ((u32)((u32)0x0 << 16 ))
+
+/* CTL078 */
+#define AXI1_EN_SIZE_LT_WIDTH_INSTR ((u32)((u32)0xFFFF << 0 ))
+
+/* CTL079 */
+#define AXI2_EN_SIZE_LT_WIDTH_INSTR ((u32)((u32)0xFFFF << 8 ))
+#define AXI1_FIFO_TYPE_REG ((u32)((u32)0x0 << 0 ))
+
+/* CTL080 */
+#define AXI3_EN_SIZE_LT_WIDTH_INSTR ((u32)((u32)0xFFFF << 16 ))
+#define AXI2_FIFO_TYPE_REG ((u32)((u32)0x0 << 8 ))
+
+/* CTL081 */
+#define AXI3_FIFO_TYPE_REG ((u32)((u32)0x0 << 16 ))
+
+/* CTL082 */
+#define AXI0_PRIORITY0_RELATIVE_PRIORITY ((u32)((u32)0x4 << 24 ))
+#define WRR_PARAM_VALUE_ERR ((u32)((u32)0x0 << 16 ))
+#define WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING ((u32)((u32)0x0 << 8 ))
+#define WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL ((u32)((u32)0x0 << 0 ))
+
+/* CTL083 */
+#define AXI0_PORT_ORDERING ((u32)((u32)0x0 << 24 ))
+#define AXI0_PRIORITY3_RELATIVE_PRIORITY ((u32)((u32)0x4 << 16 ))
+#define AXI0_PRIORITY2_RELATIVE_PRIORITY ((u32)((u32)0x4 << 8 ))
+#define AXI0_PRIORITY1_RELATIVE_PRIORITY ((u32)((u32)0x4 << 0 ))
+
+/* CTL084 */
+#define AXI1_PRIORITY1_RELATIVE_PRIORITY ((u32)((u32)0x3 << 24 ))
+#define AXI1_PRIORITY0_RELATIVE_PRIORITY ((u32)((u32)0x3 << 16 ))
+#define AXI0_PRIORITY_RELAX ((u32)((u32)0x64 << 0 ))
+
+/* CTL085 */
+#define AXI1_PORT_ORDERING ((u32)((u32)0x1 << 16 ))
+#define AXI1_RPIORITY3_RELATIVE_PRIORITY ((u32)((u32)0x3 << 8 ))
+#define AXI1_RPIORITY2_RELATIVE_PRIORITY ((u32)((u32)0x3 << 0 ))
+
+/* CTL086 */
+#define AXI2_PRIORITY1_RELATIVE_PRIORITY ((u32)((u32)0x2 << 24 ))
+#define AXI2_PRIORITY0_RELATIVE_PRIORITY ((u32)((u32)0x2 << 16 ))
+#define AXI1_PRIORITY_RELAX ((u32)((u32)0x64 << 0 ))
+
+/* CTL087 */
+#define AXI2_PORT_ORDERING ((u32)((u32)0x2 << 16 ))
+#define AXI2_PRIORITY3_RELATIVE_PRIORITY ((u32)((u32)0x2 << 8 ))
+#define AXI2_PRIORITY2_RELATIVE_PRIORITY ((u32)((u32)0x2 << 0 ))
+
+/* CTL088 */
+#define AXI3_PRIORITY1_RELATIVE_PRIORITY ((u32)((u32)0x1 << 24 ))
+#define AXI3_PRIORITY0_RELATIVE_PRIORITY ((u32)((u32)0x1 << 16 ))
+#define AXI2_PRIORITY_RELAX ((u32)((u32)0x64 << 0 ))
+
+/* CTL089 */
+#define AXI3_PORT_ORDERING ((u32)((u32)0x3 << 16 ))
+#define AXI3_PRIORITY3_RELATIVE_PRIORITY ((u32)((u32)0x1 << 8 ))
+#define AXI3_PRIORITY2_RELATIVE_PRIORITY ((u32)((u32)0x1 << 0 ))
+
+/* CTL090 */
+#define MEM_RST_VALID ((u32)((u32)0x0 << 24 ))
+#define CKE_STATUS ((u32)((u32)0x0 << 16 ))
+#define AXI3_PRIORITY_RELAX ((u32)((u32)0x64 << 0 ))
+
+/* CTL091 */
+#define TDFI_PHY_WRLAT ((u32)((u32)0x0 << 24 ))
+#define DLL_RST_ADJ_DLY ((u32)((u32)0x0 << 16 ))
+#define DLL_RST_DELAY ((u32)((u32)0x0 << 0 ))
+
+/* CTL092 */
+#define DRAM_CLK_DISABLE ((u32)((u32)0x0 << 24 ))
+#define TDFI_RDDATA_EN ((u32)((u32)0x0 << 16 ))
+#define TDFI_PHY_RDLAT ((u32)((u32)0x7 << 8 ))
+#define UPDATE_ERROR_STATUS ((u32)((u32)0x0 << 0 ))
+
+/* CTL093 */
+#define TDFI_CTRLUPD_MAX ((u32)((u32)0x1E << 8 ))
+#define TDFI_CTRLUPD_MIN ((u32)((u32)0x1 << 0 ))
+
+/* CTL094 */
+#define TDFI_PHYUPD_TYPE1 ((u32)((u32)0x200 << 16 ))
+#define TDFI_PHYUPD_TYPE0 ((u32)((u32)0x200 << 0 ))
+
+/* CTL095 */
+#define TDFI_PHYUPD_TYPE3 ((u32)((u32)0x200 << 16 ))
+#define TDFI_PHYUPD_TYPE2 ((u32)((u32)0x200 << 0 ))
+
+/* CTL096 */
+#define TDFI_PHYUPD_RESP ((u32)((u32)0xC2D << 0 ))
+
+/* CTL097 */
+#define TDFI_CTRLUPD_INTERVAL ((u32)((u32)0x0 << 0 ))
+
+/* CTL098 */
+#define DFI_WRLVL_MAX_DELAY ((u32)((u32)0x8000 << 16 ))
+#define WRLAT_ADJ ((u32)((u32)0x5 << 8 ))
+#define RDLAT_ADJ ((u32)((u32)0x3 << 0 ))
+
+/* CTL099 */
+#define TDFI_WRLVL_RESPLAT ((u32)((u32)0x0 << 24 ))
+#define TDFI_WRLVL_LOAD ((u32)((u32)0x0 << 16 ))
+#define TDFI_WRLVL_DLL ((u32)((u32)0x0 << 8 ))
+#define TDFI_WRLVL_EN ((u32)((u32)0x0 << 0 ))
+
+/* CTL100 */
+#define TDFI_WRLVL_WW ((u32)((u32)0x0 << 0 ))
+
+/* CTL101 */
+#define TDFI_WRLVL_RESP ((u32)((u32)0x0 << 0 ))
+
+/* CTL102 */
+#define TDFI_WRLVL_MAX ((u32)((u32)0x0 << 0 ))
+
+/* CTL103 */
+#define RDLVL_GATE_MAX_DELAY ((u32)((u32)0x10 << 16 ))
+#define RDLVL_MAX_DELAY ((u32)((u32)0xFFFF << 0 ))
+
+/* CTL104 */
+#define TDFI_RDLVL_RESPLAT ((u32)((u32)0x0 << 24 ))
+#define TDFI_RDLVL_LOAD ((u32)((u32)0x0 << 16 ))
+#define TDFI_RDLVL_DLL ((u32)((u32)0x0 << 8 ))
+#define TDFI_RDLVL_EN ((u32)((u32)0x0 << 0 ))
+
+/* CTL105 */
+#define TDFI_RDLVL_RR ((u32)((u32)0x0 << 0 ))
+
+/* CTL106 */
+#define TDFI_RDLVL_RESP ((u32)((u32)0x0 << 0 ))
+
+/* CTL107 */
+#define RDLVL_RESP_MASK ((u32)((u32)0x0 << 0 ))
+
+/* CTL108 */
+#define RDLVL_GATE_RESP_MASK ((u32)((u32)0x0 << 0 ))
+
+/* CTL109 */
+#define RDLVL_GATE_PREAMBLE_CHECK_EN ((u32)((u32)0x0 << 16 ))
+#define RDLVL_GATE_EN ((u32)((u32)0x0 << 8 ))
+#define RDLVL_EN ((u32)((u32)0x0 << 0 ))
+
+/* CTL110 */
+#define TDFI_RDLVL_MAX ((u32)((u32)0x0 << 0 ))
+
+/* CTL111 */
+#define RDLVL_GATE_DQ_ZERO_COUNT ((u32)((u32)0x2 << 8 ))
+#define RDLVL_DQ_ZERO_COUNT ((u32)((u32)0x4 << 0 ))
+
+/* CTL112 */
+#define RDLVL_ERROR_STATUS ((u32)((u32)0x0 << 0 ))
+
+/* CTL113 */
+#define RDLVL_GATE_REFRESH_INTERVAL ((u32)((u32)0x0 << 16 ))
+#define RDLVL_REFRESH_INTERVAL ((u32)((u32)0x0 << 0 ))
+
+/* CTL114 */
+#define ODT_ALT_EN ((u32)((u32)0x1 << 0 ))
+
+
+#define OBSOLETE ((u32)((u32)0x0 << 0 ))
+
+#endif /* _DDR3C_H */
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb8ac0300/hardware.h u-boot/arch/arm/include/asm/arch-mb8ac0300/hardware.h
--- original/u-boot-linaro-stable/arch/arm/include/asm/arch-mb8ac0300/hardware.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/arch/arm/include/asm/arch-mb8ac0300/hardware.h 2016-08-02 14:19:39.809733744 +0900
@@ -0,0 +1,139 @@
+/*
+ * u-boot/arch/arm/include/asm/arch-mb8ac0300/hardware.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/* stack of lowlevel_init */
+#define LOW_LEVEL_SRAM_STACK_0 (0x01008000) /* Stack for CPU0 */
+#define LOW_LEVEL_SRAM_STACK_1 (0x01018000) /* Stack for CPU1 */
+
+
+/*
+ * Address of Registers
+ */
+
+/* MRBC (Multi-core Remap and Boot Controller) */
+#define MRBC_BASE (0xfff68000)
+
+#define MRBC_GPREG0 (0x30) /* offset address */
+
+/* CRG11 (Clock and Reset Generator) */
+#define CRG_BASE (0xfff60000)
+
+#define CRG_CRPLC (0x00) /* offset address */
+#define CRG_CRRDY (0x04) /* offset address */
+#define CRG_CRSTP (0x08) /* offset address */
+#define CRG_CRIMA (0x10) /* offset address */
+#define CRG_CRPIC (0x14) /* offset address */
+#define CRG_CRRSC (0x20) /* offset address */
+#define CRG_CRSWR (0x24) /* offset address */
+#define CRG_CRRRS (0x28) /* offset address */
+#define CRG_CRRSM (0x2c) /* offset address */
+#define CRG_CRCDC (0x30) /* offset address */
+#define CRG_CRDM0 (0x100) /* offset address */
+#define CRG_CRLP0 (0x104) /* offset address */
+#define CRG_CRDM1 (0x110) /* offset address */
+#define CRG_CRLP1 (0x114) /* offset address */
+#define CRG_CRDM2 (0x120) /* offset address */
+#define CRG_CRLP2 (0x124) /* offset address */
+#define CRG_CRDM3 (0x130) /* offset address */
+#define CRG_CRLP3 (0x134) /* offset address */
+#define CRG_CRDM4 (0x140) /* offset address */
+#define CRG_CRLP4 (0x144) /* offset address */
+#define CRG_CRDM5 (0x150) /* offset address */
+#define CRG_CRLP5 (0x154) /* offset address */
+#define CRG_CRDM6 (0x160) /* offset address */
+#define CRG_CRLP6 (0x164) /* offset address */
+#define CRG_CRDM7 (0x170) /* offset address */
+#define CRG_CRLP7 (0x174) /* offset address */
+#define CRG_CRDM8 (0x180) /* offset address */
+#define CRG_CRLP8 (0x184) /* offset address */
+#define CRG_CRDM9 (0x190) /* offset address */
+#define CRG_CRLP9 (0x194) /* offset address */
+#define CRG_CRDMA (0x1a0) /* offset address */
+#define CRG_CRLPA (0x1a4) /* offset address */
+#define CRG_CRDMB (0x1b0) /* offset address */
+#define CRG_CRLPB (0x1b4) /* offset address */
+#define CRG_CRDMC (0x1c0) /* offset address */
+#define CRG_CRLPC (0x1c4) /* offset address */
+#define CRG_CRDMD (0x1d0) /* offset address */
+#define CRG_CRLPD (0x1d4) /* offset address */
+#define CRG_CRDME (0x1e0) /* offset address */
+#define CRG_CRLPE (0x1e4) /* offset address */
+#define CRG_CRDMF (0x1f0) /* offset address */
+#define CRG_CRLPF (0x1f4) /* offset address */
+#define CRG_PLLRDY (0x200) /* offset address */
+
+/* MEMCS (MEMory Controller S) */
+#define MEMC_BASE (0xfff64000)
+
+#define MEMC_MODE0 (MEMC_BASE + 0x00)
+#define MEMC_MODE1 (MEMC_BASE + 0x04)
+#define MEMC_MODE2 (MEMC_BASE + 0x08)
+#define MEMC_MODE3 (MEMC_BASE + 0x0c)
+#define MEMC_MODE4 (MEMC_BASE + 0x10)
+#define MEMC_MODE5 (MEMC_BASE + 0x14)
+#define MEMC_MODE6 (MEMC_BASE + 0x18)
+#define MEMC_MODE7 (MEMC_BASE + 0x1c)
+#define MEMC_TIM0 (MEMC_BASE + 0x20)
+#define MEMC_TIM1 (MEMC_BASE + 0x24)
+#define MEMC_TIM2 (MEMC_BASE + 0x28)
+#define MEMC_TIM3 (MEMC_BASE + 0x2c)
+#define MEMC_TIM4 (MEMC_BASE + 0x30)
+#define MEMC_TIM5 (MEMC_BASE + 0x34)
+#define MEMC_TIM6 (MEMC_BASE + 0x38)
+#define MEMC_TIM7 (MEMC_BASE + 0x3c)
+#define MEMC_AREA0 (MEMC_BASE + 0x40)
+#define MEMC_AREA1 (MEMC_BASE + 0x44)
+#define MEMC_AREA2 (MEMC_BASE + 0x48)
+#define MEMC_AREA3 (MEMC_BASE + 0x4c)
+#define MEMC_AREA4 (MEMC_BASE + 0x50)
+#define MEMC_AREA5 (MEMC_BASE + 0x54)
+#define MEMC_AREA6 (MEMC_BASE + 0x58)
+#define MEMC_AREA7 (MEMC_BASE + 0x5c)
+
+/* DDR3C (DDR3 sdram Controller) */
+/* Databahn */
+#define DDR3C_BASE (0xfff4a000)
+
+#define GPU_BASE (0xf0100000)
+#define GPIO0_BASE (0xfff69000)
+#define GPIO1_BASE (0xfff6a000)
+
+/* Cortex-A9 MPCore Private Mem Region */
+#define PERIPHBASE_A9 (0xf8100000)
+
+/* GICC */
+#define GICC_BASE (PERIPHBASE_A9 + 0x100)
+
+#define GICC_CTRL (0x00) /* offset address */
+#define GICC_PMR (0x04) /* offset address */
+#define GICC_IAR (0x0c) /* offset address */
+#define GICC_EOIR (0x10) /* offset address */
+
+/* FGMAC4 */
+#define FGMAC4_BASE (0xf4000000)
+
+/* F_SDH30 */
+#define F_SDH30_BASE (0xf4002000)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/include/asm/mach-types.h u-boot/arch/arm/include/asm/mach-types.h
--- original/u-boot-linaro-stable/arch/arm/include/asm/mach-types.h 2016-08-02 12:12:08.697773402 +0900
+++ u-boot/arch/arm/include/asm/mach-types.h 2016-08-02 14:19:39.836733628 +0900
@@ -1107,6 +1107,8 @@
#define MACH_TYPE_OMAP5_SEVM 3777
#define MACH_TYPE_ARMADILLO_800EVA 3863
#define MACH_TYPE_KZM9G 4140
+#define MACH_TYPE_MB8AC0300 80300
+#define MACH_TYPE_MB86S70 86700
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -14248,6 +14250,30 @@
# define machine_is_kzm9g() (0)
#endif
+#ifdef CONFIG_MB8AC0300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB8AC0300
+# endif
+# define machine_is_mb8ac0300() (machine_arch_type == MACH_TYPE_MB8AC0300)
+#else
+# define machine_is_mb8ac0300() (0)
+#endif
+
+#ifdef CONFIG_MB86S70
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB86S70
+# endif
+# define machine_is_mb86s70() (machine_arch_type == MACH_TYPE_MB86S70)
+#else
+# define machine_is_mb86s70() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/include/asm/u-boot.h u-boot/arch/arm/include/asm/u-boot.h
--- original/u-boot-linaro-stable/arch/arm/include/asm/u-boot.h 2016-08-02 12:12:08.698773398 +0900
+++ u-boot/arch/arm/include/asm/u-boot.h 2016-08-02 14:19:39.838733620 +0900
@@ -45,8 +45,15 @@
unsigned long bi_ddr_freq; /* ddr frequency */
struct /* RAM configuration */
{
+#if defined(CONFIG_MB86S7X)
+ ulong start_high;
ulong start;
+ ulong size_high;
ulong size;
+#else
+ u64 start;
+ u64 size;
+#endif
} bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/lib/board.c u-boot/arch/arm/lib/board.c
--- original/u-boot-linaro-stable/arch/arm/lib/board.c 2016-08-02 12:12:08.699773395 +0900
+++ u-boot/arch/arm/lib/board.c 2016-08-02 14:19:39.838733620 +0900
@@ -151,7 +151,7 @@
print_size(gd->bd->bi_dram[i].size, "\n");
}
#else
- ulong size = 0;
+ unsigned long long size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
size += gd->bd->bi_dram[i].size;
@@ -464,9 +464,11 @@
/* NOTREACHED - relocate_code() does not return */
}
+#if !defined(CONFIG_SKIP_FLASH_PROBE)
#if !defined(CONFIG_SYS_NO_FLASH)
static char *failed = "*** failed ***\n";
#endif
+#endif
/*
************************************************************************
@@ -482,9 +484,11 @@
void board_init_r(gd_t *id, ulong dest_addr)
{
ulong malloc_start;
+#if !defined(CONFIG_SKIP_FLASH_PROBE)
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
+#endif
gd = id;
@@ -526,6 +530,7 @@
arch_early_init_r();
#endif
+#if !defined(CONFIG_SKIP_FLASH_PROBE)
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
@@ -551,7 +556,7 @@
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
- hang();
+ //hang();
}
#endif
@@ -559,6 +564,7 @@
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
+#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/lib/bootm.c u-boot/arch/arm/lib/bootm.c
--- original/u-boot-linaro-stable/arch/arm/lib/bootm.c 2016-08-02 12:12:08.699773395 +0900
+++ u-boot/arch/arm/lib/bootm.c 2016-08-02 14:19:39.839733615 +0900
@@ -76,6 +76,7 @@
}
#ifdef CONFIG_OF_LIBFDT
+#ifndef NO_FIX_MEMORY_NODE
static int fixup_memory_node(void *blob)
{
bd_t *bd = gd->bd;
@@ -84,13 +85,21 @@
u64 size[CONFIG_NR_DRAM_BANKS];
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+#if defined(CONFIG_MB86S7X)
+ start[bank] = bd->bi_dram[bank].start_high;
+ start[bank] = (start[bank] << 32) + bd->bi_dram[bank].start;
+ size[bank] = bd->bi_dram[bank].size_high;
+ size[bank] = (size[bank] << 32) + bd->bi_dram[bank].size;
+#else
start[bank] = bd->bi_dram[bank].start;
size[bank] = bd->bi_dram[bank].size;
+#endif
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
}
#endif
+#endif
static void announce_and_cleanup(void)
{
@@ -258,12 +267,11 @@
return ret;
fdt_chosen(*of_flat_tree, 1);
+#if !defined(NO_FIX_MEMORY_NODE)
fixup_memory_node(*of_flat_tree);
+#endif
fdt_fixup_ethernet(*of_flat_tree);
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
-#ifdef CONFIG_OF_BOARD_SETUP
- ft_board_setup(*of_flat_tree, gd->bd);
-#endif
#ifdef CONFIG_OF_BOARD_SETUP
/* Call the board-specific fixup routine */
diff -urNa -x .git original/u-boot-linaro-stable/arch/arm/lib/cache-cp15.c u-boot/arch/arm/lib/cache-cp15.c
--- original/u-boot-linaro-stable/arch/arm/lib/cache-cp15.c 2016-08-02 12:12:08.699773395 +0900
+++ u-boot/arch/arm/lib/cache-cp15.c 2016-08-02 14:19:39.839733615 +0900
@@ -60,6 +60,14 @@
for (i = bd->bi_dram[bank].start >> 20;
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
i++) {
+#ifdef CONFIG_DRIVER_OGMA
+ /* Keep OGMA DMA buf area uncacheable */
+ if ((i >= (CONFIG_DRIVER_OGMA_BUF_START >> 20)) &&
+ (i < (CONFIG_DRIVER_OGMA_BUF_END >> 20))) {
+ continue;
+ }
+#endif /* CONFIG_DRIVER_OGMA */
+
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
@@ -70,6 +78,7 @@
u32 *page_table = (u32 *)gd->tlb_addr;
int i;
u32 reg;
+ bd_t *bd = gd->bd;
arm_init_before_mmu();
/* Set up an identity-mapping for all 4GB, rw for everyone */
@@ -77,6 +86,9 @@
page_table[i] = i << 20 | (3 << 10) | 0x12;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (bd->bi_dram[i].start > (u64)CONFIG_SYS_SDRAM_BASE + gd->ram_size
+ || bd->bi_dram[i].start < (u64)CONFIG_SYS_SDRAM_BASE)
+ continue;
dram_bank_mmu_setup(i);
}
diff -urNa -x .git original/u-boot-linaro-stable/board/fujitsu/mb8ac0300eb/initlogo.rle u-boot/board/fujitsu/mb8ac0300eb/initlogo.rle
--- original/u-boot-linaro-stable/board/fujitsu/mb8ac0300eb/initlogo.rle 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/fujitsu/mb8ac0300eb/initlogo.rle 2016-08-02 14:19:40.074732604 +0900
@@ -0,0 +1,26 @@
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+ ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ ßÿ ÿÿ ’” „ yÎ ÿÿ –µ „ Æ YÎ ²” „ Æ ÿÿ Æ „ ¥ ÛÞ ¶µ „ U ÿÿ ¥ „ ]ï ÿÿ <ç „ ’” ºÖ ÷½ „ –µ ÿÿ 8Æ „ 4¥ ÛÞ U „ 8Æ ÿÿ yÎ „ u ÛÞ ¥ „ yÎ ÿÿ 8Æ „ 4¥ ÛÞ 4¥ „ 8Æ ÿÿ Æ „ U ÛÞ 4¥ „ YÎ ÿÿ u „ 8Æ yÎ šÖ ÿÿ 4¥ „ ¾÷ ÿÿ 8Æ „ ßÿ ÿÿ <ç „ U ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ yÎ „ ÷½ ÿÿ <ç yÎ Óœ „ 8Æ yÎ ÿÿ Óœ „ ÿÿ „ QŒ šÖ yÎ „ qŒ ÿÿ ¾÷ „ }ï ÿÿ ¥ „ ¥ ÿÿ yÎ „ –µ yÎ 4¥ „ 4¥ ÿÿ ž÷ „ qŒ ºÖ 8Æ „ Óœ ÿÿ ×½ „ šÖ ÿÿ „ ’” yÎ ÷½ 0„ „ ž÷ ÿÿ ’” „ 0„ yÎ YÎ ²” „ Yδ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ÛÞ ÿÿ ï{ nk ÛÞ ÿÿ ·µ nk šÖ nk ·µ ÿÿ ÛÞ nk ’”= ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ ×ý äè zþ ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ <ç ÿÿ „ yÎ ÿÿ –µ „ ]ï ÿÿ ûÞ „ –µ ÿÿ u „ ç ÿÿ ßÿ „ ²” ÿÿ qŒ „ ’” „ ºÖ ÿÿ šÖ „ Æ ÿÿ qŒ „ ¥ ÿÿ –µ „ <ç ÿÿ ]ï „ u ÿÿ ×½ „ ž÷ ÿÿ ÛÞ „ ×½ ÿÿ u „ <ç ÿÿ <ç „ –µ ÿÿ u „ ]ï ÿÿ <ç „ ¶µ ÿÿ u „ }ï ÿÿ ×½ „ <ç ÿÿ –µ „ qŒ ÿÿ yÎ „ ’” „ ’” ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ ×½ „ qŒ „ U ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ]ï „ u ÿÿ ¥ „ ¾÷ „ yÎ ÿÿ ¥ „ ¥ ÿÿ yÎ „ yÎ ÿÿ ßÿ „ ²” ÿÿ ÛÞ „ ×½ ÿÿ ’” „ 0„ ÿÿ 4¥ „ ’” „ ÷½ ÿÿ „ Óœ ÿÿ –µ „ ç ÿÿ ’” „ QŒ ÿÿ ûÞ „ ¶µ´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ’” ÛÞ ÿÿ ÛÞ nk ³” ÿÿ ÷½ ï{ ÛÞ ÿÿ ]ï nk rŒ ÿÿ ·µ nk Žk ’” ·µ ×½ ÛÞ ÿÿ nk ]ï ÿÿ ’” nk ·µ< ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ äè «ò ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ šÖ ÿÿ ]ï „ yÎ ÿÿ –µ „ ]ï ÿÿ ¾÷ „ u ÿÿ 4¥ „ ßÿ ÿÿ ²” „ QŒ ÿÿ ßÿ „ ×½ „ Æ ÿÿ YÎ „ šÖ ÿÿ óœ „ ²” ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ u „ ÿÿ }ï „ –µ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¥ „ ßÿ ÿÿ ¾÷ „ U ÿÿ u „ }ï ÿÿ yÎ „ šÖ ÿÿ óœ „ ¥ ÿÿ ×½ „ qŒ U „ ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ 4¥ „ 4¥ ²” „ ²” ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ûÞ „ ÷½ ÿÿ –µ „ }ï ¾÷ „ U ÿÿ ¥ „ ¥ ÿÿ yÎ „ yÎ ÿÿ ’” „ qŒ ÿÿ šÖ „ YÎ ÿÿ 4¥ „ ßÿ ÿÿ ’” „ ¶µ „ U ÿÿ „ Óœ ÿÿ 8Æ „ ÛÞ ÿÿ ’” „ QŒ ÿÿ ž÷ „ U´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ·µ ÿÿ nk ÿÿ ¯s nk ÿÿ ·µ nk ’” ÿÿ ·µ nk ·µ ÿÿ nk 1„< ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ ó äè fé –ý ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ QŒ „ ÷½ ÿÿ ºÖ „ qŒ „ yÎ ÿÿ –µ „ ]ï ÿÿ ]ï „ Æ ÿÿ ¶µ „ }ï ÿÿ QŒ „ óœ ÿÿ <ç „ ûÞ „ U ÿÿ YÎ „ šÖ ÿÿ u ²” U ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ßÿ ¾÷ ßÿ ÿÿ ç „ 8Æ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¥ „ ßÿ ÿÿ ¾÷ „ U ÿÿ u „ }ï ÿÿ ç „ ÷½ ÿÿ qŒ „ ¶µ ÿÿ 4¥ „ ¥ ÷½ „ ]ï ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ ’” „ ¶µ 4¥ „ ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ûÞ „ ÷½ ÿÿ –µ „ }ï ¾÷ „ Óœ „ QŒ ÿÿ ¥ „ ¥ ÿÿ yÎ „ yÎ ÿÿ 0„ „ ¥ ÿÿ šÖ „ YÎ ÿÿ 4¥ „ ßÿ ÿÿ „ YÎ ’” „ ²” ÿÿ „ Óœ ÿÿ 8Æ „ ûÞ ÿÿ ’” „ QŒ ÿÿ ž÷ „ U´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ·µ ÿÿ nk ÿÿ ·µ 4¥ nk ÿÿ ·µ nk ·µ ÿÿ óœ nk ÿÿ | nk< ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ Jò äè Šò 9þ ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ óœ „ U ÿÿ Æ „ óœ „ yÎ ÿÿ –µ „ ]ï ¾÷ ¶µ „ ÛÞ ÿÿ yÎ „ ×½ ßÿ yÎ „ ×½ ÿÿ šÖ „ ¾÷ qŒ „ ²” ÿÿ YÎ „ šÖ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¾÷ u „ ç ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¥ „ ßÿ ÿÿ ¾÷ „ U ÿÿ u „ }ï ÿÿ ¾÷ „ u ÿÿ ßÿ „ YÎ ÿÿ ’” „ ¶µ šÖ „ ºÖ ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ ßÿ „ YÎ ×½ „ }ï ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ûÞ „ ÷½ ÿÿ –µ „ }ï ¾÷ „ ÷½ „ <ç ¥ „ ¥ ÿÿ yÎ „ yÎ ÿÿ yÎ „ ÷½ ÿÿ šÖ „ YÎ ÿÿ 4¥ „ ßÿ ÿÿ ]ï „ ûÞ 4¥ „ ÿÿ „ Óœ ÿÿ –µ „ ¾÷ ÿÿ ’” „ QŒ ÿÿ ž÷ „ U´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ·µ ÿÿ nk ÿÿ ÛÞ nk ¶µ ·µ ¯s nk ÿÿ ·µ nk ·µ ÿÿ nk ÿÿ Óœ nk< ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ «ò äè «ò zþ ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ ¶µ „ ²” ÿÿ u „ –µ „ yÎ ÿÿ –µ „ ÷½ ÿÿ U „ ²” ¾÷ ÿÿ ÷½ „ QŒ ÿÿ ¥ „ 0„ ÿÿ YÎ „ šÖ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ’” „ Æ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¥ „ ßÿ ÿÿ ¾÷ „ U ÿÿ u „ ¥ 4¥ U ÿÿ QŒ „ Óœ ÿÿ <ç „ ÛÞ ÿÿ „ YÎ ç „ Æ ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ ]ï „ ûÞ yÎ „ ºÖ ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ûÞ „ ÷½ ÿÿ –µ „ }ï ¾÷ „ YÎ ²” „ Æ ¥ „ ¥ ÿÿ yÎ „ 4¥ ßÿ ÿÿ šÖ „ YÎ ÿÿ 4¥ „ ßÿ ÿÿ ºÖ „ ž÷ ×½ „ ]ï ÿÿ „ ²” <ç yÎ QŒ „ Óœ ÿÿ ’” „ QŒ ÿÿ ž÷ „ U´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ·µ ÿÿ nk ÿÿ ž÷ nk ’” ÿÿ | nk ÿÿ ·µ nk ·µ ÿÿ ’” nk ÿÿ nk< ÿÿ rô äè ÿÿ Uý ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô ÿÿ ×ý †é äè 9þ ÿÿ rô äè ÿÿ äè rô ÿÿ ûÞ „ YÎ „ ÿÿ óœ „ 8Æ „ yÎ ÿÿ –µ „ šÖ ÿÿ ÛÞ „ ÷½ ÿÿ U „ óœ ÿÿ ¶µ „ }ï ÿÿ YÎ „ šÖ ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ qŒ „ QŒ }ï ÿÿ 4¥ „ ¾÷ ÿÿ ßÿ „ 4¥ ÿÿ ¥ „ ßÿ ÿÿ ¾÷ „ U ÿÿ u „ 0„ ÿÿ óœ „ 0„ ÿÿ šÖ „ }ï ÿÿ ]ï „ ûÞ ¾÷ „ u ÿÿ U „ ž÷ ÿÿ ç „ ×½ ÿÿ ¶µ „ ßÿ ÿÿ ºÖ „ ž÷ ç „ Æ ÿÿ U „ ž÷ ÿÿ Óœ „ ÿÿ ûÞ „ ÷½ ÿÿ –µ „ }ï ¾÷ „ YÎ ×½ „ ¥ „ ¥ ÿÿ yÎ „ ¶µ ÿÿ šÖ „ YÎ ÿÿ 4¥ „ ßÿ ÿÿ Æ „ 0„ ÿÿ yÎ „ ºÖ ÿÿ „ ²” ¾÷ ÿÿ ’” „ QŒ ÿÿ ž÷ „ U´ ÿÿ nk | ÿÿ nk ·µ ÿÿ nk ·µ ÿÿ nk ÿÿ ·µ nk ·µ ÿÿ | nk ÿÿ ·µ nk ·µ ÿÿ ·µ nk ÷½ ÿÿ nk Žs< ÿÿ rô äè ÿÿ ô äè rô ÿÿ äè rô ÿÿ ìò äè rô ÿÿ rô äè †é ÿÿ äè rô
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\ ファイル末尾ã«æ”¹è¡ŒãŒã‚ã‚Šã¾ã›ã‚“
diff -urNa -x .git original/u-boot-linaro-stable/board/samsung/smdk5250/monitor.S u-boot/board/samsung/smdk5250/monitor.S
--- original/u-boot-linaro-stable/board/samsung/smdk5250/monitor.S 2016-08-02 13:33:42.657023496 +0900
+++ u-boot/board/samsung/smdk5250/monitor.S 2016-08-02 14:19:40.130732363 +0900
@@ -48,8 +48,18 @@
1: mrs lr, elr_hyp
mov pc, lr
-/* In monitor mode, set up HVBAR and SCR then return to caller in NS-SVC. */
+/*
+ * In monitor mode, fix errata, set up HVBAR and SCR then return to caller in
+ * NS-SVC.
+ */
2:
+ /* Fix up Exynos5250 errata */
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 1) @ 773022
+ orr r1, r1, #(1 << 25) @ 774769
+ mcr p15, 0, r1, c1, c0, 1
+ isb
+
mrc p15, 0, r1, c1, c1, 0 @ SCR
/*
* Set SCR.NS=1 (needed for setting HVBAR and also returning to NS state)
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s70/Makefile u-boot/board/socionext/mb86s70/Makefile
--- original/u-boot-linaro-stable/board/socionext/mb86s70/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s70/Makefile 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@....
+#
+# (C) Copyright 2008
+# Stelian Pop
+# Lead Tech Design
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mb86s70.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+include $(obj).depend
+
+#########################################################################
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s70/mb86s70.c u-boot/board/socionext/mb86s70/mb86s70.c
--- original/u-boot-linaro-stable/board/socionext/mb86s70/mb86s70.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s70/mb86s70.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,88 @@
+/*
+ * u-boot/board/fujitsu/mb86s70/mb86s70.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include "mhu.h"
+
+extern void lcd_ctrl_init(void *lcd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MB8AC0300;
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->flags = 0; /* check me */
+
+/* icache_enable(); */
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+#ifdef CONFIG_DRIVER_FGMAC4
+ /* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+ gd->ram_size = PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE;
+#else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MB86S7X_MHU
+void dram_init_banksize(void)
+{
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start_high = 0;
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size_high = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (get_memory_layout()) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[1].start = 0;
+ gd->bd->bi_dram[1].size = 0;
+ }
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard(void)
+{
+ printf("BOARD: Socionext MB86S70 EVB\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s71/Makefile u-boot/board/socionext/mb86s71/Makefile
--- original/u-boot-linaro-stable/board/socionext/mb86s71/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s71/Makefile 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2015 Socionext Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mb86s71.o
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+COBJS-y += flash.o
+#endif
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+include $(obj).depend
+
+#########################################################################
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s71/flash.c u-boot/board/socionext/mb86s71/flash.c
--- original/u-boot-linaro-stable/board/socionext/mb86s71/flash.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s71/flash.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,235 @@
+/*
+ * u-boot/board/fujistu/mb86s71/flash.c
+ *
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+
+static struct spi_flash *flash[2] = {0};
+int chip_select = 0;
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_chips[2];
+
+#define MAX_TABLE_SIZE CONFIG_SYS_MAX_FLASH_SECT / 8 + 1
+
+typedef struct {
+ uint32_t digest;
+ u8 protect_table[MAX_TABLE_SIZE];
+} protect_tb_t;
+
+protect_tb_t tb[2];
+
+int init_protect_table(flash_info_t *info, int cs)
+{
+ int len = MAX_TABLE_SIZE;
+ int ret;
+ int i;
+
+ chip_select = cs;
+ /* read the table */
+ ret = spi_flash_read(flash[0], CONFIG_PROTECTION_TB_OFFSET +
+ cs * flash[0]->sector_size, sizeof(protect_tb_t), &tb[cs]);
+ if (ret)
+ return ret;
+
+ /* check if the table is there */
+ if(crc32(0, tb[cs].protect_table, MAX_TABLE_SIZE) != tb[cs].digest) {
+ for (i = 0; i < info->sector_count; i++)
+ info->protect[i] = 0;
+ for (i = 0; i < len; i++)
+ tb[cs].protect_table[i] = 0;
+
+ return 0;
+ }
+
+ /* loop: read the corresponding bit for the sector and set status */
+ for (i = 0; i < info->sector_count; i++) {
+ info->protect[i]= (tb[cs].protect_table[i / 8] >> (i % 8)) & 0x1;
+ if (info->protect[i])
+ spi_write_lock_status(flash[cs], i * flash[cs]->sector_size, 1);
+ }
+
+ return 0;
+}
+
+int save_protect_table(flash_info_t *info)
+{
+ int ret;
+ int len = MAX_TABLE_SIZE;
+ int old_cs = chip_select;
+
+ tb[old_cs].digest = crc32(0, tb[old_cs].protect_table, len);
+
+ /* erase and rewrite the sector */
+ chip_select = 0;
+
+ ret = flash_erase(&flash_chips[0], CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs,
+ CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs);
+ if (ret)
+ goto out;
+
+ ret = write_buff(&flash_chips[0], (uchar *)&tb[old_cs],
+ CONFIG_PROTECTION_TB_OFFSET + CONFIG_SYS_FLASH_BASE +
+ old_cs * flash[old_cs]->sector_size, sizeof(protect_tb_t));
+out:
+ chip_select = old_cs;
+
+ return ret;
+}
+
+int update_protect_table(flash_info_t *info, long sector, int prot, int cs)
+{
+
+ /* find the bit to update */
+ u8 byte = tb[cs].protect_table[sector / 8];
+ u8 mask = (1 << (sector % 8)) & 0xff;
+
+ byte = (byte & (~mask)) | (prot << (sector % 8));
+
+ tb[cs].protect_table[sector / 8] = byte;
+
+ return 0;
+}
+
+unsigned long flash_init (void)
+{
+ int i;
+ u32 sys_flash_size = get_sys_flash_size();
+
+ for (i = 0; i < 2; i++) {
+ flash_chips[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ flash[0] = spi_flash_probe(0, 0, 12500000, 0);
+ if(flash[0]) {
+ flash_chips[0].flash_id = 0x00;
+ flash_chips[0].size = flash[0]->size;
+ if (flash_chips[0].size > sys_flash_size)
+ flash_chips[0].size = sys_flash_size;
+ flash_chips[0].sector_count = flash[0]->size / flash[0]->sector_size;
+ if (flash_chips[0].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ flash[1] = spi_flash_probe(0, 1, 12500000, 0);
+ if(flash[1]) {
+ flash_chips[1].flash_id = 0x01;
+ flash_chips[1].size = flash[1]->size;
+ if (flash_chips[1].size > sys_flash_size)
+ flash_chips[1].size = sys_flash_size;
+ flash_chips[1].sector_count = flash[1]->size / flash[1]->sector_size;
+ if (flash_chips[1].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[1].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+
+ for(i = 0; i < flash_chips[0].sector_count; i++) {
+ flash_chips[0].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[0]->sector_size;
+ }
+
+ for(i = 0; i < flash_chips[1].sector_count; i++) {
+ flash_chips[1].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[1]->sector_size;
+ }
+
+ init_protect_table(&flash_chips[0], 0);
+ init_protect_table(&flash_chips[1], 1);
+
+ /* using chip select 0 as default */
+ chip_select = 0;
+ memcpy(&flash_info[0], &flash_chips[0], sizeof(flash_info_t));
+
+ return flash_info[0].size;
+}
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ if(flash[chip_select])
+ printf("SPI Flash: %s\n", flash[chip_select]->name);
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 4) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int offset = s_first * flash[chip_select]->sector_size;
+ size_t size = (s_last - s_first + 1) * flash[chip_select]->sector_size;
+
+ return spi_flash_erase(flash[chip_select], offset, size);
+}
+
+int read_flash_buff (uchar *dest, ulong addr, ulong cnt)
+{
+ return spi_flash_read(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, dest);
+}
+
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ return spi_flash_write(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, src);
+}
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int ret;
+ int offset = sector * flash[0]->sector_size;
+
+ /* check for protect table sector, cannot protect it */
+ if (chip_select == 0) {
+ if(offset == CONFIG_PROTECTION_TB_OFFSET ||
+ offset == (CONFIG_PROTECTION_TB_OFFSET + flash[0]->sector_size)) {
+ printf("Error:The protection bitmap table cannot be protected.\n");
+ return -1;
+ }
+ }
+
+ ret = spi_write_lock_status(flash[chip_select], sector * flash[chip_select]->sector_size, prot);
+ if (!ret)
+ info->protect[sector] = prot;
+
+ ret = update_protect_table(info, sector, prot, chip_select);
+
+ return ret;
+}
+
+int flash_chip_select(int cs)
+{
+ if (!flash[cs])
+ return -1;
+
+ chip_select = cs;
+ memcpy(&flash_info[0], &flash_chips[cs], sizeof(flash_info_t));
+
+ return 0;
+}
+
+int get_chip_select(void)
+{
+ return chip_select;
+}
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s71/mb86s71.c u-boot/board/socionext/mb86s71/mb86s71.c
--- original/u-boot-linaro-stable/board/socionext/mb86s71/mb86s71.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s71/mb86s71.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,178 @@
+/*
+ * u-boot/board/fujitsu/mb86s71/mb86s71.c
+ *
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mhu.h"
+
+extern void lcd_ctrl_init(void *lcd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MB8AC0300;
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->flags = 0; /* check me */
+
+/* icache_enable(); */
+
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+#ifdef CONFIG_DRIVER_FGMAC4
+ /* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+ gd->ram_size = PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE;
+#else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MB86S7X_MHU
+void dram_init_banksize(void)
+{
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start_high = 0;
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size_high = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (get_memory_layout()) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard(void)
+{
+ printf("BOARD: Socionext MB86S71 EVB\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void fdt_status_update(void * blob, char * node_name, char * status)
+{
+ char * status_str = NULL;
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(blob, node_name);
+ status_str = (char *)fdt_getprop(blob, nodeoffset, "status", NULL);
+ if (status_str == NULL || !strcmp(status_str, "auto")) {
+ fdt_setprop_string(blob, nodeoffset, "status", status);
+ }
+
+ return;
+}
+
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ char * status_str = NULL;
+ char * bind_addr = NULL;
+ char * fb0_addr = NULL;
+ char * fb1_addr = NULL;
+
+ int nodeoffset;
+ int video_out_capability = mhu_check_video_out_capability();
+
+ nodeoffset = fdt_path_offset(blob, "/pcie1_x2len@0x33E00600");
+ status_str = (char *)fdt_getprop(blob, nodeoffset, "status", NULL);
+ if (status_str == NULL || !strcmp(status_str, "auto")) {
+ if(mhu_check_pcie_capability()) {
+ printf(" PCIe : Auto Port Bifurcation. status -> okay\n");
+ fdt_setprop_string(blob, nodeoffset, "status", "okay");
+ }
+ else {
+ printf(" PCIe : Auto Port Bifurcation. status -> disabled\n");
+ fdt_setprop_string(blob, nodeoffset, "status", "disabled");
+ }
+ }
+
+ /* Setup display switch */
+ /* mhu_check_video_out_capability() = 0 : HDMI */
+ /* = 1 : MIPI-DSI(default) */
+ if(video_out_capability) {
+ /* fdt_setprop_string() for MIPI-DSI */
+ fdt_status_update(blob, "/fdb.0/mipidsi@fb0" , "okay");
+ fdt_status_update(blob, "/fdb.0/hdmitx14@fb1" , "disabled");
+ fdt_status_update(blob, "/fdb.0/iris-dsi@fb0" , "okay");
+ fdt_status_update(blob, "/fdb.0/iris-hdmi@fb1" , "disabled");
+ fdt_status_update(blob, "/fdb.0/fdbdrm.0" , "okay");
+ fdt_status_update(blob, "/fdb.0/f_hdmi_audio_dai", "disabled");
+ fdt_status_update(blob, "/f_hdmi_codec" , "disabled");
+ fdt_status_update(blob, "/f_hdmi_audio" , "disabled");
+ fdt_status_update(blob, "/i2c1/sc16is750@48" , "okay");
+ fdt_status_update(blob, "/i2c1/sn65dsi84@2c" , "okay");
+ fdt_status_update(blob, "/gpio_backlight" , "okay");
+ fdt_status_update(blob, "/touch-wxga" , "okay");
+ } else {
+ /* fdt_setprop_string() for HDMI */
+ fdt_status_update(blob, "/fdb.0/mipidsi@fb0" , "disabled");
+ fdt_status_update(blob, "/fdb.0/hdmitx14@fb1" , "okay");
+ fdt_status_update(blob, "/fdb.0/iris-dsi@fb0" , "disabled");
+ fdt_status_update(blob, "/fdb.0/iris-hdmi@fb1" , "okay");
+ fdt_status_update(blob, "/fdb.0/fdbdrm.0" , "okay");
+ fdt_status_update(blob, "/fdb.0/f_hdmi_audio_dai", "okay");
+ fdt_status_update(blob, "/f_hdmi_codec" , "okay");
+ fdt_status_update(blob, "/f_hdmi_audio" , "okay");
+ fdt_status_update(blob, "/i2c1/sc16is750@48" , "disabled");
+ fdt_status_update(blob, "/i2c1/sn65dsi84@2c" , "disabled");
+ fdt_status_update(blob, "/gpio_backlight" , "disabled");
+ fdt_status_update(blob, "/touch-wxga" , "disabled");
+ }
+
+ nodeoffset = fdt_path_offset(blob, "/fdb.0/fdbdrm.0");
+ bind_addr = (char *)fdt_getprop(blob, nodeoffset, "bind", NULL);
+ if (bind_addr != NULL || !bind_addr[3]) {
+ fb0_addr = (char *)fdt_getprop(blob, nodeoffset, "fb0_addr", NULL);
+ fb1_addr = (char *)fdt_getprop(blob, nodeoffset, "fb1_addr", NULL);
+
+ bind_addr[3] = video_out_capability ? fb0_addr[3] : fb1_addr[3];
+ if(video_out_capability) {
+ printf(" Video : Auto Port Selection. Selected MIPI-DSI Type.\n");
+ } else {
+ printf(" Video : Auto Port Selection. Selected HDMI Type.\n");
+ }
+ }
+}
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s72/Makefile u-boot/board/socionext/mb86s72/Makefile
--- original/u-boot-linaro-stable/board/socionext/mb86s72/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s72/Makefile 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@....
+#
+# (C) Copyright 2008
+# Stelian Pop
+# Lead Tech Design
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mb86s72.o
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+COBJS-y += flash.o
+#endif
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+include $(obj).depend
+
+#########################################################################
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s72/flash.c u-boot/board/socionext/mb86s72/flash.c
--- original/u-boot-linaro-stable/board/socionext/mb86s72/flash.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s72/flash.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,236 @@
+/*
+ * u-boot/board/fujistu/mb86s72/flash.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+
+static struct spi_flash *flash[2] = {0};
+int chip_select = 0;
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_chips[2];
+
+#define MAX_TABLE_SIZE CONFIG_SYS_MAX_FLASH_SECT / 8 + 1
+
+typedef struct {
+ uint32_t digest;
+ u8 protect_table[MAX_TABLE_SIZE];
+} protect_tb_t;
+
+protect_tb_t tb[2];
+
+int init_protect_table(flash_info_t *info, int cs)
+{
+ int len = MAX_TABLE_SIZE;
+ int ret;
+ int i;
+
+ chip_select = cs;
+ /* read the table */
+ ret = spi_flash_read(flash[0], CONFIG_PROTECTION_TB_OFFSET +
+ cs * flash[0]->sector_size, sizeof(protect_tb_t), &tb[cs]);
+ if (ret)
+ return ret;
+
+ /* check if the table is there */
+ if(crc32(0, tb[cs].protect_table, MAX_TABLE_SIZE) != tb[cs].digest) {
+ for (i = 0; i < info->sector_count; i++)
+ info->protect[i] = 0;
+ for (i = 0; i < len; i++)
+ tb[cs].protect_table[i] = 0;
+
+ return 0;
+ }
+
+ /* loop: read the corresponding bit for the sector and set status */
+ for (i = 0; i < info->sector_count; i++) {
+ info->protect[i]= (tb[cs].protect_table[i / 8] >> (i % 8)) & 0x1;
+ if (info->protect[i])
+ spi_write_lock_status(flash[cs], i * flash[cs]->sector_size, 1);
+ }
+
+ return 0;
+}
+
+int save_protect_table(flash_info_t *info)
+{
+ int ret;
+ int len = MAX_TABLE_SIZE;
+ int old_cs = chip_select;
+
+ tb[old_cs].digest = crc32(0, tb[old_cs].protect_table, len);
+
+ /* erase and rewrite the sector */
+ chip_select = 0;
+
+ ret = flash_erase(&flash_chips[0], CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs,
+ CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs);
+ if (ret)
+ goto out;
+
+ ret = write_buff(&flash_chips[0], (uchar *)&tb[old_cs],
+ CONFIG_PROTECTION_TB_OFFSET + CONFIG_SYS_FLASH_BASE +
+ old_cs * flash[old_cs]->sector_size, sizeof(protect_tb_t));
+out:
+ chip_select = old_cs;
+
+ return ret;
+}
+
+int update_protect_table(flash_info_t *info, long sector, int prot, int cs)
+{
+
+ /* find the bit to update */
+ u8 byte = tb[cs].protect_table[sector / 8];
+ u8 mask = (1 << (sector % 8)) & 0xff;
+
+ byte = (byte & (~mask)) | (prot << (sector % 8));
+
+ tb[cs].protect_table[sector / 8] = byte;
+
+ return 0;
+}
+
+unsigned long flash_init (void)
+{
+ int i;
+ u32 sys_flash_size = get_sys_flash_size();
+
+ for (i = 0; i < 2; i++) {
+ flash_chips[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ flash[0] = spi_flash_probe(0, 0, 12500000, 0);
+
+ if(flash[0]) {
+ flash_chips[0].flash_id = 0x00;
+ flash_chips[0].size = flash[0]->size;
+ if (flash_chips[0].size > sys_flash_size)
+ flash_chips[0].size = sys_flash_size;
+ flash_chips[0].sector_count = flash[0]->size / flash[0]->sector_size;
+ if (flash_chips[0].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ flash[1] = spi_flash_probe(0, 1, 12500000, 0);
+ if(flash[1]) {
+ flash_chips[1].flash_id = 0x01;
+ flash_chips[1].size = flash[1]->size;
+ if (flash_chips[1].size > sys_flash_size)
+ flash_chips[1].size = sys_flash_size;
+ flash_chips[1].sector_count = flash[1]->size / flash[1]->sector_size;
+ if (flash_chips[1].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[1].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+
+ for(i = 0; i < flash_chips[0].sector_count; i++) {
+ flash_chips[0].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[0]->sector_size;
+ }
+
+ for(i = 0; i < flash_chips[1].sector_count; i++) {
+ flash_chips[1].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[1]->sector_size;
+ }
+
+ init_protect_table(&flash_chips[0], 0);
+ init_protect_table(&flash_chips[1], 1);
+
+ /* using chip select 0 as default */
+ chip_select = 0;
+ memcpy(&flash_info[0], &flash_chips[0], sizeof(flash_info_t));
+
+ return flash_info[0].size;
+}
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ if(flash[chip_select])
+ printf("SPI Flash: %s\n", flash[chip_select]->name);
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 4) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int offset = s_first * flash[chip_select]->sector_size;
+ size_t size = (s_last - s_first + 1) * flash[chip_select]->sector_size;
+
+ return spi_flash_erase(flash[chip_select], offset, size);
+}
+
+int read_flash_buff (uchar *dest, ulong addr, ulong cnt)
+{
+ return spi_flash_read(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, dest);
+}
+
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ return spi_flash_write(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, src);
+}
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int ret;
+ int offset = sector * flash[0]->sector_size;
+
+ /* check for protect table sector, cannot protect it */
+ if (chip_select == 0) {
+ if(offset == CONFIG_PROTECTION_TB_OFFSET ||
+ offset == (CONFIG_PROTECTION_TB_OFFSET + flash[0]->sector_size)) {
+ printf("Error:The protection bitmap table cannot be protected.\n");
+ return -1;
+ }
+ }
+
+ ret = spi_write_lock_status(flash[chip_select], sector * flash[chip_select]->sector_size, prot);
+ if (!ret)
+ info->protect[sector] = prot;
+
+ ret = update_protect_table(info, sector, prot, chip_select);
+
+ return ret;
+}
+
+int flash_chip_select(int cs)
+{
+ if (!flash[cs])
+ return -1;
+
+ chip_select = cs;
+ memcpy(&flash_info[0], &flash_chips[cs], sizeof(flash_info_t));
+
+ return 0;
+}
+
+int get_chip_select(void)
+{
+ return chip_select;
+}
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s72/mb86s72.c u-boot/board/socionext/mb86s72/mb86s72.c
--- original/u-boot-linaro-stable/board/socionext/mb86s72/mb86s72.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s72/mb86s72.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,111 @@
+/*
+ * u-boot/board/fujitsu/mb86s72/mb86s72.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mhu.h"
+
+extern void lcd_ctrl_init(void *lcd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MB8AC0300;
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->flags = 0; /* check me */
+
+/* icache_enable(); */
+
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+#ifdef CONFIG_DRIVER_FGMAC4
+ /* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+ gd->ram_size = PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE;
+#else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MB86S7X_MHU
+void dram_init_banksize(void)
+{
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start_high = 0;
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size_high = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (get_memory_layout()) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard(void)
+{
+ printf("BOARD: Socionext MB86S72 EVB\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ char * status_str = NULL;
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(blob, "/pcie1_x2len@0x33E00600");
+ status_str = (char *)fdt_getprop(blob, nodeoffset, "status", NULL);
+ if (status_str == NULL || !strcmp(status_str, "auto")) {
+ if(mhu_check_pcie_capability()) {
+ printf(" PCIe : Auto Port Bifurcation. status -> okay\n");
+ fdt_setprop_string(blob, nodeoffset, "status", "okay");
+ }
+ else {
+ fdt_setprop_string(blob, nodeoffset, "status", "disabled");
+ printf(" PCIe : Auto Port Bifurcation. status -> disabled\n");
+ }
+ }
+}
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s73/Makefile u-boot/board/socionext/mb86s73/Makefile
--- original/u-boot-linaro-stable/board/socionext/mb86s73/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s73/Makefile 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@....
+#
+# (C) Copyright 2008
+# Stelian Pop
+# Lead Tech Design
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mb86s73.o
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+COBJS-y += flash.o
+#endif
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+include $(obj).depend
+
+#########################################################################
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s73/flash.c u-boot/board/socionext/mb86s73/flash.c
--- original/u-boot-linaro-stable/board/socionext/mb86s73/flash.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s73/flash.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,239 @@
+/*
+ * u-boot/board/fujistu/mb86s73/flash.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+
+static struct spi_flash *flash[2] = {0};
+int chip_select = 0;
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_chips[2];
+
+#define MAX_TABLE_SIZE CONFIG_SYS_MAX_FLASH_SECT / 8 + 1
+
+typedef struct {
+ uint32_t digest;
+ u8 protect_table[MAX_TABLE_SIZE];
+} protect_tb_t;
+
+protect_tb_t tb[2];
+
+int init_protect_table(flash_info_t *info, int cs)
+{
+ int len = MAX_TABLE_SIZE;
+ int ret;
+ int i;
+
+ chip_select = cs;
+ /* read the table */
+ ret = spi_flash_read(flash[0], CONFIG_PROTECTION_TB_OFFSET +
+ cs * flash[0]->sector_size, sizeof(protect_tb_t), &tb[cs]);
+ if (ret)
+ return ret;
+
+ /* check if the table is there */
+ if(crc32(0, tb[cs].protect_table, MAX_TABLE_SIZE) != tb[cs].digest) {
+ for (i = 0; i < info->sector_count; i++)
+ info->protect[i] = 0;
+ for (i = 0; i < len; i++)
+ tb[cs].protect_table[i] = 0;
+
+ return 0;
+ }
+
+ /* loop: read the corresponding bit for the sector and set status */
+ for (i = 0; i < info->sector_count; i++) {
+ info->protect[i]= (tb[cs].protect_table[i / 8] >> (i % 8)) & 0x1;
+ if (info->protect[i])
+ spi_write_lock_status(flash[cs], i * flash[cs]->sector_size, 1);
+ }
+
+ return 0;
+}
+
+int save_protect_table(flash_info_t *info)
+{
+ int ret;
+ int len = MAX_TABLE_SIZE;
+ int old_cs = chip_select;
+
+ tb[old_cs].digest = crc32(0, tb[old_cs].protect_table, len);
+
+ /* erase and rewrite the sector */
+ chip_select = 0;
+
+ ret = flash_erase(&flash_chips[0], CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs,
+ CONFIG_PROTECTION_TB_OFFSET / flash[chip_select]->sector_size + old_cs);
+ if (ret)
+ goto out;
+
+ ret = write_buff(&flash_chips[0], (uchar *)&tb[old_cs],
+ CONFIG_PROTECTION_TB_OFFSET + CONFIG_SYS_FLASH_BASE +
+ old_cs * flash[old_cs]->sector_size, sizeof(protect_tb_t));
+out:
+ chip_select = old_cs;
+
+ return ret;
+}
+
+int update_protect_table(flash_info_t *info, long sector, int prot, int cs)
+{
+
+ /* find the bit to update */
+ u8 byte = tb[cs].protect_table[sector / 8];
+ u8 mask = (1 << (sector % 8)) & 0xff;
+
+ byte = (byte & (~mask)) | (prot << (sector % 8));
+
+ tb[cs].protect_table[sector / 8] = byte;
+
+ return 0;
+}
+
+unsigned long flash_init (void)
+{
+ int i;
+ u32 sys_flash_size = get_sys_flash_size();
+
+ for (i = 0; i < 2; i++) {
+ flash_chips[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ flash[0] = spi_flash_probe(0, 0, 12500000, 0);
+
+ if(flash[0]) {
+ flash_chips[0].flash_id = 0x00;
+ flash_chips[0].size = flash[0]->size;
+ if (flash_chips[0].size > sys_flash_size)
+ flash_chips[0].size = sys_flash_size;
+ flash_chips[0].sector_count = flash[0]->size / flash[0]->sector_size;
+ if (flash_chips[0].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ flash[1] = spi_flash_probe(0, 1, 12500000, 0);
+ if(flash[1]) {
+ flash_chips[1].flash_id = 0x01;
+ flash_chips[1].size = flash[1]->size;
+ if (flash_chips[1].size > sys_flash_size)
+ flash_chips[1].size = sys_flash_size;
+ flash_chips[1].sector_count = flash[1]->size / flash[1]->sector_size;
+ if (flash_chips[1].sector_count > CONFIG_SYS_MAX_FLASH_SECT)
+ flash_chips[1].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ if(flash[0] == 0 && flash[1] == 0) {
+ return 0;
+ }
+
+ for(i = 0; i < flash_chips[0].sector_count; i++) {
+ flash_chips[0].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[0]->sector_size;
+ }
+
+ for(i = 0; i < flash_chips[1].sector_count; i++) {
+ flash_chips[1].start[i] = CONFIG_SYS_FLASH_BASE + i * flash[1]->sector_size;
+ }
+
+ init_protect_table(&flash_chips[0], 0);
+ init_protect_table(&flash_chips[1], 1);
+
+ /* using chip select 0 as default */
+ chip_select = 0;
+ memcpy(&flash_info[0], &flash_chips[0], sizeof(flash_info_t));
+
+ return flash_info[0].size;
+}
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ if(flash[chip_select])
+ printf("SPI Flash: %s\n", flash[chip_select]->name);
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 4) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int offset = s_first * flash[chip_select]->sector_size;
+ size_t size = (s_last - s_first + 1) * flash[chip_select]->sector_size;
+
+ return spi_flash_erase(flash[chip_select], offset, size);
+}
+
+int read_flash_buff (uchar *dest, ulong addr, ulong cnt)
+{
+ return spi_flash_read(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, dest);
+}
+
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ return spi_flash_write(flash[chip_select], addr - CONFIG_SYS_FLASH_BASE, cnt, src);
+}
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int ret;
+ int offset = sector * flash[0]->sector_size;
+
+ /* check for protect table sector, cannot protect it */
+ if (chip_select == 0) {
+ if(offset == CONFIG_PROTECTION_TB_OFFSET ||
+ offset == (CONFIG_PROTECTION_TB_OFFSET + flash[0]->sector_size)) {
+ printf("Error:The protection bitmap table cannot be protected.\n");
+ return -1;
+ }
+ }
+
+ ret = spi_write_lock_status(flash[chip_select], sector * flash[chip_select]->sector_size, prot);
+ if (!ret)
+ info->protect[sector] = prot;
+
+ ret = update_protect_table(info, sector, prot, chip_select);
+
+ return ret;
+}
+
+int flash_chip_select(int cs)
+{
+ if (!flash[cs])
+ return -1;
+
+ chip_select = cs;
+ memcpy(&flash_info[0], &flash_chips[cs], sizeof(flash_info_t));
+
+ return 0;
+}
+
+int get_chip_select(void)
+{
+ return chip_select;
+}
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb86s73/mb86s73.c u-boot/board/socionext/mb86s73/mb86s73.c
--- original/u-boot-linaro-stable/board/socionext/mb86s73/mb86s73.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb86s73/mb86s73.c 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,87 @@
+/*
+ * u-boot/board/fujitsu/mb86s73/mb86s73.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+#include "mhu.h"
+
+extern void lcd_ctrl_init(void *lcd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MB8AC0300;
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->flags = 0; /* check me */
+
+/* icache_enable(); */
+
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+#ifdef CONFIG_DRIVER_FGMAC4
+ /* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+ gd->ram_size = PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE;
+#else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MB86S7X_MHU
+void dram_init_banksize(void)
+{
+ int i;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start_high = 0;
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size_high = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (get_memory_layout()) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard(void)
+{
+ printf("BOARD: Socionext MB86S73 EVB\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/Makefile u-boot/board/socionext/mb8ac0300eb/Makefile
--- original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb8ac0300eb/Makefile 2016-08-02 14:19:40.139732324 +0900
@@ -0,0 +1,68 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@....
+#
+# (C) Copyright 2008
+# Stelian Pop
+# Lead Tech Design
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mb8ac0300.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#initlogo.h: initlogo.rle
+# $(shell hexdump -Cv initlogo.rle | \
+# cut -d' ' -f2-19 | \
+# tr -s ' ' | \
+# sed "s/\ /\,\ 0x/g" | \
+# sed "s/^\ //g" | \
+# sed "s/\$$/\,/g" | \
+# sed "s/^\,//g" | \
+# sed "s/0x\,//g" | \
+# sed "s/^0.*//g" > initlogo.h)
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+include $(obj).depend
+
+#########################################################################
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/initlogo.h u-boot/board/socionext/mb8ac0300eb/initlogo.h
--- original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/initlogo.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb8ac0300eb/initlogo.h 2016-08-02 14:19:40.140732320 +0900
@@ -0,0 +1,2136 @@
+ 0x20, 0x03, 0x5d, 0xef, 0x81, 0x06, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0xab, 0xf2,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xf3, 0x01, 0x00, 0xfb, 0xfe, 0x18, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0x38, 0xfe, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9, 0x02, 0x00, 0x72, 0xf4,
+ 0x01, 0x00, 0x4d, 0xf3, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe, 0x17, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xf2, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xfe,
+ 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x29, 0xea, 0x17, 0x03, 0xff, 0xff, 0x01, 0x00, 0xab, 0xf2,
+ 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xfe, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x11, 0x03, 0xff, 0xff, 0x01, 0x00, 0x18, 0xfe, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xb7, 0xfd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xfe, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0x25, 0xe9,
+ 0x01, 0x00, 0x51, 0xf4, 0x0f, 0x03, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0xc8, 0xe9,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x39, 0xfe, 0x08, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0xf0, 0xf3, 0x0e, 0x03, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xff,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0x1c, 0xff, 0x01, 0x00, 0xb3, 0xf4,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x0e, 0x03, 0xff, 0xff, 0x01, 0x00, 0x31, 0xf4,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xfe, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xfe,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xfe, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb3, 0xf4, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe, 0x0e, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xf2, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x39, 0xfe, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xf2, 0x0f, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xec, 0xf2, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe,
+ 0x01, 0x00, 0x04, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xf2, 0x10, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0xaf, 0xf3, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x1c, 0xff, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xaf, 0xf3,
+ 0x01, 0x00, 0x6a, 0xf2, 0x01, 0x00, 0x71, 0xf4, 0x01, 0x00, 0xd7, 0xfd, 0x11, 0x03, 0xff, 0xff,
+ 0x01, 0x00, 0x59, 0xfe, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0xf8, 0xfd,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xfe, 0x01, 0x00, 0xab, 0xf2, 0x01, 0x00, 0xe4, 0xe8,
+ 0x19, 0x03, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x38, 0xfe,
+ 0x1b, 0x03, 0xff, 0xff, 0x01, 0x00, 0x92, 0xf4, 0x02, 0x00, 0x72, 0xf4, 0x88, 0x02, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xfb, 0xde, 0xa6, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xfd,
+ 0x04, 0x00, 0x72, 0xf4, 0x01, 0x00, 0x9a, 0xfe, 0x66, 0x02, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x10, 0x7c, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x67, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xff, 0x01, 0x00, 0x05, 0xe9,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0x39, 0xfe, 0x04, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x59, 0xfe, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xfe, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xe8, 0xe9, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x04, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x9a, 0xfe, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfc, 0xfe, 0x04, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x6e, 0xf3, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xf3, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0xf4, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xa7, 0xe9,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe,
+ 0x04, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x5d, 0xff, 0x53, 0x02, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x10, 0x7c, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xba, 0xd6, 0x68, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x0a, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x0c, 0xf3, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xf3, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x08, 0xea, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9,
+ 0x02, 0x00, 0xff, 0xff, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xf4, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xab, 0xf2, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xf3, 0x02, 0x00, 0x72, 0xf4,
+ 0x01, 0x00, 0xec, 0xf2, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0x9e, 0xf7, 0x08, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xdb, 0xde,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdf, 0xff, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x03, 0x00, 0x7d, 0xef, 0x01, 0x00, 0x9e, 0xf7, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdf, 0xff, 0x06, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x5d, 0xef, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x5d, 0xef, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x5d, 0xef, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x5d, 0xef, 0x08, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x06, 0x00, 0x7d, 0xef, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x02, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xdf, 0xff, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x7d, 0xef,
+ 0x06, 0x00, 0xff, 0xff, 0x02, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x7d, 0xef, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x03, 0x00, 0x7d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x08, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0x9e, 0xf7,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0xbe, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x03, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x03, 0x00, 0x7d, 0xef, 0x01, 0x00, 0x9e, 0xf7,
+ 0x01, 0x00, 0xdf, 0xff, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xfb, 0xde,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xdf, 0xff, 0x06, 0x00, 0xff, 0xff, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0x9e, 0xf7, 0xb8, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c,
+ 0x73, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xfe, 0x01, 0x00, 0x39, 0xfe, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x0c, 0xf3,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x31, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9,
+ 0x01, 0x00, 0x1c, 0xff, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0x72, 0xf4,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x1c, 0xe7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0x9a, 0xd6, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x03, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xf3, 0x9c,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0xfb, 0xde, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x92, 0x94,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x1c, 0xe7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0xfb, 0xde, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0x92, 0x94,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x1c, 0xe7, 0x06, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x08, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x04, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x03, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x05, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0x34, 0xa5, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x18, 0xc6,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x03, 0x00, 0xff, 0xff, 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x96, 0xb5,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x04, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x7d, 0xef, 0xb5, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c, 0x73, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x7d, 0xff, 0x01, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xfd,
+ 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x51, 0x8c, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x1c, 0xe7,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x04, 0x00, 0x10, 0x84, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xf3, 0x9c, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x51, 0x8c, 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x51, 0x8c,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x51, 0x8c, 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x30, 0x84,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xbe, 0xf7, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x08, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x03, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x07, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x04, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x3c, 0xe7, 0x03, 0x00, 0xff, 0xff, 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0xdf, 0xff, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c,
+ 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xaf, 0x73, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xdb, 0xde, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5,
+ 0x01, 0x00, 0x10, 0x84, 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb3, 0x94, 0x01, 0x00, 0xdb, 0xde,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x72, 0x8c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x35, 0xa5, 0x03, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xcf, 0x7b, 0x01, 0x00, 0xb7, 0xb5, 0x3e, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x0a, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6,
+ 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xb2, 0x94, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x03, 0x00, 0x79, 0xce, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7,
+ 0x02, 0x00, 0x79, 0xce, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x9a, 0xd6,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0xba, 0xd6,
+ 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd7, 0xbd, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xb2, 0x94, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff, 0x09, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xef, 0x7b, 0x07, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x07, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94, 0x3d, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xfd, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x7a, 0xfe,
+ 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0xff, 0xff, 0x04, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb2, 0x94, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x71, 0x8c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xbe, 0xf7, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x03, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb6, 0xb5, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c,
+ 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb3, 0x94, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0xef, 0x7b, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x72, 0x8c, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x8e, 0x6b, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xf2, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x03, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c,
+ 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x03, 0x00, 0x6e, 0x6b,
+ 0x08, 0x00, 0xff, 0xff, 0x01, 0x00, 0xaf, 0x73, 0x02, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x31, 0x84, 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x0c, 0xf3, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x96, 0xfd,
+ 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x03, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x04, 0x00, 0xff, 0xff, 0x02, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0x34, 0xa5,
+ 0x04, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x02, 0x00, 0x6e, 0x6b,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0x7c, 0x02, 0x00, 0x6e, 0x6b, 0x3c, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x09, 0x00, 0xe4, 0xe8, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x4a, 0xf2, 0x04, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xf2,
+ 0x01, 0x00, 0x39, 0xfe, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xf3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x03, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c,
+ 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x03, 0x00, 0x6e, 0x6b,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb6, 0xb5,
+ 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xaf, 0x73, 0x02, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x6e, 0x6b,
+ 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x09, 0x00, 0xe4, 0xe8, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0xab, 0xf2, 0x05, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xf2, 0x01, 0x00, 0x7a, 0xfe, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9a, 0xd6, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x34, 0xa5, 0x01, 0x00, 0x55, 0xad, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x10, 0x7c, 0x02, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x02, 0x00, 0x6e, 0x6b, 0x05, 0x00, 0xff, 0xff, 0x03, 0x00, 0x6e, 0x6b, 0x3c, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xfd,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x08, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xfd,
+ 0x01, 0x00, 0x86, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x05, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x10, 0x84, 0x02, 0x00, 0x14, 0xa5,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0x7c, 0x02, 0x00, 0x6e, 0x6b,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xf7, 0xbd,
+ 0x04, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x8e, 0x73, 0x3c, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x0a, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0xf4, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x02, 0x00, 0x75, 0xad, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9a, 0xd6, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x14, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x03, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xf3, 0x9c,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0x92, 0x94,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0xff, 0xff, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x10, 0x7c, 0x08, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xaf, 0x73, 0x02, 0x00, 0x6e, 0x6b,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x76, 0xad, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x0c, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf0, 0xf3, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8b, 0xf2, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb2, 0x94, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xdf, 0xff,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x09, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x03, 0x00, 0x6e, 0x6b,
+ 0x02, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0x8e, 0x73, 0x03, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x35, 0xa5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94,
+ 0x3d, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x10, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xf4, 0x0d, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x02, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x14, 0xa5, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0xb4, 0x00, 0xff, 0xff, 0x09, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5,
+ 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x02, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0xb7, 0xb5, 0x04, 0x00, 0xff, 0xff, 0x03, 0x00, 0x6e, 0x6b,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x04, 0x00, 0x6e, 0x6b, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x18, 0xc6, 0x03, 0x00, 0x6e, 0x6b, 0x02, 0x00, 0xb7, 0xb5, 0x02, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0xb7, 0xb5, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x05, 0x00, 0x6e, 0x6b,
+ 0x01, 0x00, 0x92, 0x94, 0x3e, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x31, 0xf4,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x0e, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0xad, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x96, 0xb5, 0x03, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6, 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x14, 0xa5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x06, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c,
+ 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x08, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x38, 0xc6, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x07, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdb, 0xde,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0xd2, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb7, 0xb5, 0x01, 0x00, 0xdb, 0xde, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xd7, 0xbd, 0x0e, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6,
+ 0x02, 0x00, 0xb7, 0xb5, 0x40, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x09, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf7, 0xfd, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x0d, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xfe,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x76, 0xfd, 0x03, 0x00, 0xe4, 0xe8,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb2, 0xf4, 0xad, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x38, 0xc6,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x18, 0xc6, 0x07, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x75, 0xad, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x07, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x30, 0x84,
+ 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x08, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xba, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x08, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x75, 0xad,
+ 0x2a, 0x01, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x09, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xfe, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf7, 0xfd, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x0c, 0xf3, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x07, 0x00, 0xff, 0xff,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xfe,
+ 0x01, 0x00, 0x1c, 0xff, 0x07, 0x00, 0xff, 0xff, 0x01, 0x00, 0xab, 0xf2, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xf2, 0x02, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xf3,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0xae, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xfb, 0xde,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0x1c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x71, 0x8c, 0x03, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xf3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x03, 0x00, 0xdf, 0xff, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x04, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0xba, 0xd6, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x7d, 0xef, 0x03, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x02, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x71, 0x8c,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xd7, 0xbd,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xb2, 0x94, 0x02, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x30, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0x8c,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84,
+ 0x03, 0x00, 0xba, 0xd6, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde,
+ 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xba, 0xd6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xdf, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd,
+ 0xa8, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd9, 0xf5, 0x06, 0x00, 0x4d, 0xe2, 0x01, 0x00, 0x5d, 0xff,
+ 0x01, 0x00, 0xdd, 0xe6, 0x02, 0x00, 0x15, 0x8b, 0x01, 0x00, 0xff, 0xff, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x12, 0xcf, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x55, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x99, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x76, 0xdf, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x99, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x98, 0xe7, 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xe4, 0xe8,
+ 0x0a, 0x00, 0xff, 0xff, 0x01, 0x00, 0xaf, 0xf3, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x14, 0xf5,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x2d, 0xf3, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe,
+ 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x07, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0xba, 0xfe, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x38, 0xfe, 0x01, 0x00, 0xab, 0xf2, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xba, 0xfe,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xfe, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xf3,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x10, 0xf4, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xfd,
+ 0xae, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef,
+ 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xfb, 0xde,
+ 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0x51, 0x8c, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x30, 0x84,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x3c, 0xe7, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xa5,
+ 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xdf, 0xff, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x1c, 0xe7, 0x03, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x02, 0x00, 0x10, 0x84,
+ 0x02, 0x00, 0x30, 0x84, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x38, 0xc6, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c,
+ 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0x30, 0x84, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x07, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94, 0x07, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x5d, 0xef, 0xa7, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xe7, 0x01, 0x00, 0x72, 0xdd,
+ 0x01, 0x00, 0x4b, 0xd3, 0x05, 0x00, 0x4d, 0xe2, 0x01, 0x00, 0x9b, 0xfe, 0x01, 0x00, 0xdd, 0xe6,
+ 0x02, 0x00, 0x15, 0x8b, 0x01, 0x00, 0xff, 0xff, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0xf1, 0xc6,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7,
+ 0x3c, 0x00, 0xff, 0xff, 0x01, 0x00, 0xcb, 0xf2, 0x03, 0x00, 0xe4, 0xe8, 0x0b, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x2d, 0xf3, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x18, 0xfe, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xab, 0xf2, 0x03, 0x00, 0xe4, 0xe8, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xfe,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x6e, 0xf3,
+ 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x39, 0xfe, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xf8, 0xfd, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x14, 0xf5, 0xaf, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x30, 0x84, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x30, 0x84,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0x34, 0xa5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb6, 0xb5, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf7, 0xbd,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd7, 0xbd, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd,
+ 0x05, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf7, 0xbd, 0x06, 0x00, 0xff, 0xff, 0x01, 0x00, 0x75, 0xad,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd7, 0xbd,
+ 0x03, 0x00, 0x10, 0x84, 0x01, 0x00, 0x71, 0x8c, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xbe, 0xf7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad,
+ 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x55, 0xad, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x51, 0x8c, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x96, 0xb5, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0x51, 0x8c,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x14, 0xa5,
+ 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x55, 0xad, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x9e, 0xf7,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0x10, 0x84, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x71, 0x8c, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0x92, 0x94,
+ 0x01, 0x00, 0x7d, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0x14, 0xa5, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x06, 0x00, 0x10, 0x84,
+ 0x01, 0x00, 0xd3, 0x9c, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde,
+ 0x01, 0x00, 0x30, 0x84, 0x04, 0x00, 0x10, 0x84, 0x01, 0x00, 0xb2, 0x94, 0x01, 0x00, 0xbe, 0xf7,
+ 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf3, 0x9c, 0x01, 0x00, 0x10, 0x84, 0x01, 0x00, 0xf3, 0x9c,
+ 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x96, 0xb5,
+ 0x01, 0x00, 0xff, 0xff, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0xd3, 0x9c, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x02, 0x00, 0x10, 0x84, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x92, 0x94, 0x06, 0x00, 0x10, 0x84, 0x01, 0x00, 0x59, 0xce, 0xa8, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x12, 0xcf, 0x01, 0x00, 0xad, 0xc5, 0x01, 0x00, 0x29, 0xbc, 0x01, 0x00, 0xcc, 0xda,
+ 0x04, 0x00, 0x4d, 0xe2, 0x01, 0x00, 0x9b, 0xfe, 0x04, 0x00, 0xff, 0xff, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0xf1, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x3b, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xff, 0x04, 0x00, 0x72, 0xf4,
+ 0x01, 0x00, 0x39, 0xfe, 0x0b, 0x00, 0xff, 0xff, 0x01, 0x00, 0x39, 0xfe, 0x01, 0x00, 0xaf, 0xf3,
+ 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x01, 0x00, 0x1c, 0xff, 0x06, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xff, 0x04, 0x00, 0x72, 0xf4, 0x01, 0x00, 0x39, 0xfe, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xb7, 0xfd, 0x04, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xf8, 0xfd,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xf2, 0x01, 0x00, 0x92, 0xf4, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x31, 0xf4,
+ 0x01, 0x00, 0x7a, 0xfe, 0xb0, 0x00, 0xff, 0xff, 0x01, 0x00, 0x7d, 0xef, 0x02, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdb, 0xde, 0x03, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0x3c, 0xe7, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xd7, 0xbd,
+ 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x1c, 0xe7, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xfb, 0xde, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x5d, 0xef, 0x01, 0x00, 0x18, 0xc6,
+ 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0xba, 0xd6, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xd7, 0xbd,
+ 0x01, 0x00, 0xfb, 0xde, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x1c, 0xe7, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0xd7, 0xbd, 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x1c, 0xe7, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0xfb, 0xde, 0x01, 0x00, 0xd7, 0xbd,
+ 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x1c, 0xe7, 0x07, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xba, 0xd6, 0x06, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x38, 0xc6, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x03, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x18, 0xc6, 0x04, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xba, 0xd6, 0x06, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x18, 0xc6, 0x02, 0x00, 0x75, 0xad, 0x01, 0x00, 0x38, 0xc6,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x79, 0xce, 0x04, 0x00, 0xff, 0xff, 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x59, 0xce, 0x02, 0x00, 0xff, 0xff, 0x01, 0x00, 0xba, 0xd6, 0x02, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0xdf, 0xff, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0x79, 0xce, 0x01, 0x00, 0xf7, 0xbd,
+ 0x01, 0x00, 0x18, 0xc6, 0x03, 0x00, 0xff, 0xff, 0x01, 0x00, 0xbe, 0xf7, 0x01, 0x00, 0x38, 0xc6,
+ 0x02, 0x00, 0x96, 0xb5, 0x01, 0x00, 0x59, 0xce, 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xbe, 0xf7, 0x02, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x9a, 0xd6, 0x05, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x3c, 0xe7, 0x03, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x59, 0xce,
+ 0x01, 0x00, 0xfb, 0xde, 0x05, 0x00, 0xff, 0xff, 0x01, 0x00, 0x9e, 0xf7, 0x01, 0x00, 0x18, 0xc6,
+ 0x01, 0x00, 0x75, 0xad, 0x01, 0x00, 0xb6, 0xb5, 0x01, 0x00, 0x79, 0xce, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x38, 0xc6, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0xba, 0xd6, 0x03, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xdf, 0xff, 0x02, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x9a, 0xd6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x79, 0xce, 0x02, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x9e, 0xf7, 0x02, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0xdb, 0xde, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x59, 0xce, 0x03, 0x00, 0xf7, 0xbd, 0x01, 0x00, 0x18, 0xc6, 0x01, 0x00, 0x9a, 0xd6,
+ 0x01, 0x00, 0x7d, 0xef, 0xa9, 0x00, 0xff, 0xff, 0x01, 0x00, 0x12, 0xcf, 0x01, 0x00, 0xad, 0xc5,
+ 0x01, 0x00, 0x29, 0xbc, 0x01, 0x00, 0xcc, 0xda, 0x03, 0x00, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe2,
+ 0x01, 0x00, 0xd9, 0xe5, 0x04, 0x00, 0x1d, 0xef, 0x02, 0x00, 0xca, 0x9d, 0x01, 0x00, 0x48, 0xa6,
+ 0x04, 0x00, 0x68, 0xa6, 0x01, 0x00, 0xf1, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7,
+ 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7,
+ 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7,
+ 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7,
+ 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7,
+ 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x5b, 0x00, 0xff, 0xff, 0x01, 0x00, 0xec, 0xf2,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x7a, 0x02, 0xff, 0xff, 0x01, 0x00, 0x78, 0xe7,
+ 0x01, 0x00, 0x71, 0xd5, 0x01, 0x00, 0x8a, 0xcb, 0x01, 0x00, 0x8d, 0xda, 0x02, 0x00, 0x4d, 0xe2,
+ 0x01, 0x00, 0x2d, 0xe2, 0x01, 0x00, 0x4b, 0xc9, 0x01, 0x00, 0x74, 0xab, 0x04, 0x00, 0x17, 0xa4,
+ 0x03, 0x00, 0xf0, 0x93, 0x04, 0x00, 0x68, 0xa6, 0x01, 0x00, 0xf1, 0xc6, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6, 0x01, 0x00, 0x34, 0xd7, 0x5b, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xec, 0xf2, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xf4, 0x7b, 0x02, 0xff, 0xff,
+ 0x01, 0x00, 0x36, 0xf5, 0x04, 0x00, 0x4d, 0xe2, 0x01, 0x00, 0x0d, 0xda, 0x01, 0x00, 0x4b, 0xc9,
+ 0x01, 0x00, 0x94, 0xab, 0x04, 0x00, 0x17, 0xa4, 0x03, 0x00, 0xf0, 0x93, 0x04, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0xf1, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x5b, 0x00, 0xff, 0xff, 0x01, 0x00, 0x25, 0xe9, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x14, 0xf5, 0x7c, 0x02, 0xff, 0xff, 0x04, 0x00, 0x36, 0xf5, 0x01, 0x00, 0x95, 0xe4,
+ 0x01, 0x00, 0xd1, 0xba, 0x05, 0x00, 0x17, 0xa4, 0x03, 0x00, 0xf0, 0x93, 0x04, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0xf1, 0xc6, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x34, 0xd7, 0x07, 0x00, 0x68, 0xa6,
+ 0x01, 0x00, 0x34, 0xd7, 0x5b, 0x00, 0xff, 0xff, 0x03, 0x00, 0xe4, 0xe8, 0x81, 0x02, 0xff, 0xff,
+ 0x01, 0x00, 0x1d, 0xef, 0x06, 0x00, 0x17, 0xa4, 0x03, 0x00, 0x13, 0x9c, 0x04, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0x99, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x99, 0xe7, 0x07, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0x99, 0xe7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x99, 0xe7, 0x07, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xbb, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x99, 0xe7, 0x07, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0x9a, 0xef, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x99, 0xe7, 0x07, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xdd, 0xf7, 0x01, 0x00, 0xff, 0xff, 0x01, 0x00, 0x99, 0xe7, 0x07, 0x00, 0x34, 0xd7,
+ 0x01, 0x00, 0xbb, 0xef, 0x5a, 0x00, 0xff, 0xff, 0x01, 0x00, 0x72, 0xf4, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x39, 0xfe, 0x81, 0x02, 0xff, 0xff, 0x01, 0x00, 0x1d, 0xef, 0x09, 0x00, 0x17, 0xa4,
+ 0x91, 0x00, 0xff, 0xff, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xfe,
+ 0x82, 0x02, 0xff, 0xff, 0x01, 0x00, 0x1d, 0xef, 0x09, 0x00, 0x17, 0xa4, 0x90, 0x00, 0xff, 0xff,
+ 0x01, 0x00, 0xab, 0xf2, 0x01, 0x00, 0x10, 0xf4, 0x01, 0x00, 0x7d, 0xff, 0x81, 0x02, 0xff, 0xff,
+ 0x01, 0x00, 0xbf, 0xff, 0x01, 0x00, 0x7e, 0xff, 0x01, 0x00, 0x9c, 0xe6, 0x01, 0x00, 0xf6, 0xab,
+ 0x01, 0x00, 0x16, 0xac, 0x07, 0x00, 0x17, 0xa4, 0x14, 0x03, 0xff, 0xff, 0x02, 0x00, 0x12, 0xec,
+ 0x01, 0x00, 0xb2, 0xe3, 0x02, 0x00, 0x4f, 0xc2, 0x01, 0x00, 0xb5, 0xab, 0x06, 0x00, 0x17, 0xa4,
+ 0x14, 0x03, 0xff, 0xff, 0x02, 0x00, 0x12, 0xec, 0x01, 0x00, 0xf2, 0xeb, 0x02, 0x00, 0x4f, 0xc2,
+ 0x01, 0x00, 0x74, 0xb3, 0x05, 0x00, 0x17, 0xa4, 0x01, 0x00, 0x78, 0xac, 0x14, 0x03, 0xff, 0xff,
+ 0x05, 0x00, 0x12, 0xec, 0x01, 0x00, 0x7b, 0xf6, 0x1a, 0x03, 0xff, 0xff, 0x05, 0x00, 0x12, 0xec,
+ 0x01, 0x00, 0x7b, 0xf6, 0x1a, 0x03, 0xff, 0xff, 0x05, 0x00, 0x12, 0xec, 0x01, 0x00, 0x3d, 0xff,
+ 0xdd, 0x0c, 0xff, 0xff, 0xff, 0xff, 0x3c, 0xe7, 0x0e, 0x08, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0xaf, 0xeb, 0x02, 0x00, 0x4d, 0xeb,
+ 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0x18, 0xe6,
+ 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x08, 0xea,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0x14, 0xed,
+ 0x01, 0x00, 0xfb, 0xe6, 0x0d, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0x0c, 0xeb,
+ 0x01, 0x00, 0x04, 0xe9, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x45, 0xe9, 0x01, 0x00, 0xf0, 0xeb,
+ 0x01, 0x00, 0xba, 0xe6, 0x09, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x6e, 0xeb,
+ 0x14, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x1c, 0xe7,
+ 0x06, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x66, 0xe9, 0x17, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x51, 0xec, 0x04, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x31, 0xec,
+ 0x1b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x29, 0xea,
+ 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x25, 0xe9,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0xbb, 0xe6, 0xff, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x6e, 0xeb, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0xcb, 0xea,
+ 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x7a, 0xe6, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0xb3, 0xec, 0x01, 0x00, 0x8b, 0xea, 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea,
+ 0x01, 0x00, 0xfb, 0xe6, 0xfd, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x31, 0xec, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0x79, 0xe6, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x4d, 0xeb, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea,
+ 0xfc, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea,
+ 0x01, 0x00, 0x18, 0xe6, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0xc8, 0xe9,
+ 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xec, 0xfb, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4e, 0xeb, 0x01, 0x00, 0x1c, 0xe7, 0x12, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xab, 0xea, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0x38, 0xe6, 0xfa, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x05, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf0, 0xeb, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xec, 0xea,
+ 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xea, 0xfa, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x04, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x4a, 0xea, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x75, 0xed, 0xf9, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xea, 0x19, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x7a, 0xe6, 0x01, 0x00, 0xcf, 0xeb, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xea,
+ 0xf9, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x01, 0x00, 0xbb, 0xe6, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xa7, 0xe9,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x38, 0xe6, 0xf8, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x34, 0xed, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf0, 0xeb, 0xf8, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xea, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x86, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x09, 0xea, 0xf8, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd7, 0xe5, 0x1e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xaf, 0xeb, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xba, 0xe6, 0xf7, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0xab, 0xea, 0x1f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xe5,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0xe7, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0xb6, 0xe5, 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0xb7, 0xe5,
+ 0x01, 0x00, 0x7a, 0xe6, 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x35, 0xed,
+ 0x1f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec,
+ 0xe3, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x8a, 0xea,
+ 0x01, 0x00, 0x25, 0xe9, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xab, 0xea,
+ 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0xba, 0xe6, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6,
+ 0x01, 0x00, 0x1c, 0xe7, 0x20, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xa7, 0xe9, 0x05, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcf, 0xeb, 0xe1, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xec, 0xea,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x59, 0xe6,
+ 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x29, 0xea, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb,
+ 0xdf, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0x6e, 0xeb, 0x11, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x1c, 0xe7, 0x24, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x49, 0xea, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb, 0xde, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0xcf, 0xeb, 0x15, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x79, 0xe6,
+ 0x23, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x08, 0xea, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb,
+ 0xdc, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x17, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0x22, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x66, 0xe9,
+ 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf0, 0xeb, 0xdb, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0xec, 0xea, 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x59, 0xe6,
+ 0x20, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd3, 0xec,
+ 0xdb, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9,
+ 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0x18, 0xe6, 0x02, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0xf8, 0xe5, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x0d, 0xeb, 0x01, 0x00, 0x25, 0xe9,
+ 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0xba, 0xe6, 0x1f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x14, 0xed, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd7, 0xed, 0xda, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x75, 0xed, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x45, 0xe9, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0xfb, 0xe6, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xbb, 0xe6, 0x01, 0x00, 0xcf, 0xeb,
+ 0x01, 0x00, 0x05, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0xfb, 0xe6,
+ 0x1e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x2d, 0xeb, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0xfb, 0xe6, 0xd9, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xa7, 0xe9,
+ 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x79, 0xe6, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0xa7, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8b, 0xea,
+ 0x01, 0x00, 0x1c, 0xe7, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xbb, 0xe6, 0x01, 0x00, 0x25, 0xe9,
+ 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xea, 0xda, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec,
+ 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xea, 0x01, 0x00, 0xfb, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x7a, 0xe6, 0x01, 0x00, 0xc7, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x10, 0xec, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0xd9, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x86, 0xe9, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xc8, 0xe9, 0x01, 0x00, 0xdb, 0xe6, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0x66, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf0, 0xeb, 0x1a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x25, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0xba, 0xe6, 0xd9, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0xd7, 0xe5, 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5,
+ 0x01, 0x00, 0x25, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x18, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xe5, 0x01, 0x00, 0x8a, 0xea, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb,
+ 0xda, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x2d, 0xeb, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x18, 0xe6,
+ 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x04, 0xe9, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x35, 0xed, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x66, 0xe9,
+ 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x38, 0xe6, 0xda, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x4a, 0xea,
+ 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x1c, 0xe7, 0x14, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x29, 0xea, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8b, 0xea,
+ 0x01, 0x00, 0x1c, 0xe7, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x10, 0xec, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0x1c, 0xe7, 0xd9, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x05, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x16, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0xc7, 0xe9, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xea,
+ 0x01, 0x00, 0xfb, 0xe6, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf0, 0xeb, 0x08, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x75, 0xed, 0xda, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x66, 0xe9,
+ 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0x10, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0xcb, 0xea, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb,
+ 0xdb, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x75, 0xe5, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xe6,
+ 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0x25, 0xe9, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0xba, 0xe6, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x66, 0xe9, 0x08, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0xdb, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed,
+ 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xfb, 0xe6, 0x19, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x01, 0x00, 0x04, 0xe9, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x4e, 0xeb,
+ 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x1c, 0xe7, 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf8, 0xe5,
+ 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x86, 0xe9, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x87, 0xe9,
+ 0x01, 0x00, 0x79, 0xe6, 0xdc, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x04, 0xe9,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x0d, 0xeb,
+ 0x02, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x46, 0xe9,
+ 0x0b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0xdd, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x75, 0xed, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xe6, 0x1b, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x25, 0xe9, 0x1b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc8, 0xe9,
+ 0x01, 0x00, 0x59, 0xe6, 0xde, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x38, 0xe6, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x35, 0xed, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xed, 0x03, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0xe8, 0xe9, 0x18, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0xdb, 0xe6, 0xdf, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x05, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x17, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0xec, 0xea, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x05, 0xe9, 0x15, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb,
+ 0x01, 0x00, 0x9a, 0xe6, 0xe2, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x6a, 0xea, 0x05, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xab, 0xea,
+ 0x01, 0x00, 0xcb, 0xea, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x4d, 0xeb,
+ 0x01, 0x00, 0x05, 0xe9, 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0xb7, 0xe5,
+ 0xe4, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x31, 0xec, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0xfb, 0xe6, 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x71, 0xec, 0x01, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xea, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0x09, 0xea, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0xaf, 0xeb,
+ 0x01, 0x00, 0x18, 0xe6, 0xe6, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x45, 0xe9, 0x01, 0x00, 0x8e, 0xeb, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x0b, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x0c, 0xeb,
+ 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x09, 0xea, 0x01, 0x00, 0x08, 0xea, 0x01, 0x00, 0x6a, 0xea,
+ 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0xb3, 0xec, 0x01, 0x00, 0x59, 0xe6,
+ 0xea, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec,
+ 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0x25, 0xe9, 0x02, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xea, 0x01, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x07, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xf3, 0xec, 0x0f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec,
+ 0x01, 0x00, 0x05, 0xe9, 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x02, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0xab, 0xea, 0x05, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xea, 0x02, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xc8, 0xe9,
+ 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x59, 0xe6,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x2d, 0xeb,
+ 0x01, 0x00, 0x05, 0xe9, 0x06, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x03, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0x46, 0xe9, 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0x2d, 0xeb,
+ 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x45, 0xe9, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x10, 0xec,
+ 0x04, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xb6, 0xe5, 0x01, 0x00, 0x25, 0xe9, 0x18, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x6e, 0xeb, 0x06, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0x86, 0xe9,
+ 0x16, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf0, 0xeb, 0x08, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0x25, 0xe9, 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x01, 0x00, 0x55, 0xed, 0x0b, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x2d, 0xeb,
+ 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0xba, 0xe6,
+ 0x0e, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0x66, 0xe9,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x7a, 0xe6,
+ 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0x72, 0xec, 0x01, 0x00, 0x6e, 0xeb,
+ 0x01, 0x00, 0xab, 0xea, 0x02, 0x00, 0x6a, 0xea, 0x01, 0x00, 0xcc, 0xea, 0x01, 0x00, 0x8e, 0xeb,
+ 0x01, 0x00, 0xb2, 0xec, 0x01, 0x00, 0x18, 0xe6, 0xf8, 0x0c, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xd7, 0xe5, 0x02, 0x00, 0xb6, 0xe5,
+ 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0x39, 0xe6, 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0x1c, 0xe7,
+ 0x10, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x01, 0x00, 0x71, 0xec,
+ 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x46, 0xe9, 0x0a, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x2d, 0xeb,
+ 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0x38, 0xe6, 0x0a, 0x02, 0x3c, 0xe7,
+ 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x31, 0xec, 0x30, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x76, 0xed,
+ 0x01, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x14, 0xed, 0x15, 0x00, 0x0c, 0xeb,
+ 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0xfb, 0xe6, 0x12, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x51, 0xec, 0x15, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0xd3, 0xec,
+ 0x01, 0x00, 0xba, 0xe6, 0x03, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xd7, 0xed,
+ 0x01, 0x00, 0xb2, 0xec, 0x15, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x9a, 0xe6,
+ 0x03, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xcf, 0xeb,
+ 0x14, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0xfb, 0xe6,
+ 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x35, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0xf4, 0xec,
+ 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0xcb, 0xea,
+ 0x01, 0x00, 0x25, 0xe9, 0x16, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x2d, 0xeb,
+ 0x01, 0x00, 0x18, 0xe6, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0xb3, 0xec, 0x15, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x9a, 0xe6,
+ 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x2d, 0xeb,
+ 0x14, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0xdb, 0xe6,
+ 0xbd, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x71, 0xec, 0x01, 0x00, 0x04, 0xe9, 0x2e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x92, 0xec, 0x03, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0xa7, 0xe9,
+ 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x59, 0xe6, 0x16, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x05, 0xe9, 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9,
+ 0x01, 0x00, 0x96, 0xe5, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x46, 0xe9,
+ 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x45, 0xe9, 0x01, 0x00, 0x14, 0xed, 0x07, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x6e, 0xeb, 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea,
+ 0x01, 0x00, 0x59, 0xe6, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x36, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0x4d, 0xeb,
+ 0x01, 0x00, 0x25, 0xe9, 0x1b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x09, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x46, 0xe9, 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9,
+ 0x01, 0x00, 0x14, 0xed, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xc8, 0xe9,
+ 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0xc0, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd3, 0xec, 0x2e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x04, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x86, 0xe9, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x08, 0xea,
+ 0x01, 0x00, 0xdb, 0xe6, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x10, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0x38, 0xe6, 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5,
+ 0x01, 0x00, 0x25, 0xe9, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xb7, 0xed,
+ 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x08, 0xea,
+ 0x01, 0x00, 0xdb, 0xe6, 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec, 0x35, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0x09, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6,
+ 0x01, 0x00, 0x2d, 0xeb, 0x1e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x0a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0x25, 0xe9, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0xb6, 0xe5, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0xa7, 0xe9,
+ 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0xba, 0xe6, 0xc2, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x0c, 0xeb, 0x2d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x05, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x18, 0xe6,
+ 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf3, 0xec,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x31, 0xec,
+ 0x0b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x09, 0xea, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xab, 0xea,
+ 0x35, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xea, 0x09, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec,
+ 0x01, 0x00, 0x25, 0xe9, 0x1f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x0b, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x30, 0xec, 0x1a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xe5, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0xc3, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x39, 0xe6, 0x2d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x49, 0xea, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x1b, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0x25, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9,
+ 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x86, 0xe9, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x25, 0xe9, 0x35, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x07, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xcb, 0xea, 0x21, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x0b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x87, 0xe9, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8a, 0xea,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0xc5, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x49, 0xea,
+ 0x2c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb2, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x0c, 0xeb,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x31, 0xec, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x46, 0xe9,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x36, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xe6, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0x08, 0xea, 0x22, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xcf, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6e, 0xeb, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf3, 0xec, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x14, 0xed, 0xc5, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0xaf, 0xeb, 0x2c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x18, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb6, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xab, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xfc, 0xe6, 0x08, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x6e, 0xeb, 0x35, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0xc8, 0xe9, 0x14, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0x25, 0xe9,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x9a, 0xe6, 0xc5, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec,
+ 0x2c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x59, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x4d, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9, 0x09, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x87, 0xe9,
+ 0x35, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcf, 0xeb, 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x29, 0xea, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0x6a, 0xea,
+ 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x1c, 0xe7,
+ 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xb7, 0xed, 0x01, 0x00, 0x92, 0xec,
+ 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x05, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x1c, 0xe7,
+ 0xc5, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcc, 0xea,
+ 0x18, 0x00, 0x55, 0xed, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0x86, 0xe9,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6,
+ 0x04, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x08, 0xea, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x14, 0xed,
+ 0x0d, 0x00, 0x55, 0xed, 0x01, 0x00, 0x4e, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x14, 0xed,
+ 0x0b, 0x00, 0x55, 0xed, 0x01, 0x00, 0xb3, 0xec, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x25, 0xe9,
+ 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb6, 0xe5, 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x6d, 0xeb,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x30, 0xec, 0x01, 0x00, 0xba, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x66, 0xe9,
+ 0x03, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x31, 0xec,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x08, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x31, 0xec, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0xb6, 0xed,
+ 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0xec, 0xea, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0x1c, 0xe7, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0xdb, 0xe6, 0x12, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x6e, 0xeb, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x08, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x31, 0xec, 0x12, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x0f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x2d, 0xeb, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb, 0x04, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xc7, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb2, 0xec,
+ 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x66, 0xe9,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x92, 0xec, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0xf3, 0xec, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x0f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf3, 0xec, 0x04, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x18, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x66, 0xe9, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xf3, 0xec,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x31, 0xec, 0x14, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x10, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0xba, 0xe6, 0x03, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xa7, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb,
+ 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x10, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x1e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x06, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0xb2, 0xec, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x01, 0x00, 0x31, 0xec, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x9a, 0xe6, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x1e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x06, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x9a, 0xe6, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x10, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x9a, 0xe6, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x25, 0xe9,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd7, 0xe5, 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x46, 0xe9, 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xea,
+ 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x4d, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb, 0x29, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8a, 0xea,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb, 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb6, 0xe5, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x29, 0xea, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x4d, 0xeb, 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xc8, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xea,
+ 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xc8, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x1c, 0xe7,
+ 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x49, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x34, 0xed, 0x28, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x2d, 0xeb,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x10, 0xec, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x27, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea,
+ 0x01, 0x00, 0x1c, 0xe7, 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x05, 0xe9, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcc, 0xea, 0x01, 0x00, 0x1c, 0xe7, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x0f, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8a, 0xea, 0x01, 0x00, 0xba, 0xe6, 0x24, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xe5, 0x10, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0x55, 0xed, 0x23, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x4a, 0xea, 0x11, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0x18, 0xe6, 0x21, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x13, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x9a, 0xe6, 0x1f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x6e, 0xeb, 0x13, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xcf, 0xeb, 0x01, 0x00, 0xdb, 0xe6, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x18, 0x00, 0x29, 0xea, 0x01, 0x00, 0x75, 0xed,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xc7, 0xe9, 0x14, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x72, 0xec, 0x01, 0x00, 0x1c, 0xe7, 0x1b, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x19, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6,
+ 0x01, 0x00, 0x25, 0xe9, 0x15, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0xf4, 0xec,
+ 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x1a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x05, 0xe9, 0x16, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x09, 0xea,
+ 0x01, 0x00, 0x76, 0xed, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd3, 0xec,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x04, 0xe9, 0x17, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0x18, 0xe6, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x26, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xd3, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x25, 0xe9,
+ 0x18, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x79, 0xe6, 0x14, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd3, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf8, 0xe5,
+ 0x01, 0x00, 0x87, 0xe9, 0x18, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xaf, 0xeb,
+ 0x01, 0x00, 0xdb, 0xe6, 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd3, 0xec,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x1e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0xcb, 0xea, 0x19, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xb3, 0xec, 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x26, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xd3, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x20, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x25, 0xe9,
+ 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0x38, 0xe6, 0x0f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb, 0x11, 0x00, 0x38, 0xe6, 0x01, 0x00, 0x18, 0xe6,
+ 0x01, 0x00, 0xb6, 0xe5, 0x01, 0x00, 0x71, 0xec, 0x01, 0x00, 0x29, 0xea, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xd3, 0xec, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x21, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x0c, 0xeb,
+ 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xb3, 0xec, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf4, 0xec,
+ 0x01, 0x00, 0x45, 0xe9, 0x01, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb2, 0xec, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x23, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x09, 0xea, 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x92, 0xec,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf3, 0xec, 0x01, 0x00, 0xa7, 0xe9, 0x18, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8a, 0xea, 0x01, 0x00, 0xdb, 0xe6, 0x0b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x17, 0x00, 0x3c, 0xe7, 0x02, 0x00, 0x92, 0xec, 0x0c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x26, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xfc, 0xe6, 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x46, 0xe9, 0x17, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0xfb, 0xe6, 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb6, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x14, 0xed,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0x05, 0xe9,
+ 0x16, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xea, 0x01, 0x00, 0x1c, 0xe7, 0x09, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xbb, 0xe6,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x2a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x2d, 0xeb, 0x16, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x6e, 0xeb, 0x09, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x2c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf8, 0xe5, 0x01, 0x00, 0x8a, 0xea, 0x15, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf4, 0xec, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x2e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0x08, 0xea, 0x13, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xba, 0xe6, 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x30, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0xa7, 0xe9,
+ 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6e, 0xeb, 0x07, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x31, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0x46, 0xe9, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x59, 0xe6,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x33, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0x4d, 0xeb, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x35, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x25, 0xe9, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x01, 0x00, 0x1c, 0xe7, 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x36, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0x46, 0xe9, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x96, 0xed, 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x37, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x04, 0xe9, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0xfb, 0xe6, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x38, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf0, 0xeb, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0xd7, 0xe5, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x79, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x38, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x46, 0xe9,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0xf4, 0xec, 0x04, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0e, 0x00, 0xe4, 0xe8, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x9a, 0xe6, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x39, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x6e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0x72, 0xec, 0x04, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb7, 0xe5, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0xc6, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xec, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x14, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xfb, 0xe6, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x39, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x14, 0xed, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9, 0x01, 0x00, 0x72, 0xec,
+ 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb6, 0xe5,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x45, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x10, 0xec,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x0f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x39, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd7, 0xe5, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0xd3, 0xec,
+ 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xe8, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6e, 0xeb,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x30, 0xec, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9,
+ 0x0f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x39, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xed, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9,
+ 0x01, 0x00, 0x14, 0xed, 0x04, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xb3, 0xec, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8a, 0xea, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x6a, 0xea, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x0c, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x0f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x39, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf4, 0xec, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0xd7, 0xe5, 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xa7, 0xe9,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf4, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x31, 0xec,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xdb, 0xe6, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x86, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x0f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x39, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xaf, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcf, 0xeb, 0x01, 0x00, 0xdb, 0xe6,
+ 0x05, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea,
+ 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x6e, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec,
+ 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb,
+ 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0f, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x39, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xc7, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x35, 0xed,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x79, 0xe6,
+ 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x66, 0xe9, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x39, 0xe6, 0xc6, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x26, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x46, 0xe9,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf8, 0xe5, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x4d, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xfb, 0xe6, 0x0f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x38, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xe5, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9, 0x01, 0x00, 0xbb, 0xe6,
+ 0x06, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x10, 0xec,
+ 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x35, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9,
+ 0xc7, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x27, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x4d, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb,
+ 0x19, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x05, 0xe9, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xea, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x23, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x6a, 0xea, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xea, 0x08, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x09, 0xea, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xfb, 0xe6,
+ 0x19, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x29, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0xc7, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x27, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xd7, 0xe5, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xd7, 0xe5,
+ 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0xd3, 0xec, 0x21, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf4, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf4, 0xec, 0x08, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb2, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcf, 0xeb, 0x18, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf4, 0xec, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x39, 0xe6, 0xc7, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0x28, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x29, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc8, 0xe9, 0x01, 0x00, 0xfb, 0xe6,
+ 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9,
+ 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0xd3, 0xec, 0x1f, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x39, 0xe6, 0x01, 0x00, 0x45, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9,
+ 0x01, 0x00, 0x1c, 0xe7, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x46, 0xe9,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0xd7, 0xe5, 0x16, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x66, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8b, 0xea,
+ 0xc8, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x28, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0x45, 0xe9, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf4, 0xec, 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0x1c, 0xe7, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6,
+ 0x01, 0x00, 0xa7, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x92, 0xec, 0x0a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x51, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0x9a, 0xe6,
+ 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x4a, 0xea, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf7, 0xe5, 0xc8, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xaf, 0xeb, 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xab, 0xea, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x6e, 0xeb, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0x86, 0xe9,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x96, 0xed, 0x1a, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0x87, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x09, 0xea,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xa7, 0xe9,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x08, 0xea, 0x01, 0x00, 0xba, 0xe6, 0x12, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xcb, 0xea, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb,
+ 0xc9, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x29, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x7a, 0xe6, 0x01, 0x00, 0x46, 0xe9, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0xfb, 0xe6, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x96, 0xed,
+ 0x01, 0x00, 0x66, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x18, 0xe6,
+ 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6,
+ 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x46, 0xe9, 0x03, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0x96, 0xe5, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0x05, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9,
+ 0x01, 0x00, 0xd7, 0xe5, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb6, 0xed, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xc8, 0xe9, 0x01, 0x00, 0x18, 0xe6, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x01, 0x00, 0x6a, 0xea, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0xba, 0xe6,
+ 0xc9, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb,
+ 0x2a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc8, 0xe9,
+ 0x01, 0x00, 0xb6, 0xe5, 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xcf, 0xeb,
+ 0x01, 0x00, 0x04, 0xe9, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x13, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x8e, 0xeb, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x1d, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x72, 0xec, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xdb, 0xe6, 0x16, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x2d, 0xeb, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0x9a, 0xe6, 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xb3, 0xec,
+ 0x01, 0x00, 0xc7, 0xe9, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x30, 0xec, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf0, 0xeb, 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0x72, 0xec,
+ 0x01, 0x00, 0x1c, 0xe7, 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x01, 0x00, 0x86, 0xe9,
+ 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0xca, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x2b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf0, 0xeb,
+ 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x96, 0xed, 0x09, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0x71, 0xec, 0x01, 0x00, 0x86, 0xe9, 0x0f, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x4d, 0xeb, 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x4d, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x46, 0xe9, 0x1d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xba, 0xe6, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x34, 0xed, 0x08, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0xfb, 0xe6,
+ 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x75, 0xed, 0x01, 0x00, 0x6e, 0xeb,
+ 0x01, 0x00, 0x66, 0xe9, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb, 0x10, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xec, 0xea, 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc8, 0xe9, 0x01, 0x00, 0xd3, 0xec,
+ 0x01, 0x00, 0xfb, 0xe6, 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x01, 0x00, 0x6a, 0xea, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x51, 0xec, 0xcb, 0x01, 0x3c, 0xe7,
+ 0x01, 0x00, 0xaf, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xec, 0xea, 0x2c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x6e, 0xeb, 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0x6e, 0xeb,
+ 0x01, 0x00, 0xb2, 0xec, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0xb6, 0xe5,
+ 0x01, 0x00, 0x35, 0xed, 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0x05, 0xe9,
+ 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x1c, 0xe7, 0x14, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xab, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x1c, 0xe7, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xaf, 0xeb, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x18, 0xe6, 0x16, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0x05, 0xe9, 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9,
+ 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0xf4, 0xec,
+ 0x01, 0x00, 0xb7, 0xe5, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0xf3, 0xec, 0x01, 0x00, 0x51, 0xec,
+ 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x05, 0xe9, 0x12, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x1c, 0xe7, 0x10, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x6a, 0xea, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xcb, 0xea,
+ 0x01, 0x00, 0x51, 0xec, 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0xb7, 0xed, 0x01, 0x00, 0xd7, 0xe5,
+ 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x86, 0xe9,
+ 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xaf, 0xeb, 0xcc, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x49, 0xea,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x2d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xcf, 0xeb,
+ 0x29, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0x1c, 0xe7, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x46, 0xe9, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xed, 0x1c, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x29, 0xea, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xb2, 0xec, 0x17, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xcb, 0xea, 0x27, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x1c, 0xe7,
+ 0x12, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfc, 0xe6, 0x01, 0x00, 0xec, 0xea, 0x29, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf0, 0xeb, 0xcc, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x0f, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x76, 0xed, 0x2d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x05, 0xe9,
+ 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf0, 0xeb, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4d, 0xeb, 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x38, 0xe6,
+ 0x0e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4a, 0xea, 0x17, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xb3, 0xec,
+ 0x25, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x71, 0xec, 0x15, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xcf, 0xeb, 0x26, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x46, 0xe9,
+ 0x01, 0x00, 0xb3, 0xec, 0xcd, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x0c, 0xeb, 0x0f, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0x1c, 0xe7, 0x2d, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf8, 0xe5,
+ 0x01, 0x00, 0xe8, 0xe9, 0x23, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x76, 0xed,
+ 0x18, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x29, 0xea, 0x0e, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x05, 0xe9, 0x01, 0x00, 0x38, 0xe6, 0x1a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xec, 0xea,
+ 0x0f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x24, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0xf8, 0xe5, 0x18, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x55, 0xed, 0x01, 0x00, 0x66, 0xe9, 0x22, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9,
+ 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0x1c, 0xe7, 0xcd, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0xd3, 0xec,
+ 0x11, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcf, 0xeb, 0x2e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0x25, 0xe9, 0x1f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x04, 0xe9,
+ 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0xdb, 0xe6, 0x19, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb,
+ 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x09, 0xea, 0x01, 0x00, 0xdb, 0xe6, 0x18, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xb2, 0xec, 0x10, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x79, 0xe6,
+ 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x6a, 0xea, 0x21, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x87, 0xe9,
+ 0x01, 0x00, 0xb2, 0xec, 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x01, 0x00, 0x8e, 0xeb,
+ 0x01, 0x00, 0x04, 0xe9, 0x1f, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6a, 0xea, 0x01, 0x00, 0x18, 0xe6,
+ 0xce, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x71, 0xec, 0x01, 0x00, 0x04, 0xe9, 0x12, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0xfb, 0xe6, 0x2e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0xaf, 0xeb, 0x01, 0x00, 0x86, 0xe9, 0x1b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x39, 0xe6, 0x1b, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x0a, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x8e, 0xeb, 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x59, 0xe6,
+ 0x16, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec, 0x12, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9,
+ 0x01, 0x00, 0xd7, 0xe5, 0x15, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x51, 0xec, 0x1f, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0xb2, 0xec, 0x01, 0x00, 0xfb, 0xe6, 0x1e, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x39, 0xe6, 0x01, 0x00, 0x4d, 0xeb, 0x01, 0x00, 0x05, 0xe9, 0x1b, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0x55, 0xed, 0xce, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7,
+ 0x01, 0x00, 0x34, 0xed, 0x01, 0x00, 0xa7, 0xe9, 0x13, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x45, 0xe9,
+ 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0xfb, 0xe6, 0x2e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x01, 0x00, 0xb2, 0xec, 0x01, 0x00, 0x8a, 0xea, 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9,
+ 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0x59, 0xe6, 0x1c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x09, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfb, 0xe6,
+ 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x45, 0xe9, 0x13, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x6e, 0xeb,
+ 0x01, 0x00, 0x79, 0xe6, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x14, 0xed,
+ 0x01, 0x00, 0x87, 0xe9, 0x13, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x18, 0xe6,
+ 0x14, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x1e, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xab, 0xea,
+ 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0x1c, 0xe7, 0x20, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0x6e, 0xeb, 0x01, 0x00, 0x25, 0xe9, 0x19, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8a, 0xea,
+ 0x01, 0x00, 0x75, 0xed, 0xce, 0x01, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x79, 0xe6,
+ 0x17, 0x00, 0x38, 0xe6, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x1c, 0xe7, 0x30, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x29, 0xea, 0x13, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0xfb, 0xe6,
+ 0x1e, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x08, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x59, 0xe6, 0x17, 0x00, 0x38, 0xe6,
+ 0x01, 0x00, 0xdb, 0xe6, 0x11, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x79, 0xe6,
+ 0x17, 0x00, 0x38, 0xe6, 0x01, 0x00, 0xba, 0xe6, 0x13, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfc, 0xe6,
+ 0x01, 0x00, 0x2d, 0xeb, 0x01, 0x00, 0x46, 0xe9, 0x18, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9,
+ 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0xd3, 0xec, 0x01, 0x00, 0x9a, 0xe6, 0x25, 0x00, 0x3c, 0xe7,
+ 0x01, 0x00, 0xfb, 0xe6, 0x01, 0x00, 0xf4, 0xec, 0x01, 0x00, 0xcb, 0xea, 0x01, 0x00, 0x25, 0xe9,
+ 0x13, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x29, 0xea, 0x01, 0x00, 0x10, 0xec, 0x01, 0x00, 0x79, 0xe6,
+ 0x1e, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6, 0x01, 0x00, 0x14, 0xed, 0x01, 0x00, 0xcf, 0xeb,
+ 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0x87, 0xe9, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0xc8, 0xe9, 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0x31, 0xec, 0x01, 0x00, 0x96, 0xed,
+ 0x01, 0x00, 0x1c, 0xe7, 0x21, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x55, 0xed, 0x62, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x01, 0x00, 0xb3, 0xec, 0x01, 0x00, 0x8e, 0xeb, 0x01, 0x00, 0xab, 0xea, 0x01, 0x00, 0xc8, 0xe9,
+ 0x01, 0x00, 0x25, 0xe9, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x66, 0xe9, 0x01, 0x00, 0x29, 0xea,
+ 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0xf0, 0xeb, 0x01, 0x00, 0xf4, 0xec, 0x01, 0x00, 0x38, 0xe6,
+ 0x2c, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x96, 0xed, 0x01, 0x00, 0x31, 0xec,
+ 0x01, 0x00, 0x0c, 0xeb, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x25, 0xe9, 0x09, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x87, 0xe9, 0x01, 0x00, 0x8a, 0xea, 0x01, 0x00, 0xcf, 0xeb, 0x01, 0x00, 0x14, 0xed,
+ 0x01, 0x00, 0xba, 0xe6, 0x26, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0x1c, 0xe7, 0x01, 0x00, 0x79, 0xe6,
+ 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xd7, 0xe5, 0x02, 0x00, 0x96, 0xed, 0x01, 0x00, 0xd7, 0xe5,
+ 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xba, 0xe6, 0x27, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5,
+ 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed, 0x69, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xfc, 0xe6,
+ 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0xf7, 0xe5,
+ 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0xf7, 0xe5, 0x01, 0x00, 0xf8, 0xe5, 0x01, 0x00, 0x38, 0xe6,
+ 0x01, 0x00, 0x59, 0xe6, 0x01, 0x00, 0xba, 0xe6, 0x39, 0x00, 0x3c, 0xe7, 0x01, 0x00, 0xba, 0xe6,
+ 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0xb6, 0xed, 0x01, 0x00, 0x96, 0xed,
+ 0x01, 0x00, 0xd7, 0xe5, 0x01, 0x00, 0x18, 0xe6, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0x1c, 0xe7,
+ 0x5b, 0x02, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x55, 0xed,
+ 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x75, 0xed,
+ 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x96, 0xe5,
+ 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xf7, 0xe5,
+ 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0d, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x9a, 0xe6,
+ 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xf7, 0xe5, 0x0c, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x05, 0xe9,
+ 0x01, 0x00, 0x1c, 0xe7, 0x11, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xb6, 0xed, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x09, 0xea, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x14, 0xed, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x4d, 0xeb, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x31, 0xec, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xd3, 0xec, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x0d, 0xeb, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x9a, 0xe6, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x08, 0xea, 0x0b, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x6a, 0xea, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xdb, 0xe6, 0x0c, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xf3, 0xec, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x55, 0xed, 0x0b, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x86, 0xe9, 0x01, 0x00, 0x1c, 0xe7, 0x12, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x8e, 0xeb,
+ 0x0b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x72, 0xec, 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x87, 0xe9,
+ 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0x1c, 0xe7, 0x12, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x96, 0xed, 0x0b, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x76, 0xed, 0x13, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x0c, 0xeb, 0x0a, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x8e, 0xeb, 0x13, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x9a, 0xe6, 0x01, 0x00, 0x05, 0xe9, 0x09, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x49, 0xea,
+ 0x01, 0x00, 0x1c, 0xe7, 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xaf, 0xeb, 0x09, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0xc7, 0xe9, 0x01, 0x00, 0xba, 0xe6, 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x9a, 0xe6,
+ 0x01, 0x00, 0x25, 0xe9, 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xa7, 0xe9, 0x01, 0x00, 0x79, 0xe6,
+ 0x13, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x38, 0xe6, 0x01, 0x00, 0x2d, 0xeb, 0x08, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x08, 0xea, 0x01, 0x00, 0x9a, 0xe6, 0x14, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x6a, 0xea,
+ 0x08, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0xdb, 0xe6, 0x14, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x51, 0xec, 0x07, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x25, 0xe9, 0x01, 0x00, 0xb2, 0xec,
+ 0x15, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0xb7, 0xe5, 0x01, 0x00, 0x05, 0xe9, 0x06, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x8b, 0xea, 0x01, 0x00, 0x59, 0xe6, 0x15, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0x66, 0xe9, 0x05, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0xe8, 0xe9, 0x01, 0x00, 0x75, 0xed,
+ 0x16, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x79, 0xe6, 0x01, 0x00, 0xc7, 0xe9, 0x04, 0x00, 0xe4, 0xe8,
+ 0x01, 0x00, 0x49, 0xea, 0x01, 0x00, 0x35, 0xed, 0x17, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x59, 0xe6,
+ 0x01, 0x00, 0xa7, 0xe9, 0x02, 0x00, 0xe4, 0xe8, 0x01, 0x00, 0x4a, 0xea, 0x01, 0x00, 0xb3, 0xec,
+ 0x01, 0x00, 0xf8, 0xe5, 0x18, 0x03, 0x3c, 0xe7, 0x01, 0x00, 0x76, 0xed, 0x01, 0x00, 0xc8, 0xe9,
+ 0x01, 0x00, 0xec, 0xea, 0x01, 0x00, 0x92, 0xec, 0x01, 0x00, 0x9a, 0xe6, 0x1b, 0x03, 0x3c, 0xe7,
+ 0x01, 0x00, 0x59, 0xe6, 0xff, 0xff, 0x3c, 0xe7, 0x9e, 0x75, 0x3c, 0xe7,
+
diff -urNa -x .git original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/mb8ac0300.c u-boot/board/socionext/mb8ac0300eb/mb8ac0300.c
--- original/u-boot-linaro-stable/board/socionext/mb8ac0300eb/mb8ac0300.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/board/socionext/mb8ac0300eb/mb8ac0300.c 2016-08-02 14:19:40.140732320 +0900
@@ -0,0 +1,93 @@
+/*
+ * u-boot/board/fujitsu/mb8ac0300/mb8ac0300.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#include
+#include
+#include
+#include
+#include
+
+extern void lcd_ctrl_init(void *lcd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+static const unsigned char logo_rle[] __attribute__ ((section (".text"))) = {
+#include "initlogo.h"
+};
+
+#define LOAD_OFFSET 0x100
+
+#define SKIP_LINES 50
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ u16 *fb = (void *)0x50000000;
+ u16 *p = &fb[SKIP_LINES * 800];
+ u16 *l = (u16 *)logo_rle;
+ u16 col;
+ int size = ARRAY_SIZE(logo_rle) / 4;
+ u16 n;
+
+ gd->bd->bi_arch_number = MACH_TYPE_MB8AC0300;
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->flags = 0; /* check me */
+
+ while (size-- > 0) {
+ n = *l++;
+ col = *l++;
+
+ while (n--)
+ *p++ = col;
+ }
+
+ flush_dcache_range(fb, &fb[800 * 480]);
+
+ puts("starting lcd\n");
+ lcd_ctrl_init(fb);
+
+/* icache_enable(); */
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+#ifdef CONFIG_DRIVER_FGMAC4
+ /* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+ gd->ram_size = PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE;
+#else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard(void)
+{
+ printf("BOARD: Fujitsu Semiconductor MB8AC0300-EVB\n\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff -urNa -x .git original/u-boot-linaro-stable/boards.cfg u-boot/boards.cfg
--- original/u-boot-linaro-stable/boards.cfg 2016-08-02 12:12:08.984772381 +0900
+++ u-boot/boards.cfg 2016-08-02 14:19:40.163732221 +0900
@@ -283,6 +283,11 @@
ventana arm armv7:arm720t ventana nvidia tegra20
whistler arm armv7:arm720t whistler nvidia tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
+mb8ac0300eb arm armv7 mb8ac0300eb socionext mb8ac0300
+mb86s70 arm armv7 mb86s70 socionext mb86s7x
+mb86s73 arm armv7 mb86s73 socionext mb86s7x
+mb86s72 arm armv7 mb86s72 socionext mb86s7x
+mb86s71 arm armv7 mb86s71 socionext mb86s7x
snowball arm armv7 snowball st-ericsson u8500
kzm9g arm armv7 kzm9g kmc rmobile
armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
diff -urNa -x .git original/u-boot-linaro-stable/common/Makefile u-boot/common/Makefile
--- original/u-boot-linaro-stable/common/Makefile 2016-08-02 12:12:08.984772381 +0900
+++ u-boot/common/Makefile 2016-08-02 14:19:40.533730628 +0900
@@ -59,6 +59,7 @@
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
+COBJS-$(CONFIG_ENV_IS_IN_SCBDEV) += env_scbdev.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
@@ -171,6 +172,9 @@
COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
+ifdef CONFIG_CMD_ROMFS
+COBJS-y += cmd_romfs.o
+endif
# others
ifdef CONFIG_DDR_SPD
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_bdinfo.c u-boot/common/cmd_bdinfo.c
--- original/u-boot-linaro-stable/common/cmd_bdinfo.c 2016-08-02 12:12:08.985772378 +0900
+++ u-boot/common/cmd_bdinfo.c 2016-08-02 14:19:40.534730624 +0900
@@ -361,8 +361,13 @@
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
print_num("DRAM bank", i);
+#if defined(CONFIG_MB86S7X)
+ printf("-> start = 0x%08X_%08X\n", bd->bi_dram[i].start_high, bd->bi_dram[i].start);
+ printf("-> size = 0x%08X_%08X\n", bd->bi_dram[i].size_high, bd->bi_dram[i].size);
+#else
print_num("-> start", bd->bi_dram[i].start);
print_num("-> size", bd->bi_dram[i].size);
+#endif
}
#if defined(CONFIG_CMD_NET)
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_bootm.c u-boot/common/cmd_bootm.c
--- original/u-boot-linaro-stable/common/cmd_bootm.c 2016-08-02 12:12:08.985772378 +0900
+++ u-boot/common/cmd_bootm.c 2016-08-02 14:19:40.923728950 +0900
@@ -87,14 +87,16 @@
static void fixup_silent_linux(void);
#endif
-static image_header_t *image_get_kernel(ulong img_addr, int verify);
#if defined(CONFIG_FIT)
static int fit_check_kernel(const void *fit, int os_noffset, int verify);
#endif
+#if !defined(BOOTM_DIRECT_START_LINUX)
+static image_header_t *image_get_kernel(ulong img_addr, int verify);
static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[], bootm_headers_t *images,
ulong *os_data, ulong *os_len);
+#endif
/*
* Continue booting an OS image; caller already has:
@@ -192,7 +194,6 @@
static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- void *os_hdr;
int ret;
memset((void *)&images, 0, sizeof(images));
@@ -202,6 +203,16 @@
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start");
+#if defined(BOOTM_DIRECT_START_LINUX)
+ images.os.os = IH_OS_LINUX;
+ images.os.type = IH_TYPE_KERNEL;
+ if (argc < 2)
+ images.ep = load_addr;
+ else
+ images.ep = simple_strtoul(argv[1], NULL, 16);
+#else
+ void *os_hdr;
+
/* get kernel image header, start address and length */
os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
&images, &images.os.image_start, &images.os.image_len);
@@ -279,7 +290,7 @@
images.os.load = images.os.image_start;
images.ep += images.os.load;
}
-
+#endif
if (((images.os.type == IH_TYPE_KERNEL) ||
(images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
(images.os.type == IH_TYPE_MULTI)) &&
@@ -305,7 +316,9 @@
#endif
}
+#if !defined(BOOTM_DIRECT_START_LINUX)
images.os.start = (ulong)os_hdr;
+#endif
images.state = BOOTM_STATE_START;
return 0;
@@ -328,6 +341,10 @@
int ret;
#endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */
+#ifdef BOOTM_DIRECT_START_LINUX
+ return 0;
+#endif
+
const char *type_name = genimg_get_type_name(os.type);
switch (comp) {
@@ -515,9 +532,10 @@
ret = bootm_load_os(images.os, &load_end, 0);
if (ret)
return ret;
-
+#if !defined(BOOTM_DIRECT_START_LINUX)
lmb_reserve(&images.lmb, images.os.load,
(load_end - images.os.load));
+#endif
break;
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
case BOOTM_STATE_RAMDISK:
@@ -773,6 +791,7 @@
* pointer to a legacy image header if valid image was found
* otherwise return NULL
*/
+#if !defined(BOOTM_DIRECT_START_LINUX)
static image_header_t *image_get_kernel(ulong img_addr, int verify)
{
image_header_t *hdr = (image_header_t *)img_addr;
@@ -811,6 +830,7 @@
}
return hdr;
}
+#endif
/**
* fit_check_kernel - verify FIT format kernel subimage
@@ -872,6 +892,7 @@
* pointer to image header if valid image was found, plus kernel start
* address and length, otherwise NULL
*/
+#if !defined(BOOTM_DIRECT_START_LINUX)
static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[], bootm_headers_t *images, ulong *os_data,
ulong *os_len)
@@ -1042,6 +1063,7 @@
return (void *)img_addr;
}
+#endif
#ifdef CONFIG_SYS_LONGHELP
static char bootm_help_text[] =
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_elf.c u-boot/common/cmd_elf.c
--- original/u-boot-linaro-stable/common/cmd_elf.c 2016-08-02 12:12:08.986772374 +0900
+++ u-boot/common/cmd_elf.c 2016-08-02 14:19:40.926728937 +0900
@@ -362,8 +362,10 @@
"\t or via section headers (-s)"
);
+#ifdef CONFIG_CMD_BOOTVX
U_BOOT_CMD(
bootvx, 2, 0, do_bootvx,
"Boot vxWorks from an ELF image",
" [address] - load address of vxWorks ELF image."
);
+#endif /* CONFIG_CMD_BOOTVX */
\ ファイル末尾ã«æ”¹è¡ŒãŒã‚ã‚Šã¾ã›ã‚“
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_flash.c u-boot/common/cmd_flash.c
--- original/u-boot-linaro-stable/common/cmd_flash.c 2016-08-02 12:12:08.987772371 +0900
+++ u-boot/common/cmd_flash.c 2016-08-02 14:19:40.928728928 +0900
@@ -301,6 +301,9 @@
#ifndef CONFIG_SYS_NO_FLASH
if (argc == 1) { /* print info for all FLASH banks */
+#ifdef CONFIG_FLASH_CHIP_SELECT
+ printf ("\nFlash Chip #%i", get_chip_select());
+#endif
for (bank=0; bank
#endif
#include
+#include
+
static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
@@ -45,6 +47,10 @@
static ulong base_address = 0;
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+extern int read_flash_buff (uchar *dest, ulong addr, ulong cnt);
+#endif
+
/* Memory Display
*
* Syntax:
@@ -132,7 +138,24 @@
}
} while (nbytes > 0);
} else
-# endif
+# elif defined(CONFIG_FLASH_CMD_FOR_SF)
+ if (addr2info(addr)) {
+ uchar linebuf[DISP_LINE_LEN];
+ ulong linebytes, nbytes = length * size;
+ do {
+ linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+ read_flash_buff(linebuf, addr,linebytes);
+ print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size);
+
+ nbytes -= linebytes;
+ addr += linebytes;
+ if (ctrlc()) {
+ rc = 1;
+ break;
+ }
+ } while (nbytes > 0);
+ } else
+#endif
{
/* Print the lines. */
@@ -350,6 +373,16 @@
}
#ifndef CONFIG_SYS_NO_FLASH
+
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+ uchar *data = NULL;
+ if (addr2info(addr) != NULL) {
+ data = malloc(size);
+ read_flash_buff(data, addr, count*size);
+ addr = (ulong)data;
+ }
+#endif
+
/* check if we are copying to Flash */
if ( (addr2info(dest) != NULL)
#ifdef CONFIG_HAS_DATAFLASH
@@ -361,6 +394,10 @@
puts ("Copy to Flash... ");
rc = flash_write ((char *)addr, dest, count*size);
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+ if(data)
+ free(data);
+#endif
if (rc != 0) {
flash_perror (rc);
return (1);
@@ -447,6 +484,7 @@
return 0;
}
+#ifdef CONFIG_CMD_LOOP
static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
@@ -515,6 +553,7 @@
*cp++;
}
}
+#endif /* CONFIG_CMD_LOOP */
#ifdef CONFIG_LOOPW
int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -1210,11 +1249,13 @@
"base off\n - set address offset for memory commands to 'off'"
);
+#ifdef CONFIG_CMD_LOOP
U_BOOT_CMD(
loop, 3, 1, do_mem_loop,
"infinite loop on address range",
"[.b, .w, .l] address number_of_objects"
);
+#endif /* CONFIG_CMD_LOOP */
#ifdef CONFIG_LOOPW
U_BOOT_CMD(
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_mmc.c u-boot/common/cmd_mmc.c
--- original/u-boot-linaro-stable/common/cmd_mmc.c 2016-08-02 12:12:08.990772360 +0900
+++ u-boot/common/cmd_mmc.c 2016-08-02 14:19:40.934728903 +0900
@@ -25,6 +25,8 @@
#include
#include
+extern int mmc_part_bootenable(int dev_num, unsigned int part_num);
+
static int curr_device = -1;
#ifndef CONFIG_GENERIC_MMC
int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -170,6 +172,8 @@
printf("no mmc device at slot %x\n", curr_device);
return 1;
}
+ if (mmc->has_init)
+ mmc_reset(mmc);
mmc->has_init = 0;
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_nvedit.c u-boot/common/cmd_nvedit.c
--- original/u-boot-linaro-stable/common/cmd_nvedit.c 2016-08-02 12:12:08.990772360 +0900
+++ u-boot/common/cmd_nvedit.c 2016-08-02 14:19:40.935728898 +0900
@@ -66,6 +66,7 @@
!defined(CONFIG_ENV_IS_IN_ONENAND) && \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
!defined(CONFIG_ENV_IS_IN_REMOTE) && \
+ !defined(CONFIG_ENV_IS_IN_SCBDEV) && \
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
SPI_FLASH|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_pxe.c u-boot/common/cmd_pxe.c
--- original/u-boot-linaro-stable/common/cmd_pxe.c 2016-08-02 13:33:42.658023493 +0900
+++ u-boot/common/cmd_pxe.c 2016-08-02 14:19:40.937728890 +0900
@@ -711,10 +711,11 @@
if (bootm_argv[3])
bootm_argc = 4;
+ do_bootm(NULL, 0, bootm_argc, bootm_argv);
+
#ifdef CONFIG_CMD_BOOTZ
+ /* Try booting a zImage if do_bootm returns */
do_bootz(NULL, 0, bootm_argc, bootm_argv);
-#else
- do_bootm(NULL, 0, bootm_argc, bootm_argv);
#endif
return 1;
}
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_romfs.c u-boot/common/cmd_romfs.c
--- original/u-boot-linaro-stable/common/cmd_romfs.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/common/cmd_romfs.c 2016-08-02 14:19:40.937728890 +0900
@@ -0,0 +1,60 @@
+/*
+ * u-boot/common/cmd_romfs.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+
+int do_romfsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ void *romfs = NULL;
+ char *filepath = NULL;
+ unsigned int addr = 0x0;
+ unsigned int maxsize = 1024 * 1024 * 100;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ /* parse the parameters: offset, addr, file name, max size */
+ romfs = (void *)simple_strtoul(argv[1], NULL, 16);
+ addr = simple_strtoul(argv[2], NULL, 16);
+ filepath = argv[3];
+
+ if (argc >= 5)
+ maxsize = simple_strtoul(argv[4], NULL, 16);
+
+ if (romfs_mount(romfs)) {
+ printf("Fail to mount romfs\n");
+ return 1;
+ }
+
+ if (romfs_filesystem_read(filepath, (void *)addr, maxsize) < 1) {
+ printf("Fail to find the file\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ romfsload, 4, 0, do_romfsload,
+ "load binary file from a rom filesystem",
+ "[offset] [addr] [filename] \n"
+ " - load binary file 'filename' which max size 'size' from romfs at physical address 'offset'\n"
+ " to address 'addr'\n"
+);
diff -urNa -x .git original/u-boot-linaro-stable/common/cmd_ximg.c u-boot/common/cmd_ximg.c
--- original/u-boot-linaro-stable/common/cmd_ximg.c 2016-08-02 12:12:08.993772350 +0900
+++ u-boot/common/cmd_ximg.c 2016-08-02 14:19:40.940728877 +0900
@@ -24,6 +24,7 @@
* MA 02111-1307 USA
*/
+#ifdef CONFIG_CMD_IMXTRACT
/*
* Multi Image extract
@@ -280,3 +281,4 @@
imxtract, 4, 1, do_imgextract,
"extract a part of a multi-image", imgextract_help_text
);
+#endif /* CONFIG_CMD_IMXTRACT */
\ ファイル末尾ã«æ”¹è¡ŒãŒã‚ã‚Šã¾ã›ã‚“
diff -urNa -x .git original/u-boot-linaro-stable/common/env_flash.c u-boot/common/env_flash.c
--- original/u-boot-linaro-stable/common/env_flash.c 2016-08-02 12:12:08.995772342 +0900
+++ u-boot/common/env_flash.c 2016-08-02 14:19:40.944728860 +0900
@@ -230,11 +230,13 @@
int env_init(void)
{
+#if !defined(CONFIG_SKIP_FLASH_PROBE)
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr = (ulong)&(env_ptr->data);
gd->env_valid = 1;
return 0;
}
+#endif
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 0;
diff -urNa -x .git original/u-boot-linaro-stable/common/env_scbdev.c u-boot/common/env_scbdev.c
--- original/u-boot-linaro-stable/common/env_scbdev.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/common/env_scbdev.c 2016-08-02 14:19:40.945728856 +0900
@@ -0,0 +1,108 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mtd_info *mtd;
+env_t *env_ptr;
+char *env_name_spec = "HSSPI NOR";
+
+extern int scb_mtd_init(void);
+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES];
+
+static int init_scb_dev(void)
+{
+ int err;
+ int i;
+
+ for (i = 0; i < MAX_MTD_DEVICES; i++) {
+ mtd_table[i] = NULL;
+ }
+
+ err = scb_mtd_init();
+ if(err) {
+ printf("scb_mtd_init fail\n");
+ goto fail;
+ }
+
+ /* find the mtd device */
+ mtd = get_mtd_device_nm("scb_stroage");
+ if(mtd == NULL) {
+ printf("fail to find scb device\n");
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+
+ return -1;
+}
+
+static int read_env(struct mtd_info *mtd, void *buf)
+{
+ size_t len;
+ int ret;
+ if(mtd == NULL)
+ return -1;
+ ret = mtd->read(mtd, 0, CONFIG_ENV_SIZE, &len, buf);
+ return ret;
+}
+
+int env_init(void)
+{
+ /* let env_relocate_spec get the environment */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+int saveenv(void)
+{
+ size_t len;
+ env_t env_new;
+ char *res = (char *)&env_new.data;
+
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+
+ if(mtd == NULL)
+ return -1;
+
+ struct erase_info instr;
+
+ instr.addr = 0;
+ instr.len = CONFIG_ENV_SIZE;
+ instr.callback = NULL;
+
+ if(!mtd->erase(mtd, &instr)) {
+ return mtd->write(mtd, 0, CONFIG_ENV_SIZE, &len, (unsigned char *)&env_new);
+ }
+
+ return -1;
+}
+#endif /* CMD_SAVEENV */
+
+void env_relocate_spec(void)
+{
+ int err;
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+ /* read environment from scb block dev */
+ err = init_scb_dev();
+ if(!err) {
+ err = read_env(mtd, (void *)buf);
+ }
+
+ if(err)
+ memcpy(buf, &default_environment[0], CONFIG_ENV_SIZE);
+
+ env_import((char *)buf, 1);
+}
diff -urNa -x .git original/u-boot-linaro-stable/common/usb_hub.c u-boot/common/usb_hub.c
--- original/u-boot-linaro-stable/common/usb_hub.c 2016-08-02 12:12:08.999772328 +0900
+++ u-boot/common/usb_hub.c 2016-08-02 14:19:40.968728757 +0900
@@ -120,8 +120,8 @@
USB_HUB_PRINTF("port %d returns %lX\n", i + 1, dev->status);
}
- /* Wait at least 100 msec for power to become stable */
- mdelay(max(pgood_delay, (unsigned)100));
+ /* Wait at least 1000 msec for power to become stable */
+ mdelay(max(pgood_delay, (unsigned)1000));
}
void usb_hub_reset(void)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mmc/Makefile u-boot/drivers/mmc/Makefile
--- original/u-boot-linaro-stable/drivers/mmc/Makefile 2016-08-02 12:12:09.023772243 +0900
+++ u-boot/drivers/mmc/Makefile 2016-08-02 14:19:41.008728585 +0900
@@ -48,6 +48,7 @@
COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS-$(CONFIG_DWMMC) += dw_mmc.o
COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+COBJS-$(CONFIG_F_SDH30_SDHCI) += f_sdh30_sdhci.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mmc/f_sdh30_sdhci.c u-boot/drivers/mmc/f_sdh30_sdhci.c
--- original/u-boot-linaro-stable/drivers/mmc/f_sdh30_sdhci.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/mmc/f_sdh30_sdhci.c 2016-08-02 14:19:41.009728580 +0900
@@ -0,0 +1,70 @@
+/*
+ * u-boot/drivers/mmc/f_sdh30_sdhci.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+
+extern int mmc_go_idle(struct mmc* mmc);
+
+int f_sdh30_sdhci_init(int regbase, int tmclk, int max_clk, int min_clk, int quirks)
+{
+ int ret = 0;
+ struct sdhci_host *host = NULL;
+
+ host = (struct sdhci_host *)malloc(sizeof (struct sdhci_host));
+ if (!host) {
+ printf("sdhci_host malloc fail!\n");
+ return -1;
+ }
+
+ host->name = "f_sdh30_sdhci";
+ host->ioaddr = (void *)regbase;
+ host->quirks = quirks;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->host_caps = MMC_MODE_BUS_WIDTH_TEST;
+
+ ret = add_sdhci(host, max_clk, min_clk);
+ if (ret == 0) {
+ host->mmc->tm_clock = tmclk;
+ }
+
+ return ret;
+}
+
+void f_sdh30_reset(void)
+{
+ struct mmc *mmc;
+ int dev_num, i;
+
+ dev_num = get_mmc_num();
+ if (dev_num < 0) {
+ printf("No MMC device available\n");
+ return;
+ }
+
+ for (i = 0; i < dev_num; i++) {
+ mmc = find_mmc_device(i);
+ if (mmc && mmc->has_init) {
+ mmc_go_idle(mmc);
+ sdhci_writeb((struct sdhci_host *)mmc->priv,
+ 0, SDHCI_POWER_CONTROL);
+ }
+ }
+}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mmc/mmc.c u-boot/drivers/mmc/mmc.c
--- original/u-boot-linaro-stable/drivers/mmc/mmc.c 2016-08-02 12:12:09.024772239 +0900
+++ u-boot/drivers/mmc/mmc.c 2016-08-02 14:19:41.010728576 +0900
@@ -26,17 +26,28 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif
+static const unsigned int taac_exp[] = {
+ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
+};
+
+static const unsigned int taac_mant[] = {
+ 0, 10, 12, 13, 15, 20, 25, 30,
+ 35, 40, 45, 50, 55, 60, 70, 80,
+};
+
static struct list_head mmc_devices;
static int cur_dev_num = -1;
@@ -242,6 +253,12 @@
if (!mmc)
return -1;
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* If mmc card is read only, return 0 means here erase nothing */
+ if (mmc->state & MMC_STATE_READONLY)
+ return 0;
+#endif
if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
printf("\n\nCaution! Your devices Erase group is 0x%x\n"
@@ -306,12 +323,22 @@
* token, not a STOP_TRANSMISSION request.
*/
if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
- cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
- cmd.cmdarg = 0;
- cmd.resp_type = MMC_RSP_R1b;
- if (mmc_send_cmd(mmc, &cmd, NULL)) {
- printf("mmc fail to send stop cmd\n");
- return 0;
+ int stop = 1;
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+ if (host->quirks & SDHCI_QUIRK_AUTO_CMD12)
+ stop = 0;
+ else if (host->quirks & SDHCI_QUIRK_AUTO_CMD23)
+ if (!IS_SD(mmc) || (mmc->scr[0] & 0x02))
+ stop = 0;
+
+ if (stop) {
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+ if (mmc_send_cmd(mmc, &cmd, NULL)) {
+ printf("mmc fail to send stop cmd\n");
+ return 0;
+ }
}
}
@@ -331,6 +358,12 @@
if (!mmc)
return 0;
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* If mmc card is read only, return 0 means here write nothing */
+ if (mmc->state & MMC_STATE_READONLY)
+ return 0;
+#endif
+
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
@@ -373,12 +406,22 @@
return 0;
if (blkcnt > 1) {
- cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
- cmd.cmdarg = 0;
- cmd.resp_type = MMC_RSP_R1b;
- if (mmc_send_cmd(mmc, &cmd, NULL)) {
- printf("mmc fail to send stop cmd\n");
- return 0;
+ int stop = 1;
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+ if (host->quirks & SDHCI_QUIRK_AUTO_CMD12)
+ stop = 0;
+ else if (host->quirks & SDHCI_QUIRK_AUTO_CMD23)
+ if (!IS_SD(mmc) || (mmc->scr[0] & 0x02))
+ stop = 0;
+
+ if (stop) {
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+ if (mmc_send_cmd(mmc, &cmd, NULL)) {
+ printf("mmc fail to send stop cmd\n");
+ return 0;
+ }
}
}
@@ -417,7 +460,7 @@
return blkcnt;
}
-static int mmc_go_idle(struct mmc *mmc)
+int mmc_go_idle(struct mmc *mmc)
{
struct mmc_cmd cmd;
int err;
@@ -507,7 +550,14 @@
{
int timeout = 10000;
struct mmc_cmd cmd;
- int err;
+ int err, bit;
+ uint voltages = mmc->voltages;
+
+ bit = ffs(voltages) - 1;
+ if (bit)
+ voltages &= 3 << bit;
+ else
+ voltages = 0;
/* Some cards seem to need this */
mmc_go_idle(mmc);
@@ -528,9 +578,14 @@
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = (mmc_host_is_spi(mmc) ? 0 :
- (mmc->voltages &
+ (voltages &
(cmd.response[0] & OCR_VOLTAGE_MASK)) |
(cmd.response[0] & OCR_ACCESS_MODE));
+ /*FIXME: right now we have to use sector access mode or the emmc won't work */
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* set for sector access mode for emmc */
+ cmd.cmdarg |= 0x40000000;
+#endif
if (mmc->host_caps & MMC_MODE_HC)
cmd.cmdarg |= OCR_HCS;
@@ -561,7 +616,7 @@
mmc->ocr = cmd.response[0];
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
- mmc->rca = 0;
+ mmc->rca = 2;
return 0;
}
@@ -599,7 +654,8 @@
cmd.resp_type = MMC_RSP_R1b;
cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
(index << 16) |
- (value << 8);
+ (value << 8) |
+ set;
ret = mmc_send_cmd(mmc, &cmd, NULL);
@@ -631,7 +687,13 @@
if (err)
return err;
- cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+ cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
+
+ /* HS200 is supported */
+ if (cardtype & EXT_CSD_CARD_TYPE_HS200) {
+ mmc->card_caps |= MMC_MODE_HS200;
+ return 0;
+ }
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
@@ -649,7 +711,7 @@
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
- if (cardtype & MMC_HS_52MHZ)
+ if (cardtype & EXT_CSD_CARD_TYPE_52)
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
else
mmc->card_caps |= MMC_MODE_HS;
@@ -880,11 +942,125 @@
mmc_set_ios(mmc);
}
+
+/*
+ * Selects the desired buswidth and switch to the HS200 mode
+ * if bus width set without error
+ */
+static int mmc_select_hs200(struct mmc *mmc)
+{
+ int err = 0;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
+
+ if (mmc->set_signal_voltage)
+ err = mmc->set_signal_voltage(mmc, MMC_SELECT_VDD_180);
+
+ /* If fails try again during next card power cycle */
+ if (err)
+ goto err;
+
+ /* switch to HS200 mode if bus width set successfully */
+ if (!err)
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_HS_TIMING, 2);
+
+ /* check if the setting is correct */
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (!err && ext_csd[EXT_CSD_HS_TIMING] != 2) {
+ mmc->card_caps &= ~MMC_MODE_HS200;
+ }
+
+err:
+ return err;
+}
+
+static int mmc_send_bus_test(struct mmc *mmc, u8 opcode, u8 len)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ u8 *test_buf;
+ int i, err;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, testdata_8bit, 8);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, testdata_4bit, 4);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, len);
+ memset(testdata_8bit, 0, 8);
+ memset(testdata_4bit, 0, 4);
+ memset(data_buf, 0, len);
+
+ testdata_8bit[0] = 0x55; testdata_8bit[1] = 0xaa;
+ testdata_4bit[0] = 0x5a;
+
+ /* dma onto stack is unsafe/nonportable, but callers to this
+ * routine normally provide temporary on-stack buffers ...
+ */
+ if (len == 8)
+ test_buf = testdata_8bit;
+ else if (len == 4)
+ test_buf = testdata_4bit;
+ else {
+ printf("Invalid bus_width %d\n", len);
+ return -EINVAL;
+ }
+
+ if (opcode == MMC_CMD_BUS_TEST_W)
+ memcpy(data_buf, test_buf, len);
+
+ cmd.cmdidx = opcode;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ data.dest = (char *)data_buf;
+ data.blocksize = len;
+ data.blocks = 1;
+ if (opcode == MMC_CMD_BUS_TEST_R)
+ data.flags = MMC_DATA_READ;
+ else
+ data.flags = MMC_DATA_WRITE;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+ if (err)
+ return err;
+
+ err = 0;
+ if (opcode == MMC_CMD_BUS_TEST_R) {
+ for (i = 0; i < len / 4; i++)
+ if ((test_buf[i] ^ data_buf[i]) != 0xff) {
+ err = -EIO;
+ break;
+ }
+ }
+
+ return err;
+}
+
+int mmc_bus_test(struct mmc *mmc, u8 bus_width)
+{
+ int err, width;
+
+ if (bus_width == (MMC_MODE_8BIT >> MMC_MODE_WIDTH_BITS_SHIFT))
+ width = 8;
+ else if (bus_width == (MMC_MODE_4BIT >> MMC_MODE_WIDTH_BITS_SHIFT))
+ width = 4;
+ else if (bus_width == 0)
+ return 0; /* no need for test */
+ else
+ return -EINVAL;
+
+ /*
+ * Ignore errors from BUS_TEST_W. BUS_TEST_R will fail if there
+ * is a problem. This improves chances that the test will work.
+ */
+ mmc_send_bus_test(mmc, MMC_CMD_BUS_TEST_W, width);
+ err = mmc_send_bus_test(mmc, MMC_CMD_BUS_TEST_R, width);
+ return err;
+}
+
static int mmc_startup(struct mmc *mmc)
{
int err, width;
uint mult, freq;
u64 cmult, csize, capacity;
+ int e,m;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512);
@@ -1065,6 +1241,11 @@
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
}
+ e = CSD_TAAC(mmc) & 0x07;
+ m = (CSD_TAAC(mmc) & 0x78) >> 3;
+ mmc->taac_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
+ mmc->nsac_clock = CSD_NSAC(mmc) * 100;
+
if (IS_SD(mmc))
err = sd_change_freq(mmc);
else
@@ -1101,8 +1282,13 @@
else
mmc->tran_speed = 25000000;
} else {
- width = ((mmc->host_caps & MMC_MODE_MASK_WIDTH_BITS) >>
- MMC_MODE_WIDTH_BITS_SHIFT);
+ if (mmc->host_caps & MMC_MODE_8BIT)
+ width = MMC_MODE_8BIT >> MMC_MODE_WIDTH_BITS_SHIFT;
+ else if (mmc->host_caps & MMC_MODE_4BIT)
+ width = MMC_MODE_4BIT >> MMC_MODE_WIDTH_BITS_SHIFT;
+ else
+ width = 0;
+
for (; width >= 0; width--) {
/* Set the card to use 4 bit*/
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
@@ -1115,22 +1301,31 @@
mmc_set_bus_width(mmc, 1);
break;
} else
- mmc_set_bus_width(mmc, 4 * width);
+ mmc_set_bus_width(mmc, 4 * width);
- err = mmc_send_ext_csd(mmc, test_csd);
- if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
- == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
- && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
- == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
- && ext_csd[EXT_CSD_REV] \
- == test_csd[EXT_CSD_REV]
- && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
- == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
- &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
+ if (!(mmc->host_caps & MMC_MODE_BUS_WIDTH_TEST)) {
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
+ && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
+ == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
+ && ext_csd[EXT_CSD_REV] \
+ == test_csd[EXT_CSD_REV]
+ && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
+
+ mmc->card_caps |= width << MMC_MODE_WIDTH_BITS_SHIFT;
+ break;
+ }
+ } else {
+ err = mmc_bus_test(mmc, width);
+ if (!err) {
+ mmc->card_caps |= width << MMC_MODE_WIDTH_BITS_SHIFT;
+ break;
+ }
- mmc->card_caps |= width;
- break;
}
}
@@ -1142,8 +1337,32 @@
}
}
+ /* support for HS200 mode */
+ if (mmc->card_caps & MMC_MODE_HS200) {
+ err = mmc_select_hs200(mmc);
+
+ if (err)
+ return err;
+
+ mmc->tran_speed = 200000000;
+ mmc->timing = MMC_TIMING_MMC_HS200;
+ mmc_set_ios(mmc);
+ }
+
mmc_set_clock(mmc, mmc->tran_speed);
+ /* execute tuning for HS200 mode */
+ if (mmc->card_caps & MMC_MODE_HS200) {
+ u32 tuning_cmdidx;
+ if (IS_SD(mmc))
+ tuning_cmdidx = MMC_CMD_SEND_TUNING_BLOCK;
+ else
+ tuning_cmdidx = MMC_CMD_SEND_TUNING_BLOCK_HS200;
+ if (mmc->execute_tuning)
+ mmc->execute_tuning(mmc, tuning_cmdidx);
+ }
+
+
/* fill in device description */
mmc->block_dev.lun = 0;
mmc->block_dev.type = 0;
@@ -1216,6 +1435,14 @@
}
#endif
+int mmc_reset(struct mmc *mmc)
+{
+ if(mmc->reset)
+ return mmc->reset(mmc);
+
+ return 0;
+}
+
int mmc_init(struct mmc *mmc)
{
int err;
@@ -1229,6 +1456,8 @@
if (mmc->has_init)
return 0;
+ mmc->timing = 0;
+
err = mmc->init(mmc);
if (err)
@@ -1267,6 +1496,7 @@
mmc->has_init = 0;
else
mmc->has_init = 1;
+
return err;
}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mmc/sdhci.c u-boot/drivers/mmc/sdhci.c
--- original/u-boot-linaro-stable/drivers/mmc/sdhci.c 2016-08-02 12:12:09.025772236 +0900
+++ u-boot/drivers/mmc/sdhci.c 2016-08-02 14:19:41.011728572 +0900
@@ -31,6 +31,128 @@
void *aligned_buffer;
+#ifdef DEBUG
+static void sdhci_dumpregs(struct sdhci_host *host)
+{
+ printf(": =========== REGISTER DUMP (%s)===========\n",
+ host->name);
+
+ printf( ": Sys addr: 0x%08x | Version: 0x%08x\n",
+ sdhci_readl(host, SDHCI_DMA_ADDRESS),
+ sdhci_readw(host, SDHCI_HOST_VERSION));
+ printf( ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
+ sdhci_readw(host, SDHCI_BLOCK_SIZE),
+ sdhci_readw(host, SDHCI_BLOCK_COUNT));
+ printf( ": Argument: 0x%08x | Trn mode: 0x%08x\n",
+ sdhci_readl(host, SDHCI_ARGUMENT),
+ sdhci_readw(host, SDHCI_TRANSFER_MODE));
+ printf( ": Present: 0x%08x | Host ctl: 0x%08x\n",
+ sdhci_readl(host, SDHCI_PRESENT_STATE),
+ sdhci_readb(host, SDHCI_HOST_CONTROL));
+ printf( ": Power: 0x%08x | Blk gap: 0x%08x\n",
+ sdhci_readb(host, SDHCI_POWER_CONTROL),
+ sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
+ printf( ": Wake-up: 0x%08x | Clock: 0x%08x\n",
+ sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
+ sdhci_readw(host, SDHCI_CLOCK_CONTROL));
+ printf( ": Timeout: 0x%08x | Int stat: 0x%08x\n",
+ sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
+ sdhci_readl(host, SDHCI_INT_STATUS));
+ printf( ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
+ sdhci_readl(host, SDHCI_INT_ENABLE),
+ sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
+ printf( ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
+ sdhci_readw(host, SDHCI_ACMD12_ERR),
+ sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
+ printf( ": Caps: 0x%08x | Caps_1: 0x%08x\n",
+ sdhci_readl(host, SDHCI_CAPABILITIES),
+ sdhci_readl(host, SDHCI_CAPABILITIES_1));
+ printf( ": Cmd: 0x%08x | Max curr: 0x%08x\n",
+ sdhci_readw(host, SDHCI_COMMAND),
+ sdhci_readl(host, SDHCI_MAX_CURRENT));
+ printf( ": Host ctl2: 0x%08x\n",
+ sdhci_readw(host, SDHCI_HOST_CONTROL2));
+
+// if (host->flags & SDHCI_USE_ADMA)
+// printf( ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
+// readl(host->ioaddr + SDHCI_ADMA_ERROR),
+// readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
+
+ printf( ": ===========================================\n");
+}
+#endif
+
+static unsigned int sdhci_calc_timeout(struct mmc *mmc)
+{
+ int div = 0;
+ unsigned long timeout;
+ u64 current_time;
+
+ timeout = 10 * mmc->taac_ns;
+ if (mmc->clock)
+ timeout += 10 * mmc->nsac_clock / mmc->clock;
+
+ current_time = 1000000000 / mmc->tm_clock * (1 << 13);
+ while (current_time < timeout) {
+ div++;
+ current_time <<= 1;
+ if (div >= 0xe)
+ break;
+ }
+
+ return div;
+}
+
+#ifdef CONFIG_MMC_ADMA
+static unsigned int sdhci_adma_table_pre(struct mmc *mmc, struct mmc_data *data, unsigned int start_addr)
+{
+ struct adma_descriptor {
+ unsigned int attr;
+ unsigned int addr;
+ };
+
+ int i = 0;
+ unsigned int total;
+ unsigned int offset;
+ struct adma_descriptor *table;
+
+ if (data->blocks == 0)
+ return 0;
+
+ total = data->blocks * data->blocksize;
+ offset = 0;
+
+ table = malloc((total / 0x10000 + 1) * sizeof(struct adma_descriptor));
+ if (table == NULL)
+ return 0;
+
+ while (offset < total) {
+ unsigned int size = total - offset;
+ if (size >= 0x10000)
+ size = 0x10000;
+
+ table[i].addr = start_addr + offset;
+ table[i].attr = (size << 16) | 0x21;
+
+ offset += size;
+ i++;
+ }
+
+ table[i - 1].attr |= 0x2;
+
+ /* cache write */
+ flush_cache((unsigned long)table, i * sizeof(struct adma_descriptor));
+
+ return (unsigned int)table;
+}
+
+static void sdhci_adma_table_post(unsigned int adma_table)
+{
+ if (adma_table != 0)
+ free((void *)adma_table);
+}
+#endif
+
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
@@ -79,24 +201,17 @@
}
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
- unsigned int start_addr)
+ unsigned int start_addr, struct mmc_cmd *cmd)
{
- unsigned int stat, rdy, mask, timeout, block = 0;
-#ifdef CONFIG_MMC_SDMA
- unsigned char ctrl;
- ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
- ctrl &= ~SDHCI_CTRL_DMA_MASK;
- ctrl |= SDHCI_CTRL_SDMA;
- sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
-#endif
+ unsigned int stat, rdy, mask, block = 0, timeout = 10000;
- timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- printf("Error detected in status(0x%X)!\n", stat);
+ if (cmd->cmdidx != MMC_CMD_BUS_TEST_W)
+ printf("Error detected in status(0x%X)!\n", stat);
return -1;
}
if (stat & rdy) {
@@ -105,8 +220,42 @@
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
+#ifdef CONFIG_F_SDH30_SDHCI
+ /*
+ * It's potential that the SDHCI_INT_DATA_END bit
+ * is not set when the real transfer data is completed.
+ * We check the SDHCI_INT_DATA_END is set before quit.
+ */
+ if (++block >= data->blocks) {
+ unsigned int timeout_cnt = 10000;
+ while (1) {
+ stat = sdhci_readl(host,
+ SDHCI_INT_STATUS);
+ if (stat & SDHCI_INT_ERROR) {
+ printf("Error detected "
+ "in status(0x%X)!\n",
+ stat);
+ return -1;
+ }
+
+ if (stat & SDHCI_INT_DATA_END)
+ break;
+
+ /* kind of paranoia for checking */
+ if (timeout_cnt-- > 0)
+ udelay(10);
+ else {
+ printf("Transfer data "
+ "timeout\n");
+ return -1;
+ }
+ }
+ break;
+ }
+#else
if (++block >= data->blocks)
break;
+#endif
}
#ifdef CONFIG_MMC_SDMA
if (stat & SDHCI_INT_DMA_END) {
@@ -116,12 +265,14 @@
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
- if (timeout-- > 0)
- udelay(10);
- else {
- printf("Transfer data timeout\n");
- return -1;
+ if (timeout == 0) {
+ printf("Timeout waiting for hardware interrupt.\n");
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ sdhci_reset(host, SDHCI_RESET_DATA);
+ return TIMEOUT;
}
+ timeout--;
+ udelay(1000);
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
@@ -136,6 +287,9 @@
u32 mask, flags, mode;
unsigned int timeout, start_addr = 0;
unsigned int retry = 10000;
+#ifdef CONFIG_MMC_ADMA
+ unsigned int adma_table = 0;
+#endif
/* Wait max 10 ms */
timeout = 10;
@@ -175,18 +329,44 @@
if (data)
flags |= SDHCI_CMD_DATA;
+ /* CMD19 is special in that the Data Present Select should be set */
+ if ((IS_SD(mmc) && cmd->cmdidx== MMC_CMD_SEND_TUNING_BLOCK) ||
+ cmd->cmdidx== MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+ flags |= SDHCI_CMD_DATA;
+ mask = SDHCI_INT_DATA_AVAIL;
+ }
+
/*Set Transfer mode regarding to data flag*/
if (data != 0) {
- sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
+ int div;
+
+ div = sdhci_calc_timeout(mmc);
+ sdhci_writeb(host, div, SDHCI_TIMEOUT_CONTROL);
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ mode = 0;
+#else
mode = SDHCI_TRNS_BLK_CNT_EN;
+#endif
trans_bytes = data->blocks * data->blocksize;
- if (data->blocks > 1)
+ if (data->blocks > 1) {
mode |= SDHCI_TRNS_MULTI;
+ mode |= SDHCI_TRNS_BLK_CNT_EN;
+
+ if (host->quirks & SDHCI_QUIRK_AUTO_CMD23) {
+ if (!IS_SD(mmc) || mmc->scr[0] & 0x2) {
+ mode |= SDHCI_TRNS_ACMD23;
+ sdhci_writel(host, data->blocks, SDHCI_ARGUMENT2);
+ }
+ } else if (host->quirks & SDHCI_QUIRK_AUTO_CMD12) {
+ mode |= SDHCI_TRNS_ACMD12;
+ }
+ }
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDMA
+#if defined(CONFIG_MMC_SDMA) || defined(CONFIG_MMC_ADMA)
if (data->flags == MMC_DATA_READ)
start_addr = (unsigned int)data->dest;
else
@@ -199,9 +379,22 @@
memcpy(aligned_buffer, data->src, trans_bytes);
}
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
mode |= SDHCI_TRNS_DMA;
+
+#ifdef CONFIG_MMC_ADMA
+ unsigned int ctrl;
+ ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ ctrl |= SDHCI_CTRL_ADMA32;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+
+ adma_table = sdhci_adma_table_pre(mmc, data, start_addr);
+ sdhci_writel(host, adma_table, SDHCI_ADMA_ADDRESS);
+#else
+ sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
#endif
+#endif
+
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blocksize),
SDHCI_BLOCK_SIZE);
@@ -210,7 +403,7 @@
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDMA
+#if defined(CONFIG_MMC_SDMA) || defined(CONFIG_MMC_ADMA)
flush_cache(start_addr, trans_bytes);
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
@@ -218,11 +411,12 @@
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR)
break;
- if (--retry == 0)
- break;
} while ((stat & mask) != mask);
if (retry == 0) {
+#ifdef CONFIG_MMC_ADMA
+ sdhci_adma_table_post(adma_table);
+#endif
if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
return 0;
else {
@@ -238,10 +432,14 @@
ret = -1;
if (!ret && data)
- ret = sdhci_transfer_data(host, data, start_addr);
+ ret = sdhci_transfer_data(host, data, start_addr, cmd);
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
- udelay(1000);
+ udelay(2000);
+
+#ifdef CONFIG_MMC_ADMA
+ sdhci_adma_table_post(adma_table);
+#endif
stat = sdhci_readl(host, SDHCI_INT_STATUS);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
@@ -345,6 +543,167 @@
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
+#ifdef CONFIG_F_SDH30_SDHCI
+void sdhci_voltage_switch(struct sdhci_host *host)
+{
+ u32 ctrl = 0;
+
+ udelay(2500);
+ ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
+ ctrl |= F_SDH30_CRES_O_DN;
+ sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
+ ctrl |= F_SDH30_MSEL_O_1_8;
+ sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
+
+ ctrl &= ~F_SDH30_CRES_O_DN;
+ sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
+ udelay(2500);
+}
+#endif
+
+int sdhci_set_signal_voltage(struct mmc *mmc, int voltage)
+{
+ u16 ctrl;
+ u16 en_low_voltage = 0;
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (voltage) {
+ case MMC_SELECT_VDD_180:
+ ctrl |= MMC_SELECT_VDD_180;
+ en_low_voltage = MMC_SELECT_VDD_180;
+ break;
+ case MMC_SELECT_VDD_330:
+ ctrl &= ~MMC_SELECT_VDD_180;
+ en_low_voltage = 0;
+ break;
+ default:
+ return -2;
+ break;
+ }
+
+
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* Some controller need to do more when switching */
+ sdhci_voltage_switch(host);
+#endif
+
+ /* Wait for 5ms */
+ udelay(5000);
+
+ /* 1.8V or 3.3V regulator output should be stable within 5 ms */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if ((ctrl & SDHCI_CTRL_VDD_180) == en_low_voltage)
+ return 0;
+
+ return -1;
+}
+
+#define MAX_TUNING_LOOP 40
+
+static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode)
+{
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+ u16 ctrl;
+ int tuning_loop_counter = MAX_TUNING_LOOP;
+ unsigned long timeout;
+ int err = 0;
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* hack for s73 */
+ u32 vendor_ctrl;
+ vendor_ctrl = sdhci_readl(host,SDHCI_VENDOR_CTRL);
+ vendor_ctrl |= 0x01000000;
+ sdhci_writel(host, vendor_ctrl, SDHCI_VENDOR_CTRL);
+
+ /* tuning setting: disable CMD conflict */
+ vendor_ctrl = sdhci_readl(host,SDHCI_TUNING_SETTING);
+ vendor_ctrl |= 0x00010000;
+ sdhci_writel(host, vendor_ctrl, SDHCI_TUNING_SETTING);
+#endif
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* workaround for tuning process */
+ ctrl |= SDHCI_CTRL_TUNED_CLK;
+#endif
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /*
+ * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches 40 times or a timeout of 150ms occurs.
+ */
+ timeout = 150;
+ do {
+ struct mmc_cmd cmd;
+
+ if (!tuning_loop_counter && !timeout)
+ break;
+
+ cmd.cmdidx = opcode;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1 | R1_APP_CMD;
+
+ /*
+ * In response to CMD19, the card sends 64 bytes of tuning
+ * block to the Host Controller. So we set the block size
+ * to 64 here.
+ */
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->bus_width == 8)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
+ SDHCI_BLOCK_SIZE);
+ else if (mmc->bus_width == 4)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ } else {
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ }
+
+ /*
+ * The tuning block is sent by the card to the host controller.
+ * So we set the TRNS_READ bit in the Transfer Mode register.
+ * This also takes care of setting DMA Enable and Multi Block
+ * Select in the same register to 0.
+ */
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ err = sdhci_send_command(mmc, &cmd, NULL);
+ if (err) {
+ printf("send tuning command fail:0x%x\n", err);
+ return err;
+ }
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ tuning_loop_counter--;
+ timeout--;
+ mdelay(1);
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ /*
+ * The Host Driver has exhausted the maximum number of loops allowed,
+ * so use fixed sampling frequency.
+ */
+ if (!tuning_loop_counter || !timeout) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ } else {
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ printf("tuning timeout\n");
+ err = -5;
+ }
+ }
+
+ return err;
+}
+
+
void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
@@ -379,7 +738,51 @@
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
ctrl &= ~SDHCI_CTRL_HISPD;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ if (host->version >= SDHCI_SPEC_300) {
+ u16 clk, ctrl_2;
+
+ /* In case of UHS-I modes, set High Speed Enable */
+ if (mmc->timing == MMC_TIMING_MMC_HS200)
+ ctrl |= SDHCI_CTRL_HISPD;
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /* Reset SD Clock Enable */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (mmc->timing == MMC_TIMING_MMC_HS200)
+ ctrl_2 |= SDHCI_CTRL_HS_SDR200;
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+ /* Re-enable SD Clock */
+ clk &= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+ sdhci_set_clock(mmc, mmc->clock);
+
+ } else
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+int sdhci_sw_reset(struct mmc *mmc)
+{
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+
+ sdhci_reset(host, SDHCI_RESET_ALL);
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* use vendor register to reset for emmc, sd has no effect doing this. */
+ sdhci_writel(host, 0x2, SDHCI_VENDOR_CTRL);
+#endif
+
+ return 0;
}
int sdhci_init(struct mmc *mmc)
@@ -396,6 +799,15 @@
sdhci_set_power(host, fls(mmc->voltages) - 1);
+#ifdef CONFIG_F_SDH30_SDHCI
+ /*
+ * Reference to Part1 Physical Layer Simplified Specification Ver 3.01
+ * 6.4.1 Power Up
+ * This delay must be at least 74 clock sizes, or 1 ms.
+ */
+ udelay(1000);
+#endif
+
if (host->quirks & SDHCI_QUIRK_NO_CD) {
unsigned int status;
@@ -435,6 +847,12 @@
mmc->set_ios = sdhci_set_ios;
mmc->init = sdhci_init;
mmc->getcd = NULL;
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* not sure if needed for other host controller */
+ mmc->reset = sdhci_sw_reset;
+#endif
+ mmc->set_signal_voltage = sdhci_set_signal_voltage;
+ mmc->execute_tuning = sdhci_execute_tuning;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
@@ -443,6 +861,12 @@
return -1;
}
#endif
+#ifdef CONFIG_MMU_ADMA
+ if (!(caps & SDHCI_CAN_DO_ADMA2)) {
+ printf("Your controller don't support adma!!\n");
+ return -1;
+ }
+#endif
if (max_clk)
mmc->f_max = max_clk;
@@ -479,13 +903,23 @@
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
mmc->voltages |= host->voltages;
- mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | MMC_MODE_HS200;
if (caps & SDHCI_CAN_DO_8BIT)
mmc->host_caps |= MMC_MODE_8BIT;
if (host->host_caps)
mmc->host_caps |= host->host_caps;
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* before we reset, host clock should be set first */
+ mmc_set_clock(mmc, mmc->f_min);
+#endif
sdhci_reset(host, SDHCI_RESET_ALL);
+
+#ifdef CONFIG_F_SDH30_SDHCI
+ /* use vendor register to reset for emmc, sd has no effect doing this. */
+ sdhci_writel(host, 0x2, SDHCI_VENDOR_CTRL);
+#endif
+
mmc_register(mmc);
return 0;
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mtd/Makefile u-boot/drivers/mtd/Makefile
--- original/u-boot-linaro-stable/drivers/mtd/Makefile 2016-08-02 12:12:09.025772236 +0900
+++ u-boot/drivers/mtd/Makefile 2016-08-02 14:19:41.023728520 +0900
@@ -36,6 +36,7 @@
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
COBJS-$(CONFIG_ST_SMI) += st_smi.o
+#COBJS-$(CONFIG_SCB_STORAGE) += scb_mtd.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mtd/scb_mtd.c u-boot/drivers/mtd/scb_mtd.c
--- original/u-boot-linaro-stable/drivers/mtd/scb_mtd.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/mtd/scb_mtd.c 2016-08-02 14:19:41.053728391 +0900
@@ -0,0 +1,298 @@
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PAGE_SHIFT 12
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
+
+#define KERNEL_SECTOR_SIZE 512
+
+struct mb86s70_scb_dev {
+ unsigned long total_kernel_sectors; /* Device size in kernel blocks */
+ unsigned long total_hard_sectors; /* Device size in SCB blocks */
+ unsigned long total_hard_bytes; /* Device size in SCB bytes */
+ unsigned long erase_sector_size;
+ struct mtd_info mtd;
+ struct mtd_partition *parts;
+ unsigned int num_parts;
+};
+
+static struct mb86s70_scb_dev scb_dev;
+static char scb_mtd_names[16];
+
+static int scb_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+#if 0
+ size_t from = instr->addr;
+ size_t len = instr->len;
+ int ret = 0;
+ struct cmd_stg_block_erase *s;
+
+ if (from >= scb_dev.total_hard_bytes)
+ return -EINVAL;
+
+ if (from + len > scb_dev.total_hard_bytes)
+ len = scb_dev.total_hard_bytes - from;
+
+ instr->state = MTD_ERASING;
+
+ while (len) {
+ s = cmd_to_scb;
+ s->payload_size = sizeof(*s);
+ s->sector = from / SCB_SECTOR_SIZE;
+
+ ret = mhu_send(CMD_STG_BLOCK_ERASE_REQ);
+ if (ret < 0) {
+ printf("erase cmd failed!\n");
+ return ret;
+ }
+
+ s = rsp_from_scb;
+
+ if (len > scb_dev.erase_sector_size)
+ len -= scb_dev.erase_sector_size;
+ else
+ len = 0;
+
+ if (s->result) {
+ printf("erase sector %d failed, result:%x\n", s->sector, s->result);
+ instr->state = MTD_ERASE_FAILED;
+ ret = 1;
+ goto bail;
+ }
+
+ from += scb_dev.erase_sector_size;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+ ret = 0;
+
+bail:
+ mtd_erase_callback(instr);
+
+ return ret;
+#endif
+ return 0;
+}
+
+static int scb_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+#if 0
+ struct cmd_stg_block_read *r;
+ int ret;
+ u32 initial_offset;
+
+ if (from >= scb_dev.total_hard_bytes)
+ return -EINVAL;
+
+ if (from + len > scb_dev.total_hard_bytes)
+ len = scb_dev.total_hard_bytes - from;
+
+ if (retlen)
+ *retlen = len;
+
+ initial_offset = from % SCB_SECTOR_SIZE;
+
+ while (len) {
+ r = cmd_to_scb;
+ r->payload_size = sizeof(*r);
+ r->sector = from / SCB_SECTOR_SIZE;
+ r->result = 1;
+
+ memcpy(r->data, buf, SCB_SECTOR_SIZE);
+
+ ret = mhu_send(CMD_STG_BLOCK_READ_REQ);
+ if (ret < 0) {
+ printf("read cmd failed, ret:0x%x\n", ret);
+ goto bail;
+ }
+
+ r = rsp_from_scb;
+
+ if (r->result) {
+ printf("read failed at %d-byte sector %d\n",
+ SCB_SECTOR_SIZE, r->sector);
+ goto bail;
+ }
+
+
+ memcpy(buf, r->data + initial_offset,
+ len > SCB_SECTOR_SIZE ? SCB_SECTOR_SIZE : len);
+ initial_offset = 0;
+
+ from += SCB_SECTOR_SIZE;
+ if (len >= SCB_SECTOR_SIZE)
+ len -= SCB_SECTOR_SIZE;
+ else
+ len = 0;
+ buf += SCB_SECTOR_SIZE;
+ }
+
+ return 0;
+
+bail:
+ if (retlen)
+ *retlen -= len;
+
+ return ret;
+#endif
+ return 0;
+}
+
+static int scb_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+#if 0
+ struct cmd_stg_block_write *w;
+ int ret;
+
+ if (to >= scb_dev.total_hard_bytes)
+ return -EINVAL;
+
+ if (to + len > scb_dev.total_hard_bytes)
+ len = scb_dev.total_hard_bytes - to;
+
+
+ if (retlen)
+ *retlen = len;
+
+ while (len) {
+ w = cmd_to_scb;
+ w->payload_size = sizeof(*w);
+ w->sector = to / SCB_SECTOR_SIZE;
+ w->result = 1;
+
+ memcpy(w->data, buf, SCB_SECTOR_SIZE);
+
+ ret = mhu_send(CMD_STG_BLOCK_WRITE_REQ);
+ if (ret < 0) {
+ printf("write cmd failed\n");
+ goto bail;
+ }
+
+ w = rsp_from_scb;
+
+ if (w->result) {
+ printf("write failed at %d-byte sector %d\n",
+ SCB_SECTOR_SIZE, w->sector);
+ goto bail;
+ }
+
+
+ to += SCB_SECTOR_SIZE;
+ if (len >= SCB_SECTOR_SIZE)
+ len -= SCB_SECTOR_SIZE;
+ else
+ len = 0;
+ buf += SCB_SECTOR_SIZE;
+ }
+
+ return 0;
+
+bail:
+ if (retlen)
+ *retlen -= len;
+
+ return ret;
+#endif
+ return 0;
+}
+
+static void scb_mtd_sync(struct mtd_info *mtd)
+{
+ /* Not Implemented */
+}
+
+static int scb_mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ /* Not Implemented */
+ return 0;
+}
+
+static int scb_mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ /* Not Implemented */
+ return 0;
+}
+
+#define SCB_DEV_MIN_SUPPORTED_VER 0x509
+
+static int
+mb86s70_scb_get_mtd_info(struct mb86s70_scb_dev *priv)
+{
+ unsigned long erase, stg;
+ struct cmd_stg_get_size *s;
+ int ret;
+ u32 version;
+
+ version = get_scb_version();
+ if(version < SCB_DEV_MIN_SUPPORTED_VER) {
+ printf("Cannot access stroage!\n");
+ return -1;
+ }
+
+ s = cmd_to_scb;
+ s->payload_size = sizeof(*s);
+ ret = mhu_send(CMD_STG_GET_SIZE_REQ);
+ if (ret < 0) {
+ printf("%s:%d failed!\n", __func__, __LINE__);
+ return ret;
+ }
+
+ s = rsp_from_scb;
+
+ erase = s->erase_block_size_bytes;
+ stg = s->count_sectors;
+
+ priv->erase_sector_size = erase;
+ /* force usable storage to erase sector alignment */
+ stg = ((((stg * SCB_SECTOR_SIZE) / erase) * erase) & PAGE_MASK) /
+ SCB_SECTOR_SIZE;
+ /* use as many kernel sectors as will fit */
+ priv->total_kernel_sectors = ((stg * SCB_SECTOR_SIZE) & PAGE_MASK) /
+ KERNEL_SECTOR_SIZE;
+ priv->total_hard_bytes = priv->total_kernel_sectors *
+ KERNEL_SECTOR_SIZE;
+ /* express the kernel sectors as scb sectors (128 byte) */
+ priv->total_hard_sectors = priv->total_hard_bytes / SCB_SECTOR_SIZE;
+
+ return 0;
+}
+
+int scb_mtd_init(void)
+{
+ struct mtd_info *mtd;
+
+ mtd = &scb_dev.mtd;
+
+ mb86s70_scb_get_mtd_info(&scb_dev);
+
+ sprintf(scb_mtd_names, "scb_stroage");
+ mtd->name = scb_mtd_names;
+ mtd->type = MTD_NORFLASH;
+ mtd->flags = MTD_CAP_NORFLASH;
+ mtd->size = scb_dev.total_hard_bytes;
+ mtd->erasesize = scb_dev.erase_sector_size;
+ mtd->writesize = KERNEL_SECTOR_SIZE;
+ mtd->erase = scb_mtd_erase;
+ mtd->read = scb_mtd_read;
+ mtd->write = scb_mtd_write;
+ mtd->sync = scb_mtd_sync;
+ mtd->lock = scb_mtd_lock;
+ mtd->unlock = scb_mtd_unlock;
+ mtd->priv = &scb_dev;
+
+ if (add_mtd_device(mtd))
+ return -ENOMEM;
+
+ return 0;
+}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mtd/spi/spi_flash.c u-boot/drivers/mtd/spi/spi_flash.c
--- original/u-boot-linaro-stable/drivers/mtd/spi/spi_flash.c 2016-08-02 12:12:09.032772211 +0900
+++ u-boot/drivers/mtd/spi/spi_flash.c 2016-08-02 14:19:41.054728387 +0900
@@ -14,13 +14,21 @@
#include
#include "spi_flash_internal.h"
+static int ref_count = 0;
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(u32 addr, u8 *cmd, u32 addr_size)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ if (addr_size == 4) {
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+ cmd[3] = addr >> 8;
+ cmd[4] = addr >> 0;
+ } else {
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+ }
}
static int spi_flash_read_write(struct spi_slave *spi,
@@ -65,13 +73,47 @@
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
+static int read_rfsr(struct spi_flash *flash)
+{
+ ssize_t retval;
+ u8 code = 0x70;
+ u8 val;
+
+ retval = spi_flash_cmd_read(flash->spi, &code, 1, &val, 1);
+
+ if (retval < 0) {
+ return retval;
+ }
+
+ return val;
+}
+
+static int wait_rfs_ready(struct spi_flash *flash)
+{
+ unsigned int timeout = 1000;
+ int sr;
+
+ do {
+ if ((sr = read_rfsr(flash)) < 0)
+ break;
+ else if (sr & 0x80)
+ return 0;
+
+ mdelay(10);
+ timeout--;
+
+ } while (timeout > 0);
+
+ return 1;
+}
+
int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4];
+ u8 cmd[5];
page_size = flash->page_size;
page_addr = offset / page_size;
@@ -87,11 +129,13 @@
for (actual = 0; actual < len; actual += chunk_len) {
chunk_len = min(len - actual, page_size - byte_addr);
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
+ spi_flash_addr(offset + actual, cmd, flash->address_len);
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ if (flash->address_len == 4)
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
+ else
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
ret = spi_flash_cmd_write_enable(flash);
@@ -100,7 +144,7 @@
break;
}
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ ret = spi_flash_cmd_write(flash->spi, cmd, flash->address_len + 1,
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
@@ -111,6 +155,12 @@
if (ret)
break;
+#ifdef CONFIG_QUIRK_N25Q512A
+ ret = wait_rfs_ready(flash);
+ if (ret)
+ break;
+#endif
+
page_addr++;
byte_addr = 0;
}
@@ -129,22 +179,48 @@
int ret;
spi_claim_bus(spi);
- ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
spi_release_bus(spi);
return ret;
}
+#define BUFF_SIZE 65536
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ int ret = 0;
u8 cmd[5];
-
cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ u8 output[BUFF_SIZE];
+ u8 *tmp = output;
+ u8 *data_in = (u8 *)data;
+ u32 next_offset = offset;
+ size_t remain_size = len;
+ size_t copy_size;
+
+ while (remain_size > 0) {
+ if (remain_size + flash->dummy_read / 8 <= BUFF_SIZE)
+ copy_size = remain_size + flash->dummy_read / 8;
+ else
+ copy_size = BUFF_SIZE;
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+ spi_flash_addr(next_offset, cmd, flash->address_len);
+ ret = spi_flash_read_common(flash, cmd, flash->address_len + 1, tmp, copy_size);
+ if (ret)
+ break;
+
+ copy_size -= (flash->dummy_read / 8);
+ next_offset += copy_size;
+ remain_size -= copy_size;
+
+ /* discard the dummy bytes */
+ tmp += (flash->dummy_read / 8);
+ memcpy(data_in, tmp, copy_size);
+ data_in += copy_size;
+ }
+
+ return ret;
}
int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
@@ -194,7 +270,7 @@
{
u32 start, end, erase_size;
int ret;
- u8 cmd[4];
+ u8 cmd[5];
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -216,23 +292,32 @@
end = start + len;
while (offset < end) {
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(offset, cmd, flash->address_len);
offset += erase_size;
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], offset);
+ if (flash->address_len == 4)
+ debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], cmd[4], offset);
+ else
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
goto out;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_cmd_write(flash->spi, cmd, flash->address_len + 1, NULL, 0);
if (ret)
goto out;
ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
if (ret)
goto out;
+#ifdef CONFIG_QUIRK_N25Q512A
+ ret = wait_rfs_ready(flash);
+ if (ret)
+ goto out;
+#endif
}
debug("SF: Successfully erased %zu bytes @ %#x\n", len, start);
@@ -269,6 +354,32 @@
return 0;
}
+#define CMD_EN_4BYTE 0xB7
+#define CMD_DIS_4BYTE 0xE9
+
+int spi_set_4byte_mode(struct spi_flash *flash, int en)
+{
+ u8 cmd;
+ int ret;
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ cmd = en ? CMD_EN_4BYTE : CMD_DIS_4BYTE;
+ ret = spi_flash_cmd_write(flash->spi, &cmd, 1, NULL, 0);
+ if (ret) {
+ debug("SF: fail to set address mode\n");
+ return ret;
+ }
+
+ flash->address_len = en ? 4 : 3;
+
+ return 0;
+}
+
/*
* The following table holds all device probe functions
*
@@ -385,24 +496,94 @@
goto err_manufacturer_probe;
}
+ /* Don't print these to keep the print board info format*/
+#ifndef CONFIG_FLASH_CMD_FOR_SF
printf("SF: Detected %s with page size ", flash->name);
print_size(flash->sector_size, ", total ");
print_size(flash->size, "\n");
+#endif
spi_release_bus(spi);
+ ref_count++;
+
return flash;
err_manufacturer_probe:
err_read_id:
spi_release_bus(spi);
err_claim_bus:
- spi_free_slave(spi);
+ //spi_free_slave(spi);
return NULL;
}
void spi_flash_free(struct spi_flash *flash)
{
+ ref_count--;
+ if (ref_count <= 0 && flash->address_len == 4)
+ spi_set_4byte_mode(flash, 0);
spi_free_slave(flash->spi);
free(flash);
}
+
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+int spi_read_lock_status(struct spi_flash *flash, u32 offset, u8 *lock)
+{
+ int ret;;
+ u8 cmd[4];
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret)
+ return -1;
+
+ /* send read lock status command */
+ cmd[0] = 0xE8;
+ spi_flash_addr(offset, cmd, flash->address_len);
+ ret = spi_flash_cmd_read(flash->spi, cmd, sizeof(cmd), lock, 1);
+ if (ret)
+ debug("Fail to read loc status register.\n");
+
+ /* wait for completion */
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret)
+ return ret;
+#ifdef CONFIG_QUIRK_N25Q512A
+ ret = wait_rfs_ready(flash);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+
+}
+
+int spi_write_lock_status(struct spi_flash *flash, u32 offset, u8 lock)
+{
+ int ret;
+ u8 cmd[5];
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret)
+ return -1;
+
+ /* send write lock status command */
+ cmd[0] = 0xE5;
+ spi_flash_addr(offset, cmd, flash->address_len);
+ cmd[4] = lock;
+ ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
+ if (ret)
+ debug("fail to write lock status register.\n");
+
+ /* wait for completion */
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret)
+ return ret;
+#ifdef CONFIG_QUIRK_N25Q512A
+ ret = wait_rfs_ready(flash);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_FLASH_CMD_FOR_SF */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/mtd/spi/stmicro.c u-boot/drivers/mtd/spi/stmicro.c
--- original/u-boot-linaro-stable/drivers/mtd/spi/stmicro.c 2016-08-02 12:12:09.032772211 +0900
+++ u-boot/drivers/mtd/spi/stmicro.c 2016-08-02 14:19:41.054728387 +0900
@@ -105,6 +105,13 @@
.name = "N25Q128A",
},
{
+ .id = 0xbb20,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "N25Q512A",
+ },
+
+ {
.id = 0xba19,
.pages_per_sector = 256,
.nr_sectors = 512,
@@ -112,6 +119,27 @@
},
};
+static int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ u8 cmd[5];
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ if (flash->address_len == 4) {
+ cmd[1] = offset >> 24;
+ cmd[2] = offset >> 16;
+ cmd[3] = offset >> 8;
+ cmd[4] = offset >> 0;
+ } else {
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset >> 0;
+ }
+
+ return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+}
+
+
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
{
const struct stmicro_spi_flash_params *params;
@@ -154,13 +182,27 @@
flash->spi = spi;
flash->name = params->name;
+ flash->address_len = 3;
+
+ /* n25q512a needs special handle */
+ if(params->id == 0xbb20) {
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = spi_flash_cmd_erase;
+ flash->read = spi_flash_cmd_read_slow;
+ spi_set_4byte_mode(flash, 1);
+ flash->dummy_read = 0;
+ } else {
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = spi_flash_cmd_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->dummy_read = 8;
+ }
- flash->write = spi_flash_cmd_write_multi;
- flash->erase = spi_flash_cmd_erase;
- flash->read = spi_flash_cmd_read_fast;
flash->page_size = 256;
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
+ if (params->nr_sectors > CONFIG_SYS_MAX_FLASH_SECT)
+ flash->size = flash->sector_size * CONFIG_SYS_MAX_FLASH_SECT;
return flash;
}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/Makefile u-boot/drivers/net/Makefile
--- original/u-boot-linaro-stable/drivers/net/Makefile 2016-08-02 12:12:09.035772200 +0900
+++ u-boot/drivers/net/Makefile 2016-08-02 14:19:41.058728370 +0900
@@ -80,6 +80,8 @@
COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
+COBJS-$(CONFIG_DRIVER_FGMAC4) += fgmac4.o
+COBJS-$(CONFIG_DRIVER_OGMA) += ogma.o ogma_basic_access.o ogma_gmac_access.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/fgmac4.c u-boot/drivers/net/fgmac4.c
--- original/u-boot-linaro-stable/drivers/net/fgmac4.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/fgmac4.c 2016-08-02 14:19:41.065728339 +0900
@@ -0,0 +1,1051 @@
+/*
+ * u-boot/drivers/net/fgmac4.c
+ *
+ * Copyright (C) 2010-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "fgmac4.h"
+
+#define FGMAC4_CLK CONFIG_FGMAC4_SYS_CLK/1000000 /* SYS_CLK 125MHz *//* H_CLK */
+
+#define READ_REG(r) readl((volatile u32 *)(FGMAC4_BASE + r))
+#define WRITE_REG(val,r) writel(val, (volatile u32 *)(FGMAC4_BASE + r))
+
+#define ETH_ZLEN 60
+
+
+/* MAX size of TX&RX size */
+/* frame(1500)+EthernetHeader(14)+FCS(4)+NET_IP_ALIGN(2) */
+#define BUFFER_SIZE 1536 /* 32 * 48 */
+
+#define FGMAC4_TDESC_NUM 10
+#define FGMAC4_RDESC_NUM 10
+
+/* RX and TX descriptor number */
+#define FGMAC4_DESC_NUM (FGMAC4_TDESC_NUM + FGMAC4_RDESC_NUM)
+
+/* Size of descriptor spaces */
+#define FGMAC4_DESC_BYTES ((sizeof(struct fgmac4_desc) * FGMAC4_DESC_NUM))
+
+/* After reset device, have to wait 2000ns before access the register */
+#define DELAY_TIME 2 /* 2us = 2000ns */
+
+/* wait counter */
+#define WAIT_COUNT 1000
+#define ANEG_WAIT_COUNT (500*1000)
+
+/* MAX address of 32 PHYs */
+#define MAX_PHY_ADR 31
+
+/* we use upper 1MB non-cached region for fgmac4's tx/rx buffers */
+#define FGMAC4_BUF_BASE (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - CONFIG_FGMAC4_BUF_SIZE)
+
+/* Define the RX/TX Descriptor ring */
+static u8 *fgmac4_ring = (u8 *)FGMAC4_BUF_BASE;
+static u8 *fgmac4_buf = (u8 *)(FGMAC4_BUF_BASE + FGMAC4_DESC_BYTES);
+
+static struct eth_info fgmac4_info;
+
+/* Generic MII registers. */
+
+#ifndef MII_CTRL1000
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#endif /* MII_CTRL1000 */
+#ifndef MII_STAT1000
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#endif /* MII_STAT1000 */
+
+/* 1000BASE-T Control register */
+#ifndef ADVERTISE_1000FULL
+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
+#endif /* ADVERTISE_1000FULL */
+#ifndef ADVERTISE_1000HALF
+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
+#endif /* ADVERTISE_1000HALF */
+
+/* 1000BASE-T Status register */
+#ifndef LPA_1000FULL
+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex*/
+#endif /* LPA_1000FULL */
+#ifndef LPA_1000HALF
+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex*/
+#endif /* LPA_1000HALF */
+
+/* Enable or disable autonegotiation. If this is set to enable,
+ * the forced link modes above are completely ignored.
+ */
+#ifndef AUTONEG_DISABLE
+#define AUTONEG_DISABLE 0x00
+#endif /* AUTONEG_DISABLE */
+#ifndef AUTONEG_ENABLE
+#define AUTONEG_ENABLE 0x01
+#endif /* AUTONEG_ENABLE */
+
+/* Indicates what features are advertised by the interface. */
+#ifndef ADVERTISED_10baseT_Half
+#define ADVERTISED_10baseT_Half (1 << 0)
+#endif /* ADVERTISED_10baseT_Half */
+#ifndef ADVERTISED_10baseT_Full
+#define ADVERTISED_10baseT_Full (1 << 1)
+#endif /* ADVERTISED_10baseT_Full */
+#ifndef ADVERTISED_100baseT_Half
+#define ADVERTISED_100baseT_Half (1 << 2)
+#endif /* ADVERTISED_100baseT_Half */
+#ifndef ADVERTISED_100baseT_Full
+#define ADVERTISED_100baseT_Full (1 << 3)
+#endif /* ADVERTISED_100baseT_Full */
+#ifndef ADVERTISED_1000baseT_Half
+#define ADVERTISED_1000baseT_Half (1 << 4)
+#endif /* ADVERTISED_1000baseT_Half */
+#ifndef ADVERTISED_1000baseT_Full
+#define ADVERTISED_1000baseT_Full (1 << 5)
+#endif /* ADVERTISED_1000baseT_Full */
+
+/* The forced speed, 10Mb, 100Mb, Gigabit. */
+#ifndef SPEED_10
+#define SPEED_10 10
+#endif /* SPEED_10 */
+#ifndef SPEED_100
+#define SPEED_100 100
+#endif /* SPEED_100 */
+#ifndef SPEED_1000
+#define SPEED_1000 1000
+#endif /* SPEED_1000 */
+
+/* Duplex, half or full. */
+#ifndef DUPLEX_HALF
+#define DUPLEX_HALF 0x00
+#endif /* DUPLEX_HALF */
+#ifndef DUPLEX_FULL
+#define DUPLEX_FULL 0x01
+#endif /* DUPLEX_FULL */
+
+
+/*
+ * fgmac4_phy_wait -- confirm that PHY is not busy
+ *
+ * Description: In this function, the driver will confirm whether PHY is
+ * not busy. If PHY does not become free in time, the driver will send
+ * warning message to user and continue.
+ */
+static int fgmac4_phy_wait(void)
+{
+ u32 wtime; /* waiting time */
+ u32 val;
+
+ /* confirm that PHY is not busy befor write/read GAR and GDR.
+ * We set a waitingtime, if PHY does not become free in time,
+ * we will send warning message to user and continue.
+ */
+ wtime = WAIT_COUNT;
+ while (wtime--) {
+ val = READ_REG(FGMAC4_REG_GAR);
+ if (!(val & FGMAC4_GAR_GB))
+ return 0;
+ udelay(DELAY_TIME);
+ }
+
+ printf("PHY is busy!\n");
+ return 1;
+}
+
+/*
+ * fgmac4_phy_read -- read PHY's register
+ * @phy_addr: the id of phy. range:0-31
+ * @reg_addr: phy register address
+ * @read_val: read value from PHY register
+ *
+ * Description: read PHY's register by setting FGMAC4's GAR register and
+ * GDR register.
+ */
+static int fgmac4_phy_read(u16 phy_addr, u16 reg_addr, u32 *read_val)
+{
+ int wval, ret;
+
+ /* Set the GAR register */
+ wval = (phy_addr << FGMAC4_GAR_PA_SHIFT)
+ | ((reg_addr & FGMAC4_GAR_GR_MASK) << FGMAC4_GAR_GR_SHIFT)
+ | FGMAC4_GAR_GW_R
+ | ((fgmac4_info.mdc_clk & FGMAC4_GAR_CR_MASK) << FGMAC4_GAR_CR_SHIFT)
+ | FGMAC4_GAR_GB;
+
+ /* Wait until GMII/MII is not busy */
+ ret = fgmac4_phy_wait();
+ if (ret) {
+ printf("Read PHY Error!\n");
+ return ret;
+ }
+
+ WRITE_REG(wval, FGMAC4_REG_GAR);
+
+ /* Wait until GMII/MII is not busy */
+ ret = fgmac4_phy_wait();
+ if (ret) {
+ printf("Read PHY Error!\n");
+ return ret;
+ }
+
+ *read_val = READ_REG(FGMAC4_REG_GDR);
+ return 0;
+}
+
+/*
+ * fgmac4_phy_write -- write PHY's register
+ * @phy_addr: address of phy. range:0-31
+ * @reg_addr: phy register address
+ * @write_val: written value
+ *
+ * Description: read PHY's register by setting FGMAC4's GAR register and
+ * GDR register.
+ */
+static int fgmac4_phy_write(u16 phy_addr, u16 reg_addr, u32 write_val)
+{
+ int wval, ret;
+
+ /* Set the GAR register */
+ wval = (phy_addr << FGMAC4_GAR_PA_SHIFT)
+ | ((reg_addr & FGMAC4_GAR_GR_MASK) << FGMAC4_GAR_GR_SHIFT)
+ | FGMAC4_GAR_GW_W
+ | ((fgmac4_info.mdc_clk & FGMAC4_GAR_CR_MASK) << FGMAC4_GAR_CR_SHIFT)
+ | FGMAC4_GAR_GB;
+
+ /* Wait until GMII/MII is not busy */
+ ret = fgmac4_phy_wait();
+ if (ret) {
+ printf("Read PHY Error!\n");
+ return ret;
+ }
+
+ /* Set the value that is want to be written in PHY register */
+ WRITE_REG(write_val, FGMAC4_REG_GDR);
+ /* Set PHY Register access information */
+ WRITE_REG(wval, FGMAC4_REG_GAR);
+
+ /* Wait until GMII/MII is not busy */
+ ret = fgmac4_phy_wait();
+ if (ret) {
+ printf("Read PHY Error!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * fgmac4_get_phyaddr -- find out PHYs on the device
+ *
+ * Description: Reads the ID registers of the every PHY addr(0-31) on the
+ * device(if the corresponding bit is masked, skip it).
+ * If the ID<>0x1FFFFFFF then set i to phy_id.
+ */
+
+#define PHY_MASK_ADDR 0xffffff01
+static int fgmac4_get_phyaddr(void)
+{
+ u32 phy_id, phy_reg, i, phyaddr_mask = PHY_MASK_ADDR;
+ int ret;
+
+ /* initialize PHY installation information */
+ fgmac4_info.phy_info.phy_addr = ~0;
+
+ for (i = 0; i <= MAX_PHY_ADR; i++) {
+ /* Do not scan the masked phy addr */
+ if (phyaddr_mask & (1 << i))
+ continue;
+
+ /* Read phy ID from PHY's PHYSID1&PHYSID2 */
+ ret = fgmac4_phy_read(i, MII_PHYSID1, &phy_reg);
+ if (ret) {
+ printf("Failed to read PHYID1 register!!!\n");
+ return -EACCES;
+ }
+ phy_id = (phy_reg & 0xFFFF) << 16; /* get PHYID high */
+
+ ret = fgmac4_phy_read(i, MII_PHYSID2, &phy_reg);
+ if (ret) {
+ printf("Failed to read PHYID2 register!!!\n");
+ return -EACCES;
+ }
+ phy_id |= (phy_reg & 0xFFFF); /* get PHYID low */
+
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((phy_id & 0x1fffffff) == 0x1fffffff) {
+ printf("There is no PHY in slot(%d).\n", i);
+ continue;
+ }
+
+ /* set the bit of installed PHY */
+ fgmac4_info.phy_info.phy_addr = i;
+ break;
+ }
+ return 0;
+}
+
+/*
+ * fgmac4_init_phyparam -- initialize PHY parameters
+ * @phy_info: pointer to PHY info structure
+ *
+ * Description: Initialize PHY info structure base on environment "ethspeed".
+ */
+static int fgmac4_init_phyparam(struct fgmac4_phy_info* phy_info)
+{
+ char* env_p = getenv("ethspeed");
+ if ((env_p == NULL) || (!strcmp(env_p, "auto"))) { /* Augoneg */
+ phy_info->autoneg = AUTONEG_ENABLE;
+ phy_info->adv = ADVERTISED_10baseT_Half
+ | ADVERTISED_10baseT_Full
+ | ADVERTISED_100baseT_Half
+ | ADVERTISED_100baseT_Full;
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ phy_info->adv |= ADVERTISED_1000baseT_Half
+ | ADVERTISED_1000baseT_Full;
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+ } else {
+ /* parameter error */
+ if (strcmp(env_p, "1000f") && strcmp(env_p, "1000h")
+ && strcmp(env_p, "100f") && strcmp(env_p, "100h")
+ && strcmp(env_p, "10f") && strcmp(env_p, "10h") ) {
+ return -EINVAL;
+ }
+#ifndef CONFIG_PHY_SUPPORT_GIGA_FORCE
+ /* If do not support 1000BaseT force media */
+ if (!strcmp(env_p, "1000f") || !strcmp(env_p, "1000h")) {
+ return -EINVAL;
+ }
+#endif /* !CONFIG_PHY_SUPPORT_GIGA_FORCE */
+ phy_info->autoneg = AUTONEG_DISABLE;
+#ifdef CONFIG_PHY_SUPPORT_GIGA_FORCE
+ if (!strcmp(env_p, "1000f")) {
+ phy_info->speed = SPEED_1000;
+ phy_info->duplex = DUPLEX_FULL;
+ } else if (!strcmp(env_p, "1000h")) {
+ phy_info->speed = SPEED_1000;
+ phy_info->duplex = DUPLEX_HALF;
+ } else if (!strcmp(env_p, "100f")) {
+#else /* !CONFIG_PHY_SUPPORT_GIGA_FORCE */
+ if (!strcmp(env_p, "100f")) {
+#endif /* CONFIG_PHY_SUPPORT_GIGA_FORCE */
+ phy_info->speed = SPEED_100;
+ phy_info->duplex = DUPLEX_FULL;
+ } else if (!strcmp(env_p, "100h")) {
+ phy_info->speed = SPEED_100;
+ phy_info->duplex = DUPLEX_HALF;
+ } else if (!strcmp(env_p, "10f")) {
+ phy_info->speed = SPEED_10;
+ phy_info->duplex = DUPLEX_FULL;
+ } else {
+ phy_info->speed = SPEED_10;
+ phy_info->duplex = DUPLEX_HALF;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * fgmac4_phy_set -- set PHY parameters to PHY
+ * @phy_info: pointer to PHY info structure
+ *
+ * Description: Set PHY parameters to PHY.
+ */
+static int fgmac4_phy_set (struct fgmac4_phy_info* phy_info)
+{
+ if (phy_info->autoneg == AUTONEG_ENABLE) {
+ u32 bmcr, advert, tmp;
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ u32 advert2, tmp2;
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+
+ if ((phy_info->adv & (ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_1000baseT_Half |
+ ADVERTISED_1000baseT_Full)) == 0)
+ return -EINVAL;
+
+ /* advertise only what has been requested */ /* read */
+ fgmac4_phy_read(phy_info->phy_addr, MII_ADVERTISE, &advert);
+ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ fgmac4_phy_read(phy_info->phy_addr, MII_CTRL1000, &advert2);
+ tmp2 = advert2
+ & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+ if (phy_info->adv & ADVERTISED_10baseT_Half)
+ tmp |= ADVERTISE_10HALF;
+ if (phy_info->adv & ADVERTISED_10baseT_Full)
+ tmp |= ADVERTISE_10FULL;
+ if (phy_info->adv & ADVERTISED_100baseT_Half)
+ tmp |= ADVERTISE_100HALF;
+ if (phy_info->adv & ADVERTISED_100baseT_Full)
+ tmp |= ADVERTISE_100FULL;
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ if (phy_info->adv & ADVERTISED_1000baseT_Half)
+ tmp2 |= ADVERTISE_1000HALF;
+ if (phy_info->adv & ADVERTISED_1000baseT_Full)
+ tmp2 |= ADVERTISE_1000FULL;
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+ if (advert != tmp)
+ fgmac4_phy_write(phy_info->phy_addr,MII_ADVERTISE, tmp);
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ if (advert2 != tmp2)
+ fgmac4_phy_write(phy_info->phy_addr,MII_CTRL1000, tmp2);
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+ /* turn on autonegotiation, and force a renegotiate */
+ fgmac4_phy_read(phy_info->phy_addr, MII_BMCR, &bmcr);
+ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ fgmac4_phy_write(phy_info->phy_addr, MII_BMCR, bmcr);
+ } else {
+ u32 bmcr, tmp;
+ if (phy_info->speed != SPEED_10 &&
+ phy_info->speed != SPEED_100 &&
+ phy_info->speed != SPEED_1000)
+ return -EINVAL;
+#ifndef CONFIG_PHY_SUPPORT_GIGA_FORCE
+ if (phy_info->speed == SPEED_1000)
+ return -EINVAL;
+#endif /* !CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+ if (phy_info->duplex != DUPLEX_HALF
+ && phy_info->duplex != DUPLEX_FULL)
+ return -EINVAL;
+ /* turn off auto negotiation, set speed and duplexity */
+ fgmac4_phy_read(phy_info->phy_addr, MII_BMCR, &bmcr);
+ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
+ BMCR_SPEED1000 | BMCR_FULLDPLX);
+ if (phy_info->speed == SPEED_1000)
+ tmp |= BMCR_SPEED1000;
+ else if (phy_info->speed == SPEED_100)
+ tmp |= BMCR_SPEED100;
+ if (phy_info->duplex == DUPLEX_FULL)
+ tmp |= BMCR_FULLDPLX;
+ if (bmcr != tmp)
+ fgmac4_phy_write(phy_info->phy_addr, MII_BMCR, tmp);
+ }
+ return 0;
+}
+
+/*
+ * fgmac4_get_adv -- Get advertising info
+ * @phy_addr: address of phy. range:0-31
+ * @reg_addr: phy register address
+ *
+ * Description: Get advertising info from MII_ADVERTISE and MII_LPA,
+ * the reg_addr parameter can only be set to MII_ADVERTISE or MII_LPA.
+ */
+static u32 fgmac4_get_adv(u16 phy_addr, u16 reg_addr)
+{
+ u32 advert = 0, result = 0;
+
+ fgmac4_phy_read(phy_addr, reg_addr, &advert);
+
+ if (advert & ADVERTISE_10HALF)
+ result |= ADVERTISED_10baseT_Half;
+ if (advert & ADVERTISE_10FULL)
+ result |= ADVERTISED_10baseT_Full;
+ if (advert & ADVERTISE_100HALF)
+ result |= ADVERTISED_100baseT_Half;
+ if (advert & ADVERTISE_100FULL)
+ result |= ADVERTISED_100baseT_Full;
+
+ return result;
+}
+
+/*
+ * fgmac4_phy_get -- get setted speed and duplex info from PHY
+ * @phy_addr: address of phy. range:0-31
+ * @speed_p: pointer which is used to contain getted speed info
+ * @duplex_p: pointer which is used to contain getted duplex info
+ *
+ * Description: Get setted speed and duplex info from PHY
+ */
+static int fgmac4_phy_get (u16 phy_addr, u32* speed_p, u32* duplex_p)
+{
+ u32 bmcr, bmsr, ctrl1000 = 0, stat1000 = 0;
+ u32 nego, local_advertising = 0, lp_advertising = 0;
+
+ fgmac4_phy_read(phy_addr, MII_BMCR, &bmcr);
+ fgmac4_phy_read(phy_addr, MII_BMSR, &bmsr);
+
+ if (bmcr & BMCR_ANENABLE) {
+
+#ifdef CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+ fgmac4_phy_read(phy_addr, MII_CTRL1000, &ctrl1000);
+ fgmac4_phy_read(phy_addr, MII_STAT1000, &stat1000);
+#endif /* CONFIG_PHY_SUPPORT_GIGA_AUTONEG */
+
+ local_advertising |= fgmac4_get_adv(phy_addr, MII_ADVERTISE);
+ if (ctrl1000 & ADVERTISE_1000HALF)
+ local_advertising |= ADVERTISED_1000baseT_Half;
+ if (ctrl1000 & ADVERTISE_1000FULL)
+ local_advertising |= ADVERTISED_1000baseT_Full;
+
+ if (bmsr & BMSR_ANEGCOMPLETE) {
+ lp_advertising = fgmac4_get_adv(phy_addr, MII_LPA);
+ if (stat1000 & LPA_1000HALF)
+ lp_advertising |=
+ ADVERTISED_1000baseT_Half;
+ if (stat1000 & LPA_1000FULL)
+ lp_advertising |=
+ ADVERTISED_1000baseT_Full;
+ } else {
+ lp_advertising = 0;
+ }
+
+ nego = local_advertising & lp_advertising;
+
+ if (nego & (ADVERTISED_1000baseT_Full |
+ ADVERTISED_1000baseT_Half)) {
+ *speed_p = SPEED_1000;
+ *duplex_p = !!(nego & ADVERTISED_1000baseT_Full);
+ } else if (nego & (ADVERTISED_100baseT_Full |
+ ADVERTISED_100baseT_Half)) {
+ *speed_p = SPEED_100;
+ *duplex_p = !!(nego & ADVERTISED_100baseT_Full);
+ } else {
+ *speed_p = SPEED_10;
+ *duplex_p = !!(nego & ADVERTISED_10baseT_Full);
+ }
+ } else {
+ *speed_p = ((bmcr & BMCR_SPEED1000 &&
+ (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
+ (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
+ *duplex_p = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+ }
+
+ return 0;
+}
+
+/*
+ * fgmac4_probe -- initialize private info
+ *
+ * Description: Initialize private info
+ */
+static int fgmac4_probe(void)
+{
+ int i,err;
+
+ /* get MDC clock from SYS_CLOCK */
+ if (FGMAC4_CLK < 20) {
+ printf("Unavailable FGMAC4_CLK(%d), aborting!!!\n", FGMAC4_CLK);
+ return -EINVAL;
+
+ } else if (FGMAC4_CLK < 35) {
+ fgmac4_info.mdc_clk = 2;
+ } else if (FGMAC4_CLK < 60) {
+ fgmac4_info.mdc_clk = 3;
+ } else if (FGMAC4_CLK < 100) {
+ fgmac4_info.mdc_clk = 0;
+ } else if (FGMAC4_CLK < 150) {
+ fgmac4_info.mdc_clk = 1;
+ } else if (FGMAC4_CLK < 250) {
+ fgmac4_info.mdc_clk = 4;
+ } else if (FGMAC4_CLK < 300) {
+ fgmac4_info.mdc_clk = 5;
+ } else {
+ printf("Unavailable FGMAC4_CLK(%d), aborting!!!\n", FGMAC4_CLK);
+ return -EINVAL;
+ }
+
+ err = fgmac4_get_phyaddr(); /* get phy install information */
+ if (err) {
+ printf("Failed to find PHY, aborting!!!\n");
+ return -EINVAL;
+ }
+
+ /* initialize private info */
+ fgmac4_info.rx_ring_num = 0;
+ fgmac4_info.tx_ring_num = 0;
+
+ fgmac4_info.rx_buf_sz = BUFFER_SIZE; /* 1536 bytes */
+ fgmac4_info.rx_buf_array = (unsigned char*)fgmac4_buf;
+ fgmac4_info.tx_buf_array = fgmac4_info.rx_buf_array
+ + FGMAC4_RDESC_NUM * BUFFER_SIZE;
+
+ /* Descriptor initialization */
+ fgmac4_info.ring_dma = (dma_addr_t)fgmac4_ring;
+ fgmac4_info.rx_ring = (struct fgmac4_desc *)(fgmac4_info.ring_dma);
+
+ fgmac4_info.tx_ring =
+ (struct fgmac4_desc *)((unsigned long)fgmac4_info.rx_ring
+ + FGMAC4_RDESC_NUM * sizeof(struct fgmac4_desc));
+
+ memset(fgmac4_info.rx_ring, 0,
+ sizeof(struct fgmac4_desc) * FGMAC4_RDESC_NUM);
+ memset(fgmac4_info.tx_ring, 0,
+ sizeof(struct fgmac4_desc) * FGMAC4_TDESC_NUM);
+
+ /* set TX/RX end ring flags */
+ fgmac4_info.rx_ring[FGMAC4_RDESC_NUM - 1].opts2 =
+ FGMAC4_RDES1_RER;
+ fgmac4_info.tx_ring[FGMAC4_TDESC_NUM - 1].opts1 =
+ FGMAC4_TDES0_TER;
+ /* init receive ring */
+ for(i = 0; i < FGMAC4_RDESC_NUM; i++) {
+ struct fgmac4_desc *rx_ring;
+
+ rx_ring = &fgmac4_info.rx_ring[i];
+ rx_ring->opts2 |= FGMAC4_RDES1_DIC | BUFFER_SIZE;
+
+ rx_ring->addr1 = (u32)(&fgmac4_info.rx_buf_array[i * BUFFER_SIZE]);
+ rx_ring->addr2 = 0;
+ dmb();
+ rx_ring->opts1 = OWN_BIT;
+
+ }
+ return 0;
+}
+
+/*
+ * fgmac4_phy_aneg_wait -- wait the completion of autonegotiation
+ * @phy_info: pointer to PHY info structure
+ *
+ * Description: Wait the completion of autonegotiation
+ */
+static int fgmac4_phy_aneg_wait(struct fgmac4_phy_info* phy_info)
+{
+ u32 ctl = 0, wtime;
+ int ret = 0;
+
+ /* sure autonegotiation success */
+ wtime = ANEG_WAIT_COUNT;
+ while (wtime--) {
+ ret = fgmac4_phy_read(phy_info->phy_addr, MII_BMSR, &ctl);
+ if (ret)
+ return -EACCES;
+
+ if ((ctl & BMSR_LSTATUS) && (ctl & BMSR_ANEGCOMPLETE)) {
+ return 0;
+ }
+ udelay(DELAY_TIME);
+ }
+
+ return -EBUSY;
+}
+
+/*
+ * fgmac4_setup_aneg -- setup autonegotiation
+ * @phy_info: pointer to PHY info structure
+ *
+ * Description: Setup autonegotiation
+ */
+static int fgmac4_setup_aneg(struct fgmac4_phy_info* phy_info)
+{
+ int ret = 0;
+
+ ret = fgmac4_init_phyparam(phy_info);
+ if (ret)
+ return ret;
+ ret = fgmac4_phy_set(phy_info);
+ if (ret)
+ return ret;
+
+ if (phy_info->autoneg == AUTONEG_ENABLE) {
+ /* wait for completion of auto negotiation */
+ ret = fgmac4_phy_aneg_wait(phy_info);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * fgmac4_write_hwaddr -- set FGMAC's MAC address
+ * @netdev: pointer to ethernet device structure
+ *
+ * Description: Set FGMAC's MAC address
+ */
+static int fgmac4_write_hwaddr(struct eth_device *netdev)
+{
+ /* Mac Add = UU:VV:WW:XX:YY:ZZ
+ * MAR0H = 32'h0000ZZYY
+ * MAR0L = 32'hXXWWVVUU
+ */
+ u32 reg_data;
+ /* The validation of enetaddr is guaranteed by eth_initialize */
+ unsigned char* mac_addr = netdev->enetaddr;
+
+ printf(" MAC=%x:%x:%x:%x:%x:%x ",mac_addr[0], mac_addr[1],
+ mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+ reg_data = (mac_addr[3] << 24)|(mac_addr[2] << 16)
+ |(mac_addr[1] << 8)|mac_addr[0];
+ WRITE_REG(reg_data, FGMAC4_REG_MAR0L);
+ reg_data = (mac_addr[5] << 8)|mac_addr[4];
+ WRITE_REG(reg_data, FGMAC4_REG_MAR0H);
+
+ return 0;
+}
+
+/*
+ * fgmac4_disable_intr_all -- disable all FGMAC's interrupts
+ *
+ * Description: Disable all FGMAC's interrupts
+ */
+static void fgmac4_disable_intr_all(void)
+{
+ u32 val;
+
+ /* disable all interrupt */
+ WRITE_REG(0, FGMAC4_REG_IER);
+ WRITE_REG((FGMAC4_IMR_LPIIM | FGMAC4_IMR_TSIM
+ | FGMAC4_IMR_PIM | FGMAC4_IMR_RGIM),
+ FGMAC4_REG_IMR);
+ /* Mask all interrupt of MMC */
+ WRITE_REG(0x00FFFFFF, FGMAC4_REG_MMC_INTR_MASK_RX);
+ WRITE_REG(0x01FFFFFF, FGMAC4_REG_MMC_INTR_MASK_TX);
+ WRITE_REG(0x3FFF3FFF, FGMAC4_REG_MMC_IPC_INTR_MASK_RX);
+ /* clear status register */
+ val = READ_REG(FGMAC4_REG_SR);
+ WRITE_REG(val, FGMAC4_REG_SR);
+}
+
+/*
+ * fgmac4_init -- initialize fgmac4
+ * @eth_device: pointer to ethernet device structure
+ * @bd: pointer to board info structure
+ *
+ * Description: Initialize fgmac4
+ */
+static int fgmac4_init(struct eth_device *netdev, bd_t *bd)
+{
+ u32 val;
+ int err;
+ u32 rx_adr, tx_adr;
+ u32 speed, duplex;
+
+ err = fgmac4_probe();
+ if(err)
+ return err;
+
+ /* DMA Initialization */
+
+ /* 1.Set BMR(MDC Bus Mode Register) DMA reg 0 */
+ val = (FGMAC4_BMR_8XPBL & SET_1)
+ | (FGMAC4_BMR_USP & SET_1)
+ | (FGMAC4_BMR_FB & SET_1)
+ | (FGMAC4_BMR_DA & SET_1) /* DMA Arbitration Scheme:RX First */
+ | (FGMAC4_BMR_ATDS & SET_1) /* Use Alternative */
+ | FGMAC4_BMR_RPBL_16
+ | FGMAC4_BMR_PBL_16 /* When 8xPBL is set max value of PBL is 16 */
+ | FGMAC4_BMR_DSL; /* Descripter Skip Length is 0 */
+
+ WRITE_REG(val, FGMAC4_REG_BMR);
+
+ /* 2. Disable interrupts */
+ fgmac4_disable_intr_all();
+
+ /* Set PMTR GMAC reg 11 */
+ /* Disable Wake Up Frame | Disable Magic Packet */
+ val = (FGMAC4_PMTR_WFE & SET_0) /* Wake Up Frame Disable */
+ | (FGMAC4_PMTR_MPE & SET_0); /* Magic Packet Disable */
+
+ WRITE_REG(val, FGMAC4_REG_PMTR);
+
+ /* 3.Set MFFR(MAC Frame Filter Register) GMAC reg 1
+ * With this set the LAN can do:
+ * (1).Receive broadcast frames
+ * (2).Receive packets that has the same unicast address as MARn
+ */
+ WRITE_REG(0, FGMAC4_REG_MFFR);
+
+ /* 4.Set MHTRH(MAC Hash Table Register High) GMAC reg 2
+ * MHTRL(MAC Hash Table Register Low) GMAC reg 3
+ */
+ WRITE_REG(0, FGMAC4_REG_MHTRH);
+ WRITE_REG(0, FGMAC4_REG_MHTRL);
+
+ /* switch to GMII port */
+ val = READ_REG(FGMAC4_REG_MCR) & (~FGMAC4_MCR_MII_PORT);
+ WRITE_REG(val, FGMAC4_REG_MCR);
+ udelay(10);
+ /* 5.Setup PHY Autonegotiation */
+ err = fgmac4_setup_aneg(&fgmac4_info.phy_info);
+ if (err) {
+ printf("Failed to setup AutoNegotiation!!!\n");
+ return err;
+ }
+
+ /* 6.Set MCR(MAC Configuration Register) GMAC reg 0 */
+ val = (FGMAC4_MCR_WD & SET_1) /* Disable RX Watchdog timeout*/
+ | (FGMAC4_MCR_JD & SET_1) /* Disable TX Jabber timer */
+ | (FGMAC4_MCR_BE & SET_1) /* Frame Burst Enable */
+ | (FGMAC4_MCR_JE & SET_0) /* Jumbo Frame Disable */
+ | (FGMAC4_MCR_DO & SET_0) /* Enable Receive Own */
+ | (FGMAC4_MCR_LM & SET_0) /* Not Loop-back Mode */
+ | (FGMAC4_MCR_DR & SET_0) /* Enable Retry */
+ | (FGMAC4_MCR_DC & SET_0) /* Deferral Check Disable */
+ | (FGMAC4_MCR_TX_ENABLE & SET_1) /* Enable Transmitter */
+ | (FGMAC4_MCR_RX_ENABLE & SET_1) /* Enable Receiver */
+ | FGMAC4_MCR_BL_00; /* Back-off Limit is 0 */
+
+ err = fgmac4_phy_get(fgmac4_info.phy_info.phy_addr, &speed, &duplex);
+ if (err) {
+ printf("Failed to get speed and duplex info !!!\n");
+ return err;
+ }
+ if (duplex == DUPLEX_FULL) {
+ val |= FGMAC4_MCR_FULL_DUPLEX;
+ val &= ~FGMAC4_MCR_IFG_MASK;
+
+ val |= FGMAC4_MCR_IFG_80;
+ val &= ~FGMAC4_MCR_DCRS;
+ } else {
+ val &= ~FGMAC4_MCR_FULL_DUPLEX;
+ val &= ~FGMAC4_MCR_IFG_MASK;
+ val |= FGMAC4_MCR_IFG_64;
+ val |= FGMAC4_MCR_DCRS;
+ }
+ if (speed == SPEED_1000) { /* GMII Port */
+ /* MCR[bit15]: 0 = GMII Port; 1 = MII Port */
+ val &= ~FGMAC4_MCR_MII_PORT;
+ } else { /* MII Port */
+ val |= FGMAC4_MCR_MII_PORT;
+ }
+ WRITE_REG(val, FGMAC4_REG_MCR);
+
+ udelay(10); /* wait 10us */
+
+ /* 7.Set RDLAR(MDC Receive Descriptor List Address Register)
+ * TDLAR(MDC Transmit Descriptor List Address Register) */
+
+ rx_adr = (u32)fgmac4_info.rx_ring;
+ tx_adr = (u32)fgmac4_info.tx_ring;
+
+ WRITE_REG(rx_adr, FGMAC4_REG_RDLAR);
+ WRITE_REG(tx_adr, FGMAC4_REG_TDLAR);
+
+ /* 8.Set OMR to start RX */
+ val =
+ FGMAC4_OMR_TTC_256B /* TX after 256 bytes written in FIFO */
+ /* | FGMAC4_OMR_START_TX */ /* Start Transmissin */
+ | FGMAC4_OMR_START_RX; /* Start Receive */
+
+ WRITE_REG(val, FGMAC4_REG_OMR);
+
+ return 0;
+}
+
+/*
+ * fgmac4_halt -- stop hardware
+ * @netdev: pointer to ethernet device structure
+ *
+ * Description: In this function, the driver will stop the TX/RX engine and
+ * clear the status of hardware.
+ */
+static void fgmac4_halt(struct eth_device *netdev)
+{
+ u32 val;
+
+ /* stop TX and RX process */
+ val = 0;
+ WRITE_REG(val, FGMAC4_REG_OMR);
+
+ /* clear desc */
+ fgmac4_info.ring_dma = 0;
+ fgmac4_info.rx_ring = NULL;
+ fgmac4_info.tx_ring = NULL;
+ fgmac4_info.rx_buf_array = NULL;
+ fgmac4_info.tx_buf_array = NULL;
+
+ /* clear status register */
+ val = READ_REG(FGMAC4_REG_SR);
+ WRITE_REG(val, FGMAC4_REG_SR);
+
+ return;
+}
+
+/*
+ * fgmac4_send -- send a packet to media from the upper layer.
+ * @netdev: pointer to ethernet device structure
+ * @packet: pointer to header address of transmitting data
+ * @length: data length
+ *
+ * Description: The send function does what you think -- transmit the specified
+ * packet whose size is specified by length (in bytes). You should not return
+ * until the transmission is complete, and you should leave the state such that
+ * the send function can be called multiple times in a row.
+ */
+static int fgmac4_send(struct eth_device *netdev, volatile void *packet,
+ int length)
+{
+ u32 val;
+ int tmo, ret = 0;
+
+ struct fgmac4_desc *tx_ring;
+ unsigned char* tx_buff_addr;
+ int len = length;
+
+ tx_ring = &fgmac4_info.tx_ring[fgmac4_info.tx_ring_num];
+
+ tx_buff_addr = &fgmac4_info.tx_buf_array[fgmac4_info.tx_ring_num * BUFFER_SIZE];
+
+ /* copy data to tx buffer */
+ memcpy(tx_buff_addr, (const void*)packet, len);
+ while (len < ETH_ZLEN)
+ tx_buff_addr[len++] = '\0';
+
+ fgmac4_info.tx_ring_num++;
+ if(fgmac4_info.tx_ring_num == FGMAC4_TDESC_NUM) {
+ fgmac4_info.tx_ring_num = 0;
+ }
+
+ /* set up transmit desc (TDES0-TDES3) and set TDES0[31] */
+ tx_ring->opts1 |= FGMAC4_TDES0_FS | FGMAC4_TDES0_LS;
+ tx_ring->opts2 = len;
+ tx_ring->addr1 = (u32)tx_buff_addr;
+ tx_ring->addr2 = 0;
+
+ tx_ring->opts1 |= OWN_BIT;
+
+ /* Make sure all needed operations were finished before starting DMA */
+ dmb();
+
+ /* set ST bit (DMA 6[13]) DMA enters the Runstate */
+ val = READ_REG(FGMAC4_REG_OMR);
+ val |= FGMAC4_OMR_START_TX;
+ WRITE_REG(val, FGMAC4_REG_OMR);
+
+ /* Transmit Poll Demand */
+ val = 0xffffffff;
+ WRITE_REG(val, FGMAC4_REG_TPDR);
+
+ /* wait transmission complete */
+ tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; /* timer clk */
+
+ while ((tx_ring->opts1 & 0x80000000) == OWN_BIT) {
+ if (get_timer(0) >= tmo) {
+ printf("transmission timeout SR[0x%08x]\n", READ_REG(FGMAC4_REG_SR));
+
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ /* set ST bit to stop DMA */
+ val = READ_REG(FGMAC4_REG_OMR);
+ val &= ~FGMAC4_OMR_START_TX;
+ WRITE_REG(val, FGMAC4_REG_OMR);
+
+ return ret;
+}
+
+/*
+ * fgmac4_rx -- received a packet and pass to upper layer
+ * @netdev: pointer to ethernet device structure
+ *
+ * Description: The recv function should process packets as long as the hardware
+ * has them readily available before returning. i.e. you should drain the
+ * hardware fifo. For each packet you receive, you should call the NetReceive()
+ * function on it along with the packet length. The common code sets up packet
+ * buffers for you already in the .bss (NetRxPackets), so there should be no
+ * need to allocate your own. This doesn't mean you must use the NetRxPackets
+ * array however; you're free to call the NetReceive() function with any buffer
+ * you wish.
+ * int ape_recv(struct eth_device *dev)
+ * {
+ * int length, i = 0;
+ * ...
+ * while (packets_are_available()) {
+ * ...
+ * length = ape_get_packet(&NetRxPackets[i]);
+ * ...
+ * NetReceive(&NetRxPackets[i], length);
+ * ...
+ * if (++i >= PKTBUFSRX)
+ * i = 0;
+ * ...
+ * }
+ * ...
+ * return 0;
+ */
+static int fgmac4_rx(struct eth_device *netdev)
+{
+ u32 rx_len;
+ int i;
+
+ struct fgmac4_desc *rx_ring;
+
+ /* recevie packet */
+ for(i = 0;i < FGMAC4_RDESC_NUM; i++) {
+ rx_ring = &fgmac4_info.rx_ring[i];
+
+ if ((rx_ring->opts1 & 0x80000000) != OWN_BIT) {
+
+ /* Read error state */
+ if (rx_ring->opts1 & FGMAC4_RX_DESC_ERR) {
+ printf("RX Desc has error status(0x%08x:0x%08x).\n",
+ rx_ring->opts1,
+ READ_REG (FGMAC4_REG_SR));
+ rx_ring->opts1 = OWN_BIT;
+
+ return -EIO;
+ }
+ /* Get data length */
+ rx_len = ((rx_ring->opts1 >> 16) & 0x3FFF) - 4;
+
+ /* Read received packet from buf */
+ NetReceive((uchar *)rx_ring->addr1, rx_len);
+
+ /*
+ * Make sure all data operations were completed before
+ * restart DMA, or, a potential data corruption may
+ * happen while DMA is still going on.
+ */
+ dmb();
+ rx_ring->opts1 = OWN_BIT;
+ break;
+ }
+ }
+
+ return 0;
+}
+/*
+ * fgmac4_initialize -- register ethernet device
+ * @bis: pointer to board info
+ *
+ * Description: Register ethernet device
+ */
+int fgmac4_initialize(bd_t *bis)
+{
+ int ret;
+ struct eth_device *dev = &(fgmac4_info.netdev);
+
+ dev->init = fgmac4_init;
+ dev->halt = fgmac4_halt;
+ dev->send = fgmac4_send;
+ dev->recv = fgmac4_rx;
+ dev->write_hwaddr = fgmac4_write_hwaddr;
+ sprintf(dev->name, "fgmac4");
+
+ ret = eth_register(dev);
+ return ret;
+}
+
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/fgmac4.h u-boot/drivers/net/fgmac4.h
--- original/u-boot-linaro-stable/drivers/net/fgmac4.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/fgmac4.h 2016-08-02 14:19:41.066728335 +0900
@@ -0,0 +1,428 @@
+/*
+ * u-boot/drivers/net/fgmac4.h
+ *
+ * Copyright (C) 2010-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+/*
+ * FGMAC4 Ethernet
+ */
+
+#ifndef __FGMAC4_H
+#define __FGMAC4_H
+#ifdef CONFIG_DRIVER_FGMAC4
+
+/*
+ * F_GMAC4 Register Address Map
+ */
+#define FGMAC4_REG_MCR 0x0000 /* MAC Configuration Register */
+#define FGMAC4_REG_MFFR 0x0004 /* MAC Frame Filter Register */
+#define FGMAC4_REG_MHTRH 0x0008 /* MAC Hash Table Register(High) */
+#define FGMAC4_REG_MHTRL 0x000C /* MAC Hash Table Register(Low) */
+#define FGMAC4_REG_GAR 0x0010 /* GMII Address Register */
+#define FGMAC4_REG_GDR 0x0014 /* GMII Data Register */
+#define FGMAC4_REG_FCR 0x0018 /* Flow Control Register */
+#define FGMAC4_REG_VTR 0x001C /* VLAN Tag Register */
+
+#define FGMAC4_REG_RWFFR 0x0028 /*Remote Wake-up Frame FilterRegister*/
+#define FGMAC4_REG_PMTR 0x002C /* PMT Register */
+#define FGMAC4_REG_LPICSR 0x0030 /* LPI Control and Status Register */
+#define FGMAC4_REG_LPITCR 0x0034 /* LPI Timers Control Register */
+#define FGMAC4_REG_ISR 0x0038 /* Interrupt Status Register */
+#define FGMAC4_REG_IMR 0x003C /* Interrupt Mask Register */
+
+#define FGMAC4_REG_MAR0H 0x0040 /* MAC Address0 Register(High) */
+#define FGMAC4_REG_MAR0L 0x0044 /* MAC Address0 Register(Low) */
+#define FGMAC4_REG_MAR1H 0x0048 /* MAC Address1 Register(High) */
+#define FGMAC4_REG_MAR1L 0x004C /* MAC Address1 Register(Low) */
+#define FGMAC4_REG_MAR2H 0x0050 /* MAC Address2 Register(High) */
+#define FGMAC4_REG_MAR2L 0x0054 /* MAC Address2 Register(Low) */
+#define FGMAC4_REG_MAR3H 0x0058 /* MAC Address3 Register(High) */
+#define FGMAC4_REG_MAR3L 0x005C /* MAC Address3 Register(Low) */
+#define FGMAC4_REG_MAR4H 0x0060 /* MAC Address4 Register(High) */
+#define FGMAC4_REG_MAR4L 0x0064 /* MAC Address4 Register(Low) */
+#define FGMAC4_REG_MAR5H 0x0068 /* MAC Address5 Register(High) */
+#define FGMAC4_REG_MAR5L 0x006C /* MAC Address5 Register(Low) */
+#define FGMAC4_REG_MAR6H 0x0070 /* MAC Address6 Register(High) */
+#define FGMAC4_REG_MAR6L 0x0074 /* MAC Address6 Register(Low) */
+#define FGMAC4_REG_MAR7H 0x0078 /* MAC Address7 Register(High) */
+#define FGMAC4_REG_MAR7L 0x007C /* MAC Address7 Register(Low) */
+#define FGMAC4_REG_MAR8H 0x0080 /* MAC Address8 Register(High) */
+#define FGMAC4_REG_MAR8L 0x0084 /* MAC Address8 Register(Low) */
+#define FGMAC4_REG_MAR9H 0x0088 /* MAC Address9 Register(High) */
+#define FGMAC4_REG_MAR9L 0x008C /* MAC Address9 Register(Low) */
+#define FGMAC4_REG_MAR10H 0x0090 /* MAC Address10 Register(High) */
+#define FGMAC4_REG_MAR10L 0x0094 /* MAC Address10 Register(Low) */
+#define FGMAC4_REG_MAR11H 0x0098 /* MAC Address11 Register(High) */
+#define FGMAC4_REG_MAR11L 0x009C /* MAC Address11 Register(Low) */
+#define FGMAC4_REG_MAR12H 0x00A0 /* MAC Address12 Register(High) */
+#define FGMAC4_REG_MAR12L 0x00A4 /* MAC Address12 Register(Low) */
+#define FGMAC4_REG_MAR13H 0x00A8 /* MAC Address13 Register(High) */
+#define FGMAC4_REG_MAR13L 0x00AC /* MAC Address13 Register(Low) */
+#define FGMAC4_REG_MAR14H 0x00B0 /* MAC Address14 Register(High) */
+#define FGMAC4_REG_MAR14L 0x00B4 /* MAC Address14 Register(Low) */
+#define FGMAC4_REG_MAR15H 0x00B8 /* MAC Address15 Register(High) */
+#define FGMAC4_REG_MAR15L 0x00BC /* MAC Address15 Register(Low) */
+
+#define FGMAC4_REG_RSR 0x00D8 /* RGMII status Reigster */
+
+#define FGMAC4_REG_TSCR 0x0700 /* Time Stamp Control Register */
+#define FGMAC4_REG_SSIR 0x0704 /* Sub-Second Increment Register */
+#define FGMAC4_REG_STSR 0x0708 /* System Time - Seconds Register */
+#define FGMAC4_REG_STNR 0x070C /* System Time - Nanoseconds Register */
+#define FGMAC4_REG_STSUR 0x0710 /* System Time-Seconds Update Reg */
+#define FGMAC4_REG_STNUR 0x0714 /* System Time-Nanoseconds Update Reg */
+#define FGMAC4_REG_TSAR 0x0718 /* Time Stamp Addend Register */
+#define FGMAC4_REG_TTSR 0x071C /* Target Time Seconds Register */
+#define FGMAC4_REG_TTNR 0x0720 /* Target Time Nanoseconds Register */
+#define FGMAC4_REG_STHWSR 0x0724 /* System Time-High Word Seconds Reg */
+#define FGMAC4_REG_TSR 0x0728 /* Time Stamp Status Register */
+#define FGMAC4_REG_PPSCR 0x072C /* PPC Control Register */
+#define FGMAC4_REG_ATNR 0x0730 /* Auxiliary Time Stamp-Nanosecond Reg*/
+#define FGMAC4_REG_ATSR 0x0734 /* Auxiliary Time Stamp-Seconds Reg */
+
+#define FGMAC4_REG_MAR16H 0x0800 /* MAC Address16 Register(High) */
+#define FGMAC4_REG_MAR16L 0x0804 /* MAC Address16 Register(Low) */
+#define FGMAC4_REG_MAR17H 0x0808 /* MAC Address17 Register(High) */
+#define FGMAC4_REG_MAR17L 0x080C /* MAC Address17 Register(Low) */
+#define FGMAC4_REG_MAR18H 0x0810 /* MAC Address18 Register(High) */
+#define FGMAC4_REG_MAR18L 0x0814 /* MAC Address18 Register(Low) */
+#define FGMAC4_REG_MAR19H 0x0818 /* MAC Address19 Register(High) */
+#define FGMAC4_REG_MAR19L 0x081C /* MAC Address19 Register(Low) */
+#define FGMAC4_REG_MAR20H 0x0820 /* MAC Address20 Register(High) */
+#define FGMAC4_REG_MAR20L 0x0824 /* MAC Address20 Register(Low) */
+#define FGMAC4_REG_MAR21H 0x0828 /* MAC Address21 Register(High) */
+#define FGMAC4_REG_MAR21L 0x082C /* MAC Address21 Register(Low) */
+#define FGMAC4_REG_MAR22H 0x0830 /* MAC Address22 Register(High) */
+#define FGMAC4_REG_MAR22L 0x0834 /* MAC Address22 Register(Low) */
+#define FGMAC4_REG_MAR23H 0x0838 /* MAC Address23 Register(High) */
+#define FGMAC4_REG_MAR23L 0x083C /* MAC Address23 Register(Low) */
+#define FGMAC4_REG_MAR24H 0x0840 /* MAC Address24 Register(High) */
+#define FGMAC4_REG_MAR24L 0x0844 /* MAC Address24 Register(Low) */
+#define FGMAC4_REG_MAR25H 0x0848 /* MAC Address25 Register(High) */
+#define FGMAC4_REG_MAR25L 0x084C /* MAC Address25 Register(Low) */
+#define FGMAC4_REG_MAR26H 0x0850 /* MAC Address26 Register(High) */
+#define FGMAC4_REG_MAR26L 0x0854 /* MAC Address26 Register(Low) */
+#define FGMAC4_REG_MAR27H 0x0858 /* MAC Address27 Register(High) */
+#define FGMAC4_REG_MAR27L 0x085C /* MAC Address27 Register(Low) */
+#define FGMAC4_REG_MAR28H 0x0860 /* MAC Address28 Register(High) */
+#define FGMAC4_REG_MAR28L 0x0864 /* MAC Address28 Register(Low) */
+#define FGMAC4_REG_MAR29H 0x0868 /* MAC Address29 Register(High) */
+#define FGMAC4_REG_MAR29L 0x086C /* MAC Address29 Register(Low) */
+#define FGMAC4_REG_MAR30H 0x0870 /* MAC Address30 Register(High) */
+#define FGMAC4_REG_MAR30L 0x0874 /* MAC Address30 Register(Low) */
+#define FGMAC4_REG_MAR31H 0x0878 /* MAC Address31 Register(High) */
+#define FGMAC4_REG_MAR31L 0x087C /* MAC Address31 Register(Low) */
+
+#define FGMAC4_REG_BMR 0x1000 /* DMA BUS Mode Register */
+#define FGMAC4_REG_TPDR 0x1004 /* DMA Transmit Poll Demand Register */
+#define FGMAC4_REG_RPDR 0x1008 /* DMA Receive Poll Demand Register */
+#define FGMAC4_REG_RDLAR 0x100C /* DMA Rx Desc List Address Register */
+#define FGMAC4_REG_TDLAR 0x1010 /* DMA Tx Desc List Address Register */
+#define FGMAC4_REG_SR 0x1014 /* DMA Status Register */
+#define FGMAC4_REG_OMR 0x1018 /* DMA Operation Mode Register */
+#define FGMAC4_REG_IER 0x101C /* DMA Interrupt Enable Register */
+#define FGMAC4_REG_MFOCR 0x1020 /* DMA Missed Frame Register */
+#define FGMAC4_REG_RIWTR 0x1024 /* DMA Rx Intr Watchdog Timer Reg */
+
+#define FGMAC4_REG_AHBSR 0x102C /* DMA AHB Status Register */
+
+#define FGMAC4_REG_CHTDR 0x1048 /* DMA Cur Host Tx Desc Register */
+#define FGMAC4_REG_CHRDR 0x104C /* DMA Cur Host Rx Desc Register */
+#define FGMAC4_REG_CHTBAR 0x1050 /* DMA Cur Host TX Buffer Addr Reg */
+#define FGMAC4_REG_CHRBAR 0x1054 /* DMA Cur Host RX Buffer Addr Reg */
+
+/* MMC(MAC Management Counters) Register Address Map */
+#define FGMAC4_REG_MMC_CNTL 0x0100
+#define FGMAC4_REG_MMC_INTR_RX 0x0104
+#define FGMAC4_REG_MMC_INTR_TX 0x0108
+#define FGMAC4_REG_MMC_INTR_MASK_RX 0x010C
+#define FGMAC4_REG_MMC_INTR_MASK_TX 0x0110
+
+#define FGMAC4_REG_MMC_TXOTCETCOUNT_GB 0x0114
+#define FGMAC4_REG_MMC_TXFRAMECOUNT_GB 0x0118
+#define FGMAC4_REG_MMC_TXBROADCASTFRAMES_G 0x011C
+#define FGMAC4_REG_MMC_TXMULTICASTFRAMES_G 0x0120
+#define FGMAC4_REG_MMC_TX64OCTECS_GB 0x0124
+#define FGMAC4_REG_MMC_TX65TO127OCTETS_GB 0x0128
+#define FGMAC4_REG_MMC_TX128TO255OCTETS_GB 0x012C
+#define FGMAC4_REG_MMC_TX256TO511OCTETS_GB 0x0130
+#define FGMAC4_REG_MMC_TX512TO1023OCTETS_GB 0x0134
+#define FGMAC4_REG_MMC_TX1024TOMAXOCTETS_GB 0x0138
+#define FGMAC4_REG_MMC_TXUNICASTFRAMES_GB 0x013C
+#define FGMAC4_REG_MMC_TXMULTICASTFRAMES_GB 0x0140
+#define FGMAC4_REG_MMC_TXBROADCASTFRAMES_GB 0x0144
+#define FGMAC4_REG_MMC_TXUNDERFLOWERROR 0x0148
+#define FGMAC4_REG_MMC_TXSINGLECOL_G 0x014C
+#define FGMAC4_REG_MMC_TXMULTICOL_G 0x0150
+#define FGMAC4_REG_MMC_TXDEFERRED 0x0154
+#define FGMAC4_REG_MMC_TXLATECOL 0x0158
+#define FGMAC4_REG_MMC_TXEXESSCOL 0x015C
+#define FGMAC4_REG_MMC_TXCARRIERERROR 0x0160
+#define FGMAC4_REG_MMC_TXOCTETCOUNT_G 0x0164
+#define FGMAC4_REG_MMC_TXFRAMECOUNT_G 0x0168
+#define FGMAC4_REG_MMC_TXEXECESSDEF 0x016C
+#define FGMAC4_REG_MMC_TXPAUSEFRAMES 0x0170
+#define FGMAC4_REG_MMC_TXVLANFRAMES_G 0x0174
+
+#define FGMAC4_REG_MMC_RXFRAMECOUNT_GB 0x0180
+#define FGMAC4_REG_MMC_RXOCTETCOUNT_GB 0x0184
+#define FGMAC4_REG_MMC_RXOCTETCOUNT_G 0x0188
+#define FGMAC4_REG_MMC_RXBROADCASTFRAMES_G 0x018C
+#define FGMAC4_REG_MMC_RXMULTICASTFRAMES_G 0x0190
+#define FGMAC4_REG_MMC_RXCRCERROR 0x0194
+#define FGMAC4_REG_MMC_RXALIGNMENTERROR 0x0198
+#define FGMAC4_REG_MMC_RXRUNTERROR 0x019C
+#define FGMAC4_REG_MMC_RXJABBERERROR 0x01A0
+#define FGMAC4_REG_MMC_RXUNDERSIZE_G 0x01A4
+#define FGMAC4_REG_MMC_RXOVERSIZE_G 0x01A8
+#define FGMAC4_REG_MMC_RX64OCTETS_GB 0x01AC
+#define FGMAC4_REG_MMC_RX65TO127OCTETS_GB 0x01B0
+#define FGMAC4_REG_MMC_RX128TO255OCTETS_GB 0x01B4
+#define FGMAC4_REG_MMC_RX256TO511OCTETS_GB 0x01B8
+#define FGMAC4_REG_MMC_RX512TO1023OCTETS_GB 0x01BC
+#define FGMAC4_REG_MMC_RX1024TOMAXOCTETS_GB 0x01C0
+#define FGMAC4_REG_MMC_RXUNICASTFRAMES_G 0x01C4
+#define FGMAC4_REG_MMC_RXLENGTHERROR 0x01C8
+#define FGMAC4_REG_MMC_RXOUTOFRANGETYPE 0x01CC
+#define FGMAC4_REG_MMC_RXPAUSEFRAMES 0x01D0
+#define FGMAC4_REG_MMC_RXFIFOOVERFLOW 0x01D4
+#define FGMAC4_REG_MMC_RXVLANFRAMES_GB 0x01D8
+#define FGMAC4_REG_MMC_RXWATCHDOGERROR 0x01DC
+
+#define FGMAC4_REG_MMC_IPC_INTR_MASK_RX 0x0200
+
+#define FGMAC4_REG_MMC_IPC_INTR_RX 0x0208
+
+#define FGMAC4_REG_MMC_RXIPV4_GB_FRMS 0x0210
+#define FGMAC4_REG_MMC_RXIPV4_HDRERR_FRMS 0x0214
+#define FGMAC4_REG_MMC_RXIPV4_NOPAY_FRMS 0x0218
+#define FGMAC4_REG_MMC_RXIPV4_FRAG_FRMS 0x021C
+#define FGMAC4_REG_MMC_RXIPV4_UDSBL_FRMS 0x0220
+#define FGMAC4_REG_MMC_RXIPV6_GB_FRMS 0x0224
+#define FGMAC4_REG_MMC_RXIPV6_HDRERR_FRMS 0x0228
+#define FGMAC4_REG_MMC_RXIPV6_NOPAY_FRMS 0x022C
+#define FGMAC4_REG_MMC_RXUDP_GB_FRMS 0x0230
+#define FGMAC4_REG_MMC_RXUDP_ERR_FRMS 0x0234
+#define FGMAC4_REG_MMC_RXTCP_GB_FRMS 0x0238
+#define FGMAC4_REG_MMC_RXTCP_ERR_FRMS 0x023C
+#define FGMAC4_REG_MMC_RXICMP_GB_FRMS 0x0240
+#define FGMAC4_REG_MMC_RXICMP_ERR_FRMS 0x0244
+
+#define FGMAC4_REG_MMC_RXIPV4_GB_OCTETS 0x0250
+#define FGMAC4_REG_MMC_RXIPV4_HDRERR_OCTETS 0x0254
+#define FGMAC4_REG_MMC_RXIPV4_NOPAY_OCTETS 0x0258
+#define FGMAC4_REG_MMC_RXIPV4_FRAG_OCTETS 0x025C
+#define FGMAC4_REG_MMC_RXIPV4_UDSBL_OCTETS 0x0260
+#define FGMAC4_REG_MMC_RXIPV6_GB_OCTETS 0x0264
+#define FGMAC4_REG_MMC_RXIPV6_HDRERR_OCTETS 0x0268
+#define FGMAC4_REG_MMC_RXIPV6_NOPAY_OCTETS 0x026C
+#define FGMAC4_REG_MMC_RXUDP_GB_OCTETS 0x0270
+#define FGMAC4_REG_MMC_RXUDP_ERR_OCTETS 0x0274
+#define FGMAC4_REG_MMC_RXTCP_GB_OCTETS 0x0278
+#define FGMAC4_REG_MMC_RXTCP_ERR_OCTETS 0x027C
+#define FGMAC4_REG_MMC_RXICMP_GB_OCTETS 0x0280
+#define FGMAC4_REG_MMC_RXICMP_ERR_OCTETS 0x0284
+
+/*
+ * Values and Masks
+ */
+#define SET_0 0x00000000
+#define SET_1 0xFFFFFFFF
+
+/* IMR : Interrupt Mask Register */
+#define FGMAC4_IMR_LPIIM 0x00000400 /* LPI Interrupt Mask */
+#define FGMAC4_IMR_TSIM 0x00000200 /* Time Stamp Interrupt Mask */
+#define FGMAC4_IMR_PIM 0x00000008 /* PMT Interrupt Mask */
+#define FGMAC4_IMR_RGIM 0x00000001 /* RGMII Interrupt Mask */
+
+/* MCR:MAC Configuration Register */
+#define FGMAC4_MCR_CST 0x02000000 /* CRC strip for Type frames */
+#define FGMAC4_MCR_TC 0x01000000 /* Tx Configuration in RGMII */
+#define FGMAC4_MCR_WD 0x00800000 /*Disable RX Watchdog timeout */
+#define FGMAC4_MCR_JD 0x00400000 /* Disable TX Jabber timer */
+#define FGMAC4_MCR_BE 0x00200000 /* Frame Burst Enable */
+#define FGMAC4_MCR_JE 0x00100000 /* Jumbo Frame Enable */
+#define FGMAC4_MCR_DCRS 0x00010000 /*Disable Carrier During Trans*/
+#define FGMAC4_MCR_PS 0x00008000 /* Port Select 0:GMII,1:MII */
+#define FGMAC4_MCR_FES 0x00004000 /* Speed */
+#define FGMAC4_MCR_DO 0x00002000 /* Disable Receive Own */
+#define FGMAC4_MCR_LM 0x00001000 /* Loop-back Mode */
+#define FGMAC4_MCR_DM 0x00000800 /* Duplex mode */
+#define FGMAC4_MCR_IPC 0x00000400 /* Cehcksum Offload */
+#define FGMAC4_MCR_DR 0x00000200 /* Disable Retry */
+#define FGMAC4_MCR_LUD 0x00000100 /* Link Up/Down */
+#define FGMAC4_MCR_BL_00 0x00000000 /* Back-off Limit is setted 0 */
+#define FGMAC4_MCR_DC 0x00000010 /* Deferral Check */
+#define FGMAC4_MCR_TX_ENABLE 0x00000008 /* Enable Transmitter */
+#define FGMAC4_MCR_RX_ENABLE 0x00000004 /* Enable Receiver */
+#define FGMAC4_MCR_IFG_MASK 0x000E0000
+#define FGMAC4_MCR_IFG_96 0x00000000
+#define FGMAC4_MCR_IFG_88 0x00020000
+#define FGMAC4_MCR_IFG_80 0x00040000
+#define FGMAC4_MCR_IFG_72 0x00060000
+#define FGMAC4_MCR_IFG_64 0x00080000
+#define FGMAC4_MCR_IFG_56 0x000A0000
+#define FGMAC4_MCR_IFG_48 0x000C0000
+#define FGMAC4_MCR_IFG_40 0x000E0000
+ /* bit15:PS(Port Select) */
+#define FGMAC4_MCR_GMII_PORT 0x00000000
+#define FGMAC4_MCR_MII_PORT 0x00008000
+ /* bit11:DM(Duplex mode) */
+#define FGMAC4_MCR_HALF_DUPLEX 0x00000000
+#define FGMAC4_MCR_FULL_DUPLEX 0x00000800
+
+/* GAR:GMII Address Register */
+#define FGMAC4_GAR_GW_R 0x00000000 /* GMII/MII Read */
+#define FGMAC4_GAR_GW_W 0x00000002 /* GMII/MII Write */
+#define FGMAC4_GAR_GB 0x00000001 /* GMII/MII Busy */
+#define FGMAC4_GAR_PA_SHIFT 11 /* PHY address bit field shift*/
+#define FGMAC4_GAR_GR_MASK 0x0000001F /* GMII register field mask */
+#define FGMAC4_GAR_GR_SHIFT 6 /* GMII register field shift */
+#define FGMAC4_GAR_CR_MASK 0x0000000F /* Clock range field mask */
+#define FGMAC4_GAR_CR_SHIFT 2 /* Clock range field shift */
+
+/* BMR:MDC Bus Mode Register */
+#define FGMAC4_BMR_TXPR 0x08000000 /* Tx Pririty Higher Than Rx */
+#define FGMAC4_BMR_MB 0x04000000 /* Mixed Burst */
+#define FGMAC4_BMR_AAL 0x02000000 /* Address-Aligned Beats */
+#define FGMAC4_BMR_8XPBL 0x01000000 /* MAX burst is 8times of PBL */
+#define FGMAC4_BMR_USP 0x00800000 /* Rx/TxDMA Use Separate PBL */
+#define FGMAC4_BMR_RPBL_32 0x00400000 /* RX Burst Length is 32 Bytes*/
+#define FGMAC4_BMR_RPBL_16 0x00200000 /* RX Burst Length is 16 Bytes*/
+#define FGMAC4_BMR_RPBL_8 0x00100000 /* RX Burst Length is 8 Bytes */
+#define FGMAC4_BMR_RPBL_4 0x00080000 /* RX Burst Length is 4 Bytes */
+#define FGMAC4_BMR_RPBL_2 0x00040000 /* RX Burst Length is 2 Bytes */
+#define FGMAC4_BMR_RPBL_1 0x00020000 /* RX Burst Length is 1 Bytes */
+#define FGMAC4_BMR_FB 0x00010000 /* AHB Fixed Burst Mode */
+#define FGMAC4_BMR_PR_00 0x00000000 /* RX TX Priority ratio is 1:1*/
+#define FGMAC4_BMR_PR_01 0x00004000 /* RX TX Priority ratio is 2:1*/
+#define FGMAC4_BMR_PR_10 0x00008000 /* RX TX Priority ratio is 3:1*/
+#define FGMAC4_BMR_PR_11 0x0000C000 /* RX TX Priority ratio is 4:1*/
+#define FGMAC4_BMR_PBL_32 0x00002000 /* Burst Length is 32 Bytes */
+#define FGMAC4_BMR_PBL_16 0x00001000 /* Burst Length is 16 Bytes */
+#define FGMAC4_BMR_PBL_8 0x00000800 /* Burst Length is 8 bytes */
+#define FGMAC4_BMR_PBL_4 0x00000400 /* Burst Length is 4 Bytes */
+#define FGMAC4_BMR_PBL_2 0x00000200 /* Burst Length is 2 Bytes */
+#define FGMAC4_BMR_PBL_1 0x00000100 /* Burst Length is 1 Bytes */
+#define FGMAC4_BMR_ATDS 0x00000080 /* Alternate Descriptor Size */
+#define FGMAC4_BMR_DSL 0x00000000 /* Descripter Skip Length */
+#define FGMAC4_BMR_DA 0x00000002 /* RX have priority */
+#define FGMAC4_BMR_SOFTWARE_RESET 0x00000001 /* software reset */
+
+/* OMR:MDC Operation Mode Register */
+#define FGMAC4_OMR_RSF 0x02000000 /* RX after whole frame in FIFO */
+#define FGMAC4_OMR_TSF 0x00200000 /* TX after whole frame in FIFO */
+#define FGMAC4_OMR_START_TX 0x00002000 /* Start Transmissin */
+#define FGMAC4_OMR_START_RX 0x00000002 /* Start Receive */
+#define FGMAC4_OMR_TTC_64B 0x00000000 /* TX after 64byte written in FIFO*/
+#define FGMAC4_OMR_TTC_128B 0x00004000 /*TX after 128byte written in FIFO*/
+#define FGMAC4_OMR_TTC_192B 0x00008000 /*TX after 192byte written in FIFO*/
+#define FGMAC4_OMR_TTC_256B 0x0000C000 /*TX after 256byte written in FIFO*/
+#define FGMAC4_OMR_TTC_40B 0x00010000 /* TX after 40byte written in FIFO*/
+#define FGMAC4_OMR_TTC_32B 0x00014000 /* TX after 32byte written in FIFO*/
+#define FGMAC4_OMR_TTC_24B 0x00018000 /* TX after 24byte written in FIFO*/
+#define FGMAC4_OMR_TTC_16B 0x0001C000 /* TX after 16byte written in FIFO*/
+
+/* IER:MDC Interrupt Enable Register */
+#define FGMAC4_IER_NIE 0x00010000 /* Normal Interrupt Summary Enable */
+#define FGMAC4_IER_AIE 0x00008000 /* Abnormal Interrupt Summary Enable */
+#define FGMAC4_IER_ERE 0x00004000 /* Early Receive Interrupt Enable */
+#define FGMAC4_IER_FBE 0x00002000 /* Fatal Bus Error Enable */
+#define FGMAC4_IER_ETE 0x00000400 /* Early Transmit Interrupt Enable */
+#define FGMAC4_IER_RWE 0x00000200 /*Receive Watchdog Timeout Enable */
+#define FGMAC4_IER_RSE 0x00000100 /* Receive Process Stopped Enable */
+#define FGMAC4_IER_RUE 0x00000080 /* Receive Buffer Unavailable Enable */
+#define FGMAC4_IER_RIE 0x00000040 /* Receive Interrupt Enable */
+#define FGMAC4_IER_UNE 0x00000020 /* Transmit underflow Enable */
+#define FGMAC4_IER_OVE 0x00000010 /* Receive Overflow Enable */
+#define FGMAC4_IER_TJE 0x00000008 /* Transmit Jabber Timeout */
+#define FGMAC4_IER_TUE 0x00000004 /* Transmit Buffer Unavailable */
+#define FGMAC4_IER_TSE 0x00000002 /* Transmit Process Stopped */
+#define FGMAC4_IER_TIE 0x00000001 /* Transmit Interrupt */
+
+/* PMTR:PMT Register */
+#define FGMAC4_PMTR_WFE 0x00000004 /* Wake-Up Frame Enable */
+#define FGMAC4_PMTR_MPE 0x00000002 /* Magic Packet Enable */
+
+
+/* Descriptor Status */
+#define OWN_BIT 0x80000000 /* Own bit */
+
+#define FGMAC4_RDES1_DIC 0x80000000 /* Disable Interrupt on Completion */
+#define FGMAC4_RDES1_RER 0x00008000 /* Receive End of Ring */
+
+#define FGMAC4_TDES0_LS 0x20000000 /* Last Segment */
+#define FGMAC4_TDES0_FS 0x10000000 /* First Segment */
+#define FGMAC4_TDES0_TER 0x00200000 /* Transmit End of Ring */
+
+/* RX descriptor error status
+ * ES[bit15]:Error Summary
+ * DE[bit14]:Descriptor Error
+ * SAF[bit13]:Source Address Filter Fail
+ * LE[bit12]:Length Error
+ * OE[bit11]:Overflow Error
+ * RWT[bit4]:Receive watchdog timeout
+ * RE[bit3]:Receive Error
+ * DE[bit2]:Dribble Bit Error
+ * CE[bit1]:CRC Error
+ */
+#define FGMAC4_RX_DESC_ERR 0x0000F81E
+
+
+/* Tx/Rx descriptor definition */
+struct fgmac4_desc {
+ volatile u32 opts1;
+ volatile u32 opts2;
+ u32 addr1;
+ u32 addr2;
+
+ /* for rx descriptor, this is extended status descriptor;
+ * for tx descriptor, this is a reserved descriptor.
+ */
+ volatile u32 ex_status_rsv;
+ u32 reserved; /* reserved */
+ volatile u32 time_stmp_low; /* time stamp low */
+ volatile u32 time_stmp_high; /* time stamp high */
+};
+
+/* PHY information */
+struct fgmac4_phy_info {
+ u32 adv;
+ u32 speed;
+ u32 duplex;
+ u32 autoneg;
+ u16 phy_addr;
+};
+
+/* Private information */
+struct eth_info {
+ int mdc_clk; /* MDC clock */
+ struct fgmac4_phy_info phy_info;/* PHY info */
+
+ dma_addr_t ring_dma; /* base address of descriptor memory */
+ struct fgmac4_desc *rx_ring; /* RX Desc ring's pointer */
+ struct fgmac4_desc *tx_ring; /* TX Desc ring's pointer */
+ unsigned char* rx_buf_array; /* RX buffer pointer */
+ unsigned char* tx_buf_array; /* TX buffer pointer */
+ u32 rx_ring_num; /* Current RX desc number */
+ u32 tx_ring_num; /* Current TX desc number */
+ u32 rx_buf_sz; /* MAX size of socket buffer */
+
+ struct eth_device netdev;
+};
+
+#endif /* CONFIG_DRIVER_FGMAC4 */
+
+#endif /* __FGMAC4_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma.c u-boot/drivers/net/ogma.c
--- original/u-boot-linaro-stable/drivers/net/ogma.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma.c 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,790 @@
+/*
+ * u-boot/drivers/net/ogma.c
+ *
+ * Copyright (C) 2010-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "ogma.h"
+
+//#define OGMA_DEBUG 1
+
+#ifdef OGMA_DEBUG
+void dump_taiki_reg(void);
+#define OGMA_LOG 1
+#endif
+
+#ifdef OGMA_LOG
+#define ogma_print printf
+#else
+#define ogma_print(fmt, args...)
+#endif
+
+/*
+ * Bit field definitions for PHY status register
+ */
+#define OGMA_PHY_SR_REG_AN_C (0x0020U)
+#define OGMA_PHY_SR_REG_LINK (0x0004U)
+
+
+/*
+ * Bit field definitions for PHY 1000Base status register
+ */
+#define OGMA_PHY_1000BASE_REG_FULL (0x0800U)
+
+/*
+ * Bit field definitions for PHY ANLPA/ANA register
+ */
+#define OGMA_PHY_ANLPA_REG_TXF (0x0100U)
+#define OGMA_PHY_ANLPA_REG_TXD (0x0080U)
+#define OGMA_PHY_ANLPA_REG_TF (0x0040U)
+#define OGMA_PHY_ANLPA_REG_TD (0x0020U)
+
+/*
+ * Bit field definitions for PHY ctrl register
+ */
+#define OGMA_PHY_CTRL_REG_RESET (1U << 15)
+#define OGMA_PHY_CTRL_REG_LOOPBACK (1U << 14)
+#define OGMA_PHY_CTRL_REG_SPSEL_LSB (1U << 13)
+#define OGMA_PHY_CTRL_REG_AUTO_NEGO_EN (1U << 12)
+#define OGMA_PHY_CTRL_REG_POWER_DOWN (1U << 11)
+#define OGMA_PHY_CTRL_REG_ISOLATE (1U << 10)
+#define OGMA_PHY_CTRL_REG_RESTART_AUTO_NEGO (1U << 9)
+#define OGMA_PHY_CTRL_REG_DUPLEX_MODE (1U << 8)
+#define OGMA_PHY_CTRL_REG_COL_TEST (1U << 7)
+#define OGMA_PHY_CTRL_REG_SPSEL_MSB (1U << 6)
+#define OGMA_PHY_CTRL_REG_UNIDIR_EN (1U << 5)
+
+/*
+ * Bit field definitions for PHY MASTER-SLAVE Ctrl register
+ */
+#define OGMA_PHY_MSC_REG_1000BASE_FULL (1U << 9)
+
+/**
+ * PHY register offset constants
+ */
+#define OGMA_PHY_REG_ADDR_CTRL (0U)
+#define OGMA_PHY_REG_ADDR_SR (1U)
+#define OGMA_PHY_REG_ADDR_ANA (4U)
+#define OGMA_PHY_REG_ADDR_ANLPA (5U)
+#define OGMA_PHY_REG_ADDR_MSC (9U)
+#define OGMA_PHY_REG_ADDR_1000BASE_SR (10U)
+
+#define OGMA_RX_DESC_BASE CONFIG_DRIVER_OGMA_BUF_START
+#define OGMA_RX_BUF_ADDR (OGMA_RX_DESC_BASE + 0x00100000)
+#define OGMA_TX_DESC_BASE (OGMA_RX_BUF_ADDR - 16)
+
+#define OGMA_RX_PKT_BUF_LEN 1522
+#define RX_DESC_NUM 250
+
+#if ((OGMA_RX_DESC_BASE + RX_DESC_NUM * 16 > OGMA_TX_DESC_BASE) || (OGMA_RX_BUF_ADDR + RX_DESC_NUM * 2048 >= CONFIG_DRIVER_OGMA_BUF_END))
+#error "RX_DESC_NUM too large"
+#endif
+
+ogma_ctrl_t *ctrl_p;
+
+u32 rx_count = 0;
+
+
+static struct eth_info ogma_info;
+
+u8 phy_dev_addr = 1;
+
+unsigned int flow_ctrl_start_threshold = 36;
+unsigned int flow_ctrl_stop_threshold = 48;
+unsigned short pause_time = 256;
+int flow_ctrl = 0;
+unsigned int ogma_phy_interface = OGMA_PHY_INTERFACE_RGMII;
+
+static u32 scb_set_pkt_ctrl_reg_value = 0;
+static u32 scb_set_normal_tx_phys_addr = 0;
+
+static int ogma_write_hwaddr(struct eth_device *netdev)
+{
+ /* Mac Add = UU:VV:WW:XX:YY:ZZ
+ * MAR0H = 32'h0000ZZYY
+ * MAR0L = 32'hXXWWVVUU
+ */
+
+ /* The validation of enetaddr is guaranteed by eth_initialize */
+ unsigned char* mac_addr = netdev->enetaddr;
+
+ printf(" MAC=%x:%x:%x:%x:%x:%x ",mac_addr[0], mac_addr[1],
+ mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+
+ return 0;
+}
+
+static unsigned long ogma_calc_pkt_ctrl_reg_param (void)
+{
+ unsigned long param = OGMA_PKT_CTRL_REG_MODE_NRM;
+
+ /* don't need other parameters for U-Boot */
+
+ return param;
+}
+
+static void ogma_netdev_get_phy_link_status(
+ unsigned int *link_status_flag_p,
+ unsigned int *auto_nego_complete_flag_p,
+ unsigned int *latched_link_down_flag_p,
+ unsigned int *link_speed_p,
+ unsigned int *half_duplex_flag_p
+)
+{
+
+ unsigned short reg_val_sr, reg_val_ana, reg_val_anlpa, reg_val_msc, reg_val_mss;
+ unsigned short common_settings;
+
+ *link_status_flag_p = 0;
+ *auto_nego_complete_flag_p = 0;
+ *latched_link_down_flag_p = 0;
+ *link_speed_p = OGMA_PHY_LINK_SPEED_10M;
+ *half_duplex_flag_p = 0;
+
+ /* Read PHY status register */
+ reg_val_sr =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_SR);
+
+ if ((reg_val_sr & OGMA_PHY_SR_REG_LINK) == 0) {
+ /*
+ * Read PHY status register again to obtain up-to-date link status,
+ */
+ *latched_link_down_flag_p = 1;
+
+ reg_val_sr =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_SR);
+ }
+
+ if ((reg_val_sr & OGMA_PHY_SR_REG_LINK) != 0) {
+ *link_status_flag_p = 1;
+ }
+
+ if ((reg_val_sr & OGMA_PHY_SR_REG_AN_C) != 0) {
+ *auto_nego_complete_flag_p = 1;
+ }
+
+ /*
+ * Determine link speed and duplex
+ */
+ if (((*link_status_flag_p) == 1) && ((*auto_nego_complete_flag_p) == 1)) {
+
+ /* Read Auto-Negotiation Advertisement register */
+ reg_val_ana =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_ANA);
+
+ /* Read Auto-Negotiation Link Partner Base Page Ability register */
+ reg_val_anlpa =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_ANLPA);
+
+ /* Read MASTER-SLAVE Control register */
+ reg_val_msc =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_MSC);
+
+ /* Read MASTER-SLAVE Status register (1000Base status) */
+ reg_val_mss =
+ ogma_get_phy_reg(phy_dev_addr,
+ OGMA_PHY_REG_ADDR_1000BASE_SR);
+
+ /* Determine negotiation results */
+ if (((reg_val_msc & OGMA_PHY_MSC_REG_1000BASE_FULL) != 0) &&
+ ((reg_val_mss & OGMA_PHY_1000BASE_REG_FULL) != 0)) {
+
+ *link_speed_p = OGMA_PHY_LINK_SPEED_1G;
+
+ } else {
+
+ common_settings = (reg_val_ana & reg_val_anlpa);
+
+ if (common_settings & OGMA_PHY_ANLPA_REG_TXF) {
+ *link_speed_p = OGMA_PHY_LINK_SPEED_100M;
+ } else if (common_settings & OGMA_PHY_ANLPA_REG_TXD) {
+ *link_speed_p = OGMA_PHY_LINK_SPEED_100M;
+ *half_duplex_flag_p = 1;
+ } else if (common_settings & OGMA_PHY_ANLPA_REG_TF) {
+ *link_speed_p = OGMA_PHY_LINK_SPEED_10M;
+ } else { /* OGMA_PHY_ANLPA_REG_TD */
+ *link_speed_p = OGMA_PHY_LINK_SPEED_10M;
+ *half_duplex_flag_p = 1;
+ }
+
+ }
+
+ } /* if (((*link_status_flag_p) == 1) && ((*auto_nego_complete_flag_p) == 1)) */
+
+}
+
+static ogma_err_t ogma_netdev_configure_mac(
+ int link_speed,
+ int half_duplex_flag
+ )
+{
+
+ unsigned int ogma_err;
+ ogma_gmac_mode_t ogma_gmac_mode;
+
+ memset(&ogma_gmac_mode, 0, sizeof(ogma_gmac_mode_t));
+
+ ogma_gmac_mode.link_speed = link_speed;
+ ogma_gmac_mode.half_duplex_flag = (int)half_duplex_flag;
+ ogma_gmac_mode.flow_ctrl_enable_flag = (int)flow_ctrl;
+ ogma_gmac_mode.flow_ctrl_start_threshold =
+ (u16)flow_ctrl_start_threshold;
+ ogma_gmac_mode.flow_ctrl_stop_threshold =
+ (u16)flow_ctrl_stop_threshold;
+/*
+ ogma_err =
+ ogma_stop_gmac(1, 1);
+ if (ogma_err != OGMA_ERR_OK) {
+ printf("ogma_stop_gmac() failed with error status %d\n", ogma_err);
+ goto out;
+ }
+
+ ogma_err = ogma_set_gmac_mode(&ogma_gmac_mode);
+ if (ogma_err != OGMA_ERR_OK) {
+ printf("ogma_set_gmac() failed with error status %d\n", ogma_err);
+ goto out;
+ }
+*/
+ ogma_err =
+ ogma_start_gmac(1, 1);
+ if (ogma_err != OGMA_ERR_OK) {
+ printf("ogma_start_gmac() failed with error status %d\n", ogma_err);
+ goto out;
+ }
+
+ //dump_taiki_reg();
+
+out:
+ return ogma_err;
+
+}
+
+#define LINKUP_WAIT_TIMEOUT 5
+/**
+ * Check PHY link status and configure F_GMAC4MT if necessary.
+ */
+static int ogma_netdev_phy_poll(void)
+{
+
+ unsigned int link_status_flag;
+ unsigned int auto_nego_complete_flag;
+ unsigned int latched_link_down_flag;
+ unsigned int link_speed;
+ unsigned half_duplex_flag;
+
+ unsigned long ogma_err;
+ int timeout;
+
+ for ( timeout = 0; timeout < LINKUP_WAIT_TIMEOUT; timeout++) {
+ ogma_netdev_get_phy_link_status(
+ &link_status_flag,
+ &auto_nego_complete_flag,
+ &latched_link_down_flag,
+ &link_speed,
+ &half_duplex_flag);
+
+ if ( (link_status_flag != 0) && (auto_nego_complete_flag != 0) ) {
+ break;
+ }
+ mdelay(1000);
+ }
+
+ if ( (link_status_flag == 0) || (auto_nego_complete_flag == 0) ) {
+ printf("Network is linkdown\n");
+ return -ETIME;
+ }
+
+ ctrl_p->gmac_mode.half_duplex_flag = half_duplex_flag;
+ ctrl_p->gmac_mode.link_speed = link_speed;
+
+#if OGMA_DEBUG
+ ogma_print("link status: %i\n", link_status_flag);
+ ogma_print("auto nego complete: %i\n", auto_nego_complete_flag);
+ ogma_print("latched link down: %i\n", latched_link_down_flag);
+ ogma_print("link speed: %i\n", link_speed);
+ ogma_print("half duplex: %i\n", half_duplex_flag);
+#endif
+
+ /*
+ * Configure GMAC if link is up and auto negotiation is complete.
+ */
+ if ((ogma_err = ogma_netdev_configure_mac(
+ link_speed,
+ half_duplex_flag))
+ != OGMA_ERR_OK) {
+ printf("ogma_netdev_configure_mac() failed");
+ link_status_flag = auto_nego_complete_flag = 0;
+ return -EBUSY;
+ }
+
+
+ /* Update saved PHY status */
+// ogma_netdev_p->prev_link_status_flag = link_status_flag;
+// ogma_netdev_p->prev_auto_nego_complete_flag = auto_nego_complete_flag;
+ return 0;
+}
+
+static int stopped = 1;
+
+static int ogma_netdev_open(void)
+{
+ int err = 0;
+
+ //Tx channel int enable
+ ogma_write_reg(OGMA_REG_ADDR_NRM_TX_INTEN, 1<<17);
+
+#ifdef OGMA_DEBUG
+ unsigned long value;
+ value = ogma_read_reg(OGMA_REG_ADDR_NRM_TX_INTEN);
+ ogma_print("Tx int enable=0x%x\n", value);
+#endif
+
+ //Tx packet count int
+ ogma_write_reg(OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT, 1);
+
+
+ //Rx channel int enable
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_INTEN, 1 << 15);
+
+#ifdef OGMA_DEBUG
+ value = ogma_read_reg(OGMA_REG_ADDR_NRM_RX_INTEN);
+ ogma_print("Rx int enable=0x%x\n", value);
+#endif
+
+ //Rx packet count int
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT, 1);
+
+
+#ifdef OGMA_DEBUG
+ //Top interrent enable status
+ value = ogma_read_reg(OGMA_REG_ADDR_TOP_INTEN);
+ ogma_print("top status int enable 1=0x%x\n",value);
+#endif
+
+ ogma_write_reg(OGMA_REG_ADDR_TOP_INTEN_SET, 3);
+
+#ifdef OGMA_DEBUG
+ value = ogma_read_reg(OGMA_REG_ADDR_TOP_INTEN);
+ ogma_print("top status int enable 2=0x%x\n", value);
+#endif
+
+// ogma_write_reg(OGMA_REG_ADDR_TOP_STATUS, 3);
+
+
+ if ( ( err = ogma_netdev_phy_poll() ) == 0) {
+
+ ogma_print("f_taiki initialized\n");
+ } else {
+ ogma_print("f_taiki initialized error.\n");
+ }
+
+ stopped = 0;
+
+ return err;
+}
+
+#define WAIT_FW_RDY_TIMEOUT 50
+
+static int ogma_init(struct eth_device *netdev, bd_t *bd)
+{
+ unsigned int ogma_err = 1;
+ unsigned long value;
+ int timeout;
+
+ ctrl_p = (ogma_ctrl_t *)malloc(sizeof(ogma_ctrl_t));
+
+ ogma_write_reg( OGMA_REG_ADDR_CLK_EN,
+ OGMA_CLK_EN_REG_DOM_G | OGMA_CLK_EN_REG_DOM_C | OGMA_CLK_EN_REG_DOM_D);
+
+ /* save the descriptor start address for scb */
+ scb_set_normal_tx_phys_addr = ogma_read_reg(OGMA_REG_ADDR_NRM_TX_DESC_START);
+
+ /* setup descriptor start address */
+ ogma_write_reg(OGMA_REG_ADDR_NRM_TX_DESC_START, OGMA_TX_DESC_BASE);
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_DESC_START, OGMA_RX_DESC_BASE);
+
+ /* set pkt desc ring config */
+ value =
+ ( 0x0UL /*ctrl_p->normal_mode_hwconf.rx_tmr_mode_flag*/ <<
+ OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
+ ( 0x1UL /*ctrl_p->normal_mode_hwconf.rx_little_endian_flag*/ <<
+ OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) |
+ ( 0x1UL << OGMA_REG_DESC_RING_CONFIG_CFG_UP) |
+ ( 0x1UL <cksum_offload_flag*/ <<
+ OGMA_TX_PKT_DESC_RING_CO_FIELD) |
+ ( 0/*tx_pkt_ctrl_p->tcp_seg_offload_flag*/ << OGMA_TX_PKT_DESC_RING_SO_FIELD) |
+ ( 1U << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
+
+ //printf("tx_idx=%d\n",tx_idx);
+ *((unsigned int*)(OGMA_TX_DESC_BASE + tx_idx*16)) = attr;
+ *((unsigned int*)(OGMA_TX_DESC_BASE + tx_idx*16 + 4)) = (unsigned int)packet;
+ *((unsigned int*)(OGMA_TX_DESC_BASE + tx_idx*16 + 8)) = length;
+
+ /* Make sure all needed operations were finished before starting trasmit */
+ flush_dcache_range((unsigned long)packet, (unsigned long)packet + (unsigned long)length);
+ dmb();
+
+ ogma_write_reg(OGMA_REG_ADDR_NRM_TX_PKTCNT, 1);
+
+ do {
+ value = ogma_read_reg(OGMA_REG_ADDR_TOP_STATUS);
+ udelay(50);
+ } while (!(value & 0x1));
+
+#ifdef OGMA_DEBUG
+ value = ogma_read_reg(OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT);
+ ogma_print("Tx done=0x%x\n",value);
+ value = ogma_read_reg(OGMA_REG_ADDR_NRM_TX_STATUS);
+ ogma_print("Tx status=0x%x\n",value);//Check bit 6,7. It should be 00
+#endif
+
+ //Clear
+ value = (OGMA_CH_IRQ_REG_EMPTY & ( OGMA_CH_IRQ_REG_EMPTY | OGMA_CH_IRQ_REG_ERR));
+ ogma_write_reg(OGMA_REG_ADDR_NRM_TX_STATUS, value);
+
+#ifdef OGMA_DEBUG
+ ogma_print("ogma_send done\n");
+#endif
+
+ return 0;
+}
+
+
+static int ogma_rx(struct eth_device *netdev)
+{
+ u32 i, rx_num;
+ u32 value, len, top_status;
+ unsigned char * buf;
+
+ top_status = ogma_read_reg(OGMA_REG_ADDR_TOP_STATUS);
+
+ if (top_status & 0x2)
+ {
+ rx_num = ogma_read_reg(OGMA_REG_ADDR_NRM_RX_PKTCNT);
+ ogma_print("rx_num=%d\n",rx_num);
+ if (rx_num > 0)
+ {
+ for (i=0; i> 16 ;// len
+
+ ogma_print("info=0x%x\n",value);
+ ogma_print("buf=0x%x\n",buf);
+ ogma_print("rlen=%d\n",len);
+ NetReceive(buf, len);
+
+ value = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
+
+ if ( rx_count == (RX_DESC_NUM-1) )
+ value |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+
+ *((unsigned int*)(OGMA_RX_DESC_BASE + rx_count*16)) = value;
+ *((unsigned int*)(OGMA_RX_DESC_BASE + rx_count*16 + 4)) = OGMA_RX_BUF_ADDR + rx_count*2048;//2k
+ *((unsigned int*)(OGMA_RX_DESC_BASE + rx_count*16 + 8)) = OGMA_RX_PKT_BUF_LEN;
+
+ rx_count++;
+ //printf("rx_count=%d\n",rx_count);
+ if (rx_count == RX_DESC_NUM)
+ rx_count = 0;
+
+ }
+
+ }
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_STATUS, 1 << 15);
+ //ogma_write_reg(OGMA_REG_ADDR_TOP_STATUS, 0x3);
+
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT, 1);
+
+ ogma_write_reg(OGMA_REG_ADDR_NRM_RX_INTEN, 1 << 15);
+ }
+
+ return 0;
+}
+
+int ogma_initialize(bd_t *bis)
+{
+ int ret;
+ struct eth_device *dev = &(ogma_info.netdev);
+
+ dev->init = ogma_init;
+ dev->halt = ogma_halt;
+ dev->send = ogma_send;
+ dev->recv = ogma_rx;
+ dev->write_hwaddr = ogma_write_hwaddr;
+ sprintf(dev->name, "f_taiki");
+
+ ret = eth_register(dev);
+ return ret;
+}
+
+#ifdef OGMA_DEBUG
+void dump_taiki_reg(void)
+{
+ printf("OGMA_REG_ADDR_TOP_STATUS=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_TOP_STATUS));
+ printf("OGMA_REG_ADDR_TOP_INTEN=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_TOP_INTEN));
+ printf("OGMA_REG_ADDR_TOP_INTEN_SET=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_TOP_INTEN_SET));
+ printf("OGMA_REG_ADDR_TOP_INTEN_CLR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_TOP_INTEN_CLR));
+ printf("OGMA_REG_ADDR_NRM_TX_STATUS=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_STATUS));
+ printf("OGMA_REG_ADDR_NRM_TX_INTEN=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_INTEN));
+ printf("OGMA_REG_ADDR_NRM_TX_INTEN_SET=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_INTEN_SET));
+ printf("OGMA_REG_ADDR_NRM_TX_INTEN_CLR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_INTEN_CLR));
+ printf("OGMA_REG_ADDR_NRM_TX_INTEN_CLR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_INTEN_CLR));
+ printf("OGMA_REG_ADDR_NRM_RX_STATUS=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_STATUS));
+ printf("OGMA_REG_ADDR_NRM_RX_INTEN=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_INTEN));
+ printf("OGMA_REG_ADDR_NRM_RX_INTEN_SET=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_INTEN_SET));
+ printf("OGMA_REG_ADDR_NRM_RX_INTEN_CLR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_INTEN_CLR));
+ printf("OGMA_REG_ADDR_PKTC_CMD_BUF=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_PKTC_CMD_BUF));
+ printf("OGMA_REG_ADDR_DMAC_HM_CMD_BUF=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DMAC_HM_CMD_BUF));
+ printf("OGMA_REG_ADDR_DMAC_MH_CMD_BUF=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DMAC_MH_CMD_BUF));
+ printf("OGMA_REG_ADDR_DIS_CORE=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DIS_CORE));
+ printf("OGMA_REG_ADDR_CLK_EN=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_CLK_EN));
+ printf("OGMA_REG_ADDR_SOFT_RST=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_SOFT_RST));
+ printf("OGMA_REG_ADDR_PKT_CTRL=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_PKT_CTRL));
+ printf("OGMA_REG_ADDR_COM_INIT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_COM_INIT));
+ printf("OGMA_REG_ADDR_DMA_TMR_CTRL=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DMA_TMR_CTRL));
+ printf("OGMA_REG_ADDR_F_TAIKI_MC_VER=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_F_TAIKI_MC_VER));
+ printf("OGMA_REG_ADDR_F_TAIKI_VER=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_F_TAIKI_VER));
+ printf("OGMA_REG_ADDR_DMA_HM_CTRL=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DMA_HM_CTRL));
+ printf("OGMA_REG_ADDR_DMA_MH_CTRL=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_DMA_MH_CTRL));
+ printf("OGMA_REG_ADDR_NRM_TX_PKTCNT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_PKTCNT));
+ printf("OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT));
+ printf("OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT));
+ printf("OGMA_REG_ADDR_NRM_TX_TXINT_TMR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_TXINT_TMR));
+ printf("OGMA_REG_ADDR_NRM_RX_RXINT_TMR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_RXINT_TMR));
+ printf("OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT));
+ printf("OGMA_REG_ADDR_NRM_RX_PKTCNT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_PKTCNT));
+ printf("OGMA_REG_ADDR_NRM_TX_TMR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_TMR));
+ printf("OGMA_REG_ADDR_NRM_RX_TMR=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_TMR));
+ printf("OGMA_REG_ADDR_NRM_TX_DESC_START=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_DESC_START));
+ printf("OGMA_REG_ADDR_NRM_RX_DESC_START=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_DESC_START));
+ printf("OGMA_REG_ADDR_RESERVED_RX_DESC_START=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_RESERVED_RX_DESC_START));
+ printf("OGMA_REG_ADDR_RESERVED_TX_DESC_START=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_RESERVED_TX_DESC_START));
+ printf("OGMA_REG_ADDR_NRM_TX_CONFIG=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_TX_CONFIG));
+ printf("OGMA_REG_ADDR_NRM_RX_CONFIG=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_NRM_RX_CONFIG));
+ printf("OGMA_REG_ADDR_MAC_DATA=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_DATA));
+ printf("OGMA_REG_ADDR_MAC_CMD=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_CMD));
+ printf("OGMA_REG_ADDR_MAC_FLOW_TH=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_FLOW_TH));
+ printf("OGMA_REG_ADDR_MAC_INTF_SEL=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_INTF_SEL));
+ printf("OGMA_REG_ADDR_MAC_REG_BASE=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_REG_BASE));
+ printf("OGMA_REG_ADDR_MAC_DESC_INIT=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_DESC_INIT));
+ printf("OGMA_REG_ADDR_MAC_DESC_SOFT_RST=0x%x\n", ogma_read_reg(OGMA_REG_ADDR_MAC_DESC_SOFT_RST));
+}
+#endif /* OGMA_DEBUG */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma.h u-boot/drivers/net/ogma.h
--- original/u-boot-linaro-stable/drivers/net/ogma.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma.h 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,67 @@
+/**
+ * ogma.h
+ *
+ * Copyright (c) 2012 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#ifndef OGMA_H
+#define OGMA_H
+
+#include
+#include
+#include
+#include
+#include "ogma_reg.h"
+#include "ogma_reg_f_taiki.h"
+#include "ogma_reg_f_gmac_4mt.h"
+#include "ogma_basic_access.h"
+#include "ogma_config.h"
+#include "ogma_internal.h"
+
+struct eth_info {
+ int mdc_clk; /* MDC clock */
+// struct fgmac4_phy_info phy_info;/* PHY info */
+
+ dma_addr_t ring_dma; /* base address of descriptor memory */
+// struct fgmac4_desc *rx_ring; /* RX Desc ring's pointer */
+// struct fgmac4_desc *tx_ring; /* TX Desc ring's pointer */
+ unsigned char* rx_buf_array; /* RX buffer pointer */
+ unsigned char* tx_buf_array; /* TX buffer pointer */
+ u32 rx_ring_num; /* Current RX desc number */
+ u32 tx_ring_num; /* Current TX desc number */
+ u32 rx_buf_sz; /* MAX size of socket buffer */
+
+ struct eth_device netdev;
+};
+
+static __inline void ogma_write_reg (
+ unsigned long reg_addr,
+ unsigned long value
+ )
+{
+ writel(value, (unsigned long *)(F_TAIKI_BASE + (reg_addr << 2)));
+}
+
+static __inline unsigned long ogma_read_reg (
+ unsigned long reg_addr
+ )
+{
+ return readl((unsigned long *)(F_TAIKI_BASE + (reg_addr << 2)));
+}
+
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_api.h u-boot/drivers/net/ogma_api.h
--- original/u-boot-linaro-stable/drivers/net/ogma_api.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_api.h 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,292 @@
+/**
+ * ogma_api.h
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef OGMA_API_H
+#define OGMA_API_H
+
+#include
+#include "ogma_config.h"
+
+/**
+ * Check configuration macro settings.
+ */
+
+#ifdef OGMA_CONFIG_CLK_HZ
+#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
+#error "OGMA_CONFIG_CLK_HZ is not appropriate."
+#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
+#else /* ! OGMA_CONFIG_CLK_HZ */
+#error "OGMA_CONFIG_CLK_HZ is not given."
+#endif /* OGMA_CONFIG_CLK_HZ */
+
+#ifndef OGMA_CONFIG_GMAC_CLK_HZ
+#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
+#endif
+
+/**
+ * Number of Common Descriptor ring id
+ */
+#define OGMA_DESC_RING_ID_NRM_TX 0
+#define OGMA_DESC_RING_ID_NRM_RX 1
+#define OGMA_DESC_RING_ID_RESERVED_RX 2
+#define OGMA_DESC_RING_ID_RESERVED_TX 3
+#define OGMA_DESC_RING_ID_GMAC 15
+#define OGMA_DESC_RING_ID_MAX 3
+
+
+/**
+ * Numbre of TCP Segmentation length limits
+ */
+#define OGMA_TCP_SEG_LEN_MAX 1460
+#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
+#define OGMA_TCP_SEG_LEN_MIN 536
+
+/**
+ * Number of checksum calculation result for received packet
+ */
+#define OGMA_RX_CKSUM_RESULT_OK 0x1
+#define OGMA_RX_CKSUM_RESULT_NG 0x2
+#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
+
+/**
+ * Number of top interrupt enable register bit field
+ */
+#define OGMA_TOP_IRQ_REG_CODE_LOAD_END (1UL << 20)
+#define OGMA_TOP_IRQ_REG_NRM_RX (1UL << 1)
+#define OGMA_TOP_IRQ_REG_NRM_TX (1UL << 0)
+
+
+/**
+ * Number of top channel enable register bit field
+ */
+#define OGMA_CH_IRQ_REG_EMPTY (1UL << 17)
+#define OGMA_CH_IRQ_REG_ERR (1UL << 16)
+#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
+#define OGMA_CH_IRQ_REG_TIMEUP (1UL << 14)
+#define OGMA_CH_IRQ_REG_RCV (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
+
+/**
+ * Number of top channel enable register bit field for F_TAIKI
+ */
+#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
+#define OGMA_CH_IRQ_REG_SND (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
+
+/**
+ * Number of mode trans comp irq enable register bit field
+ */
+#define OGMA_MODE_TRANS_COMP_IRQ_N2T (1UL << 20)
+#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
+
+/**
+ * Number of various limits
+ */
+#define OGMA_DESC_ENTRY_NUM_MIN 2
+#define OGMA_DESC_ENTRY_NUM_MAX 2047
+#define OGMA_INT_PKTCNT_MAX 2047
+
+
+/**
+ * Number of ogma phy interface setting
+ */
+#define OGMA_PHY_INTERFACE_GMII 0
+#define OGMA_PHY_INTERFACE_RGMII 1
+#define OGMA_PHY_INTERFACE_RMII 4
+
+/**
+ * Number of ogma link speed setting
+ */
+#define OGMA_PHY_LINK_SPEED_1G 0
+#define OGMA_PHY_LINK_SPEED_100M 1
+#define OGMA_PHY_LINK_SPEED_10M 2
+
+
+/**
+ * Number of flow control limits
+ */
+#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 383U
+#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX 383U
+#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN 5
+
+#define OGMA_TX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_TX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_TX_PKT_DESC_RING_DRID_FIELD (24)
+#define OGMA_TX_PKT_DESC_RING_PT_FIELD (21)
+#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD (16)
+#define OGMA_TX_PKT_DESC_RING_CC_FIELD (15)
+#define OGMA_TX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_TX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_TX_PKT_DESC_RING_CO_FIELD (7)
+#define OGMA_TX_PKT_DESC_RING_SO_FIELD (6)
+#define OGMA_TX_PKT_DESC_RING_TRS_FIELD (4)
+
+#define OGMA_RX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_RX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD (24)
+#define OGMA_RX_PKT_DESC_RING_FR_FIELD (23)
+#define OGMA_RX_PKT_DESC_RING_ER_FIELD (21)
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
+#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD (12)
+#define OGMA_RX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_RX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_RX_PKT_DESC_RING_CO_FIELD (6)
+
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
+
+#define OGMA_MAX_TX_PKT_LEN 1518U
+#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
+
+#define OGMA_CLK_EN_REG_DOM_ALL 0x3f
+
+enum ogma_err_e{
+ OGMA_ERR_OK = 0,
+ OGMA_ERR_PARAM,
+ OGMA_ERR_ALLOC,
+ OGMA_ERR_BUSY,
+ OGMA_ERR_RANGE,
+ OGMA_ERR_DATA,
+ OGMA_ERR_NOTAVAIL,
+ OGMA_ERR_INTERRUPT,
+ OGMA_ERR_AGAIN,
+ OGMA_ERR_INVALID
+};
+
+typedef void *ogma_handle_t;
+typedef struct ogma_param_s ogma_param_t;
+typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
+typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
+typedef enum ogma_err_e ogma_err_t;
+typedef unsigned char ogma_desc_ring_id_t;
+typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
+typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
+typedef struct ogma_frag_info_s ogma_frag_info_t;
+typedef struct ogma_gmac_config_s ogma_gmac_config_t;
+typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
+
+struct ogma_gmac_config_s{
+ unsigned char phy_interface;
+};
+
+struct ogma_pkt_ctrl_param_s{
+ unsigned int log_chksum_er_flag:1;
+ unsigned int log_hd_imcomplete_flag:1;
+ unsigned int log_hd_er_flag:1;
+};
+
+struct ogma_desc_ring_param_s{
+ unsigned int valid_flag:1;
+ unsigned int little_endian_flag:1;
+ unsigned int tmr_mode_flag:1;
+ unsigned short entry_num;
+};
+
+struct ogma_param_s{
+ unsigned int use_gmac_flag:1;
+ unsigned int use_jumbo_pkt_flag:1;
+ ogma_pkt_ctrl_param_t pkt_ctrl_param;
+ ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
+ ogma_gmac_config_t gmac_config;
+};
+
+struct ogma_tx_pkt_ctrl_s{
+ unsigned int cksum_offload_flag:1;
+ unsigned int tcp_seg_offload_flag:1;
+ ogma_desc_ring_id_t target_desc_ring_id;
+ unsigned short tcp_seg_len;
+};
+
+
+struct ogma_rx_pkt_info_s{
+ unsigned int fragmented_flag:1;
+ unsigned int err_flag:1;
+ unsigned int rx_cksum_result:2;
+ unsigned char err_code;
+};
+
+
+struct ogma_frag_info_s{
+ unsigned long phys_addr;
+ void *addr;
+ unsigned long len;
+};
+
+struct ogma_gmac_mode_s{
+ unsigned int half_duplex_flag:1;
+ unsigned int flow_ctrl_enable_flag:1;
+ u8 link_speed;
+ u16 flow_ctrl_start_threshold;
+ u16 flow_ctrl_stop_threshold;
+ u16 pause_time;
+};
+
+
+/**************************
+***************************
+***************************/
+
+ogma_err_t ogma_start_gmac (
+ int rx_flag,
+ int tx_flag
+ );
+
+ogma_err_t ogma_stop_gmac (
+ int rx_flag,
+ int tx_flag
+ );
+
+ogma_err_t ogma_set_gmac_mode (
+ const ogma_gmac_mode_t *gmac_mode_p
+ );
+
+void ogma_set_phy_reg (
+ u8 phy_addr,
+ u8 reg_addr,
+ u16 value
+ );
+
+u16 ogma_get_phy_reg (
+ u8 phy_addr,
+ u8 reg_addr
+ );
+
+/*
+unsigned long ogma_get_desc_ring_irq_enable (
+ ogma_desc_ring_id_t ring_id
+ );
+
+unsigned long ogma_get_desc_ring_irq_status_non_clear (
+ ogma_desc_ring_id_t ring_id,
+ int mask_flag
+ );
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+ ogma_desc_ring_id_t ring_id,
+ unsigned long value
+ );
+*/
+
+unsigned long ogma_get_hw_ver (void
+ );
+
+unsigned long ogma_get_mcr_ver (void
+ );
+
+#endif /* OGMA_API_H*/
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_basic_access.c u-boot/drivers/net/ogma_basic_access.c
--- original/u-boot-linaro-stable/drivers/net/ogma_basic_access.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_basic_access.c 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,90 @@
+/**
+ * ogma_basic_access.c
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Functions to provide basic access to OGMA resources:
+ * GMAC and
+ * general purpose registers.*
+ *
+ */
+#include "ogma.h"
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+void ogma_set_mac_reg (
+ unsigned long addr,
+ unsigned long value)
+{
+
+ unsigned long cmd;
+
+// ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ ogma_write_reg( OGMA_REG_ADDR_MAC_DATA,
+ value);
+
+ cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
+
+ ogma_write_reg( OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+}
+
+unsigned long ogma_get_mac_reg (
+ unsigned long addr)
+{
+ unsigned long cmd;
+
+// ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ cmd = addr | OGMA_GMAC_CMD_ST_READ;
+
+ ogma_write_reg( OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+ return ogma_read_reg(OGMA_REG_ADDR_MAC_DATA);
+}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_basic_access.h u-boot/drivers/net/ogma_basic_access.h
--- original/u-boot-linaro-stable/drivers/net/ogma_basic_access.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_basic_access.h 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,35 @@
+/**
+ * ogma_basic_access.h
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ *
+ */
+
+#ifndef OGMA_BASIC_ACCESS_H
+#define OGMA_BASIC_ACCESS_H
+
+void ogma_set_mac_reg (
+ unsigned long addr,
+ unsigned long value);
+
+unsigned long ogma_get_mac_reg (
+ unsigned long addr);
+
+
+#endif/* OGMA_BASIC_ACCESS_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_config.h u-boot/drivers/net/ogma_config.h
--- original/u-boot-linaro-stable/drivers/net/ogma_config.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_config.h 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,38 @@
+/**
+ * ogma_config.h
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef OGMA_CONFIG_H
+#define OGMA_CONFIG_H
+
+/* ---------------------------------------------------------------------------
+ constant macro
+ --------------------------------------------------------------------------- */
+
+#define OGMA_CONFIG_USE_PKT_DESC_RING
+#define OGMA_CONFIG_USE_GMAC
+
+#define OGMA_CONFIG_CLK_HZ 250000000UL
+#define OGMA_CONFIG_GMAC_CLK_HZ ( OGMA_CONFIG_CLK_HZ >> 1)
+
+#define OGMA_CONFIG_F_NETSEC_VER OGMA_F_NETSEC_VER_F_TAIKI
+
+#endif /* OGMA_CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_gmac_access.c u-boot/drivers/net/ogma_gmac_access.c
--- original/u-boot-linaro-stable/drivers/net/ogma_gmac_access.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_gmac_access.c 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,436 @@
+/**
+ * ogma_gmac_access.c
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ *
+ */
+#include "ogma.h"
+#include
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+static void ogma_dump_gmac_stat (void);
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+extern ogma_ctrl_t *ctrl_p;
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+
+/**
+ * Clock range index for F_GMAC4MT::GAR::CR field.
+ */
+#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
+#else
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
+#endif
+
+
+/**********************************************************************
+ * Local function declarations
+ **********************************************************************/
+
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_start_gmac (
+ int rx_flag,
+ int tx_flag
+ )
+{
+ unsigned long value;
+
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+
+ /* Initializes F_GMAC4MT */
+ if ( ctrl_p->gmac_mode.link_speed ==
+ OGMA_PHY_LINK_SPEED_1G) {
+ /* Writes 0 to FGMAC4 MCR */
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_MCR,
+ 0);
+ } else {
+ /* Writes PS bit to FGMAC4 MCR */
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_MCR,
+ OGMA_GMAC_MCR_REG_PS);
+ }
+ /* F_GMAC4MT soft reset*/
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_RESET);
+
+ /* Wait soft reset */
+ udelay(1000);
+
+ /* Read F_GMAC4MT BMR */
+ value = ogma_get_mac_reg(OGMA_GMAC_REG_ADDR_BMR);
+
+ /* check software reset result*/
+ if ( value & OGMA_GMAC_BMR_REG_SWR) {
+ /* pop domain c clock*/
+ return OGMA_ERR_AGAIN;
+ }
+
+ /* MAC desc soft reset */
+ ogma_write_reg( OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
+ OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
+
+ /* Wait MAC desc soft reset done */
+ while ( ( ogma_read_reg(OGMA_REG_ADDR_MAC_DESC_SOFT_RST)
+ & OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
+ ;
+ }
+
+ /* MAC desc init */
+ ogma_write_reg( OGMA_REG_ADDR_MAC_DESC_INIT,
+ OGMA_MAC_DESC_INIT_REG_INIT);
+
+ /* Wait MAC desc init done */
+ while ( ( ogma_read_reg(OGMA_REG_ADDR_MAC_DESC_INIT)
+ & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+ ;
+ }
+
+
+ /* set BMR */
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_COMMON);
+ /* set RDLAR */
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_RDLAR,
+ OGMA_GMAC_RDLAR_REG_COMMON);
+ /* set TDLAR*/
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_TDLAR,
+ OGMA_GMAC_TDLAR_REG_COMMON);
+ /* set MFFR*/
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_MFFR,
+ 0x80000001UL);
+
+ /* calc MCR setting val */
+ value = ( ctrl_p->gmac_mode.half_duplex_flag ?
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
+
+ if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
+ value |= OGMA_GMAC_MCR_REG_PS;
+ }
+
+ if ( ( ctrl_p->param.gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_GMII ) &&
+ ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
+ value |= OGMA_GMAC_MCR_REG_FES;
+ }
+ /* set CST bit */
+ value |= OGMA_GMAC_MCR_REG_CST;
+
+ /* set JE bit */
+ value |= OGMA_GMAC_MCR_REG_JE;
+ /* set MCR */
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_MCR,
+ value);
+
+ if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
+ /* Set Flow Control Threshold */
+ value =
+ ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
+ ctrl_p->gmac_mode.flow_ctrl_start_threshold;
+
+ ogma_write_reg( OGMA_REG_ADDR_MAC_FLOW_TH,
+ value);
+ /* Set Flow Control Threshold F_GMAC4MT*/
+ value =
+ ( ctrl_p->gmac_mode.pause_time << 16) |
+ OGMA_GMAC_FCR_REG_RFE |
+ OGMA_GMAC_FCR_REG_TFE;
+
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_FCR,
+ value);
+ }
+
+
+ /* Read F_GMAC4MT OMR*/
+ value = ogma_get_mac_reg(OGMA_GMAC_REG_ADDR_OMR);
+
+ if ( rx_flag ) {
+ value |= OGMA_GMAC_OMR_REG_SR;
+ }
+
+ if ( tx_flag ) {
+ value |= OGMA_GMAC_OMR_REG_ST;
+ }
+
+ /* set OMR*/
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_OMR,
+ value);
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+ ogma_dump_gmac_stat();
+#endif
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_stop_gmac (
+ int rx_flag,
+ int tx_flag
+ )
+{
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+ /* set F_GMAC4MT OMR*/
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_OMR,
+ 0);
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+ ogma_dump_gmac_stat();
+#endif
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_gmac_mode (
+ const ogma_gmac_mode_t *gmac_mode_p
+ )
+{
+ if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G ) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
+ ( gmac_mode_p->half_duplex_flag) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->half_duplex_flag &&
+ gmac_mode_p->flow_ctrl_enable_flag) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->flow_ctrl_enable_flag) {
+
+ if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
+ ( gmac_mode_p->flow_ctrl_start_threshold >
+ OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
+ gmac_mode_p->flow_ctrl_start_threshold) ||
+ ( gmac_mode_p->flow_ctrl_stop_threshold >
+ OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ memcpy( ( void *)&ctrl_p->gmac_mode,
+ ( void *)gmac_mode_p,
+ sizeof( ogma_gmac_mode_t) );
+
+ return OGMA_ERR_OK;
+}
+
+
+void ogma_set_phy_reg (
+ u8 phy_addr,
+ u8 reg_addr,
+ u16 value
+ )
+{
+ u32 cmd;
+
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_GDR,
+ value);
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA)
+ | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR)
+ | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR)
+ | OGMA_GMAC_GAR_REG_GW
+ | OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg(OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+
+}
+
+
+u16 ogma_get_phy_reg (
+ u8 phy_addr,
+ u8 reg_addr
+ )
+{
+ u32 cmd;
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA)
+ | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR)
+ | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR)
+ | OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg(OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+
+
+ return (u16)ogma_get_mac_reg(OGMA_GMAC_REG_ADDR_GDR);
+
+}
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+static const struct {
+ u32 addr;
+ char *name_p;
+} ogma_gmac_mmc_reg_info[] = {
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_RX , "MMC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_TX , "MMC_INTR_TX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX , "MMC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX , "MMC_INTR_MASK_TX"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB , "TXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB , "TXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB , "TX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB , "TX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB , "TXUNICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR , "TXUNDERFLOWERROR"},
+ {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G , "TXSINGLECOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICOL_G , "TXMULTICOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXDEFERRED , "TXDEFERRED"},
+ {OGMA_GMAC_REG_ADDR_TXLATECOL , "TXLATECOL"},
+ {OGMA_GMAC_REG_ADDR_TXEXESSCOL , "TXEXESSCOL"},
+ {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR , "TXCARRIERERRROR"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G , "TXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G , "TXFRAMECOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXEXECESSDEF , "TXEXECESSDEF"},
+ {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES , "TXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G , "TXVLANFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB , "RXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB , "RXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G , "RXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXCRCERROR , "RXCRCERROR"},
+ {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR , "RXALLIGNMENTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXRUNTERROR , "RXRUNTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXJABBERERROR , "RXJABBERERROR"},
+ {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G , "RXUNDERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G , "RXOVERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB , "RX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB , "RX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G , "RXUNICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXLENGTHERROR , "RXLENGTHERROR"},
+ {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE , "RXOUTOFRANGETYPE"},
+ {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES , "RXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW , "RXFIFOOVERFLOW"},
+ {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB , "RXVLANFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR , "RXWATCHDOGERROR"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX , "MMC_IPC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS , "RXIPV4_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS , "RXIPV4_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS , "RXIPV4_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS , "RXIPV4_FRAG_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS , "RXIPV4_UDSBL_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS , "RXIPV6_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS , "RXIPV6_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS , "RXIPV6_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS , "RXUDP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS , "RXUDP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS , "RXTCP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS , "RXTCP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS , "RXICMP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS , "RXICMP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS , "RXIPV4_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS , "RXIPV4_FRAG_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS , "RXIPV6_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS , "RXUDP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS , "RXUDP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS , "RXTCP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS , "RXTCP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS , "RXICMP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS , "RXICMP_ERR_OCTETS"}
+};
+
+
+static void ogma_dump_gmac_stat (void)
+{
+
+ unsigned int i;
+
+ printf("Dumping GMAC statistics registers(MMC registers):\n");
+
+ for (i = 0;
+ i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
+ i++) {
+ printf(" %-21s => 0x%08lx\n",
+ ogma_gmac_mmc_reg_info[i].name_p,
+ ( unsigned long)ogma_get_mac_reg(ogma_gmac_mmc_reg_info[i].addr));
+ }
+
+
+ /* Reset all counters. */
+ ogma_set_mac_reg(OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+}
+
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_internal.h u-boot/drivers/net/ogma_internal.h
--- original/u-boot-linaro-stable/drivers/net/ogma_internal.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_internal.h 2016-08-02 14:19:41.120728103 +0900
@@ -0,0 +1,117 @@
+/**
+ * ogma_itnernal.h
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ *
+ */
+#ifndef OGMA_INTERNAL_H
+#define OGMA_INTERNAL_H
+
+#include "ogma_api.h"
+
+
+/* Just a million to prevent typing errors. */
+#define OGMA_CLK_MHZ (1000000)
+
+#define OGMA_INSTANCE_NUM_MAX 1
+
+#define OGMA_RX_PKT_BUF_LEN 1522
+#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
+#define OGMA_DUMMY_DESC_ENTRY_LEN 48
+
+/*
+extern const unsigned long desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const unsigned long desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const unsigned long desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+*/
+
+typedef struct ogma_ctrl_s ogma_ctrl_t;
+typedef struct ogma_desc_ring_s ogma_desc_ring_t;
+typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
+typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
+
+struct ogma_clk_ctrl_s{
+ u32 dmac_req_num;
+ u32 core_req_num;
+ u8 mac_req_num;
+};
+
+/*
+struct ogma_desc_ring_s{
+
+ ogma_desc_ring_id_t ring_id;
+
+ ogma_desc_ring_param_t param;
+
+ unsigned int rx_desc_ring_flag:1;
+
+ unsigned int tx_desc_ring_flag:1;
+
+ unsigned int running_flag:1;
+
+ unsigned int full_flag:1;
+
+ unsigned char desc_entry_len;
+
+ unsigned short head_idx;
+
+ unsigned short tail_idx;
+
+ unsigned short rx_num;
+
+ unsigned short tx_done_num;
+
+ void *desc_ring_cpu_addr;
+
+ dma_addr_t desc_ring_phys_addr;
+
+ ogma_frag_info_t *frag_info_p;
+
+ ogma_desc_entry_priv_t *priv_data_p;
+};
+*/
+struct ogma_ctrl_s{
+ ogma_ctrl_t *next_p;
+
+ unsigned int core_enabled_flag:1;
+
+ unsigned int gmac_rx_running_flag:1;
+
+ unsigned int gmac_tx_running_flag:1;
+
+ unsigned int gmac_mode_valid_flag:1;
+
+ ogma_param_t param;
+
+ ogma_clk_ctrl_t clk_ctrl;
+
+ unsigned long rx_pkt_buf_len;
+
+// ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
+
+
+ ogma_gmac_mode_t gmac_mode;
+
+ void *dummy_desc_entry_addr;
+
+ dma_addr_t dummy_desc_entry_phys_addr;
+
+};
+
+#endif /* OGMA_INTERNAL_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_reg.h u-boot/drivers/net/ogma_reg.h
--- original/u-boot-linaro-stable/drivers/net/ogma_reg.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_reg.h 2016-08-02 14:19:41.121728098 +0900
@@ -0,0 +1,120 @@
+/**
+ * ogma_reg.h
+ *
+ * Copyright (c) 2011 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ *
+ */
+#ifndef OGMA_REG_H
+#define OGMA_REG_H
+
+#include "ogma_reg_f_taiki.h"
+
+#include "ogma_reg_f_gmac_4mt.h"
+
+/*bit fields for PKT_CTRL*/
+#define OGMA_PKT_CTRL_REG_MODE_NRM (1UL << 28)
+#define OGMA_PKT_CTRL_REG_EN_JUMBO (1UL << 27)
+#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER (1UL << 3 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_ER (1UL << 1 )
+
+#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
+#define OGMA_CLK_EN_REG_DOM_C (1UL << 1)
+#define OGMA_CLK_EN_REG_DOM_D (1UL << 0)
+
+/************************************************************
+ * Bit fields
+ ************************************************************/
+/* bit fields for com_init */
+#define OGMA_COM_INIT_REG_PKT (1UL << 1)
+#define OGMA_COM_INIT_REG_CORE (1UL << 0)
+#define OGMA_COM_INIT_REG_ALL ( OGMA_COM_INIT_REG_CORE | OGMA_COM_INIT_REG_PKT)
+
+/* bit fields for soft_rst */
+#define OGMA_SOFT_RST_REG_RESET (0)
+#define OGMA_SOFT_RST_REG_RUN (1UL << 31)
+
+/* bit fields for dma_hm_ctrl */
+#define OGMA_DMA_CTRL_REG_STOP 1UL
+
+/* bit fields for gmac_cmd */
+#define OGMA_GMAC_CMD_ST_READ (0)
+#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
+#define OGMA_GMAC_CMD_ST_BUSY (1UL << 31)
+
+/* bit fields for F_GMAC4MT BMR*/
+#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
+#define OGMA_GMAC_BMR_REG_RESET (0x00020181)
+#define OGMA_GMAC_BMR_REG_SWR (0x00000001)
+
+/* bit fields for F_GMAC4MT OMR*/
+#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
+#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
+
+/* bit fields for F_GMAC4MT MCR*/
+#define OGMA_GMAC_MCR_REG_CST (1UL << 25)
+#define OGMA_GMAC_MCR_REG_JE (1UL << 20)
+#define OGMA_GMAC_MCR_REG_PS (1UL << 15)
+#define OGMA_GMAC_MCR_REG_FES (1UL << 14)
+#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
+#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
+
+/*bit fields for F_GMAC4MT FCR*/
+#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
+#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
+
+/* bit fields for F_GMAC4MT GAR */
+#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
+#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
+
+/* bit fields for F_GMAC4MT RDLAR*/
+#define OGMA_GMAC_RDLAR_REG_COMMON (0x31618000UL)
+
+/* bit fields for F_GMAC4MT TDLAR*/
+#define OGMA_GMAC_TDLAR_REG_COMMON (0x3161c000UL)
+
+#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
+#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
+#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
+
+#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ (2)
+#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ (3)
+#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ (0)
+#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
+#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
+#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
+
+#define OGMA_REG_ADDR_OGMA_VER_F_TAIKI 0x00020000UL
+
+/* bit fields for DESC RING CONFIG */
+#define OGMA_REG_DESC_RING_CONFIG_CFG_UP (31)
+#define OGMA_REG_DESC_RING_CONFIG_CH_RST (30)
+#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE (4)
+#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
+
+
+/* bit fields for mac_desc_soft_rst */
+#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
+
+/* bit fields for mac_desc_init */
+#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
+
+#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
+
+#endif /*OGMA_REG_H*/
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_reg_f_gmac_4mt.h u-boot/drivers/net/ogma_reg_f_gmac_4mt.h
--- original/u-boot-linaro-stable/drivers/net/ogma_reg_f_gmac_4mt.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_reg_f_gmac_4mt.h 2016-08-02 14:19:41.121728098 +0900
@@ -0,0 +1,228 @@
+/**
+ * ogma_reg_f_gmac_4mt.h
+ *
+ * Copyright (c) 2012 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#ifndef OGMA_REG_F_GMAC_4MT_H
+#define OGMA_REG_F_GMAC_4MT_H
+
+/**
+ * GMAC regtister
+ */
+#define OGMA_GMAC_REG_ADDR_MCR (0x0000)
+#define OGMA_GMAC_REG_ADDR_MFFR (0x0004)
+#define OGMA_GMAC_REG_ADDR_MHTRH (0x0008)
+#define OGMA_GMAC_REG_ADDR_MHTRL (0x000c)
+#define OGMA_GMAC_REG_ADDR_GAR (0x0010)
+#define OGMA_GMAC_REG_ADDR_GDR (0x0014)
+#define OGMA_GMAC_REG_ADDR_FCR (0x0018)
+#define OGMA_GMAC_REG_ADDR_VTR (0x001c)
+#define OGMA_GMAC_REG_ADDR_RWFFR (0x0028)
+#define OGMA_GMAC_REG_ADDR_PMTR (0x002c)
+#define OGMA_GMAC_REG_ADDR_LPICSR (0x0030)
+#define OGMA_GMAC_REG_ADDR_LPITCR (0x0034)
+#define OGMA_GMAC_REG_ADDR_ISR (0x0038)
+#define OGMA_GMAC_REG_ADDR_IMR (0x003c)
+#define OGMA_GMAC_REG_ADDR_MAR0H (0x0040)
+#define OGMA_GMAC_REG_ADDR_MAR0L (0x0044)
+#define OGMA_GMAC_REG_ADDR_MAR1H (0x0048)
+#define OGMA_GMAC_REG_ADDR_MAR1L (0x004c)
+#define OGMA_GMAC_REG_ADDR_MAR2H (0x0050)
+#define OGMA_GMAC_REG_ADDR_MAR2L (0x0054)
+#define OGMA_GMAC_REG_ADDR_MAR3H (0x0058)
+#define OGMA_GMAC_REG_ADDR_MAR3L (0x005c)
+#define OGMA_GMAC_REG_ADDR_MAR4H (0x0060)
+#define OGMA_GMAC_REG_ADDR_MAR4L (0x0064)
+#define OGMA_GMAC_REG_ADDR_MAR5H (0x0068)
+#define OGMA_GMAC_REG_ADDR_MAR5L (0x006c)
+#define OGMA_GMAC_REG_ADDR_MAR6H (0x0070)
+#define OGMA_GMAC_REG_ADDR_MAR6L (0x0074)
+#define OGMA_GMAC_REG_ADDR_MAR7H (0x0078)
+#define OGMA_GMAC_REG_ADDR_MAR7L (0x007c)
+#define OGMA_GMAC_REG_ADDR_MAR8H (0x0080)
+#define OGMA_GMAC_REG_ADDR_MAR8L (0x0084)
+#define OGMA_GMAC_REG_ADDR_MAR9H (0x0088)
+#define OGMA_GMAC_REG_ADDR_MAR9L (0x008c)
+#define OGMA_GMAC_REG_ADDR_MAR10H (0x0090)
+#define OGMA_GMAC_REG_ADDR_MAR10L (0x0094)
+#define OGMA_GMAC_REG_ADDR_MAR11H (0x0098)
+#define OGMA_GMAC_REG_ADDR_MAR11L (0x009c)
+#define OGMA_GMAC_REG_ADDR_MAR12H (0x00a0)
+#define OGMA_GMAC_REG_ADDR_MAR12L (0x00a4)
+#define OGMA_GMAC_REG_ADDR_MAR13H (0x00a8)
+#define OGMA_GMAC_REG_ADDR_MAR13L (0x00ac)
+#define OGMA_GMAC_REG_ADDR_MAR14H (0x00b0)
+#define OGMA_GMAC_REG_ADDR_MAR14L (0x00b4)
+#define OGMA_GMAC_REG_ADDR_MAR15H (0x00b8)
+#define OGMA_GMAC_REG_ADDR_MAR15L (0x00bc)
+#define OGMA_GMAC_REG_ADDR_RSR (0x00d8)
+#define OGMA_GMAC_REG_ADDR_TSCR (0x0700)
+#define OGMA_GMAC_REG_ADDR_SSIR (0x0704)
+#define OGMA_GMAC_REG_ADDR_STSR (0x0708)
+#define OGMA_GMAC_REG_ADDR_STNR (0x070c)
+#define OGMA_GMAC_REG_ADDR_STSUR (0x0710)
+#define OGMA_GMAC_REG_ADDR_STNUR (0x0714)
+#define OGMA_GMAC_REG_ADDR_TSAR (0x0718)
+#define OGMA_GMAC_REG_ADDR_TTSR (0x071c)
+#define OGMA_GMAC_REG_ADDR_TTNR (0x0720)
+#define OGMA_GMAC_REG_ADDR_STHWSR (0x0724)
+#define OGMA_GMAC_REG_ADDR_TSR (0x0728)
+#define OGMA_GMAC_REG_ADDR_PPSCR (0x072c)
+#define OGMA_GMAC_REG_ADDR_ANTR (0x0730)
+#define OGMA_GMAC_REG_ADDR_ATSR (0x0734)
+#define OGMA_GMAC_REG_ADDR_MAR16H (0x0800)
+#define OGMA_GMAC_REG_ADDR_MAR16L (0x0804)
+#define OGMA_GMAC_REG_ADDR_MAR17H (0x0808)
+#define OGMA_GMAC_REG_ADDR_MAR17L (0x080c)
+#define OGMA_GMAC_REG_ADDR_MAR18H (0x0810)
+#define OGMA_GMAC_REG_ADDR_MAR18L (0x0814)
+#define OGMA_GMAC_REG_ADDR_MAR19H (0x0818)
+#define OGMA_GMAC_REG_ADDR_MAR19L (0x081c)
+#define OGMA_GMAC_REG_ADDR_MAR20H (0x0820)
+#define OGMA_GMAC_REG_ADDR_MAR20L (0x0824)
+#define OGMA_GMAC_REG_ADDR_MAR21H (0x0828)
+#define OGMA_GMAC_REG_ADDR_MAR21L (0x082c)
+#define OGMA_GMAC_REG_ADDR_MAR22H (0x0830)
+#define OGMA_GMAC_REG_ADDR_MAR22L (0x0834)
+#define OGMA_GMAC_REG_ADDR_MAR23H (0x0838)
+#define OGMA_GMAC_REG_ADDR_MAR23L (0x083c)
+#define OGMA_GMAC_REG_ADDR_MAR24H (0x0840)
+#define OGMA_GMAC_REG_ADDR_MAR24L (0x0844)
+#define OGMA_GMAC_REG_ADDR_MAR25H (0x0848)
+#define OGMA_GMAC_REG_ADDR_MAR25L (0x084c)
+#define OGMA_GMAC_REG_ADDR_MAR26H (0x0850)
+#define OGMA_GMAC_REG_ADDR_MAR26L (0x0854)
+#define OGMA_GMAC_REG_ADDR_MAR27H (0x0858)
+#define OGMA_GMAC_REG_ADDR_MAR27L (0x085c)
+#define OGMA_GMAC_REG_ADDR_MAR28H (0x0860)
+#define OGMA_GMAC_REG_ADDR_MAR28L (0x0864)
+#define OGMA_GMAC_REG_ADDR_MAR29H (0x0868)
+#define OGMA_GMAC_REG_ADDR_MAR29L (0x086c)
+#define OGMA_GMAC_REG_ADDR_MAR30H (0x0870)
+#define OGMA_GMAC_REG_ADDR_MAR30L (0x0874)
+#define OGMA_GMAC_REG_ADDR_MAR31H (0x0878)
+#define OGMA_GMAC_REG_ADDR_MAR31L (0x087c)
+
+/**
+ * GMAC MAC Management Counters(Option) register
+ */
+#define OGMA_GMAC_REG_ADDR_MMC_CNTL (0x0100)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX (0x0104)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX (0x0108)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX (0x010c)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX (0x0110)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB (0x0114)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB (0x0118)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G (0x011c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G (0x0120)
+#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB (0x0124)
+#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB (0x0128)
+#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB (0x012c)
+#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB (0x0130)
+#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB (0x0134)
+#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB (0x0138)
+#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB (0x013c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB (0x0140)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB (0x0144)
+#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR (0x0148)
+#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G (0x014c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G (0x0150)
+#define OGMA_GMAC_REG_ADDR_TXDEFERRED (0x0154)
+#define OGMA_GMAC_REG_ADDR_TXLATECOL (0x0158)
+#define OGMA_GMAC_REG_ADDR_TXEXESSCOL (0x015c)
+#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR (0x0160)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G (0x0164)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G (0x0168)
+#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF (0x016c)
+#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES (0x0170)
+#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G (0x0174)
+#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB (0x0180)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB (0x0184)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G (0x0188)
+#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G (0x018c)
+#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G (0x0190)
+#define OGMA_GMAC_REG_ADDR_RXCRCERROR (0x0194)
+#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR (0x0198)
+#define OGMA_GMAC_REG_ADDR_RXRUNTERROR (0x019c)
+#define OGMA_GMAC_REG_ADDR_RXJABBERERROR (0x01a0)
+#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G (0x01a4)
+#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G (0x01a8)
+#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB (0x01ac)
+#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB (0x01b0)
+#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB (0x01b4)
+#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB (0x01b8)
+#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB (0x01bc)
+#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB (0x01c0)
+#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G (0x01c4)
+#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR (0x01c8)
+#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE (0x01cc)
+#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES (0x01d0)
+#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW (0x01d4)
+#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB (0x01d8)
+#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR (0x01dc)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX (0x0200)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX (0x0208)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS (0x0210)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS (0x0214)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS (0x0218)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS (0x021c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS (0x0220)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS (0x0224)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS (0x0228)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS (0x022c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS (0x0230)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS (0x0234)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS (0x0238)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS (0x023c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS (0x0240)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS (0x0244)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS (0x0250)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS (0x0254)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS (0x0258)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS (0x025c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS (0x0260)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS (0x0264)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS (0x0268)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS (0x026c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS (0x0270)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS (0x0274)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS (0x0278)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS (0x027c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS (0x0280)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS (0x0284)
+/**
+ * GMAC DMA register
+ */
+#define OGMA_GMAC_REG_ADDR_BMR (0x1000)
+#define OGMA_GMAC_REG_ADDR_TPDR (0x1004)
+#define OGMA_GMAC_REG_ADDR_RPDR (0x1008)
+#define OGMA_GMAC_REG_ADDR_RDLAR (0x100c)
+#define OGMA_GMAC_REG_ADDR_TDLAR (0x1010)
+#define OGMA_GMAC_REG_ADDR_SR (0x1014)
+#define OGMA_GMAC_REG_ADDR_OMR (0x1018)
+#define OGMA_GMAC_REG_ADDR_IER (0x101c)
+#define OGMA_GMAC_REG_ADDR_MFOCR (0x1020)
+#define OGMA_GMAC_REG_ADDR_RIWTR (0x1024)
+#define OGMA_GMAC_REG_ADDR_AHBSR (0x102c)
+#define OGMA_GMAC_REG_ADDR_CHTDR (0x1048)
+#define OGMA_GMAC_REG_ADDR_CHRDR (0x104c)
+#define OGMA_GMAC_REG_ADDR_CHTBAR (0x1050)
+#define OGMA_GMAC_REG_ADDR_CHRBAR (0x1054)
+
+#endif /* OGMA_REG_F_GMAC_4MT_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/net/ogma_reg_f_taiki.h u-boot/drivers/net/ogma_reg_f_taiki.h
--- original/u-boot-linaro-stable/drivers/net/ogma_reg_f_taiki.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/net/ogma_reg_f_taiki.h 2016-08-02 14:19:41.121728098 +0900
@@ -0,0 +1,74 @@
+/**
+ * ogma_reg_f_taiki.h
+ *
+ * Copyright (c) 2012 - 2013 Fujitsu Semiconductor Limited.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#ifndef OGMA_REG_F_TAIKI_H
+#define OGMA_REG_F_TAIKI_H
+
+#define OGMA_REG_ADDR_TOP_STATUS (0x80)
+#define OGMA_REG_ADDR_TOP_INTEN (0x81)
+#define OGMA_REG_ADDR_TOP_INTEN_SET (0x8d)
+#define OGMA_REG_ADDR_TOP_INTEN_CLR (0x8e)
+#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
+#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10a)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10b)
+#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
+#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11a)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11b)
+#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
+#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
+#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF (0x87)
+#define OGMA_REG_ADDR_DIS_CORE (0x86)
+#define OGMA_REG_ADDR_CLK_EN (0x40)
+#define OGMA_REG_ADDR_SOFT_RST (0x41)
+#define OGMA_REG_ADDR_PKT_CTRL (0x50)
+#define OGMA_REG_ADDR_COM_INIT (0x48)
+#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
+#define OGMA_REG_ADDR_F_TAIKI_MC_VER (0x8b)
+#define OGMA_REG_ADDR_F_TAIKI_VER (0x8c)
+#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
+#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
+#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
+#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
+#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
+#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
+#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
+#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
+#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START (0x102)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START (0x112)
+#define OGMA_REG_ADDR_RESERVED_RX_DESC_START (0x122)
+#define OGMA_REG_ADDR_RESERVED_TX_DESC_START (0x132)
+#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10c)
+#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11c)
+#define OGMA_REG_ADDR_MAC_DATA (0x470)
+#define OGMA_REG_ADDR_MAC_CMD (0x471)
+#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
+#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
+#define OGMA_REG_ADDR_MAC_REG_BASE (0x47e)
+#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47f)
+#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
+#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
+
+#endif /* OGMA_REG_F_TAIKI_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/spi/Makefile u-boot/drivers/spi/Makefile
--- original/u-boot-linaro-stable/drivers/spi/Makefile 2016-08-02 12:12:09.070772076 +0900
+++ u-boot/drivers/spi/Makefile 2016-08-02 14:19:41.153727961 +0900
@@ -46,6 +46,7 @@
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+COBJS-$(CONFIG_MB86S7X_HS_SPI) += mb86s7x_hs_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/spi/hs_spi_reg.h u-boot/drivers/spi/hs_spi_reg.h
--- original/u-boot-linaro-stable/drivers/spi/hs_spi_reg.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/spi/hs_spi_reg.h 2016-08-02 14:19:41.155727952 +0900
@@ -0,0 +1,485 @@
+/*
+ * linux/drivers/spi/hs_spi.h Register definitions for high speed SPI controller
+ *
+ * Copyright (C) 2010-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HS_SPI_REG_H__
+#define __HS_SPI_REG_H__
+
+/*
+ * HS_SPI register adress definitions
+ */
+#define HS_SPI_REG_MCTRL 0x00
+#define HS_SPI_REG_PCC0 0x04
+#define HS_SPI_REG_PCC1 0x08
+#define HS_SPI_REG_PCC2 0x0C
+#define HS_SPI_REG_PCC3 0x10
+#define HS_SPI_REG_TXF 0x14
+#define HS_SPI_REG_TXE 0x18
+#define HS_SPI_REG_TXC 0x1C
+#define HS_SPI_REG_RXF 0x20
+#define HS_SPI_REG_RXE 0x24
+#define HS_SPI_REG_RXC 0x28
+#define HS_SPI_REG_FAULTF 0x2C
+#define HS_SPI_REG_FAULTC 0x30
+#define HS_SPI_REG_DMCFG 0x34
+#define HS_SPI_REG_DMDMAEN 0x34
+#define HS_SPI_REG_DMSTART 0x38
+#define HS_SPI_REG_DMSTOP 0x38
+#define HS_SPI_REG_DMPSEL 0x38
+#define HS_SPI_REG_DMTRP 0x38
+#define HS_SPI_REG_DMBCC 0x3C
+#define HS_SPI_REG_DMBCS 0x3C
+#define HS_SPI_REG_DMSTATUS 0x40
+#define HS_SPI_REG_TXBITCNT 0x44
+#define HS_SPI_REG_FIFOCFG 0x4C
+#define HS_SPI_REG_TXFIFO0 0x50
+#define HS_SPI_REG_TXFIFO1 0x54
+#define HS_SPI_REG_TXFIFO2 0x58
+#define HS_SPI_REG_TXFIFO3 0x5C
+#define HS_SPI_REG_TXFIFO4 0x60
+#define HS_SPI_REG_TXFIFO5 0x64
+#define HS_SPI_REG_TXFIFO6 0x68
+#define HS_SPI_REG_TXFIFO7 0x6C
+#define HS_SPI_REG_TXFIFO8 0x70
+#define HS_SPI_REG_TXFIFO9 0x74
+#define HS_SPI_REG_TXFIFO10 0x78
+#define HS_SPI_REG_TXFIFO11 0x7C
+#define HS_SPI_REG_TXFIFO12 0x80
+#define HS_SPI_REG_TXFIFO13 0x84
+#define HS_SPI_REG_TXFIFO14 0x88
+#define HS_SPI_REG_TXFIFO15 0x8C
+#define HS_SPI_REG_RXFIFO0 0x90
+#define HS_SPI_REG_RXFIFO1 0x94
+#define HS_SPI_REG_RXFIFO2 0x98
+#define HS_SPI_REG_RXFIFO3 0x9C
+#define HS_SPI_REG_RXFIFO4 0xA0
+#define HS_SPI_REG_RXFIFO5 0xA4
+#define HS_SPI_REG_RXFIFO6 0xA8
+#define HS_SPI_REG_RXFIFO7 0xAC
+#define HS_SPI_REG_RXFIFO8 0xB0
+#define HS_SPI_REG_RXFIFO9 0xB4
+#define HS_SPI_REG_RXFIFO10 0xB8
+#define HS_SPI_REG_RXFIFO11 0xBC
+#define HS_SPI_REG_RXFIFO12 0xC0
+#define HS_SPI_REG_RXFIFO13 0xC4
+#define HS_SPI_REG_RXFIFO14 0xC8
+#define HS_SPI_REG_RXFIFO15 0xCC
+#define HS_SPI_REG_CSCFG 0xD0
+#define HS_SPI_REG_CSITIME 0xD4
+#define HS_SPI_REG_CSAEXT 0xD8
+#define HS_SPI_REG_RDCSDC0 0xDC
+#define HS_SPI_REG_RDCSDC1 0xDE
+#define HS_SPI_REG_RDCSDC2 0xE0
+#define HS_SPI_REG_RDCSDC3 0xE2
+#define HS_SPI_REG_RDCSDC4 0xE4
+#define HS_SPI_REG_RDCSDC5 0xE6
+#define HS_SPI_REG_RDCSDC6 0xE8
+#define HS_SPI_REG_RDCSDC7 0xEA
+#define HS_SPI_REG_WRCSDC0 0xEC
+#define HS_SPI_REG_WRCSDC1 0xEE
+#define HS_SPI_REG_WRCSDC2 0xF0
+#define HS_SPI_REG_WRCSDC3 0xF2
+#define HS_SPI_REG_WRCSDC4 0xF4
+#define HS_SPI_REG_WRCSDC5 0xF6
+#define HS_SPI_REG_WRCSDC6 0xF8
+#define HS_SPI_REG_WRCSDC7 0xFA
+#define HS_SPI_REG_MID 0xFC
+
+/*
+ * HS_SPI register bit definitions
+ */
+
+/* HS_SPI Module Control Register */
+#define MCTRL_SYNCON_OFFSET 5
+#define MCTRL_SYNCON_MASK 1
+
+#define MCTRL_MES_OFFSET 4
+#define MCTRL_MES_MASK 1
+
+#define MCTRL_CDSS_OFFSET 3
+#define MCTRL_CDSS_MASK 1
+
+#define MCTRL_CSEN_OFFSET 1
+#define MCTRL_CSEN_MASK 1
+
+#define MCTRL_MEN_OFFSET 0
+#define MCTRL_MEN_MASK 1
+
+/* HS_SPI Peripheral Communication Configuratio Register0-3 */
+#define PCC_RDDSEL_OFFSET 21
+#define PCC_RDDSEL_MASK 0x3
+
+#define PCC_WRDSEL_OFFSET 17
+#define PCC_WRDSEL_MASK 0xF
+
+#define PCC_ESYNC_OFFSET 16
+#define PCC_ESYNC_MASK 1
+
+#define PCC_CDRS_OFFSET 9
+#define PCC_CDRS_MASK 0x7F
+
+#define PCC_SENDIAN_OFFSET 8
+#define PCC_SENDIAN_MASK 1
+
+#define PCC_SDIR_OFFSET 7
+#define PCC_SDIR_MASK 1
+
+#define PCC_SS2CD_OFFSET 5
+#define PCC_SS2CD_MASK 3
+
+#define PCC_SSPOL_OFFSET 4
+#define PCC_SSPOL_MASK 1
+
+#define PCC_ACES_OFFSET 2
+#define PCC_ACES_MASK 1
+
+#define PCC_CPOL_OFFSET 1
+#define PCC_CPOL_MASK 1
+
+#define PCC_CPHA_OFFSET 0
+#define PCC_CPHA_MASK 1
+
+/* HS_SPI TX Interrupt Flag Register */
+#define TXF_TSSRS_OFFSET 6
+#define TXF_TSSRS_MASK 1
+
+#define TXF_TFMTS_OFFSET 5
+#define TXF_TFMTS_MASK 1
+
+#define TXF_TFLETS_OFFSET 4
+#define TXF_TFLETS_MASK 1
+
+#define TXF_TFUS_OFFSET 3
+#define TXF_TFUS_MASK 1
+
+#define TXF_TFOS_OFFSET 2
+#define TXF_TFOS_MASK 1
+
+#define TXF_TFES_OFFSET 1
+#define TXF_TFES_MASK 1
+
+#define TXF_TFFS_OFFSET 0
+#define TXF_TFFS_MASK 1
+
+/* HS_SPI TX Interrupt Enable Register */
+#define TXE_TSSRE_OFFSET 6
+#define TXE_TSSRE_MASK 1
+
+#define TXE_TFMTE_OFFSET 5
+#define TXE_TFMTE_MASK 1
+
+#define TXE_TFLETE_OFFSET 4
+#define TXE_TFLETE_MASK 1
+
+#define TXE_TFUE_OFFSET 3
+#define TXE_TFUE_MASK 1
+
+#define TXE_TFOE_OFFSET 2
+#define TXE_TFOE_MASK 1
+
+#define TXE_TFEE_OFFSET 1
+#define TXE_TFEE_MASK 1
+
+#define TXE_TFFE_OFFSET 0
+#define TXE_TFFE_MASK 1
+
+/* HS_SPI TX Interrupt Clear Register */
+#define TXC_TSSRC_OFFSET 6
+#define TXC_TSSRC_MASK 1
+
+#define TXC_TFMTC_OFFSET 5
+#define TXC_TFMTC_MASK 1
+
+#define TXC_TFLETC_OFFSET 4
+#define TXC_TFLETC_MASK 1
+
+#define TXC_TFUC_OFFSET 3
+#define TXC_TFUC_MASK 1
+
+#define TXC_TFOC_OFFSET 2
+#define TXC_TFOC_MASK 1
+
+#define TXC_TFEC_OFFSET 1
+#define TXC_TFEC_MASK 1
+
+#define TXC_TFFC_OFFSET 0
+#define TXC_TFFC_MASK 1
+
+/* HS_SPI RX Interrupt Flag Register */
+#define RXF_RSSRS_OFFSET 6
+#define RXF_RSSRS_MASK 1
+
+#define RXF_RFMTS_OFFSET 5
+#define RXF_RFMTS_MASK 1
+
+#define RXF_RFLETS_OFFSET 4
+#define RXF_RFLETS_MASK 1
+
+#define RXF_RFUS_OFFSET 3
+#define RXF_RFUS_MASK 1
+
+#define RXF_RFOS_OFFSET 2
+#define RXF_RFOS_MASK 1
+
+#define RXF_RFES_OFFSET 1
+#define RXF_RFES_MASK 1
+
+#define RXF_RFFS_OFFSET 0
+#define RXF_RFFS_MASK 1
+
+/* HS_SPI RX Interrupt Enable Register */
+#define RXE_RSSRE_OFFSET 6
+#define RXE_RSSRE_MASK 1
+
+#define RXE_RFMTE_OFFSET 5
+#define RXE_RFMTE_MASK 1
+
+#define RXE_RFLETE_OFFSET 4
+#define RXE_RFLETE_MASK 1
+
+#define RXE_RFUE_OFFSET 3
+#define RXE_RFUE_MASK 1
+
+#define RXE_RFOE_OFFSET 2
+#define RXE_RFOE_MASK 1
+
+#define RXE_RFEE_OFFSET 1
+#define RXE_RFEE_MASK 1
+
+#define RXE_RFFE_OFFSET 0
+#define RXE_RFFE_MASK 1
+
+/* HS_SPI RX Interrupt Clear Register */
+#define RXC_RSSRC_OFFSET 6
+#define RXC_RSSRC_MASK 1
+
+#define RXC_RFMTC_OFFSET 5
+#define RXC_RFMTC_MASK 1
+
+#define RXC_RFLETC_OFFSET 4
+#define RXC_RFLETC_MASK 1
+
+#define RXC_RFUC_OFFSET 3
+#define RXC_RFUC_MASK 1
+
+#define RXC_RFOC_OFFSET 2
+#define RXC_RFOC_MASK 1
+
+#define RXC_RFEC_OFFSET 1
+#define RXC_RFEC_MASK 1
+
+#define RXC_RFFC_OFFSET 0
+#define RXC_RFFC_MASK 1
+
+/* HS_SPI Fault Interrupt Flag Register */
+#define FAULTF_DRCBSFS_OFFSET 4
+#define FAULTF_DRCBSFS_MASK 1
+
+#define FAULTF_DWCBSFS_OFFSET 3
+#define FAULTF_DWCBSFS_MASK 1
+
+#define FAULTF_PVFS_OFFSET 2
+#define FAULTF_PVFS_MASK 1
+
+#define FAULTF_WAFS_OFFSET 1
+#define FAULTF_WAFS_MASK 1
+
+#define FAULTF_UMAFS_OFFSET 0
+#define FAULTF_UMAFS_MASK 1
+
+/* HS_SPI Fault Interrupt Flag Register */
+#define FAULTC_DRCBSFC_OFFSET 4
+#define FAULTC_DRCBSFC_MASK 1
+
+#define FAULTC_DWCBSFC_OFFSET 3
+#define FAULTC_DWCBSFC_MASK 1
+
+#define FAULTC_PVFC_OFFSET 2
+#define FAULTC_PVFC_MASK 1
+
+#define FAULTC_WAFC_OFFSET 1
+#define FAULTC_WAFC_MASK 1
+
+#define FAULTC_UMAFC_OFFSET 0
+#define FAULTC_UMAFC_MASK 1
+
+/* HS_SPI Direct Mode Configuration Register */
+#define DMCFG_MSTARTEN_OFFSET 2
+#define DMCFG_MSTARTEN_MASK 1
+
+#define DMCFG_SSDC_OFFSET 1
+#define DMCFG_SSDC_MASK 1
+
+/* HS_SPI Direct Mode DMA Enable Register */
+#define DMDMAEN_TXDMAEN_OFFSET 9
+#define DMDMAEN_TXDMAEN_MASK 1
+
+#define DMDMAEN_RXDMAEN_OFFSET 8
+#define DMDMAEN_RXDMAEN_MASK 1
+
+/* HS_SPI Direct Mode Start Register */
+#define DMSTART_START_OFFSET 0
+#define DMSTART_START_MASK 1
+
+/* HS_SPI Direct Mode Stop Register */
+#define DMSTOP_STOP_OFFSET 8
+#define DMSTOP_STOP_MASK 1
+
+/* HS_SPI Direct Mode Peripheral Select Register */
+#define DMPSEL_PSEL_OFFSET 16
+#define DMPSEL_PSEL_MASK 3
+
+/* HS_SPI Direct Mode Transfer Protocol Register */
+#define DMTRP_TRP_OFFSET 24
+#define DMTRP_TRP_MASK 0x0F
+
+/* HS_SPI Direct Mode Byte Count Control Register */
+#define DMBCC_BCC_OFFSET 0
+#define DMBCC_BCC_MASK 0xFFFF
+
+/* HS_SPI Direct Mode Byte Count Status Register */
+#define DMBCS_BCS_OFFSET 16
+#define DMBCS_BCS_MASK 0xFFFF
+
+/* HS_SPI Direct Mode Status Register */
+#define DMSTATUS_TXFLEVEL_OFFSET 16
+#define DMSTATUS_TXFLEVEL_MASK 0x1F
+
+#define DMSTATUS_RXFLEVEL_OFFSET 8
+#define DMSTATUS_RXFLEVEL_MASK 0x1F
+
+#define DMSTATUS_TXACTIVE_OFFSET 1
+#define DMSTATUS_TXACTIVE_MASK 1
+
+#define DMSTATUS_RXACTIVE_OFFSET 0
+#define DMSTATUS_RXACTIVE_MASK 1
+
+/* HS_SPI Transmit Bit Count Register */
+#define TXBITCNT_TXBITCNT_OFFSET 0
+#define TXBITCNT_TXBITCNT_MASK 0x3F
+
+/* HS_SPI FIFO Configuration Register */
+#define FIFOCFG_TXFLSH_OFFSET 12
+#define FIFOCFG_TXFLSH_MASK 1
+
+#define FIFOCFG_RXFLSH_OFFSET 11
+#define FIFOCFG_RXFLSH_MASK 1
+
+#define FIFOCFG_TXCTRL_OFFSET 10
+#define FIFOCFG_TXCTRL_MASK 1
+
+#define FIFOCFG_FWIDTH_OFFSET 8
+#define FIFOCFG_FWIDTH_MASK 3
+
+#define FIFOCFG_TXFTH_OFFSET 4
+#define FIFOCFG_TXFTH_MASK 0x0F
+
+#define FIFOCFG_RXFTH_OFFSET 0
+#define FIFOCFG_RXFTH_MASK 0x0F
+
+/* HS_SPI Command Sequencer Configuration Register */
+#define CSCFG_MSEL_OFFSET 16
+#define CSCFG_MSEL_MASK 0x0F
+
+#define CSCFG_SSELEN_OFFSET 8
+#define CSCFG_SSELEN_MASK 0xF
+
+#define CSCFG_BSEL_OFFSET 5
+#define CSCFG_BSEL_MASK 1
+
+#define CSCFG_BOOTEN_OFFSET 4
+#define CSCFG_BOOTEN_MASK 1
+
+#define CSCFG_SPICHNG_OFFSET 3
+#define CSCFG_SPICHNG_MASK 1
+
+#define CSCFG_MBM_OFFSET 1
+#define CSCFG_MBM_MASK 3
+
+#define CSCFG_SRAM_OFFSET 0
+#define CSCFG_SRAM_MASK 1
+
+/* HS_SPI Command Sequencer Idle Time Register */
+#define CSITIME_ITIME_OFFSET 0
+#define CSITIME_ITIME_MASK 0xFFFF
+
+/* HS_SPI Command Sequencer Address Extension Register */
+#define CSAEXT_AEXT_OFFSET 16
+#define CSAEXT_AEXT_MASK 0xFFFF
+
+/* HS_SPI Read Command Sequence Data/Control Register0-7 */
+#define RDCSDC_RDCSDATA_OFFSET 8
+#define RDCSDC_RDCSDATA_MASK 0x0F
+
+#define RDCSDC_CONT_OFFSET 3
+#define RDCSDC_CONT_MASK 1
+
+#define RDCSDC_TRP_OFFSET 1
+#define RDCSDC_TRP_MASK 0x3
+
+#define RDCSDC_DEC_OFFSET 0
+#define RDCSDC_DEC_MASK 1
+
+/* HS_SPI Write Command Sequence Data/Control Register0-7 */
+#define WRCSDC_WRCSDATA_OFFSET 8
+#define WRCSDC_WRCSDATA_MASK 0x0F
+
+#define WRCSDC_CONT_OFFSET 3
+#define WRCSDC_CONT_MASK 1
+
+#define WRCSDC_TRP_OFFSET 1
+#define WRCSDC_TRP_MASK 0x3
+
+#define WRCSDC_DEC_OFFSET 0
+#define WRCSDC_DEC_MASK 1
+
+/* Bit manipulation macros */
+#define HSSPI_BIT(bit) \
+ (1 << bit##_OFFSET)
+
+#define HSSPI_BITS(bits, val) \
+ (((val) & bits##_MASK) << bits##_OFFSET)
+
+#define HSSPI_BITS_GET(wid, bits, hs, reg) \
+ ((hs_spi_read##wid(hs, reg) >> bits##_OFFSET) & bits##_MASK)
+
+#define HSSPI_BITS_SET(wid, bits, val, hs, reg) do { \
+ hs_spi_read##wid(hs, reg); \
+ hs_spi_write##wid(hs, reg, ((hs_spi_read##wid(hs, reg) & \
+ ~(bits##_MASK << bits##_OFFSET)) | HSSPI_BITS(bits, val))); \
+ } while (0)
+
+/* Register access macros */
+#define hs_spi_fiforead(hs, regs) \
+ __raw_readb((hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_readb(hs, regs) \
+ readb((hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_readw(hs, regs) \
+ readw((hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_readl(hs, regs) \
+ readl((hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_writeb(hs, regs, val) \
+ writeb((val), (hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_writew(hs, regs, val) \
+ writew((val), (hs)->reg + HS_SPI_REG_##regs)
+
+#define hs_spi_writel(hs, regs, val) \
+ writel((val), (hs)->reg + HS_SPI_REG_##regs)
+
+#endif /* __HS_SPI_REG_H__ */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/spi/mb86s7x_hs_spi.c u-boot/drivers/spi/mb86s7x_hs_spi.c
--- original/u-boot-linaro-stable/drivers/spi/mb86s7x_hs_spi.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/spi/mb86s7x_hs_spi.c 2016-08-02 14:19:41.155727952 +0900
@@ -0,0 +1,581 @@
+/*
+ * u-boot/drivers/spi/mb86s7x_hs_spi.c
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+
+#include
+#include
+#include
+#include
+
+#include
+#include "hs_spi_reg.h"
+#include "mb8ac0300-hs_spi.h"
+#include
+
+
+/* HS_SPI all TX interrupts except Slave Select Released Interrupt */
+#define HS_SPI_TXINT_EXCEPT_TSSRC (TXC_TFMTC_MASK << TXC_TFMTC_OFFSET |\
+ TXC_TFLETC_MASK << TXC_TFLETC_OFFSET |\
+ TXC_TFUC_MASK << TXC_TFUC_OFFSET |\
+ TXC_TFOC_MASK << TXC_TFOC_OFFSET |\
+ TXC_TFEC_MASK << TXC_TFEC_OFFSET |\
+ TXC_TFFC_MASK << TXC_TFFC_OFFSET)
+/* HS_SPI all RX interrupts except Slave Select Released Interrupt */
+#define HS_SPI_RXINT_EXCEPT_RSSRC (RXC_RFMTC_MASK << RXC_RFMTC_OFFSET |\
+ RXC_RFLETC_MASK << RXC_RFLETC_OFFSET |\
+ RXC_RFUC_MASK << RXC_RFUC_OFFSET |\
+ RXC_RFOC_MASK << RXC_RFOC_OFFSET |\
+ RXC_RFEC_MASK << RXC_RFEC_OFFSET |\
+ RXC_RFFC_MASK << RXC_RFFC_OFFSET)
+/* HS_SPI all TX interrupts */
+#define HS_SPI_TX_ALL_INT (TXC_TSSRC_MASK << TXC_TSSRC_OFFSET |\
+ HS_SPI_TXINT_EXCEPT_TSSRC)
+/* HS_SPI all RX interrupts */
+#define HS_SPI_RX_ALL_INT (RXC_RSSRC_MASK << RXC_RSSRC_OFFSET |\
+ HS_SPI_RXINT_EXCEPT_RSSRC)
+/* HS_SPI all fault interrupts */
+#define HS_SPI_ALL_FAULT (FAULTC_DRCBSFC_MASK << FAULTC_DRCBSFC_OFFSET |\
+ FAULTC_DWCBSFC_MASK << FAULTC_DWCBSFC_OFFSET |\
+ FAULTC_PVFC_MASK << FAULTC_PVFC_OFFSET |\
+ FAULTC_WAFC_MASK << FAULTC_WAFC_OFFSET |\
+ FAULTC_UMAFC_MASK << FAULTC_UMAFC_OFFSET)
+/* HS_SPI mode bits mask value */
+#define HS_SPI_MODE_MASK (PCC_CPHA_MASK << PCC_CPHA_OFFSET |\
+ PCC_CPOL_MASK << PCC_CPOL_OFFSET |\
+ PCC_SSPOL_MASK << PCC_SSPOL_OFFSET |\
+ PCC_SDIR_MASK << PCC_SDIR_OFFSET)
+
+
+struct hs_spi *hs;
+static int init = 0;
+
+#ifdef HS_SPI_DEBUG
+static void dump_regs(struct hs_spi *hs)
+{
+ printf("reg:HS_SPI_REG_MCTRL, val:%x\n", hs_spi_readl(hs, MCTRL));
+ printf("reg:HS_SPI_REG_PCC0, val:%x\n", hs_spi_readl(hs, PCC0));
+ printf("reg:HS_SPI_REG_PCC1, val:%x\n", hs_spi_readl(hs, PCC1));
+ printf("reg:HS_SPI_REG_PCC2, val:%x\n", hs_spi_readl(hs, PCC2));
+ printf("reg:HS_SPI_REG_PCC3, val:%x\n", hs_spi_readl(hs, PCC3));
+ printf("reg:HS_SPI_REG_TXF, val:%x\n", hs_spi_readl(hs, TXF));
+ printf("reg:HS_SPI_REG_TXE, val:%x\n", hs_spi_readl(hs, TXE));
+ printf("reg:HS_SPI_REG_TXC, val:%x\n", hs_spi_readl(hs, TXC));
+ printf("reg:HS_SPI_REG_RXF, val:%x\n", hs_spi_readl(hs, RXF));
+ printf("reg:HS_SPI_REG_RXE, val:%x\n", hs_spi_readl(hs, RXE));
+ printf("reg:HS_SPI_REG_RXC, val:%x\n", hs_spi_readl(hs, RXC));
+
+ printf("reg:HS_SPI_REG_FAULTF, val:%x\n", hs_spi_readl(hs, FAULTF));
+ printf("reg:HS_SPI_REG_FAULTC, val:%x\n", hs_spi_readl(hs, FAULTC));
+ printf("reg:HS_SPI_REG_DMCFG, val:%x\n", hs_spi_readb(hs, DMCFG));
+ printf("reg:HS_SPI_REG_DMDMAEN, val:%x\n", hs_spi_readb(hs, DMDMAEN));
+ printf("reg:HS_SPI_REG_DMSTART, val:%x\n", hs_spi_readb(hs, DMSTART));
+ printf("reg:HS_SPI_REG_DMSTOP, val:%x\n", hs_spi_readb(hs, DMSTOP));
+ printf("reg:HS_SPI_REG_DMPSEL, val:%x\n", hs_spi_readb(hs, DMPSEL));
+ printf("reg:HS_SPI_REG_DMTRP, val:%x\n", hs_spi_readb(hs, DMTRP));
+ printf("reg:HS_SPI_REG_DMBCC, val:%x\n", hs_spi_readw(hs, DMBCC));
+ printf("reg:HS_SPI_REG_DMBCS, val:%x\n", hs_spi_readw(hs, DMBCS));
+ printf("reg:HS_SPI_REG_DMSTATUS, val:%x\n", hs_spi_readl(hs, DMSTATUS));
+ printf("reg:HS_SPI_REG_TXBITCNT, val:%x\n", hs_spi_readl(hs, TXBITCNT));
+ printf("reg:HS_SPI_REG_FIFOCFG, val:%x\n", hs_spi_readl(hs, FIFOCFG));
+ printf("reg:HS_SPI_REG_CSCFG, val:%x\n", hs_spi_readl(hs, CSCFG));
+ printf("reg:HS_SPI_REG_CSITIME, val:%x\n", hs_spi_readl(hs, CSITIME));
+ printf("reg:HS_SPI_REG_CSAEXT, val:%x\n", hs_spi_readl(hs, CSAEXT));
+
+ printf("reg:HS_SPI_REG_RDCSDC0, val:%x\n", hs_spi_readw(hs, RDCSDC0));
+ printf("reg:HS_SPI_REG_RDCSDC1, val:%x\n", hs_spi_readw(hs, RDCSDC1));
+ printf("reg:HS_SPI_REG_RDCSDC2, val:%x\n", hs_spi_readw(hs, RDCSDC2));
+ printf("reg:HS_SPI_REG_RDCSDC3, val:%x\n", hs_spi_readw(hs, RDCSDC3));
+ printf("reg:HS_SPI_REG_RDCSDC4, val:%x\n", hs_spi_readw(hs, RDCSDC4));
+ printf("reg:HS_SPI_REG_RDCSDC5, val:%x\n", hs_spi_readw(hs, RDCSDC5));
+ printf("reg:HS_SPI_REG_RDCSDC6, val:%x\n", hs_spi_readw(hs, RDCSDC6));
+ printf("reg:HS_SPI_REG_RDCSDC7, val:%x\n", hs_spi_readw(hs, RDCSDC7));
+ printf("reg:HS_SPI_REG_WRCSDC0, val:%x\n", hs_spi_readw(hs, WRCSDC0));
+ printf("reg:HS_SPI_REG_WRCSDC1, val:%x\n", hs_spi_readw(hs, WRCSDC1));
+ printf("reg:HS_SPI_REG_WRCSDC2, val:%x\n", hs_spi_readw(hs, WRCSDC2));
+ printf("reg:HS_SPI_REG_WRCSDC3, val:%x\n", hs_spi_readw(hs, WRCSDC3));
+ printf("reg:HS_SPI_REG_WRCSDC4, val:%x\n", hs_spi_readw(hs, WRCSDC4));
+ printf("reg:HS_SPI_REG_WRCSDC5, val:%x\n", hs_spi_readw(hs, WRCSDC5));
+ printf("reg:HS_SPI_REG_WRCSDC6, val:%x\n", hs_spi_readw(hs, WRCSDC6));
+ printf("reg:HS_SPI_REG_WRCSDC7, val:%x\n", hs_spi_readw(hs, WRCSDC7));
+ printf("reg:HS_SPI_REG_MID, val:%x\n", hs_spi_readl(hs, MID));
+
+}
+#endif
+
+/*
+ * hs_spi_read_dummy - read dummy from the receive FIFO at direct mode
+ * @hs: HS SPI device platform data.
+ *
+ * When transfer protocol is TX_RX,
+ * While TX-FIFO is transmitting data, RX-FIFO is also receiving dummy
+ * at the same time.
+ */
+static void hs_spi_read_dummy(struct hs_spi *hs)
+{
+ unsigned int rxbytes = HSSPI_BITS_GET(l, DMSTATUS_RXFLEVEL, hs,
+ DMSTATUS);
+ unsigned int i;
+ unsigned char rxdata;
+
+ for (i = 0; i < rxbytes; i++) {
+ rxdata = hs_spi_fiforead(hs, RXFIFO0);
+ debug("dummy data:%x", rxdata);
+ }
+
+ barrier(); /* why? */
+}
+
+
+static void hs_spi_chipselect(struct hs_spi *hs)
+{
+ HSSPI_BITS_SET(l, DMPSEL_PSEL, hs->chip_select, hs, DMPSEL);
+ HSSPI_BITS_SET(l, DMSTOP_STOP, 0, hs, DMSTOP);
+}
+
+static void hs_spi_stop_transfer(struct hs_spi *hs)
+{
+ HSSPI_BITS_SET(l, DMSTOP_STOP, 1, hs, DMSTOP);
+ while (!HSSPI_BITS_GET(l, DMSTOP_STOP, hs, DMSTOP))
+ ;
+ if (hs->rx || ((hs->tx == NULL) && (hs->rx == NULL)))
+ hs_spi_read_dummy(hs);
+ while (!(HSSPI_BITS_GET(l, TXF_TSSRS, hs, TXF) |
+ HSSPI_BITS_GET(l, RXF_RSSRS, hs, RXF)))
+ ;
+}
+
+
+/*
+ * hs_spi_write_tx_fifo - write datas into the transmit FIFO at direct mode
+ * @hs: HS SPI device platform data.
+ *
+ * No more than 16 byte datas can be write once.
+ *
+ * Returns write data size
+ */
+static int hs_spi_write_tx_fifo(struct hs_spi *hs)
+{
+ unsigned int txflevel = HSSPI_BITS_GET(l, DMSTATUS_TXFLEVEL, hs,
+ DMSTATUS);
+ unsigned int txbytes = min(HS_SPI_FIFO_LEN - txflevel,
+ hs->len - hs->tx_cnt);
+ unsigned int i;
+ unsigned char txdata;
+
+ //printf("write tx fifo:");
+
+ for (i = 0; i < txbytes; i++) {
+ txdata = hs->tx ? hs->tx[hs->tx_cnt + i] : 0xFF;
+ hs_spi_writeb(hs, TXFIFO0, txdata);
+ //printf("%02x", txdata);
+ }
+
+ //printf("\nwrite done\n");
+
+ return txbytes;
+}
+
+/*
+ * hs_spi_read_rx_fifo - read datas from the receive FIFO direct mode
+ * @hs: HS SPI device platform data.
+ *
+ * No more then 16 byte datas can be read once.
+ *
+ * Returns read data size
+ */
+static int hs_spi_read_rx_fifo(struct hs_spi *hs)
+{
+ unsigned int rxflevel = HSSPI_BITS_GET(l, DMSTATUS_RXFLEVEL, hs,
+ DMSTATUS);
+ unsigned int rxbytes = min(rxflevel, hs->len - hs->rx_cnt);
+ unsigned int i;
+ unsigned char rxdata;
+
+ //printf("read rx fifo, rxflevel:%d, data:", rxflevel);
+
+ for (i = 0; i < rxbytes; i++) {
+ rxdata = hs_spi_fiforead(hs, RXFIFO0);
+ hs->rx[hs->rx_cnt + i] = rxdata;
+ //printf("%02x", rxdata);
+ }
+ barrier(); /* dunno why this is needed */
+
+ //printf("\nread done\n");
+
+ return rxbytes;
+}
+
+static int hs_spi_tx(struct hs_spi *hs)
+{
+ int txf;
+
+ while(hs->tx_cnt <= hs->len) {
+ txf = hs_spi_readl(hs, TXF) & 0x7F;
+
+ if(!txf)
+ continue;
+
+ /* clear flags */
+ hs_spi_writel(hs, TXC, HS_SPI_TXINT_EXCEPT_TSSRC);
+
+ if (txf & HSSPI_BIT(TXF_TFLETS)) {
+ debug("TX-FIFO Fill Level <= Threshold\n");
+ if (hs->tx_cnt < hs->len)
+ hs->tx_cnt += hs_spi_write_tx_fifo(hs);
+ }
+
+ if (txf & HSSPI_BIT(TXF_TFES)) {
+ debug("TX-FIFO and Shift Register is Empty\n");
+ if (hs->tx_cnt >= hs->len) {
+ //hs_spi_writel(hs, TXE, 0x00);
+ break;
+ }
+ }
+ }
+
+ return 0;
+
+}
+
+static int hs_spi_rx(struct hs_spi *hs)
+{
+ int rxf;
+
+ while(hs->rx_cnt < hs->len) {
+ rxf = hs_spi_readl(hs, RXF) & 0x7F;
+
+ if(!rxf)
+ continue;
+
+ /* clear flags */
+ hs_spi_writel(hs, RXC, HS_SPI_RXINT_EXCEPT_RSSRC);
+
+ if (rxf & HSSPI_BIT(RXF_RFMTS)) {
+ debug("RX-FIFO Fill Level is More Than Threshold\n");
+ hs->rx_cnt += hs_spi_read_rx_fifo(hs);
+ if (hs->rx_cnt >= hs->len) {
+ //hs_spi_writel(hs, RXE, 0x00);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int hs_spi_txrx(struct hs_spi *hs)
+{
+ /* Flush RX and TX FIFO */
+ HSSPI_BITS_SET(l, FIFOCFG_TXFLSH, 1, hs, FIFOCFG);
+ HSSPI_BITS_SET(l, FIFOCFG_RXFLSH, 1, hs, FIFOCFG);
+
+ if (hs->tx) {
+ /* set tx transfer protocol */
+ if (hs->bitwidth == 2) {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_DUAL_TX_ONLY,
+ hs, DMTRP);
+ } else if (hs->bitwidth == 4) {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_QUAD_TX_ONLY,
+ hs, DMTRP);
+ } else {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_LEGACY_TX_ONLY,
+ hs, DMTRP);
+ }
+ hs->tx_cnt += hs_spi_write_tx_fifo(hs);
+ } else {
+ /* set rx transfer protocol */
+ if (hs->bitwidth == 2) {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_DUAL_RX_ONLY,
+ hs, DMTRP);
+ } else if (hs->bitwidth == 4) {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_QUAD_RX_ONLY,
+ hs, DMTRP);
+ } else {
+ HSSPI_BITS_SET(l, DMTRP_TRP, HS_SPI_LEGACY_RX_ONLY,
+ hs, DMTRP);
+ }
+ }
+ hs_spi_writel(hs, TXC, HS_SPI_TX_ALL_INT);
+ hs_spi_writel(hs, RXC, HS_SPI_RX_ALL_INT);
+ /* start transfer */
+ HSSPI_BITS_SET(l, DMSTART_START, 1, hs, DMSTART);
+ if (hs->tx) {
+ //hs_spi_writel(hs, TXE, TXE_TFLETE_MASK << TXE_TFLETE_OFFSET |
+ // TXE_TFEE_MASK << TXE_TFEE_OFFSET | TXE_TSSRE_OFFSET << TXE_TSSRE_OFFSET);
+ hs_spi_tx(hs);
+ }
+ if (hs->rx) {
+ //hs_spi_writel(hs, RXE, RXE_RFMTE_MASK << RXE_RFMTE_OFFSET |
+ // RXE_RSSRE_MASK << RXE_RSSRE_OFFSET);
+ hs_spi_rx(hs);
+ }
+
+ if (hs->fault_flag)
+ return -EPERM;
+
+ return hs->rx ? hs->rx_cnt : hs->tx_cnt;
+}
+
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+
+ spi_init();
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave->bus = bus;
+ slave->cs = cs;
+
+ return slave;
+
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ return;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ int ret;
+ if(!hs) {
+ printf("spi device not exist\n");
+ return -ENODEV;
+ }
+
+ hs->chip_select = slave->cs;
+ hs_spi_chipselect(hs);
+
+// printf("spi_xfer, bitlen:%d, dout:%x, din:%x, flags:%x\n", bitlen, (unsigned int)dout,
+// (unsigned int)din, flags);
+
+ hs->tx = dout;
+ hs->rx = din;
+ hs->fault_flag = 0;
+ hs->tx_cnt = 0;
+ hs->rx_cnt = 0;
+ hs->len = bitlen / 8; /* length in byte */
+
+ ret = hs_spi_txrx(hs);
+
+ if(flags & SPI_XFER_END) {
+ hs_spi_stop_transfer(hs);
+ }
+
+ return ret <= 0;
+
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ unsigned int div;
+ unsigned long rate;
+ unsigned char safesync = 0;
+ u32 csval = 0x230508;
+
+ rate = 125000000;
+
+ div = DIV_ROUND_UP(rate, hz * 2);
+ /*
+ * If the resulting divider doesn't fit into the
+ * register bitfield, we can't satisfy the constraint.
+ */
+ if (div > 127) {
+ printf("setup: %d Hz too slow, div %u; min %ld Hz\n",
+ hz, div, rate / (2 * 127));
+ return;
+ }
+
+#if 0
+ /* safesync bit */
+ if (hs->mode == HS_SPI_DIRECT_MODE) {
+ /* direct mode */
+ if (((spi->rx_bitwidth == 4) ||
+ (spi->tx_bitwidth == 4)) &&
+ (div < 3))
+ safesync = 1;
+ } else
+ /* cs mode */
+ if (hs->pdata->clock == HS_SPI_PCLK)
+ if (((spi->rx_bitwidth == 4) ||
+ (spi->tx_bitwidth == 4)) &&
+ (div < 3))
+ safesync = 1;
+#else
+ safesync = 0;
+#endif
+
+ switch (hs->chip_select) {
+ case 0:
+ HSSPI_BITS_SET(l, PCC_CDRS, div, hs, PCC0);
+ HSSPI_BITS_SET(l, PCC_ESYNC, safesync, hs, PCC0);
+ HSSPI_BITS_SET(l, PCC_ACES, 0, hs, PCC0);
+ HSSPI_BITS_SET(l, PCC_CPHA, 0, hs, PCC0);
+ debug("Spi speed is set to %dHz, div:%u\n",
+ hz, HSSPI_BITS_GET(l, PCC_CDRS, hs, PCC0));
+
+ /* for now set them all to something good for mb86s70 */
+
+ writel(csval, hs->reg + 4);
+ writel(csval, hs->reg + 8);
+ writel(csval, hs->reg + 0xc);
+ writel(csval, hs->reg + 0x10);
+ break;
+ case 1:
+ HSSPI_BITS_SET(l, PCC_CDRS, div, hs, PCC1);
+ HSSPI_BITS_SET(l, PCC_ESYNC, safesync, hs, PCC1);
+ debug("Spi speed is set to %dHz, div:%u\n",
+ hz, HSSPI_BITS_GET(l, PCC_CDRS, hs, PCC1));
+ /* for now set them all to something good for mb86s70 */
+
+ writel(csval, hs->reg + 4);
+ writel(csval, hs->reg + 8);
+ writel(csval, hs->reg + 0xc);
+ writel(csval, hs->reg + 0x10);
+ break;
+ case 2:
+ HSSPI_BITS_SET(l, PCC_CDRS, div, hs, PCC2);
+ HSSPI_BITS_SET(l, PCC_ESYNC, safesync, hs, PCC2);
+ debug("Spi speed is set to %dHz, div:%u\n",
+ hz, HSSPI_BITS_GET(l, PCC_CDRS, hs, PCC2));
+ break;
+ case 3:
+ HSSPI_BITS_SET(l, PCC_CDRS, div, hs, PCC3);
+ HSSPI_BITS_SET(l, PCC_ESYNC, safesync, hs, PCC3);
+ debug("Spi speed is set to %dHz, div:%u\n",
+ hz, HSSPI_BITS_GET(l, PCC_CDRS, hs, PCC3));
+ break;
+ default:
+ printf("setup: invalid chipselect %u (%u defined)\n",
+ hs->chip_select, 2);
+ return;
+ }
+ //cs->speed_hz = hz;
+
+ return;
+
+}
+
+void hs_spi_cleanup(void)
+{
+ if(!init)
+ return;
+
+ if(!hs)
+ return;
+
+ /* disable all interrupts */
+ hs_spi_writel(hs, TXE, 0x00);
+ hs_spi_writel(hs, RXE, 0x00);
+
+ /* clear all interrupts */
+ hs_spi_writel(hs, TXC, 0x7F);
+ hs_spi_writel(hs, RXC, 0x7F);
+ hs_spi_writel(hs, FAULTC, 0x7F);
+
+ /* clean up memory */
+ if(hs)
+ free(hs);
+ init = 0;
+}
+
+void spi_init(void)
+{
+ if(init)
+ return;
+
+ hs = malloc(sizeof(struct hs_spi));
+ if(!hs) {
+ return;
+ }
+
+ hs->reg = (void *)F_SPI_IP_BASE;
+ hs->mode = HS_SPI_DIRECT_MODE;
+ hs->clk_source = HS_SPI_HCLK;
+ hs->chip_select = 0;
+ hs->bitwidth = 8;
+ hs->tx = NULL;
+ hs->rx = NULL;
+
+ /* change to dm mode */
+ HSSPI_BITS_SET(l, MCTRL_CSEN, 0, hs, MCTRL);
+
+ HSSPI_BITS_SET(l, MCTRL_MEN, 0, hs, MCTRL);
+ while (HSSPI_BITS_GET(l, MCTRL_MES, hs, MCTRL))
+ ;
+
+ /* disable interrupt */
+ hs_spi_writel(hs, TXE, 0x00);
+ hs_spi_writel(hs, RXE, 0x00);
+ /* clear interrupt flag */
+ hs_spi_writel(hs, TXC, HS_SPI_TXINT_EXCEPT_TSSRC);
+ hs_spi_writel(hs, RXC, HS_SPI_RXINT_EXCEPT_RSSRC);
+
+ /* read module ID */
+ //printf("HS SPI module ID:%#4x\n", hs_spi_readl(hs, MID));
+
+ /* Clock Division Source Select 0:AHBCLK 1:PCLK*/
+ if (hs->clk_source == HS_SPI_HCLK)
+ HSSPI_BITS_SET(l, MCTRL_CDSS, 0, hs, MCTRL);
+ else
+ HSSPI_BITS_SET(l, MCTRL_CDSS, 1, hs, MCTRL);
+
+ if (hs->mode != HS_SPI_COMMAND_SEQUENCER)
+ /* set to software flow control mode */
+ HSSPI_BITS_SET(l, DMCFG_SSDC, 0, hs, DMCFG);
+ else
+ /* set to hardware flow control mode */
+ HSSPI_BITS_SET(l, DMCFG_SSDC, 1, hs, DMCFG);
+
+ /* configure the FIFO threshold levels and the FIFO width */
+ hs_spi_writel(hs, FIFOCFG,
+ HSSPI_BITS(FIFOCFG_FWIDTH, HS_SPI_FIFO_WIDTH) |
+ HSSPI_BITS(FIFOCFG_TXFTH, HS_SPI_TX_FIFO_LEVEL) |
+ HSSPI_BITS(FIFOCFG_RXFTH, HS_SPI_RX_FIFO_LEVEL));
+
+ /* enable module */
+ HSSPI_BITS_SET(l, MCTRL_MEN, 1, hs, MCTRL);
+ while (!HSSPI_BITS_GET(l, MCTRL_MES, hs, MCTRL))
+ ;
+
+ /* set max speed, don't need the slave parameter because we use only 1 chip */
+ spi_set_speed(NULL, 31250000);
+
+ /* enable all interrupt from tx or rx*/
+ hs_spi_writel(hs, TXE, 0x7F);
+ hs_spi_writel(hs, RXE, 0x7F);
+
+ init = 1;
+}
+
diff -urNa -x .git original/u-boot-linaro-stable/drivers/spi/mb8ac0300-hs_spi.h u-boot/drivers/spi/mb8ac0300-hs_spi.h
--- original/u-boot-linaro-stable/drivers/spi/mb8ac0300-hs_spi.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/spi/mb8ac0300-hs_spi.h 2016-08-02 14:19:41.155727952 +0900
@@ -0,0 +1,154 @@
+/*
+ * linux/arch/arm/mach-mb8ac0300/include/mach/hs_spi.h
+ *
+ * Copyright (C) 2010-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef __MACH_HS_SPI_H
+#define __MACH_HS_SPI_H
+
+
+#define HS_SPI_CS_DELAY 3 /* Slave-Select to Clock Delay */
+#define HS_SPI_FIFO_WIDTH 0 /* FIFO Width (1byte) */
+#define HS_SPI_TX_FIFO_LEVEL 1 /* TX-FIFO Threshold Level */
+#define HS_SPI_RX_FIFO_LEVEL 0 /* RX-FIFO Threshold Level */
+#define HS_SPI_FIFO_LEN 16 /* FIFO Length */
+
+#define HS_SPI_MAX_TRANSFER_LEN 0xFFFF /* Max numbers of transfer bytes */
+/*
+ * HS_SPI Direct Mode Transfer Protocol
+ */
+#define HS_SPI_LEGACY_TX_RX 0x00 /* TX and RX, in legacy mode */
+#define HS_SPI_LEGACY_RX_ONLY 0x04 /* RX only, in legacy mode */
+#define HS_SPI_DUAL_RX_ONLY 0x05 /* RX only, in dual mode */
+#define HS_SPI_QUAD_RX_ONLY 0x06 /* RX only, in quad mode */
+#define HS_SPI_LEGACY_TX_ONLY 0x08 /* TX only, in legacy mode */
+#define HS_SPI_DUAL_TX_ONLY 0x09 /* TX only, in dual mode */
+#define HS_SPI_QUAD_TX_ONLY 0x0A /* TX only, in quad mode */
+
+/*
+ * HS_SPI Command Sequencer Mode
+ */
+#define HS_SPI_IDLE_TIME 0xFFFF /* Command Sequencer Idle Time */
+#define HS_SPI_CS_CONT_BIT 0x08 /* Command Sequencer Continuous bit */
+#define HS_SPI_CS_1BIT (3<<1) /* Command Sequencer Protocol 1bit*/
+#define HS_SPI_CS_2BIT (2<<1) /* Command Sequencer Protocol 2bit*/
+#define HS_SPI_CS_4BIT (1<<1) /* Command Sequencer Protocol 4bit*/
+
+#define HS_SPI_DECODE_ADDR3 0x0301 /* Transmit address bits [31:24] */
+#define HS_SPI_DECODE_ADDR2 0x0201 /* Transmit address bits [23:16] */
+#define HS_SPI_DECODE_ADDR1 0x0101 /* Transmit address bits [15:08] */
+#define HS_SPI_DECODE_ADDR0 0x0001 /* Transmit address bits [07:00] */
+#define HS_SPI_HIGH_Z_BYTE 0x0401 /* High-Z byte for 1 byte time */
+#define HS_SPI_LIST_END 0x0701 /* Command Sequencer List End */
+/*
+ * HS_SPI Command Sequencer Multi Bit Mode
+ */
+#define HS_SPI_LEGACY_BIT 0x00 /* use the legacy SPI protocol */
+#define HS_SPI_DUAL_BIT 0x01 /* use the dual-bit SPI protocol */
+#define HS_SPI_QUAD_BIT 0x02 /* use the quad-bit SPI protocol */
+#define HS_SPI_CR_QUAD 0x02 /* Quad Mode Flag */
+#define HS_SPI_SR_WIP 0x01 /* Write In Progress Flag */
+#define HS_SPI_CONTINUOUS_READ_MODE 0xA0 /* Continuous read mode bits value */
+
+/*
+ * Flash operation codes
+ */
+#define HS_SPI_CMD_RDID 0x9f /* Read JEDEC ID */
+#define HS_SPI_CMD_NORM_READ 0x03 /* Read data bytes (low frequency) */
+#define HS_SPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
+#define HS_SPI_CMD_DOR 0x3B /* Dual Output Read */
+#define HS_SPI_CMD_QOR 0x6B /* Quad Output Read */
+#define HS_SPI_CMD_DIOR 0xBB /* Dual I/O High Performance Read */
+#define HS_SPI_CMD_QIOR 0xEB /* Quad I/O High Performance Read */
+#define HS_SPI_CMD_WREN 0x06 /* Write enable */
+#define HS_SPI_CMD_WRDN 0x04 /* Write Disable */
+#define HS_SPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define HS_SPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
+#define HS_SPI_CMD_BE_4K 0x20 /* Erase 4KiB block */
+#define HS_SPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
+#define HS_SPI_CMD_QPP 0x32 /* Quad Page Programming */
+#define HS_SPI_CMD_RDSR 0x05 /* Read status register */
+#define HS_SPI_CMD_WRSR 0x01 /* Write status register 1 byte */
+#define HS_SPI_CMD_RCR 0x35 /* Read Configuration Register (CFG) */
+
+
+#define HS_SPI_DIRECT_MODE 1
+#define HS_SPI_COMMAND_SEQUENCER 2
+
+#define HS_SPI_HCLK 0
+#define HS_SPI_PCLK 1
+
+/**
+ * struct hs_spi_pdata - HS SPI device platform data
+ * @mode: Direct mode or command sequencer mode.
+ * @read_operation: Read operation for direct mode and command sequencer mode.
+ * @write_operation: Write operation only for direct mode.
+ * @num_chipselect: Max numbers of slaves can be selected.
+ * @addr_width: Address width (number of bytes) for slaves.
+ * @bits_per_word: Data transfers involve one or more words; word sizes
+ * @bank_size: Bank size of each external memory devices.
+ *
+ * A @hs_spi_pdata is used by hs spi driver.
+ */
+struct hs_spi_pdata {
+ int mode;
+ int num_chipselect; /* total chipselects */
+ int bank_size; /* bank size */
+ int clock;
+ int syncon;
+};
+
+/* HS_SPI Controller driver's data. */
+
+/**
+ * struct hs_spi - HS_SPI Controller driver's data.
+ * @csa: Command sequencer access area.
+ *
+ * Other members of the struct are private.
+ *
+ * A @csa is used by flash driver hs_spi_flash.
+ */
+struct hs_spi {
+ /* private */
+
+ int tx_irq;
+ int rx_irq;
+ int fault_irq;
+ unsigned int len;
+ unsigned int tx_cnt;
+ unsigned int rx_cnt;
+ int fault_flag;
+ int bank_size;
+
+ int chip_select;
+
+ int stop;
+
+ /* data buffers */
+ const unsigned char *tx;
+ unsigned char *rx;
+
+ //struct clk *clk;
+ int clk_source;
+ int mode;
+
+ void *reg;
+
+ /* spi transfer protocol */
+ unsigned int bitwidth;
+};
+
+#endif /* __MACH_HS_SPI_H */
diff -urNa -x .git original/u-boot-linaro-stable/drivers/usb/host/Makefile u-boot/drivers/usb/host/Makefile
--- original/u-boot-linaro-stable/drivers/usb/host/Makefile 2016-08-02 12:12:09.077772051 +0900
+++ u-boot/drivers/usb/host/Makefile 2016-08-02 14:19:41.167727900 +0900
@@ -57,6 +57,7 @@
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+COBJS-$(CONFIG_USB_EHCI_F_USB20HO) += ehci-f_usb20ho.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff -urNa -x .git original/u-boot-linaro-stable/drivers/usb/host/ehci-f_usb20ho.c u-boot/drivers/usb/host/ehci-f_usb20ho.c
--- original/u-boot-linaro-stable/drivers/usb/host/ehci-f_usb20ho.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/usb/host/ehci-f_usb20ho.c 2016-08-02 14:19:41.168727896 +0900
@@ -0,0 +1,68 @@
+/**
+ * f_usb20ho_lap.c - Fujitsu EHCI platform driver
+ *
+ * Copyright (c) 2013 FUJITSU SEMICONDUCTOR LIMITED
+ * http://jp.fujitsu.com/group/fsl
+ *
+ * based on bcma-hcd.c
+ *
+ * Author: FUJITSU SEMICONDUCTOR
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include "ehci.h"
+#include
+#ifdef MB86S7X_MHU_PHYS
+#include
+#define DISABLE 0
+#define ENABLE 1
+#endif
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret = 0;
+
+ /* assign base address */
+ *hccr = (struct ehci_hccr *)F_USB20HO_LAP_EHCI_BASE;
+ *hcor = (struct ehci_hcor *)(F_USB20HO_LAP_EHCI_BASE + 0x10);
+
+#ifdef CONFIG_MB86S7X_MHU
+ /* enable power domain and usb 2.0 ehci host clock */
+ if (!get_power_state(CONFIG_F_USB20HO_POWERDOMAIN))
+ ret = set_power_state(CONFIG_F_USB20HO_POWERDOMAIN, ENABLE);
+
+ if (ret)
+ return ret;
+
+ set_clk_state(2, 2, 4, ENABLE); /* main_2_4 */
+ set_clk_state(2, 4, 5, ENABLE); /* main_4_5 */
+ set_clk_state(4, 0, 0, ENABLE); /* usb_0_0 */
+#endif
+
+ return ret;
+}
+
+int ehci_hcd_stop(int index)
+{
+#ifdef CONFIG_MB86S7X_MHU
+ int ret = 0;
+
+ /* disable PD#9 and PD#10 */
+
+ if (get_power_state(CONFIG_F_USB20HO_POWERDOMAIN))
+ ret = set_power_state(CONFIG_F_USB20HO_POWERDOMAIN, DISABLE);
+
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
diff -urNa -x .git original/u-boot-linaro-stable/drivers/video/Makefile u-boot/drivers/video/Makefile
--- original/u-boot-linaro-stable/drivers/video/Makefile 2016-08-02 12:12:09.082772033 +0900
+++ u-boot/drivers/video/Makefile 2016-08-02 14:19:41.175727866 +0900
@@ -43,6 +43,7 @@
COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
+COBJS-$(CONFIG_VIDEO_MB8AC0300) += mb8ac0300-fb.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
diff -urNa -x .git original/u-boot-linaro-stable/drivers/video/mb8ac0300-fb.c u-boot/drivers/video/mb8ac0300-fb.c
--- original/u-boot-linaro-stable/drivers/video/mb8ac0300-fb.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/drivers/video/mb8ac0300-fb.c 2016-08-02 14:19:41.221727666 +0900
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2013 Linaro Ltd
+ */
+
+#include
+#include
+#include
+
+#include "videomodes.h"
+#include
+#include
+#include
+#include
+
+struct mb8ac0300_par {
+ u32 pseudo_palette[16];
+ u32 *gpu_base;
+ dma_addr_t fbpaddr; /* real start of allocation */
+ void * fb_va;
+ u32 framesize;
+ u32 skip;
+ u32 round;
+};
+
+#define MB8AC0300GPU_BLOCK_OFS_CRTC0 0x400
+#define MB8AC0300GPU_BLOCK_OFS_CRTC1 0x500
+
+/* offset in 4-byte units */
+enum {
+ MB8AC0300_CRTC_OFS__H_CTR_SIZE = 0,
+ MB8AC0300_CRTC_OFS__H_ADDR_TIME_START = 1,
+ MB8AC0300_CRTC_OFS__H_RIGHT_BORDER_START = 2,
+ MB8AC0300_CRTC_OFS__H_BLANK_START = 3,
+ MB8AC0300_CRTC_OFS__H_LEFT_BORDER_START = 6,
+ MB8AC0300_CRTC_OFS__H_SYNC_START = 4,
+ MB8AC0300_CRTC_OFS__H_BACK_PORCH_START = 5,
+ MB8AC0300_CRTC_OFS__H_INTERRUPT_END_START = 7,
+ MB8AC0300_CRTC_OFS__H_DMA_END_START = 8,
+ MB8AC0300_CRTC_OFS__V_COUNTER_SIZE = 9,
+ MB8AC0300_CRTC_OFS__V_ADDR_TIME_START = 10,
+ MB8AC0300_CRTC_OFS__V_BOTTOM_BORDER_START = 11,
+ MB8AC0300_CRTC_OFS__V_BLANK_START = 12,
+ MB8AC0300_CRTC_OFS__V_TOP_BORDER_START = 15,
+ MB8AC0300_CRTC_OFS__V_SYNC_START = 13,
+ MB8AC0300_CRTC_OFS__V_BACK_PORCH_START = 14,
+ MB8AC0300_CRTC_OFS__V_INTERRUPT_END_START = 16,
+ MB8AC0300_CRTC_OFS__V_INCREMENT_H_VALUE = 17,
+ MB8AC0300_CRTC_OFS__OUT_SIZE = (0x5c >> 2),
+ MB8AC0300_CRTC_OFS__DATA_SIZE = (0x90 >> 2),
+ MB8AC0300_CRTC_OFS__ADR_FB0 = (0x68 >> 2),
+ MB8AC0300_CRTC_OFS__ADR_FB1 = (0x6c >> 2),
+ MB8AC0300_CRTC_OFS__SIGNAL_POL = 18,
+ MB8AC0300_CRTC_OFS__DATA_FMT = (0x70 >> 2),
+ MB8AC0300_CRTC_OFS__PIC_BORDER_H_END_START = 0x18,
+ MB8AC0300_CRTC_OFS__PIC_BORDER_V_END_START = 0x19,
+ MB8AC0300_CRTC_OFS__RAM_ADR_GAMMA = (0x80 >> 2), /* same ofs for fb0/1 */
+ MB8AC0300_CRTC_OFS__RAM_DATA_GAMMA = 0x21,
+ MB8AC0300_CRTC_OFS__START = (0x74 >> 2),
+};
+
+/* H Counter Size */
+#define HCOUNT_SIZE (1056 - 1)
+/* H Addr Time Start */
+#define H_ADD_TIM_S (215 + 6 - 1)
+/* H Sync Start */
+#define H_SYNC_STAT (6 - 1)
+/* H Back Porch Start */
+#define H_BACKPO_ST (128 + 6 - 1)
+/* H Right Border Start/Blank Start */
+#define HRBORDER_ST (1021 - 1)
+
+/* V Counter Size */
+#define VCOUNT_SIZE (525 - 1)
+/* V Addr Time Start */
+#define V_ADD_TIM_S (35 + 2 - 1)
+/* V Bottom Border Start/Blank Start */
+#define VBBORDER_ST (515 + 2 - 1)
+/* V Sync Start (2) */
+#define V_SYNC_STAT 1
+/* V Back Porch Start */
+#define V_BACKPO_ST (12 - 1)
+
+/* V Increment H Value */
+#define V_INCR_H_VA (H_SYNC_STAT - 3)
+/* DAT_SIZE(OUT_HEIGHT/OUT_WIDTH) */
+#define DATSIZE_H_W ((360 << 16) | 600)
+/* OUT_SIZE(OUT_HEIGHT/OUT_WIDTH) */
+#define OUTSIZE_H_W ((480 << 16) | 800)
+/* SIGNAL_POL V,H Posedge OUT */
+#define SIGNAL__POL 0
+
+/* H Counter Size */
+#define HCOUNT_SIZE1 (1056 - 1)
+/* H Addr Time Start */
+#define H_ADD_TIM_S1 (215 + 6 - 1)
+/* H Left Border Start */
+#define HLBORDER_ST1 H_ADD_TIM_S1
+/* H Left Border Start */
+#define HLBORDER_ST H_ADD_TIM_S1
+/* H Sync Start */
+#define H_SYNC_STAT1 (6 - 1)
+/* H Back Porch Start */
+#define H_BACKPO_ST1 (128 + 6 - 1)
+/* H Right Border Start/Blank Start */
+#define HRBORDER_ST1 (1021 - 1)
+
+/* V Counter Size */
+#define VCOUNT_SIZE1 (525 - 1)
+/* V Addr Time Start */
+#define V_ADD_TIM_S1 (35 + 2 - 1)
+/* V TOP Border Start */
+#define VTBORDER_ST V_ADD_TIM_S1
+/* V Bottom Border Start/Blank Start */
+#define VBBORDER_ST1 (515 + 2 - 1)
+/* V Sync Start (2) */
+#define V_SYNC_STAT1 1
+/* V Back Porch Start */
+#define V_BACKPO_ST1 (12 - 1)
+/* V TOP Border Start */
+#define VTBORDER_ST1 V_ADD_TIM_S1
+/* V Increment H Value */
+#define V_INCR_H_VA1 (H_SYNC_STAT1 - 3)
+/* DAT_SIZE(OUT_HEIGHT/OUT_WIDTH) */
+#define DATSIZE_H_W1 ((360 << 16) | 600)
+/* OUT_SIZE(OUT_HEIGHT/OUT_WIDTH) */
+#define OUTSIZE_H_W1 ((480 << 16) | 800)
+/* SIGNAL_POL V,H Posedge OUT */
+#define SIGNAL__POL1 0
+
+
+void lcd_ctrl_init(void *lcd_base)
+{
+ volatile u32 __iomem *crtc = (void *)
+ (GPU_BASE + MB8AC0300GPU_BLOCK_OFS_CRTC0);
+ volatile u32 __iomem *crtc0 = crtc;
+ volatile u32 __iomem *gpio = (void *)GPIO1_BASE;
+ u32 col;
+ int bpp = 16;
+ int bytes_pp = (bpp + 7) / 8;
+ int mode = 2;
+ int xres = 800;
+ int yres = 480;
+
+ crtc[MB8AC0300_CRTC_OFS__START] = 0;
+
+ /* set GPIO mux state to LCD pixel data + control signals */
+
+ gpio[0x2c >> 2] = 0xff;
+ gpio[0x28 >> 2] = 0xff;
+ gpio[0x24 >> 2] = 0xff;
+ gpio[0x1c >> 2] = 0xff;
+ gpio[0x18 >> 2] = 0xff;
+ gpio[0x14 >> 2] = 0xff;
+ gpio[0x20 >> 2] = 0xf0;
+ gpio[0x10 >> 2] = 0xf0;
+
+ crtc[MB8AC0300_CRTC_OFS__H_CTR_SIZE] = HCOUNT_SIZE;
+ crtc[MB8AC0300_CRTC_OFS__H_ADDR_TIME_START] = H_ADD_TIM_S;
+ crtc[MB8AC0300_CRTC_OFS__H_RIGHT_BORDER_START] = HRBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__H_BLANK_START] = HRBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__H_LEFT_BORDER_START] = HLBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__H_SYNC_START] = H_SYNC_STAT;
+ crtc[MB8AC0300_CRTC_OFS__H_BACK_PORCH_START] = H_BACKPO_ST;
+ crtc[MB8AC0300_CRTC_OFS__H_INTERRUPT_END_START] =
+ (H_BACKPO_ST << 16) | H_SYNC_STAT;
+ crtc[MB8AC0300_CRTC_OFS__H_DMA_END_START] =
+ ((H_SYNC_STAT + 1) << 16) | H_SYNC_STAT;
+ crtc[MB8AC0300_CRTC_OFS__V_COUNTER_SIZE] = VCOUNT_SIZE;
+ crtc[MB8AC0300_CRTC_OFS__V_ADDR_TIME_START] = V_ADD_TIM_S;
+ crtc[MB8AC0300_CRTC_OFS__V_BOTTOM_BORDER_START] = VBBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__V_BLANK_START] = VBBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__V_TOP_BORDER_START] = VTBORDER_ST;
+ crtc[MB8AC0300_CRTC_OFS__V_SYNC_START] = V_SYNC_STAT;
+ crtc[MB8AC0300_CRTC_OFS__V_BACK_PORCH_START] = V_BACKPO_ST;
+ crtc[MB8AC0300_CRTC_OFS__V_INTERRUPT_END_START] =
+ (V_BACKPO_ST << 16) | V_SYNC_STAT;
+ crtc[MB8AC0300_CRTC_OFS__V_INCREMENT_H_VALUE] = V_INCR_H_VA;
+ crtc[MB8AC0300_CRTC_OFS__OUT_SIZE] = (yres << 16) | xres;
+ crtc[MB8AC0300_CRTC_OFS__DATA_SIZE] = xres * bytes_pp;
+
+ crtc[MB8AC0300_CRTC_OFS__ADR_FB0] = (u32)lcd_base;
+ crtc[MB8AC0300_CRTC_OFS__ADR_FB1] = (u32)lcd_base;
+ crtc[MB8AC0300_CRTC_OFS__SIGNAL_POL] = SIGNAL__POL;
+ crtc[MB8AC0300_CRTC_OFS__DATA_FMT] =
+ (8 << 16) | (3 << 8) | (0 << 4) | mode;
+ crtc[MB8AC0300_CRTC_OFS__PIC_BORDER_H_END_START] =
+ (HRBORDER_ST << 16) | H_ADD_TIM_S;
+ crtc[MB8AC0300_CRTC_OFS__PIC_BORDER_V_END_START] =
+ (VBBORDER_ST << 16) | V_ADD_TIM_S;
+
+ crtc0[MB8AC0300_CRTC_OFS__RAM_ADR_GAMMA] = 0;
+ for (col = 0; col < 0x01000000; col += 0x010101)
+ crtc[MB8AC0300_CRTC_OFS__RAM_DATA_GAMMA] = col;
+
+ /* crtc1 */
+
+ crtc = (void *)(GPU_BASE + MB8AC0300GPU_BLOCK_OFS_CRTC1);
+
+ crtc[MB8AC0300_CRTC_OFS__H_CTR_SIZE] = HCOUNT_SIZE1;
+ crtc[MB8AC0300_CRTC_OFS__H_ADDR_TIME_START] = H_ADD_TIM_S1;
+ crtc[MB8AC0300_CRTC_OFS__H_RIGHT_BORDER_START] = HRBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__H_BLANK_START] = HRBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__H_LEFT_BORDER_START] = HLBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__H_SYNC_START] = H_SYNC_STAT1;
+ crtc[MB8AC0300_CRTC_OFS__H_BACK_PORCH_START] = H_BACKPO_ST1;
+ crtc[MB8AC0300_CRTC_OFS__H_INTERRUPT_END_START] =
+ (H_BACKPO_ST1 << 16) | H_SYNC_STAT1;
+ crtc[MB8AC0300_CRTC_OFS__H_DMA_END_START] =
+ ((H_SYNC_STAT1 + 1) << 16) | H_SYNC_STAT1;
+ crtc[MB8AC0300_CRTC_OFS__V_COUNTER_SIZE] = VCOUNT_SIZE1;
+ crtc[MB8AC0300_CRTC_OFS__V_ADDR_TIME_START] = V_ADD_TIM_S1;
+ crtc[MB8AC0300_CRTC_OFS__V_BOTTOM_BORDER_START] = VBBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__V_BLANK_START] = VBBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__V_TOP_BORDER_START] = VTBORDER_ST1;
+ crtc[MB8AC0300_CRTC_OFS__V_SYNC_START] = V_SYNC_STAT1;
+ crtc[MB8AC0300_CRTC_OFS__V_BACK_PORCH_START] = V_BACKPO_ST1;
+ crtc[MB8AC0300_CRTC_OFS__V_INTERRUPT_END_START] =
+ (V_BACKPO_ST1 << 16) | V_SYNC_STAT1;
+ crtc[MB8AC0300_CRTC_OFS__V_INCREMENT_H_VALUE] = V_INCR_H_VA1;
+ crtc[MB8AC0300_CRTC_OFS__OUT_SIZE] = (yres << 16) | xres;
+ crtc[MB8AC0300_CRTC_OFS__DATA_SIZE] = xres * bytes_pp;
+
+ crtc[MB8AC0300_CRTC_OFS__ADR_FB0] = (u32)lcd_base;
+ crtc[MB8AC0300_CRTC_OFS__ADR_FB1] = (u32)lcd_base;
+ crtc[MB8AC0300_CRTC_OFS__SIGNAL_POL] = SIGNAL__POL1;
+ crtc[MB8AC0300_CRTC_OFS__DATA_FMT] =
+ (8 << 16) | (3 << 8) | (0 << 4) | mode;
+ crtc[MB8AC0300_CRTC_OFS__PIC_BORDER_H_END_START] =
+ (HRBORDER_ST1 << 16) | H_ADD_TIM_S1;
+ crtc[MB8AC0300_CRTC_OFS__PIC_BORDER_V_END_START] =
+ (VBBORDER_ST1 << 16) | V_ADD_TIM_S1;
+
+ crtc0[MB8AC0300_CRTC_OFS__RAM_ADR_GAMMA] = 0;
+ for (col = 0; col < 0x03000000; col += 0x010101)
+ crtc[MB8AC0300_CRTC_OFS__RAM_DATA_GAMMA] = col;
+
+ /* start both CRTC */
+
+ crtc0[MB8AC0300_CRTC_OFS__START] = 0x10101;
+ crtc[MB8AC0300_CRTC_OFS__START] = 0x10101;
+}
+
diff -urNa -x .git original/u-boot-linaro-stable/fs/fat/fat.c u-boot/fs/fat/fat.c
--- original/u-boot-linaro-stable/fs/fat/fat.c 2016-08-02 13:33:42.658023493 +0900
+++ u-boot/fs/fat/fat.c 2016-08-02 14:19:41.230727628 +0900
@@ -569,9 +569,9 @@
__u8 ret = 0;
- for (i = 0; i < sizeof(name); i++)
+ for (i = 0; i < 8; i++)
ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i];
- for (i = 0; i < sizeof(ext); i++)
+ for (i = 0; i < 3; i++)
ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i];
return ret;
diff -urNa -x .git original/u-boot-linaro-stable/fs/romfs/Makefile u-boot/fs/romfs/Makefile
--- original/u-boot-linaro-stable/fs/romfs/Makefile 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/fs/romfs/Makefile 2016-08-02 14:19:41.235727607 +0900
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libromfs.o
+
+AOBJS =
+COBJS-$(CONFIG_CMD_ROMFS) := romfs.o
+
+SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
+
+#CPPFLAGS +=
+
+all: $(LIB) $(AOBJS)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -urNa -x .git original/u-boot-linaro-stable/fs/romfs/romfs.c u-boot/fs/romfs/romfs.c
--- original/u-boot-linaro-stable/fs/romfs/romfs.c 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/fs/romfs/romfs.c 2016-08-02 14:19:41.235727607 +0900
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2013 Andy Green
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * all of these members are big-endian
+ */
+
+#include
+#include
+
+struct sb {
+ unsigned int be_magic1;
+ unsigned int be_magic2;
+ unsigned int be_size;
+ unsigned int be_checksum;
+ char name[0];
+};
+
+struct inode {
+ unsigned int be_next;
+ unsigned int be_spec;
+ unsigned int be_size;
+ unsigned int be_checksum;
+ char name[0];
+};
+
+/*
+ * these magics are already in big-endian and don't need converting
+ */
+#define BE_ROMFS_MAGIC1 0x6d6f722d
+#define BE_ROMFS_MAGIC2 0x2d736631
+
+const void *romfs;
+
+static unsigned int le(const unsigned int *be)
+{
+ const unsigned char *c = (const unsigned char *)be;
+ return (c[0] << 24) | (c[1] << 16) | (c[2] << 8) | c[3];
+}
+
+/*
+ * rule is pad strings to 16 byte boundary
+ */
+static int pad(const char *s)
+{
+ int n = 0;
+
+ while (*s++)
+ n++;
+
+ return (n + 0xf) & ~0xf;
+}
+
+static const struct inode * lookup(const void *start, const char *filepath)
+{
+ const struct sb *sb = (struct sb *)romfs;
+ const struct inode *inode = (struct inode *)
+ (romfs + sizeof(struct sb) + pad(sb->name));
+ const struct inode *level = inode;
+ const char *p, *n;
+ int m;
+ const char *target;
+
+ if (start != romfs) {
+ inode = start;
+ level = start;
+ }
+
+ while (inode != romfs) {
+
+ //printf("%s - %x\n", filepath, inode);
+
+ /* match what we can */
+ p = filepath;
+ n = inode->name;
+
+ //puts(" ");
+ //puts(n);
+ //puts("\n");
+
+ while (*p && *p != '/' && *n && *p == *n) {
+ p++;
+ n++;
+ }
+
+ /* matched everything */
+ if (!*p && !*n) {
+ m = le(&inode->be_next) & 7;
+ switch (m) {
+ case 0: /* hard link */
+ return (struct inode *)
+ (romfs + (le(&inode->be_spec) & ~0xf));
+ case 3: /* symlink */
+ target = ((void *)(inode + 1)) +
+ pad(inode->name);
+ //puts("Symlink ");
+ //puts(target);
+ //puts("\n");
+ if (*target == '/') {
+ /* reinterpret symlink path from / */
+ level = (struct inode *)
+ (romfs + sizeof(struct sb) +
+ pad(sb->name));
+ target++;
+ } /* else reinterpret from cwd */
+ inode = lookup(level, target);
+ //puts("post-recurse ");
+ //printf("%x", inode);
+ //puts(" ");
+ //puts(filepath);
+ //puts("\n");
+ continue;
+ default: /* file of some kind, or dir */
+ return inode;
+ }
+ }
+ /* matched dir */
+ if (*p == '/' && !*n) {
+
+ m = le(&inode->be_next) & 7;
+ switch (m) {
+ case 0: /* hard link */
+ return (struct inode *)
+ (romfs + (le(&inode->be_spec) & ~0xf));
+ case 3: /* symlink */
+ target = ((void *)(inode + 1)) +
+ pad(inode->name);
+ //puts("Symlink ");
+ //puts(target);
+ //puts("\n");
+ if (*target == '/') {
+ /* reinterpret symlink path from / */
+ level = (struct inode *)
+ (romfs + sizeof(struct sb) +
+ pad(sb->name));
+ target++;
+ } /* else reinterpret from cwd */
+ inode = lookup(level, target);
+ if (!inode)
+ return 0;
+ /* resume looking one level deeper */
+ inode = (struct inode *)(((void *)(inode + 1)) +
+ pad(inode->name));
+ while (*filepath != '/' && *filepath)
+ filepath++;
+ if (!*filepath)
+ return 0;
+ filepath++;
+ //puts("post-recurse ");
+ //printf("%x", inode);
+ //puts(" ");
+ //puts(filepath);
+ //puts("\n");
+ continue;
+ default: /* file of some kind, or dir */
+ /* move past the / */
+ filepath = p + 1;
+
+ /* resume looking one level deeper */
+ inode = (struct inode *)(((void *)(inode + 1)) +
+ pad(inode->name));
+ break;
+ }
+ level = inode;
+ continue;
+ }
+
+ /* not a match, try the next at this level */
+
+ if (!(le(&inode->be_next) & ~0xf))
+ /* no more at this level */
+ return 0;
+
+ inode = (struct inode *)(romfs + (le(&inode->be_next) & ~0xf));
+ }
+
+ return 0;
+}
+
+
+int
+romfs_filesystem_read(const char *filepath, void *buf, unsigned long maxsize)
+{
+ const struct inode *inode = lookup(romfs, filepath);
+ unsigned int len;
+
+ if (!inode) {
+ //puts("failed to find ");
+ //puts(filepath);
+ //puts("\n");
+ return 0;
+ }
+
+ len = le(&inode->be_size);
+ if (len > maxsize)
+ len = maxsize;
+ memcpy(buf, (const char *)inode->name + pad(inode->name), len);
+
+ return len;
+}
+
+int romfs_mount(const void *_romfs)
+{
+ const struct sb *sb = (struct sb *)_romfs;
+
+ romfs = _romfs;
+
+ return (sb->be_magic1 != BE_ROMFS_MAGIC1 ||
+ sb->be_magic2 != BE_ROMFS_MAGIC2);
+}
diff -urNa -x .git original/u-boot-linaro-stable/include/config_cmd_default.h u-boot/include/config_cmd_default.h
--- original/u-boot-linaro-stable/include/config_cmd_default.h 2016-08-02 12:12:09.103771958 +0900
+++ u-boot/include/config_cmd_default.h 2016-08-02 14:19:41.256727517 +0900
@@ -40,4 +40,8 @@
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+#define CONFIG_CMD_LOOP /* infinite loop on address range */
+#define CONFIG_CMD_IMXTRACT /* extract a part of a multi-image */
+#define CONFIG_CMD_BOOTVX /* Boot vxWorks from an ELF image */
+
#endif /* _CONFIG_CMD_DEFAULT_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/arndale5250.h u-boot/include/configs/arndale5250.h
--- original/u-boot-linaro-stable/include/configs/arndale5250.h 2016-08-02 13:33:42.658023493 +0900
+++ u-boot/include/configs/arndale5250.h 2016-08-02 14:19:41.718725526 +0900
@@ -54,6 +54,8 @@
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_BOOTZ
+
/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
#define MACH_TYPE_SMDK5250 3774
#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/mb86s70.h u-boot/include/configs/mb86s70.h
--- original/u-boot-linaro-stable/include/configs/mb86s70.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/configs/mb86s70.h 2016-08-02 14:19:41.758725355 +0900
@@ -0,0 +1,250 @@
+/*
+ * u-boot/include/configs/mb86s70.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_ARMV7 1 /* This is an ARM v7 CPU Core */
+#define CONFIG_MB86S7X
+#define CONFIG_MB86S70
+#define CONFIG_MB86S70_IOCLK (500000000) /* 500MHz */
+
+/* UARTx(PCLK) */
+#define CONFIG_UART_CLK (CONFIG_MB86S70_IOCLK / 8) /* CLK6 100MHz */
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_TIMER_CLK (CONFIG_MB86S70_IOCLK / 16) /* CLKE 50MHz */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Device Tree Support
+ */
+
+#define CONFIG_OF_LIBFDT
+
+#define BOOTM_DIRECT_START_LINUX
+
+
+/*
+ * Hardware drivers support
+ */
+
+/* Serial(support) */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_UART_CLK
+#define CONFIG_SYS_NS16550_COM1 0x31040000 /* UART 0 */
+#define CONFIG_SYS_NS16550_COM2 0x31050000 /* UART 1 */
+#define CONFIG_SYS_NS16550_COM3 0x31060000 /* UART 2 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 1
+
+/* I2C (Non support) */
+/* USB(Non support) */
+
+/* SD(support) */
+#define CONFIG_SDHCI
+#define CONFIG_F_SDH30_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MMC_SDMA
+
+#define CONFIG_EMMC_CLOCK (2000000) /* 2MHz */
+#define CONFIG_SD_CLOCK (50000000) /* 50MHz */
+
+
+/*
+ * BOOTP options(support)
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/* Ethernet PHY options */
+/* Enable these macro if gigabit is supported by hardware */
+/* Auto negotiation */
+#define CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+/* Force media */
+/*#define CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+/*
+ * Command line configuration.
+ *
+ */
+#include
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_CMD_ELF /* bootelf, bootvx */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MMC /* mmc command support */
+#define CONFIG_CMD_EXT2 /* EXT2 file system support */
+#define CONFIG_CMD_FAT /* FAT file system support */
+#define CONFIG_CMD_ROMFS /* ROM file system support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_DHCP /* dhcp support */
+
+/* f_taiki for ethernet */
+#define CONFIG_DRIVER_OGMA
+#define CONFIG_DRIVER_OGMA_BUF_START 0x88000000
+#define CONFIG_DRIVER_OGMA_BUF_END 0x88200000
+
+/* Network default configurations */
+#define CONFIG_ETHADDR 12:34:56:78:9a:bc
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.105
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* arguments for bootm command */
+//#define CONFIG_BOOTARGS "mem=2048M console=ttyS0,115200 mtdparts=physmap-flash.0:1m(u-boot)ro,2m(kernel),-(rt) root=/dev/mtdblock2 rw rootfstype=jffs2"
+
+#define CONFIG_BOOTCOMMAND "mmc dev 1; mmc rescan ; ext2load mmc 1:1 80008000 boot/Image ; ext2load mmc 1:1 81000000 boot/mb86s70eb.dtb ; bootm 80008000 - 81000000"
+#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE 0x10000000 /* size of DDR3(256MB) */
+
+/*
+ * FLASH and environment organization
+ *
+ * cf. Flash spec.
+ * Spansion S29GL128P90TFCR2
+ * S29GL-P_00_A102_j.pdf
+ */
+
+
+/*
+ * if your U-Boot will run from XCS0, need to define this
+ * currently, it kills NOR detect in U-Boot
+ */
+
+#define UBOOT_SIZE 0x00100000 /* 1MB */
+#define KERNEL_SIZE 0x00400000 /* 4MB */
+
+
+/* boot path */
+#define CONFIG_SYS_FLASH_BASE 0x48000000 /* XCS4 BootROM(32MB) */
+#define PHYS_FLASH_SIZE_1 0x02000000 /* (16+16)MB */
+#define CONFIG_BOOTDELAY 2 /* disable autoboot */
+
+#define CONFIG_SKIP_FLASH_PROBE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (128)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+//#define CONFIG_ENV_IS_IN_SCBDEV 1
+#define CONFIG_ENV_IS_IN_MMC 1 /* create enviromment data in eMMC */
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* eMMC */
+#define CONFIG_ENV_SIZE (0x40000) /* (128*2)KB */
+#define CONFIG_BOOTPARAM_ADDR (0x2E003ECC)
+#define CONFIG_BOOTPARAM_ADDR_MASK (0x00FFFFFF)
+#define CONFIG_ENV_AREA_SIZE (0x40000)
+#define CONFIG_ENV_OFFSET ((*((u32 *)CONFIG_BOOTPARAM_ADDR))&CONFIG_BOOTPARAM_ADDR_MASK)
+#define CONFIG_PROTECTION_TB_OFFSET (CONFIG_ENV_OFFSET + CONFIG_ENV_AREA_SIZE)
+#define CONFIG_ENV_SECT_SIZE (0x40000) /* (128*2)KB */
+
+/* Support JFFS2 */
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_OFFSET (UBOOT_SIZE + KERNEL_SIZE)
+#define CONFIG_JFFS2_PART_SIZE (PHYS_FLASH_SIZE_1 - UBOOT_SIZE - KERNEL_SIZE)
+
+/* Support MTD */
+#define CONFIG_MTD_DEVICE 1
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=norflash-0"
+#define MTDPARTS_DEFAULT "mtdparts=norflash-0:2m@0(uboot),14m(kernel),-(rt)"
+
+#define CONFIG_FLASH_CFI_MTD 1
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+#define CONFIG_SCB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE / 0x10)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+/* auto boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_MALLOC_LEN (0x00400000) /* 4Mbyte size of malloc() */
+#define CONFIG_SYS_TEXT_BASE 0x80008000 /* Boot from HSSPI NOR */
+#define CONFIG_SYS_INIT_SP_ADDR 0x80004000 /* stack of init proccess */
+
+#define CONFIG_DISPLAY_CPUINFO 1 /* Display CPU information */
+#define CONFIG_DISPLAY_BOARDINFO 1 /* Display BOARD information */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+//#define NO_FIX_MEMORY_NODE 1
+
+/* MHU */
+#define CONFIG_MB86S7X_MHU 1
+
+/* undef the commands we don't use */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* needs extra care*/
+#undef CONFIG_CMD_LOOP
+#undef CONFIG_CMD_IMXTRACT
+#undef CONFIG_CMD_BOOTVX
+
+#endif /* __CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/mb86s71.h u-boot/include/configs/mb86s71.h
--- original/u-boot-linaro-stable/include/configs/mb86s71.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/configs/mb86s71.h 2016-08-02 14:19:41.759725351 +0900
@@ -0,0 +1,257 @@
+/*
+ * u-boot/include/configs/mb86s71.h
+ *
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7 1 /* This is an ARM v7 CPU Core */
+#define CONFIG_MB86S7X
+#define CONFIG_MB86S71
+#define CONFIG_MB86S71_IOCLK (500000000) /* 500MHz */
+
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_MB86S7X_MHU
+
+/* UARTx(PCLK) */
+#define CONFIG_UART_CLK (7813000)
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_TIMER_CLK (CONFIG_MB86S71_IOCLK / 16) /* CLKE 50MHz */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+#define CONFIG_EMMC_CLOCK (2000000) /* 2MHz */
+#define CONFIG_SD_CLOCK (50000000) /* 50MHz */
+#define CONFIG_EMMC_MAX_CLOCK (200000000) /* 200MHz */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Device Tree Support
+ */
+
+#define CONFIG_OF_LIBFDT
+
+#define BOOTM_DIRECT_START_LINUX
+
+
+/*
+ * Hardware drivers support
+ */
+
+/* Serial(support) */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK CONFIG_UART_CLK
+#define CONFIG_PL01x_PORTS {(void *)(0x31040000), (void *)(0x31050000), (void *)(0x31060000)}
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 0
+
+/* I2C (Not support) */
+/* USB (Not support) */
+
+/* SD(support) */
+#define CONFIG_SDHCI
+#define CONFIG_F_SDH30_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_ADMA
+#define CONFIG_SDHCI_AUTO_CMD12
+#define CONFIG_SDHCI_AUTO_CMD23
+
+/*
+ * BOOTP options(support)
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/* Ethernet PHY options */
+/* Enable these macro if gigabit is supported by hardware */
+/* Auto negotiation */
+#define CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+/* Force media */
+/*#define CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+/*
+ * Command line configuration.
+ *
+ */
+#include
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_CMD_ELF /* bootelf, bootvx */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MMC /* mmc command support */
+#define CONFIG_CMD_EXT2 /* EXT2 file system support */
+#define CONFIG_CMD_FAT /* FAT file system support */
+#define CONFIG_CMD_ROMFS /* ROM file system support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_DHCP /* dhcp support */
+
+/* f_taiki for ethernet */
+#define CONFIG_DRIVER_OGMA
+#define CONFIG_DRIVER_OGMA_BUF_START 0x88000000
+#define CONFIG_DRIVER_OGMA_BUF_END 0x88200000
+
+/* Network default configurations */
+#define CONFIG_ETHADDR 12:34:56:78:9a:bc
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.105
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* arguments for bootm command */
+//#define CONFIG_BOOTARGS "mem=2048M console=ttyS0,115200 mtdparts=physmap-flash.0:1m(u-boot)ro,2m(kernel),-(rt) root=/dev/mtdblock2 rw rootfstype=jffs2"
+
+#define CONFIG_BOOTCOMMAND "mmc dev 1; mmc rescan ; ext2load mmc 1:1 80008000 boot/Image ; ext2load mmc 1:1 81000000 boot/mb86s71eb.dtb ; bootm 80008000 - 81000000"
+//#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyS0,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyAMA0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 bank of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE 0x10000000 /* size of DDR3(256MB) */
+
+/*
+ * FLASH and environment organization
+ *
+ * cf. Flash spec.
+ * Spansion S29GL128P90TFCR2
+ * S29GL-P_00_A102_j.pdf
+ */
+
+
+/*
+ * if your U-Boot will run from XCS0, need to define this
+ * currently, it kills NOR detect in U-Boot
+ */
+
+#define UBOOT_SIZE 0x00100000 /* 1MB */
+#define KERNEL_SIZE 0x00400000 /* 4MB */
+
+
+/* boot path */
+#define CONFIG_SYS_FLASH_BASE 0x48000000 /* XCS4 BootROM(32MB) */
+#define PHYS_FLASH_SIZE_1 0x01000000 /* 16MB in memory map */
+#define CONFIG_BOOTDELAY 2 /* disable autoboot */
+
+//#define CONFIG_SKIP_FLASH_PROBE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (256 * 4)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SIZE (48 * 512) /* 24KB */
+#define CONFIG_BOOTPARAM_ADDR (0x2E003ECC)
+#define CONFIG_BOOTPARAM_ADDR_MASK (0x00FFFFFF)
+#define CONFIG_ENV_AREA_SIZE (0x40000)
+#define CONFIG_ENV_OFFSET ((*((u32 *)CONFIG_BOOTPARAM_ADDR))&CONFIG_BOOTPARAM_ADDR_MASK)
+#define CONFIG_PROTECTION_TB_OFFSET (CONFIG_ENV_OFFSET + CONFIG_ENV_AREA_SIZE)
+#define CONFIG_ENV_SECT_SIZE (0x10000) /* (128*2)KB */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CMD_FOR_SF
+
+/* Support JFFS2 */
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_OFFSET (UBOOT_SIZE + KERNEL_SIZE)
+#define CONFIG_JFFS2_PART_SIZE (PHYS_FLASH_SIZE_1 - UBOOT_SIZE - KERNEL_SIZE)
+
+/* Support MTD */
+#define CONFIG_MTD_DEVICE 1
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=norflash-0"
+#define MTDPARTS_DEFAULT "mtdparts=norflash-0:2m@0(uboot),14m(kernel),-(rt)"
+
+//#define CONFIG_FLASH_CFI_MTD 1
+/*
+ * CFI FLASH driver setup
+ */
+//#define CONFIG_SYS_FLASH_CFI 1
+//#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+//#define CONFIG_SCB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE / 0x10)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+/* auto boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_MALLOC_LEN (0x00400000) /* 4Mbyte size of malloc() */
+#define CONFIG_SYS_TEXT_BASE 0x80008000 /* Boot from HSSPI NOR */
+#define CONFIG_SYS_INIT_SP_ADDR 0x80004000 /* stack of init proccess */
+
+#define CONFIG_DISPLAY_CPUINFO 1 /* Display CPU information */
+#define CONFIG_DISPLAY_BOARDINFO 1 /* Display BOARD information */
+#define CONFIG_OF_BOARD_SETUP 1 /* config FDT for the board */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+//#define NO_FIX_MEMORY_NODE 1
+
+#define CONFIG_MB86S7X_HS_SPI 1
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_QUIRK_N25Q512A 1
+
+#define CONFIG_FLASH_CHIP_SELECT
+/* undef the commands we don't use */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* needs extra care*/
+#undef CONFIG_CMD_LOOP
+#undef CONFIG_CMD_IMXTRACT
+#undef CONFIG_CMD_BOOTVX
+
+#endif /* __CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/mb86s72.h u-boot/include/configs/mb86s72.h
--- original/u-boot-linaro-stable/include/configs/mb86s72.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/configs/mb86s72.h 2016-08-02 14:19:41.759725351 +0900
@@ -0,0 +1,262 @@
+/*
+ * u-boot/include/configs/mb86s72.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7 1 /* This is an ARM v7 CPU Core */
+#define CONFIG_MB86S7X
+#define CONFIG_MB86S72
+#define CONFIG_MB86S72_IOCLK (500000000) /* 500MHz */
+
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_MB86S7X_MHU
+
+/* UARTx(PCLK) */
+#define CONFIG_UART_CLK (7813000)
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_TIMER_CLK (CONFIG_MB86S72_IOCLK / 16) /* CLKE 50MHz */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+#define CONFIG_EMMC_CLOCK (2000000) /* 2MHz */
+#define CONFIG_SD_CLOCK (50000000) /* 50MHz */
+#define CONFIG_EMMC_MAX_CLOCK (200000000) /* 200MHz */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Device Tree Support
+ */
+
+#define CONFIG_OF_LIBFDT
+
+#define BOOTM_DIRECT_START_LINUX
+
+
+/*
+ * Hardware drivers support
+ */
+
+/* Serial(support) */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK CONFIG_UART_CLK
+#define CONFIG_PL01x_PORTS {(void *)(0x31040000), (void *)(0x31050000), (void *)(0x31060000)}
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 0
+
+/* I2C (Non support) */
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_F_USB20HO 1
+#define CONFIG_F_USB20HO_POWERDOMAIN 26
+
+/* SD(support) */
+#define CONFIG_SDHCI
+#define CONFIG_F_SDH30_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_ADMA
+#define CONFIG_SDHCI_AUTO_CMD12
+#define CONFIG_SDHCI_AUTO_CMD23
+
+/*
+ * BOOTP options(support)
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/* Ethernet PHY options */
+/* Enable these macro if gigabit is supported by hardware */
+/* Auto negotiation */
+#define CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+/* Force media */
+/*#define CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+/*
+ * Command line configuration.
+ *
+ */
+#include
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_CMD_ELF /* bootelf, bootvx */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MMC /* mmc command support */
+#define CONFIG_CMD_EXT2 /* EXT2 file system support */
+#define CONFIG_CMD_FAT /* FAT file system support */
+#define CONFIG_CMD_ROMFS /* ROM file system support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_DHCP /* dhcp support */
+
+/* f_taiki for ethernet */
+#define CONFIG_DRIVER_OGMA
+#define CONFIG_DRIVER_OGMA_BUF_START 0x88000000
+#define CONFIG_DRIVER_OGMA_BUF_END 0x88200000
+
+/* Network default configurations */
+#define CONFIG_ETHADDR 12:34:56:78:9a:bc
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.105
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* arguments for bootm command */
+//#define CONFIG_BOOTARGS "mem=2048M console=ttyS0,115200 mtdparts=physmap-flash.0:1m(u-boot)ro,2m(kernel),-(rt) root=/dev/mtdblock2 rw rootfstype=jffs2"
+
+#define CONFIG_BOOTCOMMAND "mmc dev 1; mmc rescan ; ext2load mmc 1:1 80008000 boot/Image ; ext2load mmc 1:1 81000000 boot/mb86s72eb.dtb ; bootm 80008000 - 81000000"
+//#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyS0,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyAMA0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 bank of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE 0x10000000 /* size of DDR3(256MB) */
+
+/*
+ * FLASH and environment organization
+ *
+ * cf. Flash spec.
+ * Spansion S29GL128P90TFCR2
+ * S29GL-P_00_A102_j.pdf
+ */
+
+
+/*
+ * if your U-Boot will run from XCS0, need to define this
+ * currently, it kills NOR detect in U-Boot
+ */
+
+#define UBOOT_SIZE 0x00100000 /* 1MB */
+#define KERNEL_SIZE 0x00400000 /* 4MB */
+
+
+/* boot path */
+#define CONFIG_SYS_FLASH_BASE 0x48000000 /* XCS4 BootROM(32MB) */
+#define PHYS_FLASH_SIZE_1 0x01000000 /* 16MB in memory map */
+#define CONFIG_BOOTDELAY 2 /* disable autoboot */
+
+//#define CONFIG_SKIP_FLASH_PROBE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (256 * 4)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SIZE (48 * 512) /* 24KB */
+#define CONFIG_BOOTPARAM_ADDR (0x2E003ECC)
+#define CONFIG_BOOTPARAM_ADDR_MASK (0x00FFFFFF)
+#define CONFIG_ENV_AREA_SIZE (0x40000)
+#define CONFIG_ENV_OFFSET ((*((u32 *)CONFIG_BOOTPARAM_ADDR))&CONFIG_BOOTPARAM_ADDR_MASK)
+#define CONFIG_PROTECTION_TB_OFFSET (CONFIG_ENV_OFFSET + CONFIG_ENV_AREA_SIZE)
+#define CONFIG_ENV_SECT_SIZE (0x10000) /* (128*2)KB */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CMD_FOR_SF
+
+/* Support JFFS2 */
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_OFFSET (UBOOT_SIZE + KERNEL_SIZE)
+#define CONFIG_JFFS2_PART_SIZE (PHYS_FLASH_SIZE_1 - UBOOT_SIZE - KERNEL_SIZE)
+
+/* Support MTD */
+#define CONFIG_MTD_DEVICE 1
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=norflash-0"
+#define MTDPARTS_DEFAULT "mtdparts=norflash-0:2m@0(uboot),14m(kernel),-(rt)"
+
+//#define CONFIG_FLASH_CFI_MTD 1
+/*
+ * CFI FLASH driver setup
+ */
+//#define CONFIG_SYS_FLASH_CFI 1
+//#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+//#define CONFIG_SCB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE / 0x10)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+/* auto boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_MALLOC_LEN (0x00400000) /* 4Mbyte size of malloc() */
+#define CONFIG_SYS_TEXT_BASE 0x80008000 /* Boot from HSSPI NOR */
+#define CONFIG_SYS_INIT_SP_ADDR 0x80004000 /* stack of init proccess */
+
+#define CONFIG_DISPLAY_CPUINFO 1 /* Display CPU information */
+#define CONFIG_DISPLAY_BOARDINFO 1 /* Display BOARD information */
+#define CONFIG_OF_BOARD_SETUP 1 /* config FDT for the board */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+//#define NO_FIX_MEMORY_NODE 1
+
+#define CONFIG_MB86S7X_HS_SPI 1
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_QUIRK_N25Q512A 1
+
+#define CONFIG_FLASH_CHIP_SELECT
+/* undef the commands we don't use */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* needs extra care*/
+#undef CONFIG_CMD_LOOP
+#undef CONFIG_CMD_IMXTRACT
+#undef CONFIG_CMD_BOOTVX
+
+#endif /* __CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/mb86s73.h u-boot/include/configs/mb86s73.h
--- original/u-boot-linaro-stable/include/configs/mb86s73.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/configs/mb86s73.h 2016-08-02 14:19:41.759725351 +0900
@@ -0,0 +1,265 @@
+/*
+ * u-boot/include/configs/mb86s73.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7 1 /* This is an ARM v7 CPU Core */
+#define CONFIG_MB86S7X
+#define CONFIG_MB86S73
+#define CONFIG_MB86S73_IOCLK (500000000) /* 500MHz */
+
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_MB86S7X_MHU
+
+/* UARTx(PCLK) */
+#define CONFIG_UART_CLK (CONFIG_MB86S73_IOCLK / 8) /* CLK6 100MHz */
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_TIMER_CLK (CONFIG_MB86S73_IOCLK / 16) /* CLKE 50MHz */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+#define CONFIG_EMMC_CLOCK (2000000) /* 2MHz */
+#define CONFIG_SD_CLOCK (50000000) /* 50MHz */
+#define CONFIG_EMMC_MAX_CLOCK (125000000) /* 125MHz */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Device Tree Support
+ */
+
+#define CONFIG_OF_LIBFDT
+
+#define BOOTM_DIRECT_START_LINUX
+
+
+/*
+ * Hardware drivers support
+ */
+
+/* Serial(support) */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_UART_CLK
+#define CONFIG_SYS_NS16550_COM1 0x31040000 /* UART 0 */
+#define CONFIG_SYS_NS16550_COM2 0x31050000 /* UART 1 */
+#define CONFIG_SYS_NS16550_COM3 0x31060000 /* UART 2 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 1
+
+/* I2C (Non support) */
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_F_USB20HO 1
+#define CONFIG_F_USB20HO_POWERDOMAIN 9
+
+/* SD(support) */
+#define CONFIG_SDHCI
+#define CONFIG_F_SDH30_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_ADMA
+#define CONFIG_SDHCI_AUTO_CMD12
+#define CONFIG_SDHCI_AUTO_CMD23
+
+/*
+ * BOOTP options(support)
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/* Ethernet PHY options */
+/* Enable these macro if gigabit is supported by hardware */
+/* Auto negotiation */
+#define CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+/* Force media */
+/*#define CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+/*
+ * Command line configuration.
+ *
+ */
+#include
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_CMD_ELF /* bootelf, bootvx */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MMC /* mmc command support */
+#define CONFIG_CMD_EXT2 /* EXT2 file system support */
+#define CONFIG_CMD_FAT /* FAT file system support */
+#define CONFIG_CMD_ROMFS /* ROM file system support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_DHCP /* dhcp support */
+
+/* f_taiki for ethernet */
+#define CONFIG_DRIVER_OGMA
+#define CONFIG_DRIVER_OGMA_BUF_START 0x88000000
+#define CONFIG_DRIVER_OGMA_BUF_END 0x88200000
+
+/* Network default configurations */
+#define CONFIG_ETHADDR 12:34:56:78:9a:bc
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.105
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* arguments for bootm command */
+//#define CONFIG_BOOTARGS "mem=2048M console=ttyS0,115200 mtdparts=physmap-flash.0:1m(u-boot)ro,2m(kernel),-(rt) root=/dev/mtdblock2 rw rootfstype=jffs2"
+
+#define CONFIG_BOOTCOMMAND "mmc dev 1; mmc rescan ; ext2load mmc 1:1 80008000 boot/Image ; ext2load mmc 1:1 81000000 boot/mb86s73eb.dtb ; bootm 80008000 - 81000000"
+//#define CONFIG_BOOTARGS "shm_offset=2048 loglevel=4 console=ttyS0,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_BOOTARGS " shm_offset=2048 loglevel=4 console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 bank of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE 0x10000000 /* size of DDR3(256MB) */
+
+/*
+ * FLASH and environment organization
+ *
+ * cf. Flash spec.
+ * Spansion S29GL128P90TFCR2
+ * S29GL-P_00_A102_j.pdf
+ */
+
+
+/*
+ * if your U-Boot will run from XCS0, need to define this
+ * currently, it kills NOR detect in U-Boot
+ */
+
+#define UBOOT_SIZE 0x00100000 /* 1MB */
+#define KERNEL_SIZE 0x00400000 /* 4MB */
+
+
+/* boot path */
+#define CONFIG_SYS_FLASH_BASE 0x48000000 /* XCS4 BootROM(32MB) */
+#define PHYS_FLASH_SIZE_1 0x01000000 /* 16MB in memory map */
+#define CONFIG_BOOTDELAY 2 /* disable autoboot */
+
+//#define CONFIG_SKIP_FLASH_PROBE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (256 * 4)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SIZE (48 * 512) /* 24KB */
+#define CONFIG_BOOTPARAM_ADDR (0x2E003ECC)
+#define CONFIG_BOOTPARAM_ADDR_MASK (0x00FFFFFF)
+#define CONFIG_ENV_AREA_SIZE (0x40000)
+#define CONFIG_ENV_OFFSET ((*((u32 *)CONFIG_BOOTPARAM_ADDR))&CONFIG_BOOTPARAM_ADDR_MASK)
+#define CONFIG_PROTECTION_TB_OFFSET (CONFIG_ENV_OFFSET + CONFIG_ENV_AREA_SIZE)
+#define CONFIG_ENV_SECT_SIZE (0x10000) /* (128*2)KB */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CMD_FOR_SF
+
+/* Support JFFS2 */
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_OFFSET (UBOOT_SIZE + KERNEL_SIZE)
+#define CONFIG_JFFS2_PART_SIZE (PHYS_FLASH_SIZE_1 - UBOOT_SIZE - KERNEL_SIZE)
+
+/* Support MTD */
+#define CONFIG_MTD_DEVICE 1
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=norflash-0"
+#define MTDPARTS_DEFAULT "mtdparts=norflash-0:2m@0(uboot),14m(kernel),-(rt)"
+
+//#define CONFIG_FLASH_CFI_MTD 1
+/*
+ * CFI FLASH driver setup
+ */
+//#define CONFIG_SYS_FLASH_CFI 1
+//#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+//#define CONFIG_SCB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE / 0x10)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+/* auto boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_MALLOC_LEN (0x00400000) /* 4Mbyte size of malloc() */
+#define CONFIG_SYS_TEXT_BASE 0x80008000 /* Boot from HSSPI NOR */
+#define CONFIG_SYS_INIT_SP_ADDR 0x80004000 /* stack of init proccess */
+
+#define CONFIG_DISPLAY_CPUINFO 1 /* Display CPU information */
+#define CONFIG_DISPLAY_BOARDINFO 1 /* Display BOARD information */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+//#define NO_FIX_MEMORY_NODE 1
+
+#define CONFIG_MB86S7X_HS_SPI 1
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_QUIRK_N25Q512A 1
+
+#define CONFIG_FLASH_CHIP_SELECT
+/* undef the commands we don't use */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* needs extra care*/
+#undef CONFIG_CMD_LOOP
+#undef CONFIG_CMD_IMXTRACT
+#undef CONFIG_CMD_BOOTVX
+
+#endif /* __CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/configs/mb8ac0300eb.h u-boot/include/configs/mb8ac0300eb.h
--- original/u-boot-linaro-stable/include/configs/mb8ac0300eb.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/configs/mb8ac0300eb.h 2016-08-02 14:19:41.759725351 +0900
@@ -0,0 +1,242 @@
+/*
+ * u-boot/include/configs/mb8ac0300eb.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7 1 /* This is an ARM cortexA9 Core */
+#define CONFIG_MB8AC0300
+#define CONFIG_MB8AC0300_IOCLK (662500000) /* 662.5MHz */
+
+/* UARTx(PCLK) */
+#define CONFIG_UART_CLK (CONFIG_MB8AC0300_IOCLK / 8) /* CLK6 82.8125MHz */
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_TIMER_CLK (CONFIG_MB8AC0300_IOCLK / 16) /* CLKE 41.40625MHz */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0xfff6d000 /* Timer of ARM-SP804 */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Device Tree Support
+ */
+
+#define CONFIG_OF_LIBFDT
+
+
+
+/*
+ * Hardware drivers support
+ */
+
+/* Serial(support) */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_UART_CLK
+#define CONFIG_SYS_NS16550_COM1 0xfff6b000 /* UART 0 */
+#define CONFIG_SYS_NS16550_COM2 0xfff6c000 /* UART 1 */
+
+#define CONFIG_CONS_INDEX 1
+
+/* I2C (Non support) */
+/* USB(Non support) */
+
+/* SD(support) */
+#define CONFIG_SDHCI
+#define CONFIG_F_SDH30_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MMC_SDMA
+
+/*
+ * Ethernet(support)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_FGMAC4 1
+#define CONFIG_FGMAC4_SYS_CLK 125000000 /* 125MHZ */
+#define CONFIG_FGMAC4_BUF_SIZE 0x00100000 /* 1MB */
+
+/*
+ * BOOTP options(support)
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/* Ethernet PHY options */
+/* Enable these macro if gigabit is supported by hardware */
+/* Auto negotiation */
+#define CONFIG_PHY_SUPPORT_GIGA_AUTONEG
+/* Force media */
+/*#define CONFIG_PHY_SUPPORT_GIGA_FORCE */
+
+/*
+ * Command line configuration.
+ *
+ */
+#include
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_CMD_ELF /* bootelf, bootvx */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MMC /* mmc command support */
+#define CONFIG_CMD_EXT2 /* EXT2 file system support */
+#define CONFIG_CMD_FAT /* FAT file system support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_DHCP /* dhcp support */
+
+/* Network default configurations */
+#define CONFIG_ETHADDR 12:34:56:78:9a:bc
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.105
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* arguments for bootm command */
+//#define CONFIG_BOOTARGS "mem=2048M console=ttyS0,115200 mtdparts=physmap-flash.0:1m(u-boot)ro,2m(kernel),-(rt) root=/dev/mtdblock2 rw rootfstype=jffs2"
+
+#define CONFIG_BOOTCOMMAND "mmc rescan ; ext2load mmc 0:1 40000000 uImage ; ext2load mmc 0:1 41000000 mb8ac0300eb.dtb; bootm 40000000 - 41000000"
+#define CONFIG_BOOTARGS "mem=2048M loglevel=8 earlycon=ttyS0,115200 earlyprintk=0 console=ttyS0,115200 console=tty0 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x40000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE 0x80000000 /* size of DDR3(2GB) */
+
+/*
+ * FLASH and environment organization
+ *
+ * cf. Flash spec.
+ * Spansion S29GL128P90TFCR2
+ * S29GL-P_00_A102_j.pdf
+ */
+
+#define CONFIG_VIDEO_MB8AC0300
+
+/*
+ * if your U-Boot will run from XCS0, need to define this
+ * currently, it kills NOR detect in U-Boot
+ */
+
+#define CONFIG_MB8AC0300_XCS0_MODE
+
+
+#define UBOOT_SIZE 0x00100000 /* 1MB */
+#define KERNEL_SIZE 0x00200000 /* 2MB */
+
+
+#ifndef CONFIG_MB8AC0300_XCS0_MODE
+
+/* normal, XCS4 boot path */
+
+#define CONFIG_SYS_FLASH_BASE 0x10000000 /* XCS4 BootROM(32MB) */
+#define PHYS_FLASH_SIZE_1 0x02000000 /* (16+16)MB */
+#define CONFIG_BOOTDELAY -1 /* disable autoboot */
+
+#else
+
+/* XCS0 boot path */
+
+#define CONFIG_SYS_FLASH_BASE 0x11000000 /* XCS0 BootROM(16MB) */
+#define PHYS_FLASH_SIZE_1 0x01000000 /* 16MB */
+#define CONFIG_BOOTDELAY 0 /* enable autoboot */
+
+#endif /* CONFIG_MB8AC0300_XCS0_MODE */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (128)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH 1 /* create enviromment data in Flash ROM */
+#define CONFIG_ENV_SIZE (0x40000) /* (128*2)KB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE \
+ + UBOOT_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SECT_SIZE (0x40000) /* (128*2)KB */
+
+/* Support JFFS2 */
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_OFFSET (UBOOT_SIZE + KERNEL_SIZE)
+#define CONFIG_JFFS2_PART_SIZE (PHYS_FLASH_SIZE_1 - UBOOT_SIZE - KERNEL_SIZE)
+
+/* Support MTD */
+#define CONFIG_MTD_DEVICE 1
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=norflash-0"
+#define MTDPARTS_DEFAULT "mtdparts=norflash-0:1m@0(uboot),2m(kernel),-(rt)"
+
+#define CONFIG_FLASH_CFI_MTD 1
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+/* auto boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_MALLOC_LEN (0x00400000) /* 4Mbyte size of malloc() */
+#define CONFIG_SYS_TEXT_BASE 0x00000000 /* Boot from NOR */
+#define CONFIG_SYS_INIT_SP_ADDR 0x43000000 /* stack of init proccess */
+
+#define CONFIG_SYS_L2_PL310 1
+#define CONFIG_SYS_PL310_BASE 0xf8102000
+
+#define CONFIG_USE_ARCH_MEMCPY 1
+
+#define CONFIG_DISPLAY_CPUINFO 1 /* Display CPU information */
+#define CONFIG_DISPLAY_BOARDINFO 1 /* Display BOARD information */
+#define CONFIG_SILENT_CONSOLE 1
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/flash.h u-boot/include/flash.h
--- original/u-boot-linaro-stable/include/flash.h 2016-08-02 12:12:09.169771724 +0900
+++ u-boot/include/flash.h 2016-08-02 14:19:41.824725073 +0900
@@ -129,6 +129,11 @@
extern flash_info_t *flash_get_info(ulong base);
#endif
+#if defined(CONFIG_FLASH_CHIP_SELECT)
+extern int flash_chip_select(int cs);
+extern int get_chip_select(void);
+#endif
+
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
diff -urNa -x .git original/u-boot-linaro-stable/include/mhu.h u-boot/include/mhu.h
--- original/u-boot-linaro-stable/include/mhu.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/mhu.h 2016-08-02 14:19:41.875724853 +0900
@@ -0,0 +1,34 @@
+#ifdef MB86S7X_SHM_FROM_SCB
+
+#define SHM_OFFSET 0x800
+
+#define rsp_from_scb ((void *)MB86S7X_SHM_FROM_SCB + SHM_OFFSET)
+#define cmd_to_scb ((void *)(MB86S7X_SHM_FROM_SCB + SHM_OFFSET + 0x100))
+#define cmd_from_scb ((void *)(MB86S7X_SHM_FROM_SCB + SHM_OFFSET + 0x200))
+#define rsp_to_scb ((void *)(MB86S7X_SHM_FROM_SCB + SHM_OFFSET + 0x300))
+
+#define INTR_STAT_OFS 0
+#define INTR_SET_OFS 8
+#define INTR_CLR_OFS 0x10
+
+#define MHU_SCFG 0x400
+
+#define MB86S7X_SYS_FLASH_SIZE_MASK 0x00000003
+#define MB86S7X_SYS_FLASH_SIZE_8MB 0x00000001
+#define MB86S7X_SYS_FLASH_SIZE_2MB 0x00000002
+#define MB86S7X_SYS_FLASH_SIZE_4MB 0x00000003
+
+extern int mhu_send(u32 cmd);
+extern int mhu_send_norep(u32 cmd);
+
+extern u32 get_scb_version(void);
+extern u32 get_sys_flash_size(void);
+extern int set_power_state(u32 pd_index, u32 state);
+extern int get_power_state(u32 pd_index);
+extern int set_clk_state(u32 cntrlr, u32 domain, u32 port, u32 en);
+extern int get_memory_layout(void);
+extern int mhu_check_pcie_capability(void);
+extern int mhu_check_video_out_capability(void);
+
+#endif
+
diff -urNa -x .git original/u-boot-linaro-stable/include/mmc.h u-boot/include/mmc.h
--- original/u-boot-linaro-stable/include/mmc.h 2016-08-02 12:12:09.177771695 +0900
+++ u-boot/include/mmc.h 2016-08-02 14:19:41.875724853 +0900
@@ -47,6 +47,10 @@
#define MMC_MODE_8BIT 0x200
#define MMC_MODE_SPI 0x400
#define MMC_MODE_HC 0x800
+#define MMC_MODE_HS200 0x1000
+#define MMC_MODE_BUS_WIDTH_TEST 0x2000
+
+#define MMC_TIMING_MMC_HS200 8
#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
#define MMC_MODE_WIDTH_BITS_SHIFT 8
@@ -75,9 +79,13 @@
#define MMC_CMD_SEND_CID 10
#define MMC_CMD_STOP_TRANSMISSION 12
#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_BUS_TEST_R 14 /* adtc R1 */
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_BUS_TEST_W 19 /* adtc R1 */
+#define MMC_CMD_SEND_TUNING_BLOCK 19 /* adtc R1 */
+#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_ERASE_GROUP_START 35
@@ -101,9 +109,6 @@
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
-#define MMC_HS_TIMING 0x00000100
-#define MMC_HS_52MHZ 0x2
-
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
@@ -136,6 +141,9 @@
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
+#define MMC_SELECT_VDD_180 0x0008
+#define MMC_SELECT_VDD_330 0x0000
+
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
addressed by index which are
@@ -148,6 +156,9 @@
#define SD_SWITCH_CHECK 0
#define SD_SWITCH_SWITCH 1
+#define CSD_TAAC(mmc) ((mmc->csd[0] >> 16) & 0xff)
+#define CSD_NSAC(mmc) ((mmc->csd[0] >> 8) & 0xff)
+
/*
* EXT_CSD fields
*/
@@ -172,6 +183,14 @@
#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V (1 << 4)
+#define EXT_CSD_CARD_TYPE_HS200_1_2V (1 << 5)
+#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V \
+ | EXT_CSD_CARD_TYPE_HS200_1_2V)
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
@@ -255,18 +274,31 @@
uint write_bl_len;
uint erase_grp_size;
u64 capacity;
+ uint timing;
+ uint taac_ns;
+ uint nsac_clock;
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*getcd)(struct mmc *mmc);
+#ifdef CONFIG_F_SDH30_SDHCI
+ void (*get_ro)(struct mmc *mmc);
+ unsigned int state;
+ unsigned int tm_clock;
+#define MMC_STATE_READONLY (1<<0) /* card is read-only */
+#endif
+ int (*set_signal_voltage)(struct mmc *mmc, int voltage);
+ int (*execute_tuning)(struct mmc *mmc, u32 opcode);
+ int (*reset) (struct mmc *mmc);
uint b_max;
};
int mmc_register(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
+int mmc_reset(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
diff -urNa -x .git original/u-boot-linaro-stable/include/netdev.h u-boot/include/netdev.h
--- original/u-boot-linaro-stable/include/netdev.h 2016-08-02 12:12:09.180771684 +0900
+++ u-boot/include/netdev.h 2016-08-02 14:19:41.879724836 +0900
@@ -97,6 +97,8 @@
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
+int fgmac4_initialize(bd_t *bis);
+int ogma_initialize(bd_t *bis);
int armada100_fec_register(unsigned long base_addr);
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr);
diff -urNa -x .git original/u-boot-linaro-stable/include/romfs.h u-boot/include/romfs.h
--- original/u-boot-linaro-stable/include/romfs.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/romfs.h 2016-08-02 14:19:42.016724240 +0900
@@ -0,0 +1,25 @@
+/*
+ * u-boot/include/romfs.h
+ *
+ * Copyright (C) 2011-2012 FUJITSU SEMICONDUCTOR LIMITED
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _ROMFS_H_
+#define _ROMFS_H_
+
+int romfs_filesystem_read(
+const char *filepath, void *buf, unsigned long maxsize);
+extern int romfs_mount(const void *_romfs);
+#endif
diff -urNa -x .git original/u-boot-linaro-stable/include/scb_mhu_api.h u-boot/include/scb_mhu_api.h
--- original/u-boot-linaro-stable/include/scb_mhu_api.h 1970-01-01 09:00:00.000000000 +0900
+++ u-boot/include/scb_mhu_api.h 2016-08-02 14:19:42.041724134 +0900
@@ -0,0 +1,198 @@
+#ifndef __SCB_MHU_API_H
+#define __SCB_MHU_API_H
+
+#define CMD_ID_SHIFT 0
+#define CMD_ID_MASK 0xff
+#define CMD_TOKEN_ID_SHIFT 8
+#define CMD_TOKEN_ID_MASK 0xff
+#define CMD_DATA_SIZE_SHIFT 16
+#define CMD_DATA_SIZE_MASK 0x1ff
+#define PACK_SCPI_CMD(cmd_id, token, tx_sz) \
+ ((((cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
+ (((token) & CMD_TOKEN_ID_MASK) << CMD_TOKEN_ID_SHIFT) | \
+ (((tx_sz) & CMD_DATA_SIZE_MASK) << CMD_DATA_SIZE_SHIFT))
+
+#define UBOOT_ID 0xFF
+#define CPU_RESET 0x2
+#define CPU_SHUTDOWN 0x0
+#define AP_REQ 0x1 // channel 0x1: Request from AP to SCP non-secure high priority
+
+enum {
+ /* SCPI-commands */
+ CMD_SET_CSS_POWER_STATE = 0x03,
+ CMD_GET_CSS_POWER_STATE = 0x04,
+ CMD_SET_SYSTEM_POWER_STATE = 0x05,
+ CMD_SET_CLOCK_VALUE = 0x0f,
+ CMD_GET_CLOCK_VALUE = 0x10,
+ CMD_SET_POWER_SUPPLY = 0x13,
+ CMD_GET_POWER_SUPPLY = 0x14,
+ CMD_GET_SCB_CAPABILITY = 0x80,
+ CMD_GET_MEMORY_LAYOUT = 0x83,
+ CMD_GET_RESUME_ENTRY_POINT = 0x87,
+ /* Do NOT add new commands below this line */
+ NUM_CMDS,
+};
+
+/*
+ * SCPI command header
+ */
+struct scpi_cmd_header {
+ union {
+ u32 cmd;
+ struct {
+ u32 id :8;
+ u32 sender_id :8;
+ u32 payload_size :9;
+ u32 reserved :7;
+ } cmd_e;
+ };
+ u32 status;
+} __attribute__ ((packed));
+
+/*
+ * SCPI Set Clock Value : cmd_id 0x0f
+ */
+struct periclk_control {
+ u32 id;
+ u32 frequency;
+} __packed;
+
+struct cmd_periclk_control {
+ struct scpi_cmd_header header;
+ struct periclk_control payload;
+} __packed;
+
+/**
+ * SCPI Get SCB Capability : cmd_id 0x80
+ */
+struct scb_version {
+ u32 version;
+ u32 config_version;
+#define S73_SCB_CAPABILITY0_STR_ENABLE (1 << 0)
+#define S73_SCB_CAPABILITY0_HSSPI_ACCESS (1 << 1)
+#define S7X_SCB_CAPABILITY0_SECURE_AP (1 << 2)
+#define S7X_SCB_CAPABILITY0_PCIE (1 << 3)
+#define S7X_SCB_CAPABILITY0_VIDEO_OUT (1 << 6)
+ u32 capabilities[2];
+} __packed;
+
+struct cmd_scb_version {
+ struct scpi_cmd_header header;
+ struct scb_version payload;
+} __packed;
+
+/*
+ * SCPI Set taiki :cmd_id 0x81
+ */
+struct taiki {
+ u32 payload_data[64];
+} __packed;
+
+struct cmd_taiki {
+ struct scpi_cmd_header header;
+ struct taiki payload;
+} __packed;
+
+/*
+ * SCPI Set taiki async :cmd_id 0x82
+ */
+struct taiki_async_msg {
+ u32 payload_data[64];
+} __packed;
+
+struct cmd_taiki_async_msg {
+ struct scpi_cmd_header header;
+ struct taiki_async_msg payload;
+} __packed;
+
+/*
+ * SCPI Get Memory Layout :cmd_id 0x83
+ */
+struct memory_layout_region {
+ u64 start;
+ u64 length; /* currently only 32-bit region length used by DT */
+} __attribute__ ((packed));
+
+struct memory_layout {
+ u32 count_regions; /* filled in by SCB */
+ struct memory_layout_region regions[0]; /* filled in by SCB */
+} __attribute__ ((packed));
+
+struct cmd_memory_layout {
+ struct scpi_cmd_header header;
+ struct memory_layout payload;
+} __attribute__ ((packed));
+
+/*
+ * SCPI Set CSS Power State : cmd_id 0x03
+ */
+struct set_css_powerstate {
+ union {
+ u32 state;
+ struct {
+ u32 cpu_id :4;
+ u32 cluster_id :4;
+ u32 cpu_power_state :4;
+ u32 cluster_power_state :4;
+ u32 css_power_state :4;
+ u32 reserved :12;
+ } e;
+ };
+} __attribute__ ((packed));
+
+struct cmd_set_css_powerstate {
+ struct scpi_cmd_header header;
+ struct set_css_powerstate payload;
+} __attribute__ ((packed));
+
+/*
+ * SCPI Set Power Supply : cmd_id 0x13
+ */
+struct powerdomain_set {
+ u32 power_supply_id; /* Power domain id 0-27; */
+ u32 voltage; /* Power state 0 = OFF, 1 = ON, SCB fills for Response */
+} __attribute__ ((packed));
+
+struct cmd_powerdomain_set {
+ struct scpi_cmd_header header;
+ struct powerdomain_set payload;
+} __attribute__ ((packed));
+
+/**
+ * SCPI Get Power Supply : cmd_id 0x14
+ */
+struct powerdomain_get {
+ union {
+ u16 power_supply_id; /* Power domain id 0-27; AP fills for Request */
+ u32 voltage; /* Power state 0 = OFF, 1 = ON, SCB fills for Response */
+ };
+} __attribute__ ((packed));
+
+struct cmd_powerdomain_get {
+ struct scpi_cmd_header header;
+ struct powerdomain_get payload;
+} __attribute__ ((packed));
+
+/**
+ * SCPI Get Resume Entry Point : cmd_id 0x87
+ */
+struct resume_entry_point_msg {
+ u32 resume_entry_point;
+ u32 resume_flag;
+} __attribute__ ((packed));
+
+struct cmd_resume_entry_point_msg {
+ struct scpi_cmd_header header;
+ struct resume_entry_point_msg payload;
+} __attribute__ ((packed));
+
+
+/**
+ * SCPI Get Resume Entry Point : cmd_id 0x87
+ */
+struct cmd_system_set_state {
+ struct scpi_cmd_header header;
+ u32 state;
+} __attribute__ ((packed));
+
+#endif /* __SCB_MHU_API_H */
diff -urNa -x .git original/u-boot-linaro-stable/include/sdhci.h u-boot/include/sdhci.h
--- original/u-boot-linaro-stable/include/sdhci.h 2016-08-02 12:12:09.183771674 +0900
+++ u-boot/include/sdhci.h 2016-08-02 14:19:42.041724134 +0900
@@ -34,6 +34,7 @@
*/
#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
#define SDHCI_BLOCK_SIZE 0x04
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
@@ -46,6 +47,7 @@
#define SDHCI_TRNS_DMA 0x01
#define SDHCI_TRNS_BLK_CNT_EN 0x02
#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_ACMD23 0x08
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
@@ -92,6 +94,13 @@
#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_CTRL_CD_TEST_INS 0x40
#define SDHCI_CTRL_CD_TEST 0x80
+#define SDHCI_CTRL_UHS_MASK 0x0007
+#define SDHCI_CTRL_HS_SDR200 0x0005
+#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
@@ -126,6 +135,8 @@
#define SDHCI_INT_STATUS 0x30
#define SDHCI_INT_ENABLE 0x34
#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_VENDOR_CTRL 0x124
+#define SDHCI_TUNING_SETTING 0x108
#define SDHCI_INT_RESPONSE 0x00000001
#define SDHCI_INT_DATA_END 0x00000002
#define SDHCI_INT_DMA_END 0x00000008
@@ -159,9 +170,12 @@
#define SDHCI_ACMD12_ERR 0x3C
+#define SDHCI_HOST_CONTROL2 0x3E
+
/* 3E-3F reserved */
#define SDHCI_CAPABILITIES 0x40
+#define SDHCI_CAPABILITIES_1 0x44
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
#define SDHCI_TIMEOUT_CLK_SHIFT 0
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
@@ -208,6 +222,10 @@
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
+#define F_SDH30_IO_CONTROL2 0x114
+#define F_SDH30_CRES_O_DN 0x00080000
+#define F_SDH30_MSEL_O_1_8 0x00040000
+
/*
* End of controller registers.
*/
@@ -225,6 +243,8 @@
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
#define SDHCI_QUIRK_NO_CD (1 << 5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
+#define SDHCI_QUIRK_AUTO_CMD12 (1 << 17)
+#define SDHCI_QUIRK_AUTO_CMD23 (1 << 18)
/* to make gcc happy */
struct sdhci_host;
diff -urNa -x .git original/u-boot-linaro-stable/include/serial.h u-boot/include/serial.h
--- original/u-boot-linaro-stable/include/serial.h 2016-08-02 12:12:09.183771674 +0900
+++ u-boot/include/serial.h 2016-08-02 14:19:42.042724129 +0900
@@ -33,7 +33,7 @@
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
- defined(CONFIG_MICROBLAZE)
+ defined(CONFIG_MICROBLAZE) || defined(CONFIG_MB8AC0300)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#endif
diff -urNa -x .git original/u-boot-linaro-stable/include/spi_flash.h u-boot/include/spi_flash.h
--- original/u-boot-linaro-stable/include/spi_flash.h 2016-08-02 12:12:09.184771670 +0900
+++ u-boot/include/spi_flash.h 2016-08-02 14:19:42.043724125 +0900
@@ -38,6 +38,10 @@
u32 page_size;
/* Erase (sector) size */
u32 sector_size;
+ /* Length of an address in bytes */
+ u32 address_len;
+ /* dummy cycles need by read */
+ int dummy_read;
int (*read)(struct spi_flash *flash, u32 offset,
size_t len, void *buf);
@@ -50,6 +54,12 @@
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);
+#ifdef CONFIG_FLASH_CMD_FOR_SF
+int spi_read_lock_status(struct spi_flash *flash, u32 offset, u8 *lock);
+int spi_write_lock_status(struct spi_flash *flash, u32 offset, u8 lock);
+#endif
+int spi_set_4byte_mode(struct spi_flash *flash, int en);
+
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
diff -urNa -x .git original/u-boot-linaro-stable/lib/string.c u-boot/lib/string.c
--- original/u-boot-linaro-stable/lib/string.c 2016-08-02 12:12:09.194771635 +0900
+++ u-boot/lib/string.c 2016-08-02 14:19:42.069724014 +0900
@@ -542,13 +542,21 @@
if (src == dest)
return dest;
- if (dest <= src) {
+ if (dest < src) {
+
+ if ((unsigned long)dest + count <= (unsigned long)src)
+ return memcpy(dest, src, count);
+
tmp = (char *) dest;
s = (char *) src;
while (count--)
*tmp++ = *s++;
}
else {
+
+ if ((unsigned long)src + count <= (unsigned long)dest)
+ return memcpy(dest, src, count);
+
tmp = (char *) dest + count;
s = (char *) src + count;
while (count--)