diff --git a/MAINTAINERS b/MAINTAINERS index 2daee7d..3f94785 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -927,9 +927,11 @@ Hugo Villeneuve SFFSDR ARM926EJS -Matt Waddel +Ryan Harkin +Jon Medhurst (Tixy) - ca9x4_ct_vxp ARM ARMV7 (Quad Core) + vexpress_ca9x4 ARM ARMV7 (Quad Core) + vexpress_ca5x2 ARM ARMV7 (Dual Core) Prafulla Wadaskar diff --git a/Makefile b/Makefile index bc15209..9733e36 100644 --- a/Makefile +++ b/Makefile @@ -793,7 +793,7 @@ clean: $(obj)tools/gdb/{astest,gdbcont,gdbsend} \ $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ - $(obj)tools/mk{smdk5250,}spl \ + $(obj)tools/mk{$(SOC),$(BOARD),}spl \ $(obj)tools/mxsboot \ $(obj)tools/ncb $(obj)tools/ubsha1 \ $(obj)tools/kernel-doc/docproc diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..e496dd4 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -92,6 +92,70 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } +/* exynos4: return pll clock frequency */ +static unsigned long exynos4412_get_pll_clk(int pllreg) +{ + struct exynos4412_clock *clk = + (struct exynos4412_clock *)samsung_get_base_clock(); + unsigned long r, m, p, s, k = 0, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + /* + * APLL_CON: MIDV [25:16] + * MPLL_CON: MIDV [25:16] + * EPLL_CON: MIDV [24:16] + * VPLL_CON: MIDV [24:16] + */ + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + + m = (r >> 16) & mask; + + /* PDIV [13:8] */ + p = (r >> 8) & 0x3f; + /* SDIV [2:0] */ + s = r & 0x7; + + freq = CONFIG_SYS_CLK_FREQ; + + if (pllreg == EPLL) { + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); + } else if (pllreg == VPLL) { + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); + } else { + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); + } + + return fout; +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { @@ -246,7 +310,9 @@ static unsigned long exynos4_get_pwm_clk(void) sel = readl(&clk->src_peril0); sel = (sel >> 24) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -314,7 +380,9 @@ static unsigned long exynos4_get_uart_clk(int dev_index) sel = readl(&clk->src_peril0); sel = (sel >> (dev_index << 2)) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -361,7 +429,9 @@ static unsigned long exynos5_get_uart_clk(int dev_index) sel = readl(&clk->src_peric0); sel = (sel >> (dev_index << 2)) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -387,6 +457,44 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos4: return mmc clock frequency */ +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + if (dev_index == 0) { + ratio = readl(&clk->div_fsys0); + pre_ratio = readl(&clk->div_fsys0); + } else if (dev_index == 4) { + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + } else + return 0; + + ratio = ratio & 0xf; + pre_ratio = (pre_ratio >> (dev_index + 8)) & 0xff; + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -414,13 +522,28 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } -/* exynos5: set the mmc clock */ -static void exynos5_set_mmc_clk(int dev_index, unsigned int div) +/* exynos5: return mmc clock frequency */ +static unsigned long exynos5_get_mmc_clk(int dev_index) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int addr; - unsigned int val; + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + unsigned int addr, addr_mmc; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; /* * CLK_DIV_FSYS1 @@ -435,6 +558,54 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } + ratio = readl(addr); + ratio = (ratio >> (dev_index << 2)) & 0xf; + pre_ratio = readl(addr); + pre_ratio = (pre_ratio >> ((dev_index<< 4) + 8)) & 0xff; + + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + /* Actual sclk mmc is available after mmc divider */ + ratio = readl(addr_mmc); + ratio = (ratio >> 24 ) & 0x7; + + return uclk; +} + +/* exynos5: set the mmc clock */ +static void exynos5_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int val; + + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + dev_index -= 2; + } + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO[3:0], MMC1_RATIO[3:0] + * CLK_DIV_FSYS2 + * MMC2_RATIO[3:0], MMC3_RATIO[3:0] + * Bypass the divider ratio and use only pre ratio to select + * the sclk mmc + */ + + val = readl(addr); + val &= ~(0xf << (dev_index * 16)); + writel(val, addr); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ val = readl(addr); val &= ~(0xff << ((dev_index << 4) + 8)); val |= (div & 0xff) << ((dev_index << 4) + 8); @@ -462,7 +633,9 @@ static unsigned long exynos4_get_lcd_clk(void) * 0x7: SCLK_EPLL * 0x8: SCLK_VPLL */ - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -737,6 +910,9 @@ unsigned long get_pll_clk(int pllreg) if (cpu_is_exynos5()) return exynos5_get_pll_clk(pllreg); else + if (cpu_is_exynos4412()) + return exynos4412_get_pll_clk(pllreg); + else return exynos4_get_pll_clk(pllreg); } @@ -774,6 +950,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) + return exynos5_get_mmc_clk(dev_index); + else + return exynos4_get_mmc_clk(dev_index); +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) @@ -803,3 +987,17 @@ void set_mipi_clk(void) if (cpu_is_exynos4()) exynos4_set_mipi_clk(); } + +/* + * Dump some core clockes. + */ +int do_showclocks(void) +{ + printf("\n"); + printf("USDHC1 %8d kHz\n", get_mmc_clk(0)); + printf("USDHC2 %8d kHz\n", get_mmc_clk(1)); + printf("USDHC3 %8d kHz\n", get_mmc_clk(2)); + printf("USDHC4 %8d kHz\n", get_mmc_clk(3)); + + return 0; +} diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..52d6e67 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -26,6 +26,245 @@ #include #include +static void exynos4_uart_config(int peripheral) +{ + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos4_mmc_config(int peripheral, int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + struct s5p_gpio_bank *bank, *bank_ext; + int i, start = 0, gpio_func = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio2->k0; + bank_ext = &gpio2->k1; + start = 3; + gpio_func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC1: + bank = &gpio2->k1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio2->k2; + bank_ext = &gpio2->k3; + start = 3; + gpio_func = GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC3: + bank = &gpio2->k3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos4_sromc_config(int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio2->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio2->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y6, i, GPIO_PULL_UP); + } +} + +static void exynos4_i2c_config(int peripheral, int flags) +{ + + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos4_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos4_sromc_config(flags); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4_i2c_config(peripheral, flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos5_uart_config(int peripheral) { struct exynos5_gpio_part1 *gpio1 = @@ -102,12 +341,12 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { + for (i = 0; i < 2 ; i++) { s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { + for (i = 2; i <= 6; i++) { s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); @@ -269,6 +508,8 @@ int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags); + else if (cpu_is_exynos4()) + return exynos4_pinmux_config(peripheral, flags); else { debug("pinmux functionality not supported\n"); return -1; diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index 0f985e2..d93de1e 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -26,7 +26,7 @@ #undef SYSTIMER_BASE #define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */ -#define SYSTIMER_RATE 150000000 +#define SYSTIMER_RATE (150000000 / 256) static ulong timestamp; static ulong lastinc; @@ -40,9 +40,11 @@ int timer_init(void) /* * Setup timer0 */ + writel(0, &systimer_base->timer0control); writel(SYSTIMER_RELOAD, &systimer_base->timer0load); writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control); + writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, + &systimer_base->timer0control); reset_timer_masked(); @@ -124,5 +126,5 @@ ulong get_timer_masked(void) ulong get_tbclk(void) { - return CONFIG_SYS_HZ; + return SYSTIMER_RATE; } diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 9ef10bd..42b14ed 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -29,6 +29,7 @@ */ #include #include +#include #include #include #include @@ -252,6 +253,46 @@ int print_cpuinfo(void) return 0; } + +/* + * this uses the unique per-cpu info from the cpu fuses set at factory to + * generate a 6-byte MAC address. Two bits in the generated code are used + * to elaborate the generated address into four, so it can be used on multiple + * network interfaces. + */ +void omap4_die_id_to_ethernet_mac(u8 *mac, int subtype) +{ + struct ctrl_id *id_base = (struct ctrl_id *)(CTRL_BASE + 0x200); + u32 idcode; + u32 id[4]; + + idcode = readl(&id_base->idcode); + id[0] = readl(&id_base->die_id_0); + id[1] = readl(&id_base->die_id_1); + id[2] = readl(&id_base->die_id_2); + id[3] = readl(&id_base->die_id_3); + + mac[0] = id[2]; + mac[1] = id[2] >> 8; + mac[2] = id[1]; + mac[3] = id[1] >> 8; + mac[4] = id[1] >> 16; + mac[5] = id[1] >> 24; + /* XOR other chip-specific data with ID */ + idcode ^= id[3]; + + mac[0] ^= idcode; + mac[1] ^= idcode >> 8; + mac[2] ^= idcode >> 16; + mac[3] ^= idcode >> 24; + + /* allow four MACs from this same basic data */ + mac[1] = (mac[1] & ~0xc0) | ((subtype & 3) << 6); + + /* mark it as not multicast and outside official 80211 MAC namespace */ + mac[0] = (mac[0] & ~1) | 2; +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 3581077..d5b2ed4 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -66,7 +66,13 @@ ENTRY(save_boot_params) bgt 2f /* Store the boot mode (raw/FAT) in omap_bootmode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr + bic r3, r2, #255 + cmp r3, #0 + beq 1f ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr + bic r3, r2, #255 + cmp r3, #0 + beq 1f ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode ldr r3, =omap_bootmode str r2, [r3] diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index ac597be..301853c 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o +SOBJS += cache.o COBJS += board.o COBJS += clock.o diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9cee1d9..05da747 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -49,8 +48,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); -static void omap3_invalidate_l2_cache_secure(void); static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -234,13 +231,24 @@ void s_init(void) try_unlock_memory(); - /* Errata workarounds */ - omap3_setup_aux_cr(); + /* + * Right now flushing at low MPU speed. + * Need to move after clock init + */ + invalidate_dcache(get_device_type()); -#ifndef CONFIG_SYS_L2CACHE_OFF - /* Invalidate L2-cache from secure mode */ - omap3_invalidate_l2_cache_secure(); +#ifdef CONFIG_L2_OFF + l2_cache_disable(); +#else + l2_cache_enable(); #endif + /* + * Writing to AuxCR in U-boot using SMI for GP DEV + * Currently SMI in Kernel on ES2 devices seems to have an issue + * Once that is resolved, we can postpone this config to kernel + */ + if (get_device_type() == GP_DEVICE) + setup_auxcr(); set_muxconf_regs(); sdelay(100); @@ -370,114 +378,6 @@ int checkboard (void) } #endif /* CONFIG_DISPLAY_BOARDINFO */ -static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) -{ - u32 i, num_params = *parameters; - u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; - - /* - * copy the parameters to an un-cached area to avoid coherency - * issues - */ - for (i = 0; i < num_params; i++) { - __raw_writel(*parameters, sram_scratch_space); - parameters++; - sram_scratch_space++; - } - - /* Now make the PPA call */ - do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); -} - -static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); - } -} - -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - -static void omap3_setup_aux_cr(void) -{ - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); -} - -#ifndef CONFIG_SYS_L2CACHE_OFF -/* Invalidate the entire L2 cache from secure mode */ -static void omap3_invalidate_l2_cache_secure(void) -{ - if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = 0; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, - (u32 *)&emu_romcode_params); - } -} - -void v7_outer_cache_enable(void) -{ - /* Set L2EN */ - omap3_update_aux_cr_secure(0x2, 0); - - /* - * On some revisions L2EN bit is banked on some revisions it's not - * No harm in setting both banked bits(in fact this is required - * by an erratum) - */ - omap3_update_aux_cr(0x2, 0); -} - -void omap3_outer_cache_disable(void) -{ - /* Clear L2EN */ - omap3_update_aux_cr_secure(0, 0x2); - - /* - * On some revisions L2EN bit is banked on some revisions it's not - * No harm in clearing both banked bits(in fact this is required - * by an erratum) - */ - omap3_update_aux_cr(0, 0x2); -} -#endif - #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S new file mode 100644 index 0000000..cda87ba --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is based on and replaces the existing cache.c file + * The copyrights for the cache.c file are: + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * omap3 cache code + */ + +.align 5 +.global invalidate_dcache +.global l2_cache_enable +.global l2_cache_disable +.global setup_auxcr + +/* + * invalidate_dcache() + * + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mov r7, r0 @ take a backup of device type + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 +smi: .word 0x01600070 @ Call SMI monitor (smieq) + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +l2_cache_set: + stmfd r13!, {r4 - r6, lr} + mov r5, r0 + bl get_cpu_rev + mov r4, r0 + bl get_cpu_family + @ ES2 onwards we can disable/enable L2 ourselves + cmp r0, #CPU_OMAP34XX + cmpeq r4, #CPU_3XX_ES10 + mrc 15, 0, r0, cr1, cr0, 1 + bic r0, r0, #2 + orr r0, r0, r5, lsl #1 + mcreq 15, 0, r0, cr1, cr0, 1 + @ GP Device ROM code API usage here + @ r12 = AUXCR Write function and r0 value + mov ip, #3 + @ SMCNE instruction to call ROM Code API + .word 0x11600070 + ldmfd r13!, {r4 - r6, pc} + +l2_cache_enable: + mov r0, #1 + b l2_cache_set + +l2_cache_disable: + mov r0, #0 + b l2_cache_set + +/****************************************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. + * general use. + *****************************************************************************/ +setup_auxcr: + mrc p15, 0, r0, c0, c0, 0 @ read main ID register + and r2, r0, #0x00f00000 @ variant + and r3, r0, #0x0000000f @ revision + orr r1, r3, r2, lsr #20-4 @ combine variant and revision + mov r12, #0x3 + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x10 @ Enable ASA + @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 5 + .word 0xE1600070 @ SMC + mov r12, #0x2 + mrc p15, 1, r0, c9, c0, 2 + @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 27 + .word 0xE1600070 @ SMC + bx lr + +.align 5 +.global v7_flush_dcache_all +.global v7_flush_cache_all + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * + * - mm - mm_struct describing address space + */ +v7_flush_dcache_all: +# dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr +# dsb + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mov pc, lr + +/* + * v7_flush_cache_all() + * + * Flush the entire cache system. + * The data cache flush is now achieved using atomic clean / invalidates + * working outwards from L1 cache. This is done using Set/Way based cache + * maintainance instructions. + * The instruction cache can still be invalidated back to the point of + * unification in a single instruction. + * + */ +v7_flush_cache_all: + stmfd sp!, {r0-r7, r9-r11, lr} + bl v7_flush_dcache_all + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + ldmfd sp!, {r0-r7, r9-r11, lr} + mov pc, lr diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index eacfef8..32b5a31 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -46,38 +46,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif -ENTRY(omap3_gp_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Service ID in R12 - MOV r0, r1 @ Copy parameter to R0 - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(omap3_gp_romcode_call) - -/* - * Funtion for making PPA HAL API calls in secure devices - * Input: - * R0 - Service ID - * R1 - paramer list - */ -ENTRY(do_omap3_emu_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Secure Service ID in R12 - MOV r3, r1 @ Copy the pointer to va_list in R3 - MOV r1, #0 @ Process ID - 0 - MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer - @ to va_list in R3 - MOV r6, #0xFF @ Indicate new Task call - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(do_omap3_emu_romcode_call) - #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 3c80113..10808e5 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -79,6 +79,8 @@ void dieid_num_r(void) printf("Die ID #%s\n", uid_s); } + + /****************************************** * get_cpu_type(void) - extract cpu info ******************************************/ @@ -366,3 +368,36 @@ int print_cpuinfo (void) return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ + +void omap3_die_id_to_ethernet_mac(u8 *mac, int subtype) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + u32 idcode; + u32 id[4]; + + idcode = readl(&id_base->idcode); + id[0] = readl(&id_base->die_id_0); + id[1] = readl(&id_base->die_id_1); + id[2] = readl(&id_base->die_id_2); + id[3] = readl(&id_base->die_id_3); + + mac[0] = id[2]; + mac[1] = id[2] >> 8; + mac[2] = id[1]; + mac[3] = id[1] >> 8; + mac[4] = id[1] >> 16; + mac[5] = id[1] >> 24; + /* XOR other chip-specific data with ID */ + idcode ^= id[3]; + + mac[0] ^= idcode; + mac[1] ^= idcode >> 8; + mac[2] ^= idcode >> 16; + mac[3] ^= idcode >> 24; + + /* allow four MACs from this same basic data */ + mac[1] = (mac[1] & ~0xc0) | ((subtype & 3) << 6); + + /* mark it as not multicast and outside official 80211 MAC namespace */ + mac[0] = (mac[0] & ~1) | 2; +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7df97c5..5b53c7a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -124,6 +124,29 @@ IRQ_STACK_START_IN: */ reset: +#if defined CONFIG_SPL_BUILD && defined CONFIG_SPL_USB +/* + * When loaded over USB the code lands at the base + * of SRAM so we need to copy to our actual link + * address. The destination overlaps with the source + * so copy backwards. + */ + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + ldr r8, =_start /* linked here */ + adr r7, _start /* loaded here */ + subs r6, r8, r7 /* offset */ + beq done /* nothing todo */ + ldr r9, =__image_copy_end /* dest = end of linked code */ + sub r7, r9, r6 /* source = dest - offset */ +2: ldr r6, [r7], #-4 + str r6, [r9], #-4 + cmp r9, r8 + bne 2b + ldr lr, =done + mov pc, lr +done: +#endif bl save_boot_params /* * set the cpu to SVC32 mode diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h index e745e37..08125f7 100644 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -30,6 +30,8 @@ #define SYSTIMER_RELOAD 0xFFFFFFFF #define SYSTIMER_EN (1 << 7) #define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) struct systimer { u32 timer0load; /* 0x00 */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 5529025..e015668 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -33,6 +33,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); +unsigned long get_mmc_clk(int dev_index); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..77760f2 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -251,6 +251,246 @@ struct exynos4_clock { unsigned int div_iem_l1; }; +struct exynos4412_clock { + unsigned char res1[0x4200]; + unsigned int src_leftbus; + unsigned char res2[0x1fc]; + unsigned int mux_stat_leftbus; + unsigned char res3[0xfc]; + unsigned int div_leftbus; + unsigned char res4[0xfc]; + unsigned int div_stat_leftbus; + unsigned char res5[0x1fc]; + unsigned int gate_ip_leftbus; + unsigned char res6[0x12c]; + unsigned int gate_ip_image; + unsigned char res7[0xcc]; + unsigned int clkout_cmu_leftbus; + unsigned int clkout_cmu_leftbus_div_stat; + unsigned char res8[0x37f8]; + unsigned int src_rightbus; + unsigned char res9[0x1fc]; + unsigned int mux_stat_rightbus; + unsigned char res10[0xfc]; + unsigned int div_rightbus; + unsigned char res11[0xfc]; + unsigned int div_stat_rightbus; + unsigned char res12[0x1fc]; + unsigned int gate_ip_rightbus; + unsigned char res13[0x15c]; + unsigned int gate_ip_perir; + unsigned char res14[0x9c]; + unsigned int clkout_cmu_rightbus; + unsigned int clkout_cmu_rightbus_div_stat; + unsigned char res15[0x3608]; + unsigned int epll_lock; + unsigned char res16[0xc]; + unsigned int vpll_lock; + unsigned char res17[0xec]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res18[0x4]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned int vpll_con2; + unsigned char res19[0xe4]; + unsigned int src_top0; + unsigned int src_top1; + unsigned char res20[0x8]; + unsigned int src_cam0; + unsigned int src_tv; + unsigned int src_mfc; + unsigned int src_g3d; + unsigned char res21[0x4]; + unsigned int src_lcd0; + unsigned int src_isp; + unsigned int src_maudio; + unsigned int src_fsys; + unsigned char res22[0xc]; + unsigned int src_peril0; + unsigned int src_peril1; + unsigned int src_cam1; + unsigned char res23[0xc4]; + unsigned int src_mask_cam0; + unsigned int src_mask_tv; + unsigned char res24[0xc]; + unsigned int src_mask_lcd; + unsigned int src_mask_isp; + unsigned int src_mask_maudio; + unsigned int src_mask_fsys; + unsigned char res25[0xc]; + unsigned int src_mask_peril0; + unsigned int src_mask_peril1; + unsigned char res26[0xb8]; + unsigned int mux_stat_top; + unsigned int mux_stat_top1; + unsigned char res27[0x10]; + unsigned int mux_stat_mfc; + unsigned int mux_stat_g3d; + unsigned char res28[0x28]; + unsigned int mux_stat_cam1; + unsigned char res29[0xb4]; + unsigned int div_top; + unsigned char res30[0xc]; + unsigned int div_cam0; + unsigned int div_tv; + unsigned int div_mfc; + unsigned int div_g3d; + unsigned char res31[0x4]; + unsigned int div_lcd; + unsigned int div_isp; + unsigned int div_maudio; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned int div_fsys3; + unsigned int div_peril0; + unsigned int div_peril1; + unsigned int div_peril2; + unsigned int div_peril3; + unsigned int div_peril4; + unsigned int div_peril5; + unsigned int div_cam1; + unsigned char res32[0x14]; + unsigned int div2_ratio; + unsigned char res33[0x8c]; + unsigned int div_stat_top; + unsigned char res34[0xc]; + unsigned int div_stat_cam0; + unsigned int div_stat_tv; + unsigned int div_stat_mfc; + unsigned int div_stat_g3d; + unsigned char res35[0x4]; + unsigned int div_stat_lcd; + unsigned int div_stat_isp; + unsigned int div_stat_maudio; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned int div_stat_fsys3; + unsigned int div_stat_peril0; + unsigned int div_stat_peril1; + unsigned int div_stat_peril2; + unsigned int div_stat_peril3; + unsigned int div_stat_peril4; + unsigned int div_stat_peril5; + unsigned int div_stat_cam1; + unsigned char res36[0x14]; + unsigned int div2_stat; + unsigned char res37[0xc0]; + unsigned int gate_bus_fsys1; + unsigned char res38[0x1d8]; + unsigned int gate_ip_cam; + unsigned int gate_ip_tv; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned char res39[0x4]; + unsigned int gate_ip_lcd; + unsigned int gate_ip_isp; + unsigned char res40[0x4]; + unsigned int gate_ip_fsys; + unsigned char res41[0x8]; + unsigned int gate_ip_gps; + unsigned int gate_ip_peril; + unsigned char res42[0x1c]; + unsigned int gate_block; + unsigned char res43[0x8c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res44[0x3600]; + unsigned int mpll_lock; + unsigned char res45[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res46[0xf0]; + unsigned int src_dmc; + unsigned char res47[0xfc]; + unsigned int src_mask_dmc; + unsigned char res48[0xfc]; + unsigned int mux_stat_dmc; + unsigned char res49[0xfc]; + unsigned int div_dmc0; + unsigned int div_dmc1; + unsigned char res50[0xf8]; + unsigned int div_stat_dmc0; + unsigned int div_stat_dmc1; + unsigned char res51[0x2f8]; + unsigned int gate_ip_dmc; + unsigned int gate_ip_dmc1; + unsigned char res52[0xf8]; + unsigned int clkout_cmu_dmc; + unsigned int clkout_cmu_dmc_div_stat; + unsigned char res53[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res54[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res55[0x18]; + unsigned int dvcidx_map; + unsigned char res56[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res57[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res58[0xc]; + unsigned int dmc_puause_ctrl; + unsigned int ddrphy_lock_ctrl; + unsigned int c2c_state; + unsigned char res59[0x2f60]; + unsigned int apll_lock; + unsigned char res60[0xfc]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res61[0xf8]; + unsigned int src_cpu; + unsigned char res62[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res63[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res64[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res65[0x2f8]; + unsigned int gate_ip_cpu; + unsigned char res66[0xfc]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res67[0x5f8]; + unsigned int armclk_stopctrl; + unsigned int atclk_stopctrl; + unsigned char res68[0x18]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res69[0x3d8]; + unsigned int l2_status; + unsigned char res70[0xc]; + unsigned int cpu_status; + unsigned char res71[0xc]; + unsigned int ptm_status; + unsigned char res72[0x2edc]; + unsigned int clk_div_isp0; + unsigned int clk_div_isp1; + unsigned char res73[0xf8]; + unsigned int clk_div_stat_isp0; + unsigned int clk_div_stat_isp1; + unsigned char res74[0x3f8]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res75[0x1f8]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_isp_stat; + unsigned char res76[0xf8]; + unsigned int clkout_cmu_spare0; + unsigned int clkout_cmu_spare1; + unsigned int clkout_cmu_spare2; + unsigned int clkout_cmu_spare3; +}; + struct exynos5_clock { unsigned int apll_lock; unsigned char res1[0xfc]; diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2cd4ae1..a6a7f9a 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -58,16 +58,25 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4412_DMC0_BASE 0x10600000 +#define EXYNOS4412_DMC1_BASE 0x10610000 +#define EXYNOS4412_GPIO_PART4_BASE 0x106E0000 + /* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_GPIO_PART4_BASE 0x03860000 #define EXYNOS5_PRO_ID 0x10000000 +#define EXYNOS5_GUID_LOW 0x10000014 +#define EXYNOS5_GUID_HIGH 0x10000018 #define EXYNOS5_CLOCK_BASE 0x10010000 #define EXYNOS5_POWER_BASE 0x10040000 #define EXYNOS5_SWRESET 0x10040400 #define EXYNOS5_SYSREG_BASE 0x10050000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5_GIC_DIST_BASE 0x10481000 +#define EXYNOS5_GIC_CPU_BASE 0x10482000 + #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 @@ -130,14 +139,16 @@ static inline char *s5p_get_cpu_name(void) return EXYNOS_CPU_NAME; } -#define IS_SAMSUNG_TYPE(type, id) \ +#define IS_SAMSUNG_TYPE(type, id, shift) \ static inline int cpu_is_##type(void) \ { \ - return (s5p_cpu_id >> 12) == id; \ + return (s5p_cpu_id >> shift) == id; \ } -IS_SAMSUNG_TYPE(exynos4, 0x4) -IS_SAMSUNG_TYPE(exynos5, 0x5) +IS_SAMSUNG_TYPE(exynos4, 0x4, 12) +IS_SAMSUNG_TYPE(exynos4210, 0x4210, 0) +IS_SAMSUNG_TYPE(exynos4412, 0x4412, 0) +IS_SAMSUNG_TYPE(exynos5, 0x5, 12) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h new file mode 100644 index 0000000..8acdf9b --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DWMCI_CLKSEL 0x09C +#define DWMCI_SHIFT_0 0x0 +#define DWMCI_SHIFT_1 0x1 +#define DWMCI_SHIFT_2 0x2 +#define DWMCI_SHIFT_3 0x3 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +int exynos_dwmci_init(u32 regbase, int bus_width, int index); + +static inline unsigned int exynos_dwmmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return exynos_dwmci_init(base, bus_width, index); +} diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index 8aeff8a..663d319 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -37,6 +37,25 @@ #define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HSIC_CTRL_REFCLKSEL (0x2) +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#define HSIC_CTRL_REFCLKSEL_SHIFT (23) + +#define HSIC_CTRL_REFCLKDIV_12 (0x24) +#define HSIC_CTRL_REFCLKDIV_15 (0x1C) +#define HSIC_CTRL_REFCLKDIV_16 (0x1A) +#define HSIC_CTRL_REFCLKDIV_19_2 (0x15) +#define HSIC_CTRL_REFCLKDIV_20 (0x14) +#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) +#define HSIC_CTRL_REFCLKDIV_SHIFT (16) + +#define HSIC_CTRL_SIDDQ (0x1 << 6) +#define HSIC_CTRL_FORCESLEEP (0x1 << 5) +#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) +#define HSIC_CTRL_WORDINTERFACE (0x1 << 3) +#define HSIC_CTRL_UTMISWRST (0x1 << 2) +#define HSIC_CTRL_PHYSWRST (0x1 << 0) + #define EHCICTRL_ENAINCRXALIGN (1 << 29) #define EHCICTRL_ENAINCR4 (1 << 28) #define EHCICTRL_ENAINCR8 (1 << 27) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 97be4ea..0928645 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -49,6 +49,9 @@ struct exynos4_gpio_part1 { struct s5p_gpio_bank f1; struct s5p_gpio_bank f2; struct s5p_gpio_bank f3; + struct s5p_gpio_bank res1[2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; }; struct exynos4_gpio_part2 { @@ -68,7 +71,13 @@ struct exynos4_gpio_part2 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; + struct s5p_gpio_bank res1[3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res2[72]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -79,6 +88,16 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -207,6 +226,25 @@ static inline unsigned int s5p_gpio_base(int nr) return 0; } +static inline unsigned int s5p_gpio_part_max(int nr) +{ + if (cpu_is_exynos5()) { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART1_MAX; + else + return EXYNOS5_GPIO_PART2_MAX; + + } else if (cpu_is_exynos4()) { + if (nr < EXYNOS4_GPIO_PART1_MAX) + return 0; + else + return EXYNOS4_GPIO_PART1_MAX; + } + + return 0; +} #endif /* Pin configurations */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 2b5e9ae..7a08538 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -155,14 +155,8 @@ struct gpio { SRAM_OFFSET2) #define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) -#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ -#define OMAP3_PUBLIC_SRAM_END 0x40210000 - #define LOW_LEVEL_SRAM_STACK 0x4020FFFC -/* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE - #define DEBUG_LED1 149 /* gpio */ #define DEBUG_LED2 150 /* gpio */ @@ -239,18 +233,4 @@ struct gpio { #define OMAP3730 0x0c00 -/* - * ROM code API related flags - */ -#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 -#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 - -/* - * EMU device PPA HAL related flags - */ -#define OMAP3_EMU_HAL_API_L2_INVAL 40 -#define OMAP3_EMU_HAL_API_WRITE_ACR 42 - -#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 - #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e52b12..5f82626 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -27,11 +27,6 @@ typedef struct { char *nand_string; } omap3_sysinfo; -struct emu_hal_params { - u32 num_params; - u32 param1; -}; - void prcm_init(void); void per_clocks_enable(void); void ehci_clocks_enable(void); @@ -61,7 +56,9 @@ u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); u32 get_device_type(void); +void l2cache_enable(void); void secureworld_exit(void); +void setup_auxcr(void); void try_unlock_memory(void); u32 get_boot_type(void); void invalidate_dcache(u32); @@ -72,7 +69,6 @@ void make_cs1_contiguous(void); void omap_nand_switch_ecc(int); void power_init_r(void); void dieid_num_r(void); -void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); u32 warm_reset(void); +void omap3_die_id_to_ethernet_mac(u8 *, int); #endif diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 3a0bfbf..4258f34 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -94,6 +94,17 @@ struct gptimer { u32 tcicr; /* 0x40 rw */ u32 tcar2; /* 0x44 r */ }; + +struct ctrl_id { + u32 die_id_0; /* 0x00 */ + u32 idcode; /* 0x04 */ + u32 die_id_1; /* 0x08 */ + u32 die_id_2; /* 0x0c */ + u32 die_id_3; /* 0x10 */ + u32 prod_id_0; /* 0x14 */ + u32 prod_id_1; /* 0x18 */ +}; + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index d4b5076..a7e97eb 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -167,7 +167,7 @@ struct control_lpddr2io_regs { * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ -#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_START 0x40303000 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index cec84dc..abbb9bc 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -31,5 +31,6 @@ #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 0xFF +#define BOOT_DEVICE_USB 69 /* usb periperal */ #endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index b48f81d..77f2cf7 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -58,6 +58,7 @@ void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); +void omap4_die_id_to_ethernet_mac(u8 *, int); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 76b901b..00e498d 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -143,7 +143,12 @@ static inline unsigned int s5p_gpio_base(int nr) return S5PC110_GPIO_BASE; } -#define s5pc110_gpio_get_nr(bank, pin) \ +static inline unsigned int s5p_gpio_part_max(int nr) +{ + return 0; +} + +#define s5pc110_gpio_get_nr(bank, pin) \ ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 37476cc..9f31307 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -265,6 +265,11 @@ static int create_fdt(bootm_headers_t *images) ft_board_setup(*of_flat_tree, gd->bd); #endif +#ifdef CONFIG_OF_BOARD_SETUP + /* Call the board-specific fixup routine */ + ft_board_setup(*of_flat_tree, gd->bd); +#endif + return 0; } #endif diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile index 8749590..6719f3d 100644 --- a/board/armltd/vexpress/Makefile +++ b/board/armltd/vexpress/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := ca9x4_ct_vxp.o +COBJS := vexpress_common.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c deleted file mode 100644 index d5e109e..0000000 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include "../drivers/mmc/arm_pl180_mmci.h" - -static ulong timestamp; -static ulong lastdec; - -static struct wdt *wdt_base = (struct wdt *)WDT_BASE; -static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE; -static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; - -static void flash__init(void); -static void vexpress_timer_init(void); -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -static inline void delay(ulong loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_init(void) -{ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; - gd->flags = 0; - - icache_enable(); - flash__init(); - vexpress_timer_init(); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -int cpu_mmc_init(bd_t *bis) -{ - int rc = 0; - (void) bis; -#ifdef CONFIG_ARM_PL180_MMCI - struct pl180_mmc_host *host; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - strcpy(host->name, "MMC"); - host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; - host->pwr_init = INIT_PWR; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; - host->voltages = VOLTAGE_WINDOW_MMC; - host->caps = 0; - host->clock_in = ARM_MCLK; - host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); - host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; - rc = arm_pl180_mmci_init(host); -#endif - return rc; -} - -static void flash__init(void) -{ - /* Setup the sytem control register to allow writing to flash */ - writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, - &sysctrl_base->scflashctrl); -} - -int dram_init(void) -{ - gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = - get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); -} - -int timer_init(void) -{ - return 0; -} - -/* - * Start timer: - * Setup a 32 bit timer, running at 1KHz - * Versatile Express Motherboard provides 1 MHz timer - */ -static void vexpress_timer_init(void) -{ - /* - * Set clock frequency in system controller: - * VEXPRESS_REFCLK is 32KHz - * VEXPRESS_TIMCLK is 1MHz - */ - writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | - SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | - readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); - - /* - * Set Timer0 to be: - * Enabled, free running, no interrupt, 32-bit, wrapping - */ - writel(SYSTIMER_RELOAD, &systimer_base->timer0load); - writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT | \ - readl(&systimer_base->timer0control), \ - &systimer_base->timer0control); - - reset_timer_masked(); -} - -/* Use the ARM Watchdog System to cause reset */ -void reset_cpu(ulong addr) -{ - writeb(WDT_EN, &wdt_base->wdogcontrol); - writel(WDT_RESET_LOAD, &wdt_base->wdogload); - while (1) - ; -} - -/* - * Delay x useconds AND perserve advance timstamp value - * assumes timer is ticking at 1 msec - */ -void __udelay(ulong usec) -{ - ulong tmo, tmp; - - tmo = usec / 1000; - tmp = get_timer(0); /* get current timestamp */ - - /* - * If setting this forward will roll time stamp then - * reset "advancing" timestamp to 0 and set lastdec value - * otherwise set the advancing stamp to the wake up time - */ - if ((tmo + tmp + 1) < tmp) - reset_timer_masked(); - else - tmo += tmp; - - while (get_timer_masked() < tmo) - ; /* loop till wakeup event */ -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void reset_timer_masked(void) -{ - lastdec = readl(&systimer_base->timer0value) / 1000; - timestamp = 0; -} - -ulong get_timer_masked(void) -{ - ulong now = readl(&systimer_base->timer0value) / 1000; - - if (lastdec >= now) { /* normal mode (non roll) */ - timestamp += lastdec - now; - } else { /* count down timer overflowed */ - /* - * nts = ts + ld - now - * ts = old stamp, ld = time before passing through - 1 - * now = amount of time after passing though - 1 - * nts = new "advancing time stamp" - */ - timestamp += lastdec + SYSTIMER_RELOAD - now; - } - lastdec = now; - - return timestamp; -} - -void lowlevel_init(void) -{ -} - -ulong get_board_rev(void){ - return readl((u32 *)SYS_ID); -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c new file mode 100644 index 0000000..369b06f --- /dev/null +++ b/board/armltd/vexpress/vexpress_common.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "../drivers/mmc/arm_pl180_mmci.h" + +static ulong timestamp; +static ulong lastdec; + +static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; +static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; + +static void flash__init(void); +static void vexpress_timer_init(void); +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(ulong loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; + gd->flags = 0; + + icache_enable(); + flash__init(); + vexpress_timer_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +int cpu_mmc_init(bd_t *bis) +{ + int rc = 0; + (void) bis; +#ifdef CONFIG_ARM_PL180_MMCI + struct pl180_mmc_host *host; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + strcpy(host->name, "MMC"); + host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; + host->voltages = VOLTAGE_WINDOW_MMC; + host->caps = 0; + host->clock_in = ARM_MCLK; + host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; + rc = arm_pl180_mmci_init(host); +#endif + return rc; +} + +static void flash__init(void) +{ + /* Setup the sytem control register to allow writing to flash */ + writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, + &sysctrl_base->scflashctrl); +} + +int dram_init(void) +{ + gd->ram_size = + get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = + get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +} + +int timer_init(void) +{ + return 0; +} + +/* + * Start timer: + * Setup a 32 bit timer, running at 1KHz + * Versatile Express Motherboard provides 1 MHz timer + */ +static void vexpress_timer_init(void) +{ + /* + * Set clock frequency in system controller: + * VEXPRESS_REFCLK is 32KHz + * VEXPRESS_TIMCLK is 1MHz + */ + writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | + SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | + readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); + + /* + * Set Timer0 to be: + * Enabled, free running, no interrupt, 32-bit, wrapping + */ + writel(SYSTIMER_RELOAD, &systimer_base->timer0load); + writel(SYSTIMER_RELOAD, &systimer_base->timer0value); + writel(SYSTIMER_EN | SYSTIMER_32BIT | \ + readl(&systimer_base->timer0control), \ + &systimer_base->timer0control); + + reset_timer_masked(); +} + +int v2m_cfg_write(u32 devfn, u32 data) +{ + /* Configuration interface broken? */ + u32 val; + + devfn |= SYS_CFG_START | SYS_CFG_WRITE; + + val = readl(V2M_SYS_CFGSTAT); + writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); + + writel(data, V2M_SYS_CFGDATA); + writel(devfn, V2M_SYS_CFGCTRL); + + do { + val = readl(V2M_SYS_CFGSTAT); + } while (val == 0); + + return !!(val & SYS_CFG_ERR); +} + +/* Use the ARM Watchdog System to cause reset */ +void reset_cpu(ulong addr) +{ + if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) + printf("Unable to reboot\n"); +} + +/* + * Delay x useconds AND perserve advance timstamp value + * assumes timer is ticking at 1 msec + */ +void __udelay(ulong usec) +{ + ulong tmo, tmp; + + tmo = usec / 1000; + tmp = get_timer(0); /* get current timestamp */ + + /* + * If setting this forward will roll time stamp then + * reset "advancing" timestamp to 0 and set lastdec value + * otherwise set the advancing stamp to the wake up time + */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + while (get_timer_masked() < tmo) + ; /* loop till wakeup event */ +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + lastdec = readl(&systimer_base->timer0value) / 1000; + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = readl(&systimer_base->timer0value) / 1000; + + if (lastdec >= now) { /* normal mode (non roll) */ + timestamp += lastdec - now; + } else { /* count down timer overflowed */ + /* + * nts = ts + ld - now + * ts = old stamp, ld = time before passing through - 1 + * now = amount of time after passing though - 1 + * nts = new "advancing time stamp" + */ + timestamp += lastdec + SYSTIMER_RELOAD - now; + } + lastdec = now; + + return timestamp; +} + +void lowlevel_init(void) +{ +} + +ulong get_board_rev(void){ + return readl((u32 *)SYS_ID); +} + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk (void) +{ + return (ulong)CONFIG_SYS_HZ; +} diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index f41bf05..c27c40a 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -25,11 +25,19 @@ #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 +#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 +#define HB_SYSRAM_OPP_TABLE_BASE 0xfff8f000 +#define HB_OPP_VERSION 0 + #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 #define HB_PWR_HARD_RESET 2 #define HB_PWR_SHUTDOWN 3 +#define PWRDOM_STAT_SATA 0x80000000 +#define PWRDOM_STAT_PCI 0x40000000 +#define PWRDOM_STAT_EMMC 0x20000000 + DECLARE_GLOBAL_DATA_PTR; /* @@ -58,9 +66,12 @@ int misc_init_r(void) { char envbuffer[16]; u32 boot_choice; + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); - ahci_init(0xffe08000); - scsi_scan(1); + if (reg & PWRDOM_STAT_SATA) { + ahci_init(0xffe08000); + scsi_scan(1); + } boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; sprintf(envbuffer, "bootcmd%d", boot_choice); @@ -85,8 +96,46 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } +#if defined(CONFIG_OF_BOARD_SETUP) +struct a9_opp { + unsigned int freq_hz; + unsigned int volt_mv; +}; + + +void ft_board_setup(void *fdt, bd_t *bd) +{ + const char disabled[] = "disabled"; + u32 *opp_table = HB_SYSRAM_OPP_TABLE_BASE; + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + + if (!(reg & PWRDOM_STAT_SATA)) + do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status", disabled, sizeof(disabled), 1); + + if (!(reg & PWRDOM_STAT_EMMC)) + do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", disabled, sizeof(disabled), 1); + + if ((opp_table[0] >> 16) == HB_OPP_VERSION) { + u32 dtb_table[2*10]; + u32 i; + u32 num_opps = opp_table[0] & 0xff; + for (i = 0; i < num_opps; i++) { + dtb_table[2 * i] = cpu_to_be32(opp_table[3 + 3 * i]); + dtb_table[2 * i + 1] = + cpu_to_be32(opp_table[2 + 3 * i]); + } + fdt_find_and_setprop(fdt, "/cpus/cpu@0", "transition-latency", + cpu_to_be32(opp_table[1]), 4, 1); + fdt_find_and_setprop(fdt, "/cpus/cpu@0", "operating-points", + dtb_table, 8 * num_opps, 1); + } +} +#endif + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); - asm(" wfi"); + writeb(0x3, 0xfff10008); + /* older compilers don't understand wfi instr, so hardcode it */ + asm(" .word 0xe320f003"); } diff --git a/board/highbank/scripts/autoboot.txt b/board/highbank/scripts/autoboot.txt new file mode 100644 index 0000000..eee5116 --- /dev/null +++ b/board/highbank/scripts/autoboot.txt @@ -0,0 +1,30 @@ +bootcmd_setup= +bootcmd_pxe=setenv bootfile "" ;dhcp; pxe get; pxe boot +bootcmd_disk_scr=ext2load ${boot_ifc} ${bootdevice} ${scr_addr_r} boot.scr && source ${scr_addr_r} +bootcmd_disk_sysboot1=setenv bootfile /boot/extlinux/extlinux.conf; sysboot ${boot_ifc} ${bootdevice} ext2 +bootcmd_disk_sysboot2=setenv bootfile /extlinux/extlinux.conf; sysboot ${boot_ifc} ${bootdevice} ext2 +bootcmd_disk_uenv=ext2load ${boot_ifc} ${bootdevice} ${uenv_addr_r} uEnv.txt; env import -t ${uenv_addr_r} ${filesize}; run bootcmd_uenv +bootcmd_disk_kernel=ext2load ${boot_ifc} ${bootdevice} ${kernel_addr_r} vmlinuz && ext2load ${boot_ifc} ${bootdevice} ${ramdisk_addr_r} initrd.img && bootz ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr} +bootcmd_disk=run bootcmd_disk_sysboot1; run bootcmd_disk_sysboot2; run bootcmd_disk_uenv; run bootcmd_disk_scr; run bootcmd_disk_kernel +bootcmd_sata=setenv boot_ifc scsi; scsi scan && run bootcmd_disk +bootcmd_mmc=setenv boot_ifc mmc; mmc rescan && run bootcmd_disk +bootcmd_default=run bootcmd_sata; run bootcmd_pxe +bootcmd0=run bootcmd_setup; run bootcmd_default +bootcmd1=run bootcmd_setup; run bootcmd_pxe +bootcmd2=run bootcmd_setup; run bootcmd_sata +bootcmd15=run bootcmd_setup; run bootcmd_mmc +localcmd=run bootcmd_sata +bootdevice=0 +bootargs=console=ttyAMA0 root=LABEL=rootfs nosplash +bootdelay=2 +bootretry=90 +netretry=once +fdt_addr=0x1000 +fdt_high=0xffffffff +pxefile_addr_r=0x700000 +kernel_addr_r=0x800000 +ramdisk_addr_r=0x01000000 +initrd_high=0xffffffff +scr_addr_r=0x100000 +uenv_addr_r=0x600000 + diff --git a/board/insignal/origen_quad/Makefile b/board/insignal/origen_quad/Makefile new file mode 100644 index 0000000..04f609a --- /dev/null +++ b/board/insignal/origen_quad/Makefile @@ -0,0 +1,63 @@ +# +# Copyright (C) 2012 Samsung Electronics +# +# Copyright (C) 2012 Insignal +# +# Makefile for the Insignal OrigenQUAD board (Exynos4x12) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +SOBJS := lowlevel_init.o + +COBJS := clock.o +COBJS += dmc.o + +ifdef CONFIG_PMIC +COBJS += pmic.o +endif + +ifndef CONFIG_SPL_BUILD +COBJS += origen_quad.o +else +COBJS += boot.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +ALL := $(obj).depend $(LIB) + +all: $(ALL) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/insignal/origen_quad/boot.c b/board/insignal/origen_quad/boot.c new file mode 100644 index 0000000..10f2289 --- /dev/null +++ b/board/insignal/origen_quad/boot.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Board initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "setup.h" + +#define IRAM_ADDRESS 0x02020000 +#define EXTERNAL_FUNC_ADDRESS (IRAM_ADDRESS + 0x0030) +#define IROM_READ_SDMMC EXTERNAL_FUNC_ADDRESS + +void inline irom_read_sdmmc(u32 start, u32 count, u32 addr) +{ + void (*read_sdmmc)(u32, u32, u32) = (void *) *(u32 *)IROM_READ_SDMMC; + read_sdmmc(start, count, addr); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + + irom_read_sdmmc(BL2_BLK_OFFSET, BL2_BLK_COUNT, CONFIG_SYS_TEXT_BASE); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* Function attribute is no-return */ + /* This Function never executes */ + while (1); +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} diff --git a/board/insignal/origen_quad/clock.c b/board/insignal/origen_quad/clock.c new file mode 100644 index 0000000..7f08e49 --- /dev/null +++ b/board/insignal/origen_quad/clock.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Clock setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "setup.h" + +void clock_ctrl_init(void) +{ + struct exynos4412_clock *clk = (struct exynos4412_clock *)EXYNOS4_CLOCK_BASE; + unsigned int val; + + /* CLK_SRC_CPU */ + writel(0x00000000, &clk->src_cpu); + sdelay(0x10000); + + /* CLK_DIV_DMC */ + writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); + writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); + + /* CLK_SRC_TOP */ + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + sdelay(0x10000); + writel(CLK_DIV_TOP_VAL, &clk->div_top); + + /* LEFTBUS */ + writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); + sdelay(0x10000); + writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); + /* RIGHTBUS */ + writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); + sdelay(0x10000); + writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); + + /* PLL locktime */ + writel(APLL_LOCK_VAL, &clk->apll_lock); + writel(MPLL_LOCK_VAL, &clk->mpll_lock); + writel(EPLL_LOCK_VAL, &clk->epll_lock); + writel(VPLL_LOCK_VAL, &clk->vpll_lock); + + /* CLK_DIV_CPU0/1 */ + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); + + /* APLL */ + writel(APLL_CON1_VAL, &clk->apll_con1); + writel(APLL_CON0_VAL, &clk->apll_con0); + /* MPLL */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + writel(MPLL_CON0_VAL, &clk->mpll_con0); + /* EPLL */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + writel(EPLL_CON0_VAL, &clk->epll_con0); + /* VPLL */ + writel(VPLL_CON2_VAL, &clk->vpll_con2); + writel(VPLL_CON1_VAL, &clk->vpll_con1); + writel(VPLL_CON0_VAL, &clk->vpll_con0); + sdelay(0x40000); + + writel(CLK_SRC_CPU_VAL, &clk->src_cpu); + writel(CLK_SRC_DMC_VAL, &clk->src_dmc); + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + sdelay(0x10000); + + /* UART */ + writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); + writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); + + /* for IROM */ + /* CLK_DIV_FSYS2 */ + writel(0x0000000F, &clk->div_fsys2); /* MMC2 - SDMMC */ + /* CLK_DIV_FSYS3 */ + writel(0x00000100, &clk->div_fsys3); /* MMC4 - eMMC */ +} + diff --git a/board/insignal/origen_quad/dmc.c b/board/insignal/origen_quad/dmc.c new file mode 100644 index 0000000..412f33a --- /dev/null +++ b/board/insignal/origen_quad/dmc.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Memory setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "setup.h" + +void mem_ctrl_init(void) +{ + struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE; + struct exynos4_dmc *dmc0 = (struct exynos4_dmc *)(EXYNOS4412_DMC0_BASE); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(EXYNOS4412_DMC1_BASE); + + /* Set DMC to 50MHz for IROM */ + writel(0x00117713, &clk->div_dmc0); + + /* + * DMC 0 + */ + writel(0xE3855403, &dmc0->phyzqcontrol); + writel(0x71101008, &dmc0->phycontrol0); + writel(0x7110100A, &dmc0->phycontrol0); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x71101008, &dmc0->phycontrol0); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x0FFF30CA, &dmc0->concontrol); + writel(0x00202500, &dmc0->memcontrol); + writel(0x40C01323, &dmc0->memconfig0); + writel(0x80000007, &dmc0->ivcontrol); + + writel(0x64000000, &dmc0->prechconfig); + writel(0x9C4000FF, &dmc0->phycontrol0); + writel(0x0000005D, &dmc0->timingref); + +#if (CONFIG_CLK_MPLL == 330) + writel(0x2b47654e, &dmc0->timingrow); + writel(0x35330306, &dmc0->timingdata); + writel(0x442f0365, &dmc0->timingpower); +#else + writel(0x34498691, &dmc0->timingrow); + writel(0x36330306, &dmc0->timingdata); + writel(0x50380365, &dmc0->timingpower); +#endif + sdelay(0x100000); + + writel(0x07000000, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00071C00, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00010BFC, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00000608, &dmc0->directcmd); + writel(0x00000810, &dmc0->directcmd); + writel(0x00000C08, &dmc0->directcmd); + + /* + * DMC 1 + */ + writel(0xE3855403, &dmc1->phyzqcontrol); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x7110100A, &dmc1->phycontrol0); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x0FFF30CA, &dmc1->concontrol); + writel(0x00202500, &dmc1->memcontrol); + writel(0x40C01323, &dmc1->memconfig0); + writel(0x80000007, &dmc1->ivcontrol); + writel(0x64000000, &dmc1->prechconfig); + writel(0x9C4000FF, &dmc1->phycontrol0); + writel(0x0000005D, &dmc1->timingref); + +#if (CONFIG_CLK_MPLL == 330) + writel(0x2b47654e, &dmc1->timingrow); + writel(0x35330306, &dmc1->timingdata); + writel(0x442f0365, &dmc1->timingpower); +#else + writel(0x34498691, &dmc1->timingrow); + writel(0x36330306, &dmc1->timingdata); + writel(0x50380365, &dmc1->timingpower); +#endif + sdelay(0x100000); + + writel(0x07000000, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00071C00, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00010BFC, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00000608, &dmc1->directcmd); + writel(0x00000810, &dmc1->directcmd); + writel(0x00000C08, &dmc1->directcmd); +} + +void mem_ctrl_init_2nd(void) +{ + struct exynos4_dmc *dmc0 = (struct exynos4_dmc *)(EXYNOS4_MIU_BASE); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000); + + writel(0x7F10100A, &dmc0->phycontrol0); + writel(0xE0000084, &dmc0->phycontrol1); + writel(0x7F10100B, &dmc0->phycontrol0); + sdelay(20000); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + sdelay(20000); + + writel(0x7F10100A, &dmc1->phycontrol0); + writel(0xE0000084, &dmc1->phycontrol1); + writel(0x7F10100B, &dmc1->phycontrol0); + sdelay(20000); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + sdelay(20000); + + writel(0x0FFF30FA, &dmc0->concontrol); + writel(0x0FFF30FA, &dmc1->concontrol); + writel(0x00202533, &dmc0->memcontrol); + writel(0x00202533, &dmc1->memcontrol); +} diff --git a/board/insignal/origen_quad/lowlevel_init.S b/board/insignal/origen_quad/lowlevel_init.S new file mode 100644 index 0000000..427b5c6 --- /dev/null +++ b/board/insignal/origen_quad/lowlevel_init.S @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Lowlevel initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "setup.h" + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + + /* use iRAM stack in bl2 */ + ldr sp, =0x02060000 + stmdb r13!, {ip,lr} + + /* check reset status */ + ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM1 */ + ldr r1, [r0] + + /* AFTR wakeup reset */ + ldr r2, =S5P_CHECK_DIDLE + cmp r1, r2 + beq exit_wakeup + + /* LPA wakeup reset */ + ldr r2, =S5P_CHECK_LPA + cmp r1, r2 + beq exit_wakeup + + /* Sleep wakeup reset */ + ldr r2, =S5P_CHECK_SLEEP + cmp r1, r2 + beq wakeup_reset + + /* + * If U-boot is already running in RAM, no need to relocate U-Boot. + * Memory controller must be configured before relocating U-Boot + * in ram. + */ + ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ + bic r1, pc, r0 /* pc <- current addr of code */ + /* r1 <- unmasked bits of pc */ + ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ + bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ + cmp r1, r2 /* compare r1, r2 */ + beq 1f /* r0 == r1 then skip sdram init */ + +#ifdef CONFIG_PMIC + /* PMIC initialize */ + bl pmic_init +#endif + + /* DMC initialize */ + bl mem_ctrl_init + + /* CMU initialize */ + bl clock_ctrl_init + + /* DMC initialize */ + bl mem_ctrl_init_2nd + + /* Trust zone initialize */ + bl tzpc_init + +1: + ldmia r13!, {ip,pc} + +wakeup_reset: + bl clock_ctrl_init + bl mem_ctrl_init + bl tzpc_init + +exit_wakeup: + /* Load return address and jump to kernel */ + ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM0 */ + + /* r1 = physical address of exynos4_cpu_resume function*/ + ldr r1, [r0] + + /* Jump to kernel */ + mov pc, r1 + nop + nop + +/* + * Setting TZPC[TrustZone Protection Controller] + */ +tzpc_init: + + ldr r0, =TZPC0_BASE + mov r1, #0x0 + str r1, [r0] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + mov r1, #0xbd + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + mov pc, lr + diff --git a/board/insignal/origen_quad/origen_quad.c b/board/insignal/origen_quad/origen_quad.c new file mode 100644 index 0000000..284519d --- /dev/null +++ b/board/insignal/origen_quad/origen_quad.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Board initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: " CONFIG_BOARDNAME "\n"); + return 0; +} +#endif + + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + +#ifdef CONFIG_RESERVED_DRAM + gd->ram_size -= CONFIG_RESERVED_DRAM; +#endif + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + +#ifdef CONFIG_RESERVED_DRAM + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= CONFIG_RESERVED_DRAM; +#endif +} + +#ifdef CONFIG_GENERIC_MMC +int board_emmc_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) { + debug("SDMMC0 not configured\n"); + return err; + } + return s5p_mmc_init(0, 8); +} + +int board_sdmmc_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; + } + return s5p_mmc_init(2, 4); +} + +int board_mmc_init(bd_t *bis) +{ + int err; + + struct exynos4_power *power = (struct exynos4_power *)samsung_get_base_power(); + + if ((power->om_stat & 0x1E) == 0x8) { + err = board_emmc_init(); + err = board_sdmmc_init(); + } else { + err = board_sdmmc_init(); + err = board_emmc_init(); + } + + return 0; +} +#endif + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + if (smc9115_pre_init()) + return -1; + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return 0; +} + +static int board_uart_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE); + if (err) + debug("UART%d not configured\n", + PERIPH_ID_UART - PERIPH_ID_UART0); + return err; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + err = board_uart_init(); + if (err) + debug("UART%d init failed\n", + PERIPH_ID_UART - PERIPH_ID_UART0); + return err; +} +#endif diff --git a/board/insignal/origen_quad/pmic.c b/board/insignal/origen_quad/pmic.c new file mode 100644 index 0000000..070a3a5 --- /dev/null +++ b/board/insignal/origen_quad/pmic.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * PMIC setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "setup.h" + +int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) +{ + return 0; +} + +int pmic_reg_write(struct pmic *p, u32 reg, u32 *val) +{ + return 0; +} + +void pmic_init(void) +{ + /* PS-Hold high */ + writel(0x5300, EXYNOS4_POWER_BASE + 0x330c); +} + diff --git a/board/insignal/origen_quad/setup.h b/board/insignal/origen_quad/setup.h new file mode 100644 index 0000000..98a6171 --- /dev/null +++ b/board/insignal/origen_quad/setup.h @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Configuration settings for the Insignal Origen QUAD board (Exynos4412) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SETUP_ORIGEN_QUAD_H +#define __SETUP_ORIGEN_QUAD_H + +#include +#include +#include + +/* Set PLL */ +#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) + +/* APLL */ +#define set_clk_div_cpu0(core2, apll, pclk_dbg, atb, periph, corem1, corem0, core) \ + ((core2 << 28) \ + |(apll << 24) \ + |(pclk_dbg << 20) \ + |(atb << 16) \ + |(periph <<12) \ + |(corem1 << 8) \ + |(corem0 << 4) \ + |(core)) +#define set_clk_div_cpu1(cores, hpm, copy) \ + ((cores << 8) \ + |(hpm << 4) \ + |(copy)) + +#if (CONFIG_CLK_APLL == 800) +#define APLL_CON0_VAL set_pll(0x64, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 3, 7, 5, 2, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 3) +#elif (CONFIG_CLK_APLL == 1000) +#define APLL_CON0_VAL set_pll(0x7D, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 4, 7, 5, 2, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 4) +#elif (CONFIG_CLK_APLL == 1100) +#define APLL_CON0_VAL set_pll(0x113, 0x6, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 4, 7, 6, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4) +#elif (CONFIG_CLK_APLL == 1200) +#define APLL_CON0_VAL set_pll(0x96, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4) +#elif (CONFIG_CLK_APLL == 1300) +#define APLL_CON0_VAL set_pll(0x145, 0x6, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 5) +#elif (CONFIG_CLK_APLL == 1400) +#define APLL_CON0_VAL set_pll(0xAF, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6) +#elif (CONFIG_CLK_APLL == 1500) +#define APLL_CON0_VAL set_pll(0xFA, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 4, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6) +#else +#error Not supported APLL freq +#endif + +#define APLL_CON1_VAL (0x00803800) +#define APLL_LOCK_VAL (((APLL_CON0_VAL >> 8) & 0x3F) * 270) + +/* EPLL */ +#define EPLL_CON0_VAL set_pll(0x40, 0x2, 0x3) +#define EPLL_CON1_VAL (0x66010000) +#define EPLL_CON2_VAL (0x00000080) +#define EPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000) + +/* MPLL */ +#if (CONFIG_CLK_MPLL == 200) +#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x1) +#elif (CONFIG_CLK_MPLL == 330) +#define MPLL_CON0_VAL set_pll(0x116, 0x5, 0x1) +#elif (CONFIG_CLK_MPLL == 400) +#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x0) +#else +#error Not supported MPLL freq +#endif +#define MPLL_CON1_VAL (0x00803800) +#define MPLL_LOCK_VAL (((MPLL_CON0_VAL >> 8) & 0x3F) * 270) + +/* VPLL */ +#define VPLL_CON0_VAL set_pll(0x48, 0x2, 0x3) +#define VPLL_CON1_VAL (0x66010000) +#define VPLL_CON2_VAL (0x00000080) +#define VPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000) + +/* CLK_SRC_CPU */ +#define MUX_MPLL_USER_SEL 1 +#define MUX_HPM_SEL 0 +#define MUX_CORE_SEL 0 +#define MUX_APLL_SEL 1 +#define CLK_SRC_CPU_VAL ((MUX_MPLL_USER_SEL << 24) \ + |(MUX_HPM_SEL << 20) \ + |(MUX_CORE_SEL << 16) \ + |(MUX_APLL_SEL)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166 */ +#define MUX_ACLK_133_SEL 0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */ +#define MUX_ACLK_160_SEL 0x0 +#define MUX_ACLK_100_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL << 28) \ + |(MUX_ACLK_133_SEL << 24) \ + |(MUX_ACLK_160_SEL << 20) \ + |(MUX_ACLK_100_SEL << 16) \ + |(MUX_ACLK_200_SEL << 12) \ + |(MUX_VPLL_SEL << 8) \ + |(MUX_EPLL_SEL << 4)) + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL 0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */ +#define CLK_SRC_TOP1_VAL (0x01111000) + +/* CLK_DIV_TOP */ +#define ACLK_400_MCUISP_RATIO 0x1 +#define ACLK_266_GPS_RATIO 0x2 +#define ONENAND_RATIO 0x1 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x4 +#define CLK_DIV_TOP_VAL ((ACLK_400_MCUISP_RATIO << 24) \ + |(ACLK_266_GPS_RATIO << 20) \ + |(ONENAND_RATIO << 16) \ + |(ACLK_133_RATIO << 12) \ + |(ACLK_160_RATIO << 8) \ + |(ACLK_100_RATIO << 4) \ + |(ACLK_200_RATIO)) + +/* CLK_SRC_LEFTBUS */ +#define CLK_SRC_LEFTBUS_VAL (0x10) + +/* CLK_DIV_LEFRBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4)|(GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define CLK_SRC_RIGHTBUS_VAL (0x10) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4)|(GDR_RATIO)) + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL 0x1 +#define MUX_CORE_TIMERS_SEL 0x1 +#define MUX_DPHY_SEL 0x0 +#define MUX_DMC_BUS_SEL 0x0 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL << 16) \ + |(MUX_CORE_TIMERS_SEL << 12) \ + |(MUX_DPHY_SEL << 8) \ + |(MUX_DMC_BUS_SEL << 4)) + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x0 +#define COPY2_RATIO 0x0 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#if (CONFIG_CLK_MPLL == 200) +#define DMC_RATIO 0x3 +#else +#define DMC_RATIO 0x1 +#endif +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 + +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + |(COPY2_RATIO << 24) \ + |(DMCP_RATIO << 20) \ + |(DMCD_RATIO << 16) \ + |(DMC_RATIO << 12) \ + |(DPHY_RATIO << 8) \ + |(ACP_PCLK_RATIO << 4) \ + |(ACP_RATIO)) + +#define CLK_DIV_DMC1_VAL (0x07071713) + +/* CLK_SRC_PERIL0 */ +#define UART4_SEL 1 +#define UART3_SEL 1 +#define UART2_SEL 1 +#define UART1_SEL 1 +#define UART0_SEL 1 +#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ + |(UART3_SEL << 12) \ + |(UART2_SEL<< 8) \ + |(UART1_SEL << 4) \ + |(UART0_SEL)) + +/* CLK_DIV_PERIL0 */ +#define UART4_RATIO 3 +#define UART3_RATIO 3 +#define UART2_RATIO 3 +#define UART1_RATIO 3 +#define UART0_RATIO 3 +#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ + |(UART3_RATIO << 12) \ + |(UART2_RATIO << 8) \ + |(UART1_RATIO << 4) \ + |(UART0_RATIO)) + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* TZPC */ +#define TZPC_BASE 0x10110000 +#define TZPC_OFFSET 0x10000 +#define TZPC0_BASE (TZPC_BASE) +#define TZPC1_BASE (TZPC0_BASE + TZPC_OFFSET) +#define TZPC2_BASE (TZPC1_BASE + TZPC_OFFSET) +#define TZPC3_BASE (TZPC2_BASE + TZPC_OFFSET) +#define TZPC4_BASE (TZPC3_BASE + TZPC_OFFSET) +#define TZPC5_BASE (TZPC4_BASE + TZPC_OFFSET) +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* IMAGE SIZE (BYTE) */ +#define MBR_BYTE_COUNT CONFIG_MBR_SIZE +#define SBL_BYTE_COUNT CONFIG_SBL_SIZE +#define BL1_BYTE_COUNT CONFIG_BL1_SIZE +#define BL2_BYTE_COUNT CONFIG_BL2_SIZE +#define ENV_BYTE_COUNT CONFIG_ENV_SIZE + +/* IMAGE OFFSET (BYTE) */ +#define MBR_BYTE_OFFSET (0) +#define SBL_BYTE_OFFSET (MBR_BYTE_OFFSET + MBR_BYTE_COUNT) +#define BL1_BYTE_OFFSET (SBL_BYTE_OFFSET + SBL_BYTE_COUNT) +#define BL2_BYTE_OFFSET (BL1_BYTE_OFFSET + BL1_BYTE_COUNT) +#define ENV_BYTE_OFFSET (Bl2_BYTE_OFFSET + BL2_BYTE_COUNT) + +#define SDMMC_BLK_SIZE (512) + +/* IMAGE SIZE (BLOCK) */ +#define SBL_BLK_COUNT (SBL_BYTE_COUNT / SDMMC_BLK_SIZE) +#define BL1_BLK_COUNT (BL1_BYTE_COUNT / SDMMC_BLK_SIZE) +#define BL2_BLK_COUNT (BL2_BYTE_COUNT / SDMMC_BLK_SIZE) +#define ENV_BLK_COUNT (ENV_BYTE_COUNT / SDMMC_BLK_SIZE) + +/* IMAGE OFFSET (BLOCK) */ +#define SBL_BLK_OFFSET (SBL_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define BL1_BLK_OFFSET (BL1_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define BL2_BLK_OFFSET (BL2_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define ENV_BLK_OFFSET (ENV_BYTE_OFFSET / SDMMC_BLK_SIZE) + +/* UART */ +#if defined(CONFIG_SERIAL0) +#define PERIPH_ID_UART PERIPH_ID_UART0 +#elif defined(CONFIG_SERIAL1) +#define PERIPH_ID_UART PERIPH_ID_UART1 +#elif defined(CONFIG_SERIAL2) +#define PERIPH_ID_UART PERIPH_ID_UART2 +#elif defined(CONFIG_SERIAL3) +#define PERIPH_ID_UART PERIPH_ID_UART3 +#endif + +#ifndef __ASSEMBLY__ +void sdelay(unsigned long); +void clock_ctrl_init(void); +void mem_ctrl_init(void); +void tzpc_init(void); +#endif + +#endif /* __SETUP_ORIGEN_QUAD_H */ diff --git a/board/overo/overo.c b/board/overo/overo.c index c6d50a0..a94b85b 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -159,16 +159,30 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = MICRON_V_MCFG_165(256 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() != CPU_OMAP36XX) { + *mcfg = MICRON_V_MCFG_165(256 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = HYNIX_V_MCFG_165(256 << 20); - *ctrla = HYNIX_V_ACTIMA_165; - *ctrlb = HYNIX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() != CPU_OMAP36XX) { + *mcfg = HYNIX_V_MCFG_165(256 << 20); + *ctrla = HYNIX_V_ACTIMA_165; + *ctrlb = HYNIX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + *mcfg = HYNIX_V_MCFG_200(256 << 20); + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } break; default: *mcfg = MICRON_V_MCFG_165(128 << 20); diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 3a885a5..bb95cc8 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -41,7 +41,7 @@ OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) ALL +=$(obj).depend $(LIB) ifdef CONFIG_SPL_BUILD -ALL += $(OBJTREE)/tools/mk$(BOARD)spl +ALL += $(OBJTREE)/tools/mk$(SOC)spl endif all: $(ALL) @@ -50,8 +50,8 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +$(OBJTREE)/tools/mk$(SOC)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(SOC)spl endif ######################################################################### diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 1474fa8..64f8c42 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o SOBJS := lowlevel_init.o +SOBJS += monitor.o COBJS := clock_init.o +COBJS += timer_init.o non_secure.o COBJS += dmc_common.o dmc_init_ddr3.o COBJS += tzpc_init.o COBJS += smdk5250_spl.o @@ -36,6 +38,7 @@ COBJS += smdk5250.o endif ifdef CONFIG_SPL_BUILD +SOBJS += smp.o COBJS += mmc_boot.o endif diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S index bc6cb6f..25e2e68 100644 --- a/board/samsung/smdk5250/lowlevel_init.S +++ b/board/samsung/smdk5250/lowlevel_init.S @@ -32,6 +32,29 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SPL_BUILD + /* check if we're the first cpu or not */ + mrc p15, 0, r0, c0, c0, 5 /* MPIDR */ + and r0, r0, #15 + cmp r0, #0 + beq first_cpu + + /* Secondary CPU */ + bl arch_timer_init + bl non_secure_init + bl monitor_init + bl enter_ns + bl enter_hyp + b enter_smp_pen + + /* + * We entered the SMP pen above, and we expect kernels to write an + * address into the ALIVE SFR SYSFLAGS register thingy at 0x02020000 + * which should not be here, but some kernel secondary entry point. + */ +#endif + +first_cpu: /* use iRAM stack in bl2 */ ldr sp, =CONFIG_IRAM_STACK stmdb r13!, {ip,lr} @@ -55,6 +78,17 @@ lowlevel_init: cmp r1, r2 beq wakeup_reset + /* Init architected timers */ + bl arch_timer_init + + /* Non-secure-init */ + bl non_secure_init + + /*PS-Hold High*/ + ldr r0, =0x1004330c + ldr r1, [r0] + orr r1, r1, #0x100 + str r1, [r0] /* * If U-boot is already running in RAM, no need to relocate U-Boot. * Memory controller must be configured before relocating U-Boot @@ -68,6 +102,8 @@ lowlevel_init: cmp r1, r2 /* compare r1, r2 */ beq 1f /* r0 == r1 then skip sdram init */ + bl read_om + /* init system clock */ bl system_clock_init @@ -76,6 +112,11 @@ lowlevel_init: 1: bl tzpc_init +#ifdef CONFIG_SPL_BUILD + bl smp_kick_secondary /* Bring other CPU1 into smp pen */ +#else + bl monitor_init /* Setup monitor mode */ +#endif ldmia r13!, {ip,pc} wakeup_reset: @@ -94,3 +135,24 @@ exit_wakeup: mov pc, r1 nop nop + +read_om: + /* Read booting information */ + ldr r0, =EXYNOS5_POWER_BASE + ldr r1, [r0,#0x0] /*OMR_OFFSET*/ + bic r2, r1, #0xffffffc1 + + /* SD/MMC BOOT */ + cmp r2, #0x4 + moveq r3, #BOOT_MMCSD + + /* eMMC 4.4 BOOT */ + cmp r2, #0x8 + moveq r3, #BOOT_EMMC_4_4 + cmp r2, #0x28 + moveq r3, #BOOT_EMMC_4_4 + + ldr r0, =(EXYNOS5_POWER_BASE + INFORM3_OFFSET) + str r3, [r0] + + mov pc, lr diff --git a/board/samsung/smdk5250/mmc_boot.c b/board/samsung/smdk5250/mmc_boot.c index 449a919..c0b79eb 100644 --- a/board/samsung/smdk5250/mmc_boot.c +++ b/board/samsung/smdk5250/mmc_boot.c @@ -30,9 +30,18 @@ */ void copy_uboot_to_ram(void) { - u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + u32 (*copy_bl2_from_mmc)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + u32 (*copy_bl2_from_emmc)(u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR_EMMC; + u32 (*copy_bl2_from_emmc_done)() = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR_EMMC_DONE; - copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + u32 inform3 = readl(EXYNOS5_POWER_BASE + INFORM3_OFFSET); + + if (inform3 == BOOT_MMCSD) + copy_bl2_from_mmc(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + else if (inform3 == BOOT_EMMC_4_4) { + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + copy_bl2_from_emmc_done(); + } } void board_init_f(unsigned long bootflag) diff --git a/board/samsung/smdk5250/monitor.S b/board/samsung/smdk5250/monitor.S new file mode 100644 index 0000000..8bc21d8 --- /dev/null +++ b/board/samsung/smdk5250/monitor.S @@ -0,0 +1,97 @@ +/* + * + * Copyright (c) 2012 Christoffer Dall + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.syntax unified +.arch_extension sec +.arch_extension virt +.text + +.align 5 + +/* We use the same vector table for Hyp and Monitor mode, since + * we will only use each once and they don't overlap. + */ +mon_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + b 2f /* smc */ + .word 0 /* pabt */ + .word 0 /* dabt */ + b 1f + .word 0 /* irq */ + .word 0 /* fiq */ + +/* Return directly back to the caller without leaving Hyp mode: */ +1: mrs lr, elr_hyp + mov pc, lr + +/* In monitor mode, set up HVBAR and SCR then return to caller in NS-SVC. */ +2: + mrc p15, 0, r1, c1, c1, 0 @ SCR + /* + * Set SCR.NS=1 (needed for setting HVBAR and also returning to NS state) + * .IRQ,FIQ,EA=0 (don't take aborts/exceptions to Monitor mode) + * .FW,AW=1 (CPSR.A,F modifiable in NS state) + * .nET=0 (early termination OK) + * .SCD=0 (SMC in NS mode OK, so we can call secure firmware) + * .HCE=1 (HVC does Hyp call) + */ + bic r1, r1, #0x07f + ldr r2, =0x131 + orr r1, r1, r2 + mcr p15, 0, r2, c1, c1, 0 @ SCR + isb + ldr r2, =mon_vectors + mcr p15, 4, r2, c12, c0, 0 @ set HVBAR + /* ...and return to calling code in NS state */ + movs pc, lr + +/****************************************************************************** + * This code is called from u-boot into the above handler + */ + + .globl monitor_init +monitor_init: + ldr ip, =mon_vectors + mcr p15, 0, ip, c12, c0, 1 @ Monitor vector base address + mov pc, lr + + /* Try to go into NS-SVC: void enter_ns(void); */ + .globl enter_ns +enter_ns: + smc #0 + mov pc, lr + + /* void enter_hyp(void); */ + .globl enter_hyp +enter_hyp: + /* Now we're in NS-SVC, make a Hyp call to get into Hyp mode */ + mov r0, lr + mov r1, sp + hvc #0 + /* We will end up here in NS-Hyp. */ + mov sp, r1 + mov pc, r0 diff --git a/board/samsung/smdk5250/non_secure.c b/board/samsung/smdk5250/non_secure.c new file mode 100644 index 0000000..e46b6f8 --- /dev/null +++ b/board/samsung/smdk5250/non_secure.c @@ -0,0 +1,96 @@ + +/* + * Architected Timer setup for SMDK5250 board based on EXYNOS5 + * + * Copyright (C) 2012 Christoffer Dall + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include "setup.h" + +#define ARM_GICV2_DIST_CTRL 0x00 +#define ARM_GICV2_DIST_TYPE 0x04 +#define ARM_GICV2_DIST_SEC_REG 0x80 + +#define ARM_GICV2_CPU_CTRL 0x00 + +#define ARM_GICV2_ICCPMR 0x04 + +static unsigned long read_mpidr(void) +{ + unsigned long val; + asm volatile("mrc p15, 0, %0, c0, c0, 5": "=r" (val)); + return val; +} + +static unsigned long read_nsacr(void) +{ + unsigned long val; + asm volatile("mrc p15, 0, %0, c1, c1, 2": "=r" (val)); + return val; +} + +static void write_nsacr(unsigned long val) +{ + asm volatile("mcr p15, 0, %0, c1, c1, 2": : "r" (val)); +} + +void non_secure_init(void) +{ + unsigned long addr, type, num_regs; + unsigned long nsacr, ctrl; + int i; + + addr = EXYNOS5_GIC_DIST_BASE; + type = readl(addr + ARM_GICV2_DIST_TYPE); + num_regs = (type & 0x1f) + 1; + + /* Set all interrupts to be non-secure */ + addr = EXYNOS5_GIC_DIST_BASE + ARM_GICV2_DIST_SEC_REG; + for (i = 0; i < num_regs; i++) { + writel(0xffffffff, addr); + addr += 4; + } + + /* Set GIC priority mask bit [7] = 1 */ + addr = EXYNOS5_GIC_CPU_BASE; + writel(0x80, addr + ARM_GICV2_ICCPMR); + + /* Set NSACR to allow coprocessor access from non-secure */ + nsacr = read_nsacr(); + nsacr |= 0x43fff; + write_nsacr(nsacr); + + /* Enable group 1 interrupts on CPU interface */ + addr = EXYNOS5_GIC_CPU_BASE + ARM_GICV2_CPU_CTRL; + ctrl = readl(addr); + writel(ctrl | 0x1, addr); + + /* Disable group 0 interrupts and enable group 1 interrupts on Dist */ + addr = EXYNOS5_GIC_DIST_BASE + ARM_GICV2_DIST_CTRL; + ctrl = readl(addr); + ctrl = (ctrl & ~0x1) | 0x2; + writel(ctrl | 0x1, addr); +} diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index a159601..bb8e971 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -591,4 +591,6 @@ void sdelay(unsigned long); void mem_ctrl_init(void); void system_clock_init(void); void tzpc_init(void); +void enter_ns(void); +void enter_hyp(void); #endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index a5816e4..28cf0af 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,10 +26,13 @@ #include #include #include -#include +#include #include #include +#include "setup.h" + +unsigned int OmPin; DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SMC911X @@ -63,6 +66,18 @@ static int smc9115_pre_init(void) int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + + OmPin = readl(EXYNOS5_POWER_BASE + INFORM3_OFFSET); + + printf("\nChecking Boot Mode ..."); + if (OmPin == BOOT_MMCSD) { + printf(" SDMMC\n"); + } else if (OmPin == BOOT_EMMC_4_4) { + printf(" EMMC4.41\n"); + } else { + printf(" Please check OM_pin\n"); + } + return 0; } @@ -120,7 +135,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - printf("\nBoard: SMDK5250\n"); + printf("\nBoard: %s\n",CONFIG_IDENT_STRING); return 0; } @@ -137,7 +152,22 @@ int board_mmc_init(bd_t *bis) return err; } - err = s5p_mmc_init(0, 8); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; + } + + if (OmPin == BOOT_EMMC_4_4) { + err = exynos_dwmmc_init(0, 8); + err = exynos_dwmmc_init(2, 4); + } else { + err = exynos_dwmmc_init(2, 4); + err = exynos_dwmmc_init(0, 8); + } + + err = exynos_dwmmc_init(0, 8); + return err; } #endif @@ -191,6 +221,32 @@ static int board_i2c_init(void) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int i; + uchar mac[6]; + unsigned int guid_high = readl(EXYNOS5_GUID_HIGH); + unsigned int guid_low = readl(EXYNOS5_GUID_LOW); + + for (i = 0; i < 2; i++) + mac[i] = (guid_high >> (8 * (1 - i))) & 0xFF; + + for (i = 0; i < 4; i++) + mac[i+2] = (guid_low >> (8 * (3 - i))) & 0xFF; + + /* mark it as not multicast and outside official 80211 MAC namespace */ + mac[0] = (mac[0] & ~0x1) | 0x2; + + eth_setenv_enetaddr("ethaddr", mac); + eth_setenv_enetaddr("usbethaddr", mac); + +#ifdef CONFIG_PREBOOT + setenv("preboot", CONFIG_PREBOOT); +#endif +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { @@ -206,3 +262,24 @@ int board_early_init_f(void) return err; } #endif + +void arch_preboot_os(void) +{ + /* + * We should now long be done with accessing any peripherals or + * setting up any other hardware state that needs to be set up from + * the secure mode (TrustZone), so we can switch to non-secure mode + * and we rely on board-specific logic to put a board-specific monitor + * in place for stuff like L2 cache maintenance and power management. + */ + enter_ns(); + + /* + * Enter Hyp mode immediately before booting the kernel to allow + * the first Linux kernel access to and control of Hyp mode so that + * modules like KVM can run VMs. + * + * Without further ado... + */ + enter_hyp(); +} diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c index 1d453ca..1f0ce72 100644 --- a/board/samsung/smdk5250/smdk5250_spl.c +++ b/board/samsung/smdk5250/smdk5250_spl.c @@ -49,8 +49,8 @@ static struct spl_machine_param machine_param .uboot_size = 0x100000, .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1700, + .frequency_mhz = CONFIG_BUS_CLK_FREQ, + .arm_freq_mhz = CONFIG_ARM_CLK_FREQ, .serial_base = 0x12c30000, .i2c_base = 0x12c60000, .mem_manuf = MEM_MANUF_SAMSUNG, diff --git a/board/samsung/smdk5250/smp.S b/board/samsung/smdk5250/smp.S new file mode 100644 index 0000000..998d2ab --- /dev/null +++ b/board/samsung/smdk5250/smp.S @@ -0,0 +1,69 @@ +/* + * + * Copyright (c) 2012 Christoffer Dall + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +__smp_pen: + wfe + ldr r1, [r0] + mov pc, r1 + + .globl enter_smp_pen +enter_smp_pen: + adr r1, __smp_pen + ldmia r1, {r4, r5, r6} + ldr r2, =CONFIG_SPL_SMP_PEN + stmia r2, {r4, r5, r6} + + /* + * Store SMP pen into SYSFLAGS so the processor stays in the loop if + * it gets a spurious interrupt + */ + ldr r0, =CONFIG_SYSFLAGS_ADDR + str r2, [r0] + + /* + * Make instruction copy coherent + */ + mcr p15, 0, r2, c7, c11, 1 /* Clean the data cache by MVA*/ + mov r10, #0 + mcr p15, 0, r10, c7, c5, 0 /* Invalidate the I-cache */ + isb /* Make sure the invalidate ops are complete */ + dsb + + mov pc, r2 + + .globl smp_kick_secondary +smp_kick_secondary: + /* Bring up the secondary CPU */ + ldr r0, =CONFIG_SYSFLAGS_ADDR + ldr r1, =CONFIG_SPL_TEXT_BASE + str r1, [r0] + dsb + ldr r0, =(EXYNOS5_GIC_DIST_BASE + 0xf00) /* GICD_SGIR */ + ldr r1, =(2 << 16) /* Bring up CPU 1*/ + str r1, [r0] + dsb + + mov pc, lr diff --git a/board/samsung/smdk5250/timer_init.c b/board/samsung/smdk5250/timer_init.c new file mode 100644 index 0000000..cf90177 --- /dev/null +++ b/board/samsung/smdk5250/timer_init.c @@ -0,0 +1,45 @@ +/* + * Architected Timer setup for SMDK5250 board based on EXYNOS5 + * + * Copyright (C) 2012 Christoffer Dall + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "setup.h" + +void arch_timer_init(void) +{ + unsigned long cpuid, freq; + asm volatile("mrc p15, 0, %[cpuid], c0, c1, 1": + [cpuid] "=r" (cpuid)); + + if ((cpuid >> 16) & 1) { + freq = 24000000; + asm volatile("mcr p15, 0, %[freq], c14, c0, 0" : : + [freq] "r" (freq)); + } +} diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index 56e0c16..c2f344e 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -40,7 +40,7 @@ OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) ALL := $(obj).depend $(LIB) ifdef CONFIG_SPL_BUILD -ALL += $(OBJTREE)/tools/mk$(BOARD)spl +ALL += $(OBJTREE)/tools/mk$(SOC)spl endif all: $(ALL) @@ -49,8 +49,8 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +$(OBJTREE)/tools/mk$(SOC)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(SOC)spl endif ######################################################################### diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index e11a892..d5c681c 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -93,7 +94,9 @@ void i2c_init_board(void) int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; } @@ -104,6 +107,10 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; } static unsigned int get_hw_revision(void) @@ -151,54 +158,22 @@ int board_mmc_init(bd_t *bis) { struct exynos4_gpio_part2 *gpio = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i, err; + int err; /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio->k0, 2, 1); s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); - /* GPK0[0:6] pull disable */ - s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); - /* GPK0[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); - } - - for (i = 3; i < 7; i++) { - /* GPK1[3:6] special function 3 */ - s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); - /* GPK1[3:6] pull disable */ - s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); - /* GPK1[3:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); - } - - /* * MMC device init * mmc0 : eMMC (8-bit buswidth) * mmc2 : SD card (4-bit buswidth) */ - err = s5p_mmc_init(0, 8); + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) + debug("SDMMC0 not configured\n"); + else + err = s5p_mmc_init(0, 8); /* T-flash detect */ s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); @@ -209,24 +184,11 @@ int board_mmc_init(bd_t *bis) * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio->x3, 4)) { - /* - * SD card GPIO: - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn -> Not used - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); - /* GPK2[0:6] pull disable */ - s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); - } - err = s5p_mmc_init(2, 4); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) + debug("SDMMC2 not configured\n"); + else + err = s5p_mmc_init(2, 4); } return err; @@ -359,6 +321,10 @@ static void board_power_init(void) writel(0, (unsigned int)&pwr->lcd1_configuration); writel(0, (unsigned int)&pwr->gps_configuration); writel(0, (unsigned int)&pwr->gps_alive_configuration); + + /* It is necessary to power down core 1 */ + /* to successfully boot CPU1 in kernel */ + writel(0, (unsigned int)&pwr->arm_core1_configuration); } static void board_uart_init(void) diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile index bfec08f..587cc1b 100644 --- a/board/samsung/universal_c210/Makefile +++ b/board/samsung/universal_c210/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o COBJS-y := universal.o onenand.o -SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S deleted file mode 100644 index dc7f69e..0000000 --- a/board/samsung/universal_c210/lowlevel_init.S +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Lowlevel setup for universal board based on EXYNOS4210 - * - * Copyright (C) 2010 Samsung Electronics - * Kyungmin Park - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * Register usages: - * - * r5 has zero always - * r7 has GPIO part1 base 0x11400000 - * r6 has GPIO part2 base 0x11000000 - */ - - .globl lowlevel_init -lowlevel_init: - mov r11, lr - - /* r5 has always zero */ - mov r5, #0 - - ldr r7, =EXYNOS4_GPIO_PART1_BASE - ldr r6, =EXYNOS4_GPIO_PART2_BASE - - /* System Timer */ - ldr r0, =EXYNOS4_SYSTIMER_BASE - ldr r1, =0x5000 - str r1, [r0, #0x0] - ldr r1, =0xffffffff - str r1, [r0, #0x8] - ldr r1, =0x49 - str r1, [r0, #0x4] - - /* PMIC manual reset */ - /* nPOWER: XEINT_23: GPX2[7] */ - add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) @ Output - str r1, [r0, #0x0] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - /* init system clock */ - bl system_clock_init - - /* Disable Watchdog */ - ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000 - str r5, [r0] - - /* UART */ - bl uart_asm_init - - /* PMU init */ - bl system_power_init - - bl tzpc_init - - mov lr, r11 - mov pc, lr - nop - nop - nop - -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* - * setup UART0-UART4 GPIOs (part1) - * GPA1CON[3] = I2C_3_SCL (3) - * GPA1CON[2] = I2C_3_SDA (3) - */ - mov r0, r7 - ldr r1, =0x22222222 - str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET - ldr r1, =0x00223322 - str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET - - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) - str r1, [r0, #0x0] - - ldr r1, [r0, #0x8] - bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit - orr r1, r1, #(0x3 << 14) @ Pull-up enabled - str r1, [r0, #0x8] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - mov pc, lr - nop - nop - nop - -system_clock_init: - ldr r0, =EXYNOS4_CLOCK_BASE - - /* APLL(1), MPLL(1), CORE(0), HPM(0) */ - ldr r1, =0x0101 - ldr r2, =0x14200 @ CLK_SRC_CPU - str r1, [r0, r2] - - /* wait ?us */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* - * CLK_SRC_TOP0 - * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166 - * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL - * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL - */ - ldr r1, =0x10000110 - ldr r2, =0x0C210 @ CLK_SRC_TOP - str r1, [r0, r2] - - /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ - ldr r1, =0x0066666 - ldr r2, =0x0C240 @ CLK_SRC_FSYS - str r1, [r0, r2] - /* UART[0:5], PWM: SCLKMPLL(6) */ - ldr r1, =0x6666666 - ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET - str r1, [r0, r2] - - /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ - ldr r1, =0x0133730 - ldr r2, =0x14500 @ CLK_DIV_CPU0 - str r1, [r0, r2] - /* CPU1: COPY, HPM */ - ldr r1, =0x03 - ldr r2, =0x14504 @ CLK_DIV_CPU1 - str r1, [r0, r2] - /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ - ldr r1, =0x13111113 - ldr r2, =0x10500 @ CLK_DIV_DMC0 - str r1, [r0, r2] - /* DMC1: PWI, DVSEM, DPM */ - ldr r1, =0x01010100 - ldr r2, =0x10504 @ CLK_DIV_DMC1 - str r1, [r0, r2] - /* LEFTBUS: GDL, GPL */ - ldr r1, =0x13 - ldr r2, =0x04500 @ CLK_DIV_LEFTBUS - str r1, [r0, r2] - /* RIGHHTBUS: GDR, GPR */ - ldr r1, =0x13 - ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS - str r1, [r0, r2] - /* - * CLK_DIV_TOP - * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1) - * ACLK_200, ACLK_100, ACLK_160, ACLK_133, - */ - ldr r1, =0x00005473 - ldr r2, =0x0C510 @ CLK_DIV_TOP - str r1, [r0, r2] - /* MMC[0:1] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C544 @ CLK_DIV_FSYS1 - str r1, [r0, r2] - /* MMC[2:3] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C548 @ CLK_DIV_FSYS2 - str r1, [r0, r2] - /* MMC4 */ - ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C54C @ CLK_DIV_FSYS3 - str r1, [r0, r2] - /* UART[0:5] */ - ldr r1, =0x774777 - ldr r2, =0x0C550 @ CLK_DIV_PERIL0 - str r1, [r0, r2] - /* SLIMBUS: ???, PWM */ - ldr r1, =0x8 - ldr r2, =0x0C55C @ CLK_DIV_PERIL3 - str r1, [r0, r2] - - /* PLL Setting */ - ldr r1, =0x1C20 - ldr r2, =0x14000 @ APLL_LOCK - str r1, [r0, r2] - ldr r2, =0x14008 @ MPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C010 @ EPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C020 @ VPLL_LOCK - str r1, [r0, r2] - - /* APLL */ - ldr r1, =0x8000001c - ldr r2, =0x14104 @ APLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14100 @ APLL_CON0 - str r1, [r0, r2] - /* MPLL */ - ldr r1, =0x8000001C - ldr r2, =0x1410C @ MPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14108 @ MPLL_CON0 - str r1, [r0, r2] - /* EPLL */ - ldr r1, =0x0 - ldr r2, =0x0C114 @ EPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80300302 @ 96MHz - ldr r2, =0x0C110 @ EPLL_CON0 - str r1, [r0, r2] - /* VPLL */ - ldr r1, =0x11000400 - ldr r2, =0x0C124 @ VPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80350302 @ 108MHz - ldr r2, =0x0C120 @ VPLL_CON0 - str r1, [r0, r2] - - /* - * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 - * Turn off all - */ - ldr r1, =0xFFF80000 - ldr r2, =0x0C920 @ CLK_GATE_IP_CAM - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C924 @ CLK_GATE_IP_VP - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFE0 - ldr r2, =0x0C928 @ CLK_GATE_IP_MFC - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C92C @ CLK_GATE_IP_G3D - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFC00 - ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE - str r1, [r0, r2] - - /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ - ldr r1, =0xFFFFFFF1 - ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0 - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1 - str r1, [r0, r2] - - /* - * SMMUPCIE[18], NFCON[16] : 1111 1010 - * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 - * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 - */ - ldr r1, =0xFFFAB8A3 - ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C94C @ CLK_GATE_IP_GPS - str r1, [r0, r2] - - /* - * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 - * I2C2[8] : 1111 1110 - */ - ldr r1, =0xF1FFFEFF - ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL - str r1, [r0, r2] - - /* - * KEYIF[16] : 1111 1110 - */ - ldr r1, =0xFFFEFFFF - ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR - str r1, [r0, r2] - - /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ - ldr r1, =0xFFFFFFD1 - ldr r2, =0x0C970 @ CLK_GATE_BLOCK - str r1, [r0, r2] - mov pc, lr - nop - nop - nop - -system_power_init: - ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000 - - ldr r2, =0x330C @ PS_HOLD_CONTROL - ldr r1, [r0, r2] - orr r1, r1, #(0x3 << 8) @ Data High, Output En - str r1, [r0, r2] - - /* Power Down */ - add r2, r0, #0x3000 - str r5, [r2, #0xC20] @ TV_CONFIGURATION - str r5, [r2, #0xC40] @ MFC_CONFIGURATION - str r5, [r2, #0xC60] @ G3D_CONFIGURATION - str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION - str r5, [r2, #0xCE0] @ GPS_CONFIGURATION - - mov pc, lr - nop - nop - nop - -tzpc_init: - ldr r0, =0x10110000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10120000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10130000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10140000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10150000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - mov pc, lr diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 90fff5c..ded97ca 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,10 +27,12 @@ #include #include #include +#include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -177,7 +179,7 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; + int err; switch (get_hwrev()) { case 0: @@ -200,75 +202,30 @@ int board_mmc_init(bd_t *bis) } /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) + * MMC device init + * mmc0 : eMMC (8-bit buswidth) + * mmc2 : SD card (4-bit buswidth) */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); - /* GPK0[0:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); - /* GPK0[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); - } - - for (i = 3; i < 7; i++) { - /* GPK1[3:6] special function 3 */ - s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); - /* GPK1[3:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); - /* GPK1[3:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); - } + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) + debug("SDMMC0 not configured\n"); + else + err = s5p_mmc_init(0, 8); /* T-flash detect */ s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = s5p_mmc_init(0, 8); - - /* * Check the T-flash detect pin * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - /* - * SD card GPIO: - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn -> Not used - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); - /* GPK2[0:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - } - err = s5p_mmc_init(2, 4); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) + debug("SDMMC2 not configured\n"); + else + err = s5p_mmc_init(2, 4); } return err; @@ -320,3 +277,10 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_flags = PHY0_SLEEP, }; #endif + +int board_early_init_f(void) +{ + wdt_stop(); + + return 0; +} diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6175e1d..4e80d64 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -100,6 +100,29 @@ int board_init(void) } /* + * Beagle-xM has a usb nic with no ethernet rom so generate a macaddr + * from the SOC die-id and set the usbethaddr env var to that + * value. + */ +int board_eth_init(bd_t *bis) +{ + u8 macaddr[6]; + char usbethaddr[20]; + + /* + * NB: The 1 here has been found to generate an address + * consistent with the kernel. + */ + omap3_die_id_to_ethernet_mac(macaddr, 1); + sprintf (usbethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + macaddr[0], macaddr[1], + macaddr[2], macaddr[3], + macaddr[4], macaddr[5]) ; + setenv ("usbethaddr", usbethaddr); + return 0; +} + +/* * Routine: get_board_revision * Description: Detect if we are running on a Beagle revision Ax/Bx, * C1/2/3, C4 or xM. This can be done by reading diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 4feef78..20be81c 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -61,8 +61,27 @@ int board_init(void) return 0; } +/* + * Panda has a usb nic with no ethernet rom so generate a macaddr + * from the SOC die-id and set the usbethaddr env var to that + * value. + */ int board_eth_init(bd_t *bis) { + u8 macaddr[6]; + char usbethaddr[20]; + + /* + * NB: The 1 here has been found to generate an address + * consistent with the kernel. + */ + omap4_die_id_to_ethernet_mac(macaddr, 1); + sprintf (usbethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + macaddr[0], macaddr[1], + macaddr[2], macaddr[3], + macaddr[4], macaddr[5]) ; + setenv ("usbethaddr", usbethaddr); + return 0; } diff --git a/boards.cfg b/boards.cfg index 0ecd1b8..4cd5c2e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -224,7 +224,8 @@ versatilepb arm arm926ejs versatile armltd versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES -ca9x4_ct_vxp arm armv7 vexpress armltd +vexpress_ca5x2 arm armv7 vexpress armltd +vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg @@ -265,6 +266,7 @@ mcx arm armv7 mcx htkw tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 +omap4_panda_splusb arm armv7 panda ti omap4 omap4_panda:SPL_USB omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 s5p_goni arm armv7 goni samsung s5pc1xx @@ -272,7 +274,9 @@ smdkc100 arm armv7 smdkc100 samsung origen arm armv7 origen samsung exynos s5pc210_universal arm armv7 universal_c210 samsung exynos smdk5250 arm armv7 smdk5250 samsung exynos +arndale5250 arm armv7 smdk5250 samsung exynos arndale5250:ARNDALE5250 smdkv310 arm armv7 smdkv310 samsung exynos +origen_quad arm armv7 origen_quad insignal exynos trats arm armv7 trats samsung exynos harmony arm armv7:arm720t harmony nvidia tegra20 seaboard arm armv7:arm720t seaboard nvidia tegra20 diff --git a/build_flash/FWL1 b/build_flash/FWL1 new file mode 100644 index 0000000..f4f2ddc Binary files /dev/null and b/build_flash/FWL1 differ diff --git a/build_flash/README b/build_flash/README new file mode 100644 index 0000000..62bc856 --- /dev/null +++ b/build_flash/README @@ -0,0 +1,14 @@ +This Directory contains the following files: + +build.sh: Utility to build and flash the boar specific u-boot images + +export.sh: Utility to export the build environment. Please update the + correct tool-chain path in this file. + +FWL1: First 8K firmware for the needed for the emdkv310 EVT1 boards. + +NOTE****** +Please keep this directory in the TOPDIR(U-Boot-source). +e.g. if u-boot source lies in a/u-boot-samsung + place this directory at a/u-boot-samsung + diff --git a/build_flash/build.sh b/build_flash/build.sh new file mode 100755 index 0000000..353dc5a --- /dev/null +++ b/build_flash/build.sh @@ -0,0 +1,55 @@ +#!/bin/sh + +. ./export.sh; +cd ..; +case $1 in + -h) clear; + echo "This is a automated tool to build and flash" + echo "ORIGEN and SMDKV310(EVT0|EVT1) boards" + echo""; + echo "-b: Build Image"; + echo "-f: Flash Image"; + echo "-h: Show Help"; + echo "-v: Show Version"; + echo""; + echo "examples:" + echo "Build image: \$ build.sh -b origen|smdkv310"; + echo""; + echo "Flash image: \$ build.sh -f origen|smdkv310|smdkv310_evt1"; + echo""; + echo"";; + + -v) clear; + echo "Version 1.0"; + echo ""; + echo "Written By: Chander kashyap"; + echo "";; + + -b) make distclean; + + case $2 in + smdkv310 | smdkv310_evt1) + make smdkv310_config;; + + origen) + make origen_config;; + esac + make -j8;; + + -f) umount /media/*; + + case $2 in + smdkv310) + sudo dd if=spl/smdkv310-spl.bin of=/dev/sdc bs=512 count=32 seek=1; + sudo dd if=u-boot.bin of=/dev/sdc bs=512 count=1024 seek=65;; + + origen) + sudo dd if=spl/origen-spl.bin of=/dev/sdc bs=512 count=32 seek=1; + sudo dd if=u-boot.bin of=/dev/sdc bs=512 count=1024 seek=65 ;; + smdkv310_evt1) + cd -;sudo dd if=FWL1 of=/dev/sdc bs=512 count=16 seek=1;cd -; + sudo dd if=spl/smdkv310-spl.bin of=/dev/sdc bs=512 count=32 seek=17; + sudo dd if=u-boot.bin of=/dev/sdc bs=512 count=1024 seek=49;; + esac +esac +cd -; diff --git a/build_flash/export.sh b/build_flash/export.sh new file mode 100644 index 0000000..afe5af3 --- /dev/null +++ b/build_flash/export.sh @@ -0,0 +1,2 @@ +export ARCH=arm +export CROSS_COMPILE=/opt/linaro-gcc-4.5-arm-linux-gnueabi-32bit/bin/arm-linux-gnueabi- diff --git a/common/Makefile b/common/Makefile index 9e43322..910a80e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)libcommon.o # core ifndef CONFIG_SPL_BUILD COBJS-y += main.o +COBJS-$(CONFIG_S3C_USBD) += cmd_usbd.o COBJS-y += command.o COBJS-y += exports.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index d256ddf..7181634 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -579,6 +579,33 @@ static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, return ret; } +#ifdef CONFIG_BOOTM_BOOTARGS_APPEND_MAC +static void append_mac_addr() +{ + char *bootarg, *ethaddr; + size_t bootarg_len, ethaddr_len; + + ethaddr = getenv("ethaddr"); + + if (!ethaddr) + ethaddr = getenv("usbethaddr"); + + if (!ethaddr) + return; + + ethaddr_len = strlen(ethaddr); + + bootarg_len = strlen(getenv("bootargs")) + ethaddr_len + 6; + + bootarg = malloc(bootarg_len); + if (!bootarg) + return; + + sprintf(bootarg, "%s mac=%s", getenv("bootargs"), ethaddr); + setenv("bootargs", bootarg); +} +#endif + /*******************************************************************/ /* bootm - boot application image from image in memory */ /*******************************************************************/ @@ -602,6 +629,9 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif +#ifdef CONFIG_BOOTM_BOOTARGS_APPEND_MAC + append_mac_addr(); +#endif /* determine if we have a sub command */ if (argc > 1) { char *endp; @@ -1601,7 +1631,7 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } -static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { bootm_headers_t images; diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 62a1c22..c50b6d3 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -199,7 +199,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mmc_devices('\n'); return 0; } else if (strcmp(argv[1], "dev") == 0) { - int dev, part = -1; + int dev, part = -1, bootable = 0; struct mmc *mmc; if (argc == 2) @@ -214,6 +214,19 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) " than %d\n", PART_ACCESS_MASK); return 1; } + } else if (argc == 5) { + dev = (int)simple_strtoul(argv[2], NULL, 10); + part = (int)simple_strtoul(argv[3], NULL, 10); + if (part > PART_ACCESS_MASK) { + printf("#part_num shouldn't be larger" + " than %d\n", PART_ACCESS_MASK); + return 1; + } + bootable = (int)simple_strtoul(argv[4], NULL, 10); + if (bootable < 0 || bootable > 1) { + printf("bootable is boolean variable \n"); + return 1; + } } else return CMD_RET_USAGE; @@ -231,7 +244,14 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - if (part != mmc->part_num) { + if (bootable) { + ret = mmc_part_bootenable(dev, part); + if (!ret) + mmc->part_num = part; + printf("partions #%d, made bootable %s\n", + part, (!ret) ? "OK" : "ERROR"); + + } else if (part != mmc->part_num) { ret = mmc_switch_part(dev, part); if (!ret) mmc->part_num = part; @@ -317,6 +337,6 @@ U_BOOT_CMD( "mmc erase blk# cnt\n" "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" - "mmc dev [dev] [part] - show or set current mmc device [partition]\n" + "mmc dev [dev] [part] [bootable]- show or set current mmc device [partition] [bootable]\n" "mmc list - lists available devices"); #endif diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index ee75db9..9f1c14d 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -26,12 +26,19 @@ #define MAX_TFTP_PATH_LEN 127 +const char *pxe_default_paths[] = { + "default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC, + "default-" CONFIG_SYS_ARCH, + "default", + NULL +}; + /* * Like getenv, but prints an error if envvar isn't defined in the * environment. It always returns what getenv does, so it can be used in * place of getenv without changing error handling otherwise. */ -static char *from_env(char *envvar) +static char *from_env(const char *envvar) { char *ret; @@ -61,6 +68,9 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len) ethaddr = from_env("ethaddr"); if (!ethaddr) + ethaddr = from_env("usbethaddr"); + + if (!ethaddr) return -ENOENT; ethaddr_len = strlen(ethaddr); @@ -131,14 +141,14 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, return 1; } -static int (*do_getfile)(char *file_path, char *file_addr); +static int (*do_getfile)(const char *file_path, char *file_addr); -static int do_get_tftp(char *file_path, char *file_addr) +static int do_get_tftp(const char *file_path, char *file_addr) { char *tftp_argv[] = {"tftp", NULL, NULL, NULL}; tftp_argv[1] = file_addr; - tftp_argv[2] = file_path; + tftp_argv[2] = (void *)file_path; if (do_tftpb(NULL, 0, 3, tftp_argv)) return -ENOENT; @@ -148,12 +158,12 @@ static int do_get_tftp(char *file_path, char *file_addr) static char *fs_argv[5]; -static int do_get_ext2(char *file_path, char *file_addr) +static int do_get_ext2(const char *file_path, char *file_addr) { #ifdef CONFIG_CMD_EXT2 fs_argv[0] = "ext2load"; fs_argv[3] = file_addr; - fs_argv[4] = file_path; + fs_argv[4] = (void *)file_path; if (!do_ext2load(NULL, 0, 5, fs_argv)) return 1; @@ -161,12 +171,12 @@ static int do_get_ext2(char *file_path, char *file_addr) return -ENOENT; } -static int do_get_fat(char *file_path, char *file_addr) +static int do_get_fat(const char *file_path, char *file_addr) { #ifdef CONFIG_CMD_FAT fs_argv[0] = "fatload"; fs_argv[3] = file_addr; - fs_argv[4] = file_path; + fs_argv[4] = (void *)file_path; if (!do_fat_fsload(NULL, 0, 5, fs_argv)) return 1; @@ -182,7 +192,7 @@ static int do_get_fat(char *file_path, char *file_addr) * * Returns 1 for success, or < 0 on error. */ -static int get_relfile(char *file_path, void *file_addr) +static int get_relfile(const char *file_path, void *file_addr) { size_t path_len; char relfile[MAX_TFTP_PATH_LEN+1]; @@ -221,7 +231,7 @@ static int get_relfile(char *file_path, void *file_addr) * * Returns 1 on success, or < 0 for error. */ -static int get_pxe_file(char *file_path, void *file_addr) +static int get_pxe_file(const char *file_path, void *file_addr) { unsigned long config_file_size; char *tftp_filesize; @@ -258,7 +268,7 @@ static int get_pxe_file(char *file_path, void *file_addr) * * Returns 1 on success or < 0 on error. */ -static int get_pxelinux_path(char *file, void *pxefile_addr_r) +static int get_pxelinux_path(const char *file, void *pxefile_addr_r) { size_t base_len = strlen(PXELINUX_DIR); char path[MAX_TFTP_PATH_LEN+1]; @@ -355,7 +365,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *pxefile_addr_str; unsigned long pxefile_addr_r; - int err; + int err, i = 0; do_getfile = do_get_tftp; @@ -378,14 +388,21 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ if (pxe_uuid_path((void *)pxefile_addr_r) > 0 || pxe_mac_path((void *)pxefile_addr_r) > 0 - || pxe_ipaddr_paths((void *)pxefile_addr_r) > 0 - || get_pxelinux_path("default", (void *)pxefile_addr_r) > 0) { + || pxe_ipaddr_paths((void *)pxefile_addr_r) > 0) { printf("Config file found\n"); return 0; } + while (pxe_default_paths[i]) { + if (get_pxelinux_path(pxe_default_paths[i], (void *)pxefile_addr_r) > 0) { + printf("Config file found\n"); + return 0; + } + i++; + } + printf("Config file not found\n"); return 1; @@ -398,7 +415,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * * Returns 1 on success or < 0 on error. */ -static int get_relfile_envaddr(char *file_path, char *envaddr_name) +static int get_relfile_envaddr(const char *file_path, const char *envaddr_name) { unsigned long file_addr; char *envaddr; @@ -445,14 +462,17 @@ static int get_relfile_envaddr(char *file_path, char *envaddr_name) * list - lets these form a list, which a pxe_menu struct will hold. */ struct pxe_label { + char num[4]; char *name; char *menu; char *kernel; char *append; char *initrd; char *fdt; + int ipappend; int attempted; int localboot; + int localboot_val; struct list_head list; }; @@ -533,21 +553,9 @@ static void label_destroy(struct pxe_label *label) static void label_print(void *data) { struct pxe_label *label = data; - const char *c = label->menu ? label->menu : label->kernel; - - printf("%s:\t%s\n", label->name, c); - - if (label->kernel) - printf("\t\tkernel: %s\n", label->kernel); - - if (label->append) - printf("\t\tappend: %s\n", label->append); + const char *c = label->menu ? label->menu : label->name; - if (label->initrd) - printf("\t\tinitrd: %s\n", label->initrd); - - if (label->fdt) - printf("\tfdt: %s\n", label->fdt); + printf("%s:\t%s\n", label->num, c); } /* @@ -591,34 +599,43 @@ static int label_localboot(struct pxe_label *label) * If the label specifies an 'append' line, its contents will overwrite that * of the 'bootargs' environment variable. */ -static void label_boot(struct pxe_label *label) +static int label_boot(struct pxe_label *label) { char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL }; + char initrd_str[22]; + char mac_str[29] = ""; + char ip_str[68] = ""; + char *bootargs; int bootm_argc = 3; + int len = 0; label_print(label); label->attempted = 1; if (label->localboot) { - label_localboot(label); - return; + if (label->localboot_val >= 0) + label_localboot(label); + return 0; } if (label->kernel == NULL) { printf("No kernel given, skipping %s\n", label->name); - return; + return 1; } if (label->initrd) { if (get_relfile_envaddr(label->initrd, "ramdisk_addr_r") < 0) { printf("Skipping %s for failure retrieving initrd\n", label->name); - return; + return 1; } - bootm_argv[2] = getenv("ramdisk_addr_r"); + bootm_argv[2] = initrd_str; + strcpy(bootm_argv[2], getenv("ramdisk_addr_r")); + strcat(bootm_argv[2], ":"); + strcat(bootm_argv[2], getenv("filesize")); } else { bootm_argv[2] = "-"; } @@ -626,11 +643,43 @@ static void label_boot(struct pxe_label *label) if (get_relfile_envaddr(label->kernel, "kernel_addr_r") < 0) { printf("Skipping %s for failure retrieving kernel\n", label->name); - return; + return 1; + } + + if (label->ipappend & 0x1) { + sprintf(ip_str, " ip=%s:%s:%s:%s", + getenv("ipaddr"), getenv("serverip"), + getenv("gatewayip"), getenv("netmask")); + len += strlen(ip_str); + } + + if (label->ipappend & 0x2) { + int err; + strcpy(mac_str, " BOOTIF="); + err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8); + if (err < 0) + mac_str[0] = '\0'; + len += strlen(mac_str); } if (label->append) - setenv("bootargs", label->append); + len += strlen(label->append); + + if (len) { + bootargs = malloc(len + 1); + if (!bootargs) + return 1; + bootargs[0] ='\0'; + if (label->append) + strcpy(bootargs, label->append); + strcat(bootargs, ip_str); + strcat(bootargs, mac_str); + + setenv("bootargs", bootargs); + printf("append: %s\n", bootargs); + + free(bootargs); + } bootm_argv[1] = getenv("kernel_addr_r"); @@ -662,7 +711,12 @@ static void label_boot(struct pxe_label *label) if (bootm_argv[3]) bootm_argc = 4; +#ifdef CONFIG_CMD_BOOTZ + do_bootz(NULL, 0, bootm_argc, bootm_argv); +#else do_bootm(NULL, 0, bootm_argc, bootm_argv); +#endif + return 1; } /* @@ -685,6 +739,8 @@ enum token_type { T_PROMPT, T_INCLUDE, T_FDT, + T_ONTIMEOUT, + T_IPAPPEND, T_INVALID }; @@ -713,6 +769,8 @@ static const struct token keywords[] = { {"initrd", T_INITRD}, {"include", T_INCLUDE}, {"fdt", T_FDT}, + {"ontimeout", T_ONTIMEOUT,}, + {"ipappend", T_IPAPPEND,}, {NULL, T_INVALID} }; @@ -912,12 +970,7 @@ static int parse_integer(char **c, int *dst) return -EINVAL; } - if (strict_strtoul(t.val, 10, &temp) < 0) { - printf("Expected unsigned integer: %s\n", t.val); - return -EINVAL; - } - - *dst = (int)temp; + *dst = simple_strtol(t.val, &temp, 10); free(t.val); @@ -1016,10 +1069,8 @@ static int parse_label_menu(char **c, struct pxe_menu *cfg, switch (t.type) { case T_DEFAULT: - if (cfg->default_label) - free(cfg->default_label); - - cfg->default_label = strdup(label->name); + if (!cfg->default_label) + cfg->default_label = strdup(label->name); if (!cfg->default_label) return -ENOMEM; @@ -1053,6 +1104,7 @@ static int parse_label(char **c, struct pxe_menu *cfg) char *s = *c; struct pxe_label *label; int err; + int localboot; label = label_create(); if (!label) @@ -1108,7 +1160,12 @@ static int parse_label(char **c, struct pxe_menu *cfg) break; case T_LOCALBOOT: - err = parse_integer(c, &label->localboot); + label->localboot = 1; + err = parse_integer(c, &label->localboot_val); + break; + + case T_IPAPPEND: + err = parse_integer(c, &label->ipappend); break; case T_EOL: @@ -1164,6 +1221,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) err = 0; switch (t.type) { case T_MENU: + cfg->prompt = 1; err = parse_menu(&p, cfg, b, nest_level); break; @@ -1176,6 +1234,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) break; case T_DEFAULT: + case T_ONTIMEOUT: err = parse_sliteral(&p, &label_name); if (label_name) { @@ -1193,7 +1252,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) break; case T_PROMPT: - err = parse_integer(&p, &cfg->prompt); + eol_or_eof(&p); break; case T_EOL: @@ -1276,6 +1335,8 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) struct list_head *pos; struct menu *m; int err; + int i = 1; + char *default_num = NULL; /* * Create a menu and add items for all the labels. @@ -1288,18 +1349,23 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) list_for_each(pos, &cfg->labels) { label = list_entry(pos, struct pxe_label, list); - if (menu_item_add(m, label->name, label) != 1) { + sprintf(label->num, "%d", i++); + if (menu_item_add(m, label->num, label) != 1) { menu_destroy(m); return NULL; } + if (cfg->default_label && + (strcmp(label->name, cfg->default_label) == 0)) + default_num = label->num; + } /* * After we've created items for each label in the menu, set the * menu's default label if one was specified. */ - if (cfg->default_label) { - err = menu_default_set(m, cfg->default_label); + if (default_num) { + err = menu_default_set(m, default_num); if (err != 1) { if (err != -ENOENT) { menu_destroy(m); @@ -1366,8 +1432,11 @@ static void handle_pxe_menu(struct pxe_menu *cfg) * we give up. */ - if (err == 1) - label_boot(choice); + if (err == 1) { + err = label_boot(choice); + if (!err) + return; + } else if (err != -ENOENT) return; diff --git a/common/cmd_usbd.c b/common/cmd_usbd.c new file mode 100644 index 0000000..7b7a930 --- /dev/null +++ b/common/cmd_usbd.c @@ -0,0 +1,129 @@ +/* + * common/cmd_usbd.c + * + * $Id: cmd_usbd.c,v 1.2 2009/01/28 00:11:42 dark0351 Exp $ + * + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. + * - support for S3C2412, S3C2443 and S3C6400 + * + * (C) Copyright SAMSUNG Electronics + * SW.LEE + * - add USB device fo S3C2440A, S3C24A0A + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* + * Memory Functions + * + * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) + */ + +#include +#include +#include "cpu.h" + +#ifdef CONFIG_S3C_USBD + +//#include + +#if defined(CONFIG_S3C2412) || defined(CONFIG_S3C2442) +#include "../cpu/s3c24xx/usbd-fs.h" +#elif defined(CONFIG_S3C2443) || \ + defined(CONFIG_S3C2450) || \ + defined(CONFIG_S3C2416) +#include "../cpu/s3c24xx/usbd-hs.h" +#elif defined(CONFIG_S3C6400) || \ + defined(CONFIG_S3C6410) || \ + defined(CONFIG_S3C6430) +#include "../cpu/s3c64xx/usbd-otg-hs.h" +#elif defined(CONFIG_S5PC100) +#include "../cpu/s5pc1xx/usbd-otg-hs.h" +#elif defined(CONFIG_S5PC210) || defined(CONFIG_EXYNOS4) +#include "../drivers/usb/gadget/usbd-otg-hs.h" +#elif defined(CONFIG_S5P6440) +#include "../cpu/s5p64xx/usbd-otg-hs.h" +#elif defined(CONFIG_S5P6442) +#include "../cpu/s5p644x/usbd-otg-hs.h" +#else +#error "* CFG_ERROR : you have to setup right Samsung CPU configuration" +#endif + +#undef CMD_USBD_DEBUG +#ifdef CMD_USBD_DEBUG +#define PRINTF(fmt, args...) printf(fmt, ##args) +#else +#define PRINTF(fmt, args...) +#endif + +static const char pszMe[] = "usbd: "; + +int do_usbd_dnw(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + if (argv[0][0] == 'u') { + DNW = 0; + } else { + DNW = 1; + s3c_got_header = 0; + } + + switch (argc) { + case 1: + s3c_usbd_dn_addr = USBD_DOWN_ADDR; /* Default Address */ + break; + case 2: + s3c_usbd_dn_addr = simple_strtoul(argv[1], NULL, 16); + break; + default: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + s3c_receive_done = 0; + + s3c_usbctl_init(); + s3c_usbc_activate(); + + PRINTF("Download address 0x%08x\n", s3c_usbd_dn_addr); + printf("Now, Waiting for DNW to transmit data\n"); + + while (1) { + if (S3C_USBD_DETECT_IRQ()) { + s3c_udc_int_hndlr(); + S3C_USBD_CLEAR_IRQ(); + } + + if (s3c_receive_done) + break; + + if (serial_tstc()) { + serial_getc(); + break; + } + } + + /* when operation is done, usbd must be stopped */ + s3c_usb_stop(); + + return 0; +} + +U_BOOT_CMD( + dnw, 3, 0, do_usbd_dnw, + "dnw - initialize USB device and ready \ + to receive for Windows server (specific)\n", + "[download address]\n" +); + +#endif /* CONFIG_S3C_USBD */ diff --git a/common/cpu.h b/common/cpu.h new file mode 100644 index 0000000..2d9ca0f --- /dev/null +++ b/common/cpu.h @@ -0,0 +1,768 @@ +/* + * (C) Copyright 2011 Samsung Electronics Co. Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _S5PV310_CPU_H +#define _S5PV310_CPU_H + +#ifdef CONFIG_CPU_EXYNOS5210 +#include "cpu_exynos5210.h" +#elif CONFIG_CPU_EXYNOS5250 +#include "cpu_exynos5250.h" +#else + +//#define S5PV310_ADDR_BASE 0xE0000000 +/* S5PV310 */ +#define S5PV310_PRO_ID 0x10000000 +#define S5PV310_SYSREG_BASE 0x10010000 +#define S5PV310_POWER_BASE 0x10020000 +#define S5PV310_CLOCK_BASE 0x10030000 +//#define S5PC100_GPIO_BASE 0xE0300000 +//#define S5PC100_VIC0_BASE 0xE4000000 +//#define S5PC100_VIC1_BASE 0xE4100000 +//#define S5PC100_VIC2_BASE 0xE4200000 +//#define S5PC100_DMC_BASE 0xE6000000 +//#define S5PC100_SROMC_BASE 0xE7000000 +//#define S5PC100_ONENAND_BASE 0xE7100000 +#define S5PV310_HSMMC_BASE 0x12510000 +#define S5PV310_PWMTIMER_BASE 0x139D0000 +//#define S5PC100_WATCHDOG_BASE 0xEA200000 +#define S5PV310_UART_BASE 0x13800000 +//#define S5PC100_MMC_BASE 0xED800000 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define __REG(x) (*(unsigned int *)(x)) + +/* + * CHIP ID + */ +#define CHIP_ID_BASE 0x10000000 + +#define PRO_ID_OFFSET 0x0 +#define PRO_ID __REG(CHIP_ID_BASE+PRO_ID_OFFSET) + +/* + * SYSREG + */ +#define GENERAL_CTRL_C2C_OFFSET 0x10C +#define USB_CFG_OFFSET 0x21C +#define USB_CFG_REG (S5PV310_SYSREG_BASE+USB_CFG_OFFSET) + +/* + * POWER + */ +#define OMR_OFFSET 0x0 +#define SW_RST_REG_OFFSET 0x400 +#define SW_RST_REG __REG(S5PV310_POWER_BASE+SW_RST_REG_OFFSET) + +#define INF_REG_BASE 0x10020800 + +#define INF_REG0_OFFSET 0x00 +#define INF_REG1_OFFSET 0x04 +#define INF_REG2_OFFSET 0x08 +#define INF_REG3_OFFSET 0x0c +#define INF_REG4_OFFSET 0x10 +#define INF_REG5_OFFSET 0x14 +#define INF_REG6_OFFSET 0x18 +#define INF_REG7_OFFSET 0x1c + +#define C2C_CTRL_OFFSET 0x24 + +#define INF_REG0_REG __REG(INF_REG_BASE+INF_REG0_OFFSET) +#define INF_REG1_REG __REG(INF_REG_BASE+INF_REG1_OFFSET) +#define INF_REG2_REG __REG(INF_REG_BASE+INF_REG2_OFFSET) +#define INF_REG3_REG __REG(INF_REG_BASE+INF_REG3_OFFSET) +#define INF_REG4_REG __REG(INF_REG_BASE+INF_REG4_OFFSET) +#define INF_REG5_REG __REG(INF_REG_BASE+INF_REG5_OFFSET) +#define INF_REG6_REG __REG(INF_REG_BASE+INF_REG6_OFFSET) +#define INF_REG7_REG __REG(INF_REG_BASE+INF_REG7_OFFSET) + +/* Define Mode */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* + * CLOCK + */ +#define ELFIN_CLOCK_BASE 0x10030000 + +#define CLK_SRC_LEFTBUS_OFFSET 0x04200 +#define CLK_DIV_LEFTBUS_OFFSET 0x04500 + +#define CLK_SRC_RIGHTBUS_OFFSET 0x08200 +#define CLK_DIV_RIGHTBUS_OFFSET 0x08500 + +#define EPLL_LOCK_OFFSET 0x0C010 +#define VPLL_LOCK_OFFSET 0x0C020 +#define EPLL_CON0_OFFSET 0x0C110 +#define EPLL_CON1_OFFSET 0x0C114 +#ifdef CONFIG_SMDKC220 +#define EPLL_CON2_OFFSET 0x0C118 +#endif +#define VPLL_CON0_OFFSET 0x0C120 +#define VPLL_CON1_OFFSET 0x0C124 +#ifdef CONFIG_SMDKC220 +#define VPLL_CON2_OFFSET 0x0C128 +#endif + +#define CLK_SRC_TOP0_OFFSET 0x0C210 +#define CLK_SRC_TOP1_OFFSET 0x0C214 +#define CLK_SRC_FSYS_OFFSET 0x0C240 +#define CLK_SRC_PERIL0_OFFSET 0x0C250 +#define CLK_DIV_TOP_OFFSET 0x0C510 +#define CLK_DIV_FSYS1_OFFSET 0x0C544 +#define CLK_DIV_FSYS2_OFFSET 0x0C548 +#define CLK_DIV_FSYS3_OFFSET 0x0C54C +#define CLK_DIV_PERIL0_OFFSET 0x0C550 + +#define CLK_SRC_DMC_OFFSET 0x10200 +#define CLK_DIV_DMC0_OFFSET 0x10500 +#define CLK_DIV_DMC1_OFFSET 0x10504 + +#define APLL_LOCK_OFFSET 0x14000 +#define MPLL_LOCK_OFFSET 0x14008 +#define APLL_CON0_OFFSET 0x14100 +#define APLL_CON1_OFFSET 0x14104 +#ifdef CONFIG_SMDKC220 +#define MPLL_CON0_OFFSET 0x10108 +#define MPLL_CON1_OFFSET 0x1010C +#else +#define MPLL_CON0_OFFSET 0x14108 +#define MPLL_CON1_OFFSET 0x1410C +#endif + +#define CLK_SRC_CPU_OFFSET 0x14200 +#define CLK_DIV_CPU0_OFFSET 0x14500 +#define CLK_DIV_CPU1_OFFSET 0x14504 + +#define CLK_SRC_FSYS __REG(ELFIN_CLOCK_BASE+CLK_SRC_FSYS_OFFSET) +#define CLK_DIV_FSYS1 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS1_OFFSET) +#define CLK_DIV_FSYS2 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS2_OFFSET) +#define CLK_DIV_FSYS3 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS3_OFFSET) +#define APLL_CON0_REG __REG(ELFIN_CLOCK_BASE+APLL_CON0_OFFSET) +#define MPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+MPLL_CON0_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+EPLL_CON0_OFFSET) +#define VPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+VPLL_CON0_OFFSET) + +#define USB_PHY_CONTROL_OFFSET 0x0704 +#define USB_PHY_CONTROL (0x10020000+USB_PHY_CONTROL_OFFSET)//(ELFIN_CLOCK_POWER_BASE+USB_PHY_CONTROL_OFFSET) + +/* + * TZPC + */ +#define ELFIN_TZPC0_BASE 0x10110000 +#define ELFIN_TZPC1_BASE 0x10120000 +#define ELFIN_TZPC2_BASE 0x10130000 +#define ELFIN_TZPC3_BASE 0x10140000 +#define ELFIN_TZPC4_BASE 0x10150000 +#define ELFIN_TZPC5_BASE 0x10160000 + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE 0x12570000 + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10) +#define SROM_BC4_REG __REG(ELFIN_SROM_BASE+0x14) +#define SROM_BC5_REG __REG(ELFIN_SROM_BASE+0x18) + +/* + * SDRAM Controller + */ +#ifdef CONFIG_SMDKC220 +#define APB_DMC_0_BASE 0x10600000 +#define APB_DMC_1_BASE 0x10610000 +#else +#define APB_DMC_0_BASE 0x10400000 +#define APB_DMC_1_BASE 0x10410000 +#endif + +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PHYCONTROL1 0x1C +#define DMC_PHYCONTROL2 0x20 +#define DMC_PWRDNCONFIG 0x28 +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYSTATUS 0x40 +#define DMC_PHYZQCONTROL 0x44 +#define DMC_CHIP0STATUS 0x48 +#define DMC_CHIP1STATUS 0x4C +#define DMC_AREFSTATUS 0x50 +#define DMC_MRSTATUS 0x54 +#define DMC_PHYTEST0 0x58 +#define DMC_PHYTEST1 0x5C +#define DMC_QOSCONTROL0 0x60 +#define DMC_QOSCONFIG0 0x64 +#define DMC_QOSCONTROL1 0x68 +#define DMC_QOSCONFIG1 0x6C +#define DMC_QOSCONTROL2 0x70 +#define DMC_QOSCONFIG2 0x74 +#define DMC_QOSCONTROL3 0x78 +#define DMC_QOSCONFIG3 0x7C +#define DMC_QOSCONTROL4 0x80 +#define DMC_QOSCONFIG4 0x84 +#define DMC_QOSCONTROL5 0x88 +#define DMC_QOSCONFIG5 0x8C +#define DMC_QOSCONTROL6 0x90 +#define DMC_QOSCONFIG6 0x94 +#define DMC_QOSCONTROL7 0x98 +#define DMC_QOSCONFIG7 0x9C +#define DMC_QOSCONTROL8 0xA0 +#define DMC_QOSCONFIG8 0xA4 +#define DMC_QOSCONTROL9 0xA8 +#define DMC_QOSCONFIG9 0xAC +#define DMC_QOSCONTROL10 0xB0 +#define DMC_QOSCONFIG10 0xB4 +#define DMC_QOSCONTROL11 0xB8 +#define DMC_QOSCONFIG11 0xBC +#define DMC_QOSCONTROL12 0xC0 +#define DMC_QOSCONFIG12 0xC4 +#define DMC_QOSCONTROL13 0xC8 +#define DMC_QOSCONFIG13 0xCC +#define DMC_QOSCONTROL14 0xD0 +#define DMC_QOSCONFIG14 0xD4 +#define DMC_QOSCONTROL15 0xD8 +#define DMC_QOSCONFIG15 0xDC +#ifdef CONFIG_SMDKC220 +#define DMC_IVCONTROL 0xF0 +#endif + +/* + * MIU + */ +#define MIU_BASE 0x10600000 +#define MIU_INTLV_CONFIG 0x400 +#define MIU_INTLV_START_ADDR 0x808 +#define MIU_MAPPING_UPDATE 0x800 +#define MIU_INTLV_END_ADDR 0x810 + +#define MIU_SINGLE_MAPPING0_START_ADDR 0x818 +#define MIU_SINGLE_MAPPING0_END_ADDR 0x820 +#define MIU_SINGLE_MAPPING1_START_ADDR 0x828 +#define MIU_SINGLE_MAPPING1_END_ADDR 0x830 + +/* + * UART + */ + +#define S5PV310_UART0_OFFSET 0x00000 +#define S5PV310_UART1_OFFSET 0x10000 +#define S5PV310_UART2_OFFSET 0x20000 +#define S5PV310_UART3_OFFSET 0x30000 + +#if defined(CONFIG_SERIAL0) +#define S5PV310_UART_CONSOLE_BASE (S5PV310_UART_BASE + S5PV310_UART0_OFFSET) +#elif defined(CONFIG_SERIAL1) +#define S5PV310_UART_CONSOLE_BASE (S5PV310_UART_BASE + S5PV310_UART1_OFFSET) +#elif defined(CONFIG_SERIAL2) +#define S5PV310_UART_CONSOLE_BASE (S5PV310_UART_BASE + S5PV310_UART2_OFFSET) +#elif defined(CONFIG_SERIAL3) +#define S5PV310_UART_CONSOLE_BASE (S5PV310_UART_BASE + S5PV310_UART3_OFFSET) +#else +#define S5PV310_UART_CONSOLE_BASE (S5PV310_UART_BASE + S5PV310_UART0_OFFSET) +#endif + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 +//#define UTRSTAT_TX_EMPTY BIT2 +//#define UTRSTAT_RX_READY BIT0 +#define UART_ERR_MASK 0xF + +/* + * HS MMC + */ +#define ELFIN_HSMMC_0_BASE 0x12510000 +#define ELFIN_HSMMC_1_BASE 0x12520000 +#define ELFIN_HSMMC_2_BASE 0x12530000 +#define ELFIN_HSMMC_3_BASE 0x12540000 +#define ELFIN_HSMMC_4_BASE 0x12550000 + +#define HM_SYSAD (0x00) +#define HM_BLKSIZE (0x04) +#define HM_BLKCNT (0x06) +#define HM_ARGUMENT (0x08) +#define HM_TRNMOD (0x0c) +#define HM_CMDREG (0x0e) +#define HM_RSPREG0 (0x10) +#define HM_RSPREG1 (0x14) +#define HM_RSPREG2 (0x18) +#define HM_RSPREG3 (0x1c) +#define HM_BDATA (0x20) +#define HM_PRNSTS (0x24) +#define HM_HOSTCTL (0x28) +#define HM_PWRCON (0x29) +#define HM_BLKGAP (0x2a) +#define HM_WAKCON (0x2b) +#define HM_CLKCON (0x2c) +#define HM_TIMEOUTCON (0x2e) +#define HM_SWRST (0x2f) +#define HM_NORINTSTS (0x30) +#define HM_ERRINTSTS (0x32) +#define HM_NORINTSTSEN (0x34) +#define HM_ERRINTSTSEN (0x36) +#define HM_NORINTSIGEN (0x38) +#define HM_ERRINTSIGEN (0x3a) +#define HM_ACMD12ERRSTS (0x3c) +#define HM_CAPAREG (0x40) +#define HM_MAXCURR (0x48) +#define HM_CONTROL2 (0x80) +#define HM_CONTROL3 (0x84) +#define HM_CONTROL4 (0x8c) +#define HM_HCVER (0xfe) + +/* USBD 2.0 SFR */ +#define USBOTG_LINK_BASE (0x12480000) //(0xEC000000) +#define USBOTG_PHY_BASE (0x125B0000) //(0xEC100000) + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#ifndef __ASSEMBLY__ +#include +/* CPU detection macros */ +//extern unsigned int s5p_cpu_id; + +//static inline void s5p_set_cpu_id(void) +//{ +// s5p_cpu_id = readl(S5PC100_PRO_ID); +// s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); +//} + +//#define IS_SAMSUNG_TYPE(type, id) \ +//static inline int cpu_is_##type(void) \ +//{ \ +// return s5p_cpu_id == id ? 1 : 0; \ +//} + +//IS_SAMSUNG_TYPE(s5pc100, 0xc100) +//IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +/*#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + return S5PV310_##base; \ +} +*/ +//SAMSUNG_BASE(clock, CLOCK_BASE) +//SAMSUNG_BASE(gpio, GPIO_BASE) +//SAMSUNG_BASE(pro_id, PRO_ID) +//SAMSUNG_BASE(mmc, MMC_BASE) +//SAMSUNG_BASE(sromc, SROMC_BASE) +//SAMSUNG_BASE(timer, PWMTIMER_BASE) +//SAMSUNG_BASE(uart, UART_CONSOLE_BASE) +#endif +#endif /* !CONFIG_EXYNOS5210 */ +/* + * USB2.0 HS OTG (Chapter 26) + */ + +#define S5P_OTG_PHYPWR (USBOTG_PHY_BASE + 0x000) /* R/W OTG PHY Power Control Register */ +#define S5P_OTG_PHYCLK (USBOTG_PHY_BASE + 0x004) /* R/W OTG PHY Clock Control Register */ +#define S5P_OTG_RSTCON (USBOTG_PHY_BASE + 0x008) /* R/W OTG Reset Control Register */ +#define S5P_OTG_PHYTUNE0 (USBOTG_PHY_BASE + 0x020) /* R/W OTG PHY0 Tuning Register */ +#define S5P_OTG_PHYTUNE1 (USBOTG_PHY_BASE + 0x024) /* R/W OTG PHY1 Tuning Register */ + +/* Core Global Register */ +#define S5P_OTG_GOTGCTL (USBOTG_LINK_BASE + 0x000) /* R/W OTG Control and Status Register */ +#define S5P_OTG_GOTGINT (USBOTG_LINK_BASE + 0x004) /* R/W OTG Interrupt Register */ +#define S5P_OTG_GAHBCFG (USBOTG_LINK_BASE + 0x008) /* R/W Core AHB Configuration Register */ +#define S5P_OTG_GUSBCFG (USBOTG_LINK_BASE + 0x00C) /* R/W Core USB Configuration Register */ +#define S5P_OTG_GRSTCTL (USBOTG_LINK_BASE + 0x010) /* R/W Core Reset Register */ +#define S5P_OTG_GINTSTS (USBOTG_LINK_BASE + 0x014) /* R/W Core Interrupt Register */ +#define S5P_OTG_GINTMSK (USBOTG_LINK_BASE + 0x018) /* R/W Core Interrupt Mask Register */ +#define S5P_OTG_GRXSTSR (USBOTG_LINK_BASE + 0x01C) /* R Receive Status Debug Read Register */ +#define S5P_OTG_GRXSTSP (USBOTG_LINK_BASE + 0x020) /* R Receive Status Read/Pop Register */ +#define S5P_OTG_GRXFSIZ (USBOTG_LINK_BASE + 0x024) /* R/W Receive FIFO Size Register */ +#define S5P_OTG_GNPTXFSIZ (USBOTG_LINK_BASE + 0x028) /* R/W Non-Periodic Transmit FIFO Size Register */ +#define S5P_OTG_GNPTXSTS (USBOTG_LINK_BASE + 0x02C) /* R Non-Periodic Transmit FIFO/Queue Status Register */ +#define S5P_OTG_HPTXFSIZ (USBOTG_LINK_BASE + 0x100) /* R/W Host Periodic Transmit FIFO Size Register */ +#define S5P_OTG_DPTXFSIZ1 (USBOTG_LINK_BASE + 0x104) /* R/W Device Periodic Transmit FIFO-1 Size Register */ +#define S5P_OTG_DPTXFSIZ2 (USBOTG_LINK_BASE + 0x108) /* R/W Device Periodic Transmit FIFO-2 Size Register */ +#define S5P_OTG_DPTXFSIZ3 (USBOTG_LINK_BASE + 0x10C) /* R/W Device Periodic Transmit FIFO-3 Size Register */ +#define S5P_OTG_DPTXFSIZ4 (USBOTG_LINK_BASE + 0x110) /* R/W Device Periodic Transmit FIFO-4 Size Register */ +#define S5P_OTG_DPTXFSIZ5 (USBOTG_LINK_BASE + 0x114) /* R/W Device Periodic Transmit FIFO-5 Size Register */ +#define S5P_OTG_DPTXFSIZ6 (USBOTG_LINK_BASE + 0x118) /* R/W Device Periodic Transmit FIFO-6 Size Register */ +#define S5P_OTG_DPTXFSIZ7 (USBOTG_LINK_BASE + 0x11C) /* R/W Device Periodic Transmit FIFO-7 Size Register */ +#define S5P_OTG_DPTXFSIZ8 (USBOTG_LINK_BASE + 0x120) /* R/W Device Periodic Transmit FIFO-8 Size Register */ +#define S5P_OTG_DPTXFSIZ9 (USBOTG_LINK_BASE + 0x124) /* R/W Device Periodic Transmit FIFO-9 Size Register */ +#define S5P_OTG_DPTXFSIZ10 (USBOTG_LINK_BASE + 0x128) /* R/W Device Periodic Transmit FIFO-10 Size Register */ +#define S5P_OTG_DPTXFSIZ11 (USBOTG_LINK_BASE + 0x12C) /* R/W Device Periodic Transmit FIFO-11 Size Register */ +#define S5P_OTG_DPTXFSIZ12 (USBOTG_LINK_BASE + 0x130) /* R/W Device Periodic Transmit FIFO-12 Size Register */ +#define S5P_OTG_DPTXFSIZ13 (USBOTG_LINK_BASE + 0x134) /* R/W Device Periodic Transmit FIFO-13 Size Register */ +#define S5P_OTG_DPTXFSIZ14 (USBOTG_LINK_BASE + 0x138) /* R/W Device Periodic Transmit FIFO-14 Size Register */ +#define S5P_OTG_DPTXFSIZ15 (USBOTG_LINK_BASE + 0x13C) /* R/W Device Periodic Transmit FIFO-15 Size Register */ + +/* Host Mode Register */ +/* Host Global Register */ +#define S5P_OTG_HCFG (USBOTG_LINK_BASE + 0x400) /* R/W Host Configuration Register */ +#define S5P_OTG_HFIR (USBOTG_LINK_BASE + 0x404) /* R/W Host Frame Interval Register */ +#define S5P_OTG_HFNUM (USBOTG_LINK_BASE + 0x408) /* R Host Frame Number/Frame Time Remaining Register */ + +#define S5P_OTG_HPTXSTS (USBOTG_LINK_BASE + 0x410) /* R Host Periodic Transmit FIFO/Queue Status Register */ +#define S5P_OTG_HAINT (USBOTG_LINK_BASE + 0x414) /* R Host All Channels Interrupt Register */ +#define S5P_OTG_HAINTMSK (USBOTG_LINK_BASE + 0x418) /* R/W Host All Channels Interrupt Mask Register */ + +/*Host Port Control and Status Register */ +#define S5P_OTG_HPRT (USBOTG_LINK_BASE + 0x440) /* R/W Host Port Control and Status Register */ + +/*Host Channel-Specific Register */ +#define S5P_OTG_HCCHAR0 (USBOTG_LINK_BASE + 0x500) /* R/W Host Channel 0 Characteristics Register */ +#define S5P_OTG_HCSPLT0 (USBOTG_LINK_BASE + 0x504) /* R/W Host Channel 0 Spilt Control Register */ +#define S5P_OTG_HCINT0 (USBOTG_LINK_BASE + 0x508) /* R/W Host Channel 0 Interrupt Register */ +#define S5P_OTG_HCINTMSK0 (USBOTG_LINK_BASE + 0x50C) /* R/W Host Channel 0 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ0 (USBOTG_LINK_BASE + 0x510) /* R/W Host Channel 0 Transfer Size Register */ +#define S5P_OTG_HCDMA0 (USBOTG_LINK_BASE + 0x514) /* R/W Host Channel 0 DMA Address Register */ +#define S5P_OTG_HCCHAR1 (USBOTG_LINK_BASE + 0x520) /* R/W Host Channel 1 Characteristics Register */ +#define S5P_OTG_HCSPLT1 (USBOTG_LINK_BASE + 0x524) /* R/W Host Channel 1 Spilt Control Register */ +#define S5P_OTG_HCINT1 (USBOTG_LINK_BASE + 0x528) /* R/W Host Channel 1 Interrupt Register */ +#define S5P_OTG_HCINTMSK1 (USBOTG_LINK_BASE + 0x52C) /* R/W Host Channel 1 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ1 (USBOTG_LINK_BASE + 0x530) /* R/W Host Channel 1 Transfer Size Register */ +#define S5P_OTG_HCDMA1 (USBOTG_LINK_BASE + 0x534) /* R/W Host Channel 1 DMA Address Register */ +#define S5P_OTG_HCCHAR2 (USBOTG_LINK_BASE + 0x540) /* R/W Host Channel 2 Characteristics Register */ +#define S5P_OTG_HCSPLT2 (USBOTG_LINK_BASE + 0x544) /* R/W Host Channel 2 Spilt Control Register */ +#define S5P_OTG_HCINT2 (USBOTG_LINK_BASE + 0x548) /* R/W Host Channel 2 Interrupt Register */ +#define S5P_OTG_HCINTMSK2 (USBOTG_LINK_BASE + 0x54C) /* R/W Host Channel 2 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ2 (USBOTG_LINK_BASE + 0x550) /* R/W Host Channel 2 Transfer Size Register */ +#define S5P_OTG_HCDMA2 (USBOTG_LINK_BASE + 0x554) /* R/W Host Channel 2 DMA Address Register */ +#define S5P_OTG_HCCHAR3 (USBOTG_LINK_BASE + 0x560) /* R/W Host Channel 3 Characteristics Register */ +#define S5P_OTG_HCSPLT3 (USBOTG_LINK_BASE + 0x564) /* R/W Host Channel 3 Spilt Control Register */ +#define S5P_OTG_HCINT3 (USBOTG_LINK_BASE + 0x568) /* R/W Host Channel 3 Interrupt Register */ +#define S5P_OTG_HCINTMSK3 (USBOTG_LINK_BASE + 0x56C) /* R/W Host Channel 3 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ3 (USBOTG_LINK_BASE + 0x570) /* R/W Host Channel 3 Transfer Size Register */ +#define S5P_OTG_HCDMA3 (USBOTG_LINK_BASE + 0x574) /* R/W Host Channel 3 DMA Address Register */ +#define S5P_OTG_HCCHAR4 (USBOTG_LINK_BASE + 0x580) /* R/W Host Channel 4 Characteristics Register */ +#define S5P_OTG_HCSPLT4 (USBOTG_LINK_BASE + 0x584) /* R/W Host Channel 4 Spilt Control Register */ +#define S5P_OTG_HCINT4 (USBOTG_LINK_BASE + 0x588) /* R/W Host Channel 4 Interrupt Register */ +#define S5P_OTG_HCINTMSK4 (USBOTG_LINK_BASE + 0x58C) /* R/W Host Channel 4 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ4 (USBOTG_LINK_BASE + 0x580) /* R/W Host Channel 4 Transfer Size Register */ +#define S5P_OTG_HCDMA4 (USBOTG_LINK_BASE + 0x584) /* R/W Host Channel 4 DMA Address Register */ +#define S5P_OTG_HCCHAR5 (USBOTG_LINK_BASE + 0x5A0) /* R/W Host Channel 5 Characteristics Register */ +#define S5P_OTG_HCSPLT5 (USBOTG_LINK_BASE + 0x5A4) /* R/W Host Channel 5 Spilt Control Register */ +#define S5P_OTG_HCINT5 (USBOTG_LINK_BASE + 0x5A8) /* R/W Host Channel 5 Interrupt Register */ +#define S5P_OTG_HCINTMSK5 (USBOTG_LINK_BASE + 0x5AC) /* R/W Host Channel 5 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ5 (USBOTG_LINK_BASE + 0x5B0) /* R/W Host Channel 5 Transfer Size Register */ +#define S5P_OTG_HCDMA5 (USBOTG_LINK_BASE + 0x5B4) /* R/W Host Channel 5 DMA Address Register */ +#define S5P_OTG_HCCHAR6 (USBOTG_LINK_BASE + 0x5C0) /* R/W Host Channel 6 Characteristics Register */ +#define S5P_OTG_HCSPLT6 (USBOTG_LINK_BASE + 0x5C4) /* R/W Host Channel 6 Spilt Control Register */ +#define S5P_OTG_HCINT6 (USBOTG_LINK_BASE + 0x5C8) /* R/W Host Channel 6 Interrupt Register */ +#define S5P_OTG_HCINTMSK6 (USBOTG_LINK_BASE + 0x5CC) /* R/W Host Channel 6 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ6 (USBOTG_LINK_BASE + 0x5D0) /* R/W Host Channel 6 Transfer Size Register */ +#define S5P_OTG_HCDMA6 (USBOTG_LINK_BASE + 0x5D4) /* R/W Host Channel 6 DMA Address Register */ +#define S5P_OTG_HCCHAR7 (USBOTG_LINK_BASE + 0x5E0) /* R/W Host Channel 7 Characteristics Register */ +#define S5P_OTG_HCSPLT7 (USBOTG_LINK_BASE + 0x5E4) /* R/W Host Channel 7 Spilt Control Register */ +#define S5P_OTG_HCINT7 (USBOTG_LINK_BASE + 0x5E8) /* R/W Host Channel 7 Interrupt Register */ +#define S5P_OTG_HCINTMSK7 (USBOTG_LINK_BASE + 0x5EC) /* R/W Host Channel 7 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ7 (USBOTG_LINK_BASE + 0x5F0) /* R/W Host Channel 7 Transfer Size Register */ +#define S5P_OTG_HCDMA7 (USBOTG_LINK_BASE + 0x5F4) /* R/W Host Channel 7 DMA Address Register */ +#define S5P_OTG_HCCHAR8 (USBOTG_LINK_BASE + 0x600) /* R/W Host Channel 8 Characteristics Register */ +#define S5P_OTG_HCSPLT8 (USBOTG_LINK_BASE + 0x604) /* R/W Host Channel 8 Spilt Control Register */ +#define S5P_OTG_HCINT8 (USBOTG_LINK_BASE + 0x608) /* R/W Host Channel 8 Interrupt Register */ +#define S5P_OTG_HCINTMSK8 (USBOTG_LINK_BASE + 0x60C) /* R/W Host Channel 8 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ8 (USBOTG_LINK_BASE + 0x610) /* R/W Host Channel 8 Transfer Size Register */ +#define S5P_OTG_HCDMA8 (USBOTG_LINK_BASE + 0x614) /* R/W Host Channel 8 DMA Address Register */ +#define S5P_OTG_HCCHAR9 (USBOTG_LINK_BASE + 0x620) /* R/W Host Channel 9 Characteristics Register */ +#define S5P_OTG_HCSPLT9 (USBOTG_LINK_BASE + 0x624) /* R/W Host Channel 9 Spilt Control Register */ +#define S5P_OTG_HCINT9 (USBOTG_LINK_BASE + 0x628) /* R/W Host Channel 9 Interrupt Register */ +#define S5P_OTG_HCINTMSK9 (USBOTG_LINK_BASE + 0x62C) /* R/W Host Channel 9 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ9 (USBOTG_LINK_BASE + 0x630) /* R/W Host Channel 9 Transfer Size Register */ +#define S5P_OTG_HCDMA9 (USBOTG_LINK_BASE + 0x634) /* R/W Host Channel 9 DMA Address Register */ +#define S5P_OTG_HCCHAR10 (USBOTG_LINK_BASE + 0x640) /* R/W Host Channel 10 Characteristics Register */ +#define S5P_OTG_HCSPLT10 (USBOTG_LINK_BASE + 0x644) /* R/W Host Channel 10 Spilt Control Register */ +#define S5P_OTG_HCINT10 (USBOTG_LINK_BASE + 0x648) /* R/W Host Channel 10 Interrupt Register */ +#define S5P_OTG_HCINTMSK10 (USBOTG_LINK_BASE + 0x64C) /* R/W Host Channel 10 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ10 (USBOTG_LINK_BASE + 0x650) /* R/W Host Channel 10 Transfer Size Register */ +#define S5P_OTG_HCDMA10 (USBOTG_LINK_BASE + 0x654) /* R/W Host Channel 10 DMA Address Register */ +#define S5P_OTG_HCCHAR11 (USBOTG_LINK_BASE + 0x660) /* R/W Host Channel 11 Characteristics Register */ +#define S5P_OTG_HCSPLT11 (USBOTG_LINK_BASE + 0x664) /* R/W Host Channel 11 Spilt Control Register */ +#define S5P_OTG_HCINT11 (USBOTG_LINK_BASE + 0x668) /* R/W Host Channel 11 Interrupt Register */ +#define S5P_OTG_HCINTMSK11 (USBOTG_LINK_BASE + 0x66C) /* R/W Host Channel 11 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ11 (USBOTG_LINK_BASE + 0x670) /* R/W Host Channel 11 Transfer Size Register */ +#define S5P_OTG_HCDMA11 (USBOTG_LINK_BASE + 0x674) /* R/W Host Channel 11 DMA Address Register */ +#define S5P_OTG_HCCHAR12 (USBOTG_LINK_BASE + 0x680) /* R/W Host Channel 12 Characteristics Register */ +#define S5P_OTG_HCSPLT12 (USBOTG_LINK_BASE + 0x684) /* R/W Host Channel 12 Spilt Control Register */ +#define S5P_OTG_HCINT12 (USBOTG_LINK_BASE + 0x688) /* R/W Host Channel 12 Interrupt Register */ +#define S5P_OTG_HCINTMSK12 (USBOTG_LINK_BASE + 0x68C) /* R/W Host Channel 12 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ12 (USBOTG_LINK_BASE + 0x690) /* R/W Host Channel 12 Transfer Size Register */ +#define S5P_OTG_HCDMA12 (USBOTG_LINK_BASE + 0x694) /* R/W Host Channel 12 DMA Address Register */ +#define S5P_OTG_HCCHAR13 (USBOTG_LINK_BASE + 0x6A0) /* R/W Host Channel 13 Characteristics Register */ +#define S5P_OTG_HCSPLT13 (USBOTG_LINK_BASE + 0x6A4) /* R/W Host Channel 13 Spilt Control Register */ +#define S5P_OTG_HCINT13 (USBOTG_LINK_BASE + 0x6A8) /* R/W Host Channel 13 Interrupt Register */ +#define S5P_OTG_HCINTMSK13 (USBOTG_LINK_BASE + 0x6AC) /* R/W Host Channel 13 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ13 (USBOTG_LINK_BASE + 0x6B0) /* R/W Host Channel 13 Transfer Size Register */ +#define S5P_OTG_HCDMA13 (USBOTG_LINK_BASE + 0x6B4) /* R/W Host Channel 13 DMA Address Register */ +#define S5P_OTG_HCCHAR14 (USBOTG_LINK_BASE + 0x6C0) /* R/W Host Channel 14 Characteristics Register */ +#define S5P_OTG_HCSPLT14 (USBOTG_LINK_BASE + 0x6C4) /* R/W Host Channel 14 Spilt Control Register */ +#define S5P_OTG_HCINT14 (USBOTG_LINK_BASE + 0x6C8) /* R/W Host Channel 14 Interrupt Register */ +#define S5P_OTG_HCINTMSK14 (USBOTG_LINK_BASE + 0x6CC) /* R/W Host Channel 14 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ14 (USBOTG_LINK_BASE + 0x6D0) /* R/W Host Channel 14 Transfer Size Register */ +#define S5P_OTG_HCDMA14 (USBOTG_LINK_BASE + 0x6D4) /* R/W Host Channel 14 DMA Address Register */ +#define S5P_OTG_HCCHAR15 (USBOTG_LINK_BASE + 0x6E0) /* R/W Host Channel 15 Characteristics Register */ +#define S5P_OTG_HCSPLT15 (USBOTG_LINK_BASE + 0x6E4) /* R/W Host Channel 15 Spilt Control Register */ +#define S5P_OTG_HCINT15 (USBOTG_LINK_BASE + 0x6E8) /* R/W Host Channel 15 Interrupt Register */ +#define S5P_OTG_HCINTMSK15 (USBOTG_LINK_BASE + 0x6EC) /* R/W Host Channel 15 Interrupt Mask Register */ +#define S5P_OTG_HCTSIZ15 (USBOTG_LINK_BASE + 0x6F0) /* R/W Host Channel 15 Transfer Size Register */ +#define S5P_OTG_HCDMA15 (USBOTG_LINK_BASE + 0x6F4) /* R/W Host Channel 15 DMA Address Register */ + +/* Device Global Register */ +#define S5P_OTG_DCFG (USBOTG_LINK_BASE + 0x800) /* R/W Device Configuration Register */ +#define S5P_OTG_DCTL (USBOTG_LINK_BASE + 0x804) /* R/W Device Control Register */ +#define S5P_OTG_DSTS (USBOTG_LINK_BASE + 0x808) /* R Device Status Register */ +#define S5P_OTG_DIEPMSK (USBOTG_LINK_BASE + 0x810) /* R/W Device IN Endpoint Common Interrupt Mask Register */ +#define S5P_OTG_DOEPMSK (USBOTG_LINK_BASE + 0x814) /* R/W Device OUT Endpoint Common Interrupt Mask Register */ +#define S5P_OTG_DAINT (USBOTG_LINK_BASE + 0x818) /* R Device ALL Endpoints Interrupt Register */ +#define S5P_OTG_DAINTMSK (USBOTG_LINK_BASE + 0x81C) /* R/W Device ALL Endpoints Interrupt Mask Register */ +#define S5P_OTG_DTKNQR1 (USBOTG_LINK_BASE + 0x820) /* R Device IN Token Sequence Learning Queue Read Register */ +#define S5P_OTG_DTKNQR2 (USBOTG_LINK_BASE + 0x824) /* R Device IN Token Sequence Learning Queue Read Register */ +#define S5P_OTG_DVBUSDIS (USBOTG_LINK_BASE + 0x828) /* R/W Device VBUS Discharge Time Register */ +#define S5P_OTG_DVBUSPULSE (USBOTG_LINK_BASE + 0x82C) /* R/W Device VBUS Pulsing Time Register */ +#define S5P_OTG_DTKNQR3 (USBOTG_LINK_BASE + 0x830) /* R Device IN Token Sequence Learning Queue Read Register */ +#define S5P_OTG_DTKNQR4 (USBOTG_LINK_BASE + 0x834) /* R Device IN Token Sequence Learning Queue Read Register */ + +/* Device Logical IN Endpo int-Specific Registers */ +#define S5P_OTG_DIEPCTL0 (USBOTG_LINK_BASE + 0x900) /* R/W Device Control IN Endpoint 0 Control Register */ +#define S5P_OTG_DIEPINT0 (USBOTG_LINK_BASE + 0x908) /* R/W Device IN Endpoint 0 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ0 (USBOTG_LINK_BASE + 0x910) /* R/W Device IN Endpoint 0 Transfer Size Register */ +#define S5P_OTG_DIEPDMA0 (USBOTG_LINK_BASE + 0x914) /* R/W Device IN Endpoint 0 DMA Address Register */ +#define S5P_OTG_DIEPCTL1 (USBOTG_LINK_BASE + 0x920) /* R/W Device Control IN Endpoint 1 Control Register */ +#define S5P_OTG_DIEPINT1 (USBOTG_LINK_BASE + 0x928) /* R/W Device IN Endpoint 1 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ1 (USBOTG_LINK_BASE + 0x930) /* R/W Device IN Endpoint 1 Transfer Size Register */ +#define S5P_OTG_DIEPDMA1 (USBOTG_LINK_BASE + 0x934) /* R/W Device IN Endpoint 1 DMA Address Register */ +#define S5P_OTG_DIEPCTL2 (USBOTG_LINK_BASE + 0x940) /* R/W Device Control IN Endpoint 2 Control Register */ +#define S5P_OTG_DIEPINT2 (USBOTG_LINK_BASE + 0x948) /* R/W Device IN Endpoint 2 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ2 (USBOTG_LINK_BASE + 0x950) /* R/W Device IN Endpoint 2 Transfer Size Register */ +#define S5P_OTG_DIEPDMA2 (USBOTG_LINK_BASE + 0x954) /* R/W Device IN Endpoint 2 DMA Address Register */ +#define S5P_OTG_DIEPCTL3 (USBOTG_LINK_BASE + 0x960) /* R/W Device Control IN Endpoint 3 Control Register */ +#define S5P_OTG_DIEPINT3 (USBOTG_LINK_BASE + 0x968) /* R/W Device IN Endpoint 3 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ3 (USBOTG_LINK_BASE + 0x970) /* R/W Device IN Endpoint 3 Transfer Size Register */ +#define S5P_OTG_DIEPDMA3 (USBOTG_LINK_BASE + 0x974) /* R/W Device IN Endpoint 3 DMA Address Register */ +#define S5P_OTG_DIEPCTL4 (USBOTG_LINK_BASE + 0x980) /* R/W Device Control IN Endpoint 0 Control Register */ +#define S5P_OTG_DIEPINT4 (USBOTG_LINK_BASE + 0x988) /* R/W Device IN Endpoint 4 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ4 (USBOTG_LINK_BASE + 0x990) /* R/W Device IN Endpoint 4 Transfer Size Register */ +#define S5P_OTG_DIEPDMA4 (USBOTG_LINK_BASE + 0x994) /* R/W Device IN Endpoint 4 DMA Address Register */ +#define S5P_OTG_DIEPCTL5 (USBOTG_LINK_BASE + 0x9A0) /* R/W Device Control IN Endpoint 5 Control Register */ +#define S5P_OTG_DIEPINT5 (USBOTG_LINK_BASE + 0x9A8) /* R/W Device IN Endpoint 5 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ5 (USBOTG_LINK_BASE + 0x9B0) /* R/W Device IN Endpoint 5 Transfer Size Register */ +#define S5P_OTG_DIEPDMA5 (USBOTG_LINK_BASE + 0x9B4) /* R/W Device IN Endpoint 5 DMA Address Register */ +#define S5P_OTG_DIEPCTL6 (USBOTG_LINK_BASE + 0x9C0) /* R/W Device Control IN Endpoint 6 Control Register */ +#define S5P_OTG_DIEPINT6 (USBOTG_LINK_BASE + 0x9C8) /* R/W Device IN Endpoint 6 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ6 (USBOTG_LINK_BASE + 0x9D0) /* R/W Device IN Endpoint 6 Transfer Size Register */ +#define S5P_OTG_DIEPDMA6 (USBOTG_LINK_BASE + 0x9D4) /* R/W Device IN Endpoint 6 DMA Address Register */ +#define S5P_OTG_DIEPCTL7 (USBOTG_LINK_BASE + 0x9E0) /* R/W Device Control IN Endpoint 7 Control Register */ +#define S5P_OTG_DIEPINT7 (USBOTG_LINK_BASE + 0x9E8) /* R/W Device IN Endpoint 7 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ7 (USBOTG_LINK_BASE + 0x9F0) /* R/W Device IN Endpoint 7 Transfer Size Register */ +#define S5P_OTG_DIEPDMA7 (USBOTG_LINK_BASE + 0x9F4) /* R/W Device IN Endpoint 7 DMA Address Register */ +#define S5P_OTG_DIEPCTL8 (USBOTG_LINK_BASE + 0xA00) /* R/W Device Control IN Endpoint 8 Control Register */ +#define S5P_OTG_DIEPINT8 (USBOTG_LINK_BASE + 0xA08) /* R/W Device IN Endpoint 8 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ8 (USBOTG_LINK_BASE + 0xA10) /* R/W Device IN Endpoint 8 Transfer Size Register */ +#define S5P_OTG_DIEPDMA8 (USBOTG_LINK_BASE + 0xA14) /* R/W Device IN Endpoint 8 DMA Address Register */ +#define S5P_OTG_DIEPCTL9 (USBOTG_LINK_BASE + 0xA20) /* R/W Device Control IN Endpoint 9 Control Register */ +#define S5P_OTG_DIEPINT9 (USBOTG_LINK_BASE + 0xA28) /* R/W Device IN Endpoint 9 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ9 (USBOTG_LINK_BASE + 0xA30) /* R/W Device IN Endpoint 9 Transfer Size Register */ +#define S5P_OTG_DIEPDMA9 (USBOTG_LINK_BASE + 0xA34) /* R/W Device IN Endpoint 9 DMA Address Register */ +#define S5P_OTG_DIEPCTL10 (USBOTG_LINK_BASE + 0xA40) /* R/W Device Control IN Endpoint 10 Control Register */ +#define S5P_OTG_DIEPINT10 (USBOTG_LINK_BASE + 0xA48) /* R/W Device IN Endpoint 10 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ10 (USBOTG_LINK_BASE + 0xA50) /* R/W Device IN Endpoint 10 Transfer Size Register */ +#define S5P_OTG_DIEPDMA10 (USBOTG_LINK_BASE + 0xA54) /* R/W Device IN Endpoint 10 DMA Address Register */ +#define S5P_OTG_DIEPCTL11 (USBOTG_LINK_BASE + 0xA60) /* R/W Device Control IN Endpoint 11 Control Register */ +#define S5P_OTG_DIEPINT11 (USBOTG_LINK_BASE + 0xA68) /* R/W Device IN Endpoint 11 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ11 (USBOTG_LINK_BASE + 0xA70) /* R/W Device IN Endpoint 11 Transfer Size Register */ +#define S5P_OTG_DIEPDMA11 (USBOTG_LINK_BASE + 0xA74) /* R/W Device IN Endpoint 11 DMA Address Register */ +#define S5P_OTG_DIEPCTL12 (USBOTG_LINK_BASE + 0xA80) /* R/W Device Control IN Endpoint 12 Control Register */ +#define S5P_OTG_DIEPINT12 (USBOTG_LINK_BASE + 0xA88) /* R/W Device IN Endpoint 12 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ12 (USBOTG_LINK_BASE + 0xA90) /* R/W Device IN Endpoint 12 Transfer Size Register */ +#define S5P_OTG_DIEPDMA12 (USBOTG_LINK_BASE + 0xA94) /* R/W Device IN Endpoint 12 DMA Address Register */ +#define S5P_OTG_DIEPCTL13 (USBOTG_LINK_BASE + 0xAA0) /* R/W Device Control IN Endpoint 13 Control Register */ +#define S5P_OTG_DIEPINT13 (USBOTG_LINK_BASE + 0xAA8) /* R/W Device IN Endpoint 13 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ13 (USBOTG_LINK_BASE + 0xAB0) /* R/W Device IN Endpoint 13 Transfer Size Register */ +#define S5P_OTG_DIEPDMA13 (USBOTG_LINK_BASE + 0xAB4) /* R/W Device IN Endpoint 13 DMA Address Register */ +#define S5P_OTG_DIEPCTL14 (USBOTG_LINK_BASE + 0xAC0) /* R/W Device Control IN Endpoint 14 Control Register */ +#define S5P_OTG_DIEPINT14 (USBOTG_LINK_BASE + 0xAC8) /* R/W Device IN Endpoint 14 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ14 (USBOTG_LINK_BASE + 0xAD0) /* R/W Device IN Endpoint 14 Transfer Size Register */ +#define S5P_OTG_DIEPDMA14 (USBOTG_LINK_BASE + 0xAD4) /* R/W Device IN Endpoint 14 DMA Address Register */ +#define S5P_OTG_DIEPCTL15 (USBOTG_LINK_BASE + 0xAE0) /* R/W Device Control IN Endpoint 15 Control Register */ +#define S5P_OTG_DIEPINT15 (USBOTG_LINK_BASE + 0xAE8) /* R/W Device IN Endpoint 15 Interrupt Register */ +#define S5P_OTG_DIEPTSIZ15 (USBOTG_LINK_BASE + 0xAF0) /* R/W Device IN Endpoint 15 Transfer Size Register */ +#define S5P_OTG_DIEPDMA15 (USBOTG_LINK_BASE + 0xAF4) /* R/W Device IN Endpoint 15 DMA Address Register */ + +/* Device Logical OUT Endpoint-Specific Register */ +#define S5P_OTG_DOEPCTL0 (USBOTG_LINK_BASE + 0xB00) /* R/W Device Control OUT Endpoint 0 Control Register */ +#define S5P_OTG_DOEPINT0 (USBOTG_LINK_BASE + 0xB08) /* R/W Device OUT Endpoint 0 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ0 (USBOTG_LINK_BASE + 0xB10) /* R/W Device OUT Endpoint 0 Transfer Size Register */ +#define S5P_OTG_DOEPDMA0 (USBOTG_LINK_BASE + 0xB14) /* R/W Device OUT Endpoint 0 DMA Address Register */ +#define S5P_OTG_DOEPCTL1 (USBOTG_LINK_BASE + 0xB20) /* R/W Device Control OUT Endpoint 1 Control Register */ +#define S5P_OTG_DOEPINT1 (USBOTG_LINK_BASE + 0xB28) /* R/W Device OUT Endpoint 1 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ1 (USBOTG_LINK_BASE + 0xB30) /* R/W Device OUT Endpoint 1 Transfer Size Register */ +#define S5P_OTG_DOEPDMA1 (USBOTG_LINK_BASE + 0xB34) /* R/W Device OUT Endpoint 1 DMA Address Register */ +#define S5P_OTG_DOEPCTL2 (USBOTG_LINK_BASE + 0xB40) /* R/W Device Control OUT Endpoint 2 Control Register */ +#define S5P_OTG_DOEPINT2 (USBOTG_LINK_BASE + 0xB48) /* R/W Device OUT Endpoint 2 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ2 (USBOTG_LINK_BASE + 0xB50) /* R/W Device OUT Endpoint 2 Transfer Size Register */ +#define S5P_OTG_DOEPDMA2 (USBOTG_LINK_BASE + 0xB54) /* R/W Device OUT Endpoint 2 DMA Address Register */ +#define S5P_OTG_DOEPCTL3 (USBOTG_LINK_BASE + 0xB60) /* R/W Device Control OUT Endpoint 3 Control Register */ +#define S5P_OTG_DOEPINT3 (USBOTG_LINK_BASE + 0xB68) /* R/W Device OUT Endpoint 3 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ3 (USBOTG_LINK_BASE + 0xB70) /* R/W Device OUT Endpoint 3 Transfer Size Register */ +#define S5P_OTG_DOEPDMA3 (USBOTG_LINK_BASE + 0xB74) /* R/W Device OUT Endpoint 3 DMA Address Register */ +#define S5P_OTG_DOEPCTL4 (USBOTG_LINK_BASE + 0xB80) /* R/W Device Control OUT Endpoint 4 Control Register */ +#define S5P_OTG_DOEPINT4 (USBOTG_LINK_BASE + 0xB88) /* R/W Device OUT Endpoint 4 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ4 (USBOTG_LINK_BASE + 0xB90) /* R/W Device OUT Endpoint 4 Transfer Size Register */ +#define S5P_OTG_DOEPDMA4 (USBOTG_LINK_BASE + 0xB94) /* R/W Device OUT Endpoint 4 DMA Address Register */ +#define S5P_OTG_DOEPCTL5 (USBOTG_LINK_BASE + 0xBA0) /* R/W Device Control OUT Endpoint 5 Control Register */ +#define S5P_OTG_DOEPINT5 (USBOTG_LINK_BASE + 0xBA8) /* R/W Device OUT Endpoint 5 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ5 (USBOTG_LINK_BASE + 0xBB0) /* R/W Device OUT Endpoint 5 Transfer Size Register */ +#define S5P_OTG_DOEPDMA5 (USBOTG_LINK_BASE + 0xBB4) /* R/W Device OUT Endpoint 5 DMA Address Register */ +#define S5P_OTG_DOEPCTL6 (USBOTG_LINK_BASE + 0xBC0) /* R/W Device Control OUT Endpoint 6 Control Register */ +#define S5P_OTG_DOEPINT6 (USBOTG_LINK_BASE + 0xBC8) /* R/W Device OUT Endpoint 6 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ6 (USBOTG_LINK_BASE + 0xBD0) /* R/W Device OUT Endpoint 6 Transfer Size Register */ +#define S5P_OTG_DOEPDMA6 (USBOTG_LINK_BASE + 0xBD4) /* R/W Device OUT Endpoint 6 DMA Address Register */ +#define S5P_OTG_DOEPCTL7 (USBOTG_LINK_BASE + 0xBE0) /* R/W Device Control OUT Endpoint 7 Control Register */ +#define S5P_OTG_DOEPINT7 (USBOTG_LINK_BASE + 0xBE8) /* R/W Device OUT Endpoint 7 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ7 (USBOTG_LINK_BASE + 0xBF0) /* R/W Device OUT Endpoint 7 Transfer Size Register */ +#define S5P_OTG_DOEPDMA7 (USBOTG_LINK_BASE + 0xBF4) /* R/W Device OUT Endpoint 7 DMA Address Register */ +#define S5P_OTG_DOEPCTL8 (USBOTG_LINK_BASE + 0xC00) /* R/W Device Control OUT Endpoint 8 Control Register */ +#define S5P_OTG_DOEPINT8 (USBOTG_LINK_BASE + 0xC08) /* R/W Device OUT Endpoint 8 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ8 (USBOTG_LINK_BASE + 0xC10) /* R/W Device OUT Endpoint 8 Transfer Size Register */ +#define S5P_OTG_DOEPDMA8 (USBOTG_LINK_BASE + 0xC14) /* R/W Device OUT Endpoint 8 DMA Address Register */ +#define S5P_OTG_DOEPCTL9 (USBOTG_LINK_BASE + 0xC20) /* R/W Device Control OUT Endpoint 9 Control Register */ +#define S5P_OTG_DOEPINT9 (USBOTG_LINK_BASE + 0xC28) /* R/W Device OUT Endpoint 9 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ9 (USBOTG_LINK_BASE + 0xC30) /* R/W Device OUT Endpoint 9 Transfer Size Register */ +#define S5P_OTG_DOEPDMA9 (USBOTG_LINK_BASE + 0xC34) /* R/W Device OUT Endpoint 9 DMA Address Register */ +#define S5P_OTG_DOEPCTL10 (USBOTG_LINK_BASE + 0xC40) /* R/W Device Control OUT Endpoint 10 Control Register */ +#define S5P_OTG_DOEPINT10 (USBOTG_LINK_BASE + 0xC48) /* R/W Device OUT Endpoint 10 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ10 (USBOTG_LINK_BASE + 0xC50) /* R/W Device OUT Endpoint 10 Transfer Size Register */ +#define S5P_OTG_DOEPDMA10 (USBOTG_LINK_BASE + 0xC54) /* R/W Device OUT Endpoint 10 DMA Address Register */ +#define S5P_OTG_DOEPCTL11 (USBOTG_LINK_BASE + 0xC60) /* R/W Device Control OUT Endpoint 11 Control Register */ +#define S5P_OTG_DOEPINT11 (USBOTG_LINK_BASE + 0xC68) /* R/W Device OUT Endpoint 11 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ11 (USBOTG_LINK_BASE + 0xC70) /* R/W Device OUT Endpoint 11 Transfer Size Register */ +#define S5P_OTG_DOEPDMA11 (USBOTG_LINK_BASE + 0xC74) /* R/W Device OUT Endpoint 11 DMA Address Register */ +#define S5P_OTG_DOEPCTL12 (USBOTG_LINK_BASE + 0xC80) /* R/W Device Control OUT Endpoint 12 Control Register */ +#define S5P_OTG_DOEPINT12 (USBOTG_LINK_BASE + 0xC88) /* R/W Device OUT Endpoint 12 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ12 (USBOTG_LINK_BASE + 0xC90) /* R/W Device OUT Endpoint 12 Transfer Size Register */ +#define S5P_OTG_DOEPDMA12 (USBOTG_LINK_BASE + 0xC94) /* R/W Device OUT Endpoint 12 DMA Address Register */ +#define S5P_OTG_DOEPCTL13 (USBOTG_LINK_BASE + 0xCA0) /* R/W Device Control OUT Endpoint 13 Control Register */ +#define S5P_OTG_DOEPINT13 (USBOTG_LINK_BASE + 0xCA8) /* R/W Device OUT Endpoint 13 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ13 (USBOTG_LINK_BASE + 0xCB0) /* R/W Device OUT Endpoint 13 Transfer Size Register */ +#define S5P_OTG_DOEPDMA13 (USBOTG_LINK_BASE + 0xCB4) /* R/W Device OUT Endpoint 13 DMA Address Register */ +#define S5P_OTG_DOEPCTL14 (USBOTG_LINK_BASE + 0xCC0) /* R/W Device Control OUT Endpoint 14 Control Register */ +#define S5P_OTG_DOEPINT14 (USBOTG_LINK_BASE + 0xCC8) /* R/W Device OUT Endpoint 14 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ14 (USBOTG_LINK_BASE + 0xCD0) /* R/W Device OUT Endpoint 14 Transfer Size Register */ +#define S5P_OTG_DOEPDMA14 (USBOTG_LINK_BASE + 0xCD4) /* R/W Device OUT Endpoint 14 DMA Address Register */ +#define S5P_OTG_DOEPCTL15 (USBOTG_LINK_BASE + 0xCE0) /* R/W Device Control OUT Endpoint 15 Control Register */ +#define S5P_OTG_OTG_DOEPINT15 (USBOTG_LINK_BASE + 0xCE8) /* R/W Device OUT Endpoint 15 Interrupt Register */ +#define S5P_OTG_DOEPTSIZ15 (USBOTG_LINK_BASE + 0xCF0) /* R/W Device OUT Endpoint 15 Transfer Size Register */ +#define S5P_OTG_DOEPDMA15 (USBOTG_LINK_BASE + 0xCF4) /* R/W Device OUT Endpoint 15 DMA Address Register */ + +/* Power and Clock Gating Register */ +#define S5P_OTG_PCGCCTL (USBOTG_LINK_BASE + 0xE00) /* R/W Power and Clock Gating Control Register */ + +/* Endpoint FIFO address */ +#define S5P_OTG_EP0_FIFO (USBOTG_LINK_BASE + 0x1000) + +/* USB Global Interrupt Status register(GINTSTS) setting value */ +#define GINTSTS_WkUpInt (1<<31) +#define GINTSTS_OEPInt (1<<19) +#define GINTSTS_IEPInt (1<<18) +#define GINTSTS_EnumDone (1<<13) +#define GINTSTS_USBRst (1<<12) +#define GINTSTS_USBSusp (1<<11) +#define GINTSTS_RXFLvl (1<<4) + +#endif /* _S5PV310_CPU_H */ diff --git a/common/main.c b/common/main.c index 592ce07..4f8e68f 100644 --- a/common/main.c +++ b/common/main.c @@ -68,10 +68,8 @@ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); static const char erase_seq[] = "\b \b"; /* erase sequence */ static const char tab_seq[] = " "; /* used to expand TABs */ -#ifdef CONFIG_BOOT_RETRY_TIME static uint64_t endtime = 0; /* must be set, default is instant timeout */ static int retry_time = -1; /* -1 so can call readline before main_loop */ -#endif #define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) @@ -84,6 +82,20 @@ int do_mdm_init = 0; extern void mdm_init(void); /* defined in board.c */ #endif +int wait_for_ch_timeout(int rel_timeout, uint64_t abs_timeout) +{ + uint64_t etime = abs_timeout; + + if (rel_timeout) + etime = endtick(rel_timeout); + + while (!tstc()) { /* while no incoming data */ + if ((retry_time >= 0) && etime && (get_ticks() > etime)) + return (-2); /* timed out */ + WATCHDOG_RESET(); + } + return 0; +} /*************************************************************************** * Watch for 'delay' seconds for autoboot stop or autoboot delay string. * returns: 0 - no key string, allow autoboot 1 - got key string, abort @@ -685,29 +697,16 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, int esc_len = 0; char esc_save[8]; int init_len = strlen(buf); - int first = 1; + int rc; if (init_len) cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); while (1) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif - if (first && timeout) { - uint64_t etime = endtick(timeout); - - while (!tstc()) { /* while no incoming data */ - if (get_ticks() >= etime) - return -2; /* timed out */ - WATCHDOG_RESET(); - } - first = 0; - } + rc = wait_for_ch_timeout(timeout, endtime); + if (rc < 0) + return rc; + timeout = 0; ichar = getcmd_getch(); @@ -930,9 +929,9 @@ int readline (const char *const prompt) int readline_into_buffer(const char *const prompt, char *buffer, int timeout) { char *p = buffer; + int rc; #ifdef CONFIG_CMDLINE_EDITING unsigned int len = CONFIG_SYS_CBSIZE; - int rc; static int initted = 0; /* @@ -969,13 +968,11 @@ int readline_into_buffer(const char *const prompt, char *buffer, int timeout) col = plen; for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif + rc = wait_for_ch_timeout(timeout, endtime); + if (rc < 0) + return rc; + timeout = 0; + WATCHDOG_RESET(); /* Trigger watchdog, if needed */ #ifdef CONFIG_SHOW_ACTIVITY diff --git a/common/spl/Makefile b/common/spl/Makefile index 5698a23..e1960b8 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -19,6 +19,7 @@ COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o +COBJS-$(CONFIG_SPL_DSU_SUPPORT) += spl_dsu.o endif COBJS := $(sort $(COBJS-y)) diff --git a/common/spl/spl.c b/common/spl/spl.c index 0d829c0..3b484e3 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -205,6 +205,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif break; #endif +#ifdef CONFIG_SPL_DSU_SUPPORT + case BOOT_DEVICE_USB: + spl_dsu_load_image(); + break; +#endif default: debug("SPL: Un-supported Boot Device\n"); hang(); diff --git a/common/spl/spl_dsu.c b/common/spl/spl_dsu.c new file mode 100644 index 0000000..b26a2ea --- /dev/null +++ b/common/spl/spl_dsu.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_DSU_SUPPORT +void spl_dsu_load_image(void) +{ + u32 loadaddr; + u32 size; + int err; + struct image_header *header; + + err = dsudownload(&loadaddr, &size); + + if (err) { + serial_printf("usb download failed"); + hang(); + } + header = (struct image_header *)loadaddr; + spl_parse_image_header(header); + memcpy((void *)spl_image.load_addr, (void *)loadaddr, spl_image.size); +} +#endif diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 8c785ae..9b6d8c5 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -918,7 +918,8 @@ int ahci_init(u32 base) | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; probe_ent->pio_mask = 0x1f; - probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ + probe_ent->udma_mask = 0x3f; /* Fixme,assume to support up to UDMA5 + * as some drives don't support UDMA6 */ probe_ent->mmio_base = base; diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 47f3213..656bf4a 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -144,9 +144,11 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) { - int bank = gpio / GPIO_PER_BANK; - bank *= sizeof(struct s5p_gpio_bank); + int bank; + unsigned g = gpio - s5p_gpio_part_max(gpio); + bank = g / GPIO_PER_BANK; + bank *= sizeof(struct s5p_gpio_bank); return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); } diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a1dd730..65791aa 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS-$(CONFIG_DWMMC) += dw_mmc.o +COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4070d4e..2fc5e90 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -331,7 +331,7 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); - fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + fifo_size = 0x80; if (host->fifoth_val) fifoth_val = host->fifoth_val; else diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c new file mode 100644 index 0000000..55e13bb --- /dev/null +++ b/drivers/mmc/exynos_dw_mmc.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +static char *EXYNOS_NAME = "EXYNOS DWMMC"; + +static void exynos_dwmci_clksel(struct dwmci_host *host) +{ + u32 val; + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3); + + dwmci_writel(host, DWMCI_CLKSEL, val); +} + +int exynos_dwmci_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + /* MPLL = 800MHz + * FSYS DIVS = 0, 2 + * CLK_SEL = 4 800/2/4 = 100MHz + * Set the sclk_mmc such that it generates 100Mhz output + */ + set_mmc_clk(index, 1); + host->name = EXYNOS_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = exynos_dwmci_clksel; + host->dev_index = index; + host->mmc_clk = get_mmc_clk; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 5ffd8c5..1d2fa73 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -669,6 +669,20 @@ int mmc_switch_part(int dev_num, unsigned int part_num) | (part_num & PART_ACCESS_MASK)); } +int mmc_part_bootenable(int dev_num, unsigned int part_num) +{ + struct mmc *mmc = find_mmc_device(dev_num); + + if (!mmc) + return -1; + + return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + (mmc->part_config & ~(BOOT_PART_ENABLE_MASK | PART_ACCESS_MASK)) + | (part_num & PART_ACCESS_MASK) + | ((part_num << 3) & BOOT_PART_ENABLE_MASK) + | BOOT_ACK); +} + int mmc_getcd(struct mmc *mmc) { int cd; diff --git a/drivers/mmc/spl_mmc.c b/drivers/mmc/spl_mmc.c index 753c6a0..07a6226 100644 --- a/drivers/mmc/spl_mmc.c +++ b/drivers/mmc/spl_mmc.c @@ -71,6 +71,7 @@ static void mmc_load_image_fat(struct mmc *mmc) { s32 err; struct image_header *header; + char *payloadname; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); @@ -82,20 +83,27 @@ static void mmc_load_image_fat(struct mmc *mmc) hang(); } - err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + payloadname = CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME; + err = file_fat_read(payloadname, (u8 *)header, sizeof(struct image_header)); - if (err <= 0) - goto end; + if (err <= 0) { + payloadname = "u-boot.bin"; + err = file_fat_read(payloadname, + (u8 *)header, sizeof(struct image_header)); + if (err <= 0) { + goto end; + } + } spl_parse_image_header(header); - err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + err = file_fat_read(payloadname, (u8 *)spl_image.load_addr, 0); end: if (err <= 0) { printf("spl: error reading image %s, err - %d\n", - CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err); + payloadname, err); hang(); } } diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index e3553d6..333c400 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -400,13 +400,13 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis) /* set flow control parameters and store and forward mode */ value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | - XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; writel(value, ®s->core_opmode); /* enable pause frames */ value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) | (1 << XGMAC_CORE_FLOW_PLT_SHIFT) | - XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE; + XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE; writel(value, ®s->flow_control); /* Initialize the descriptor chains */ diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index b331be7..dfdba9f 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -163,8 +163,8 @@ static int pl01x_serial_init(void) } #endif /* Finally, enable the UART */ - writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, - ®s->pl011_cr); + writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | + UART_PL011_CR_RTS, ®s->pl011_cr); return 0; } diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 3c41242..e65125c 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,6 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); @@ -87,8 +91,8 @@ int serial_init_dev(const int dev_index) { struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - /* reset and enable FIFOs, set triggers to the maximum */ - writel(0, &uart->ufcon); + /* enable FIFOs */ + writel(0x1, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); @@ -130,7 +134,8 @@ int serial_getc_dev(const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for character to arrive */ - while (!(readl(&uart->utrstat) & 0x1)) { + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { if (serial_err_check(dev_index, 0)) return 0; } @@ -146,7 +151,7 @@ void serial_putc_dev(const char c, const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for room in the tx FIFO */ - while (!(readl(&uart->utrstat) & 0x2)) { + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (serial_err_check(dev_index, 1)) return; } diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 040eaba..9e4db37 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -47,9 +47,11 @@ COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_SPL_DSU_SUPPORT) += dsuboot.o endif endif +COBJS-y += usbd-otg-hs.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/usb/gadget/core.c b/drivers/usb/gadget/core.c index 46ab3f6..235efbc 100644 --- a/drivers/usb/gadget/core.c +++ b/drivers/usb/gadget/core.c @@ -117,6 +117,7 @@ char *usbd_device_status[] = { /* Descriptor support functions ************************************************************** */ +char *usb_string_NA = "\010\003N\000/\000A\000"; /** * usbd_get_string - find and return a string descriptor @@ -127,6 +128,8 @@ char *usbd_device_status[] = { struct usb_string_descriptor *usbd_get_string (__u8 index) { if (index >= maxstrings) { + if (index == 0xee) + return (struct usb_string_descriptor *)usb_string_NA; return NULL; } return usb_strings[index]; @@ -534,6 +537,11 @@ void urb_append (urb_link * hd, struct urb *urb) /* URB create/destroy functions ***************************************************** */ +#ifdef CONFIG_SPL_BUILD +static struct urb urbpool[10]; +static struct urb *urbp = urbpool; +#endif + /** * usbd_alloc_urb - allocate an URB appropriate for specified endpoint * @device: device instance @@ -550,11 +558,15 @@ struct urb *usbd_alloc_urb (struct usb_device_instance *device, { struct urb *urb; +#ifndef CONFIG_SPL_BUILD if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) { usberr (" F A T A L: malloc(%zu) FAILED!!!!", sizeof (struct urb)); return NULL; } +#else + urb = urbp++; +#endif /* Fill in known fields */ memset (urb, 0, sizeof (struct urb)); diff --git a/drivers/usb/gadget/dsuboot.c b/drivers/usb/gadget/dsuboot.c new file mode 100644 index 0000000..f116c0f --- /dev/null +++ b/drivers/usb/gadget/dsuboot.c @@ -0,0 +1,656 @@ +/* + * Copyright (C) 2011 Linaro + * + * Original based on fastboot.c from omapzoom u-boot and usbtty.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CONFIG_USBD_MANUFACTURER "linaro" +#define CONFIG_USBD_PRODUCT_NAME "dsuboot" +#define DSUBOOT_PRODUCT_NAME "dsuboot" +#define CONFIG_USBD_VENDORID 0x0525 /* netchip id used for many Linux-USB stuff */ +#define CONFIG_USBD_PRODUCTID 0xFFFF +#define CONFIG_DSUBOOT_TRANSFER_BUFFER 0x90000000 +#define CONFIG_DSUBOOT_TRANSFER_BUFFER_SIZE 64*1024*1024 +//#define CONFIG_USBD_DSUBOOT_BULK_PKTSIZE_HS 512 +#define CONFIG_USBD_DSUBOOT_BULK_PKTSIZE_HS 64 + +#define DSUBOOT_INTERFACE_CLASS 0xff +#define DSUBOOT_INTERFACE_SUB_CLASS 0x42 +#define DSUBOOT_INTERFACE_PROTOCOL 0x03 + +#define ERR +#define WARN +/*#define INFO */ +/*#define DEBUG*/ +#define SHOW_DOWNLOAD_PROGRESS + +#ifdef DEBUG +#define DSUBTDBG(fmt,args...)\ + printf("DEBUG: [%s]: %d: \n"fmt, __FUNCTION__, __LINE__,##args) +#else +#define DSUBTDBG(fmt,args...) do{}while(0) +#endif + +#ifdef INFO +#define DSUBTINFO(fmt,args...)\ + printf("INFO: [%s]: "fmt, __FUNCTION__, ##args) +#else +#define DSUBTINFO(fmt,args...) do{}while(0) +#endif + +#ifdef WARN +#define DSUBTWARN(fmt,args...)\ + printf("WARNING: [%s]: "fmt, __FUNCTION__, ##args) +#else +#define DSUBTWARN(fmt,args...) do{}while(0) +#endif + +#ifdef ERR +#define DSUBTERR(fmt,args...)\ + printf("ERROR: [%s]: "fmt, __FUNCTION__, ##args) +#else +#define DSUBTERR(fmt,args...) do{}while(0) +#endif + +/* USB specific */ + +#include + +#if defined(CONFIG_PPC) +#include +#elif defined(CONFIG_OMAP1510) +#include +#elif defined(CONFIG_MUSB_UDC) +#include +#elif defined(CONFIG_PXA27X) +#include +#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) +#include +#endif + +#define STR_LANG 0x00 +#define STR_MANUFACTURER 0x01 +#define STR_PRODUCT 0x02 +#define STR_SERIAL 0x03 +#define STR_CONFIGURATION 0x04 +#define STR_INTERFACE 0x05 +#define STR_COUNT 0x06 + +#define CONFIG_USBD_CONFIGURATION_STR "dsuboot configuration" +#define CONFIG_USBD_INTERFACE_STR "dsuboot interface" + +#define USBDSUBT_BCD_DEVICE 0x0 +#define USBDSUBT_MAXPOWER 0x32 + +#define NUM_CONFIGS 1 +#define NUM_INTERFACES 1 +#define NUM_ENDPOINTS 2 + +#define RX_EP_INDEX 1 +#define TX_EP_INDEX 2 + +struct _dsubt_config_desc { + struct usb_configuration_descriptor configuration_desc; + struct usb_interface_descriptor interface_desc; + struct usb_endpoint_descriptor endpoint_desc[NUM_ENDPOINTS]; +}; + +static int dsubt_handle_response(void); + +/* defined and used by gadget/ep0.c */ +extern struct usb_string_descriptor **usb_strings; + +/* USB Descriptor Strings */ +static char serial_number[28]; /* what should be the length ?, 28 ? */ +static u8 wstr_lang[4] = {4,USB_DT_STRING,0x9,0x4}; +static u8 wstr_manufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)]; +static u8 wstr_product[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)]; +static u8 wstr_serial[2 + 2*(sizeof(serial_number) - 1)]; +static u8 wstr_configuration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)]; +static u8 wstr_interface[2 + 2*(sizeof(CONFIG_USBD_INTERFACE_STR)-1)]; + +/* USB descriptors */ +static struct usb_device_descriptor device_descriptor = { + .bLength = sizeof(struct usb_device_descriptor), + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = cpu_to_le16(USB_BCD_VERSION), + .bDeviceClass = 0xFF, + .bDeviceSubClass = 0xFF, + .bDeviceProtocol = 0xFF, + .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, + .idVendor = cpu_to_le16(CONFIG_USBD_VENDORID), + .idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID), + .bcdDevice = cpu_to_le16(USBDSUBT_BCD_DEVICE), + .iManufacturer = STR_MANUFACTURER, + .iProduct = STR_PRODUCT, + .iSerialNumber = STR_SERIAL, + .bNumConfigurations = NUM_CONFIGS +}; + +static struct _dsubt_config_desc dsubt_config_desc = { + .configuration_desc = { + .bLength = sizeof(struct usb_configuration_descriptor), + .bDescriptorType = USB_DT_CONFIG, + .wTotalLength = cpu_to_le16(sizeof(struct _dsubt_config_desc)), + .bNumInterfaces = NUM_INTERFACES, + .bConfigurationValue = 1, + .iConfiguration = STR_CONFIGURATION, + .bmAttributes = BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED, + .bMaxPower = USBDSUBT_MAXPOWER, + }, + .interface_desc = { + .bLength = sizeof(struct usb_interface_descriptor), + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0x2, + .bInterfaceClass = DSUBOOT_INTERFACE_CLASS, + .bInterfaceSubClass = DSUBOOT_INTERFACE_SUB_CLASS, + .bInterfaceProtocol = DSUBOOT_INTERFACE_PROTOCOL, + .iInterface = STR_INTERFACE, + }, + .endpoint_desc = { + { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = RX_EP_INDEX | USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .bInterval = 0, + }, + { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = TX_EP_INDEX | USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .bInterval = 0, + }, + }, +}; + +static struct usb_interface_descriptor interface_descriptors[NUM_INTERFACES]; +static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS]; + +static struct usb_string_descriptor *dsubt_string_table[STR_COUNT]; +static struct usb_device_instance device_instance[1]; +static struct usb_bus_instance bus_instance[1]; +static struct usb_configuration_instance config_instance[NUM_CONFIGS]; +static struct usb_interface_instance interface_instance[NUM_INTERFACES]; +static struct usb_alternate_instance alternate_instance[NUM_INTERFACES]; +static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS + 1]; + +/* U-boot version */ +extern char version_string[]; + +struct priv_data { + void *transfer_buffer; + int transfer_buffer_size; + char *serial_no; + int flag; + int d_size; + int d_bytes; + int bs; + int exit; + unsigned char *product_name; + int configured; + char response[65]; +}; + +#define FASTBOOT_FLAG_RESPONSE 1 + +static struct priv_data priv = +{ + .transfer_buffer = (void *)CONFIG_DSUBOOT_TRANSFER_BUFFER, + .transfer_buffer_size = CONFIG_DSUBOOT_TRANSFER_BUFFER_SIZE, +}; + +static int dsubt_init_endpoints (void); + +/* USB specific */ + +/* utility function for converting char* to wide string used by USB */ +static void str2wide (char *str, u16 * wide) +{ + int i; + for (i = 0; i < strlen (str) && str[i]; i++){ + #if defined(__LITTLE_ENDIAN) + wide[i] = (u16) str[i]; + #elif defined(__BIG_ENDIAN) + wide[i] = ((u16)(str[i])<<8); + #else + #error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined" + #endif + } +} + +/* dsuboot_init has to be called before this fn to get correct serial string */ +static int dsubt_init_strings(void) +{ + struct usb_string_descriptor *string; + + dsubt_string_table[STR_LANG] = + (struct usb_string_descriptor*)wstr_lang; + + string = (struct usb_string_descriptor *) wstr_manufacturer; + string->bLength = sizeof(wstr_manufacturer); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_MANUFACTURER, string->wData); + dsubt_string_table[STR_MANUFACTURER] = string; + + string = (struct usb_string_descriptor *) wstr_product; + string->bLength = sizeof(wstr_product); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData); + dsubt_string_table[STR_PRODUCT] = string; + + string = (struct usb_string_descriptor *) wstr_serial; + string->bLength = sizeof(wstr_serial); + string->bDescriptorType = USB_DT_STRING; + str2wide (serial_number, string->wData); + dsubt_string_table[STR_SERIAL] = string; + + string = (struct usb_string_descriptor *) wstr_configuration; + string->bLength = sizeof(wstr_configuration); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData); + dsubt_string_table[STR_CONFIGURATION] = string; + + string = (struct usb_string_descriptor *) wstr_interface; + string->bLength = sizeof(wstr_interface); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_INTERFACE_STR, string->wData); + dsubt_string_table[STR_INTERFACE] = string; + + /* Now, initialize the string table for ep0 handling */ + usb_strings = dsubt_string_table; + + return 0; +} + +#define init_wMaxPacketSize(x) le16_to_cpu(get_unaligned(\ + &ep_descriptor_ptrs[(x) - 1]->wMaxPacketSize)); + +static void dsubt_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data) +{ + switch (event) { + case DEVICE_RESET: + case DEVICE_BUS_INACTIVE: + priv.configured = 0; + DSUBTINFO("dsuboot configured = 0\n"); + break; + case DEVICE_CONFIGURED: + priv.configured = 1; + DSUBTINFO("dsuboot configured = 1\n"); + break; + + case DEVICE_ADDRESS_ASSIGNED: + dsubt_init_endpoints (); + DSUBTINFO("dsuboot endpoints init'd\n"); + + default: + break; + } +} + +/* dsuboot_init has to be called before this fn to get correct serial string */ +static int dsubt_init_instances(void) +{ + int i; + + /* initialize device instance */ + memset (device_instance, 0, sizeof (struct usb_device_instance)); + device_instance->device_state = STATE_INIT; + device_instance->device_descriptor = &device_descriptor; + device_instance->event = dsubt_event_handler; + device_instance->cdc_recv_setup = NULL; + device_instance->bus = bus_instance; + device_instance->configurations = NUM_CONFIGS; + device_instance->configuration_instance_array = config_instance; + + /* XXX: what is this bus instance for ?, can't it be removed by moving + endpoint_array and serial_number_str is moved to device instance */ + /* initialize bus instance */ + memset (bus_instance, 0, sizeof (struct usb_bus_instance)); + bus_instance->device = device_instance; + bus_instance->endpoint_array = endpoint_instance; + /* XXX: what is the relevance of max_endpoints & maxpacketsize ? */ + bus_instance->max_endpoints = 1; + bus_instance->maxpacketsize = 64; + bus_instance->serial_number_str = serial_number; + + /* configuration instance */ + memset (config_instance, 0, + sizeof (struct usb_configuration_instance)); + config_instance->interfaces = NUM_INTERFACES; + config_instance->configuration_descriptor = + (struct usb_configuration_descriptor *)&dsubt_config_desc; + config_instance->interface_instance_array = interface_instance; + + /* XXX: is alternate instance required in case of no alternate ? */ + /* interface instance */ + memset (interface_instance, 0, + sizeof (struct usb_interface_instance)); + interface_instance->alternates = 1; + interface_instance->alternates_instance_array = alternate_instance; + + /* alternates instance */ + memset (alternate_instance, 0, + sizeof (struct usb_alternate_instance)); + alternate_instance->interface_descriptor = interface_descriptors; + alternate_instance->endpoints = NUM_ENDPOINTS; + alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs; + + /* endpoint instances */ + memset (&endpoint_instance[0], 0, + sizeof (struct usb_endpoint_instance)); + endpoint_instance[0].endpoint_address = 0; + endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL; + endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL; + /* XXX: following statement to done along with other endpoints + at another place ? */ + udc_setup_ep (device_instance, 0, &endpoint_instance[0]); + + for (i = 1; i <= NUM_ENDPOINTS; i++) { + memset (&endpoint_instance[i], 0, + sizeof (struct usb_endpoint_instance)); + + endpoint_instance[i].endpoint_address = + ep_descriptor_ptrs[i - 1]->bEndpointAddress; + + endpoint_instance[i].rcv_attributes = + ep_descriptor_ptrs[i - 1]->bmAttributes; + + endpoint_instance[i].rcv_packetSize = init_wMaxPacketSize(i); + + endpoint_instance[i].tx_attributes = + ep_descriptor_ptrs[i - 1]->bmAttributes; + + endpoint_instance[i].tx_packetSize = init_wMaxPacketSize(i); + + endpoint_instance[i].tx_attributes = + ep_descriptor_ptrs[i - 1]->bmAttributes; + + urb_link_init (&endpoint_instance[i].rcv); + urb_link_init (&endpoint_instance[i].rdy); + urb_link_init (&endpoint_instance[i].tx); + urb_link_init (&endpoint_instance[i].done); + + if (endpoint_instance[i].endpoint_address & USB_DIR_IN) + endpoint_instance[i].tx_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + else + endpoint_instance[i].rcv_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + } + + return 0; +} + +/* XXX: ep_descriptor_ptrs can be removed by making better use of + dsubt_config_desc.endpoint_desc */ +static int dsubt_init_endpoint_ptrs(void) +{ + ep_descriptor_ptrs[0] = &dsubt_config_desc.endpoint_desc[0]; + ep_descriptor_ptrs[1] = &dsubt_config_desc.endpoint_desc[1]; + + return 0; +} + +static int dsubt_init_endpoints(void) +{ + int i; + + /* XXX: should it be moved to some other function ? */ + bus_instance->max_endpoints = NUM_ENDPOINTS + 1; + + /* XXX: is this for loop required ?, yes for MUSB it is */ + for (i = 1; i <= NUM_ENDPOINTS; i++) { + + /* configure packetsize based on HS negotiation status */ + DSUBTINFO("setting up HS USB device ep%x\n", + endpoint_instance[i].endpoint_address); + ep_descriptor_ptrs[i - 1]->wMaxPacketSize = + CONFIG_USBD_DSUBOOT_BULK_PKTSIZE_HS; + + endpoint_instance[i].tx_packetSize = + le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize); + endpoint_instance[i].rcv_packetSize = + le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize); + + udc_setup_ep (device_instance, i, &endpoint_instance[i]); + + } + + return 0; +} + +static struct urb *next_urb (struct usb_device_instance *device, + struct usb_endpoint_instance *endpoint) +{ + struct urb *current_urb = NULL; + int space; + + /* If there's a queue, then we should add to the last urb */ + if (!endpoint->tx_queue) { + current_urb = endpoint->tx_urb; + } else { + /* Last urb from tx chain */ + current_urb = + p2surround (struct urb, link, endpoint->tx.prev); + } + + /* Make sure this one has enough room */ + space = current_urb->buffer_length - current_urb->actual_length; + if (space > 0) { + return current_urb; + } else { /* No space here */ + /* First look at done list */ + current_urb = first_urb_detached (&endpoint->done); + if (!current_urb) { + current_urb = usbd_alloc_urb (device, endpoint); + } + + urb_append (&endpoint->tx, current_urb); + endpoint->tx_queue++; + } + return current_urb; +} + +static int dsubt_dsuboot_init(void) +{ + priv.flag = 0; + priv.d_size = 0; + priv.exit = 0; + priv.serial_no = (char *)"00123"; + priv.product_name = (unsigned char *)DSUBOOT_PRODUCT_NAME; + priv.bs = 1024; + return 0; +} + +static int dsubt_rx_process(unsigned char *buffer, int length) +{ + /* + * Rather than roll our own protocol we just implement the fastboot + * download command. + * If a dfu or fastboot implementation ever goes mainline then try to share + * code then. + */ + /* Generic failed response */ + strcpy(priv.response, "FAIL"); + + if (!priv.d_size) { + /* command */ + char *cmdbuf = (char *) buffer; + + if(memcmp(cmdbuf, "download:", 9) == 0) { + DSUBTDBG("download\n"); + + /* XXX: need any check for size & bytes ? */ + priv.d_size = + simple_strtoul (cmdbuf + 9, NULL, 16); + priv.d_bytes = 0; + +#ifdef SHOW_DOWNLOAD_PROGRESS + printf("starting download of %d bytes\n", + priv.d_size); +#endif + + if (priv.d_size == 0) { + strcpy(priv.response, "FAILdata invalid size"); + } else if (priv.d_size > + priv.transfer_buffer_size) { + priv.d_size = 0; + strcpy(priv.response, "FAILdata too large"); + } else { + sprintf(priv.response, "DATA%08x", priv.d_size); + } + } + + priv.flag |= FASTBOOT_FLAG_RESPONSE; + } else { + if (length) { + unsigned int xfr_size; + + xfr_size = priv.d_size - priv.d_bytes; + if (xfr_size > length) + xfr_size = length; + memcpy(priv.transfer_buffer + priv.d_bytes, + buffer, xfr_size); + priv.d_bytes += xfr_size; + +#ifdef SHOW_DOWNLOAD_PROGRESS + /* Inform via prompt that download is happening */ + if (! (priv.d_bytes % (16 * priv.bs))) + printf("."); + if (! (priv.d_bytes % (80 * 16 * priv.bs))) + printf("\n"); +#endif + if (priv.d_bytes >= priv.d_size) { + priv.d_size = 0; + strcpy(priv.response, "OKAY"); + priv.flag |= FASTBOOT_FLAG_RESPONSE; +#ifdef SHOW_DOWNLOAD_PROGRESS + printf(".\n"); +#endif + printf("downloaded %d bytes\n", priv.d_bytes); + priv.exit |= 1; + } + } else + DSUBTWARN("empty buffer download\n"); + } + + return 0; +} + +static int dsubt_handle_rx(void) +{ + struct usb_endpoint_instance *ep = &endpoint_instance[RX_EP_INDEX]; + + if (ep->rcv_urb->actual_length) { + DSUBTDBG("rx length: %u\n", ep->rcv_urb->actual_length); + dsubt_rx_process(ep->rcv_urb->buffer, ep->rcv_urb->actual_length); + /* Required to poison rx urb buffer as in omapzoom ?, + yes, as dsuboot command are sent w/o NULL termination. + Attempt is made here to reduce poison length, may be safer + to posion the whole buffer, also it is assumed that at + the time of creation of urb it is poisoned */ + memset(ep->rcv_urb->buffer, 0, ep->rcv_urb->actual_length); + ep->rcv_urb->actual_length = 0; + } + + return 0; +} + +static int dsubt_response_process(void) +{ + struct usb_endpoint_instance *ep = &endpoint_instance[TX_EP_INDEX]; + struct urb *current_urb = NULL; + unsigned char *dest = NULL; + int n, ret = 0; + + current_urb = next_urb (device_instance, ep); + if (!current_urb) { + DSUBTERR("%s: current_urb NULL", __func__); + return -1; + } + + dest = current_urb->buffer + current_urb->actual_length; + n = MIN (64, strlen(priv.response)); + memcpy(dest, priv.response, n); + current_urb->actual_length += n; + DSUBTDBG("response urb length: %u\n", current_urb->actual_length); + if (ep->last == 0) { + ret = udc_endpoint_write (ep); + return ret; + } + + return ret; +} + +static int dsubt_handle_response(void) +{ + if (priv.flag & FASTBOOT_FLAG_RESPONSE) { + dsubt_response_process(); + priv.flag &= ~FASTBOOT_FLAG_RESPONSE; + } + + return 0; +} + +int dsudownload(u32 *loadaddr, u32 *loadsize) +{ + printf("booting from usb peripheral port\n"); + dsubt_dsuboot_init(); + dsubt_init_endpoint_ptrs(); + if (udc_init() < 0) { + DSUBTERR("%s: MUSB UDC init failure\n", __func__); + return -1; + } + dsubt_init_strings(); + dsubt_init_instances(); + + udc_startup_events (device_instance); + udc_connect(); + + DSUBTINFO("dsuboot initialized\n"); + + while(1) { + udc_irq(); + if (priv.configured) { + dsubt_handle_rx(); + dsubt_handle_response(); + } + priv.exit |= ctrlc(); + if (priv.exit) { + printf("dsudownload end\n"); + break; + } + } + + *loadaddr = (u32)priv.transfer_buffer; + *loadsize = priv.d_bytes; + return 0; +} diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index aa8f916..a6ab324 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -196,7 +196,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, /* setup tx urb */ urb->actual_length = 0; - dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type)); + //dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type)); switch (descriptor_type) { case USB_DESCRIPTOR_TYPE_DEVICE: @@ -264,7 +264,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, serial_printf("Invalid string index %d\n", index); return -1; } - dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength); + /*dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength); */ copy_config (urb, string_descriptor, string_descriptor->bLength, max); } break; diff --git a/drivers/usb/gadget/usbd-otg-hs.c b/drivers/usb/gadget/usbd-otg-hs.c new file mode 100644 index 0000000..ec9d349 --- /dev/null +++ b/drivers/usb/gadget/usbd-otg-hs.c @@ -0,0 +1,1936 @@ +/* + * cpu/s5pc1xx/usbd-otg-hs.c + * + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. + * - only support for S5PC100 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_S5PC110) || defined(CONFIG_S5PC210) || defined(CONFIG_S5PC220) || defined(CONFIG_S5P6450) || defined(CONFIG_ARCH_EXYNOS) +#include +#include +#include +#include +#include "../../../common/cpu.h" +#include "usbd-otg-hs.h" + +#if defined(CONFIG_S5P6450) + DECLARE_GLOBAL_DATA_PTR; +#endif + +#undef USB_OTG_DEBUG_SETUP +#ifdef USB_OTG_DEBUG_SETUP +#define DBG_SETUP0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args) +#define DBG_SETUP1(fmt, args...) printf("\t" fmt, ##args) +#define DBG_SETUP2(fmt, args...) printf(fmt, ##args) +#else +#define DBG_SETUP0(fmt, args...) do { } while (0) +#define DBG_SETUP1(fmt, args...) do { } while (0) +#define DBG_SETUP2(fmt, args...) do { } while (0) +#endif + +#undef USB_OTG_DEBUG_BULK +#ifdef USB_OTG_DEBUG_BULK +#define DBG_BULK0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args) +#define DBG_BULK1(fmt, args...) printf("\t" fmt, ##args) +#else +#define DBG_BULK0(fmt, args...) do { } while (0) +#define DBG_BULK1(fmt, args...) do { } while (0) +#endif + +#define USB_CHECKSUM_EN + +#define TRUE 1 +#define FALSE 0 +#define SUSPEND_RESUME_ON FALSE + + +u32 s3c_usbd_dn_addr = 0; +u32 s3c_usbd_dn_cnt = 0; +u32 remode_wakeup; +u16 config_value; + +int DNW; +int is_fastboot = 0; +int s3c_receive_done = 0; +int s3c_got_header = 0; + +USB_OPMODE op_mode = USB_CPU; +USB_SPEED speed = USB_HIGH; + +otg_dev_t otg; +get_status_t get_status; +get_intf_t get_intf; + +enum EP_INDEX +{ + EP0, EP1, EP2, EP3, EP4 +}; + +/*------------------------------------------------*/ +/* EP0 state */ +enum EP0_STATE +{ + EP0_STATE_INIT = 0, + EP0_STATE_GD_DEV_0 = 11, + EP0_STATE_GD_DEV_1 = 12, + EP0_STATE_GD_DEV_2 = 13, + EP0_STATE_GD_CFG_0 = 21, + EP0_STATE_GD_CFG_1 = 22, + EP0_STATE_GD_CFG_2 = 23, + EP0_STATE_GD_CFG_3 = 24, + EP0_STATE_GD_CFG_4 = 25, + EP0_STATE_GD_STR_I0 = 30, + EP0_STATE_GD_STR_I1 = 31, + EP0_STATE_GD_STR_I2 = 32, + EP0_STATE_GD_STR_I3 = 133, + EP0_STATE_GD_DEV_QUALIFIER = 33, + EP0_STATE_INTERFACE_GET = 34, + EP0_STATE_GET_STATUS0 = 35, + EP0_STATE_GET_STATUS1 = 36, + EP0_STATE_GET_STATUS2 = 37, + EP0_STATE_GET_STATUS3 = 38, + EP0_STATE_GET_STATUS4 = 39, + EP0_STATE_GD_OTHER_SPEED = 40, + EP0_STATE_GD_CFG_ONLY_0 = 41, + EP0_STATE_GD_CFG_ONLY_1 = 42, + EP0_STATE_GD_IF_ONLY_0 = 44, + EP0_STATE_GD_IF_ONLY_1 = 45, + EP0_STATE_GD_EP0_ONLY_0 = 46, + EP0_STATE_GD_EP1_ONLY_0 = 47, + EP0_STATE_GD_EP2_ONLY_0 = 48, + EP0_STATE_GD_EP3_ONLY_0 = 49, + EP0_STATE_GD_OTHER_SPEED_HIGH_1 = 51, + EP0_STATE_GD_OTHER_SPEED_HIGH_2 = 52, + EP0_STATE_GD_OTHER_SPEED_HIGH_3 = 53 +}; + +/*definitions related to CSR setting */ + +/* S5P_OTG_GOTGCTL*/ +#define B_SESSION_VALID (0x1<<19) +#define A_SESSION_VALID (0x1<<18) + +/* S5P_OTG_GAHBCFG*/ +#define PTXFE_HALF (0<<8) +#define PTXFE_ZERO (1<<8) +#define NPTXFE_HALF (0<<7) +#define NPTXFE_ZERO (1<<7) +#define MODE_SLAVE (0<<5) +#define MODE_DMA (1<<5) +#define BURST_SINGLE (0<<1) +#define BURST_INCR (1<<1) +#define BURST_INCR4 (3<<1) +#define BURST_INCR8 (5<<1) +#define BURST_INCR16 (7<<1) +#define GBL_INT_UNMASK (1<<0) +#define GBL_INT_MASK (0<<0) + +/* S5P_OTG_GRSTCTL*/ +#define AHB_MASTER_IDLE (1u<<31) +#define CORE_SOFT_RESET (0x1<<0) + +/* S5P_OTG_GINTSTS/S5P_OTG_GINTMSK core interrupt register */ +#define INT_RESUME (1u<<31) +#define INT_DISCONN (0x1<<29) +#define INT_CONN_ID_STS_CNG (0x1<<28) +#define INT_OUT_EP (0x1<<19) +#define INT_IN_EP (0x1<<18) +#define INT_ENUMDONE (0x1<<13) +#define INT_RESET (0x1<<12) +#define INT_SUSPEND (0x1<<11) +#define INT_TX_FIFO_EMPTY (0x1<<5) +#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) +#define INT_SOF (0x1<<3) +#define INT_DEV_MODE (0x0<<0) +#define INT_HOST_MODE (0x1<<1) + +/* S5P_OTG_GRXSTSP STATUS*/ +#define GLOBAL_OUT_NAK (0x1<<17) +#define OUT_PKT_RECEIVED (0x2<<17) +#define OUT_TRNASFER_COMPLETED (0x3<<17) +#define SETUP_TRANSACTION_COMPLETED (0x4<<17) +#define SETUP_PKT_RECEIVED (0x6<<17) + +/* S5P_OTG_DCTL device control register */ +#define NORMAL_OPERATION (0x1<<0) +#define SOFT_DISCONNECT (0x1<<1) +#define TEST_J_MODE (TEST_J<<4) +#define TEST_K_MODE (TEST_K<<4) +#define TEST_SE0_NAK_MODE (TEST_SE0_NAK<<4) +#define TEST_PACKET_MODE (TEST_PACKET<<4) +#define TEST_FORCE_ENABLE_MODE (TEST_FORCE_ENABLE<<4) +#define TEST_CONTROL_FIELD (0x7<<4) + +/* S5P_OTG_DAINT device all endpoint interrupt register */ +#define INT_IN_EP0 (0x1<<0) +#define INT_IN_EP1 (0x1<<1) +#define INT_IN_EP3 (0x1<<3) +#define INT_OUT_EP0 (0x1<<16) +#define INT_OUT_EP2 (0x1<<18) +#define INT_OUT_EP4 (0x1<<20) + +/* S5P_OTG_DIEPCTL0/S5P_OTG_DOEPCTL0 */ +#define DEPCTL_EPENA (0x1<<31) +#define DEPCTL_EPDIS (0x1<<30) +#define DEPCTL_SNAK (0x1<<27) +#define DEPCTL_CNAK (0x1<<26) +#define DEPCTL_CTRL_TYPE (EP_TYPE_CONTROL<<18) +#define DEPCTL_ISO_TYPE (EP_TYPE_ISOCHRONOUS<<18) +#define DEPCTL_BULK_TYPE (EP_TYPE_BULK<<18) +#define DEPCTL_INTR_TYPE (EP_TYPE_INTERRUPT<<18) +#define DEPCTL_USBACTEP (0x1<<15) + +/*ep0 enable, clear nak, next ep0, max 64byte */ +#define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0)) + +/*ep0 enable, clear nak, next ep0, 8byte */ +#define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0)) + +/* DIEPCTLn/DOEPCTLn */ +#define BACK2BACK_SETUP_RECEIVED (0x1<<6) +#define INTKN_TXFEMP (0x1<<4) +#define NON_ISO_IN_EP_TIMEOUT (0x1<<3) +#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) +#define AHB_ERROR (0x1<<2) +#define TRANSFER_DONE (0x1<<0) + + +/* codes representing languages */ +const u8 string_desc0[] = +{ + 4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H, +}; + +const u8 dnw_string_desc1[] = /* Manufacturer */ +{ + (0x14+2), STRING_DESCRIPTOR, + 'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0, + 'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0, +}; + +const u8 dnw_string_desc2[] = /* Product */ +{ + (0x2a+2), STRING_DESCRIPTOR, + 'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0, + '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0, + '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0, + 's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0, + 'D', 0x0 +}; + +/* setting the device qualifier descriptor and a string descriptor */ +const u8 qualifier_desc[] = +{ + 0x0a, /* 0 desc size */ + 0x06, /* 1 desc type (DEVICE_QUALIFIER)*/ + 0x00, /* 2 USB release */ + 0x02, /* 3 => 2.00*/ + 0xFF, /* 4 class */ + 0x00, /* 5 subclass */ + 0x00, /* 6 protocol */ + 64, /* 7 max pack size */ + 0x01, /* 8 number of other-speed configuration */ + 0x00, /* 9 reserved */ +}; + +const u8 config_full[] = +{ + 0x09, /* 0 desc size */ + 0x07, /* 1 desc type (other speed)*/ + 0x20, /* 2 Total length of data returned */ + 0x00, /* 3 */ + 0x01, /* 4 Number of interfaces supported by this speed configuration */ + 0x01, /* 5 value to use to select configuration */ + 0x00, /* 6 index of string desc */ + /* 7 same as configuration desc */ + CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED, + 0x19, /* 8 same as configuration desc */ + +}; + +const u8 config_full_total[] = +{ + 0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19, + 0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00, + 0x07 ,0x05 ,0x83 ,0x02 ,0x40 ,0x00 ,0x00, + 0x07 ,0x05 ,0x04 ,0x02 ,0x40 ,0x00 ,0x00 +}; + +const u8 config_high[] = +{ + 0x09, /* 0 desc size */ + 0x07, /* 1 desc type (other speed)*/ + 0x20, /* 2 Total length of data returned */ + 0x00, /* 3 */ + 0x01, /* 4 Number of interfaces supported by this speed configuration */ + 0x01, /* 5 value to use to select configuration */ + 0x00, /* 6 index of string desc */ + /* 7 same as configuration desc */ + CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED, + 0x19, /* 8 same as configuration desc */ + +}; + +const u8 config_high_total[] = +{ + 0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19, + 0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00, + 0x07 ,0x05 ,0x81 ,0x02 ,0x00 ,0x02 ,0x00, + 0x07 ,0x05 ,0x02 ,0x02 ,0x00 ,0x02 ,0x00 +}; + +/* Descriptor size */ +enum DESCRIPTOR_SIZE +{ + DEVICE_DESC_SIZE = sizeof(device_desc_t), + CONFIG_DESC_SIZE = sizeof(config_desc_t), + INTERFACE_DESC_SIZE = sizeof(intf_desc_t), + ENDPOINT_DESC_SIZE = sizeof(ep_desc_t), + DEVICE_QUALIFIER_SIZE = sizeof(qualifier_desc), + OTHER_SPEED_CFG_SIZE = 9 + +}; + +/*32 +++*/ +#define CONFIG_DESC_TOTAL_SIZE \ + (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2) +#define TEST_PKT_SIZE 53 + +u8 test_pkt [TEST_PKT_SIZE] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /*JKJKJKJK x 9*/ + 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, /*JJKKJJKK x 8*/ + 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, /*JJJJKKKK x 8*/ + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, /*JJJJJJJKKKKKKK x8 - '1'*/ + 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, /*'1' + JJJJJJJK x 8*/ + 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E /*{JKKKKKKK x 10},JK*/ +}; + +int s3c_usbctl_init(void); +void s3c_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize); +void s3c_usb_write_in_fifo(u8 *buf, int num); +void s3c_usb_read_out_fifo(u8 *buf, int num); + + +void s3c_usb_init_phy(void) +{ +#if defined(CONFIG_ARCH_EXYNOS5) + writel(0x0, USB_CFG_REG); + writel(0x7454, EXYNOS5_OTG_SYS); + udelay(10); + writel(0x0454, EXYNOS5_OTG_SYS); + udelay(10); +#else /* EXYNOS4 or under */ +#if defined(CONFIG_S5PC110) + writel(0xa0, S5P_OTG_PHYPWR); + writel(0x3, S5P_OTG_PHYCLK); +#elif defined(CONFIG_S5PC220) + writel(0x0, USB_CFG_REG); + writel(0x7f80, S5P_OTG_PHYPWR); + writel(0x5, S5P_OTG_PHYCLK); +#elif defined(CONFIG_S5PC210) + writel(0x1f80, S5P_OTG_PHYPWR); + writel(0x3, S5P_OTG_PHYCLK); +#elif defined(CONFIG_S5P6450) + writel(0xa0, S5P_OTG_PHYPWR); + writel(0x21, S5P_OTG_PHYCLK); +#endif + writel(0x1, S5P_OTG_RSTCON); + udelay(10); + writel(0x0, S5P_OTG_RSTCON); + udelay(10); +#endif +} + +/* OTG PHY Power Off */ +void s3c_usb_phy_off(void) { +#if defined(CONFIG_ARCH_EXYNOS5) + writel(0x145F, EXYNOS5_OTG_SYS); +#else + writel(readl(S5P_OTG_PHYPWR)|(0x18), S5P_OTG_PHYPWR); +#endif +#if !defined(CONFIG_S5P6450) + writel(readl(USB_PHY_CONTROL)&~(1<<0), USB_PHY_CONTROL); +#else + writel(readl(OTHERS)|(1<<16), OTHERS); +#endif +} + +void s3c_usb_core_soft_reset(void) +{ + u32 tmp; + + writel(CORE_SOFT_RESET, S5P_OTG_GRSTCTL); + + do + { + tmp = readl(S5P_OTG_GRSTCTL); + }while(!(tmp & AHB_MASTER_IDLE)); + +} + +void s3c_usb_wait_cable_insert(void) +{ + u32 tmp; + int ucFirst=1; + + do { + udelay(50); + + tmp = readl(S5P_OTG_GOTGCTL); + + if (tmp & (B_SESSION_VALID|A_SESSION_VALID)) { + printf("OTG cable Connected!\n"); + break; + } else if(ucFirst == 1) { + printf("Insert a OTG cable into the connector!\n"); + ucFirst = 0; + } + } while(1); +} + +void s3c_usb_init_core(void) +{ + writel(PTXFE_HALF|NPTXFE_HALF|MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK, + S5P_OTG_GAHBCFG); + + writel( 0<<15 /* PHY Low Power Clock sel */ + |1<<14 /* Non-Periodic TxFIFO Rewind Enable */ + |0x5<<10 /* Turnaround time */ + |0<<9 /* 0:HNP disable, 1:HNP enable */ + |0<<8 /* 0:SRP disable, 1:SRP enable */ + |0<<7 /* ULPI DDR sel */ + |0<<6 /* 0: high speed utmi+, 1: full speed serial */ + |0<<4 /* 0: utmi+, 1:ulpi */ + |1<<3 /* phy i/f 0:8bit, 1:16bit */ + |0x7<<0, /* HS/FS Timeout**/ + S5P_OTG_GUSBCFG ); +} + +void s3c_usb_check_current_mode(u8 *pucMode) +{ + u32 tmp; + + tmp = readl(S5P_OTG_GINTSTS); + *pucMode = tmp & 0x1; +} + +void s3c_usb_set_soft_disconnect(void) +{ + u32 tmp; + + tmp = readl(S5P_OTG_DCTL); + tmp |= SOFT_DISCONNECT; + writel(tmp, S5P_OTG_DCTL); +} + +void s3c_usb_clear_soft_disconnect(void) +{ + u32 tmp; + + tmp = readl(S5P_OTG_DCTL); + tmp &= ~SOFT_DISCONNECT; + writel(tmp, S5P_OTG_DCTL); +} + +void s3c_usb_init_device(void) +{ + writel(1<<18|otg.speed<<0, S5P_OTG_DCFG); /* [][1: full speed(30Mhz) 0:high speed]*/ + + writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE| + INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY, + S5P_OTG_GINTMSK); /*gint unmask */ +} + +int s3c_usbctl_init(void) +{ + u8 ucMode; + + DBG_SETUP0("USB Control Init\n"); +#if defined(CONFIG_S5PC110)||defined(CONFIG_S5PV310) || defined(CONFIG_S5PC210) || defined(CONFIG_S5PC220) || defined(CONFIG_ARCH_EXYNOS) + writel(readl(USB_PHY_CONTROL)|(1<<0), USB_PHY_CONTROL); /*USB PHY0 Enable */ // c110 +#elif defined(CONFIG_S5PC100) + writel(readl(OTHERS)|~(1<<16), OTHERS); +#elif defined(CONFIG_S5P6450) + writel(readl(OTHERS)&~(1<<16), OTHERS); +#else +#error "* CFG_ERROR : you have to select proper CPU for Android Fastboot" +#endif + + otg.speed = speed; + otg.set_config = 0; + otg.ep0_state = EP0_STATE_INIT; + otg.ep0_substate = 0; + s3c_usb_init_phy(); + s3c_usb_core_soft_reset(); + s3c_usb_wait_cable_insert(); + s3c_usb_init_core(); + s3c_usb_check_current_mode(&ucMode); + is_fastboot = 0; + + if (ucMode == INT_DEV_MODE) { + s3c_usb_set_soft_disconnect(); + udelay(10); + s3c_usb_clear_soft_disconnect(); + s3c_usb_init_device(); + return 0; + } else { + printf("Error : Current Mode is Host\n"); + return 0; + } +} + +int s3c_usbc_activate (void) +{ + /* dont used in usb high speed, but used in common file cmd_usbd.c */ + return 0; +} + +int s3c_usb_stop (void) +{ + /* dont used in usb high speed, but used in common file cmd_usbd.c */ + s3c_usb_core_soft_reset(); + s3c_usb_phy_off(); + return 0; +} + +void s3c_usb_print_pkt(u8 *pt, u8 count) +{ + int i; + printf("[s3c_usb_print_pkt:"); + + for(i=0;i MEM:%x DNW:%x\n",checkSum,dnCS); + printf("Checksum failed.\n\n"); + } + +} + +void s3c_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize) +{ + if(type == EP_TYPE_CONTROL) + { + writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ0); + } + else if(type == EP_TYPE_BULK) + { + writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ_IN); + } +} + +void s3c_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize) +{ + if(type == EP_TYPE_CONTROL) + { + writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ0); + } + else if(type == EP_TYPE_BULK) + { + writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ_OUT); + } +} + +void s3c_usb_write_ep0_fifo(u8 *buf, int num) +{ + int i; + u32 Wr_Data=0; + + DBG_SETUP1("[s3c_usb_write_ep0_fifo:"); + + for(i=0;i>8); + buf[i+2] = (u8)(data>>16); + buf[i+3] = (u8)(data>>24); + } +} + +void s3c_usb_get_desc(void) +{ + switch (otg.dev_req.wValue_H) { + case DEVICE_DESCRIPTOR: + otg.req_length = (u32)((otg.dev_req.wLength_H << 8) | + otg.dev_req.wLength_L); + DBG_SETUP1("DEVICE_DESCRIPTOR = 0x%x \n",otg.req_length); + otg.ep0_state = EP0_STATE_GD_DEV_0; + break; + + case CONFIGURATION_DESCRIPTOR: + otg.req_length = (u32)((otg.dev_req.wLength_H << 8) | + otg.dev_req.wLength_L); + DBG_SETUP1("CONFIGURATION_DESCRIPTOR = 0x%x \n",otg.req_length); + + /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */ + if (otg.req_length > CONFIG_DESC_SIZE){ + otg.ep0_state = EP0_STATE_GD_CFG_0; + } else + otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0; + break; + + case STRING_DESCRIPTOR : + DBG_SETUP1("STRING_DESCRIPTOR \n"); + + switch(otg.dev_req.wValue_L) { + case 0: + otg.ep0_state = EP0_STATE_GD_STR_I0; + break; + case 1: + otg.ep0_state = EP0_STATE_GD_STR_I1; + break; + case 2: + otg.ep0_state = EP0_STATE_GD_STR_I2; + break; + case 3: + otg.ep0_state = EP0_STATE_GD_STR_I3; + break; + default: + break; + } + break; + + case ENDPOINT_DESCRIPTOR: + DBG_SETUP1("ENDPOINT_DESCRIPTOR \n"); + switch(otg.dev_req.wValue_L&0xf) { + case 0: + otg.ep0_state=EP0_STATE_GD_EP0_ONLY_0; + break; + case 1: + otg.ep0_state=EP0_STATE_GD_EP1_ONLY_0; + break; + default: + break; + } + break; + + case DEVICE_QUALIFIER: + otg.req_length = (u32)((otg.dev_req.wLength_H << 8) | + otg.dev_req.wLength_L); + DBG_SETUP1("DEVICE_QUALIFIER = 0x%x \n",otg.req_length); + otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER; + break; + + case OTHER_SPEED_CONFIGURATION : + DBG_SETUP1("OTHER_SPEED_CONFIGURATION \n"); + otg.req_length = (u32)((otg.dev_req.wLength_H << 8) | + otg.dev_req.wLength_L); + otg.ep0_state = EP0_STATE_GD_OTHER_SPEED; + break; + + } +} + +void s3c_usb_clear_feature(void) +{ + switch (otg.dev_req.bmRequestType) { + case DEVICE_RECIPIENT: + DBG_SETUP1("DEVICE_RECIPIENT \n"); + if (otg.dev_req.wValue_L == 1) + remode_wakeup = FALSE; + break; + + case ENDPOINT_RECIPIENT: + DBG_SETUP1("ENDPOINT_RECIPIENT \n"); + if (otg.dev_req.wValue_L == 0) { + if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP) + get_status.ep_ctrl= 0; + + /* IN Endpoint */ + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP) + get_status.ep_in= 0; + + /* OUT Endpoint */ + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP) + get_status.ep_out= 0; + } + break; + + default: + DBG_SETUP1("\n"); + break; + } + otg.ep0_state = EP0_STATE_INIT; + +} + +void s3c_usb_set_feature(void) +{ + u32 tmp; + + switch (otg.dev_req.bmRequestType) { + case DEVICE_RECIPIENT: + DBG_SETUP1("DEVICE_RECIPIENT \n"); + if (otg.dev_req.wValue_L == 1) + remode_wakeup = TRUE; + break; + + case ENDPOINT_RECIPIENT: + DBG_SETUP1("ENDPOINT_RECIPIENT \n"); + if (otg.dev_req.wValue_L == 0) { + if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP) + get_status.ep_ctrl= 1; + + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP) + get_status.ep_in= 1; + + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP) + get_status.ep_out= 1; + } + break; + + default: + DBG_SETUP1("\n"); + break; + } + + switch (otg.dev_req.wValue_L) { + case EP_STALL: + /* TBD: additional processing if required */ + break; + + case TEST_MODE: + if ((0 != otg.dev_req.wIndex_L ) ||(0 != otg.dev_req.bmRequestType)) + break; + + /* Set TEST MODE*/ + tmp = readl(S5P_OTG_DCTL); + tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_FORCE_ENABLE_MODE); + writel(tmp, S5P_OTG_DCTL); + + switch(otg.dev_req.wIndex_H) { + case TEST_J: + /*Set Test J*/ + tmp = readl(S5P_OTG_DCTL); + tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_J_MODE); + writel(tmp, S5P_OTG_DCTL); + break; + + case TEST_K: + /*Set Test K*/ + tmp = readl(S5P_OTG_DCTL); + tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_K_MODE); + writel(tmp, S5P_OTG_DCTL); + break; + + case TEST_SE0_NAK: + /*Set Test SE0NAK*/ + tmp = readl(S5P_OTG_DCTL); + tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_SE0_NAK_MODE); + writel(tmp, S5P_OTG_DCTL); + break; + + case TEST_PACKET: + DBG_SETUP1 ("Test_packet\n"); + writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0); + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, TEST_PKT_SIZE); + s3c_usb_write_ep0_fifo(test_pkt, TEST_PKT_SIZE); + tmp = readl(S5P_OTG_DCTL); + tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_PACKET_MODE); + writel(tmp, S5P_OTG_DCTL); + DBG_SETUP1 ("S5P_OTG_DCTL=0x%08x\n", tmp); + break; + } + break; + + default: + break; + } + otg.ep0_state = EP0_STATE_INIT; +} + +void s3c_usb_get_status(void) +{ + switch(otg.dev_req.bmRequestType) { + case (0x80): /*device */ + DBG_SETUP1("DEVICE\n"); + get_status.Device=((u8)remode_wakeup<<1)|0x1; /* SelfPowered */ + otg.ep0_state = EP0_STATE_GET_STATUS0; + break; + + case (0x81): /*interface */ + DBG_SETUP1("INTERFACE\n"); + get_status.Interface=0; + otg.ep0_state = EP0_STATE_GET_STATUS1; + break; + + case (0x82): /*endpoint */ + DBG_SETUP1("ENDPOINT\n"); + if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP) + otg.ep0_state = EP0_STATE_GET_STATUS2; + + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP) + otg.ep0_state = EP0_STATE_GET_STATUS3; + + if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP) + otg.ep0_state = EP0_STATE_GET_STATUS4; + break; + + default: + DBG_SETUP1("\n"); + break; + } +} + +void s3c_usb_ep0_int_hndlr(void) +{ + u16 i; + u32 buf[2]={0x0000, }; + u16 addr; + + DBG_SETUP0("Event EP0\n"); + + if (otg.ep0_state == EP0_STATE_INIT) { + + for(i=0;i<2;i++) + buf[i] = readl(S5P_OTG_EP0_FIFO); + + otg.dev_req.bmRequestType = buf[0]; + otg.dev_req.bRequest = buf[0]>>8; + otg.dev_req.wValue_L = buf[0]>>16; + otg.dev_req.wValue_H = buf[0]>>24; + otg.dev_req.wIndex_L = buf[1]; + otg.dev_req.wIndex_H = buf[1]>>8; + otg.dev_req.wLength_L = buf[1]>>16; + otg.dev_req.wLength_H = buf[1]>>24; + +#ifdef USB_OTG_DEBUG_SETUP + s3c_usb_print_pkt((u8 *)&otg.dev_req, 8); +#endif + + switch (otg.dev_req.bRequest) { + case STANDARD_SET_ADDRESS: + /* Set Address Update bit */ + addr = (otg.dev_req.wValue_L); + writel(1<<18|addr<<4|otg.speed<<0, S5P_OTG_DCFG); + DBG_SETUP1("S5P_OTG_DCFG : %x, STANDARD_SET_ADDRESS : %d\n", + readl(S5P_OTG_DCFG), addr); + otg.ep0_state = EP0_STATE_INIT; + break; + + case STANDARD_SET_DESCRIPTOR: + DBG_SETUP1("STANDARD_SET_DESCRIPTOR \n"); + break; + + case STANDARD_SET_CONFIGURATION: + DBG_SETUP1("STANDARD_SET_CONFIGURATION \n"); + /* Configuration value in configuration descriptor */ + config_value = otg.dev_req.wValue_L; + otg.set_config = 1; + otg.ep0_state = EP0_STATE_INIT; + break; + + case STANDARD_GET_CONFIGURATION: + DBG_SETUP1("STANDARD_GET_CONFIGURATION \n"); + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1); + + /*ep0 enable, clear nak, next ep0, 8byte */ + writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0); + writel(config_value, S5P_OTG_EP0_FIFO); + otg.ep0_state = EP0_STATE_INIT; + break; + + case STANDARD_GET_DESCRIPTOR: + DBG_SETUP1("STANDARD_GET_DESCRIPTOR :"); + s3c_usb_get_desc(); + break; + + case STANDARD_CLEAR_FEATURE: + DBG_SETUP1("STANDARD_CLEAR_FEATURE :"); + s3c_usb_clear_feature(); + break; + + case STANDARD_SET_FEATURE: + DBG_SETUP1("STANDARD_SET_FEATURE :"); + s3c_usb_set_feature(); + break; + + case STANDARD_GET_STATUS: + DBG_SETUP1("STANDARD_GET_STATUS :"); + s3c_usb_get_status(); + break; + + case STANDARD_GET_INTERFACE: + DBG_SETUP1("STANDARD_GET_INTERFACE \n"); + otg.ep0_state = EP0_STATE_INTERFACE_GET; + break; + + case STANDARD_SET_INTERFACE: + DBG_SETUP1("STANDARD_SET_INTERFACE \n"); + get_intf.AlternateSetting= otg.dev_req.wValue_L; + otg.ep0_state = EP0_STATE_INIT; + break; + + case STANDARD_SYNCH_FRAME: + DBG_SETUP1("STANDARD_SYNCH_FRAME \n"); + otg.ep0_state = EP0_STATE_INIT; + break; + + default: + break; + } + } + + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize); + + /*clear nak, next ep0, 64byte */ + writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0); + +} + +void s3c_usb_set_otherspeed_conf_desc(u32 length) +{ + /* Standard device descriptor */ + if (length ==9) + { + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9); + writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0); + s3c_usb_write_ep0_fifo(((u8 *)&config_full)+0, 9); + } + else if(length ==32) + { + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32); + writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0); + s3c_usb_write_ep0_fifo(((u8 *)&config_full_total)+0, 32); + + } + otg.ep0_state = EP0_STATE_INIT; +} + +void s3c_usb_transfer_ep0(void) +{ + const u8 *string_desc1, *string_desc2, *string_desc3; + u32 string_desc1_size, string_desc2_size, string_desc3_size; + + if (is_fastboot) { +/* string_desc1 = fboot_string_desc1; + string_desc2 = fboot_string_desc2; + string_desc3 = fboot_string_desc3; + + string_desc1_size = sizeof(fboot_string_desc1); + string_desc2_size = sizeof(fboot_string_desc2); + string_desc3_size = sizeof(fboot_string_desc3); +*/ } else { + string_desc1 = dnw_string_desc1; + string_desc2 = dnw_string_desc2; + string_desc3 = dnw_string_desc2; + + string_desc1_size = sizeof(dnw_string_desc1); + string_desc2_size = sizeof(dnw_string_desc2); + string_desc3_size = sizeof(dnw_string_desc2); + } + + DBG_SETUP0("otg.ep0_state = %d\n", otg.ep0_state); + + switch (otg.ep0_state) { + case EP0_STATE_INIT: + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0); + + /*ep0 enable, clear nak, next ep0, 8byte */ + writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0); + DBG_SETUP1("EP0_STATE_INIT\n"); + break; + + /* GET_DESCRIPTOR:DEVICE */ + case EP0_STATE_GD_DEV_0: + DBG_SETUP1("EP0_STATE_GD_DEV_0 :"); + + /*ep0 enable, clear nak, next ep0, max 64byte */ + writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0); + if (otg.req_length < DEVICE_DESC_SIZE) { + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length); + s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, otg.req_length); + } else { + s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, DEVICE_DESC_SIZE); + s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, DEVICE_DESC_SIZE); + } + otg.ep0_state = EP0_STATE_INIT; + break; + + /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */ + case EP0_STATE_GD_CFG_0: + DBG_SETUP1("EP0_STATE_GD_CFG_0 :"); + writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0); + if(otg.req_length otg.bulkin_max_pktsize) { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.bulkin_max_pktsize); + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); + + s3c_usb_write_in_fifo(bulkin_buf, otg.bulkin_max_pktsize); + + otg.up_ptr += otg.bulkin_max_pktsize; + + while(readl(S5P_OTG_DIEPCTL_IN) & (1<<31)); + } else if(remain_cnt > 0) { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, remain_cnt); + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); + + s3c_usb_write_in_fifo(bulkin_buf, remain_cnt); + + otg.up_ptr += remain_cnt; + + while(readl(S5P_OTG_DIEPCTL_IN) & (1<<31)); + } else { /*remain_cnt = 0*/ + writel((DEPCTL_SNAK|DEPCTL_BULK_TYPE), S5P_OTG_DIEPCTL_IN); + } +} + +void s3c_usb_upload_start(void) +{ + u8 tmp_buf[12]; + u32 check; + + s3c_usb_read_out_fifo((u8 *)tmp_buf, 10); + check = *((u8 *)(tmp_buf+8)) + (*((u8 *)(tmp_buf+9))<<8); + + if (check==0x1) { + otg.up_addr = + *((u8 *)(tmp_buf+0))+ + (*((u8 *)(tmp_buf+1))<<8)+ + (*((u8 *)(tmp_buf+2))<<16)+ + (*((u8 *)(tmp_buf+3))<<24); + + otg.up_size = + *((u8 *)(tmp_buf+4))+ + (*((u8 *)(tmp_buf+5))<<8)+ + (*((u8 *)(tmp_buf+6))<<16)+ + (*((u8 *)(tmp_buf+7))<<24); + + otg.up_ptr=(u8 *)otg.up_addr; + DBG_BULK1("UploadAddress : 0x%x, UploadSize: %d\n", + otg.up_addr, otg.up_size); + + if (otg.op_mode == USB_CPU) { + if (otg.up_size > otg.bulkin_max_pktsize) { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, + otg.bulkin_max_pktsize); + } else { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, + otg.up_size); + } + + /*ep1 enable, clear nak, bulk, usb active, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); + } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) { + u32 pktcnt, remainder; + + DBG_BULK1("Dma Start for IN PKT \n"); + + writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK, + S5P_OTG_GAHBCFG); + writel(INT_RESUME|INT_OUT_EP|INT_IN_EP| INT_ENUMDONE| + INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK); + + writel((u32)otg.up_ptr, S5P_OTG_DIEPDMA_IN); + + pktcnt = (u32)(otg.up_size/otg.bulkin_max_pktsize); + remainder = (u32)(otg.up_size%otg.bulkin_max_pktsize); + if(remainder != 0) { + pktcnt += 1; + } + + if (pktcnt > 1023) { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023, + (otg.bulkin_max_pktsize*1023)); + } else { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt, + otg.up_size); + } + + /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */ + writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11| + otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); + } + } + otg.dn_filesize=0; +} + +void s3c_usb_download_start(u32 fifo_cnt_byte) +{ + u8 tmp_buf[8]; + + s3c_usb_read_out_fifo((u8 *)tmp_buf, 8); + DBG_BULK1("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n", + fifo_cnt_byte); + + otg.dn_addr=s3c_usbd_dn_addr; + otg.dn_filesize= + *((u8 *)(tmp_buf+4))+ + (*((u8 *)(tmp_buf+5))<<8)+ + (*((u8 *)(tmp_buf+6))<<16)+ + (*((u8 *)(tmp_buf+7))<<24); + + otg.dn_ptr=(u8 *)otg.dn_addr; + DBG_BULK1("downloadAddress : 0x%x, downloadFileSize: %x\n", + otg.dn_addr, otg.dn_filesize); + + /* The first 8-bytes are deleted.*/ + s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte-8); + otg.dn_ptr += fifo_cnt_byte-8; + + if (otg.op_mode == USB_CPU) { + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, + otg.bulkout_max_pktsize); + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0, + S5P_OTG_DOEPCTL_OUT); + } else if (otg.dn_filesize>otg.bulkout_max_pktsize) { + u32 pkt_cnt, remain_cnt; + + DBG_BULK1("downloadFileSize!=0, Dma Start for 2nd OUT PKT \n"); + writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE| + INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK); /*gint unmask */ + writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK, + S5P_OTG_GAHBCFG); + writel((u32)otg.dn_ptr, S5P_OTG_DOEPDMA_OUT); + pkt_cnt = (u32)(otg.dn_filesize-otg.bulkout_max_pktsize)/otg.bulkout_max_pktsize; + remain_cnt = (u32)((otg.dn_filesize-otg.bulkout_max_pktsize)%otg.bulkout_max_pktsize); + if(remain_cnt != 0) { + pkt_cnt += 1; + } + + if (pkt_cnt > 1023) { + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023, + (otg.bulkout_max_pktsize*1023)); + } else { + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt, + (otg.dn_filesize-otg.bulkout_max_pktsize)); + } + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0, + S5P_OTG_DOEPCTL_OUT); + } +} + +void s3c_usb_download_continue(u32 fifo_cnt_byte) +{ + if (otg.op_mode == USB_CPU) { + s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte); + otg.dn_ptr += fifo_cnt_byte; + DBG_BULK1("downloadFileSize!=0, 2nd BYTE_READ_CNT_REG = 0x%x, m_pDownPt = 0x%x\n", + fifo_cnt_byte, otg.dn_ptr); + + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize); + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0, + S5P_OTG_DOEPCTL_OUT); + + /* USB format : addr(4)+size(4)+data(n)+cs(2) */ + if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize - 8)) { + printf("Download Done!! Download Address: 0x%x, Download Filesize:0x%x\n", + otg.dn_addr, (otg.dn_filesize-10)); + + s3c_usbd_dn_cnt = otg.dn_filesize-10; + s3c_usbd_dn_addr = otg.dn_addr; + +#ifdef USB_CHECKSUM_EN + s3c_usb_verify_checksum(); +#endif + s3c_receive_done = 1; + } + + }\ +} + +void s3c_usb_int_bulkout(u32 fifo_cnt_byte) +{ + DBG_BULK0("Bulk Out Function : otg.dn_filesize=0x%x\n", otg.dn_filesize); + if (otg.dn_filesize==0) { + if (fifo_cnt_byte == 10) { + s3c_usb_upload_start(); + } else { + s3c_usb_download_start(fifo_cnt_byte); + } + } else { + s3c_usb_download_continue(fifo_cnt_byte); + } +} + +void s3c_usb_dma_in_done(void) +{ + s32 remain_cnt; + + DBG_BULK0("DMA IN : Transfer Done\n"); + + otg.up_ptr = (u8 *)readl(S5P_OTG_DIEPDMA_IN); + remain_cnt = otg.up_size- ((u32)otg.up_ptr - otg.up_addr); + + if (remain_cnt>0) { + u32 pktcnt, remainder; + pktcnt = (u32)(remain_cnt/otg.bulkin_max_pktsize); + remainder = (u32)(remain_cnt%otg.bulkin_max_pktsize); + if(remainder != 0) { + pktcnt += 1; + } + DBG_SETUP1("remain_cnt : %d \n", remain_cnt); + if (pktcnt> 1023) { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023, + (otg.bulkin_max_pktsize*1023)); + } else { + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt, + remain_cnt); + } + + /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */ + writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11|otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); + } else + DBG_SETUP1("DMA IN : Transfer Complete\n"); +} + +void s3c_usb_dma_out_done(void) +{ + s32 remain_cnt; + + DBG_BULK1("DMA OUT : Transfer Done\n"); + otg.dn_ptr = (u8 *)readl(S5P_OTG_DOEPDMA_OUT); + + remain_cnt = otg.dn_filesize - ((u32)otg.dn_ptr - otg.dn_addr + 8); + + if (remain_cnt>0) { + u32 pktcnt, remainder; + pktcnt = (u32)(remain_cnt/otg.bulkout_max_pktsize); + remainder = (u32)(remain_cnt%otg.bulkout_max_pktsize); + if(remainder != 0) { + pktcnt += 1; + } + DBG_BULK1("remain_cnt : %d \n", remain_cnt); + if (pktcnt> 1023) { + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023, + (otg.bulkout_max_pktsize*1023)); + } else { + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt, + remain_cnt); + } + + /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0, + S5P_OTG_DOEPCTL_OUT); + } else { + DBG_BULK1("DMA OUT : Transfer Complete\n"); + udelay(500); /*for FPGA ???*/ + } +} + +void s3c_usb_set_all_outep_nak(void) +{ + u8 i; + u32 tmp; + + for(i=0;i<16;i++) + { + tmp = readl(S5P_OTG_DOEPCTL0+0x20*i); + tmp |= DEPCTL_SNAK; + writel(tmp, S5P_OTG_DOEPCTL0+0x20*i); + } +} + +void s3c_usb_clear_all_outep_nak(void) +{ + u8 i; + u32 tmp; + + for(i=0;i<16;i++) + { + tmp = readl(S5P_OTG_DOEPCTL0+0x20*i); + tmp |= (DEPCTL_EPENA|DEPCTL_CNAK); + writel(tmp, S5P_OTG_DOEPCTL0+0x20*i); + } +} + +void s3c_usb_set_max_pktsize(USB_SPEED speed) +{ + if (speed == USB_HIGH) + { + otg.speed = USB_HIGH; + otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE; + otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE; + otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE; + } + else + { + otg.speed = USB_FULL; + otg.ctrl_max_pktsize = FS_CTRL_PKT_SIZE; + otg.bulkin_max_pktsize = FS_BULK_PKT_SIZE; + otg.bulkout_max_pktsize = FS_BULK_PKT_SIZE; + } +} + +void s3c_usb_set_endpoint(void) +{ + /* Unmask S5P_OTG_DAINT source */ + writel(0xff, S5P_OTG_DIEPINT0); + writel(0xff, S5P_OTG_DOEPINT0); + writel(0xff, S5P_OTG_DIEPINT_IN); + writel(0xff, S5P_OTG_DOEPINT_OUT); + + /* Init For Ep0*/ + /*MPS:64bytes */ + writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0); + /*ep0 enable, clear nak */ + writel((1u<<31)|(1<<26)|(0<<0), S5P_OTG_DOEPCTL0); +} + +void s3c_usb_set_descriptors(void) +{ + /* Standard device descriptor */ + otg.desc.dev.bLength=DEVICE_DESC_SIZE; /*0x12*/ + otg.desc.dev.bDescriptorType=DEVICE_DESCRIPTOR; + otg.desc.dev.bDeviceClass=0xFF; /* 0x0*/ + otg.desc.dev.bDeviceSubClass=0x0; + otg.desc.dev.bDeviceProtocol=0x0; + otg.desc.dev.bMaxPacketSize0=otg.ctrl_max_pktsize; + otg.desc.dev.idVendorL=0xE8; /*0x45;*/ + otg.desc.dev.idVendorH=0x04; /*0x53;*/ + otg.desc.dev.idProductL=0x34; /*0x00*/ + otg.desc.dev.idProductH=0x12; /*0x64*/ + otg.desc.dev.bcdDeviceL=0x00; + otg.desc.dev.bcdDeviceH=0x01; + otg.desc.dev.iManufacturer=0x1; /* index of string descriptor */ + otg.desc.dev.iProduct=0x2; /* index of string descriptor */ + otg.desc.dev.iSerialNumber=0x0; + otg.desc.dev.bNumConfigurations=0x1; + if (otg.speed == USB_FULL) { + otg.desc.dev.bcdUSBL=0x10; + otg.desc.dev.bcdUSBH=0x01; /* Ver 1.10*/ + } + else { + otg.desc.dev.bcdUSBL=0x00; + otg.desc.dev.bcdUSBH=0x02; /* Ver 2.0*/ + } + + /* Standard configuration descriptor */ + otg.desc.config.bLength=CONFIG_DESC_SIZE; /* 0x9 bytes */ + otg.desc.config.bDescriptorType=CONFIGURATION_DESCRIPTOR; + otg.desc.config.wTotalLengthL=CONFIG_DESC_TOTAL_SIZE; + otg.desc.config.wTotalLengthH=0; + otg.desc.config.bNumInterfaces=1; +/* dbg descConf.bConfigurationValue=2; // why 2? There's no reason.*/ + otg.desc.config.bConfigurationValue=1; + otg.desc.config.iConfiguration=0; + otg.desc.config.bmAttributes=CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED; /* bus powered only.*/ + otg.desc.config.maxPower=25; /* draws 50mA current from the USB bus.*/ + + /* Standard interface descriptor */ + otg.desc.intf.bLength=INTERFACE_DESC_SIZE; /* 9*/ + otg.desc.intf.bDescriptorType=INTERFACE_DESCRIPTOR; + otg.desc.intf.bInterfaceNumber=0x0; + otg.desc.intf.bAlternateSetting=0x0; /* ?*/ + otg.desc.intf.bNumEndpoints = 2; /* # of endpoints except EP0*/ + otg.desc.intf.bInterfaceClass=0xff; /* 0x0 ?*/ + otg.desc.intf.bInterfaceSubClass=0x0; + otg.desc.intf.bInterfaceProtocol=0x0; + otg.desc.intf.iInterface=0x0; + + /* Standard endpoint0 descriptor */ + otg.desc.ep1.bLength=ENDPOINT_DESC_SIZE; + otg.desc.ep1.bDescriptorType=ENDPOINT_DESCRIPTOR; + otg.desc.ep1.bEndpointAddress=BULK_IN_EP|EP_ADDR_IN; + otg.desc.ep1.bmAttributes=EP_ATTR_BULK; + otg.desc.ep1.wMaxPacketSizeL=(u8)otg.bulkin_max_pktsize; /* 64*/ + otg.desc.ep1.wMaxPacketSizeH=(u8)(otg.bulkin_max_pktsize>>8); + otg.desc.ep1.bInterval=0x0; /* not used */ + + /* Standard endpoint1 descriptor */ + otg.desc.ep2.bLength=ENDPOINT_DESC_SIZE; + otg.desc.ep2.bDescriptorType=ENDPOINT_DESCRIPTOR; + otg.desc.ep2.bEndpointAddress=BULK_OUT_EP|EP_ADDR_OUT; + otg.desc.ep2.bmAttributes=EP_ATTR_BULK; + otg.desc.ep2.wMaxPacketSizeL=(u8)otg.bulkout_max_pktsize; /* 64*/ + otg.desc.ep2.wMaxPacketSizeH=(u8)(otg.bulkout_max_pktsize>>8); + otg.desc.ep2.bInterval=0x0; /* not used */ +} + +void s3c_usb_check_speed(USB_SPEED *speed) +{ + u32 status; + + status = readl(S5P_OTG_DSTS); /* System status read */ + + *speed = (USB_SPEED)((status&0x6) >>1); +} + +void s3c_usb_clear_dnfile_info(void) +{ + otg.dn_addr = 0; + otg.dn_filesize = 0; + otg.dn_ptr = 0; +} + +void s3c_usb_clear_upfile_info(void) +{ + otg.up_addr= 0; + otg.up_size= 0; + otg.up_ptr = 0; +} + + +int s3c_usb_check_setconf(void) +{ + if (otg.set_config == 0) + return FALSE; + else + return TRUE; +} + +void s3c_usb_set_opmode(USB_OPMODE mode) +{ + otg.op_mode = mode; + + writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE| + INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY, + S5P_OTG_GINTMSK); /*gint unmask */ + + writel(MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK, S5P_OTG_GAHBCFG); + + s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize); + s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0); + + /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */ + writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0, + S5P_OTG_DOEPCTL_OUT); + + /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */ + writel(0u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0, + S5P_OTG_DIEPCTL_IN); +} + +void s3c_usb_reset(void) +{ + s3c_usb_set_all_outep_nak(); + + otg.ep0_state = EP0_STATE_INIT; + writel(((1<>1) == USB_HIGH) { + DBG_SETUP1("High Speed Detection\n"); + s3c_usb_set_max_pktsize(USB_HIGH); + } + else if(((status&0x6) >>1) == USB_FULL) { + DBG_SETUP1("Full Speed Detec tion\n"); + s3c_usb_set_max_pktsize(USB_FULL); + } + else { + printf("**** Error:Neither High_Speed nor Full_Speed\n"); + return FALSE; + } + + s3c_usb_set_endpoint(); +/* if (is_fastboot) + fboot_usb_set_descriptors(); + else +*/ s3c_usb_set_descriptors(); + s3c_usb_clear_dnfile_info(); + s3c_usb_set_opmode(op_mode); + + return TRUE; +} + +void s3c_usb_pkt_receive(void) +{ + u32 rx_status; + u32 fifo_cnt_byte; + + rx_status = readl(S5P_OTG_GRXSTSP); + DBG_SETUP0("S5P_OTG_GRXSTSP = 0x%x\n", rx_status); + + if ((rx_status & (0xf<<17)) == SETUP_PKT_RECEIVED) { + DBG_SETUP1("SETUP_PKT_RECEIVED\n"); + s3c_usb_ep0_int_hndlr(); + + } else if ((rx_status & (0xf<<17)) == OUT_PKT_RECEIVED) { + fifo_cnt_byte = (rx_status & 0x7ff0)>>4; + DBG_SETUP1("OUT_PKT_RECEIVED\n"); + + if((rx_status & BULK_OUT_EP)&&(fifo_cnt_byte)) { +/* if (is_fastboot) + fboot_usb_int_bulkout(fifo_cnt_byte); + else +*/ s3c_usb_int_bulkout(fifo_cnt_byte); + if( otg.op_mode == USB_CPU ) + writel(INT_RESUME|INT_OUT_EP|INT_IN_EP| + INT_ENUMDONE|INT_RESET|INT_SUSPEND| + INT_RX_FIFO_NOT_EMPTY, + S5P_OTG_GINTMSK); + return; + } + + } else if ((rx_status & (0xf<<17)) == GLOBAL_OUT_NAK) { + DBG_SETUP1("GLOBAL_OUT_NAK\n"); + + } else if ((rx_status & (0xf<<17)) == OUT_TRNASFER_COMPLETED) { + DBG_SETUP1("OUT_TRNASFER_COMPLETED\n"); + + } else if ((rx_status & (0xf<<17)) == SETUP_TRANSACTION_COMPLETED) { + DBG_SETUP1("SETUP_TRANSACTION_COMPLETED\n"); + + } else { + DBG_SETUP1("Reserved\n"); + } +} + +void s3c_usb_transfer(void) +{ + u32 ep_int; + u32 check_dma; + u32 ep_int_status; + + ep_int = readl(S5P_OTG_DAINT); + DBG_SETUP0("S5P_OTG_DAINT = 0x%x", ep_int); + + if (ep_int & (1< +#include +#include + +#define S3C_USBD_DETECT_IRQ() (readl(S5P_OTG_GINTSTS) & \ + (GINTSTS_WkUpInt|GINTSTS_OEPInt|GINTSTS_IEPInt| \ + GINTSTS_EnumDone|GINTSTS_USBRst|GINTSTS_USBSusp|GINTSTS_RXFLvl)) +#define S3C_USBD_CLEAR_IRQ() do { \ + writel(BIT_ALLMSK, (S5P_OTG_GINTSTS)); \ + } while (0) + +#define CONTROL_EP 0 +#define BULK_IN_EP 1 +#define BULK_OUT_EP 2 + +#define FS_CTRL_PKT_SIZE 64 +#define FS_BULK_PKT_SIZE 64 + +#define HS_CTRL_PKT_SIZE 64 +#define HS_BULK_PKT_SIZE 512 + +#define RX_FIFO_SIZE 512 +#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE +#define NPTX_FIFO_SIZE 512 +#define PTX_FIFO_SIZE 512 + +// string descriptor +#define LANGID_US_L (0x09) +#define LANGID_US_H (0x04) + +// Feature Selectors +#define EP_STALL 0 +#define DEVICE_REMOTE_WAKEUP 1 +#define TEST_MODE 2 + +/* Test Mode Selector*/ +#define TEST_J 1 +#define TEST_K 2 +#define TEST_SE0_NAK 3 +#define TEST_PACKET 4 +#define TEST_FORCE_ENABLE 5 + +#define S5P_OTG_DIEPCTL_IN (S5P_OTG_DIEPCTL0 + 0x20*BULK_IN_EP) +#define S5P_OTG_DIEPINT_IN (S5P_OTG_DIEPINT0 + 0x20*BULK_IN_EP) +#define S5P_OTG_DIEPTSIZ_IN (S5P_OTG_DIEPTSIZ0 + 0x20*BULK_IN_EP) +#define S5P_OTG_DIEPDMA_IN (S5P_OTG_DIEPDMA0 + 0x20*BULK_IN_EP) +#define S5P_OTG_DOEPCTL_OUT (S5P_OTG_DOEPCTL0 + 0x20*BULK_OUT_EP) +#define S5P_OTG_DOEPINT_OUT (S5P_OTG_DOEPINT0 + 0x20*BULK_OUT_EP) +#define S5P_OTG_DOEPTSIZ_OUT (S5P_OTG_DOEPTSIZ0 + 0x20*BULK_OUT_EP) +#define S5P_OTG_DOEPDMA_OUT (S5P_OTG_DOEPDMA0 + 0x20*BULK_OUT_EP) +#define S5P_OTG_IN_FIFO (S5P_OTG_EP0_FIFO + 0x1000*BULK_IN_EP) +#define S5P_OTG_OUT_FIFO (S5P_OTG_EP0_FIFO + 0x1000*BULK_OUT_EP) + + +typedef struct +{ + u8 bLength; + u8 bDescriptorType; + u8 bcdUSBL; + u8 bcdUSBH; + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + u8 bMaxPacketSize0; + u8 idVendorL; + u8 idVendorH; + u8 idProductL; + u8 idProductH; + u8 bcdDeviceL; + u8 bcdDeviceH; + u8 iManufacturer; + u8 iProduct; + u8 iSerialNumber; + u8 bNumConfigurations; +} __attribute__ ((packed)) device_desc_t; + +typedef struct +{ + u8 bLength; + u8 bDescriptorType; + u8 wTotalLengthL; + u8 wTotalLengthH; + u8 bNumInterfaces; + u8 bConfigurationValue; + u8 iConfiguration; + u8 bmAttributes; + u8 maxPower; +} __attribute__ ((packed)) config_desc_t; + +typedef struct +{ + u8 bLength; + u8 bDescriptorType; + u8 bInterfaceNumber; + u8 bAlternateSetting; + u8 bNumEndpoints; + u8 bInterfaceClass; + u8 bInterfaceSubClass; + u8 bInterfaceProtocol; + u8 iInterface; +} __attribute__ ((packed)) intf_desc_t; + +typedef struct +{ + u8 bLength; + u8 bDescriptorType; + u8 bEndpointAddress; + u8 bmAttributes; + u8 wMaxPacketSizeL; + u8 wMaxPacketSizeH; + u8 bInterval; +} __attribute__ ((packed)) ep_desc_t; + +typedef struct +{ + u8 bmRequestType; + u8 bRequest; + u8 wValue_L; + u8 wValue_H; + u8 wIndex_L; + u8 wIndex_H; + u8 wLength_L; + u8 wLength_H; +} __attribute__ ((packed)) device_req_t; + +typedef struct +{ + device_desc_t dev; + config_desc_t config; + intf_desc_t intf; + ep_desc_t ep1; + ep_desc_t ep2; + ep_desc_t ep3; + ep_desc_t ep4; +} __attribute__ ((packed)) descriptors_t; + +typedef struct +{ + u8 Device; + u8 Interface; + u8 ep_ctrl; + u8 ep_in; + u8 ep_out; +} __attribute__ ((packed)) get_status_t; + +typedef struct +{ + u8 AlternateSetting; +} __attribute__ ((packed)) get_intf_t; + + +typedef enum +{ + USB_CPU, USB_DMA +} USB_OPMODE; + +typedef enum +{ + USB_HIGH, USB_FULL, USB_LOW +} USB_SPEED; + +typedef enum +{ + EP_TYPE_CONTROL, EP_TYPE_ISOCHRONOUS, EP_TYPE_BULK, EP_TYPE_INTERRUPT +} EP_TYPE; + + +typedef struct +{ + descriptors_t desc; + device_req_t dev_req; + + u32 ep0_state; + u32 ep0_substate; + USB_OPMODE op_mode; + USB_SPEED speed; + u32 ctrl_max_pktsize; + u32 bulkin_max_pktsize; + u32 bulkout_max_pktsize; + u32 dn_addr; + u32 dn_filesize; + u32 up_addr; + u32 up_size; + u8* dn_ptr; + u8* up_ptr; + u32 set_config; + u32 req_length; +} __attribute__ ((packed)) otg_dev_t; + +// SPEC1.1 + +// Standard bmRequestType (direction) +enum DEV_REQUEST_DIRECTION +{ + HOST_TO_DEVICE = 0x00, + DEVICE_TO_HOST = 0x80 +}; + +// Standard bmRequestType (Type) +enum DEV_REQUEST_TYPE +{ + STANDARD_TYPE = 0x00, + CLASS_TYPE = 0x20, + VENDOR_TYPE = 0x40, + RESERVED_TYPE = 0x60 +}; + +// Standard bmRequestType (Recipient) +enum DEV_REQUEST_RECIPIENT +{ + DEVICE_RECIPIENT = 0, + INTERFACE_RECIPIENT = 1, + ENDPOINT_RECIPIENT = 2, + OTHER_RECIPIENT = 3 +}; + +// Descriptor types +enum DESCRIPTOR_TYPE +{ + DEVICE_DESCRIPTOR = 1, + CONFIGURATION_DESCRIPTOR = 2, + STRING_DESCRIPTOR = 3, + INTERFACE_DESCRIPTOR = 4, + ENDPOINT_DESCRIPTOR = 5, + DEVICE_QUALIFIER = 6, + OTHER_SPEED_CONFIGURATION = 7, + INTERFACE_POWER = 8, +}; + +// configuration descriptor: bmAttributes +enum CONFIG_ATTRIBUTES +{ + CONF_ATTR_DEFAULT = 0x80, + CONF_ATTR_REMOTE_WAKEUP = 0x20, + CONF_ATTR_SELFPOWERED = 0x40 +}; + +// endpoint descriptor +enum ENDPOINT_ATTRIBUTES +{ + EP_ADDR_IN = 0x80, + EP_ADDR_OUT = 0x00, + + EP_ATTR_CONTROL = 0x0, + EP_ATTR_ISOCHRONOUS = 0x1, + EP_ATTR_BULK = 0x2, + EP_ATTR_INTERRUPT = 0x3 +}; + +// Standard bRequest codes +enum STANDARD_REQUEST_CODE +{ + STANDARD_GET_STATUS = 0, + STANDARD_CLEAR_FEATURE = 1, + STANDARD_RESERVED_1 = 2, + STANDARD_SET_FEATURE = 3, + STANDARD_RESERVED_2 = 4, + STANDARD_SET_ADDRESS = 5, + STANDARD_GET_DESCRIPTOR = 6, + STANDARD_SET_DESCRIPTOR = 7, + STANDARD_GET_CONFIGURATION = 8, + STANDARD_SET_CONFIGURATION = 9, + STANDARD_GET_INTERFACE = 10, + STANDARD_SET_INTERFACE = 11, + STANDARD_SYNCH_FRAME = 12 +}; + +int s3c_usbctl_init(void); +int s3c_usbc_activate (void); +int s3c_usb_stop( void ); +int s3c_udc_int_hndlr(void); + +/* in usbd-otg-hs.c */ +extern unsigned int s3c_usbd_dn_addr; +extern unsigned int s3c_usbd_dn_cnt; +extern int DNW; +extern int s3c_got_header; +extern int s3c_receive_done; + +#endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6c94794..d248be2 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_host.o # ohci +COBJS-$(CONFIG_S3C_USBD) += usb_ohci.o COBJS-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o COBJS-$(CONFIG_USB_ATMEL) += ohci-at91.o COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 9f0ed06..c484fa7 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -26,11 +26,14 @@ #include #include #include +#include #include "ehci.h" /* Setup the EHCI host controller. */ static void setup_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); @@ -57,6 +60,33 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_UTMISWRST); udelay(20); + /* HSIC phy reset */ + clrbits_le32(&usb->hsicphyctrl1, + HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + clrbits_le32(&usb->hsicphyctrl2, + HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) + << HSIC_CTRL_REFCLKDIV_SHIFT) + | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) + << HSIC_CTRL_REFCLKSEL_SHIFT) + | HSIC_CTRL_PHYSWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + udelay(10); + + clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST); + clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST); + + udelay(80); + /* EHCI Ctrl setting */ setbits_le32(&usb->ehcictrl, EHCICTRL_ENAINCRXALIGN | @@ -79,6 +109,7 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } +struct exynos5_gpio_part1 *gpio; /* * EHCI-initialization * Create the appropriate control structures to manage @@ -87,14 +118,20 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct exynos_usb_phy *usb; - + gpio = (struct exynos5_gpio_part1 *) EXYNOS5_GPIO_PART1_BASE; usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); + + s5p_gpio_direction_output(&gpio->x3, 5, 0); + s5p_gpio_direction_output(&gpio->d1, 7, 0); + setup_usb_phy(usb); + s5p_gpio_direction_output(&gpio->x3, 5, 1); + s5p_gpio_direction_output(&gpio->d1, 7, 1); + *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci(); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", (uint32_t)*hccr, (uint32_t)*hcor, (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/drivers/usb/host/usb_ohci.c b/drivers/usb/host/usb_ohci.c new file mode 100644 index 0000000..734709c --- /dev/null +++ b/drivers/usb/host/usb_ohci.c @@ -0,0 +1,750 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the S3C24XX. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include + +#ifdef CONFIG_USB_OHCI + +#include +#include + +#include + +#include "usb_ohci.h" + + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#define OHCI_VERBOSE_DEBUG /* not always helpful */ + + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +//#define readl(a) (*((vu_long *)(a))) +//#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#undef DEBUG_USB_OHCI +#ifdef DEBUG_USB_OHCI +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG_USB_OHCI */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#undef SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) le16_to_cpu(x) +#define m32_swap(x) le32_to_cpu(x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + + static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } + + +/* forward declaration */ +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG_USB_OHCI +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)m32_swap(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG_USB_OHCI */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG_USB_OHCI +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return m16_swap (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = m32_swap (td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); + if (data) + td->hwBE = m32_swap (data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = m32_swap (td_pt); + td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG_USB_OHCI +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + return 0; +} + + /*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + return 0; +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ +int usb_lowlevel_init(int index, void **controller) +{ + return 0; +} + +int usb_lowlevel_stop(int index) +{ + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/drivers/usb/host/usb_ohci.h b/drivers/usb/host/usb_ohci.h new file mode 100644 index 0000000..cadef9e --- /dev/null +++ b/drivers/usb/host/usb_ohci.h @@ -0,0 +1,397 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + +#include + +/* ED States */ +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index e0b4217..cb23008 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -378,6 +378,11 @@ static void musb_peri_ep0_idle(void) u16 csr0; /* + * NB: This fails/hangs sometimes if debug_level is set early before + * udc_device->address is set. Maybe fix by setting hw faddr to zero + * at reset/init time???? + */ + /* * Verify addresses * A lot of confusion can be caused if the address * in software, udc layer, does not agree with the diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index c7876ed..b90f273 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -111,6 +111,10 @@ int musb_platform_init(void) goto end; } #endif +#ifdef CONFIG_OMAP4430 + /* Power down the phy during init */ + writel(0x1, (void *)0x4a002300); +#endif #ifdef CONFIG_TWL6030_POWER twl6030_usb_device_settings(); @@ -137,6 +141,8 @@ int musb_platform_init(void) #ifdef CONFIG_OMAP4430 u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C); *usbotghs_control = 0x15; + /* Power up the phy now that initialization is complete */ + writel(0, (void *)0x4a002300); #endif platform_needs_initialization = 0; } diff --git a/include/configs/arndale5250.h b/include/configs/arndale5250.h new file mode 100644 index 0000000..0376d1f --- /dev/null +++ b/include/configs/arndale5250.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ +#define CONFIG_SMDK5250 /* which is in a SMDK5250 */ + +#include /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_ARM_CLK_FREQ 1000 /* in MHz*/ +#define CONFIG_BUS_CLK_FREQ 800 /* in MHz*/ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5250 3774 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +/* Boot configuration */ +#define BOOT_MMCSD 0x3 +#define BOOT_EMMC_4_4 0x7 + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM3_OFFSET 0x808 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SERIAL2 /* use SERIAL 3 */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 + +#define TZPC_BASE_OFFSET 0x10000 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC + +#define CONFIG_BOARD_EARLY_INIT_F + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_PREBOOT "usb start" + +/* SYSFLAGS register */ +#define CONFIG_SYSFLAGS_ADDR 0x02020000 + +/* MMC SPL */ +#define CONFIG_SPL +#define COPY_BL2_FNPTR_ADDR 0x02020030 +#define COPY_BL2_FNPTR_ADDR_EMMC 0x02020044 +#define COPY_BL2_FNPTR_ADDR_EMMC_DONE 0x02020048 + +/* specific .lds file */ +#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds" +#define CONFIG_SPL_TEXT_BASE 0x02023400 +#define CONFIG_SPL_MAX_SIZE (14 * 1024) + +/* secondary SMP pens */ +#define CONFIG_SPL_SMP_PEN (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE - 8) + +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "ARNDALE5250 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_RD_LVL + +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_IDENT_STRING " for ARNDALE5250" + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) +#define CONFIG_DOS_PARTITION + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* I2C */ +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_HARD_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ +#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_MAX_I2C_NUM 8 +#define CONFIG_SYS_I2C_SLAVE 0x0 + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_BOOTM_BOOTARGS_APPEND_MAC +#endif /*CONFIG_CMD_NET*/ + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_MENU + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */ diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h deleted file mode 100644 index a7cd1d4..0000000 --- a/include/configs/ca9x4_ct_vxp.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * (C) Copyright 2010 Linaro - * Matt Waddel, - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board info register */ -#define SYS_ID 0x10000000 -#define CONFIG_REVISION_TAG 1 -#define CONFIG_SYS_TEXT_BASE 0x60800000 - -#define CONFIG_SYS_MEMTEST_START 0x60000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_SYS_L2CACHE_OFF 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -#define SCTL_BASE 0x10001000 -#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) - -/* SMSC9115 Ethernet from SMSC9118 family */ -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_32_BIT 1 -#define CONFIG_SMC911X_BASE 0x4E000000 - -/* PL011 Serial Configuration */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} -#define CONFIG_CONS_INDEX 0 - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_SYS_SERIAL0 0x10009000 -#define CONFIG_SYS_SERIAL1 0x1000A000 - -/* Command line configuration */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_RUN - -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_MMC 1 -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_ARM_PL180_MMCI -#define CONFIG_ARM_PL180_MMCI_BASE 0x10005000 -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_PXE -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.ca9x4_ct_vxp" - -/* Miscellaneous configurable options */ -#undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_LOAD_ADDR 0x60008000 /* load address */ -#define LINUX_BOOT_PARAM_ADDR 0x60000200 -#define CONFIG_BOOTDELAY 2 - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x60000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ - -/* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* Basic environment settings */ -#define CONFIG_BOOTCOMMAND "run bootflash;" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80008000\0" \ - "ramdisk_addr_r=0x61000000\0" \ - "kernel_addr=0x44100000\0" \ - "ramdisk_addr=0x44800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0x88000000\0" \ - "kernel_addr_r=0x80008000\0" \ - "console=ttyAMA0,38400n8\0" \ - "dram=1024M\0" \ - "root=/dev/sda1 rw\0" \ - "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ - "24M@0x2000000(initrd)\0" \ - "flashargs=setenv bootargs root=${root} console=${console} " \ - "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ - "devtmpfs.mount=0 vmalloc=256M\0" \ - "bootflash=run flashargs; " \ - "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ - "bootm ${kernel_addr} ${ramdisk_addr_r}\0" - -/* FLASH and environment organization */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BASE0 0x40000000 -#define CONFIG_SYS_FLASH_BASE1 0x44000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 - -/* Timeout values in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ -#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ - -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ - -/* - * Amount of flash used for environment: - * We don't know which end has the small erase blocks so we use the penultimate - * sector location for the environment - */ -#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE -#define CONFIG_ENV_OVERWRITE 1 - -/* Store environment at top of flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \ - (2 * CONFIG_ENV_SECT_SIZE)) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \ - CONFIG_ENV_OFFSET) -#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ - CONFIG_SYS_FLASH_BASE1 } - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PROMPT "VExpress# " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_CMD_SOURCE -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_MAXARGS 16 /* max command args */ - -#endif diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 62cc08c..8fae05e 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -25,7 +25,9 @@ #define CONFIG_SYS_HZ CFG_HZ #define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT +#define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* @@ -38,7 +40,7 @@ #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD @@ -54,6 +56,7 @@ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION #define CONFIG_CALXEDA_XGMAC @@ -66,33 +69,45 @@ * Command line configuration. */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADS #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT #define CONFIG_CMD_PXE #define CONFIG_MENU #define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY + /* * Miscellaneous configurable options */ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PROMPT "Highbank #" +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_64BIT_LBA + /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index c81ab76..11fc0d1 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -178,6 +178,9 @@ "run nandargs; " \ "onenand read ${loadaddr} 280000 400000; " \ "bootm ${loadaddr}\0" \ + "kernel_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x81600000\0" \ + "pxefile_addr_r=0x86000000\0" #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ @@ -192,6 +195,11 @@ "if run loaduimage; then " \ "run mmcboot;" \ "fi;" \ + "fi; " \ + "setenv autoload no; "\ + "bootp; " \ + "if pxe get; then " \ + "pxe boot;" \ "fi;" \ "run nandboot;" \ @@ -279,6 +287,20 @@ #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* PXE */ +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.omap3_igep0020" + #endif /* (CONFIG_CMD_NET) */ /* diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index ffe771f..2453526 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -25,6 +25,8 @@ #define __CONFIG_H #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 /* * High Level Board Configuration Options diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index dcae537..4df7c8a 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -145,6 +145,8 @@ ***********************************************************/ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #undef CONFIG_CMD_IMLS diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 62cb42b..89cee6b 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -78,6 +78,8 @@ /* Command definition */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #undef CONFIG_CMD_IMLS diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 55efeb7..eb0e367 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -104,6 +104,8 @@ /* Command definition */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #undef CONFIG_CMD_IMLS diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index fbc5162..dd58216 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -70,6 +70,8 @@ /* Command definition */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #undef CONFIG_CMD_IMLS diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index ec9ab26..2395d31 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -126,6 +126,8 @@ /* Command definition */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #undef CONFIG_CMD_IMLS diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 7a3cc16..42850ea 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -142,9 +142,23 @@ #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* PXE */ +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.omap3_beagle" /* commands to include */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #define CONFIG_CMD_ASKENV @@ -257,10 +271,18 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ + "preenv=preEnv.txt\0" \ + "loadpreenv=fatload mmc ${mmcdev} ${loadaddr} ${preenv}\0" \ + "importpreenv=echo Importing preboot environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ + "bootscr=boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "mpurate=${mpurate} " \ @@ -283,11 +305,27 @@ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ + "kernel_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x81600000\0" \ + "pxefile_addr_r=0x86000000\0" \ "userbutton=if gpio input 173; then run userbutton_xm; " \ "else run userbutton_nonxm; fi;\0" \ "userbutton_xm=gpio input 4;\0" \ "userbutton_nonxm=gpio input 7;\0" /* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */ +#define CONFIG_PREBOOT \ + "echo checking for ${preenv};" \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadpreenv; then " \ + "echo Loaded environment from ${preenv};" \ + "run importpreenv;" \ + "if test -n $preenvcmd; then " \ + "echo Running preenvcmd ...;" \ + "run preenvcmd;" \ + "fi;" \ + "fi;" \ + "fi" + #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ @@ -299,21 +337,31 @@ "if run loadbootenv; then " \ "echo Loaded environment from ${bootenv};" \ "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "elif run loadbootscript; then " \ + "echo Loaded script from ${bootscr};" \ + "run bootscript; "\ "fi;" \ "if run loaduimage; then " \ "run mmcboot;" \ "fi;" \ "fi;" \ + "if usb start; then " \ + "setenv autoload no; "\ + "bootp; "\ + "pxe get;" \ + "pxe boot;" \ + "fi;" \ "run nandboot;" \ #define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ +#define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 626cf7a..afd3f60 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -91,6 +91,8 @@ /* commands to include */ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index a32369a..99c2b80 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -114,12 +114,17 @@ /* USB device configuration */ #define CONFIG_USB_DEVICE 1 +#ifndef CONFIG_SPL_USB #define CONFIG_USB_TTY 1 +#endif #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* Flash */ #define CONFIG_SYS_NO_FLASH 1 +/* clocks */ +#define CONFIG_SYS_CLOCKS_ENABLE_ALL + /* commands to include */ #include @@ -156,24 +161,72 @@ "vram=${vram} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscr=boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ + "preenv=preEnv.txt\0" \ + "loadpreenv=fatload mmc ${mmcdev} ${loadaddr} ${preenv}\0" \ + "importpreenv=echo Importing preboot environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "kernel_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x81600000\0" \ + "pxefile_addr_r=0x86000000\0" +#ifdef CONFIG_SPL_USB +#define CONFIG_BOOTCOMMAND \ + "if usb start; then " \ + "set autoload no; "\ + "bootp; "\ + "pxe get;" \ + "pxe boot;" \ + "fi" +#else +#define CONFIG_PREBOOT \ + "echo checking for ${preenv};" \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadpreenv; then " \ + "echo Loaded environment from ${preenv};" \ + "run importpreenv;" \ + "if test -n $preenvcmd; then " \ + "echo Running preenvcmd ...;" \ + "run preenvcmd;" \ + "fi;" \ + "fi; " \ + "fi" #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "elif run loadbootscript; then " \ + "echo Loaded script from ${bootscr};" \ "run bootscript; " \ "else " \ "if run loaduimage; then " \ "run mmcboot; " \ "fi; " \ "fi; " \ + "fi; " \ + "if usb start; then " \ + "set autoload no; "\ + "bootp; "\ + "pxe get;" \ + "pxe boot;" \ "fi" +#endif #define CONFIG_AUTO_COMPLETE 1 @@ -181,13 +234,14 @@ * Miscellaneous configurable options */ +#define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_CBSIZE 512 /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MAXARGS 32 /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) @@ -233,7 +287,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40304350 +#define CONFIG_SPL_TEXT_BASE 0x40303080 #define CONFIG_SPL_MAX_SIZE (38 * 1024) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_DISPLAY_PRINT @@ -262,13 +316,26 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT +/* + * TODO: Fix this: + * Because of spl image size issues, usb peripheral boot + * and mmc/fat boot can not be enabled at the same time + */ +#ifdef CONFIG_SPL_USB +#define CONFIG_SPL_DSU_SUPPORT +#define CONFIG_SPL_USB_SUPPORT +#define CONFIG_SPL_MUSB_SUPPORT +#else #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT +#endif #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_ENABLE_PADS_ALL + #define CONFIG_SYS_THUMB_BUILD #endif /* __CONFIG_OMAP4_COMMON_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index eacb5f5..94dba9f 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -55,8 +55,24 @@ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* PXE */ +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.omap4_panda" + #include #define CONFIG_CMD_NET +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 + /* GPIO */ #define CONFIG_CMD_GPIO diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 623da77..3975b58 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -51,6 +51,8 @@ /* Clock Defines */ #define V_OSCK 19200000 /* Clock output from T2 */ #define V_SCLK V_OSCK +#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */ +#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */ #define CONFIG_MISC_INIT_R diff --git a/include/configs/origen.h b/include/configs/origen.h index ff2b24d..cfdaac5 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -28,6 +28,7 @@ /* High Level Configuration Options */ #define CONFIG_SAMSUNG 1 /* SAMSUNG core */ #define CONFIG_S5P 1 /* S5P Family */ +#define CONFIG_S5PC210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ @@ -96,7 +97,32 @@ #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x42000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=0:2\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -152,6 +178,13 @@ #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI +#define CONFIG_S3C_USBD +#define USBD_DOWN_ADDR 0xC0000000 +#endif + /* Enable devicetree support */ #define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ diff --git a/include/configs/origen_quad.h b/include/configs/origen_quad.h new file mode 100644 index 0000000..657ddca --- /dev/null +++ b/include/configs/origen_quad.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Configuration settings for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_ORIGEN_QUAD_H +#define __CONFIG_ORIGEN_QUAD_H + +/* + * High Level Configuration Options + */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 series */ +#define CONFIG_EXYNOS4412 /* which is in a Exynos4412 */ +#define CONFIG_ORIGEN_QUAD /* which is in a ORIGEN QUAD */ +#define CONFIG_BOARDNAME "OrigenQuad" +#define CONFIG_IDENT_STRING " for Insignal Origen" +#define CONFIG_MACH_TYPE 4200 + +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_CPU_EXYNOS4X12 1 /* which is in a Exynos4X12 */ +#define CONFIG_S5PC210 1 /* which is in a S5PC210 */ +#define CONFIG_S5PC220 1 /* which is in a S5PC220 */ +#define CONFIG_SMDKC210 1 +#define CONFIG_SMDKC220 1 +#define CONFIG_EXYNOS4212 1 +#define CONFIG_EXYNOS4412_EVT1 1 + +#include /* get chip and board defs */ + +/* + * Clock / PLL + */ +#define CONFIG_SYS_CLK_FREQ 24000000 /* 24MHz input clock */ +#define CONFIG_CLK_APLL 1000 +#define CONFIG_CLK_MPLL 400 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_PWM + +/* + * Memory + */ +/* Default address */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 << 20UL) +/* Cache */ +#define CONFIG_SYS_DCACHE_OFF /* Keep L2 Cache Disabled */ +/* DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 /* 256 MB * 4 = 1 GB */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (PHYS_SDRAM_3 + PHYS_SDRAM_3_SIZE) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +/* Reserved */ +#define CONFIG_RESERVED_DRAM 0x100000 +/* Mem test */ +#define CONFIG_CMD_MEMORY +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE - (8UL << 20UL)) + +/* + * Serial + */ +#define CONFIG_SERIAL2 2 /* use SERIAL2 in 0~3 */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 115200 + +/* + * PMIC + */ +#define CONFIG_PMIC 1 + +/* + * SD/MMC + */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_CMD_MMC + +/* + * File System + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Flash + */ +#define CONFIG_SYS_NO_FLASH + +/* + * Image map on sdmmc/emmc + */ +#define CONFIG_SECURE_BL1_ONLY +#define CONFIG_SPL +#define CONFIG_MBR_SIZE (512) +#define CONFIG_SBL_SIZE (8UL << 10) /* 8KB */ +#define CONFIG_BL1_SIZE (16UL << 10) /* 16KB */ +#define CONFIG_BL2_SIZE (512UL << 10) /* 512KB */ + +/* + * Console + */ +#define CONFIG_SYS_PROMPT CONFIG_BOARDNAME " # " +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + +/* + * Commands + */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#include +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (CONFIG_MBR_SIZE \ + +CONFIG_SBL_SIZE \ + +CONFIG_BL1_SIZE \ + +CONFIG_BL2_SIZE) +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ +#define CONFIG_ENV_OVERWRITE +/* Default */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" + +/* + * Misc + */ +/* Initialize */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 +/* display information */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +/* Delay */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +/* TAGS */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* USB Options */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI +#define CONFIG_S3C_USBD +#define USBD_DOWN_ADDR 0xC0000000 +#endif +#define CONFIG_OF_LIBFDT + +#endif diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 5fc6136..07849fb 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -56,6 +56,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG #define CONFIG_CMDLINE_EDITING +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index c0f8622..67eac2e 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -45,6 +45,8 @@ /* input clock of PLL: SMDK5250 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_ARM_CLK_FREQ 1700 /* in MHz*/ +#define CONFIG_BUS_CLK_FREQ 800 /* in MHz*/ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG @@ -77,8 +79,8 @@ /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC #define CONFIG_BOARD_EARLY_INIT_F @@ -90,6 +92,8 @@ /* Command definition*/ #include +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #define CONFIG_CMD_PING #define CONFIG_CMD_ELF @@ -212,6 +216,12 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ +/* Enable PXE Support */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#endif + /* Enable devicetree support */ #define CONFIG_OF_LIBFDT diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 30f4a4e..a7ce95f 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -96,23 +96,19 @@ #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_SYS_NO_FLASH + /* * Commands */ -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB +#include + #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_SOURCE + +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #ifndef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 1 @@ -176,10 +172,11 @@ "mmcboot=echo Booting from external MMC ...; " \ "run commonargs mmcargs memargs; " \ "bootm ${loadaddr}\0" \ - "fdt_high=0x2BC00000\0" \ "stdout=serial,usbtty\0" \ "stdin=serial,usbtty\0" \ - "stderr=serial,usbtty\0" + "stderr=serial,usbtty\0" \ + "initrd_high=0x06000000\0" \ + "fdt_high=0x05000000\0" /*----------------------------------------------------------------------- * Miscellaneous configurable options @@ -201,7 +198,7 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_CMDLINE_EDITING - +#define CONFIG_OF_LIBFDT 1 #define CONFIG_SETUP_MEMORY_TAGS 2 #define CONFIG_INITRD_TAG 1 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ @@ -237,11 +234,6 @@ #define CFG_MMC_BASE 0x80126000 /* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* * base register values for U8500 */ #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ diff --git a/include/configs/trats.h b/include/configs/trats.h index d7808aa..a24e945 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -189,12 +189,17 @@ #define CONFIG_SYS_HZ 1000 -/* TRATS has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */ +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h new file mode 100644 index 0000000..aa60d0d --- /dev/null +++ b/include/configs/vexpress_ca5x2.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2011 Linaro + * Ryan Harkin, + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VEXPRESS_CA5X2_h +#define __VEXPRESS_CA5X2_h + +#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP +#include "vexpress_common.h" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca5x2" + +#endif diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h new file mode 100644 index 0000000..f30e927 --- /dev/null +++ b/include/configs/vexpress_ca9x4.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2011 Linaro + * Ryan Harkin, + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VEXPRESS_CA9X4_H +#define __VEXPRESS_CA9X4_H + +#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +#include "vexpress_common.h" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca9x4" + +#endif diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h new file mode 100644 index 0000000..efdb2f1 --- /dev/null +++ b/include/configs/vexpress_common.h @@ -0,0 +1,326 @@ +/* + * (C) Copyright 2011 ARM Limited + * (C) Copyright 2010 Linaro + * Matt Waddel, + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VEXPRESS_COMMON_H +#define __VEXPRESS_COMMON_H + +/* Definitions copied from linux kernel: arch/arm/mach-vexpress/include/mach/motherboard.h */ +#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x40000000 +#define V2M_PA_CS1 0x44000000 +#define V2M_PA_CS2 0x48000000 +#define V2M_PA_CS3 0x4c000000 +#define V2M_PA_CS7 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 12) +#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0)) +#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) + +#define V2M_BASE 0x60000000 +#define CONFIG_SYS_TEXT_BASE 0x60800000 +#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) +/* CS register bases for the extended memory map. */ +#define V2M_PA_CS0 0x08000000 +#define V2M_PA_CS1 0x0c000000 +#define V2M_PA_CS2 0x14000000 +#define V2M_PA_CS3 0x18000000 +#define V2M_PA_CS7 0x1c000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS1) +#define V2M_SRAM (V2M_PA_CS2) +#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) +#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) +#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) + +#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12)) + +#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31)) +#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* + * Configuration + */ +#define SYS_CFG_START (1 << 31) +#define SYS_CFG_WRITE (1 << 30) +#define SYS_CFG_OSC (1 << 20) +#define SYS_CFG_VOLT (2 << 20) +#define SYS_CFG_AMP (3 << 20) +#define SYS_CFG_TEMP (4 << 20) +#define SYS_CFG_RESET (5 << 20) +#define SYS_CFG_SCC (6 << 20) +#define SYS_CFG_MUXFPGA (7 << 20) +#define SYS_CFG_SHUTDOWN (8 << 20) +#define SYS_CFG_REBOOT (9 << 20) +#define SYS_CFG_DVIMODE (11 << 20) +#define SYS_CFG_POWER (12 << 20) +#define SYS_CFG_SITE_MB (0 << 16) +#define SYS_CFG_SITE_DB1 (1 << 16) +#define SYS_CFG_SITE_DB2 (2 << 16) +#define SYS_CFG_STACK(n) ((n) << 12) + +#define SYS_CFG_ERR (1 << 1) +#define SYS_CFG_COMPLETE (1 << 0) + +/* Board info register */ +#define SYS_ID V2M_SYSREGS +#define CONFIG_REVISION_TAG 1 + +#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END 0x20000000 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_SYS_L2CACHE_OFF 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_OF_LIBFDT 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +#define SCTL_BASE V2M_SYSCTL +#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) + +/* SMSC9115 Ethernet from SMSC9118 family */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT 1 +#define CONFIG_SMC911X_BASE V2M_LAN9118 + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 + +/* Command line configuration */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_ARM_PL180_MMCI +#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 +#define CONFIG_API +#define CONFIG_SYS_MMC_MAX_DEVICE 2 +#define CONFIG_NET_MULTI + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) /* load address */ +#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) +#define CONFIG_BOOTDELAY 2 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + ((unsigned int)0x20000000)) /* SDRAM Bank #2 */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ + +/* additions for new relocation code */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* Basic environment settings */ +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi; " \ + "run bootflash;" + +#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +#define CONFIG_PLATFORM_ENV_SETTINGS \ + "loadaddr=0x80008000\0" \ + "ramdisk_addr_r=0x61000000\0" \ + "kernel_addr=0x44100000\0" \ + "ramdisk_addr=0x44800000\0" \ + "maxramdisk=0x1800000\0" \ + "pxefile_addr_r=0x88000000\0" \ + "kernel_addr_r=0x80008000\0" +#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) +#define CONFIG_PLATFORM_ENV_SETTINGS \ + "loadaddr=0xa0008000\0" \ + "ramdisk_addr_r=0x81000000\0" \ + "kernel_addr=0x0c100000\0" \ + "ramdisk_addr=0x0c800000\0" \ + "maxramdisk=0x1800000\0" \ + "pxefile_addr_r=0xa8000000\0" \ + "kernel_addr_r=0xa0008000\0" +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS \ + "console=ttyAMA0,38400n8\0" \ + "dram=1024M\0" \ + "root=/dev/sda1 rw\0" \ + "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ + "24M@0x2000000(initrd)\0" \ + "flashargs=setenv bootargs root=${root} console=${console} " \ + "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ + "devtmpfs.mount=0 vmalloc=256M\0" \ + "bootflash=run flashargs; " \ + "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ + "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \ + "mmcdev=0\0" \ + "bootscr=boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" + +/* FLASH and environment organization */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 +#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ + +/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ + +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ + +/* + * Amount of flash used for environment: + * We don't know which end has the small erase blocks so we use the penultimate + * sector location for the environment + */ +#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE +#define CONFIG_ENV_OVERWRITE 1 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \ + (2 * CONFIG_ENV_SECT_SIZE)) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ + CONFIG_SYS_FLASH_BASE1 } + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "VExpress# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_CMD_SOURCE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 16 /* max command args */ + +#endif // VEXPRESS_COMMON_H diff --git a/include/mmc.h b/include/mmc.h index a13e2bd..ed4c4e2 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -199,6 +199,8 @@ #define MMCPART_NOAVAILABLE (0xff) #define PART_ACCESS_MASK (0x7) +#define BOOT_PART_ENABLE_MASK (0x7 << 3) +#define BOOT_ACK (0x1 << 6) #define PART_SUPPORT (0x1) struct mmc_cid { diff --git a/include/spl.h b/include/spl.h index b02f36f..21744f3 100644 --- a/include/spl.h +++ b/include/spl.h @@ -74,6 +74,10 @@ void spl_spi_load_image(void); /* Ethernet SPL functions */ void spl_net_load_image(const char *device); +/* USB SPL functions */ +void spl_dsu_load_image(void); +int dsudownload(u32 *, u32 *); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h index be808fd..03cc2bd 100644 --- a/include/usb/musb_udc.h +++ b/include/usb/musb_udc.h @@ -50,4 +50,8 @@ int udc_init(void); #endif /* CONFIG_USB_TTY */ +#ifdef CONFIG_SPL_DSU_SUPPORT +#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */ +#endif + #endif /* __MUSB_UDC_H__ */ diff --git a/net/bootp.c b/net/bootp.c index 4300f1c..885cf09 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -63,6 +63,39 @@ static char *dhcpmsg2str(int type) } } #endif + +#if defined(CONFIG_BOOTP_VENDOREX) +extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ +extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ +u8 *__dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *__dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} +u8 *dhcp_vendorex_prep(u8 *e) __attribute__((weak, alias("__dhcp_vendorex_prep"))); +u8 *dhcp_vendorex_proc(u8 *e) __attribute__((weak, alias("__dhcp_vendorex_proc"))); +#endif #endif static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) diff --git a/spl/Makefile b/spl/Makefile index 3195390..c1e02a1 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -60,6 +60,8 @@ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o +LIBS-$(CONFIG_SPL_USB_SUPPORT) += drivers/usb/gadget/libusb_gadget.o +LIBS-$(CONFIG_SPL_MUSB_SUPPORT) += drivers/usb/musb/libusb_musb.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o @@ -130,7 +132,7 @@ all: $(ALL-y) ifdef CONFIG_SAMSUNG $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mk$(BOARD)spl \ + $(OBJTREE)/tools/mk$(SOC)spl \ $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin endif diff --git a/tools/.gitignore b/tools/.gitignore index 9bce719..365f819 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -18,3 +18,4 @@ /gdb/gdbcont /gdb/gdbsend /kernel-doc/docproc +/mk*spl diff --git a/tools/Makefile b/tools/Makefile index 686840a..f7f57f7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -68,7 +68,8 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) -BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) +BIN_FILES-$(CONFIG_EXYNOS5) += mkexynosspl$(SFX) +BIN_FILES-$(CONFIG_EXYNOS4) += mkexynosspl$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) @@ -97,7 +98,8 @@ NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o NOPED_OBJ_FILES-y += mkimage.o -OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o +OBJ_FILES-$(CONFIG_EXYNOS5) += mkexynosspl.o +OBJ_FILES-$(CONFIG_EXYNOS4) += mkexynosspl.o OBJ_FILES-$(CONFIG_MX28) += mxsboot.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o @@ -220,7 +222,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ -$(obj)mk$(BOARD)spl$(SFX): $(obj)mkexynosspl.o +$(obj)mk$(SOC)spl$(SFX): $(obj)mkexynosspl.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@