diff -Naur u-boot-2009.08.orig/board/marvell/common/mv802_3.h u-boot-2009.08/board/marvell/common/mv802_3.h --- u-boot-2009.08.orig/board/marvell/common/mv802_3.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mv802_3.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,244 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmv802_3h +#define __INCmv802_3h + +/* includes */ +#include "mvTypes.h" + +/* Defines */ +#define MV_MAX_ETH_DATA 1500 + +/* 802.3 types */ +#define MV_IP_TYPE 0x0800 +#define MV_IP_ARP_TYPE 0x0806 +#define MV_IP6_TYPE 0x86dd +#define MV_APPLE_TALK_ARP_TYPE 0x80F3 +#define MV_NOVELL_IPX_TYPE 0x8137 +#define MV_EAPOL_TYPE 0x888e +#define MV_VLAN_TYPE 0x8100 +#define MV_PPPOE_TYPE 0x8864 + +/* Encapsulation header for RFC1042 and Ethernet_tunnel */ + +#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00} + +#define MV_ETH_SNAP_LSB 0xF8 + +#define MV_MAC_ADDR_SIZE (6) +#define MV_MAC_STR_SIZE (20) +#define MV_LLC_HLEN (6) +#define MV_VLAN_HLEN (4) +#define MV_ETH_TYPE_LEN (2) +#define MV_ETH_ALEN (MV_MAC_ADDR_SIZE + MV_MAC_ADDR_SIZE + MV_ETH_TYPE_LEN) +#define MV_PPP_HDR_SIZE (2) +#define MV_PPPOE_HDR_SIZE (8) /* PPP header is 2, PPPoE header is 6 */ + +/* This macro checks for a multicast mac address */ +#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1) + +/* IPv4 */ +#define MV_INET 2 +/* IPv6 */ +#define MV_INET6 10 + +#define MV_MAX_L3_ADDR_SIZE (16) /* IPv4: 4, IPv6: 16 */ + +/* This macro checks for an broadcast mac address */ +#define MV_IS_BROADCAST_MAC(mac) \ + (((mac)[0] == 0xFF) && \ + ((mac)[1] == 0xFF) && \ + ((mac)[2] == 0xFF) && \ + ((mac)[3] == 0xFF) && \ + ((mac)[4] == 0xFF) && \ + ((mac)[5] == 0xFF)) + +/* Typedefs */ +typedef struct { + MV_U8 pDA[MV_MAC_ADDR_SIZE]; + MV_U8 pSA[MV_MAC_ADDR_SIZE]; + MV_U16 typeOrLen; + +} MV_802_3_HEADER; + +/* 8 bytes - PPPoE header + PPP header */ +typedef struct { + MV_U8 version; + MV_U8 code; + MV_U16 session; + MV_U16 len; + MV_U16 proto; +} PPPoE_HEADER; + +enum { + MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */ + MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */ + MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */ + MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */ + MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */ + MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */ + MV_IP_PROTO_PUP = 12, /* PUP protocol */ + MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */ + MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */ + MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */ + MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */ + MV_IP_PROTO_RSVP = 46, /* RSVP protocol */ + MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */ + MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */ + MV_IP_PROTO_AH = 51, /* Authentication Header protocol */ + MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */ + MV_IP_PROTO_PIM = 103, + MV_IP_PROTO_COMP = 108, /* Compression Header protocol */ + MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */ + MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */ + MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */ + + MV_IP_PROTO_RAW = 255, /* Raw IP packets */ + MV_IP_PROTO_MAX +}; + +typedef struct { + MV_U8 version; + MV_U8 tos; + MV_U16 totalLength; + MV_U16 identifier; + MV_U16 fragmentCtrl; + MV_U8 ttl; + MV_U8 protocol; + MV_U16 checksum; + MV_U32 srcIP; + MV_U32 dstIP; + +} MV_IP_HEADER; + +typedef struct { + MV_U32 verClassFlow; + MV_U16 payloadLength; + MV_U8 protocol; + MV_U8 hoplimit; + MV_U8 srcAddr[16]; + MV_U8 dstAddr[16]; + +} MV_IP6_HEADER; + +typedef struct +{ + MV_U8 protocol; + MV_U8 length; + MV_U16 reserverd; + MV_U32 spi; + MV_U32 seqNum; +} MV_AH_HEADER; + + +typedef struct { + MV_U32 spi; + MV_U32 seqNum; +} MV_ESP_HEADER; + +#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */ +#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */ +#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */ +#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */ +#define MV_ICMP_ECHO 8 /* Echo Request */ +#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */ +#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */ +#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */ +#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */ +#define MV_ICMP_INFO_REQUEST 15 /* Information Request */ +#define MV_ICMP_INFO_REPLY 16 /* Information Reply */ +#define MV_ICMP_ADDRESS 17 /* Address Mask Request */ +#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */ + +typedef struct { + MV_U8 type; + MV_U8 code; + MV_U16 checksum; + MV_U16 id; + MV_U16 sequence; + +} MV_ICMP_ECHO_HEADER; + +typedef struct { + MV_U16 source; + MV_U16 dest; + MV_U32 seq; + MV_U32 ack_seq; + MV_U16 flags; + MV_U16 window; + MV_U16 chksum; + MV_U16 urg_offset; + +} MV_TCP_HEADER; + +typedef struct { + MV_U16 source; + MV_U16 dest; + MV_U16 len; + MV_U16 check; + +} MV_UDP_HEADER; + +#endif /* __INCmv802_3h */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCommon.c u-boot-2009.08/board/marvell/common/mvCommon.c --- u-boot-2009.08.orig/board/marvell/common/mvCommon.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCommon.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,355 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" + +int mvCharToHex(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + + if ((ch >= 'a') && (ch <= 'f')) + return (ch - 'a') + 10; + + if ((ch >= 'A') && (ch <= 'F')) + return (ch - 'A') + 10; + + return -1; +} + +int mvCharToDigit(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + + return -1; +} + +/******************************************************************************* +* mvMacStrToHex - Convert MAC format string to hex. +* +* DESCRIPTION: +* This function convert MAC format string to hex. +* +* INPUT: +* macStr - MAC address string. Fornat of address string is +* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter. +* +* OUTPUT: +* macHex - MAC in hex format. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacStrToHex(const char *macStr, MV_U8 *macHex) +{ + int i; + char tmp[3]; + + for (i = 0; i < MV_MAC_ADDR_SIZE; i++) { + tmp[0] = macStr[(i * 3) + 0]; + tmp[1] = macStr[(i * 3) + 1]; + tmp[2] = '\0'; + macHex[i] = (MV_U8) (strtol(tmp, NULL, 16)); + } + return MV_OK; +} + +/******************************************************************************* +* mvMacHexToStr - Convert MAC in hex format to string format. +* +* DESCRIPTION: +* This function convert MAC in hex format to string format. +* +* INPUT: +* macHex - MAC in hex format. +* +* OUTPUT: +* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacHexToStr(MV_U8 *macHex, char *macStr) +{ + int i; + + for (i = 0; i < MV_MAC_ADDR_SIZE; i++) + mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]); + + macStr[(i * 3) - 1] = '\0'; + + return MV_OK; +} + +/******************************************************************************* +* mvSizePrint - Print the given size with size unit description. +* +* DESCRIPTION: +* This function print the given size with size unit description. +* FOr example when size paramter is 0x180000, the function prints: +* "size 1MB+500KB" +* +* INPUT: +* size - Size in bytes. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSizePrint(MV_U32 size) +{ + mvOsOutput("size "); + + if (size >= _1G) { + mvOsOutput("%3dGB ", size / _1G); + size %= _1G; + if (size) + mvOsOutput("+"); + } + if (size >= _1M) { + mvOsOutput("%3dMB ", size / _1M); + size %= _1M; + if (size) + mvOsOutput("+"); + } + if (size >= _1K) { + mvOsOutput("%3dKB ", size / _1K); + size %= _1K; + if (size) + mvOsOutput("+"); + } + if (size > 0) + mvOsOutput("%3dB ", size); + +} + +/******************************************************************************* +* mvHexToBin - Convert hex to binary +* +* DESCRIPTION: +* This function Convert hex to binary. +* +* INPUT: +* pHexStr - hex buffer pointer. +* size - Size to convert. +* +* OUTPUT: +* pBin - Binary buffer pointer. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvHexToBin(const char *pHexStr, MV_U8 *pBin, int size) +{ + int j, i; + char tmp[3]; + MV_U8 byte; + + for (j = 0, i = 0; j < size; j++, i += 2) { + tmp[0] = pHexStr[i]; + tmp[1] = pHexStr[i + 1]; + tmp[2] = '\0'; + byte = (MV_U8) (strtol(tmp, NULL, 16) & 0xFF); + pBin[j] = byte; + } +} + +void mvAsciiToHex(const char *asciiStr, char *hexStr) +{ + int i = 0; + + while (asciiStr[i] != 0) { + mvOsSPrintf(&hexStr[i * 2], "%02x", asciiStr[i]); + i++; + } + hexStr[i * 2] = 0; +} + +void mvBinToHex(const MV_U8 *bin, char *hexStr, int size) +{ + int i; + + for (i = 0; i < size; i++) + mvOsSPrintf(&hexStr[i * 2], "%02x", bin[i]); + + hexStr[i * 2] = '\0'; +} + +void mvBinToAscii(const MV_U8 *bin, char *asciiStr, int size) +{ + int i; + + for (i = 0; i < size; i++) + mvOsSPrintf(&asciiStr[i * 2], "%c", bin[i]); + + asciiStr[i * 2] = '\0'; +} + +/******************************************************************************* +* mvLog2 - +* +* DESCRIPTION: +* Calculate the Log2 of a given number. +* +* INPUT: +* num - A number to calculate the Log2 for. +* +* OUTPUT: +* None. +* +* RETURN: +* Log 2 of the input number, or 0xFFFFFFFF if input is 0. +* +*******************************************************************************/ +MV_U32 mvLog2(MV_U32 num) +{ + MV_U32 result = 0; + if (num == 0) + return 0xFFFFFFFF; + while (num != 1) { + num = num >> 1; + result++; + } + return result; +} + +/******************************************************************************* +* mvWinOverlapTest +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS mvWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + /* check if we have overflow than 4G */ + if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size - 1) || + ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size - 1)) { + return MV_TRUE; + } + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size - 1; + winTop2 = winBase2 + pAddrWin2->size - 1; + + if (((winBase1 <= winTop2) && (winTop2 <= winTop1)) || ((winBase1 <= winBase2) && (winBase2 <= winTop1))) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvWinWithinWinTest +* +* DESCRIPTION: +* This function checks the given win1 boundries is within win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS mvWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size - 1; + winTop2 = winBase2 + pAddrWin2->size - 1; + + if (((winBase1 >= winBase2) && (winBase1 <= winTop2)) || ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + return MV_TRUE; + else + return MV_FALSE; +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCommon.h u-boot-2009.08/board/marvell/common/mvCommon.h --- u-boot-2009.08.orig/board/marvell/common/mvCommon.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCommon.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,359 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCommonh +#define __INCmvCommonh + +#include "mvTypes.h" +#include "mvDeviceId.h" +#ifndef MV_ASMLANGUAGE +#include "mv802_3.h" +#include "mvVideo.h" +#endif + +/* Swap tool */ + +/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ +#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4)) + +/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ +#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4) | \ + ((X&0xf0000) << 4) | \ + ((X&0xf00000) >> 4) | \ + ((X&0xf000000) << 4) | \ + ((X&0xf0000000) >> 4)) + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) + +/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ +#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ + (((X)&0xff00ULL)<<40) | \ + (((X)&0xff0000ULL)<<24) | \ + (((X)&0xff000000ULL)<<8) | \ + (((X)&0xff00000000ULL)>>8) | \ + (((X)&0xff0000000000ULL)>>24) | \ + (((X)&0xff000000000000ULL)>>40) | \ + (((X)&0xff00000000000000ULL)>>56))) + +/* Endianess macros. */ +#if defined(MV_CPU_LE) +#define MV_16BIT_LE(X) (X) +#define MV_32BIT_LE(X) (X) +#define MV_64BIT_LE(X) (X) +#define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) +#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) +#elif defined(MV_CPU_BE) +#define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) +#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) +#define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) +#define MV_16BIT_BE(X) (X) +#define MV_32BIT_BE(X) (X) +#define MV_64BIT_BE(X) (X) +#else +#error "CPU endianess isn't defined!\n" +#endif + +/* Bit field definitions */ +#define NO_BIT 0x00000000 + +/* avoid redefinition of bits */ +#ifndef BIT0 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT0 */ +/* Handy sizes */ +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/* Tclock and Sys clock define */ +#define _100MHz 100000000 +#define _125MHz 125000000 +#define _133MHz 133333334 +#define _150MHz 150000000 +#define _160MHz 160000000 +#define _166MHz 166666667 +#define _175MHz 175000000 +#define _178MHz 178000000 +#define _183MHz 183333334 +#define _187MHz 187000000 +#define _192MHz 192000000 +#define _194MHz 194000000 +#define _200MHz 200000000 +#define _233MHz 233333334 +#define _250MHz 250000000 +#define _266MHz 266666667 +#define _300MHz 300000000 + +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333333 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 +#define MV_BOARD_TCLK_250MHZ 250000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333333 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_233MHZ 233333333 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 +#define MV_BOARD_SYSCLK_300MHZ 300000000 +#define MV_BOARD_SYSCLK_333MHZ 333333334 +#define MV_BOARD_SYSCLK_400MHZ 400000000 + +#define MV_BOARD_REFCLK_25MHZ 25000000 + +/* For better address window table readability */ +#define EN MV_TRUE +#define DIS MV_FALSE +#define N_A -1 /* Not applicable */ + +/* Cache configuration options for memory (DRAM, SRAM, ... ) */ + +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +/* Macro for testing aligment. Positive if number is NOT aligned */ +#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) + +/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ +#define MV_ALIGN_UP(number, align) \ +(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) + +/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ +#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) + +/* This macro returns absolute value */ +#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) + +/* Bit fields manipulation macros */ + +/* An integer word which its 'x' bit is set */ +#define MV_BIT_MASK(bitNum) (1 << (bitNum)) + +/* Checks wheter bit 'x' in integer word is set */ +#define MV_BIT_CHECK(word, bitNum) ((word) & MV_BIT_MASK(bitNum)) + +/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ +#define MV_BIT_CLEAR(word, bitNum) ((word) &= ~(MV_BIT_MASK(bitNum))) + +/* Set bit 'x' in integer word (RMW) */ +#define MV_BIT_SET(word, bitNum) ((word) |= MV_BIT_MASK(bitNum)) + +/* Invert bit 'x' in integer word (RMW) */ +#define MV_BIT_INV(word, bitNum) ((word) ^= MV_BIT_MASK(bitNum)) + +/* Get the min between 'a' or 'b' */ +#define MV_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/* Get the max between 'a' or 'b' */ +#define MV_MAX(a, b) (((a) < (b)) ? (b) : (a)) + +#define mvOsDivide(num, div) \ +({ \ + int i = 0, rem = (num); \ + while (rem >= (div)) { \ + rem -= (div); \ + i++; \ + } \ + (i); \ +}) + +#define mvOsReminder(num, div) \ +({ \ + int rem = (num); \ + while (rem >= (div)) \ + rem -= (div); \ + (rem); \ +}) + +#define MV_MACQUAD_FMT "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x" + +#define MV_MACQUAD(addr) \ + ((unsigned char *)addr)[0], \ + ((unsigned char *)addr)[1], \ + ((unsigned char *)addr)[2], \ + ((unsigned char *)addr)[3], \ + ((unsigned char *)addr)[4], \ + ((unsigned char *)addr)[5] + +#define MV_IPQUAD_FMT "%u.%u.%u.%u" +#define MV_IPQUAD(ip) (ip&0xFF), ((ip>>8)&0xFF), ((ip>>16)&0xFF), ((ip>>24)&0xFF) +#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) + +#define MV_IP6_FMT "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x" +#define MV_IP6_ARG(L3) L3[0], L3[1], L3[2], L3[3], \ + L3[4], L3[5], L3[6], L3[7], \ + L3[8], L3[9], L3[10], L3[11], \ + L3[12], L3[13], L3[14], L3[15] + +#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) + +#define MV_GET_BIT(word, bitNum) (((word) & (1 << (bitNum))) >> (bitNum)) + +#define MV_SET_BIT(word, bitNum, bitVal) (((word) & ~(1 << (bitNum))) | (bitVal << bitNum)) + +#ifndef MV_ASMLANGUAGE +/* mvCommon API list */ + +int mvCharToHex(char ch); +int mvCharToDigit(char ch); + +MV_VOID mvHexToBin(const char *pHexStr, MV_U8 *pBin, int size); +void mvAsciiToHex(const char *asciiStr, char *hexStr); +void mvBinToHex(const MV_U8 *bin, char *hexStr, int size); +void mvBinToAscii(const MV_U8 *bin, char *asciiStr, int size); + +MV_STATUS mvMacStrToHex(const char *macStr, MV_U8 *macHex); +MV_STATUS mvMacHexToStr(MV_U8 *macHex, char *macStr); +void mvSizePrint(MV_U32); + +MV_U32 mvLog2(MV_U32 num); + +MV_STATUS mvWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS mvWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCommonh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCompVer.txt u-boot-2009.08/board/marvell/common/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/common/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCompVer.txt 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,2 @@ +Global HAL Version:FEROCEON_HAL_3_1_7 + Unit HAL Version:3.1 .4 Description:This component includes an implementation of the unit HAL drivers diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDebug.c u-boot-2009.08/board/marvell/common/mvDebug.c --- u-boot-2009.08.orig/board/marvell/common/mvDebug.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDebug.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,275 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mv802_3.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "mvDebug.h" + +/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros + * mvDebug - map of bits (one for each module) bit=1 means enable + * debug code and messages for this module + * mvModuleDebug - array of 32 bits varables one for each module + */ +MV_U32 mvDebug = 0; +MV_U32 mvDebugModules[MV_MODULE_MAX]; + +/* Init mvModuleDebug array to default values */ +void mvDebugInit(void) +{ + int bit; + + mvDebug = 0; + for (bit = 0; bit < MV_MODULE_MAX; bit++) { + mvDebugModules[bit] = MV_DEBUG_FLAG_ERR | MV_DEBUG_FLAG_STATS; + mvDebug |= MV_BIT_MASK(bit); + } +} + +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable) +{ + if (isEnable) + MV_BIT_SET(mvDebug, module); + else + MV_BIT_CLEAR(mvDebug, module); +} + +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags) +{ + mvDebugModules[module] |= flags; +} + +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags) +{ + mvDebugModules[module] &= ~flags; +} + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void *addr, int size, int access) +{ + int i, j; + MV_U32 memAddr = (MV_U32) addr; + + if (access == 0) + access = 1; + + if ((access != 4) && (access != 2) && (access != 1)) { + mvOsPrintf("%d wrong access size. Access must be 1 or 2 or 4\n", access); + return; + } + memAddr = MV_ALIGN_DOWN((unsigned int)addr, 4); + size = MV_ALIGN_UP(size, 4); + addr = (void *)MV_ALIGN_DOWN((unsigned int)addr, access); + while (size > 0) { + mvOsPrintf("%08x: ", memAddr); + i = 0; + /* 32 bytes in the line */ + while (i < 32) { + if (memAddr >= (MV_U32) addr) { + switch (access) { + case 1: + mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); + break; + + case 2: + mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); + break; + + case 4: + mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); + break; + } + } else { + for (j = 0; j < (access * 2 + 1); j++) + mvOsPrintf(" "); + } + i += access; + memAddr += access; + size -= access; + if (size <= 0) + break; + } + mvOsPrintf("\n"); + } +} + +void mvDebugPrintBufInfo(BUF_INFO *pBufInfo, int size, int access) +{ + if (pBufInfo == NULL) { + mvOsPrintf("\n!!! pBufInfo = NULL\n"); + return; + } + mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", + (unsigned int)pBufInfo, + (unsigned int)pBufInfo->cmdSts, (unsigned int)pBufInfo->pBuff, (unsigned int)pBufInfo->bufSize); + mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", + (unsigned int)pBufInfo->pData, + (unsigned int)pBufInfo->byteCnt, + (unsigned int)pBufInfo->pNextBufInfo, + (unsigned int)pBufInfo->userInfo1, (unsigned int)pBufInfo->userInfo2); + if (pBufInfo->pData != NULL) { + if (size > pBufInfo->byteCnt) + size = pBufInfo->byteCnt; + mvDebugMemDump(pBufInfo->pData, size, access); + } +} + +void mvDebugPrintPktInfo(MV_PKT_INFO *pPktInfo, int size, int access) +{ + int frag, len; + + if (pPktInfo == NULL) { + mvOsPrintf("\n!!! pPktInfo = NULL\n"); + return; + } + mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", + pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, + pPktInfo->pFrags, pPktInfo->osInfo); + + for (frag = 0; frag < pPktInfo->numFrags; frag++) { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pPktInfo->pFrags[frag].bufVirtPtr, pPktInfo->pFrags[frag].bufSize); + if (size > 0) { + len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); + mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); + size -= len; + } + } + +} + +void mvDebugPrintIpAddr(MV_U32 ipAddr) +{ + mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); +} + +void mvDebugPrintMacAddr(const MV_U8 *pMacAddr) +{ + int i; + + mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); + for (i = 1; i < MV_MAC_ADDR_SIZE; i++) + mvOsPrintf(":%02x", pMacAddr[i]); + + /* mvOsPrintf("\n"); */ +} + +/******* There are three functions deals with MV_DEBUG_TIMES structure ********/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES *pTimeEntry, int count, char *pName) +{ + pTimeEntry->begin = 0; + pTimeEntry->count = count; + pTimeEntry->end = 0; + pTimeEntry->left = pTimeEntry->count; + pTimeEntry->total = 0; + pTimeEntry->min = 0xFFFFFFFF; + pTimeEntry->max = 0x0; + strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name) - 1); + pTimeEntry->name[sizeof(pTimeEntry->name) - 1] = '\0'; +} + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES *pTimeEntry, MV_BOOL isTitle) +{ + int num; + + if (isTitle == MV_TRUE) + mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); + + num = pTimeEntry->count - pTimeEntry->left; + if (num > 0) { + mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", + pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total / num, + pTimeEntry->min, pTimeEntry->max); + } +} + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES *pTimeEntry) +{ + MV_U32 delta; + + if (pTimeEntry->left > 0) { + if (pTimeEntry->end <= pTimeEntry->begin) + delta = pTimeEntry->begin - pTimeEntry->end; + else + delta = ((MV_U32) 0x10000 - pTimeEntry->end) + pTimeEntry->begin; + + pTimeEntry->total += delta; + + if (delta < pTimeEntry->min) + pTimeEntry->min = delta; + + if (delta > pTimeEntry->max) + pTimeEntry->max = delta; + + pTimeEntry->left--; + } +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDebug.h u-boot-2009.08/board/marvell/common/mvDebug.h --- u-boot-2009.08.orig/board/marvell/common/mvDebug.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDebug.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,169 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDebugh +#define __INCmvDebugh + +/* includes */ +#include "mvTypes.h" + +typedef enum { + MV_MODULE_INVALID = -1, + MV_MODULE_ETH = 0, + MV_MODULE_IDMA, + MV_MODULE_XOR, + MV_MODULE_TWASI, + MV_MODULE_MGI, + MV_MODULE_USB, + MV_MODULE_CESA, + + MV_MODULE_MAX +} MV_MODULE_ID; + +/* Define generic flags useful for most of modules */ +#define MV_DEBUG_FLAG_ALL (0) +#define MV_DEBUG_FLAG_INIT (1 << 0) +#define MV_DEBUG_FLAG_RX (1 << 1) +#define MV_DEBUG_FLAG_TX (1 << 2) +#define MV_DEBUG_FLAG_ERR (1 << 3) +#define MV_DEBUG_FLAG_TRACE (1 << 4) +#define MV_DEBUG_FLAG_DUMP (1 << 5) +#define MV_DEBUG_FLAG_CACHE (1 << 6) +#define MV_DEBUG_FLAG_IOCTL (1 << 7) +#define MV_DEBUG_FLAG_STATS (1 << 8) + +extern MV_U32 mvDebug; +extern MV_U32 mvDebugModules[MV_MODULE_MAX]; + +#ifdef MV_DEBUG +# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) code +#elif defined(MV_RT_DEBUG) +# define MV_DEBUG_PRINT(module, flags, msg) \ + if ((mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags))) \ + mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) \ + if ((mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags))) \ + code +#else +# define MV_DEBUG_PRINT(module, flags, msg) +# define MV_DEBUG_CODE(module, flags, code) +#endif + +/* typedefs */ + +/* time measurement structure used to check how much time pass between + * two points + */ +typedef struct { + char name[20]; /* name of the entry */ + unsigned long begin; /* time measured on begin point */ + unsigned long end; /* time measured on end point */ + unsigned long total; /* Accumulated time */ + unsigned long left; /* The rest measurement actions */ + unsigned long count; /* Maximum measurement actions */ + unsigned long min; /* Minimum time from begin to end */ + unsigned long max; /* Maximum time from begin to end */ +} MV_DEBUG_TIMES; + +/* mvDebug.h API list */ + +/****** Error Recording ******/ + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void *addr, int size, int access); + +void mvDebugPrintBufInfo(BUF_INFO *pBufInfo, int size, int access); + +void mvDebugPrintPktInfo(MV_PKT_INFO *pPktInfo, int size, int access); + +void mvDebugPrintIpAddr(MV_U32 ipAddr); + +void mvDebugPrintMacAddr(const MV_U8 *pMacAddr); + +/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES *pTimeEntry, int count, char *name); + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES *pTimeEntry); + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES *pTimeEntry, MV_BOOL isTitle); + +/******** General ***********/ + +/* Change value of mvDebugPrint global variable */ + +void mvDebugInit(void); +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); + +#endif /* __INCmvDebug.h */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDeviceId.h u-boot-2009.08/board/marvell/common/mvDeviceId.h --- u-boot-2009.08.orig/board/marvell/common/mvDeviceId.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDeviceId.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,293 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceIdh +#define __INCmvDeviceIdh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MARVELL_VEN_ID 0x11ab + +/* Disco-3 */ +#define MV64460_DEV_ID 0x6480 +#define MV64460B_DEV_ID 0x6485 +#define MV64430_DEV_ID 0x6420 + +/* Disco-5 */ +#define MV64560_DEV_ID 0x6450 + +/* Disco-6 */ +#define MV64660_DEV_ID 0x6460 + +/* Orion */ +#define MV_1181_DEV_ID 0x1181 +#define MV_5181_DEV_ID 0x5181 +#define MV_5281_DEV_ID 0x5281 +#define MV_5182_DEV_ID 0x5182 +#define MV_8660_DEV_ID 0x8660 +#define MV_5180_DEV_ID 0x5180 +#define MV_5082_DEV_ID 0x5082 +#define MV_1281_DEV_ID 0x1281 +#define MV_6082_DEV_ID 0x6082 +#define MV_6183_DEV_ID 0x6183 +#define MV_6183L_DEV_ID 0x6083 + +#define MV_5281_D0_REV 0x4 +#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) +#define MV_5281_D0_NAME "88F5281 D0" + +#define MV_5281_D1_REV 0x5 +#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) +#define MV_5281_D1_NAME "88F5281 D1" + +#define MV_5281_D2_REV 0x6 +#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) +#define MV_5281_D2_NAME "88F5281 D2" + +#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ +#define MV_5181_A1_REV 0x1 /* for USB Er .. */ +#define MV_5181_B0_REV 0x2 +#define MV_5181_B1_REV 0x3 +#define MV_5182_A1_REV 0x1 +#define MV_5180N_B1_REV 0x3 +#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) + +/* kw */ +#define MV_6281_DEV_ID 0x6281 +#define MV_6282_DEV_ID 0x1155 +#define MV_6192_DEV_ID 0x6192 +#define MV_6190_DEV_ID 0x6190 +#define MV_6180_DEV_ID 0x6180 +#define MV_6280_DEV_ID 0x6280 + +#define MV_6281_A0_REV 0x2 +#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) +#define MV_6281_A0_NAME "88F6281 A0" + +#define MV_6192_A0_REV 0x2 +#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) +#define MV_6192_A0_NAME "88F6192 A0" + +#define MV_6190_A0_REV 0x2 +#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) +#define MV_6190_A0_NAME "88F6190 A0" + +#define MV_6180_A0_REV 0x2 +#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) +#define MV_6180_A0_NAME "88F6180 A0" + +#define MV_6281_A1_REV 0x3 +#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) +#define MV_6281_A1_NAME "88F6281 A1" + +#define MV_6282_A1_REV 0x3 +#define MV_6282_A1_ID ((MV_6282_DEV_ID << 16) | MV_6282_A1_REV) +#define MV_6282_A1_NAME "88F6282 A1" + +#define MV_6280_A1_REV 0x3 +#define MV_6280_A1_ID ((MV_6280_DEV_ID << 16) | MV_6280_A0_REV) +#define MV_6280_A1_NAME "88F6280 A1" + +#define MV_6192_A1_REV 0x3 +#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) +#define MV_6192_A1_NAME "88F6192 A1" + +#define MV_6190_A1_REV 0x3 +#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) +#define MV_6190_A1_NAME "88F6190 A1" + +#define MV_6180_A1_REV 0x3 +#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) +#define MV_6180_A1_NAME "88F6180 A1" + +#define MV_88F6XXX_A0_REV 0x2 +#define MV_88F6XXX_A1_REV 0x3 +/* Disco-Duo */ +#define MV_78XX0_ZY_DEV_ID 0x6381 +#define MV_78XX0_ZY_NAME "MV78X00" + +#define MV_78XX0_Z0_REV 0x1 +#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) +#define MV_78XX0_Z0_NAME "78X00 Z0" + +#define MV_78XX0_Y0_REV 0x2 +#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) +#define MV_78XX0_Y0_NAME "78X00 Y0" + +#define MV_78XX0_DEV_ID 0x7800 +#define MV_78XX0_NAME "MV78X00" + +#define MV_76100_DEV_ID 0x7610 +#define MV_78200_DEV_ID 0x7820 +#define MV_78100_DEV_ID 0x7810 +#define MV_78XX0_A0_REV 0x1 +#define MV_78XX0_A1_REV 0x2 + +#define MV_76100_NAME "MV76100" +#define MV_78100_NAME "MV78100" +#define MV_78200_NAME "MV78200" + +#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) + +#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) + +#define MV_76100_A0_NAME "MV76100 A0" +#define MV_78100_A0_NAME "MV78100 A0" +#define MV_78200_A0_NAME "MV78200 A0" +#define MV_78XX0_A0_NAME "MV78XX0 A0" + +#define MV_76100_A1_NAME "MV76100 A1" +#define MV_78100_A1_NAME "MV78100 A1" +#define MV_78200_A1_NAME "MV78200 A1" +#define MV_78XX0_A1_NAME "MV78XX0 A1" + +/*MV88F632X family*/ +#define MV_6321_DEV_ID 0x6321 +#define MV_6322_DEV_ID 0x6322 +#define MV_6323_DEV_ID 0x6323 + +#define MV_6321_NAME "88F6321" +#define MV_6322_NAME "88F6322" +#define MV_6323_NAME "88F6323" + +#define MV_632X_A1_REV 0x2 + +#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) + +#define MV_6321_A1_NAME "88F6321 A1" +#define MV_6322_A1_NAME "88F6322 A1" +#define MV_6323_A1_NAME "88F6323 A1" + +/*MV88F6500 family*/ +#define MV_65XX_DEV_ID 0x6500 +#define MV_6510_DEV_ID 0x6510 +#define MV_6530_DEV_ID 0x6530 +#define MV_6550_DEV_ID 0x6550 +#define MV_6560_DEV_ID 0x6560 + +#define MV_6510_Z0_REV 0x1 +#define MV_6510_Z0_ID ((MV_6510_DEV_ID << 16) | MV_6510_Z0_REV) +#define MV_6510_Z0_NAME "88F6510 Z0" + +#define MV_6530_Z0_REV 0x1 +#define MV_6530_Z0_ID ((MV_6530_DEV_ID << 16) | MV_6530_Z0_REV) +#define MV_6530_Z0_NAME "88F6530 Z0" + +#define MV_6550_Z0_REV 0x1 +#define MV_6550_Z0_ID ((MV_6550_DEV_ID << 16) | MV_6550_Z0_REV) +#define MV_6550_Z0_NAME "88F6550 Z0" + +#define MV_6560_Z0_REV 0x1 +#define MV_6560_Z0_ID ((MV_6560_DEV_ID << 16) | MV_6560_Z0_REV) +#define MV_6560_Z0_NAME "88F6560 Z0" + + +/* KW40 */ +#define MV_6710_DEV_ID 0x6710 + +#define MV_6710_Z1_REV 0x0 +#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV) +#define MV_6710_Z1_NAME "MV6710 Z1" + +/* Armada XP Family */ +#define MV_78130_DEV_ID 0x7813 +#define MV_78160_DEV_ID 0x7816 +#define MV_78230_DEV_ID 0x7823 +#define MV_78260_DEV_ID 0x7826 +#define MV_78460_DEV_ID 0x7846 +#define MV_78000_DEV_ID 0x7888 + +#define MV_FPGA_DEV_ID 0x2107 + +#define MV_78XX0_Z1_REV 0x0 + +#define MV_78130_Z1_ID ((MV_78130_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78130_Z1_NAME "MV78130 Z1" + +#define MV_78160_Z1_ID ((MV_78160_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78160_Z1_NAME "MV78160 Z1" + +#define MV_78230_Z1_ID ((MV_78230_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78230_Z1_NAME "MV78230 Z1" + +#define MV_78260_Z1_ID ((MV_78260_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78260_Z1_NAME "MV78260 Z1" + +#define MV_78460_Z1_ID ((MV_78460_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78460_Z1_NAME "MV78460 Z1" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDeviceIdh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvHalVer.h u-boot-2009.08/board/marvell/common/mvHalVer.h --- u-boot-2009.08.orig/board/marvell/common/mvHalVer.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvHalVer.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvHalVerh +#define __INCmvHalVerh + +/* Defines */ +#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" +#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" + +#endif /* __INCmvHalVerh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvList.h u-boot-2009.08/board/marvell/common/mvList.h --- u-boot-2009.08.orig/board/marvell/common/mvList.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvList.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,78 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvList_h__ +#define __mvList_h__ + +#include "mvCommon.h" +#include "mvOs.h" + +typedef struct mv_list { + struct mv_list *prev; + struct mv_list *next; + unsigned long data; + +} MV_LIST; + +static INLINE MV_LIST *mvListFind(MV_LIST *head, MV_ULONG data) +{ + return NULL; +} + +/* Add new element before head */ +static INLINE MV_LIST *mvListAddHead(MV_LIST **head, MV_ULONG data) +{ + MV_LIST *element; + + element = mvOsMalloc(sizeof(MV_LIST)); + if (element) { + element->data = data; + element->next = (*head); + element->prev = NULL; + if (*head) + (*head)->prev = element; + + *head = element; + } + return element; +} + +static INLINE MV_LIST *mvListDel(MV_LIST **list) +{ + MV_LIST *prev = (*list)->prev; + MV_LIST *next = (*list)->next; + + mvOsFree(*list); + + if (prev) + prev->next = next; + else + (*list) = next; + + if (next) + next->prev = prev; + + return next; +} + +#endif /* __mvList_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvStack.c u-boot-2009.08/board/marvell/common/mvStack.c --- u-boot-2009.08.orig/board/marvell/common/mvStack.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvStack.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvQueue.c +* +* FILENAME: $Workfile: mvStack.c $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file implements simple Stack LIFO functionality. +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvStack.h" + +/* defines */ + +/* Public functions */ + +/* Purpose: Create new stack + * Inputs: + * - MV_U32 noOfElements - maximum number of elements in the stack. + * Each element 4 bytes size + * Return: void* - pointer to created stack. + */ +void *mvStackCreate(int numOfElements) +{ + MV_STACK *pStack; + MV_U32 *pStackElements; + + pStack = (MV_STACK *) mvOsMalloc(sizeof(MV_STACK)); + pStackElements = (MV_U32 *) mvOsMalloc(numOfElements * sizeof(MV_U32)); + if ((pStack == NULL) || (pStackElements == NULL)) { + mvOsPrintf("mvStack: Can't create new stack\n"); + if (pStack) + mvOsFree(pStack); + if (pStackElements) + mvOsFree(pStackElements); + return NULL; + } + memset(pStackElements, 0, numOfElements * sizeof(MV_U32)); + pStack->numOfElements = numOfElements; + pStack->stackIdx = 0; + pStack->stackElements = pStackElements; + + return pStack; +} + +/* Purpose: Delete existing stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function + * + * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. + * MV_OK - Success. + */ +MV_STATUS mvStackDelete(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if ((pStack == NULL) || (pStack->stackElements == NULL)) + return MV_NOT_FOUND; + + mvOsFree(pStack->stackElements); + mvOsFree(pStack); + + return MV_OK; +} + +/* PrintOut status of the stack */ +void mvStackStatus(void *stackHndl, MV_BOOL isPrintElements) +{ + int i; + MV_STACK *pStack = (MV_STACK *) stackHndl; + + mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", + stackHndl, pStack->stackElements, pStack->numOfElements, pStack->stackIdx); + if (isPrintElements == MV_TRUE) { + for (i = 0; i < pStack->stackIdx; i++) + mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); + } +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvStack.h u-boot-2009.08/board/marvell/common/mvStack.h --- u-boot-2009.08.orig/board/marvell/common/mvStack.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvStack.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,133 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvStack_h__ +#define __mvStack_h__ + +/* includes */ +#include "mvTypes.h" + +/* defines */ + +/* typedefs */ +/* Data structure describes general purpose Stack */ +typedef struct { + int stackIdx; + int numOfElements; + MV_U32 *stackElements; +} MV_STACK; + +static INLINE MV_BOOL mvStackIsFull(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if (pStack->stackIdx == pStack->numOfElements) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE MV_BOOL mvStackIsEmpty(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if (pStack->stackIdx == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Purpose: Push new element to stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - New element. + * + * Return: MV_STATUS MV_FULL - Failure. Stack is full. + * MV_OK - Success. Element is put to stack. + */ +static INLINE void mvStackPush(void *stackHndl, MV_U32 value) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + +#ifdef MV_RT_DEBUG + if (pStack->stackIdx == pStack->numOfElements) { + mvOsPrintf("mvStackPush: Stack is FULL\n"); + return; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackElements[pStack->stackIdx] = value; + pStack->stackIdx++; +} + +/* Purpose: Pop element from the top of stack and copy it to "pValue" + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - Element in the top of stack. + * + * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. + * MV_OK - Success. Element is removed from the stack and + * copied to pValue argument + */ +static INLINE MV_U32 mvStackPop(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + +#ifdef MV_RT_DEBUG + if (pStack->stackIdx == 0) { + mvOsPrintf("mvStackPop: Stack is EMPTY\n"); + return 0; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackIdx--; + return pStack->stackElements[pStack->stackIdx]; +} + +static INLINE int mvStackIndex(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + return pStack->stackIdx; +} + +static INLINE int mvStackFreeElements(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + return (pStack->numOfElements - pStack->stackIdx); +} + +/* mvStack.h API list */ + +/* Create new Stack */ +void *mvStackCreate(int numOfElements); + +/* Delete existing stack */ +MV_STATUS mvStackDelete(void *stackHndl); + +/* Print status of the stack */ +void mvStackStatus(void *stackHndl, MV_BOOL isPrintElements); + +#endif /* __mvStack_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvTypes.h u-boot-2009.08/board/marvell/common/mvTypes.h --- u-boot-2009.08.orig/board/marvell/common/mvTypes.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvTypes.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,269 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTypesh +#define __INCmvTypesh + +/* Defines */ + +/* The following is a list of Marvell status */ +#define MV_ERROR (-1) +#define MV_OK (0) /* Operation succeeded */ +#define MV_FAIL (1) /* Operation failed */ +#define MV_BAD_VALUE (2) /* Illegal value (general) */ +#define MV_OUT_OF_RANGE (3) /* The value is out of range */ +#define MV_BAD_PARAM (4) /* Illegal parameter in function called */ +#define MV_BAD_PTR (5) /* Illegal pointer value */ +#define MV_BAD_SIZE (6) /* Illegal size */ +#define MV_BAD_STATE (7) /* Illegal state of state machine */ +#define MV_SET_ERROR (8) /* Set operation failed */ +#define MV_GET_ERROR (9) /* Get operation failed */ +#define MV_CREATE_ERROR (10) /* Fail while creating an item */ +#define MV_NOT_FOUND (11) /* Item not found */ +#define MV_NO_MORE (12) /* No more items found */ +#define MV_NO_SUCH (13) /* No such item */ +#define MV_TIMEOUT (14) /* Time Out */ +#define MV_NO_CHANGE (15) /* Parameter(s) is already in this value */ +#define MV_NOT_SUPPORTED (16) /* This request is not support */ +#define MV_NOT_IMPLEMENTED (17) /* Request supported but not implemented */ +#define MV_NOT_INITIALIZED (18) /* The item is not initialized */ +#define MV_NO_RESOURCE (19) /* Resource not available (memory ...) */ +#define MV_FULL (20) /* Item is full (Queue or table etc...) */ +#define MV_EMPTY (21) /* Item is empty (Queue or table etc...) */ +#define MV_INIT_ERROR (22) /* Error occured while INIT process */ +#define MV_HW_ERROR (23) /* Hardware error */ +#define MV_TX_ERROR (24) /* Transmit operation not succeeded */ +#define MV_RX_ERROR (25) /* Recieve operation not succeeded */ +#define MV_NOT_READY (26) /* The other side is not ready yet */ +#define MV_ALREADY_EXIST (27) /* Tried to create existing item */ +#define MV_OUT_OF_CPU_MEM (28) /* Cpu memory allocation failed. */ +#define MV_NOT_STARTED (29) /* Not started yet */ +#define MV_BUSY (30) /* Item is busy. */ +#define MV_TERMINATE (31) /* Item terminates it's work. */ +#define MV_NOT_ALIGNED (32) /* Wrong alignment */ +#define MV_NOT_ALLOWED (33) /* Operation NOT allowed */ +#define MV_WRITE_PROTECT (34) /* Write protected */ +#define MV_DROPPED (35) /* Packet dropped */ +#define MV_STOLEN (36) /* Packet stolen */ + +#define MV_INVALID (int)(-1) + +#define MV_FALSE 0 +#define MV_TRUE (!(MV_FALSE)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef MV_ASMLANGUAGE +/* typedefs */ + +typedef char MV_8; +typedef unsigned char MV_U8; + +typedef int MV_32; +typedef unsigned int MV_U32; + +typedef short MV_16; +typedef unsigned short MV_U16; + +#ifdef MV_PPC64 +typedef long MV_64; +typedef unsigned long MV_U64; +#else +typedef long long MV_64; +typedef unsigned long long MV_U64; +#endif + +typedef long MV_LONG; /* 32/64 */ +typedef unsigned long MV_ULONG; /* 32/64 */ + +typedef int MV_STATUS; +typedef int MV_BOOL; +typedef void MV_VOID; +typedef float MV_FLOAT; +/*typedef _Bool MV_STD_BOOL;*/ + +typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ +typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double */ +typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ + +typedef MV_U32 MV_KHZ; +typedef MV_U32 MV_MHZ; +typedef MV_U32 MV_HZ; + +/* This enumerator describes the set of commands that can be applied on */ +/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ +/* status (see MV_STATE enumerator) */ +/* Start can be applied only when status is IDLE */ +/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ +/* Pause can be applied only when status is ACTIVE */ +/* Restart can be applied only when status is PAUSED */ +typedef enum _mvCommand { + MV_START, /* Start */ + MV_STOP, /* Stop */ + MV_PAUSE, /* Pause */ + MV_RESTART /* Restart */ +} MV_COMMAND; + +/* This enumerator describes the set of state conditions. */ +/* Moving from one state to other is stricted. */ +typedef enum _mvState { + MV_IDLE, + MV_ACTIVE, + MV_PAUSED, + MV_UNDEFINED_STATE +} MV_STATE; + +typedef enum { + ETH_MAC_SPEED_10M, + ETH_MAC_SPEED_100M, + ETH_MAC_SPEED_1000M, + ETH_MAC_SPEED_AUTO, + +} MV_ETH_MAC_SPEED; + +/* This structure describes address space window. Window base can be */ +/* 64 bit, window size up to 4GB */ +typedef struct _mvAddrWin { + MV_U32 baseLow; /* 32bit base low */ + MV_U32 baseHigh; /* 32bit base high */ + MV_U32 size; /* 32bit size */ +} MV_ADDR_WIN; + +/* This binary enumerator describes protection attribute status */ +typedef enum _mvProtRight { + ALLOWED, /* Protection attribute allowed */ + FORBIDDEN /* Protection attribute forbidden */ +} MV_PROT_RIGHT; + +/* Unified struct for Rx and Tx packet operations. The user is required to */ +/* be familier only with Tx/Rx descriptor command status. */ +typedef struct _bufInfo { + MV_U32 cmdSts; /* Tx/Rx command status */ + MV_U16 byteCnt; /* Size of valid data in the buffer */ + MV_U16 bufSize; /* Total size of the buffer */ + MV_U8 *pBuff; /* Pointer to Buffer */ + MV_U8 *pData; /* Pointer to data in the Buffer */ + MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ + MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ + struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ +} BUF_INFO; + +/* This structure contains information describing one of buffers + * (fragments) they are built Ethernet packet. + */ +typedef struct { + MV_U8 *bufVirtPtr; + MV_ULONG bufPhysAddr; + MV_U32 bufSize; + MV_U32 dataSize; + MV_U32 memHandle; + MV_32 bufAddrShift; +} MV_BUF_INFO; + +/* This structure contains information describing Ethernet packet. + * The packet can be divided for few buffers (fragments) + */ +typedef struct { + MV_ULONG osInfo; + MV_BUF_INFO *pFrags; + MV_U32 status; + MV_U16 pktSize; + MV_U16 numFrags; + MV_U32 ownerId; + MV_U32 fragIP; + MV_U32 txq; +} MV_PKT_INFO; + +/* This structure describes SoC units address decode window */ +typedef struct { + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + MV_U8 attrib; /* chip select attributes */ + MV_U8 targetId; /* Target Id of this MV_TARGET */ +} MV_UNIT_WIN_INFO; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights { + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +} MV_ACCESS_RIGHTS; + +typedef struct _mvDecRegs { + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 ctrlReg; +} MV_DEC_REGS; + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvTypesh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvVideo.h u-boot-2009.08/board/marvell/common/mvVideo.h --- u-boot-2009.08.orig/board/marvell/common/mvVideo.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvVideo.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvVideoh +#define __INCmvVideoh + +/* includes */ + +/* Defines */ + +typedef struct mvVideoResolution { + MV_U32 width; + MV_U32 height; + char *name; +} MV_VIDEO_RESOLUTION; + +/* + * Basic window sizes. + */ + +#define VGA_WIDTH 640 +#define VGA_HEIGHT 480 +#define QVGA_WIDTH 320 +#define QVGA_HEIGHT 240 +#define CIF_WIDTH 352 +#define CIF_HEIGHT 288 +#define QCIF_WIDTH 176 +#define QCIF_HEIGHT 144 + +#define MV_VIDEO_RESOLUTION_VGA {VGA_WIDTH, VGA_HEIGHT, "VGA"} +#define MV_VIDEO_RESOLUTION_QVGA {QVGA_WIDTH, QVGA_HEIGHT, "QVGA"} +#define MV_VIDEO_RESOLUTION_CIF {CIF_WIDTH, CIF_HEIGHT, "CIF"} +#define MV_VIDEO_RESOLUTION_QCIF {QCIF_WIDTH, QCIF_HEIGHT, "QCIF"} + +/* Pixel format */ +typedef enum mvPixFormatId { + MV_PIX_FORMAT_ID_RGB444 = 0x444, + MV_PIX_FORMAT_ID_RGB555 = 0x555, + MV_PIX_FORMAT_ID_RGB565 = 0x565, + MV_PIX_FORMAT_ID_YUV422 = 0x422, + MV_PIX_FORMAT_ID_RAW_BAYER = 0x111, +} MV_PIX_FORMAT_ID; + +typedef struct mvPixelFormat { + MV_PIX_FORMAT_ID id; + char *name; +} MV_PIXEL_FORMAT; + +/* known formats */ +#define MV_PIXEL_FORMAT_RGB444 {MV_PIX_FORMAT_ID_RGB444, "RGB444"} +#define MV_PIXEL_FORMAT_RGB555 {MV_PIX_FORMAT_ID_RGB555, "RGB555"} +#define MV_PIXEL_FORMAT_RGB565 {MV_PIX_FORMAT_ID_RGB565, "RGB565"} +#define MV_PIXEL_FORMAT_YUV422 {MV_PIX_FORMAT_ID_YUV422, "YUV422"} +#define MV_PIXEL_FORMAT_RAW_BAYER {MV_PIX_FORMAT_ID_RAW_BAYER, "RAW BAYER"} + +typedef struct { + MV_PIXEL_FORMAT pixelFormat; + MV_VIDEO_RESOLUTION resolution; +} MV_IMAGE_FORMAT; + +#endif /* __INCmvVideoh */ diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config_def.mk u-boot-2009.08/board/marvell/config_armada_xp/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config_def.mk 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config.mk u-boot-2009.08/board/marvell/config_armada_xp/config.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config.mk 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config_nand.mk u-boot-2009.08/board/marvell/config_armada_xp/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/marvell/mv_dove/nBootstrap.o +NAND_OBJS += ./board/marvell/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/Makefile u-boot-2009.08/board/marvell/config_armada_xp/Makefile --- u-boot-2009.08.orig/board/marvell/config_armada_xp/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,113 @@ +include mvRules.mk + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +##$(HAL_SYS_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysCesa.o +##$(HAL_SYS_DIR)/mvSysAudio.o $(HAL_SYS_DIR)/mvSysCamController.o $(HAL_IF_DIR)/mvSysTdm.o + +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSpi.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + +# ## $(HAL_AC97_DIR)/mvAc97.o +# ## $(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/dac/mvCLAudioCodec.o +# ## $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +# ## $(HAL_CAMERA_DIR)/mvCamController.o $(HAL_CAMERA_DIR)/mvCamAddrDec.o +# ## $(HAL_CAMERA_DIR)/OV7680CamSensor.o +## $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o + +HAL_OBJS = $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o \ + $(HAL_NFC_DIR)/mvNfc.o + + +SOC_OBJS = $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o \ + $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o \ + $(SOC_DIR)/mv_phy.o $(SOC_DIR)/cmd_bubt.o $(SOC_DIR)/cmd_bios.o \ + $(SOC_DIR)/cmd_resetenv.o $(SOC_DIR)/cmd_pcie.o $(SOC_DIR)/cmd_ddr.o $(SOC_DIR)/cmd_sar.o + +##ifneq ($(MV_TINY_IMAGE), y) +##SOC_OBJS += $(HAL_PCIIF_DIR)/pci_util/mvPciUtils.o +##endif $(USP_DIR)/cmd_rcvr +## $(USP_DIR)/mv_nfc_nand.o +##$(USP_DIR)/cmd_loadnet.o + +USP_OBJS = $(USP_DIR)/mv_serial.o $(USP_DIR)/nand_nfc.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o \ + $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_flash.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o \ + $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o \ + $(USP_DIR)/mv_tsc2005.o \ + $(USP_DIR)/mv_sdhci.o $(USP_DIR)/mv_spi.o \ + $(USP_DIR)/mv_usb.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + + + +# ## $(HAL_SFLASH_DIR)/mvSFlash.o \ +# ## $(HAL_FLASH_DIR)/mvFlash.o $(HAL_FLASH_DIR)/mvAmdFlash.o \ +# ## $(HAL_FLASH_DIR)/mvIntelFlash.o $(HAL_FLASH_DIR)/mvFlashCom.o +# ## $(HAL_MFLASH_DIR)/mvMFlash.o +# ## $(HAL_MFLASH_DIR)/mvSMFlash.o $(HAL_MFLASH_DIR)/mvPMFlash.o + +# ##ifeq ($(NAND_BOOT), y) +# ##USP_OBJS += $(USP_DIR)/nBootloader.o +# ##endif + + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ +# $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o + + +## $(SOC_SYS_DIR)/mvCpuIfInit.o - do we need this?? + +# ifeq ($(NAND_BOOT), y) +# SOBJS += ../mv_dsmp/nBootstrap.o +# endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/mvRules.mk u-boot-2009.08/board/marvell/config_armada_xp/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,89 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = armada_xp +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/marvell +HAL_DIR = $(SRC_PATH)/mv_hal + +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +#HAL_DRAM_DIR = $(HAL_DIR)/ddr2_3 +#HAL_SPD_DIR = $(HAL_DIR)/ddr2_3/spd +HAL_DRAM_DIR = $(HAL_DIR)/ddr2_3/bak +HAL_SPD_DIR = $(HAL_DIR)/ddr2_3/bak/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +#HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa +HAL_NFC_DIR = $(HAL_DIR)/nfc + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_IF_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) -I$(USP_ETH_SWITCH_DIR) -I$(HAL_IF_DIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_SYS_DIR) -I$(SOC_ENV_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(CONFIG_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) -I$(TOPDIR) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-nand.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0xA0000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0xAFFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k-header.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/marvell/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0xA0000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0xAFFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_16mb.mk u-boot-2009.08/board/marvell/config_kw/config_16mb.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_16mb.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_16mb.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_def.mk u-boot-2009.08/board/marvell/config_kw/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_def.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config.mk u-boot-2009.08/board/marvell/config_kw/config.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,13 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_nand.mk u-boot-2009.08/board/marvell/config_kw/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_prpmc.mk u-boot-2009.08/board/marvell/config_kw/config_prpmc.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_prpmc.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_prpmc.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/Makefile u-boot-2009.08/board/marvell/config_kw/Makefile --- u-boot-2009.08.orig/board/marvell/config_kw/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,86 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o +##$(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +##$(HAL_TS_DIR)/mvTsu.o $(HAL_TS_DIR)/mvTsuAddrDec.o + +HAL_OBJS = $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o + +#$(HAL_IF_DIR)/mvSysTs.o +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysCesa.o $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysSpi.o $(HAL_IF_DIR)/mvSysTdm.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_service.o \ + $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +USP_OBJS = $(USP_DIR)/cmd_rcvr.o $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o $(USP_DIR)/mv_spi.o\ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o $(USP_DIR)/mv_mmc.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o $(USP_DIR)/mv_usb.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + +#ifeq ($(NAND_BOOT), y) +#USP_OBJS += $(USP_DIR)/nBootloader.o +#endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += ../mv_kw/nBootstrap.o +endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/mvRules.mk u-boot-2009.08/board/marvell/config_kw/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_kw/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,85 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = kw +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DIR)/ddr2/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) -I$(HAL_PCIIF_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(CONFIG_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot_16mb.lds u-boot-2009.08/board/marvell/config_kw/u-boot_16mb.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot_16mb.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot_16mb.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot.lds u-boot-2009.08/board/marvell/config_kw/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-nand.lds u-boot-2009.08/board/marvell/config_kw/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header-nand.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_16mb.mk u-boot-2009.08/board/marvell/config_kw2/config_16mb.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_16mb.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_16mb.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_def.mk u-boot-2009.08/board/marvell/config_kw2/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_def.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config.mk u-boot-2009.08/board/marvell/config_kw2/config.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_nand.mk u-boot-2009.08/board/marvell/config_kw2/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_prpmc.mk u-boot-2009.08/board/marvell/config_kw2/config_prpmc.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_prpmc.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_prpmc.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/Makefile u-boot-2009.08/board/marvell/config_kw2/Makefile --- u-boot-2009.08.orig/board/marvell/config_kw2/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,86 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +##$(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/mvAudioAddrDec.o mvDramIf.c +##$(HAL_TS_DIR)/mvTsu.o $(HAL_TS_DIR)/mvTsuAddrDec.o +HAL_OBJS = $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o + +##$(HAL_IF_DIR)/mvSysTs.o +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysCesa.o $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysSpi.o $(HAL_IF_DIR)/mvSysTdm.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_phy.o \ + $(SOC_DIR)/cmd_sar.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_ENV_DIR)/mvCtrlEthCompLib.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +USP_OBJS = $(USP_DIR)/cmd_rcvr.o $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o $(USP_DIR)/mv_spi.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o $(USP_DIR)/mv_mmc.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o $(USP_DIR)/mv_usb.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + +#ifeq ($(NAND_BOOT), y) +#USP_OBJS += $(USP_DIR)/nBootloader.o +#endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += ../mv_kw2/nBootstrap.o +endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/mvRules.mk u-boot-2009.08/board/marvell/config_kw2/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,85 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = kw2 +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DIR)/ddr2/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +#HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) -I$(USP_ETH_SWITCH_DIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(CONFIG_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot_16mb.lds u-boot-2009.08/board/marvell/config_kw2/u-boot_16mb.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot_16mb.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot_16mb.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot.lds u-boot-2009.08/board/marvell/config_kw2/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-nand.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-tiny.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-tiny.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,1950 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "eth/gbe/mvEthRegs.h" +#include "gpp/mvGppRegs.h" + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +extern MV_BOARD_INFO *boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; +extern MV_U8 mvDbDisableModuleDetection; + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_U32 nandDev; + MV_U32 reg; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + } + + nandDev = boardGetDevCSNum(0, BOARD_DEV_NAND_FLASH); + if (nandDev != 0xFFFFFFFF) { + /* Set NAND interface access parameters */ + nandDev = BOOT_CS; + MV_REG_WRITE(DEV_BANK_PARAM_REG(nandDev), BOARD_INFO(boardId)->nandFlashReadParams); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(nandDev), BOARD_INFO(boardId)->nandFlashWriteParams); + MV_REG_WRITE(DEV_NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl); + } + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValMid); + MV_REG_WRITE(GPP_DATA_OUT_REG(2), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValMid); + mvGppPolaritySet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Set GPP Out Enable */ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValMid); + mvGppTypeSet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); + + /* TODO FIXME */ +#if 0 + reg = MV_REG_READ(0x184e0); + reg &= ~0x3; + MV_REG_WRITE(0x184e0, reg); +#endif + +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsSPrintf(pNameBuff, "Board unknown.\n"); + return MV_ERROR; + } + if (mvCtrlModelRevGet() == MV_6710_Z1_ID) { + mvOsSPrintf(pNameBuff, "%s", "DB-6710-Z1"); + } else { + mvOsSPrintf(pNameBuff, "%s", BOARD_INFO(boardId)->boardName); + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + /* MV_U32 boardId = mvBoardIdGet(); */ + if (ethPortNum > 1) + return MV_TRUE; +#if 0 + if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod == MV_BOARD_MII_GMII) { + if (ethPortNum < 1) /* Port 0 and 1 can be connected as GMII module */ + return MV_TRUE; + } +#endif + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ +#ifdef TCLK_AUTO_DETECT + MV_U8 coreClock = 0; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_TCLCK0_MASK) != 0) + coreClock = 1; + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & MSAR_TCLCK1_MASK) != 0) + coreClock += 2; + + switch (coreClock) { + case 1: + return MV_BOARD_TCLK_166MHZ; + case 3: + return MV_BOARD_TCLK_200MHZ; + default: + return MV_BOARD_TCLK_250MHZ; + } +#else + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + return MV_BOARD_TCLK_250MHZ; +#endif +} + +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock , i.e. DDR clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardSysClkGet(MV_VOID) +{ +#ifdef SYSCLK_AUTO_DETECT + MV_U32 idx; + MV_U32 cpuFreqMhz, ddrFreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */ + cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */ + cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */ + ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr; + /* round up to integer MHz */ + if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5) + ddrFreqMhz++; + + return ddrFreqMhz * 1000000; + } else + return 0; +#else + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + return MV_BOARD_DEFAULT_SYSCLK; +#endif +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displied in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val[MV_GPP_MAX_GROUP] = {0}; + MV_U32 mask[MV_GPP_MAX_GROUP] = {0}; + MV_U32 digitMask; + MV_U32 i, pinNum, gppGroup; + MV_U32 boardId = mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + hexNum &= (1 << BOARD_INFO(boardId)->activeLedsNumber) - 1; + + for (i = 0, digitMask = 1; i < BOARD_INFO(boardId)->activeLedsNumber; i++, digitMask <<= 1) { + if (hexNum & digitMask) { + pinNum = BOARD_INFO(boardId)->pLedGppPin[i]; + gppGroup = pinNum / 32; + val[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + mask[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + } + } + + for (gppGroup = 0; gppGroup < MV_GPP_MAX_GROUP; gppGroup++) { + mvGppValueSet(gppGroup, mask[gppGroup], + BOARD_INFO(boardId)->ledsPolarity == 0 ? val[gppGroup] : ~val[gppGroup]); + } +} + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* gppClass - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS gppClass, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == gppClass) { + if (indexFound == index) + return (MV_U32) BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + } + } + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) { + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(0), (1 << resetPin)); + MV_REG_BIT_RESET(GPP_DATA_OUT_EN_REG(0), (1 << resetPin)); + } else { + /* No gpp reset pin was found, try to reset ussing + ** system reset out */ + MV_REG_BIT_SET(CPU_RSTOUTN_MASK_REG, BIT2); + MV_REG_BIT_SET(CPU_SYS_SOFT_RST_REG, BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); +} + +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* type - Type of SDIO GPP to get. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type) +{ + if ((type != BOARD_GPP_SDIO_POWER) && (type != BOARD_GPP_SDIO_DETECT) && (type != BOARD_GPP_SDIO_WP)) + return MV_FAIL; + + return mvBoarGpioPinNumGet(type, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + } + + switch (gppGrp) { + case (0): + return BOARD_INFO(boardId)->intsGppMaskLow; + break; + case (1): + return BOARD_INFO(boardId)->intsGppMaskMid; + break; + case (2): + return BOARD_INFO(boardId)->intsGppMaskHigh; + break; + default: + return MV_ERROR; + } +} + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represents MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + MV_U32 mppMod; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + } + + mppMod = BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod; + if (mppMod >= BOARD_INFO(boardId)->numBoardMppConfigValue) + mppMod = 0; /* default */ + + return BOARD_INFO(boardId)->pBoardMppConfigValue[mppMod].mppGroup[mppGroupNum]; +} + +/******************************************************************************* +* mvBoardGppConfigGet +* +* DESCRIPTION: +* Get board configuration according to the input configuration GPP's. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The value of the board configuration GPP's. +* +*******************************************************************************/ +MV_U32 mvBoardGppConfigGet(void) +{ + MV_U32 boardId, i; + MV_U32 result = 0; + MV_U32 gpp; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGppConfigGet: Board unknown.\n"); + return 0; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_GPP_CONF) { + gpp = BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + result <<= 1; + result |= (mvGppValueGet(gpp >> 5, 1 << (gpp & 0x1F)) >> (gpp & 0x1F)); + } + } + return result; + +} + +/******************************************************************************* +* mvBoardTdmSpiModeGet - return SLIC/DAA connection +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardTdmSpiModeGet(MV_VOID) +{ + return DUAL_CHIP_SELECT_MODE; +} + +/******************************************************************************* +* mvBoardTdmDevicesCountGet +* +* DESCRIPTION: +* Return the number of TDM devices on board. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Number of devices. +* +*******************************************************************************/ +MV_U8 mvBoardTdmDevicesCountGet(void) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return 0; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + return BOARD_INFO(boardId)->numBoardTdmInfo[index]; +} + +/******************************************************************************* +* mvBoardTdmSpiCsGet +* +* DESCRIPTION: +* Return the SPI Chip-select number for a given device. +* +* INPUT: +* devId - The Slic device ID to get the SPI CS for. +* +* OUTPUT: +* None. +* +* RETURN: +* The SPI CS if found, -1 otherwise. +* +*******************************************************************************/ +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return -1; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + if (devId >= BOARD_INFO(boardId)->numBoardTdmInfo[index]) + return -1; + + return BOARD_INFO(boardId)->pBoardTdmInt2CsInfo[index][devId].spiCs; +} + +/******************************************************************************* +* mvBoardModuleTypePrint +* +* DESCRIPTION: +* Print on-board detected modules. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + mvOsOutput("Modules Detected:\n"); + + /* TDM */ + if (mvBoardTdmDevicesCountGet() > 0) + mvOsOutput(" TDM module.\n"); + + return; +} + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devNum; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + foundIndex++; + } + + return foundIndex; +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devIndex; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) { + if (foundIndex == devNum) + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/******************************************************************************* +* boardGetDevCSNum +* +* DESCRIPTION: +* Return the device's chip-select number. +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardTwsiAddrTypeGet - +* +* DESCRIPTION: +* Return the TWSI address type for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address type. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + } + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiAddrGet - +* +* DESCRIPTION: +* Return the TWSI address for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + } + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in bytes +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId = mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; + +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + if (gBoardId == -1) { + /* Use DB as default */ + gBoardId = DB_88F78XX0_BP_ID; + } + + return gBoardId; +} + +/******************************************************************************* +* mvBoardTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + + twsiSlave.validOffset = MV_TRUE; + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + + if (MV_OK != mvTwsiRead(0, &twsiSlave, &data, 1)) { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoardTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", + twsiSlave.slaveAddr.address, twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + if (MV_OK != mvTwsiWrite(0, &twsiSlave, ®Val, 1)) { + DB(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* SatR Configuration functions +*******************************************************************************/ +MV_U8 mvBoardFabFreqGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + return ((sar0 & 0x1E) >> 1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + sar0 &= ~(0xF << 1); + sar0 |= (freqVal & 0xF) << 1; + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardFabFreqModeGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(3, 0); + return (sar0 & 0x1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqModeSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(3, 0); + sar0 &= ~(0x1); + sar0 |= (freqVal & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqModeGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + return (sar0 & 0x1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqModeSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + sar0 &= ~(0x1); + sar0 |= (freqVal & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + return ((sar & 0x1C) >> 2); +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + sar &= ~(0x7 << 2); + sar |= (freqVal & 0x7) << 2; + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuFreq S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + return (sar & 0x7); +} + +/*******************************************************************************/ +MV_STATUS mvBoardBootDevSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + sar &= ~(0x7); + sar |= (val & 0x7); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB(mvOsPrintf("Board: Write BootDev S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDev S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevWidthGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + return (sar & 0x18) >> 3; +} + +/*******************************************************************************/ +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + sar &= ~(0x3 << 3); + sar |= ((val & 0x3) << 3); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB(mvOsPrintf("Board: Write BootDevWidth S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDevWidth S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardCpu0CoreModeGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + return (sar & 0x18) >> 3; +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpu0CoreModeSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + sar &= ~(0x3 << 3); + sar |= ((val & 0x3) << 3); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB(mvOsPrintf("Board: Write Cpu0CoreMode S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write Cpu0CoreMode S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardL2SizeGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + return (sar & 0x3); +} + +/*******************************************************************************/ +MV_STATUS mvBoardL2SizeSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + sar &= ~(0x3); + sar |= (val & 0x3); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB(mvOsPrintf("Board: Write L2Size S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write L2Size S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardCpuCoresNumGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + return (sar & 0x6) >> 1; +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val) +{ + MV_U8 sar, temp; + + sar = mvBoardTwsiSatRGet(3, 0); + sar &= ~(0x3 << 1); + sar |= ((val & 0x3) << 1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB(mvOsPrintf("Board: Write CpuCoreNum S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuCoreNum S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvBoardConfIdSet(MV_U16 conf) +{ + if (MV_OK != mvBoardTwsiSatRSet(0, 1, conf)) { + DB(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardConfIdGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 1); + return (sar & 0xFF); +} +/******************************************************************************* +* End of SatR Configuration functions +*******************************************************************************/ + +/******************************************************************************* +* mvBoardMppModulesScan +* +* DESCRIPTION: +* Scan for modules connected through MPP lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardMppModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if (boardId == DB_88F78XX0_BP_ID) { + twsiSlave.slaveAddr.address = MV_BOARD_MPP_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_MPP_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + switch (regVal) { + case MV_BOARD_LCD_DVI_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_LCD_DVI; + return MV_OK; + + case MV_BOARD_MII_GMII_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_MII_GMII; + return MV_OK; + + case MV_BOARD_TDM_MODULE_ID: + /* + TODO - how to distinguish between SLIC types? + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_3215; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_880; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_792; + return MV_OK; + */ + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_OTHER; + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_TDM_32CH; + return MV_OK; + + default: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_OTHER; + DB(mvOsPrintf("mvBoardMppModulesScan: Unsupported module!\n")); + break; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardOtherModulesScan +* +* DESCRIPTION: +* Scan for modules connected through SERDES/LVDS/... lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardOtherModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if (boardId == DB_88F78XX0_BP_ID) { + /* reset modules flags */ + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_NONE; + + /* SERDES module (only PEX moduel is supported now) */ + twsiSlave.slaveAddr.address = MV_BOARD_PEX_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_PEX_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_PEX_MODULE_ID) { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "PEX module DETECTED!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_PEX; + } else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ PEX module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + + /* LVDS (LCD) module */ + twsiSlave.slaveAddr.address = MV_BOARD_LVDS_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_LVDS_MODULE_ADDR_TYPE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_LVDS_MODULE_ID) + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_LVDS; + else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ LVDS module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPexModuleConnected +* +* DESCRIPTION: +* Check if PEX module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsPexModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + /* TODO - remove this after finishing debug */ + /*return MV_TRUE;*/ + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsPexModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_PEX) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLvdsModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLvdsModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsLvdsModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_LVDS) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLcdDviModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLcdDviModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsLcdDviModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod & MV_BOARD_LCD_DVI) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTwsiMuxChannelSet +* +* DESCRIPTION: +* Set the channel number of the on-board TWSI mux. +* +* INPUT: +* chNum - The channel number to set. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum) +{ + static MV_U8 currChNum = 0xFF; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if (currChNum == muxChNum) + return MV_OK; + + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_TWSI_MUX, 0); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_TWSI_MUX, 0); + twsiSlave.validOffset = 0; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + muxChNum += 4; + return mvTwsiWrite(0, &twsiSlave, &muxChNum, 1); +} + +/******************************************************************************* +* mvBoardTwsiReadByteThruMux +* +* DESCRIPTION: +* Read a single byte from a TWSI device through the TWSI Mux. +* +* INPUT: +* muxChNum - The Twsi Mux channel number to read through. +* chNum - The TWSI channel number. +* pTwsiSlave - The TWSI slave address. +* data - Buffer to read into (1 byte). +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data) +{ + MV_STATUS res; + + /* Set Mux channel */ + res = mvBoardTwsiMuxChannelSet(muxChNum); + if (res == MV_OK) + res = mvTwsiRead(chNum, pTwsiSlave, data, 1); + + return res; +} + +/******************************************************************************* +* mvBoardMppGet - Get board SERDES configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* SERDES configuration structure or NULL on error +* +*******************************************************************************/ +MV_SERDES_CFG *mvBoardSerdesCfgGet(void) +{ + MV_U32 boardId; + MV_U32 serdesCfg = 0; /* default */ + + boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) { + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return NULL; + } + + if (mvBoardIsPexModuleConnected()) + serdesCfg = 1; + + return &BOARD_INFO(boardId)->pBoardSerdesConfigValue[serdesCfg]; +} + + +/******************************************************************************* +* mvBoardPexInfoGet - Get board PEX Info +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +*******************************************************************************/ +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) { + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return NULL; + } + + return &BOARD_INFO(boardId)->boardPexInfo; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,401 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + +/* +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +*/ +#define MV_BOARD_MAX_USB_IF 3 +#define MV_BOARD_MAX_MPP 9 /* number of MPP conf registers */ +#define MV_BOARD_NAME_LEN 0x20 + +/* EPPROM Modules detection information */ + +#define MV_BOARD_EEPROM_MODULE_ADDR 0x50 +#define MV_BOARD_EEPROM_MODULE_ADDR_TYPE ADDR7_BIT + +#define MV_BOARD_PEX_MODULE_ADDR 0x23 +#define MV_BOARD_PEX_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_PEX_MODULE_ID 0 + +#define MV_BOARD_LVDS_MODULE_ADDR 0x41 +#define MV_BOARD_LVDS_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LVDS_MODULE_ID 0 + +#define MV_BOARD_MPP_MODULE_ADDR 0x40 +#define MV_BOARD_MPP_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LCD_DVI_MODULE_ID 0 +#define MV_BOARD_TDM_MODULE_ID 1 +#define MV_BOARD_MII_GMII_MODULE_ID 4 + +typedef enum { + BOARD_EPON_CONFIG, + BOARD_GPON_CONFIG, + BOARD_PON_NONE, + BOARD_PON_AUTO +} MV_BOARD_PON_CONFIG; + +typedef struct _boardData { + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; +} BOARD_DATA; + +typedef enum _devBoardMppGroupClass { + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MPP_GROUP_3, + MV_BOARD_MAX_MPP_GROUP +} MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass { + MV_BOARD_AUTO = 0, + MV_BOARD_TDM_32CH, + MV_BOARD_LCD_DVI, + MV_BOARD_MII_GMII, + MV_BOARD_OTHER +} MV_BOARD_MPP_TYPE_CLASS; + +typedef enum _devBoardOtherTypeClass { + MV_BOARD_NONE = 0x00000000, + MV_BOARD_LVDS = 0x00000001, + MV_BOARD_PEX = 0x00000002, + MV_BOARD_UNKNOWN = 0x80000000 +} MV_BOARD_OTHER_TYPE_CLASS; + +#define MV_BOARD_TDM MV_BOARD_TDM_32CH + +typedef struct _boardModuleTypeInfo { + MV_BOARD_MPP_TYPE_CLASS boardMppMod; + MV_BOARD_OTHER_TYPE_CLASS boardOtherMod; +} MV_BOARD_MODULE_TYPE_INFO; + +typedef enum _devBoardClass { + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER, +} MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass { + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_MUX, + BOARD_TWSI_OTHER +} MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass { + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_CONF, + BOARD_GPP_OTHER +} MV_BOARD_GPP_CLASS; + +typedef struct _devCsInfo { + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; +} MV_DEV_CS_INFO; + +typedef struct _boardLedInfo { + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8 *gppPinNum; /* Pointer to GPP values */ +} MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo { + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; +} MV_BOARD_GPP_INFO; + +typedef struct _boardTwsiInfo { + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; +} MV_BOARD_TWSI_INFO; + +typedef enum _boardMacSpeed { + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, +} MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo { + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; +} MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo { + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; +} MV_BOARD_MPP_INFO; + +typedef struct { + MV_U8 spiCs; +} MV_BOARD_TDM_INFO; + +typedef struct _boardPexUnitCfg { + MV_PEX_UNIT_CFG pexCfg; + MV_U8 pexLaneStat[4]; /* 1: enabled, 2: disabled */ +} MV_BOARD_PEX_UNIT_CFG; + +typedef struct _boardPexInfo { + MV_PEXIF_INDX pexMapping[MV_PEX_MAX_IF]; + MV_BOARD_PEX_UNIT_CFG pexUnitCfg[MV_PEX_MAX_UNIT]; + MV_U32 boardPexIfNum; +} MV_BOARD_PEX_INFO; + +typedef enum { + BOARD_TDM_SLIC_880 = 0, + BOARD_TDM_SLIC_792, + BOARD_TDM_SLIC_3215, + BOARD_TDM_SLIC_OTHER, + BOARD_TDM_SLIC_COUNT +} MV_BOARD_TDM_SLIC_TYPE; + +typedef struct _boardInfo { + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MODULE_TYPE_INFO *pBoardModTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO *pBoardMppConfigValue; + MV_U8 numBoardSerdesConfigValue; + MV_SERDES_CFG *pBoardSerdesConfigValue; + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskMid; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO *pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO *pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO *pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO *pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8 *pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValMid; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValMid; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValMid; + MV_U32 gppPolarityValHigh; + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + MV_U8 numBoardTdmInfo[BOARD_TDM_SLIC_COUNT]; + MV_BOARD_TDM_INFO *pBoardTdmInt2CsInfo[BOARD_TDM_SLIC_COUNT]; + MV_16 boardTdmInfoIndex; + + /* NAND init params */ + MV_U32 nandFlashReadParams; + MV_U32 nandFlashWriteParams; + MV_U32 nandFlashControl; + MV_BOARD_PEX_INFO boardPexInfo; /* filled in runtime */ + +} MV_BOARD_INFO; + +/* For backward compatability with Legacy mode */ +#define mvBoardSwitchConnectedPortGet(port) (-1) +#define mvBoardIsSwitchConnected(port) (mvBoardSwitchConnectedPortGet(port) != -1) +/*#define mvBoardLinkStatusIrqGet(port) mvBoardSwitchIrqGet()*/ + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); + +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); +MV_VOID mvBoardReset(MV_VOID); +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type); +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId); +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); +MV_U32 mvBoardGppConfigGet(void); +MV_32 mvBoardTdmSpiModeGet(MV_VOID); +MV_U8 mvBoardTdmDevicesCountGet(void); +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId); +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_32 mvBoardNandWidthGet(void); +MV_U32 mvBoardIdGet(MV_VOID); + +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_U8 mvBoardFabFreqGet(MV_VOID); +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqGet(MV_VOID); +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqModeGet(MV_VOID); +MV_STATUS mvBoardCpuFreqModeSet(MV_U8 freqVal); +MV_U8 mvBoardFabFreqModeGet(MV_VOID); +MV_STATUS mvBoardFabFreqModeSet(MV_U8 freqVal); +MV_U8 mvBoardBootDevGet(MV_VOID); +MV_STATUS mvBoardBootDevSet(MV_U8 val); +MV_U8 mvBoardBootDevWidthGet(MV_VOID); +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val); +MV_U8 mvBoardCpu0CoreModeGet(MV_VOID); +MV_STATUS mvBoardCpu0CoreModeSet(MV_U8 val); +MV_U8 mvBoardL2SizeGet(MV_VOID); +MV_STATUS mvBoardL2SizeSet(MV_U8 val); +MV_U8 mvBoardCpuCoresNumGet(MV_VOID); +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val); +MV_STATUS mvBoardConIdSet(MV_U16 conf); +MV_U16 mvBoardConfIdGet(MV_VOID); + + +MV_STATUS mvBoardMppModulesScan(void); +MV_STATUS mvBoardOtherModulesScan(void); +MV_BOOL mvBoardIsPexModuleConnected(void); +MV_BOOL mvBoardIsLvdsModuleConnected(void); +MV_BOOL mvBoardIsLcdDviModuleConnected(void); +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum); +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_SERDES_CFG *mvBoardSerdesCfgGet(void); +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void); + +#endif /* __INCmvBoardEnvLibh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,404 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPexRegs.h" +/**********************/ +/* ARMADA-XP DB BOARD */ +/**********************/ + +#define DB_88F78XX0_BOARD_TWSI_DEF_NUM 0x5 +#define DB_88F78XX0_BOARD_SWITCH_NUM 0x1 +#define DB_88F78XX0_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F78XX0_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F78XX0_BOARD_MPP_CONFIG_NUM 0x5 +#define DB_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define DB_88F78XX0_BOARD_SERDES_CONFIG_NUM 0x2 + +#if defined(MV_NAND) && defined(MV_SPI) +#define DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x2 +#else +#define DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif + +#define DB_88F78XX0_BOARD_DEBUG_LED_NUM 0x3 + +#define DB_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +MV_U8 mvDbDisableModuleDetection = 0; + +MV_U8 db88f6781InfoBoardDebugLedIf[] = + {26, 27, 48}; + +MV_BOARD_TWSI_INFO db88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO db88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0}, + {BOARD_MAC_SPEED_AUTO, 0x1}, + {BOARD_MAC_SPEED_AUTO, 0x19}, + {BOARD_MAC_SPEED_AUTO, 0x1B} +}; + +MV_BOARD_MODULE_TYPE_INFO db88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO db88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) /* TODO - which CS if any? */ +/* {NFLASH_CS, N_A, BOARD_DEV_NAND_FLASH, 8} */ /* NAND DEV */ +#endif +#if defined(MV_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f78XX0InfoBoardMppConfigValue[] = { + { { + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_TDM_32CH */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + (DB_88F78XX0_MPP24_31 & 0x00000000) | 0x33333333, + (DB_88F78XX0_MPP32_39 & 0xFFFF0000) | 0x00003333, + (DB_88F78XX0_MPP40_47 & 0xFFFFF0FF) | 0x00000300, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_LCD_DVI */ + (DB_88F78XX0_MPP0_7 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP8_15 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP16_23 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP24_31 & 0xFFFF0000) | 0x00004444, + DB_88F78XX0_MPP32_39, + (DB_88F78XX0_MPP40_47 & 0xFFFFFF00) | 0x00000044, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_MII_GMII */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_OTHER */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, +}; + +MV_SERDES_CFG db88f78XX0InfoBoardSerdesConfigValue[] = { +/* {0x32221111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 0x00000030}, */ /* Default */ + {0x32221111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 0x00000030}, /* Default */ +/* {0x11111111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, 0x00000030} */ /* PEX module */ + {0x31211111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, 0x00000030} /* PEX module */ +}; + +MV_BOARD_TDM_INFO db88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO db88f78XX0Info = { + .boardName = "DB-78460-BP", + .numBoardMppTypeValue = DB_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM, + .pBoardModTypeValue = db88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = DB_88F78XX0_BOARD_MPP_CONFIG_NUM, + .pBoardMppConfigValue = db88f78XX0InfoBoardMppConfigValue, + .numBoardSerdesConfigValue = DB_88F78XX0_BOARD_SERDES_CONFIG_NUM, + .pBoardSerdesConfigValue = db88f78XX0InfoBoardSerdesConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM, + .pDevCsInfo = db88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = DB_88F78XX0_BOARD_TWSI_DEF_NUM, + .pBoardTwsiDev = db88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = DB_88F78XX0_BOARD_MAC_INFO_NUM, + .pBoardMacInfo = db88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = DB_88F78XX0_BOARD_GPP_INFO_NUM, + .pBoardGppInfo = db88f78XX0InfoBoardGppInfo, + .activeLedsNumber = DB_88F78XX0_BOARD_DEBUG_LED_NUM, + .pLedGppPin = db88f6781InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = DB_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = DB_88F78XX0_GPP_POL_HIGH, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = { 2, 6, 1 }, + .pBoardTdmInt2CsInfo = { db88f78XX0Tdm880, + db88f78XX0Tdm792, + db88f78XX0Tdm3215 + }, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_88F78XX0_BOARD_NAND_CONTROL +}; + +/************************/ +/* ARMADA-XP FPGA BOARD */ +/************************/ + +#define FPGA_88F78XX0_BOARD_TWSI_DEF_NUM 0x5 +#define FPGA_88F78XX0_BOARD_SWITCH_NUM 0x1 +#define FPGA_88F78XX0_BOARD_MAC_INFO_NUM 0x2 +#define FPGA_88F78XX0_BOARD_GPP_INFO_NUM 0x3 +#define FPGA_88F78XX0_BOARD_MPP_CONFIG_NUM 0x1 +#define FPGA_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define FPGA_88F78XX0_BOARD_SERDES_CONFIG_NUM 0x2 + +#if defined(MV_NAND) && defined(MV_SPI) +#define FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x2 +#else +#define FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif + +#define FPGA_88F78XX0_BOARD_DEBUG_LED_NUM 0x0 + +#define FPGA_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define FPGA_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +MV_BOARD_TWSI_INFO fpga88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO fpga88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1}, + {BOARD_MAC_SPEED_AUTO, 0x2}, + {BOARD_MAC_SPEED_AUTO, 0x3}, + {BOARD_MAC_SPEED_AUTO, 0x4} +}; + +MV_BOARD_MODULE_TYPE_INFO fpga88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO fpga88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO fpga88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) /* TODO - which CS if any? */ +/* {NFLASH_CS, N_A, BOARD_DEV_NAND_FLASH, 8} */ /* NAND DEV */ +#endif +#if defined(MV_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO fpga88f78XX0InfoBoardMppConfigValue[] = { + { { + FPGA_88F78XX0_MPP0_7, + FPGA_88F78XX0_MPP8_15, + FPGA_88F78XX0_MPP16_23, + FPGA_88F78XX0_MPP24_31, + FPGA_88F78XX0_MPP32_39, + FPGA_88F78XX0_MPP40_47, + FPGA_88F78XX0_MPP48_55, + FPGA_88F78XX0_MPP56_63, + FPGA_88F78XX0_MPP64_67, + } } +}; + +MV_SERDES_CFG fpga88f78XX0InfoBoardSerdesConfigValue[] = { + {0x00000000, 0x00000000, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, 0x00000000} /* No PEX in FPGA */ +}; + +MV_BOARD_TDM_INFO fpga88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO fpga88f78XX0Info = { + .boardName = "FPGA-88F78XX0", + .numBoardMppTypeValue = FPGA_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM, + .pBoardModTypeValue = fpga88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = FPGA_88F78XX0_BOARD_MPP_CONFIG_NUM, + .pBoardMppConfigValue = fpga88f78XX0InfoBoardMppConfigValue, + .numBoardSerdesConfigValue = FPGA_88F78XX0_BOARD_SERDES_CONFIG_NUM, + .pBoardSerdesConfigValue = fpga88f78XX0InfoBoardSerdesConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM, + .pDevCsInfo = fpga88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = FPGA_88F78XX0_BOARD_TWSI_DEF_NUM, + .pBoardTwsiDev = fpga88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = FPGA_88F78XX0_BOARD_MAC_INFO_NUM, + .pBoardMacInfo = fpga88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = FPGA_88F78XX0_BOARD_GPP_INFO_NUM, + .pBoardGppInfo = fpga88f78XX0InfoBoardGppInfo, + .activeLedsNumber = FPGA_88F78XX0_BOARD_DEBUG_LED_NUM, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = FPGA_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = FPGA_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = FPGA_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = FPGA_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = FPGA_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = FPGA_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = FPGA_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = FPGA_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = FPGA_88F78XX0_GPP_POL_HIGH, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = { 2, 6, 1 }, + .pBoardTdmInt2CsInfo = { fpga88f78XX0Tdm880, + fpga88f78XX0Tdm792, + fpga88f78XX0Tdm3215 + }, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = FPGA_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = FPGA_88F78XX0_BOARD_NAND_CONTROL +}; + +MV_BOARD_INFO *boardInfoTbl[] = { + &db88f78XX0Info, + &fpga88f78XX0Info +}; diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +/* I2C bus addresses TODO - take from board design */ +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x57 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + + +/* Board specific configuration */ +/* ============================ */ + +/* boards ID numbers */ +#define BOARD_ID_BASE 0 + +/* New board ID numbers */ +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define FPGA_88F78XX0_ID (DB_88F78XX0_BP_ID + 1) +#define MV_MAX_BOARD_ID (FPGA_88F78XX0_ID + 1) + +/******************/ +/* DB-88F78XX0-BP */ +/******************/ +#define DB_88F78XX0_MPP0_7 0x11111111 +#define DB_88F78XX0_MPP8_15 0x22221111 +#define DB_88F78XX0_MPP16_23 0x22222222 +/* TODO Kostap - change MPP29 (CPU0 Vdd) back to default value 5 + when PM configuration changed to have it as active "high" + Otherwise setting it to default value will shut down CPU0 */ +/*#define DB_88F78XX0_MPP24_31 0x11540000 */ +#define DB_88F78XX0_MPP24_31 0x11040000 +#define DB_88F78XX0_MPP32_39 0x11111111 +#define DB_88F78XX0_MPP40_47 0x34221130 /* TODO set to 0x34221133 to enable PM for CPU1 */ +#define DB_88F78XX0_MPP48_55 0x11111110 +#define DB_88F78XX0_MPP56_63 0x11111101 /* TODO set to 0x11111111 to enable PM for CPU2/3 */ +#define DB_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define DB_88F78XX0_GPP_OUT_ENA_LOW ~(BIT26 | BIT27) +#define DB_88F78XX0_GPP_OUT_ENA_MID ~(BIT16) +#define DB_88F78XX0_GPP_OUT_ENA_HIGH ~(0x0) + +#define DB_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define DB_88F78XX0_GPP_OUT_VAL_MID 0x0 +#define DB_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F78XX0_GPP_POL_LOW 0x0 +#define DB_88F78XX0_GPP_POL_MID 0x0 +#define DB_88F78XX0_GPP_POL_HIGH 0x0 + +/********************/ +/* FPGA-88F78XX0-BP */ +/********************/ +#define FPGA_88F78XX0_MPP0_7 0x11111111 +#define FPGA_88F78XX0_MPP8_15 0x22221111 +#define FPGA_88F78XX0_MPP16_23 0x22222222 +#define FPGA_88F78XX0_MPP24_31 0x11500000 +#define FPGA_88F78XX0_MPP32_39 0x11111111 +#define FPGA_88F78XX0_MPP40_47 0x44221133 +#define FPGA_88F78XX0_MPP48_55 0x11111111 +#define FPGA_88F78XX0_MPP56_63 0x11111111 +#define FPGA_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define FPGA_88F78XX0_GPP_OUT_ENA_LOW (BIT26 | BIT27) +#define FPGA_88F78XX0_GPP_OUT_ENA_MID (BIT16) +#define FPGA_88F78XX0_GPP_OUT_ENA_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_MID 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_POL_LOW 0x0 +#define FPGA_88F78XX0_GPP_POL_MID 0x0 +#define FPGA_88F78XX0_GPP_POL_HIGH 0x0 + +#endif /* __INCmvBoardEnvSpech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,320 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in MHertz. +* +*******************************************************************************/ +MV_U32 mvCpuPclkGet(MV_VOID) +{ +#if defined(PCLCK_AUTO_DETECT) + MV_U32 idx; + MV_U32 cpuClk[] = MV_CPU_CLK_TBL; + + idx = MSAR_CPU_CLK_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)), MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + return cpuClk[idx] * 1000000; +#else + return MV_DEFAULT_PCLK; +#endif +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ +#ifdef L2CLK_AUTO_DETECT + MV_U32 idx; + MV_U32 freqMhz, l2FreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { + freqMhz = mvCpuPclkGet() / 1000000; /* CPU freq */ + freqMhz *= clockRatioTbl[idx].vco2cpu; /* VCO freq */ + l2FreqMhz = freqMhz / clockRatioTbl[idx].vco2l2c; + /* round up to integer MHz */ + if (((freqMhz % clockRatioTbl[idx].vco2l2c) * 10 / clockRatioTbl[idx].vco2l2c) >= 5) + l2FreqMhz++; + + return l2FreqMhz * 1000000; + } else + return (MV_U32)-1; +#else + return MV_BOARD_DEFAULT_L2CLK; +#endif +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch (cpuModel) { + case CPU_PART_MRVLPJ4B_V6UP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v6 UP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V7UP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v7 UP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V6MP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v6 MP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V7MP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v7 MP", mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff, "??? (0x%04x) (Rev %d)", cpuModel, mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_ECC_MASK) == CL2ACR_ECC_EN) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2ParityMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PARITY_MASK) == CL2ACR_PARITY_EN) + mvOsSPrintf(buf, "L2 Parity Enabled"); + else + mvOsSPrintf(buf, "L2 Parity Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CTRL_REG); + if (regVal & CL2CR_L2_EN_MASK) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PFU_MASK) == CL2ACR_PFU_DIS) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_FORCE_WA_MASK) == CL2ACR_FORCE_NO_WA) + mvOsSPrintf(buf, "L2 Write Allocate Disabled"); + else + mvOsSPrintf(buf, "L2 Write Allocate Enabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register0 */ + mvOsPrintf("Extra Features Reg[0] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 1, %0, c15, c1, 1" : "=r" (regVal)); /* Read Marvell extra features register1 */ + mvOsPrintf("Extra Features Reg[1] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read Main ID register */ + mvOsPrintf("Main ID Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_CTRL_REG); + mvOsPrintf("L2 Control Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + mvOsPrintf("L2 Auxilary Control Reg = 0x%x\n", regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + MV_8 L2_Parity_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2ParityMode(L2_Parity_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Parity_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + +/******************************************************************************* +* whoAmI - Get the CPU ID +* +* DESCRIPTION: +* This function returns CPU ID in multiprocessor system +* +* INPUT: +* None. +* +* OUTPUT: +* none. +* +* RETURN: +* CPU ID. +*******************************************************************************/ +unsigned int whoAmI(void) +{ + MV_U32 value; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5 @ read CPUID reg\n" : "=r"(value) : : "memory"); + return (value & 0x7); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,130 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#ifndef MV_ASMLANGUAGE +#include "mvOs.h" +#endif +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#define MASTER_CPU 0 +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#if 0 +/* TODO: alior, need to be removed after moving to MRVL ID */ +#define CPU_PART_ARM1176 0xB76 +#define CPU_PART_MRVLPJ4MP 0xB02 +#define CPU_PART_MRVL_A8 0xC08 +#endif +#define CPU_PART_MRVL_A9 0xC09 +#define CPU_PART_MRVL571 0x571 +#define CPU_PART_MRVL521 0x521 + + +#define CPU_PART_MRVLPJ4B_V6UP 0xb76 +#define CPU_PART_MRVLPJ4B_V7UP 0xc08 +#define CPU_PART_MRVLPJ4B_V6MP 0xb02 +/* TODO: alior, need to update the v7MP id */ +#define CPU_PART_MRVLPJ4B_V7MP 0xaaa + +#if 0 +#define CPU_PART_ARM_V6UP 0xb76 +#define CPU_PART_ARM_V7UP 0xc08 +#define CPU_PART_ARM_V6MP 0xb02 + +#define CPU_PART_MRVLPJ4B_V6UP 0x581 +#define CPU_PART_MRVLPJ4B_V7UP 0xc00 +#define CPU_PART_MRVLPJ4B_V6MP 0x584 +/* TODO: alior, need to update the v7MP id */ +#define CPU_PART_MRVLPJ4B_V7MP 0xaaa +#endif + +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClkRatio { + MV_U32 vco2cpu; /* VCO:PCLK0(CPU) clock ratio */ + MV_U32 vco2l2c; /* VCO:NB(L2 cache) clock ratio */ + MV_U32 vco2hcl; /* VCO:HCLK(DDR controller) clock ratio */ + MV_U32 vco2ddr; /* VCO:DDR(DDR memory) clock ratio */ + +} MV_CPU_ARM_CLK_RATIO; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCpuh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,271 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "sys/mvCpuIf.h" + +#undef MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET sampleAtResetTargetArray[]; + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlTargetByWinInfoGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == unitWinInfo->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlAddrWinMapBuild +* +* DESCRIPTION: +* Build the windows address decoding table, to be used for initializing +* the unit's address decoding windows. +* +* INPUT: +* pAddrWinMap: An array to hold the address decoding windows parameters. +* len: Number of entries in pAddrWinMap. +* +* OUTPUT: +* pAddrWinMap: Address window information. +* +* RETURN: +* MV_BAD_PARAM: input array is smaller than needed to store all window +* addresses. +* MV_ERROR: Otherwise. +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + /* Check size of CPU address win table */ + if (len <= MAX_TARGETS) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - Table size too small.\n"); + return MV_BAD_PARAM; + } + + /* Fill in the pAddrWinMap fields */ + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) { + if (status == MV_NO_SUCH) { + pAddrWinMap[i].enable = MV_FALSE; + continue; + } else { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCpuIfTargetWinGet() failed.\n"); + return MV_ERROR; + } + } + + pAddrWinMap[i].addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinMap[i].addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinMap[i].addrWin.size = cpuAddrDecWin.addrWin.size; + pAddrWinMap[i].enable = cpuAddrDecWin.enable; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinMap[i].attrib = targetAttrib.attrib; + pAddrWinMap[i].targetId = targetAttrib.targetId; + } + pAddrWinMap[i].addrWin.baseLow = TBL_TERM; + pAddrWinMap[i].addrWin.baseHigh = TBL_TERM; + pAddrWinMap[i].addrWin.size = TBL_TERM; + pAddrWinMap[i].enable = TBL_TERM; + pAddrWinMap[i].attrib = TBL_TERM; + pAddrWinMap[i].targetId = TBL_TERM; + + return MV_OK; +} + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) + continue; + + if ((physAddr >= cpuAddrDecWin.addrWin.baseLow) && + (physAddr < cpuAddrDecWin.addrWin.baseLow + cpuAddrDecWin.addrWin.size)) { + /* Found */ + pAddrWinInfo->addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinInfo->addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinInfo->addrWin.size = cpuAddrDecWin.addrWin.size; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinInfo->attrib = targetAttrib.attrib; + pAddrWinInfo->targetId = targetAttrib.targetId; + return MV_OK; + } + } + /* not found */ + return MV_NOT_FOUND; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,183 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvTargetAttrib { + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ +} MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin { + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +} MV_DEC_WIN; + +typedef struct _mvDecWinParams { + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +} MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo); + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, MV_DEC_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len); + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr); + +#endif /* __INCmvCtrlEnvAddrDech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +#endif /* __INCmvCtrlEnvAsmh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,2218 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "gpp/mvGpp.h" +#include "mvSysEthConfig.h" + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) +#include "eth/mvEth.h" +#else +#include "neta/gbe/mvNeta.h" +#endif /* MV_ETH_LEGACY or MV_ETH_NETA */ +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "sata/CoreDriver/mvSata.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#if defined(MV_INCLUDE_TDM) +#include "mvSysTdmConfig.h" +#endif + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif +MV_U32 dummyFlavour = 0; +MV_BIOS_MODE bios_modes[BIOS_MODES_NUM] = { +/* DB Conf Conf ID Plat Code L2 size CPU Freq CpuFreqMode Fabric Freq FabricFreqMode CPU1/2/3 Enable CPU Mode v7UP/v6MP */ +/* 0x4d/[1:0] 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] 0x4f/[2:1] 0x4f/[4:3] */ + {"78130", 0x10, 0x7813, 0x1, 0x3, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"6710", 0x11, 0x6710, 0x0, 0x2, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"78160", 0x12, 0x7816, 0x1, 0x3, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"78230", 0x13, 0x7823, 0x1, 0x3, 0x0, 0x5, 0x0, 0x2, 0x2}, + {"78260", 0x14, 0x7826, 0x1, 0x3, 0x0, 0x5, 0x0, 0x2, 0x2}, + {"78460", 0x15, 0x7846, 0x3, 0x3, 0x0, 0x5, 0x0, 0x3, 0x2}, + {"78480", 0x16, 0x7846, 0x3, 0x5, 0x0, 0x5, 0x0, 0x3, 0x2} +}; + +#if 0 +table below before moving all flavour to 1333/667 mode only +MV_BIOS_MODE bios_modes[BIOS_MODES_NUM] = { +/* DB Conf Code L2 size CPU Freq Fabric Freq CPU1/2/3 Enable CPU Mode v6UP/v6MP + 0x4d/[1:0] 0x4d/[4:2] 0x4e/[4:1] 0x4f/[2:1] 4f/[4:3]*/ + {"78130", 0x7813, 0x1, 0x1, 0x1, 0x0, 0x0}, + {"KW40", 0x6710, 0x1, 0x1, 0x1, 0x0, 0x0}, + {"78160", 0x7816, 0x1, 0x3, 0x5, 0x0, 0x0}, + {"78230", 0x7823, 0x1, 0x1, 0x1, 0x2, 0x2}, + {"78260", 0x7826, 0x1, 0x3, 0x5, 0x2, 0x2}, + {"78460", 0x7846, 0x3, 0x3, 0x5, 0x3, 0x2}, + {"78480", 0x7846, 0x3, 0x5, 0x5, 0x3, 0x2} +}; +#endif +MV_U32 mvCtrlGetCpuNum(MV_VOID) +{ + return ((MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET); +} +MV_BOOL mvCtrlIsValidSatR(MV_VOID) +{ + int i=0; + MV_U32 tmpSocCores; + MV_U8 cpuEna; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 fabricFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreqMode; + + MV_U32 confId = mvBoardConfIdGet(); + + l2size = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_L2_SIZE_MASK) >> SAR0_L2_SIZE_OFFSET; + cpuFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_CPU_FREQ_MASK) >> SAR0_CPU_FREQ_OFFSET; + fabricFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET; + tmpSocCores = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET; + cpuFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_MODE_MASK) >> SAR1_CPU_MODE_OFFSET; + fabricFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_FABRIC_MODE_MASK) >> SAR1_FABRIC_MODE_OFFSET; + /* Bug fix in HW, bit0 & bit1 are swapped */ + cpuEna |= (tmpSocCores & 0x2) >> 1; + cpuEna |= (tmpSocCores & 0x1) << 1; + + /* Find out what is programmed in SAR and change device ID accordingly */ + for (i = 0; i < BIOS_MODES_NUM; i++) { + if (bios_modes[i].confId == confId) { + DB(mvOsPrintf("confId = 0x%x\n", confId)); + DB(mvOsPrintf("cpuFreq [0x%x] = 0x%x\n", cpuFreq, bios_modes[i].cpuFreq)); + DB(mvOsPrintf("fabricFreq [0x%x] = 0x%x\n", fabricFreq, bios_modes[i].fabricFreq)); + DB(mvOsPrintf("cpuEna [0x%x] = 0x%x\n", cpuEna, bios_modes[i].cpuEna)); + DB(mvOsPrintf("cpuFreqMode [0x%x] = 0x%x\n", cpuFreqMode, bios_modes[i].cpuFreqMode)); + DB(mvOsPrintf("fabricFreqMode [0x%x] = 0x%x\n", fabricFreqMode, bios_modes[i].fabricFreqMode)); + DB(mvOsPrintf("l2size [0x%x] = 0x%x\n", l2size, bios_modes[i].l2size)); + if ((cpuFreq == bios_modes[i].cpuFreq) && + (fabricFreq == bios_modes[i].fabricFreq) && + (cpuEna == bios_modes[i].cpuEna) && + (cpuFreqMode == bios_modes[i].cpuFreqMode) && + (fabricFreqMode == bios_modes[i].fabricFreqMode) && + (l2size == bios_modes[i].l2size)) { + return MV_TRUE; + } else { + return MV_FALSE; + } + } + } +} +MV_STATUS mvCtrlUpdatePexId(MV_VOID) +{ + //MV_U32 socFreq, tmpSocCores; + //MV_U32 socCores = 0; + MV_U32 pmCtrl; + MV_U32 devVendId; + int i; + MV_U16 confId; + + /* if PEX0 clock is disabled - enable it for reading the device ID */ + pmCtrl = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((pmCtrl & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + MV_REG_WRITE(POWER_MNG_CTRL_REG, + (pmCtrl & ~PMC_PEXSTOPCLOCK_MASK(0))| PMC_PEXSTOPCLOCK_EN(0)); + } + + devVendId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + //socFreq = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_DDR3_FREQ_MASK; + //tmpSocCores = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET; + confId = mvBoardConfIdGet(); + + /* Bug fix in HW, bit0 & bit1 are swapped */ +/* socCores |= (tmpSocCores & 0x2) >> 1; + socCores |= (tmpSocCores & 0x1) << 1; +*/ + /* Find out what is programmed in SAR and change device ID accordingly */ +/* if ((socFreq == SAR_CPU_FAB_GET(bios_modes[i].cpuFreq, bios_modes[i].fabricFreq)) && + (socCores == bios_modes[i].cpuEna)) { +*/ + for (i = 0; i < BIOS_MODES_NUM; i++) { + if (bios_modes[i].confId == confId) { + devVendId &= 0x0000FFFF; + devVendId |= bios_modes[i].code << 16; + MV_REG_WRITE(MV_PEX_IF_REGS_OFFSET(0), devVendId); + } + } + + /* Reset the original value of PEX0 clock */ + if ((pmCtrl & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) + MV_REG_WRITE(POWER_MNG_CTRL_REG, pmCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 mppVal; + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + MV_U32 pexUnit = 0; + + /* Disable MBus Error Propagation */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); + + /* Use Background sync barrier (polling) for I/O cache coherency */ + MV_REG_BIT_SET(SOC_CIB_CTRL_CFG_REG, BIT8); + + /* MPP Init - scan which modeule is connected */ + /* mvBoardMppModulesScan(); */ + + /* Read MPP config values from board level and write MPP options to HW */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) { + mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */ + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Scan for other modules (SERDES/LVDS/...) */ + mvBoardOtherModulesScan(); + + /* Update interfaces configuration based on above scan */ + if (MV_OK != mvCtrlSerdesPhyConfig()) + mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n"); + + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + /* PEX enabling */ + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg != PEX_BUS_DISABLED) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); + else + MV_REG_BIT_RESET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); + } + + mvOsDelay(100); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + if (mppGroup >= MV_MPP_MAX_GROUP) + mppGroup = 0; + + ret = MPP_CONTROL_REG(mppGroup); + + return ret; +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; +/* TODO: alior fix PexMaxIfGet for KW40... */ + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_IF; + + default: + return 0; + } +} +/******************************************************************************* +* mvCtrlPexMaxUnitGet - Get Marvell controller number of PEX units. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 2; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 3; + + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_UNIT; + + default: + return 0; + } +} + +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_FPGA_DEV_ID: + return 1; + + default: + return 0; + } +} +#endif + +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); +#if 0 + /* FIXME - assuming MV_78460_DEV_ID */ + devId = MV_78460_DEV_ID; +#endif + switch (devId) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return MV_78130_ETH_MAX_PORT; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_78460_ETH_MAX_PORT; + + default: + return 0; + } +} + +/******************************************************************************* +* mvCtrlEthMaxCPUsGet - Get Marvell controller number of CPUs. +* +* DESCRIPTION: +* This function returns Marvell controller number of CPUs. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of CPUs. +* +*******************************************************************************/ +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + /* FIXME - assuming MV_78460_DEV_ID */ + devId = MV_78460_DEV_ID; + + switch (devId) { + case MV_78130_DEV_ID: + case MV_78230_DEV_ID: + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + return 4; + + default: + return 0; + } +} + + +#if defined(MV_INCLUDE_SATA) +/******************************************************************************* +* mvCtrlSataMaxPortGet - Get Marvell controller number of Sata ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of Sata ports. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of Sata ports. +* +*******************************************************************************/ +MV_U32 mvCtrlSataMaxPortGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_SATA_MAX_CHAN; + break; + } + return res; +} +#endif + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_CHAN; + break; + } + return res; +} + +/******************************************************************************* +* mvCtrlXorMaxUnitGet - Get Marvell controller number of XOR units. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR units. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_UNIT; + break; + } + return res; +} + +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_FPGA_DEV_ID: + res = 0; + break; + + default: + res = ARMADA_XP_MAX_USB_PORTS; + break; + } + + return res; +} +#endif + +#if defined(MV_INCLUDE_LEGACY_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + return ARMADA_XP_NAND; +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + return ARMADA_XP_SDIO; +} +#endif + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + return ARMADA_XP_TDM; +} + +/******************************************************************************* +* mvCtrlTdmMaxGet - Return the maximum number of TDM ports. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of TDM ports in device. +* +*******************************************************************************/ +MV_U32 mvCtrlTdmMaxGet(MV_VOID) +{ + return ARMADA_XP_MAX_TDM_PORTS; +} + +/******************************************************************************* +* mvCtrlTdmTypeGet +* +* DESCRIPTION: +* Return the TDM unit type being compiled in. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The TDM unit type. +* +*******************************************************************************/ +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID) +{ + return TDM_UNIT_32CH; +} + +/******************************************************************************* +* mvCtrlTdmUnitIrqGet +* +* DESCRIPTION: +* Return the TDM unit IRQ number depending on the TDM unit compilation +* options. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +******************************************************************************/ +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID) +{ + return MV_TDM_IRQ_NUM; +} + +#endif /* if defined(MV_INCLUDE_TDM) */ + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 devId; + MV_U16 model = 0; + MV_U32 reg, reg2; + /* if PEX0 clocks are disabled - enabled it to read */ + reg = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + reg2 = ((reg & ~PMC_PEXSTOPCLOCK_MASK(0)) | PMC_PEXSTOPCLOCK_EN(0)); + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2); + } + + devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + + /* Reset the original value of the PEX0 clock */ + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg); + } + + model = (MV_U16) ((devId >> 16) & 0xFFFF); +#if 0 + /* FIXME */ + /* Temperarely override model numebr for Z1 */ + switch (model) { + case MV_78130_DEV_ID: + case MV_78160_DEV_ID: + case MV_78230_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + model = MV_78460_DEV_ID; + break; + + /* Fallback: assume 78460 */ + default: + model = MV_78460_DEV_ID; + } +#endif + return model; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8) MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + if (mvCtrlModelGet() == 0x7800) + mvOsSPrintf(pNameBuff, "%s78XX", SOC_NAME_PREFIX); + else + mvOsSPrintf(pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, mvCtrlModelGet(), mvCtrlRevGet()); + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + switch (mvCtrlModelRevGet()) { + case MV_78130_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78130_Z1_NAME); + break; + + case MV_6710_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6710_Z1_NAME); + break; + + case MV_78230_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78230_Z1_NAME); + break; + case MV_78160_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78160_Z1_NAME); + break; + case MV_78260_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78260_Z1_NAME); + break; + case MV_78460_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78460_Z1_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} + +static const char *cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target) +{ + if (target >= MAX_TARGETS) + return "target unknown"; + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvCtrlPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar, winNum; + + for (pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++) { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) + continue; + mvOsOutput("\n"); + mvOsOutput("PEX%d:\n", pexIf); + mvOsOutput("-----\n"); + + mvOsOutput("\nPex Bars \n\n"); + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + memset(&pexBar, 0, sizeof(MV_PEX_BAR)); + + mvOsOutput("%s ", pexBarNameGet(bar)); + + if (mvPexBarGet(pexIf, bar, &pexBar) == MV_OK) { + if (pexBar.enable) { + mvOsOutput("base %08x, ", pexBar.addrWin.baseLow); + mvSizePrint(pexBar.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + mvOsOutput("\nPex Decode Windows\n\n"); + + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) { + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvPexTargetWinRead(pexIf, winNum, &win) == MV_OK) { + if (win.winInfo.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win.winInfo)), + win.winInfo.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.winInfo.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("default win - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("Expansion ROM - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + } +} + +/******************************************************************************* +* mvUnitAddrDecShow - Print the Unit's address decode map. +* +* DESCRIPTION: +* This is a generic function for printing the different unit's address +* decode map. +* +* INPUT: +* unit - The unit to print the address decode for. +* name - The unit's name. +* winGetFuncPtr - A pointer to the HAL's window get function. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvUnitAddrDecShow(MV_U8 numUnits, MV_UNIT_ID unitId, const char *name, MV_WIN_GET_FUNC_PTR winGetFuncPtr) +{ + MV_UNIT_WIN_INFO win; + MV_U32 unit, i; + + for (unit = 0; unit < numUnits; unit++) { + + if (MV_FALSE == mvCtrlPwrClckGet(unitId, unit)) + continue; + mvOsOutput("\n"); + mvOsOutput("%s %d:\n", name, unit); + mvOsOutput("----\n"); + + for (i = 0; i < 16; i++) { + memset(&win, 0, sizeof(MV_UNIT_WIN_INFO)); + + mvOsOutput("win%d - ", i); + + if (winGetFuncPtr(unit, i, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win)), + win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + } + return; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvCtrlPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUnitAddrDecShow(mvCtrlUsbMaxGet(), USB_UNIT_ID, "USB", mvUsbWinRead); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvEthWinRead); +#else + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvNetaWinRead); +#endif /* MV_ETH_LEGACY */ +#endif /* MV_INCLUDE_GIG_ETH */ + +#if defined(MV_INCLUDE_XOR) + mvUnitAddrDecShow(mvCtrlXorMaxChanGet(), XOR_UNIT_ID, "XOR", mvXorTargetWinRead); +#endif +#if defined(MV_INCLUDE_SATA) + mvUnitAddrDecShow(mvCtrlSataMaxPortGet(), SATA_UNIT_ID, "Sata", mvSataWinRead); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while (alignment & 1) { /* Check that alignmet LSB is set */ + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", (MV_U32) alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + retVal = size; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while (size & 1) /* Check that LSB is set */ + size = (size >> 1); /* If LSB is set, move one bit to the right */ + + if (size) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", size)); + return -1; + } + return retVal; +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while (temp & 1) /* Check that LSB is set */ + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + + if (temp) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", regSize)); + return -1; + } + + /* Check that aligment is a power of two */ + temp = alignment - 1; /* Now the alignmet is a sequance of '1' (0xffff) */ + + while (temp & 1) /* Check that alignmet LSB is set */ + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while (alignment & 1) { /* Check that alignmet LSB is set */ + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + return size; + + while (size) { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + return alignment; + else + return retSize; +} + +/******************************************************************************* +* mvCtrlIsBootFromNOR +* +* DESCRIPTION: +* Check if device is configured to boot from NOR flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_NOR) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromSPI +* +* DESCRIPTION: +* Check if device is configured to boot from SPI flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_SPI) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromNAND +* +* DESCRIPTION: +* Check if device is confiogured to boot from NAND flash according to the SAR +* registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from NAND. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if ((satr == MSAR_BOOT_DOVE_NAND) || (satr == MSAR_BOOT_LEGACY_NAND)) + return MV_TRUE; + else + return MV_FALSE; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + + break; +#endif + case TDM_32CH_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + + break; + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK(index)) == PMC_PEXSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_CESASTOPCLOCK_MASK) == PMC_CESASTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK(index)) == PMC_USBSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_32CH_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} + +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_MASK); + + break; +#endif + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg; + MV_BOOL state = MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX)); + if ((reg & PMC_PEXSTOPMEM_MASK(index)) == PMC_PEXSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE)); + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA)); + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA)); + if ((reg & PMC_CESASTOPMEM_MASK) == PMC_CESASTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB)); + if ((reg & PMC_USBSTOPMEM_MASK(index)) == PMC_USBSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR)); + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM)); + if ((reg & PMC_BMSTOPMEM_MASK) == PMC_BMSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC)); + if ((reg & PMC_PNCSTOPMEM_MASK) == PMC_PNCSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + return; +} + +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + return MV_TRUE; +} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvCtrlSerdesMaxLinesGet - Get Marvell controller number of SERDES lines. +* +* DESCRIPTION: +* This function returns Marvell controller number of SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 12; + break; + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return 16; + default: + return 0; + } +} + +MV_U32 mvCtrlDDRBudWidth(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x1400); + + return (reg & 0x8000)?64:32; +} +MV_BOOL mvCtrlDDRThruXbar(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x20184); + + return (reg & 0x1)?MV_FALSE:MV_TRUE; +} + +static const MV_U8 serdesCfg[][8] = SERDES_CFG; + +/******************************************************************************* +* mvCtrlSerdesPhyConfig +* +* DESCRIPTION: +* Configure Serdes MUX and init PHYs connected to SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Status +* +*******************************************************************************/ +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID) +{ + MV_U32 serdesLineCfg; + MV_U8 serdesLineNum; + MV_U32 regAddr[16][10], regVal[16][10]; /* addr/value for each line @ every setup step */ + MV_U8 pexUnit, pexLineNum; + MV_U8 step; + MV_U8 maxSerdesLines = mvCtrlSerdesMaxLinesGet(); + MV_SERDES_CFG *pSerdesInfo = mvBoardSerdesCfgGet(); + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + MV_STATUS status = MV_OK; + MV_U32 tmp; + + /* Check if no SERDESs available - FPGA */ + if (maxSerdesLines == 0) + return MV_OK; + + if (pSerdesInfo == NULL) { + DB(mvOsPrintf("%s: Error reading SERDES configuration!\n", __FUNCTION__)); + return MV_ERROR; + } + + memset(regAddr, 0, sizeof(regAddr)); + memset(regVal, 0, sizeof(regVal)); + memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO)); + + /* Prepare PHY parameters for each step according to MUX selection */ + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + /* for each serdes lane*/ + MV_U32 *pRegVal = regVal[serdesLineNum]; + MV_U32 *pRegAddr = regAddr[serdesLineNum]; + MV_U8 sgmiiPort = 0; + + if (serdesLineNum < 8) + serdesLineCfg = (pSerdesInfo->serdesLine0_7 >> (serdesLineNum << 2)) & 0xF; + else + serdesLineCfg = (pSerdesInfo->serdesLine8_15 >> ((serdesLineNum - 8) << 2)) & 0xF; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_PEX]) { + pexUnit = serdesLineNum >> 2; + pexLineNum = serdesLineNum % 4; + + /* Map the PCI-E interfaces according to their HW mapping + Map PCI-E virtual intrefaces in an array where we have information about + every interface (e.g. HW mapping, x1,x4,x8 ( disabled) .. ) + */ + switch (pexUnit) { + case 0: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex0Mod; + break; + case 1: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex1Mod; + break; + case 2: + if (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X4) + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_MODE_X4; + else + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_DISABLED; + break; + case 3: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex3Mod; + break; + } + if ((pexUnit < 2) && (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1)) { + + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexUnit * 4 + pexLineNum; + boardPexInfo->boardPexIfNum++; + boardPexInfo->pexUnitCfg[pexUnit].pexLaneStat[pexLineNum] = 0x1; + + } else if ((pexUnit < 4) && + (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) && + (pexLineNum == 0)) { + + switch (pexUnit) { + case 0: + case 1: + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexUnit*4 + pexLineNum; + break; + case 2: + case 3: + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = PEX2_0x4 + (pexUnit - 2); + break; + } + + boardPexInfo->boardPexIfNum++; + + } else if ((pexUnit == 3) && + (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X8) && + (pexLineNum == 0)) { + + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = PEX3_0x4; + boardPexInfo->boardPexIfNum++; + } + + /* Needed for PEX_PHY_ACCESS_REG macro */ + if ((serdesLineNum > 7) && (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X8)) + pexUnit = 3; /* lines 8 - 15 are belong to PEX3 in x8 mode */ + + /* regVal bits: + bit[31] - 0:write, 1:read + bit[23:16] - PHY REG offset + bit[29:24] - PEX line + bit[15:0] - value to be set in PHY REG + */ + pRegAddr[0] = PEX_PHY_ACCESS_REG(pexUnit); + pRegAddr[1] = 0; /*PEX_PHY_ACCESS_REG(pexUnit); */ + pRegAddr[2] = PEX_PHY_ACCESS_REG(pexUnit); + pRegAddr[3] = 0; + pRegAddr[4] = 0; + + /* PHY_MODE [7:5] - 3 (PCIe) + REF_FREF_SEL [4:0] - 0 (100MHz) */ + pRegVal[0] = (0x01 << 16) | (pexLineNum << 24) | 0xFC60; + +#if 0 + /* SEL_BITS [11:10] + For 2.5G: 0 (10bit) + For 5G: 1 (20bit) */ + pRegVal[1] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x0400 : 0x0; + pRegVal[1] |= (0x23 << 16) | (pexLineNum << 24); +#endif + /* SEL_BITS [11:10] - NA */ + pRegVal[1] = 0; + + /* REFCLK_SEL [10] - 0 */ + pRegVal[2] = (0x46 << 16) | (pexLineNum << 24); + + /* PIN_PHY_GEN [12:5] - NA */ + pRegVal[3] = 0; + pRegVal[4] = 0; + + + } else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SATA]) { + + MV_U8 sataPort; + + if ((serdesLineNum == 4) || (serdesLineNum == 8)) + sataPort = 0; + else if ((serdesLineNum == 5) || (serdesLineNum == 9)) + sataPort = 1; + else + goto err_cfg; + + pRegAddr[0] = SATA_PWR_PLL_CTRL_REG(sataPort); + pRegAddr[1] = SATA_DIG_LP_ENA_REG(sataPort); + pRegAddr[2] = SATA_REF_CLK_SEL_REG(sataPort); + pRegAddr[3] = SATA_LP_PHY_EXT_CTRL_REG(sataPort); + pRegAddr[4] = SATA_LP_PHY_EXT_STAT_REG(sataPort); + pRegVal[0] = 0xF801; + pRegVal[1] = 0x400; + pRegVal[2] = 0x400; + pRegVal[3] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x227 : 0x7; + pRegVal[4] = 0x7; + + } else { + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII0]) { + sgmiiPort = 0; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII1]) { + sgmiiPort = 1; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII2]) { + sgmiiPort = 2; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII3]) { + sgmiiPort = 3; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII]) { + sgmiiPort = 0; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_UNCONNECTED]) + continue; + + pRegAddr[0] = SGMII_PWR_PLL_CTRL_REG(sgmiiPort); + pRegAddr[1] = SGMII_DIG_LP_ENA_REG(sgmiiPort); + pRegAddr[2] = SGMII_REF_CLK_SEL_REG(sgmiiPort); + pRegAddr[3] = SGMII_SERDES_CFG_REG(sgmiiPort); + pRegAddr[4] = SGMII_SERDES_STAT_REG(sgmiiPort); + pRegVal[0] = 0xF881; + pRegVal[1] = 0; + pRegVal[2] = 0x400; + pRegVal[3] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x1547 : 0xCC7; + pRegVal[4] = 0x7; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII]) { + pRegVal[1] = 0x400; + pRegVal[3] = 0x667; + } + } + + } /* for each serdes lane*/ + + + /* Step 0 - configure SERDES MUXes */ + MV_REG_WRITE(SERDES_LINE_MUX_REG_0_7, pSerdesInfo->serdesLine0_7); + MV_REG_WRITE(SERDES_LINE_MUX_REG_8_15, pSerdesInfo->serdesLine8_15); + DB(mvOsPrintf("\nStep[0].1 Addr[0x%08x] Value[0x%08x]\n", SERDES_LINE_MUX_REG_0_7, pSerdesInfo->serdesLine0_7)); + DB(mvOsPrintf("Step[0].2 Addr[0x%08x] Value[0x%08x]\n\n", SERDES_LINE_MUX_REG_8_15, pSerdesInfo->serdesLine8_15)); + + /* Step 1 [PEX-Only] PEX-Main configuration (X4 or X1): */ + /* First disable all PEXs in SoC Control Reg */ + MV_REG_WRITE(SOC_CTRL_REG, 0x0); + + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + /* SoC Control + 0x18204 [7,8] + 0x0 X4-Link. + 0x1 n*X1-Link’s */ + if (pexUnit < 2) { + tmp = MV_REG_READ(SOC_CTRL_REG); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + tmp |= SCR_PEX_4BY1_MASK(pexUnit); + + DB(mvOsPrintf("Step[1].1 Addr[0x%08x] pexUnit [%d] value [0x%x]\n", SOC_CTRL_REG, pexUnit, tmp)); + MV_REG_WRITE(SOC_CTRL_REG, tmp); + } + } + + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + + if (serdesLineNum < 8) + serdesLineCfg = (pSerdesInfo->serdesLine0_7 >> (serdesLineNum << 2)) & 0xF; + else + serdesLineCfg = (pSerdesInfo->serdesLine8_15 >> ((serdesLineNum - 8) << 2)) & 0xF; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_PEX]) { + /* PCI Express Control + 0xX1A00 [0]: + 0x0 X4-Link. + 0x1 X1-Link */ + tmp = MV_REG_READ(PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum))); + tmp &= ~(0x3F0); + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X1) + tmp |= (0x1 << 4); + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X4) + tmp |= (0x4 << 4); + MV_REG_WRITE(PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum)), tmp); + DB(mvOsPrintf("Step[1].2 Addr[0x%08x] serdesLine [%d] value [0x%x]\n", PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum)), serdesLineNum, tmp)); + /* if pex is X4, no need to pass thru the other 3X1 serdes lines */ + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X4) + serdesLineNum += 3; + } + } + DB(mvOsPrintf("\n")); + + /* Step 2 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you need to config the register SOC_Misc/General Purpose2 (Address= 182F8)*/ + tmp = MV_REG_READ(GEN_PURP_RES_2_REG); + + if (pSerdesInfo->pex0Mod == PEX_BUS_MODE_X4) + tmp |= 0x0000000F; +/* else + tmp &= 0xFFFFFFF0; +*/ + if (pSerdesInfo->pex1Mod == PEX_BUS_MODE_X4) + tmp |= 0x000000F0; +/* else + tmp &= 0xFFFFFF0F; */ + + if (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X4) + tmp |= 0x0000FF00; +/* else + tmp &= 0xFFFF00FF; */ + + DB(mvOsPrintf("Step[2] Addr[0x%08x] Value[0x%08x]\n\n", GEN_PURP_RES_2_REG, tmp)); + + MV_REG_WRITE(GEN_PURP_RES_2_REG, tmp); + + /* STEP 3 [PEX-Only] First phase of PEX-PIPE Configuration:*/ + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + DB(mvOsPrintf("Step[3].1 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA5)); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) + DB(mvOsPrintf("Step[3].2 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC2 << 16) | 0x200)); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + DB(mvOsPrintf("Step[3].3 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC3 << 16) | 0x0F)); + + DB(mvOsPrintf("Step[3].4 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC8 << 16) | 0x05)); + DB(mvOsPrintf("Step[3].5 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xD0 << 16) | 0x100)); + DB(mvOsPrintf("Step[3].6 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xD1 << 16) | 0x3014)); + DB(mvOsPrintf("Step[3].7 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC5 << 16) | 0x11F)); + DB(mvOsPrintf("Step[3].8 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0x80 << 16) | 0x1000)); + DB(mvOsPrintf("Step[3].9 Addr[0x%08x] Value[0x%08x]\n\n", PEX_PHY_ACCESS_REG(pexUnit), (0x81 << 16) | 0x11)); + + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0x25); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC2 << 16) | 0x200); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC3 << 16) | 0x0F); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC8 << 16) | 0x05); + /* MV_REG_WRITE(PEX_PHY_ACCESS_REG(0), (0xC2 << 16) | 0x200); *//* BC was disabled per HW team request */ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xD0 << 16) | 0x100); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xD1 << 16) | 0x3014); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC5 << 16) | 0x11F); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x80 << 16) | 0x1000); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x81 << 16) | 0x11); + } + + /* Steps 4, 5, 6, 7 - use prepared REG addresses and values */ + for (step = 0; step < 4; step++) { + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + if (regAddr[serdesLineNum][step] != 0) { + DB(mvOsPrintf("Step[%d] Lane[%d] Addr[0x%08x] Value[0x%08x]\n", + step + 4, serdesLineNum, regAddr[serdesLineNum][step], regVal[serdesLineNum][step])); + MV_REG_WRITE(regAddr[serdesLineNum][step], regVal[serdesLineNum][step]); + } + } + DB(mvOsPrintf("\n")); + } + + /*Step 8 [PEX-Only] Last phase of PEX-PIPE Configuration */ + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + DB(mvOsPrintf("Step[8].1 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0x2 << 16) | 0x40)); + DB(mvOsPrintf("Step[8].2 Addr[0x%08x] Value[0x%08x]\n\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA4)); + + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x2 << 16) | 0x40); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA4); + } + + /* Wait 5ms before checking results */ + mvOsDelay(15); + + /* Step 9 - check that PLL RX/TX is ready and RX init done */ + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + MV_U32 tmp; + if (regAddr[serdesLineNum][4] != 0) { /* SATA, QSGMII, SGMII */ + tmp = MV_REG_READ(regAddr[serdesLineNum][4]); + if ((tmp & 0x7)!= regVal[serdesLineNum][4]) { /* check bits[2:0] */ + DB(mvOsPrintf("%s: PHY on SERDES lane %d is not ready!\n", + __FUNCTION__, serdesLineNum)); + status = MV_ERROR; + } +#if 1 + } else if (regAddr[serdesLineNum][0] != 0){ /* PEX that is enabled and passed step1 */ + /* First step writes into Power and PLL control register. + It's possible to read it back now for checking the PLL lock status */ + MV_REG_WRITE(regAddr[serdesLineNum][0], (regVal[serdesLineNum][0] | BIT31) & 0xFFFF0000); + tmp = MV_REG_READ(regAddr[serdesLineNum][0]); + if ((tmp & BIT8) == 0) { + DB(mvOsPrintf("%s: PEX PHY PLL on SERDES lane %d is not locked!\n", + __FUNCTION__, serdesLineNum)); + status = MV_ERROR; + } +#endif + } + } + + return status; + +err_cfg: + DB(mvOsPrintf("%s: Wrong CFG (%#x) for SERDES line %d.\n", + __FUNCTION__, serdesLineCfg, serdesLineNum)); + return MV_ERROR; + +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,243 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +/*#include "boardEnv/mvBoardEnvLib.h"*/ + +/* 0 for Auto scan mode, 1 for manual. */ +#define MV_INTERNAL_SWITCH_SMI_SCAN_MODE 0 + +/* typedefs */ +typedef MV_STATUS (*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*); + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy { + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +} MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType { + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +} MV_SWAP_TYPE; + +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7, + SERDES_UNIT_LAST +} MV_SERDES_UNIT_INDX; + +typedef enum { + PEX_BUS_DISABLED = 0, + PEX_BUS_MODE_X1 = 1, + PEX_BUS_MODE_X4 = 2, + PEX_BUS_MODE_X8 = 3 +} MV_PEX_UNIT_CFG; + +/* Configuration per SERDES line. + Each nibble is MV_SERDES_LINE_TYPE */ +typedef struct _boardSerdesConf { + MV_U32 serdesLine0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */ + MV_U32 serdesLine8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */ + MV_PEX_UNIT_CFG pex0Mod; + MV_PEX_UNIT_CFG pex1Mod; + MV_PEX_UNIT_CFG pex3Mod; + MV_U32 busSpeed; /* Bus speed - one bit per SERDES line: + Low speed (0) High speed (1) + PEX 2.5 G (10 bit) 5 G (20 bit) + SATA 1.5 G 3 G + SGMII 1.25 Gbps 3.125 Gbps */ +} MV_SERDES_CFG; + + + +/* BIOS Modes related defines */ +#define SAR0_CPU_FREQ_MASK 0x00E00000 +#define SAR0_CPU_FREQ_OFFSET 21 +#define SAR0_FABRIC_FREQ_MASK 0x0F000000 +#define SAR0_FABRIC_FREQ_OFFSET 24 +#define SAR0_L2_SIZE_MASK 0x00180000 +#define SAR0_L2_SIZE_OFFSET 19 +#define SAR1_CPU_CORE_MASK 0x00000018 +#define SAR1_CPU_CORE_OFFSET 3 +#define SAR1_CPU_MODE_MASK 0x00100000 +#define SAR1_CPU_MODE_OFFSET 20 +#define SAR1_FABRIC_MODE_MASK 0x00080000 +#define SAR1_FABRIC_MODE_OFFSET 19 + + +#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) +#define BIOS_MODES_NUM 7 + +typedef struct { + char *name; + MV_U16 confId; + MV_U16 code; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreq; + MV_U8 fabricFreqMode; + MV_U8 cpuEna; + MV_U8 cpuMode; +}MV_BIOS_MODE; + +extern MV_BIOS_MODE bios_modes[]; + +/* mcspLib.h API list */ +MV_U32 mvCtrlGetCpuNum(MV_VOID); +MV_STATUS mvCtrlUpdatePexId(MV_VOID); + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif + +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +#else +#define mvCtrlPciIfMaxIfGet() (mvCtrlPexMaxIfGet()) +#endif + +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID); +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_LEGACY_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmSupport(MV_VOID); +MV_U32 mvCtrlTdmMaxGet(MV_VOID); +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID); +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID); +#endif + +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID); +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); + +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID); +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID); +MV_U32 mvCtrlDDRBudWidth(MV_VOID); +MV_BOOL mvCtrlDDRThruXbar(MV_VOID); + +#endif /* __INCmvCtrlEnvLibh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,523 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + : : "memory"); +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ +#define MV_TDM_IRQ_NUM 56 + +/* Power Management Memory Power Down Registers 1 - 6 */ +#define POWER_MNG_MEM_CTRL_REG(num) ((num) < 6 ? 0x1821 + (num) * 4 : 0x18228) +#define PMC_MCR_NUM_COMM 6 +#define PMC_MCR_NUM_PEX 2 +#define PMC_MCR_NUM_USB 4 +#define PMC_MCR_NUM_DUNIT 3 +#define PMC_MCR_NUM_DEVB 4 +#define PMC_MCR_NUM_NF 4 +#define PMC_MCR_NUM_XOR 4 +#define PMC_MCR_NUM_SATA 5 +#define PMC_MCR_NUM_CESA 4 +#define PMC_MCR_NUM_GE 5 +#define PMC_MCR_NUM_PNC 5 +#define PMC_MCR_NUM_BM 5 +#define PMC_MCR_NUM_PDMA 1 +#define PMC_MCR_NUM_NCS 3 +#define PMC_MCR_NUM_CFU 3 +#define PMC_MCR_NUM_L2 3 +#define PMC_MCR_NUM_CIB 3 +#define PMC_MCR_NUM_CPU 3 +#define PMC_MCR_NUM_IDMA 4 +#define PMC_MCR_NUM_LCD 4 +#define PMC_MCR_NUM_PMU 6 + +#define PMC_COMMSTOPMEM_OFFS 4 +#define PMC_COMMSTOPMEM_MASK (7 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_EN (0 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_STOP (1 << PMC_COMMSTOPMEM_OFFS) + +#define PMC_PEXSTOPMEM_OFFS(port) ((port) < 10 ? ((port) * 3) : 0) +#define PMC_PEXSTOPMEM_MASK(port) (7 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_EN(port) (0 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_STOP(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) + +#define PMC_USBSTOPMEM_OFFS(port) ((port) < 3 ? (3 + (port) * 3) : 0) +#define PMC_USBSTOPMEM_MASK(port) (7 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_EN(port) (0 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_STOP(port) (1 << PMC_USBSTOPMEM_OFFS(port)) + +#define PMC_DUNITSTOPMEM_OFFS 12 +#define PMC_DUNITSTOPMEM_MASK (7 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +#define PMC_NFSTOPMEM_OFFS 27 +#define PMC_NFSTOPMEM_MASK (7 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_EN (0 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_STOP (1 << PMC_NFSTOPMEM_OFFS) + +#define PMC_DEVBSTOPMEM_OFFS 21 +#define PMC_DEVBSTOPMEM_MASK (7 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_EN (0 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_STOP (1 << PMC_DEVBSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) ((port) == 0 ? 15 : 24) +#define PMC_XORSTOPMEM_MASK(port) (7 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_SATASTOPMEM_OFFS(port) ((port) == 0 ? 18 : 24) +#define PMC_SATASTOPMEM_MASK(port) (0x3F << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (9 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_CESASTOPMEM_OFFS 18 +#define PMC_CESASTOPMEM_MASK (7 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_EN (0 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_STOP (1 << PMC_CESASTOPMEM_OFFS) + +#define PMC_GESTOPMEM_OFFS(port) ((port) < 4 ? (9 - (port) * 3) : 0) +#define PMC_GESTOPMEM_MASK(port) (7 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +#define PMC_PNCSTOPMEM_OFFS 12 +#define PMC_PNCSTOPMEM_MASK (7 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_EN (0 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_STOP (1 << PMC_PNCSTOPMEM_OFFS) + +#define PMC_BMSTOPMEM_OFFS 15 +#define PMC_BMSTOPMEM_MASK (7 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_EN (0 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_STOP (1 << PMC_BMSTOPMEM_OFFS) + +#define PMC_PDMASTOPMEM_OFFS 0 +#define PMC_PDMATOPMEM_MASK (7 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_EN (0 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_STOP (1 << PMC_PDMASTOPMEM_OFFS) + +#define PMC_NCSSTOPMEM_OFFS 24 +#define PMC_NCSSTOPMEM_MASK (7 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_EN (0 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_STOP (1 << PMC_NCSSTOPMEM_OFFS) + +#define PMC_CFUSTOPMEM_OFFS 21 +#define PMC_CFUSTOPMEM_MASK (7 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_EN (0 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_STOP (1 << PMC_CFUSTOPMEM_OFFS) + +#define PMC_L2STOPMEM_OFFS 18 +#define PMC_L2STOPMEM_MASK (7 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_EN (0 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_STOP (1 << PMC_L2STOPMEM_OFFS) + +#define PMC_CIBSTOPMEM_OFFS 15 +#define PMC_CIBSTOPMEM_MASK (7 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_EN (0 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_STOP (1 << PMC_CIBSTOPMEM_OFFS) + +/* TODO - verify, the manual has no description */ +#define PMC_CPUSTOPMEM_OFFS(id) ((id) < 4 ? (id) * 3 : 0) +#define PMC_CPUSTOPMEM_MASK(id) (7 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_EN(id) (0 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_STOP(id) (1 << PMC_CPUSTOPMEM_OFFS(id)) + +#define PMC_IDMASTOPMEM_OFFS 12 +#define PMC_IDMASTOPMEM_MASK (7 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_EN (0 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_STOP (1 << PMC_IDMASTOPMEM_OFFS) + +#define PMC_LCDSTOPMEM_OFFS 0 +#define PMC_LCDSTOPMEM_MASK (7 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_EN (0 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_STOP (1 << PMC_LCDSTOPMEM_OFFS) + +#define PMC_PMUSTOPMEM_OFFS 0 +#define PMC_PMUSTOPMEM_MASK (7 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_EN (0 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_STOP (1 << PMC_PMUSTOPMEM_OFFS) + + +/* Power Management Clock Gating Control Register */ +#define POWER_MNG_CTRL_REG 0x18220 + +#define PMC_TDMSTOPCLOCK_OFFS 25 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) +#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) + +#define PMC_USBSTOPCLOCK_OFFS(port) ((port) < 3 ? (18 + (port)) : 0) +#define PMC_USBSTOPCLOCK_MASK(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_EN(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_STOP(port) (0 << PMC_USBSTOPCLOCK_OFFS(port)) + +#define PMC_SDIOSTOPCLOCK_OFFS 17 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_RUNITSTOPCLOCK_OFFS 24 +#define PMC_RUNITSTOPCLOCK_MASK (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_EN (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_STOP (0 << PMC_RUNITSTOPCLOCK_OFFS) + +#define PMC_XORSTOPCLOCK_OFFS 22 +#define PMC_XORSTOPCLOCK_MASK (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_EN (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_STOP (0 << PMC_XORSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS(ch) (ch == 0 ? 14 : 29) +#define PMC_SATASTOPCLOCK_MASK(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_EN(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_STOP(ch) (0 << PMC_SATASTOPCLOCK_OFFS(ch)) + +#define PMC_CESASTOPCLOCK_OFFS 23 +#define PMC_CESASTOPCLOCK_MASK (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_EN (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_STOP (0 << PMC_CESASTOPCLOCK_OFFS) + +#define PMC_GESTOPCLOCK_OFFS(port) ((port) < 4 ? (4 - (port)) : 0) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_NETASTOPCLOCK_OFFS 13 +#define PMC_NETASTOPCLOCK_MASK (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_EN (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_STOP (0 << PMC_NETASTOPCLOCK_OFFS) + +#define PMC_LCDSTOPCLOCK_OFFS 16 +#define PMC_LCDSTOPCLOCK_MASK (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_EN (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_STOP (0 << PMC_LCDSTOPCLOCK_OFFS) + +#define PMC_IDMASTOPCLOCK_OFFS 21 +#define PMC_IDMASTOPCLOCK_MASK (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_EN (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_STOP (0 << PMC_IDMASTOPCLOCK_OFFS) + +#define PMC_DDRSTOPCLOCK_OFFS 28 +#define PMC_DDRSTOPCLOCK_MASK (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_EN (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_STOP (0 << PMC_DDRSTOPCLOCK_OFFS) + +#define SATA_PWR_PLL_CTRL_REG(port) (0xA2804 + (port)*0x2000) +#define SATA_DIG_LP_ENA_REG(port) (0xA288C + (port)*0x2000) +#define SATA_REF_CLK_SEL_REG(port) (0xA2918 + (port)*0x2000) +#define SATA_LP_PHY_EXT_CTRL_REG(port) (0xA2058 + (port)*0x2000) +#define SATA_LP_PHY_EXT_STAT_REG(port) (0xA205C + (port)*0x2000) + +#define SGMII_PWR_PLL_CTRL_REG(port) (0x72E04 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_DIG_LP_ENA_REG(port) (0x72E8C + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_REF_CLK_SEL_REG(port) (0x72F18 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_CFG_REG(port) (0x724A0 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_STAT_REG(port) (0x724A4 + ((port)%2)*0x4000 - ((port)/2)*0x40000) + +#define SERDES_LINE_MUX_REG_0_7 0x18270 +#define SERDES_LINE_MUX_REG_8_15 0x18274 + +/* Controler environment registers offsets */ +#define GEN_PURP_RES_1_REG 0x182F4 +#define GEN_PURP_RES_2_REG 0x182F8 + +#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) + +/* Sample at Reset */ +#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) + +/* SYSRSTn Length Counter */ +#define SYSRST_LENGTH_COUNTER_REG 0x18250 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) + +/* Device ID */ +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK 0x3 + +#define MPP_OUTPUT_DRIVE_REG 0x184E4 +#define MPP_GE_A_OUTPUT_DRIVE_OFFS 6 +#define MPP_GE_A_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_A_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_OUTPUT_DRIVE_OFFS 14 +#define MPP_GE_B_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_B_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_B_OUTPUT_DRIVE_OFFS) + +#define MSAR_BOOT_MODE_OFFS 5 +#define MSAR_BOOT_MODE_MASK (0xF << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NOR (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI (0x3 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_DOVE_NAND (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_LEGACY_NAND (0x6 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLCK0_OFFS 24 +#define MSAR_TCLCK1_OFFS 8 +#define MSAR_TCLCK0_MASK (0x1 << MSAR_TCLCK0_OFFS) +#define MSAR_TCLCK1_MASK (0x1 << MSAR_TCLCK1_OFFS) + + +/* Extract CPU, L2, DDR clocks SAR value from +** SAR bits 24-27 +*/ +#define MSAR_CPU_CLK_IDX(sar0, sar1) ((((sar0) >> 21) & 0x7) + ((((sar1) >> 20) & 1) << 3)) +#define MSAR_CPU_CLK_TWSI(sar0, sar1) ((((sar0) >> 2) & 0x7) + (((sar1) & 1) << 3)) +#define MSAR_DDR_L2_CLK_RATIO_IDX(sar0,sar1) ((((sar0) >> 24) & 0xF) + ((((sar1) >> 19) & 1) << 4)) +#define MSAR_DDR_L2_CLK_RATIO_TWSI(sar0) (((sar0) >> 1) & 0xF) + +#ifndef MV_ASMLANGUAGE + +#define MV_CPU_CLK_TBL { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000,\ + 600, 667, 800, 1600, 2133, 2200, 2400, 0 } + +#define MV_DEFAULT_PCLK 1333000000 +#define MV_BOARD_DEFAULT_SYSCLK MV_DEFAULT_PCLK +#define MV_BOARD_DEFAULT_L2CLK 667000000 + +/* cpu l2c hclk ddr */ +#define MV_DDR_L2_CLK_RATIO_TBL { \ +/*00*/ { 1, 1, 4, 2 },\ +/*01*/ { 1, 2, 2, 2 },\ +/*02*/ { 2, 2, 6, 3 },\ +/*03*/ { 2, 2, 3, 3 },\ +/*04*/ { 1, 2, 3, 3 },\ +/*05*/ { 1, 2, 4, 2 },\ +/*06*/ { 1, 1, 2, 2 },\ +/*07*/ { 2, 3, 6, 6 },\ +/*08*/ { 2, 3, 5, 5 },\ +/*09*/ { 1, 2, 6, 3 },\ +/*10*/ { 2, 4, 10, 5 },\ +/*11*/ { 1, 3, 6, 6 },\ +/*12*/ { 1, 2, 5, 5 },\ +/*13*/ { 1, 3, 6, 3 },\ +/*14*/ { 1, 2, 5, 5 },\ +/*15*/ { 2, 2, 5, 5 },\ +/*16*/ { 1, 1, 3, 3 },\ +/*17*/ { 2, 5, 10, 10 },\ +/*18*/ { 1, 3, 8, 4 },\ +/*19*/ { 1, 1, 2, 1 },\ +/*20*/ { 2, 3, 6, 3 },\ +/*21*/ { 1, 2, 8, 4 },\ +/*22*/ { 2, 5, 10, 5 } \ +} + +/* These macros help units to identify a target Mport Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) +#define MV_TARGET_IS_PEX2(target) \ + ((target >= PEX2_MEM) && (target <= PEX2_IO)) +#define MV_TARGET_IS_PEX3(target) \ + ((target >= PEX3_MEM) && (target <= PEX3_IO)) +#define MV_TARGET_IS_PEX4(target) \ + ((target >= PEX4_MEM) && (target <= PEX4_IO)) +#define MV_TARGET_IS_PEX5(target) \ + ((target >= PEX5_MEM) && (target <= PEX5_IO)) +#define MV_TARGET_IS_PEX6(target) \ + ((target >= PEX6_MEM) && (target <= PEX6_IO)) +#define MV_TARGET_IS_PEX7(target) \ + ((target >= PEX7_MEM) && (target <= PEX7_IO)) +#define MV_TARGET_IS_PEX8(target) \ + ((target >= PEX8_MEM) && (target <= PEX8_IO)) +#define MV_TARGET_IS_PEX9(target) \ + ((target >= PEX9_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_PEX(target) ((target >= PEX0_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_DEVICE(target) ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == BOOT_ROM_CS) + +#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS) ? \ + sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) \ + & MSAR_BOOT_MODE_MASK) \ + >> MSAR_BOOT_MODE_OFFS)] : (target)) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + + +#define BOOT_TARGETS_NAME_ARRAY { \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS \ +} + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + START_DEV_CS) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +/* This enumerator defines the Marvell controller target ID (see Address map) */ +typedef enum _mvTargetId { + DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */ + PEX0_2_TARGET_ID = 4, /* Port 4 -> PCI Express 0 and 2 */ + PEX1_3_TARGET_ID = 8, /* Port 4 -> PCI Express 1 and 3 */ + CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */ + PNC_BM_TARGET_ID = 12, /* Port 12 -> PNC + BM Unit */ + MAX_TARGETS_ID +} MV_TARGET_ID; + +/* +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7 +} MV_SERDES_UNIT_INDX; +*/ + +/* + This structure refrect registers: + Serdes 0-7 selectors 0x18270 + and Serdes 8-15 selectors 0x18274 +*/ +#define SERDES_CFG { \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 0 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 1 */ \ + {0, 1, -1 , 2, -1, -1, -1, -1}, /* Lane 2 */ \ + {0, 1, -1 , -1, 2, -1, -1, -1}, /* Lane 3 */ \ + {0, 1, 2 , -1, -1, 3, -1, -1}, /* Lane 4 */ \ + {0, 1, 2 , -1, 3, -1, -1, 4}, /* Lane 5 */ \ + {0, 1, -1 , -1, -1, 2, 3, -1}, /* Lane 6 */ \ + {0, 1, -1 , 2, -1, -1, 3, -1}, /* Lane 7*/ \ + {0, 1, 2 , -1, -1, -1, 3, 4}, /* Lane 8 */ \ + {0, 1, 2 , 3, -1, -1, -1, -1}, /* Lane 9 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 10 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 11 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 12 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 13 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 14 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1} /* Lane 15 */ \ +} + +/* + This enum should reflect the units numbers in register + space which we will need when accessing the HW +*/ + +typedef enum { + PEX0_0x4 = 0, + PEX0_1x4 = 1, + PEX0_2x4 = 2, + PEX0_3x4 = 3, + PEX1_0x4 = 4, + PEX1_1x4 = 5, + PEX1_2x4 = 6, + PEX1_3x4 = 7, + PEX2_0x4 = 8, + PEX3_0x4 = 9, + PEXIF_MAX = 10 +} MV_PEXIF_INDX; + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,457 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +#include "cpu/mvCpu.h" /* whoAmI() */ + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define OLD_CESA_HAL +/* #if defined OLD_CESA_HAL +#warning "Workign with old CESA HAL (one channel only!)" +#endif +*/ +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* + * Armada-XP Units Address decoding + */ +#define MV_DRAM_REGS_OFFSET (0x0) +#define MV_AURORA_L2_REGS_OFFSET (0x8000) +#define MV_RTC_REGS_OFFSET (0x10300) +#define MV_DEV_BUS_REGS_OFFSET (0x10400) +#define MV_SPI_REGS_OFFSET(unit) (0x10600) +#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100)) +#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100)) +#define MV_MPP_REGS_OFFSET (0x18000) +#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x20)) +#define MV_MISC_REGS_OFFSET (0x18200) +#define MV_MBUS_REGS_OFFSET (0x20000) +#define MV_COHERENCY_FABRIC_OFFSET (0x20200) +#define MV_CNTMR_REGS_OFFSET (0x20300) +#define MV_CPUIF_REGS_OFFSET(cpu) (0x21000 + (cpu) * 0x100) +#if defined(MV_ETH_LEGACY) + #define MV_ETH_BASE_ADDR (0x72000) +#else + #define MV_ETH_BASE_ADDR (0x70000) +#endif +#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * 0x40000 + ((port) % 2) * 0x4000) +#define MV_PEX_IF_REGS_OFFSET(pexIf) (pexIf < 8 ? (0x40000 + ((pexIf) / 4) * 0x40000 + ((pexIf) % 4) * 0x4000)\ + : (0X42000 + ((pexIf) % 8) * 0x40000)) +#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000)) +#define MV_XOR_REGS_OFFSET(unit) (0x60900) +#define MV_CESA_TDMA_REGS_OFFSET (0x90000) +#define MV_CESA_REGS_OFFSET (0x9D000) +#define MV_SATA_REGS_OFFSET (0xA0000) +#define MV_COMM_UNIT_REGS_OFFSET (0xB0000) +#define MV_NFC_REGS_OFFSET (0xC0000) +#define MV_BM_REGS_OFFSET (0xC0000) +#define MV_PNC_REGS_OFFSET (0xC8000) +#define MV_SDMMC_REGS_OFFSET (0xD4000) + +#define MV_SERDES_NUM_TO_PEX_NUM(sernum) ((sernum < 8) ? (sernum) : (8 + (sernum/12))) +/* + * Miscellanuous Controller Configurations + */ +#define INTER_REGS_SIZE _1M + +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG CPU_MAIN_INT_CAUSE_REG(1, whoAmI()) +#define TWSI0_CPU_MAIN_INT_BIT(ch) ((ch) + 3) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_PINS 68 +#define MV_GPP_MAX_GROUP 3 /* group == configuration register? */ +#define MV_CNTMR_MAX_COUNTER 8 /* 4 global + 2 per CPU + 2*WD*/ +#define MV_UART_MAX_CHAN 4 + +#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ + +#define MV_SATA_MAX_CHAN 2 + +#define MV_MPP_MAX_GROUP 9 + +#define MV_DRAM_MAX_CS 4 +#define MV_SPI_MAX_CS 8 +/* This define describes the maximum number of supported PCI\PCIX Interfaces */ +#ifdef MV_INCLUDE_PCI + #define MV_PCI_MAX_IF 1 + #define MV_PCI_START_IF 0 + #define PCI_HOST_BUS_NUM(pciIf) (pciIf) + #define PCI_HOST_DEV_NUM(pciIf) 0 +#else + #define MV_PCI_MAX_IF 0 + #define MV_PCI_START_IF 0 +#endif + +/* This define describes the maximum number of supported PEX Interfaces */ +#ifdef MV_INCLUDE_PEX +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR + +#define MV_PEX_MAX_IF 10 +#define MV_PEX_START_IF MV_PCI_MAX_IF +#define MV_PEX_MAX_UNIT 4 + #define PEX_HOST_BUS_NUM(pciIf) (pciIf) + #define PEX_HOST_DEV_NUM(pciIf) 0 +#else + #undef MV_INCLUDE_PEX0 +#endif + +#define PCI_IO(pciIf) (PEX0_IO + 2 * (pciIf)) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM0 + 2 * (pciIf)) +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_IDMA_MAX_CHAN 4 +#define ARMADA_XP_MAX_USB_PORTS 3 +#define ARMADA_XP_NAND 1 +#define ARMADA_XP_SDIO 1 +#define ARMADA_XP_MAX_TDM_PORTS 32 +#define ARMADA_XP_TDM 1 +#define MV_DEVICE_MAX_CS 4 + +#ifndef MV_USB_MAX_PORTS +#define MV_USB_MAX_PORTS (ARMADA_XP_MAX_USB_PORTS) +#endif + + +/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */ +#define MV_CESA_VERSION 3 /*TODO verify */ +#define MV_CESA_SRAM_SIZE (2 * 1024) +#ifndef OLD_CESA_HAL +#define MV_CESA_ENGINES 2 +#endif + +/* This define describes the maximum number of supported Ethernet ports */ +/* TODO - verify all these numbers */ +#define MV_ETH_VERSION 4 /* for Legacy mode */ +#define MV_NETA_VERSION 1 /* for NETA mode */ +#define MV_ETH_MAX_PORTS 4 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_TX_CSUM_MAX_SIZE 9800 +#define MV_ETH_TCAM_LINES 1024 /* TCAM num of entries */ + +#define MV_78130_ETH_MAX_PORT 3 +#define MV_78460_ETH_MAX_PORT 4 + +/* This define describes the the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_SPI_VERSION 2 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#ifndef MV_ASMLANGUAGE + +#define TBL_UNUSED 0 /* Used to mark unused entry */ + +typedef enum { + TDM_UNIT_32CH +} MV_TDM_UNIT_TYPE; + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId { + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_32CH_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + SDIO_UNIT_ID, + BM_UNIT_ID, + PNC_UNIT_ID, + MAX_UNITS_ID +} MV_UNIT_ID; + +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice { +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif + BOOT_CS, /* Device connected to BOOT dev */ + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +} MV_DEVICE; + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget { + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /*0 SDRAM chip select 0 */ + SDRAM_CS1, /*1 SDRAM chip select 1 */ + SDRAM_CS2, /*2 SDRAM chip select 2 */ + SDRAM_CS3, /*3 SDRAM chip select 3 */ + DEVICE_CS0, /*4 Device chip select 0 */ + DEVICE_CS1, /*5 Device chip select 1 */ + DEVICE_CS2, /*6 Device chip select 2 */ + DEVICE_CS3, /*7 Device chip select 3 */ + PEX0_MEM, /*8 PCI Express 0 Memory */ + PEX0_IO, /*9 PCI Express 0 IO */ + PEX1_MEM, /*10 PCI Express 1 Memory */ + PEX1_IO, /*11 PCI Express 1 IO */ + PEX2_MEM, /*12 PCI Express 2 Memory */ + PEX2_IO, /*13 PCI Express 2 IO */ + PEX3_MEM, /*14 PCI Express 3 Memory */ + PEX3_IO, /*15 PCI Express 3 IO */ + PEX4_MEM, /*16 PCI Express 4 Memory */ + PEX4_IO, /*17 PCI Express 4 IO */ + PEX5_MEM, /*18 PCI Express 5 Memory */ + PEX5_IO, /*19 PCI Express 5 IO */ + PEX6_MEM, /*20 PCI Express 6 Memory */ + PEX6_IO, /*21 PCI Express 6 IO */ + PEX7_MEM, /*22 PCI Express 7 Memory */ + PEX7_IO, /*23 PCI Express 7 IO */ + PEX8_MEM, /*24 PCI Express 8 Memory */ + PEX8_IO, /*25 PCI Express 8 IO */ + PEX9_MEM, /*26 PCI Express 9 Memory */ + PEX9_IO, /*27 PCI Express 9 IO */ + INTER_REGS, /*28 Internal registers */ + DMA_UART, /*29 DMA based UART request */ + SPI_CS0, /*30 SPI_CS0 */ + SPI_CS1, /*31 SPI_CS1 */ + SPI_CS2, /*32 SPI_CS2 */ + SPI_CS3, /*33 SPI_CS3 */ + SPI_CS4, /*34 SPI_CS4 */ + SPI_CS5, /*35 SPI_CS5 */ + SPI_CS6, /*36 SPI_CS6 */ + SPI_CS7, /*37 SPI_CS7 */ + BOOT_ROM_CS, /*38 BOOT_ROM_CS */ + DEV_BOOCS, /*39 DEV_BOOCS */ + PMU_SCRATCHPAD, /*40 PMU Scratchpad */ +#ifdef MV_INCLUDE_LEGACY_NAND + LEGACY_NAND, /* Legacy NAND controller */ +#endif + CRYPT_ENG, /*41 Crypto Engine */ +#ifndef OLD_CESA_HAL + CRYPT_ENG1, /* Crypto Engine1 */ +#endif +#ifdef CONFIG_MV_ETH_BM + PNC_BM, /* PNC + BM */ +#endif + MAX_TARGETS +} MV_TARGET; + +#if defined OLD_CESA_HAL +#define CESA_TARGET_ID_DEF {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG */ +#else +#define CESA_TARGET_ID_DEF {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG0 */ \ + {0x05, CRYPT_TARGET_ID }, /* CRYPT_ENG1 */ +#endif + +#ifdef AURORA_IO_CACHE_COHERENCY +#define DRAM_CS0_ATTR 0x1E +#define DRAM_CS1_ATTR 0x1D +#define DRAM_CS2_ATTR 0x1B +#define DRAM_CS3_ATTR 0x17 +#else +#define DRAM_CS0_ATTR 0x0E +#define DRAM_CS1_ATTR 0x0D +#define DRAM_CS2_ATTR 0x0B +#define DRAM_CS3_ATTR 0x07 +#endif + +#define TARGETS_DEF_ARRAY { \ + {DRAM_CS0_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS1_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {DRAM_CS2_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS3_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0x3E, DEV_TARGET_ID }, /* DEVICE_CS0 */ \ + {0x3D, DEV_TARGET_ID }, /* DEVICE_CS1 */ \ + {0x3B, DEV_TARGET_ID }, /* DEVICE_CS2 */ \ + {0x37, DEV_TARGET_ID }, /* DEVICE_CS3 */ \ + {0xE8, PEX0_2_TARGET_ID }, /* PEX0_LANE0_MEM */ \ + {0xE0, PEX0_2_TARGET_ID }, /* PEX0_LANE0_IO */ \ + {0xD8, PEX0_2_TARGET_ID }, /* PEX0_LANE1_MEM */ \ + {0xD0, PEX0_2_TARGET_ID }, /* PEX0_LANE1_IO */ \ + {0xB8, PEX0_2_TARGET_ID }, /* PEX0_LANE2_MEM */ \ + {0xB0, PEX0_2_TARGET_ID }, /* PEX0_LANE2_IO */ \ + {0x78, PEX0_2_TARGET_ID }, /* PEX0_LANE3_MEM */ \ + {0x70, PEX0_2_TARGET_ID }, /* PEX0_LANE3_IO */ \ + {0xE8, PEX1_3_TARGET_ID }, /* PEX1_LANE0_MEM */ \ + {0xE0, PEX1_3_TARGET_ID }, /* PEX1_LANE0_IO */ \ + {0xD8, PEX1_3_TARGET_ID }, /* PEX1_LANE1_MEM */ \ + {0xD0, PEX1_3_TARGET_ID }, /* PEX1_LANE1_IO */ \ + {0xB8, PEX1_3_TARGET_ID }, /* PEX1_LANE2_MEM */ \ + {0xB0, PEX1_3_TARGET_ID }, /* PEX1_LANE2_IO */ \ + {0x78, PEX1_3_TARGET_ID }, /* PEX1_LANE3_MEM */ \ + {0x70, PEX1_3_TARGET_ID }, /* PEX1_LANE3_IO */ \ + {0xF8, PEX0_2_TARGET_ID }, /* PEX2_LANE0_MEM */ \ + {0xF0, PEX0_2_TARGET_ID }, /* PEX2_LANE0_IO */ \ + {0xF8, PEX1_3_TARGET_ID }, /* PEX3_LANE0_MEM */ \ + {0xF0, PEX1_3_TARGET_ID }, /* PEX3_LANE0_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x01, DEV_TARGET_ID }, /* DMA_UART */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS0 */ \ + {0x5E, DEV_TARGET_ID }, /* SPI_CS1 */ \ + {0x9E, DEV_TARGET_ID }, /* SPI_CS2 */ \ + {0xDE, DEV_TARGET_ID }, /* SPI_CS3 */ \ + {0x1F, DEV_TARGET_ID }, /* SPI_CS4 */ \ + {0x5F, DEV_TARGET_ID }, /* SPI_CS5 */ \ + {0x9F, DEV_TARGET_ID }, /* SPI_CS6 */ \ + {0xDF, DEV_TARGET_ID }, /* SPI_CS7 */ \ + {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ + {0x2F, DEV_TARGET_ID }, /* DEV_BOOT_CS */ \ + {0x2D, DEV_TARGET_ID }, /* PMU_SCRATCHPAD */ \ + CESA_TARGET_ID_DEF \ + {0x00, PNC_BM_TARGET_ID }, /* PNC_BM */ \ +} + +#if defined OLD_CESA_HAL +#define CESA_TARGET_NAME_DEF "CRYPT_ENG" +#else +#define CESA_TARGET_NAME_DEF "CRYPT_ENG0", "CRYPT_ENG1" +#endif + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS1 */ \ + "SDRAM_CS3", /* SDRAM_CS1 */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEVICE_CS3", /* DEVICE_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "PEX2_MEM", /* PEX2_MEM */ \ + "PEX2_IO", /* PEX2_IO */ \ + "PEX3_MEM", /* PEX3_MEM */ \ + "PEX3_IO", /* PEX3_IO */ \ + "PEX4_MEM", /* PEX4_MEM */ \ + "PEX4_IO", /* PEX4_IO */ \ + "PEX5_MEM", /* PEX5_MEM */ \ + "PEX5_IO", /* PEX5_IO */ \ + "PEX6_MEM", /* PEX6_MEM */ \ + "PEX6_IO", /* PEX6_IO */ \ + "PEX7_MEM", /* PEX7_MEM */ \ + "PEX7_IO", /* PEX7_IO */ \ + "PEX8_MEM", /* PEX8_MEM */ \ + "PEX8_IO", /* PEX8_IO */ \ + "PEX9_MEM", /* PEX9_MEM */ \ + "PEX9_IO", /* PEX9_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DMA_UART", /* DMA_UART */ \ + "SPI_CS0", /* SPI_CS0 */ \ + "SPI_CS1", /* SPI_CS1 */ \ + "SPI_CS2", /* SPI_CS2 */ \ + "SPI_CS3", /* SPI_CS3 */ \ + "SPI_CS4", /* SPI_CS4 */ \ + "SPI_CS5", /* SPI_CS5 */ \ + "SPI_CS6", /* SPI_CS6 */ \ + "SPI_CS7", /* SPI_CS7 */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */ \ + CESA_TARGET_NAME_DEF, \ + "PNC_BM" /* PNC_BM */ \ +} + + + + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvSpech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,750 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "mvCpuIfRegs.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* typedefs */ + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs { + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +} AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + MV_U32 sizeToReg; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to " + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* Size parameter validity check. */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.size, ATMWCR_WIN_SIZE_ALIGNMENT)) { + mvOsPrintf("mvAhbToMbusWinSet: Failed, size not aligned to 0x%x.\n", ATMWCR_WIN_SIZE_ALIGNMENT); + return MV_BAD_PARAM; + } + + /* Write to address decode Base Address Register */ + decRegs.baseReg = (pAddrDecWin->addrWin.baseLow & ATMWBR_BASE_MASK); + + /* Get size register value according to window size */ + sizeToReg = (pAddrDecWin->addrWin.size / ATMWCR_WIN_SIZE_ALIGNMENT) - 1; + + /* set size */ + decRegs.ctrlReg = (sizeToReg << ATMWCR_WIN_SIZE_OFFS); + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + decRegs.ctrlReg |= ATMWCR_WIN_ENABLE; + else + decRegs.ctrlReg &= ~ATMWCR_WIN_ENABLE; + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.ctrlReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.ctrlReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.ctrlReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.ctrlReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + mvAhbToMbusWinEnable(winNum, MV_FALSE); +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + } else { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + } + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.ctrlReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 sizeRegVal; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal register space size have no size register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.ctrlReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + else + decRegs.ctrlReg = 0; + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + else + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + + pAddrDecWin->addrWin.baseHigh = 0; + pAddrDecWin->addrWin.baseLow = decRegs.baseReg & ATMWBR_BASE_MASK; + sizeRegVal = (decRegs.ctrlReg & ATMWCR_WIN_SIZE_MASK) >> ATMWCR_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * ATMWCR_WIN_SIZE_ALIGNMENT; + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + if (decRegs.ctrlReg & ATMWCR_WIN_ENABLE) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + + if (-1 == pAddrDecWin->addrWin.size) + return MV_ERROR; + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.ctrlReg & ATMWCR_WIN_ATTR_MASK) >> ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.ctrlReg & ATMWCR_WIN_TARGET_MASK) >> ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is illegal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + return MV_AHB_TO_MBUS_INTREG_WIN; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) { + if (decWin.target == target) + return winNum; + } + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_FALSE) + return winNum; + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + return (enable ? MV_OK : MV_ERROR); + + + if (enable == MV_TRUE) { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } else { + /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + MV_U32 effectiveBaseAddress = 0, baseAddrValue = 0, windowSizeValue = 0; + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + return 0xffffffff; + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &= ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2) +{ + MV_U32 winNum1, winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1, winDec2, winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1, remapRegs2; + MV_U32 remapBaseLow1 = 0, remapBaseLow2 = 0; + MV_U32 remapBaseHigh1 = 0, remapBaseHigh2 = 0; + + /* Check parameters */ + if (target1 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target1, winNum1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + if (winNum2 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target2, winNum2); + return MV_ERROR; + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1, &winDec1)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinGet(winNum2, &winDec2)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum2); + return MV_ERROR; + } + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", winNum2); + return MV_ERROR; + } + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + /* now set the new values */ + mvAhbToMbusWinSet(winNum1, &winDec1); + mvAhbToMbusWinSet(winNum2, &winDec2); + + /* now we will treat the remap windows if exist */ + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows */ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs, remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs, remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs, remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs, remapBaseLow2); + } else { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs, winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs, winDec1.addrWin.baseLow); + } + } else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs, winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs, winDec2.addrWin.baseLow); + } + + return MV_OK; +} + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + case 4: + case 5: + case 6: + case 7: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + default: + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput("\n"); + mvOsOutput("AHB To MBUS Bridge:\n"); + mvOsOutput("-------------------\n"); + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + memset(&win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvAhbToMbusWinGet(winNum, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +typedef struct _mvAhbtoMbusDecWin { + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2); + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + +#endif /* __INCmvAhbToMbush */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,142 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +#define MAX_AHB_TO_MBUS_WINS 21 +#define MAX_AHB_TO_MBUS_REMAP_WINS 8 +#define MV_AHB_TO_MBUS_INTREG_WIN 20 + +/***********************/ +/* AHB TO MBUS WINDOWS */ +/***********************/ +/* Window-X Control Registers */ +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + winNum * 0x10): \ + (MV_MBUS_REGS_OFFSET + 0x90 + (winNum-8)*0x08)) +#define ATMWCR_WIN_ENABLE BIT0 +#define ATMWCR_WIN_TARGET_OFFS 4 +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) +#define ATMWCR_WIN_ATTR_OFFS 8 +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) +#define ATMWCR_WIN_SIZE_OFFS 16 +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window-X Base Register */ +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0x4 + winNum*0x10): \ + (MV_MBUS_REGS_OFFSET + 0x94 + (winNum-8)*0x08)) +#define ATMWBR_BASE_OFFS 16 +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window-X Remap Low Register */ +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0x8 + winNum*0x10): \ + (0)) +#define ATMWRLR_REMAP_LOW_OFFS 16 +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window-X Remap Hi Register */ +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0xC + winNum*0x10): \ + (0)) +#define ATMWRHR_REMAP_HIGH_OFFS 0 +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + +/*****************************/ +/* INTERNAL REGISTERS WINDOW */ +/*****************************/ +/* Internal Registers Base Address in set to be window 20 */ +#define AHB_TO_MBUS_WIN_INTEREG_REG (MV_MBUS_REGS_OFFSET + 0x80) + +/************************/ +/* SDRAM DECODE WINDOWS */ +/************************/ +/* All DRAM Window definitions are declared under the ddr2_3 HAL */ + +/****************************/ +/* SRAM (L2) DECODE WINDOWS */ +/****************************/ +#define SRAM_WIN_CTRL_REG(winNum) (MV_MBUS_REGS_OFFSET + 0x240 + winNum * 0x4) +#define SRAMWCR_ENABLE BIT0 +#define SRAMWCR_SIZE_OFFS 8 +#define SRAMWCR_SIZE_MASK (0x7 << SRAMWCR_SIZE_OFFS) +#define SRAMWCR_BASE_OFFS 16 +#define SRAMWCR_BASE_MASK (0xFFFF << SRAMWCR_BASE_OFFS) + +/**********************/ +/* MBUS BRIDGE WINDOW */ +/**********************/ +#define MBUS_BRIDGE_WIN_CTRL_REG (MV_MBUS_REGS_OFFSET + 0x250) +#define BRIDGWCR_ENABLE BIT0 +#define BRIDGWCR_SIZE_OFFS 16 +#define BRIDGWCR_SIZE_MASK (0xFFFF << BRIDGWCR_SIZE_OFFS) + +#endif /* __INCmvAhbToMbusRegsh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,875 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +/*#include "cpu/mvCpu.h" *//* whoAmI() */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "ddr2_3/mvDramIf.h" +#include "pex/mvPexRegs.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +/******************************************************************************* +* mvCpuIfInitForCpu - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* cpu - CPU id. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInitForCpu(MV_U32 cpu, MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal, i; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set CPU Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG(cpu)); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG(cpu), regVal); + + for (i = 0; i < MAX_AHB_TO_MBUS_WINS-2; i++) + mvAhbToMbusWinEnable(i, MV_FALSE); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS)) + continue; + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target), MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + continue; +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ + if (MV_TARGET_IS_AS_BOOT(target)) + continue; + + if ((0 == cpuAddrWinMap[target].addrWin.size) || (DIS == cpuAddrWinMap[target].enable)) { + #if 0 /* TODO: windows are already disabled above, we need to skip only*/ + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + #else + {continue;} + #endif + } else { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + } + } +#warning TODO: this is not needed anymore cause pex enabled is already at CtrlEnvInit +#if 0 +#ifdef MV_INCLUDE_PEX + if (cpu == 0) { /* Not needed for all CPUs */ + MV_U32 pexUnits = mvCtrlPexMaxUnitGet(); + for (i = 0; i < pexUnits; i++) + mvCpuIfEnablePex(i); + } +#endif +#endif + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + return mvCpuIfInitForCpu(whoAmI(), cpuAddrWinMap); +} + +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is illegal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + if (mvDramIfWinSet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + } else { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS) && (existingWinNum != pAddrDecWin->winNum)) { + /* if we want to enable the new window number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum, MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum, &decWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_U32 winNum = 0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is illegal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinGet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = target; + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return MV_NO_SUCH; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", __func__, winNum); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is illegal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) { + return (enable ? MV_ERROR : MV_OK); + } else if (MV_OK != temp) { + mvOsPrintf("%s: ERR. Getting target %d failed.\n", __func__, target); + return MV_ERROR; + } + + /* check overlap */ + if (MV_TRUE == enable) { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n", __func__, target)); + return MV_ERROR; + } + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinEnable(target, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + } + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return (enable ? MV_ERROR : MV_OK); + + if (mvAhbToMbusWinEnable(winNum, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", winNum); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is illegal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + return (addrDecWin.addrWin.size); + else + return 0; /* Window disabled. return 0 */ +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0xffffffff; + + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0; + + return (addrDecWin.addrWin.baseHigh); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (mvCtrlPexMaxIfGet() > 1) { + if ((!MV_TARGET_IS_PEX0(pexTarget)) && + (!MV_TARGET_IS_PEX1(pexTarget)) && + (!MV_TARGET_IS_PEX2(pexTarget)) && + (!MV_TARGET_IS_PEX3(pexTarget)) && + (!MV_TARGET_IS_PEX4(pexTarget)) && + (!MV_TARGET_IS_PEX5(pexTarget)) && + (!MV_TARGET_IS_PEX6(pexTarget)) && + (!MV_TARGET_IS_PEX7(pexTarget)) && + (!MV_TARGET_IS_PEX8(pexTarget)) && + (!MV_TARGET_IS_PEX9(pexTarget))) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } else { + if (!MV_TARGET_IS_PEX0(pexTarget)) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciIfTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for (target = 0; target < MAX_TARGETS; target++) { + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) + break; + } + } else + return MAX_TARGETS; + } + + return target; +} + +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + for (targetNum = 0; targetNum < MAX_TARGETS; targetNum++) { +#if defined(MV_RUN_FROM_FLASH) + if (MV_TARGET_IS_AS_BOOT(target)) { + if (MV_CHANGE_BOOT_CS(targetNum) == target) + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* don't check our target or illegal targets */ + if (targetNum == target) + continue; + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if (MV_NO_SUCH == status) + continue; + + if (MV_OK != status) { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) { + DB(mvOsPrintf("cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + mvOsOutput("\n"); + mvOsOutput("CPU Interface\n"); + mvOsOutput("-------------\n"); + + for (target = 0; target < MAX_TARGETS; target++) { + memset(&win, 0, sizeof(MV_CPU_DEC_WIN)); + + mvOsOutput("%s ", mvCtrlTargetNameGet(target)); + mvOsOutput("...."); + + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("base %08x, ", win.addrWin.baseLow); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } else if (mvCpuIfTargetWinGet(target, &win) == MV_NO_SUCH) { + mvOsOutput("no such\n"); + } + } +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfEnablePex - Enable PCI Express unit. +* +* DESCRIPTION: +* This function enables PCI Express access to the device address +* space. +* +* INPUT: +* pexUnit - PEX unit (0 - 3). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfEnablePex(MV_U32 pexUnit) +{ + MV_U32 socMaxPexUnit = mvCtrlPexMaxUnitGet(); + + if (pexUnit > socMaxPexUnit) { + DB(mvOsPrintf("mvCpuIfEnablePex: Bad PEX unit ID (%x)\n", pexUnit)); + return; + } + + /* SOC config register Pex enable */ + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); +} + +/******************************************************************************* +* mvCpuIfPex4x1Enable - Enable/Disable the 4x1 mode on PCI Express unit. +* +* DESCRIPTION: +* This function enables/disables 4x1 mode on PCI Express unit 0 or 1 +* +* INPUT: +* pexUnit - PEX unit (0 or 1). +* enable - enable (MV_TRUE) or disable (MV_FALSE) 4x1 mode +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfPex4x1Enable(MV_U32 pexUnit, MV_BOOL enable) +{ + if (pexUnit == 0) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX0_4BY1_MASK); + else if (pexUnit == 1) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX1_4BY1_MASK); + else + DB(mvOsPrintf("mvCpuIfPex4x1Enable: Bad PEX unit ID (%x)\n", pexUnit)); +} + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_CPU_DEC_WIN; + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_VOID mvCpuIfEnablePex(MV_U32 pexUnit); +MV_VOID mvCpuIfPex4x1Enable(MV_U32 pexUnit, MV_BOOL enable); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +#endif /* __INCmvCpuIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,167 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvCommon.h" +#include "mvOsAsm.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + b done +#if 0 + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281/6282 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) +#endif + +done: + mov PC, r11 /* r11 is saved link register */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,299 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + +#define MV_CPUIF_REGS_BASE(cpu) (MV_CPUIF_REGS_OFFSET(cpu)) +#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) +#define MV_L2C_REGS_BASE (MV_AURORA_L2_REGS_OFFSET) +#define MV_CPUIF_SHARED_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_COHERENCY_FABRIC_REGS_BASE (MV_COHERENCY_FABRIC_OFFSET) + +#define CPU_CONFIG_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x800) +#define CPU_CTRL_STAT_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x808) +#define CPU_RSTOUTN_MASK_REG (MV_MISC_REGS_BASE + 0x60) +#define CPU_SYS_SOFT_RST_REG (MV_MISC_REGS_BASE + 0x64) +#define CPU_L2_CTRL_REG (MV_L2C_REGS_BASE + 0x100) +#define CPU_L2_AUX_CTRL_REG (MV_L2C_REGS_BASE + 0x104) +#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) +#define SOC_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_REGS_BASE) +#define SOC_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x4) +#define SOC_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x80) + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK (1 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK (1 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + +#define CCR_ARM_ID_SEL_OFFS 4 +#define CCR_CPU_ID_SEL_MASK (1 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_ARM (0 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_MRVL (1 << CCR_ARM_ID_SEL_OFFS) + +#define CCR_TE_INIT_OFFS 5 +#define CCR_TE_INIT_MASK (1 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_ARM (0 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_THUMB (1 << CCR_NCB_BLOCKING_OFFS) + +#define CCR_NFMI_EN_OFFS 6 +#define CCR_NFMI_EN_MASK (1 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_DIS (0 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_EN (1 << CCR_NFMI_EN_OFFS) + +#define CCR_CORE_MODE_OFFS 9 +#define CCR_CORE_MODE_MASK (3 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM1176 (0 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_CORTEX_A8 (1 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM11_MPC (2 << CCR_CORE_MODE_OFFS) + +#define CCR_UBIT_INIT_OFFS 11 +#define CCR_UBIT_INIT_MASK (1 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_DIS (0 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_EN (1 << CCR_UBIT_INIT_OFFS) + +#define CCR_PCLK_WFI_OFFS 15 +#define CCR_PCLK_WFI_MASK (1 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_DIS (0 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_EN (1 << CCR_PCLK_WFI_OFFS) + +#define CCR_SHARED_L2_OFFS 16 +#define CCR_SHARED_L2_MASK (1 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_DIS (0 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_EN (1 << CCR_SHARED_L2_OFFS) + +#define CCR_SP_IN_MP_OFFS 17 +#define CCR_SP_IN_MP_MASK (1 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_DIS (0 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_EN (1 << CCR_SP_IN_MP_OFFS) + +#define CCR_SRAM_LOW_LEAK_OFFS 19 +#define CCR_SRAM_LOW_LEAK_MASK (1 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_EN (0 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_DIS (1 << CCR_SRAM_LOW_LEAK_OFFS) + +#define CCR_CLUSTER_ID_OFFS 24 +#define CCR_CLUSTER_ID_MASK (0xF << CCR_SRAM_LOW_LEAK_OFFS) + + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + +#define CCSR_SMP_N_AMP_OFFS 0 +#define CCSR_SMP_N_AMP_MASK (1 << CCSR_SMP_N_AMP_OFFS) + +#define CCSR_ENDIAN_STATUS_OFFS 0 +#define CCSR_ENDIAN_STATUS_MASK (1 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_LITTLE (0 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_BIG (1 << CCSR_ENDIAN_STATUS_OFFS) + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_SOFT_RST_OUT_OFFS 0 +#define CRMR_SOFT_RST_OUT_MASK (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISABLE (0 << CRMR_SOFT_RST_OUT_OFFS) + +#define CRMR_PEX_SYSRST_OUT_OFFS(bus) (1 + ((bus) & 0x3)) +#define CRMR_PEX_SYSRST_OUT_MASK(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_ENABLE(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_DISABLE(bus) (0 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) + +#define CRMR_PEX_TRST_OUT_OFFS(bus) (5 + ((bus) & 0x3)) +#define CRMR_PEX_TRST_OUT_MASK(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_ENABLE(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_DISABLE(bus) (0 << CRMR_PEX_TRST_OUT_OFFS(bus)) + + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + + +/* CPU_L2_CTRL_REG fields */ + +#define CL2CR_L2_EN_OFFS 0 +#define CL2CR_L2_EN_MASK (1 << CL2CR_L2_EN_OFFS) + +/* CPU_L2_AUX_CTRL_REG fields */ + +#define CL2ACR_WB_WT_ATTR_OFFS 0 +#define CL2ACR_WB_WT_ATTR_MASK (3 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_PAGE (0 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WB (1 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WT (2 << CL2ACR_WB_WT_ATTR_OFFS) + +#define CL2ACR_PFU_OFFS 2 +#define CL2ACR_PFU_MASK (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_EN (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_DIS (0 << CL2ACR_PFU_OFFS) + +#define CL2ACR_L2_SIZE_OFFS 10 +#define CL2ACR_L2_SIZE_MASK (3 << CL2ACR_L2_SIZE_OFFS) +#define CL2ACR_L2_SIZE_KB(reg) ((((((reg) & 0x3) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_PFU_OFFS) + 1) * _512K) + +#define CL2ACR_ASSOC_OFFS 13 +#define CL2ACR_ASSOC_MASK (0xF << CL2ACR_ASSOC_OFFS) + +#define CL2ACR_L2_WAY_SZ_OFFS 17 +#define CL2ACR_L2_WAY_SZ_MASK (7 << CL2ACR_L2_WAY_SZ_OFFS) +#define CL2ACR_L2_WAY_SZ_KB(reg) (_16K << (((((reg) & 0x7) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_L2_WAY_SZ_OFFS))) + +#define CL2ACR_ECC_OFFS 20 +#define CL2ACR_ECC_MASK (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_EN (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_DIS (0 << CL2ACR_ECC_OFFS) + +#define CL2ACR_PARITY_OFFS 21 +#define CL2ACR_PARITY_MASK (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_EN (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_DIS (0 << CL2ACR_PARITY_OFFS) + +#define CL2ACR_INVAL_UCE_OFFS 22 +#define CL2ACR_INVAL_UCE_MASK (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_EN (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_DIS (0 << CL2ACR_INVAL_UCE_OFFS) + +#define CL2ACR_FORCE_WA_OFFS 23 +#define CL2ACR_FORCE_WA_MASK (3 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA_DISABLE (0 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_NO_WA (1 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA (2 << CL2ACR_FORCE_WA_OFFS) + +#define CL2ACR_REP_STRGY_OFFS 27 +#define CL2ACR_REP_STRGY_MASK (3 << CL2ACR_REP_STRGY_OFFS) + +/* SOC_CTRL_REG fields */ +#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) +#define SCR_PEX_ENA_MASK(pex) (1 << pex) + +#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) +#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) + +#define SCR_PEX0_4BY1_OFFS 7 +#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS) + +#define SCR_PEX1_4BY1_OFFS 8 +#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG(vec, cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x880 + (vec * 0x4)) +#define CPU_MAIN_INT_TWSI_OFFS(i) (2 + i) +#define CPU_MAIN_INT_CAUSE_TWSI(i) (31 + i) + +#define CPU_CF_LOCAL_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x8c4) +#define CPU_INT_SOURCE_CONTROL_REG(i) (MV_CPUIF_SHARED_REGS_BASE + 0xB00 + (i * 0x4)) + +#define CPU_INT_SOURCE_CONTROL_ENA_OFFS 28 +#define CPU_INT_SOURCE_CONTROL_ENA_MASK (1 << CPU_INT_SOURCE_CONTROL_ENA_OFFS) + + + +#define MV_IRQ_NR 116 + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x878) +#define CPU_HOST_TO_ARM_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x87C) +#define CPU_ARM_TO_HOST_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x870) +#define CPU_ARM_TO_HOST_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x874) + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK) +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +#endif /* __INCmvCpuIfRegsh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->turnOff out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->badrSkew out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8) && (pDevParams->deviceWidth != 16) && (pDevParams->deviceWidth != 32)) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } + + /* devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); */ + /* setting values */ + devParam |= DBP_TURNOFF_SET(pDevParams->turnOff); + devParam |= DBP_ACC2FIRST_SET(pDevParams->acc2First); + devParam |= DBP_ACC2NEXT_SET(pDevParams->acc2Next); + devParam |= ((pDevParams->badrSkew & DBP_BADRSKEW_MASK) << DBP_BADRSKEW_OFFS); + + switch (pDevParams->deviceWidth) { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + return MV_ERROR; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device), devParam); + + devParam = 0; + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(device), devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = DBP_TURNOFF_GET(devParam); + pDevParams->acc2First = DBP_ACC2FIRST_GET(devParam); + pDevParams->acc2Next = DBP_ACC2NEXT_GET(devParam); + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + switch (devParam & DBP_DEVWIDTH_MASK) { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth = 8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth = 16; + break; + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth = 32; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG_WR(device)); + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bits (8,16,32...). +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32) (0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandDevCsSet - Set NAND chip-select, care mode and init sequence +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(device)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(device)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(device)); + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "device/mvDeviceRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam { + /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash control registers with NAND device- */ +/* select and care mode */ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode); + +#endif /* #ifndef __INCmvDeviceH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,269 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_DEVICE_MAX_XBAR_TIMEOUT 0x0FFF +/* TODO - usage of DEV_BANK_PARAM_REG_DV is unclear */ +/* #define DEV_BANK_PARAM_REG_DV 0x80000000 */ +/* registers offsets */ + +static INLINE MV_U32 DEV_BANK_PARAM_REG(int num) +{ + switch (num) { + case (BOOT_CS): + return MV_DEV_BUS_REGS_OFFSET + 0x400; + case (DEV_CS0): + return MV_DEV_BUS_REGS_OFFSET + 0x408; + case (DEV_CS1): + return MV_DEV_BUS_REGS_OFFSET + 0x410; +#ifdef MV_INCLUDE_DEVICE_CS2 + case (DEV_CS2): + return MV_DEV_BUS_REGS_OFFSET + 0x418; +#endif +#ifdef MV_INCLUDE_DEVICE_CS3 + case (DEV_CS3): + return MV_DEV_BUS_REGS_OFFSET + 0x420; +#endif + default: + return 0xFFFFFFFF; + } +} + +#define DEV_BANK_PARAM_REG_WR(num) (DEV_BANK_PARAM_REG(num)+0x4) +#define DEV_NAND_CTRL_REG (MV_DEV_BUS_REGS_OFFSET + 0x0470) + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ +/* DBP_XXX_MASK_HIGH is the offset of the extend bit from the msb of the input value */ + +#define DBP_TURNOFF_OFFS_LOW 0 +#define DBP_TURNOFF_MASK_LOW 0x3F +#define MAX_DBP_TURNOFF 0xf + + +#define DBP_TURNOFF_SET(value) \ +((value & DBP_TURNOFF_MASK_LOW) << DBP_TURNOFF_OFFS_LOW) + +#define DBP_TURNOFF_GET(value) \ +((value >> DBP_TURNOFF_OFFS_LOW) & DBP_TURNOFF_MASK_LOW) + +#define DBP_ACC2FIRST_OFFS_LOW 6 +#define DBP_ACC2FIRST_MASK_LOW 0x3f +#define MAX_DBP_ACC2FIRST 0x3f + +#define DBP_ACC2FIRST_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2FIRST_GET(value) \ +((value >> DBP_ACC2FIRST_OFFS_LOW) & DBP_ACC2FIRST_MASK_LOW) + +#define DBP_ACC2NEXT_OFFS_LOW 17 +#define DBP_ACC2NEXT_MASK_LOW 0x3f +#define MAX_DBP_ACC2NEXT 0x3f + +#define DBP_ACC2NEXT_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2NEXT_GET(value) \ +((value >> DBP_ACC2NEXT_OFFS_LOW) & DBP_ACC2NEXT_MASK_LOW) + +#define DBP_DEVWIDTH_OFFS 30 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + + +#define DBP_ALE2WR_OFFS_LOW 0 +#define DBP_ALE2WR_MASK_LOW 0x3f +#define MAX_DBP_ALE2WR 0x3F + +#define DBP_ALE2WR_SET(value) \ +((value & DBP_ALE2WR_MASK_LOW) << DBP_ALE2WR_OFFS_LOW) + +#define DBP_ALE2WR_GET(value) \ +((value >> DBP_ALE2WR_OFFS_LOW) & DBP_ALE2WR_MASK_LOW) + +#define DBP_WRLOW_OFFS_LOW 8 +#define DBP_WRLOW_MASK_LOW 0x3F +#define MAX_DBP_WRLOW 0x3F + +#define DBP_WRLOW_SET(value) \ +((value & DBP_WRLOW_MASK_LOW) << DBP_WRLOW_OFFS_LOW) + +#define DBP_WRLOW_GET(value) \ +((value >> DBP_WRLOW_OFFS_LOW) & DBP_WRLOW_MASK_LOW) + +#define DBP_WRHIGH_OFFS_LOW 16 +#define DBP_WRHIGH_MASK_LOW 0x3F +#define MAX_DBP_WRHIGH 0x3F + +#define DBP_WRHIGH_SET(value) \ +((value & DBP_WRHIGH_MASK_LOW) << DBP_WRHIGH_OFFS_LOW) + +#define DBP_WRHIGH_GET(value) \ +((value >> DBP_WRHIGH_OFFS_LOW) & DBP_WRHIGH_MASK_LOW) + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +/* NAND Flash Control register fields (NF) (NF_REG)*/ +#define NF_BOOTCS_OFFS 0 /* Define if BOOTCS is connected to NAND Flash */ +#define NF_BOOT_MASK (1 << NF_BOOTCS_OFFS) +#define NF_BOOT_NC (0 << NF_BOOTCS_OFFS) +#define NF_BOOT_C (1 << NF_BOOTCS_OFFS) + +#define NF_BOOTCS_CE_ACT_OFFS 1 /* Define if NAND Flash on BOOTCS is CE care or CE don't care */ +#define NF_BOOTCS_CE_ACT_MASK (1 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_NCARE (0 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_CARE (1 << NF_BOOTCS_CE_ACT_OFFS) + +#define NF_CS0_OFFS 2 /* Define if CS0 is connected to NAND Flash */ +#define NF_CS0_MASK (1 << NF_CS0_OFFS) +#define NF_CS0_NC (0 << NF_CS0_OFFS) +#define NF_CS0_C (1 << NF_CS0_OFFS) + +#define NF_CS0_CE_ACT_OFFS 3 /* Define if NAND Flash on CS0 is CE care or CE don't care */ +#define NF_CS0_CE_ACT_MASK (1 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_NCARE (0 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_CARE (1 << NF_CS0_CE_ACT_OFFS) + +#define NF_CS1_OFFS 4 /* Define if CS1 is connected to NAND Flash */ +#define NF_CS1_MASK (1 << NF_CS1_OFFS) +#define NF_CS1_NC (0 << NF_CS1_OFFS) +#define NF_CS1_C (1 << NF_CS1_OFFS) + +#define NF_CS1_CE_ACT_OFFS 5 /* Define if NAND Flash on CS1 is CE care or CE don't care */ +#define NF_CS1_CE_ACT_MASK (1 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_NCARE (0 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_CARE (1 << NF_CS1_CE_ACT_OFFS) + +#define NF_CS2_OFFS 6 /* Define if CS2 is connected to NAND Flash */ +#define NF_CS2_MASK (1 << NF_CS2_OFFS) +#define NF_CS2_NC (0 << NF_CS2_OFFS) +#define NF_CS2_C (1 << NF_CS2_OFFS) + +#define NF_CS2_CE_ACT_OFFS 7 /* Define if NAND Flash on CS2 is CE care or CE don't care */ +#define NF_CS2_CE_ACT_MASK (1 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_NCARE (0 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_CARE (1 << NF_CS2_CE_ACT_OFFS) + +#define NF_INIT_SEQ_OFFS 8 /* NAND Flash initialization sequence */ +#define NF_INIT_SEQ_MASK (1 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_EN (0 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_DIS (1 << NF_INIT_SEQ_OFFS) + +#define NF_OE_HIGHW_OFFS 9 /* NAND Flash OE high width in core clocks units (value + 1) */ +#define NF_OE_HIGHW_MASK (0x1f << NF_OE_HIGHW_OFFS) +#define MAX_OE_HIGHW (0x1f << NF_OE_HIGHW_OFFS) + +#define NF_TREADY_OFFS 14 /* NAND Flash time ready in core clocks units (value + 1) */ +#define NF_TREADY_MASK (0x1f << NF_TREADY_OFFS) +#define MAX_TREADY (0x1f << NF_TREADY_OFFS) + +#define NF_OE_TCTRL_OFFS 19 /* NAND Flash OE toggle control */ +#define NF_OE_TCTRL_MASK (1 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_1_CYC_AFT (0 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_SAME_CYC (1 << NF_OE_TCTRL_OFFS) + +#define NF_CS3_OFFS 20 /* Define if CS3 is connected to NAND Flash */ +#define NF_CS3_MASK (1 << NF_CS3_OFFS) +#define NF_CS3_NC (0 << NF_CS3_OFFS) +#define NF_CS3_C (1 << NF_CS3_OFFS) + +#define NF_CS3_CE_ACT_OFFS 21 /* Define if NAND Flash on CS3 is CE care or CE don't care */ +#define NF_CS3_CE_ACT_MASK (1 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_NCARE (0 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_CARE (1 << NF_CS3_CE_ACT_OFFS) + + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) \ +(csNum == BOOT_CS) ? 0x1 : ((csNum == DEV_CS3) ? (0x1 << 20) : (0x1 << (((csNum+1) % MV_DEV_MAX_CS) * 2))) + + +#define DINFCR_NF_ACT_CE_MASK(csNum) \ +(csNum == DEV_CS3) ? (0x2 << 20) : (0x2 << (((csNum+1) % MV_DEV_MAX_CS) * 2)) + +#define NAND_ACTCEBOOT_BIT BIT1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCmvDeviceRegsH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bios.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bios.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bios.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bios.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,138 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#include "mvCommon.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + + +static int do_bios_list() +{ + int i = 0; + MV_U8 confId = mvBoardConfIdGet(); + + printf("DB Conf Conf ID L2 size CPU Freq Fabric Freq CPU1/2/3 Enable CPU Mode V6UP/V6MP\n"); +#warning TODO: -1 is for not showing the 78480 problematic flavour + if (confId != 0x11) { + for (i=0; i < BIOS_MODES_NUM-1; i++) { + + printf("%s\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n", bios_modes[i].name, bios_modes[i].confId, bios_modes[i].l2size, bios_modes[i].cpuFreq, bios_modes[i].fabricFreq, bios_modes[i].cpuEna, bios_modes[i].cpuMode); + } + } else { + printf("%s\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n", bios_modes[1].name, bios_modes[1].confId, bios_modes[1].l2size, bios_modes[1].cpuFreq, bios_modes[1].fabricFreq, bios_modes[1].cpuEna, bios_modes[1].cpuMode); + } + + return 0; +} +static int do_bios_read() +{ + int i = 0; + int flag = 0; + MV_U8 l2size = mvBoardL2SizeGet(); + MV_U8 cpuFreq = mvBoardCpuFreqGet(); + MV_U8 fabricFreq = mvBoardFabFreqGet(); + MV_U8 cpuEna = mvBoardCpuCoresNumGet(); + MV_U8 cpuMode = mvBoardCpu0CoreModeGet(); + MV_U8 confId = mvBoardConfIdGet(); + + for (i=0; i < BIOS_MODES_NUM; i++) { + if ((bios_modes[i].l2size == l2size) && + (bios_modes[i].cpuFreq == cpuFreq) && + (bios_modes[i].fabricFreq == fabricFreq) && + (bios_modes[i].cpuEna == cpuEna) && + (bios_modes[i].cpuMode == cpuMode) && + (bios_modes[i].confId == confId)) { + + printf("Current BIOS mode is: %s\n", bios_modes[i].name); + flag = 1; + } + } + if (flag == 0) + printf("Current BIOS mode is invalid!\n"); + + return 0; +} +static int do_bios_write(int argc, char *argv[]) +{ + int i = 0; + int flag = 0; + const char *cmd; + + if (argc < 1) + goto usage; + cmd = argv[0]; + + for (i=0; i < BIOS_MODES_NUM; i++) { + if (strcmp(cmd, bios_modes[i].name) == 0) { + + printf("Setting BIOS mode : %s\n", bios_modes[i].name); + mvBoardL2SizeSet(bios_modes[i].l2size); + mvBoardCpuFreqSet(bios_modes[i].cpuFreq); + mvBoardCpuFreqModeSet(bios_modes[i].cpuFreqMode); + mvBoardFabFreqSet(bios_modes[i].fabricFreq); + mvBoardFabFreqModeSet(bios_modes[i].fabricFreqMode); + mvBoardCpuCoresNumSet(bios_modes[i].cpuEna); + mvBoardCpu0CoreModeSet(bios_modes[i].cpuMode); + mvBoardConfIdSet(bios_modes[i].confId); + flag = 1; + } + } + if (flag == 0) + printf("BIOS mode is invalid!, please use bios list to see all modes\n"); + + return 0; +usage: + printf("Usage: bios write (see help) \n", argv[0]); + return 1; +} +int do_bios(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "list") == 0) + return do_bios_list(); + if (strcmp(cmd, "write") == 0) { + if (do_bios_write(argc - 2, argv + 2) == 0) + do_bios_read(); + return 0; + } + if (strcmp(cmd, "read") == 0) + return do_bios_read(); + +usage: + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD(bios, 3, 1, do_bios, + "BIOS command to set the DB configuration.\n", + + "list - prints the BIOS modes list\n" + "bios read - read and print the BIOS value\n" + + "bios write - write the BIOS to , see list for all modes\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bubt.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bubt.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bubt.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bubt.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,440 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +extern nand_info_t nand_info[]; /* info for NAND chips */ +#endif + +#ifdef CONFIG_CMD_SF +#include +extern struct spi_flash *flash; +#endif + +#if 0 +#if !defined(MV_NAND_BOOT) || !defined(MV_SPI_BOOT) +static unsigned int flash_in_which_sec(flash_info_t *fl,unsigned int offset) +{ + unsigned int sec_num; + if(NULL == fl) + return 0xFFFFFFFF; + + for( sec_num = 0; sec_num < fl->sector_count ; sec_num++){ + /* If last sector*/ + if (sec_num == fl->sector_count -1) + { + if((offset >= fl->start[sec_num]) && + (offset <= (fl->size + fl->start[0] - 1)) ) + { + return sec_num; + } + + } + else + { + if((offset >= fl->start[sec_num]) && + (offset < fl->start[sec_num + 1]) ) + { + return sec_num; + } + + } + } + /* return illegal sector Number */ + return 0xFFFFFFFF; + +} + +#endif /* !defined(CONFIG_NAND_BOOT) */ + +#include "bootstrap_def.h" +#if defined(CONFIG_CMD_NET) +/* + * 8 bit checksum + */ +MV_U8 checksum8(MV_U32 start, MV_U32 len, MV_U8 csum) +{ + register MV_U8 sum = csum; + volatile MV_U8* startp = (volatile MV_U8*)start; + + do { + sum += *startp; + startp++; + } while(--len); + + return (sum); +} /* end of checksum8 */ + +#if 0 +/* + * Check the extended header and execute the image + */ +static MV_U32 verify_extheader(ExtBHR_t *extBHR) +{ + MV_U8 chksum; + + + /* Caclulate abd check the checksum to valid */ + chksum = checksum8((MV_U32)extBHR , EXT_HEADER_SIZE -1, 0); + if (chksum != (*(MV_U8*)((MV_U32)extBHR + EXT_HEADER_SIZE - 1))) + { + printf("Error! invalid extende header checksum\n"); + return MV_FAIL; + } + + return MV_OK; +} +#endif +/* + * Check the CSUM8 on the main header + */ +static MV_U32 verify_main_header(BHR_t *pBHR, MV_U8 headerID) +{ + MV_U8 chksum,chksumtemp; + + /* Verify Checksum */ + chksumtemp = pBHR->checkSum; + pBHR->checkSum = 0; + chksum = checksum8((MV_U32)pBHR, MAIN_HDR_GET_LEN(pBHR), 0); + pBHR->checkSum = chksumtemp; + if (chksum != chksumtemp) + { + printf("\t[Fail] invalid image header checksum\n"); + return MV_FAIL; + } + + /* Verify Header */ + if (pBHR->blockID != headerID) + { + printf("\t[Fail] invalid image header ID\n"); + return MV_FAIL; + } + + /* Verify Alignment */ + if (pBHR->blockSize & 0x3) + { + printf("\t[Fail] invalid image header alignment\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->destinationAddr) & 0x3) && (cpu_to_le32(pBHR->destinationAddr) != 0xffffffff)) + { + printf("\t[Fail] invalid image header destination\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->sourceAddr) & 0x3) && (pBHR->blockID != IBR_HDR_SATA_ID)) + { + printf("\t[Fail] invalid image header source\n"); + return MV_FAIL; + } + + return MV_OK; +} +#endif //0 +#endif //0 + +#if defined(MV_NAND_BOOT) +/* Boot from NAND flash */ +/* Write u-boot image into the nand flash */ +int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + //u_char *load_addr; + load_addr = CONFIG_SYS_LOAD_ADDR; + uint64_t size = CONFIG_ENV_OFFSET; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("Using default filename \"u-boot.bin\" \n"); + } + filesize = NetLoop(TFTP); + printf("Checking file size:"); + if (filesize == -1) + { + printf("\t[Fail]\n"); + return 0; + } + printf("\t[Done]\n"); +#if 0 +#ifdef MV_BOOTROM + printf("Checking header cksum:"); + BHR_t* tmpBHR = (BHR_t*) load_addr; + + /* Verify Main header checksum */ + if (verify_main_header(tmpBHR, IBR_HDR_NAND_ID)) + return 0; + + printf("\t[Done]\n"); +#endif +#endif //0 + printf("Override Env parameters to default? [y/N]"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_RANGE); + nand_erase(nand, CONFIG_ENV_OFFSET, CONFIG_ENV_RANGE); + printf("\t[Done]\n"); + } + + printf("Erasing 0x%x - 0x%x: ", 0, 0 + CONFIG_ENV_OFFSET); + nand_erase(nand, 0, CONFIG_ENV_OFFSET); + printf("\t[Done]\n"); + + printf("Writing image to NAND:"); + ret = nand_write(nand, 0, &size, load_addr); + if (ret) + printf("\t[Fail]\n"); + else + printf("\t[Done]\n"); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nand_burn_uboot_cmd, + "bubt - Burn an image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Nand Flash, default file-name is u-boot.bin .\n" +); +#endif /* defined(CONFIG_NAND_BOOT) */ + +#if defined(MV_SPI_BOOT) +/* Boot from SPI flash */ +/* Write u-boot image into the SPI flash */ +int spi_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + size_t len = CONFIG_SYS_MONITOR_LEN; + load_addr = CONFIG_SYS_LOAD_ADDR; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("Using default filename \"u-boot.bin\" \n"); + } + filesize = NetLoop(TFTP); + printf("Checking file size:"); + if (filesize == -1) + { + printf("\t\t[ERR!]\n"); + return 0; + } + printf("\t\t[Done]\n"); +#if 0 +#ifdef MV_BOOTROM + printf("Checking header cksum:"); + BHR_t* tmpBHR = (BHR_t*) load_addr; + + /* Verify Main header checksum */ + if (verify_main_header(tmpBHR, IBR_HDR_SPI_ID)) + return 0; + + printf("\t[Done]\n"); +#endif +#endif //0 + + printf("Override Env parameters to default? [y/N]"); + readline(" "); +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE); + spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + printf("\t[Done]\n"); + } + + printf("Erasing 0x%x - 0x%x: ",0, 0 + CONFIG_ENV_OFFSET); + spi_flash_erase(flash, 0, CONFIG_ENV_OFFSET); + printf("\t\t[Done]\n"); + + printf("Writing image to flash:"); + ret = spi_flash_write(flash, 0, filesize, load_addr); + + if (ret) + printf("\t\t[Err!]\n"); + else + printf("\t\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, spi_burn_uboot_cmd, + "bubt - Burn an image on the Boot SPI Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot SPI Flash, default file-name is u-boot.bin .\n" +); +#endif + +#if 0 +#ifdef MV_BOOTROM +/* Upgrade BootROM image */ +int spi_burn_bootrom_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 from, to; + ushort sector_count; + ulong sector_size; + extern char console_buffer[]; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + printf("Must provide image file name as a parameter.\n"); + return 0; + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + sector_count = flash_info[BOOT_FLASH_INDEX].sector_count; + sector_size = flash_info[BOOT_FLASH_INDEX].size / sector_count; + from = flash_info[BOOT_FLASH_INDEX].start[sector_count - 1]; + to = from + sector_size; + + printf("Un-Protecting 0x%X to 0x%X\n", from, to); + flash_protect (FLAG_PROTECT_CLEAR, from, to, &flash_info[BOOT_FLASH_INDEX]); + + printf("Erasing 0x%X to 0x%X\n", from, to); + flash_erase(&flash_info[BOOT_FLASH_INDEX], (sector_count-1), (sector_count-1)); + + printf("Copy to Flash... "); + + flash_write ( (char *)(CFG_LOAD_ADDR + CFG_MONITOR_IMAGE_OFFSET), from, sector_size); + + printf("done\nProtecting 0x%X to 0x%X\n", from, to); + flash_protect (FLAG_PROTECT_SET, from, to, &flash_info[BOOT_FLASH_INDEX]); + + return 1; +} + +U_BOOT_CMD( + bbrom, 2, 1, spi_burn_bootrom_cmd, + "bbrom - Upgrade the BootROM image on the SPI Flash.\n", + " file-name \n" + "\tBurn a binary BootrOM image on the SPI Flash. Must provide image file name as a parameter.\n" +); +#endif +#endif /*0*/ + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_ENV_IS_IN_NAND) + int ret = 0; + nand_erase_options_t nand_erase_options; + size_t offset = 0; + + +#if defined(CONFIG_SKIP_BAD_BLOCK) + int i = 0; + size_t blocksize; + blocksize = nand_info[0].erasesize; + while(i * blocksize < nand_info[0].size) { + if (!nand_block_isbad(&nand_info[0], offset)) + offset += blocksize; + if (offset >= CONFIG_ENV_OFFSET) + break; + i++; + } +#else + offset = CONFIG_ENV_OFFSET; +#endif + nand_erase_options.length = CONFIG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + nand_erase_options.offset = offset; + + puts ("Erasing Nand:\n"); + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + return 1; + puts ("[Done]\n"); +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + u32 sector = 1; + + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { + sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; + if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) + sector++; + } + + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + sector * CONFIG_ENV_SECT_SIZE); + if (spi_flash_erase(flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) + return 1; + puts("\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + +#endif + printf("Warning: Default Environment Variables will take effect Only after RESET\n"); + return 0; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - earse environment sector to reset all variables to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_ddr.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_ddr.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_ddr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_ddr.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,64 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include "ddr2_3/mvDramIf.h" + +int ddr_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvDdrPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + ddrPhyRead, 3, 3, ddr_phy_read_cmd, + "ddrPhyRead - Read DDR PHY register\n", + " \n" + "\t - register number in the PHY\n" + "\t - PuP number in the PHY\n" + +); + +int ddr_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvDdrPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + ddrPhyWrite, 4, 4, ddr_phy_write_cmd, + "ddrPhyWrite - Write DDR PHY register\n", + " \n" + "\t - register number in the PHY\n" + "\t - PuP number in the PHY\n" + "\t - the new register value to write\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_pcie.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_pcie.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_pcie.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_pcie.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,60 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include "pci-if/mvPciIf.h" + +int pcie_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvPexPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + pciePhyRead, 3, 3, pcie_phy_read_cmd, + "phyRead - Read PCI-E Phy register\n", + " PCI-E_interface Phy_offset. \n" + "\tRead the PCI-E Phy register. \n" +); + +int pcie_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvPexPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + pciePhyWrite, 4, 4, pcie_phy_write_cmd, + "pciePhyWrite - Write PCI-E Phy register\n", + " PCI-E_interface Phy_offset value.\n" + "\tWrite to the PCI-E Phy register.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_resetenv.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_resetenv.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_resetenv.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_resetenv.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +extern nand_info_t nand_info[]; /* info for NAND chips */ +#endif + +#ifdef CONFIG_CMD_SF +#include +extern struct spi_flash *flash; +#endif + + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_ENV_IS_IN_NAND) + int ret = 0; + nand_erase_options_t nand_erase_options; + size_t offset = 0; + + +#if defined(CONFIG_SKIP_BAD_BLOCK) + int i = 0; + size_t blocksize; + blocksize = nand_info[0].erasesize; + while(i * blocksize < nand_info[0].size) { + if (!nand_block_isbad(&nand_info[0], offset)) + offset += blocksize; + if (offset >= CONFIG_ENV_OFFSET) + break; + i++; + } +#else + offset = CONFIG_ENV_OFFSET; +#endif + nand_erase_options.length = CONFIG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + nand_erase_options.offset = offset; + + puts ("Erasing Nand:\n"); + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + return 1; + puts ("[Done]\n"); +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + u32 sector = 1; + + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { + sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; + if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) + sector++; + } + + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + sector * CONFIG_ENV_SECT_SIZE); + if (spi_flash_erase(flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) + return 1; + puts("\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + +#endif + printf("Warning: Default Environment Variables will take effect Only after RESET\n"); + return 0; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - earse environment sector to reset all variables to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_sar.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_sar.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_sar.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_sar.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,336 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#if defined(CONFIG_CMD_SAR) +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +extern MV_BIOS_MODE bios_modes[BIOS_MODES_NUM]; + +#define FREQ_MODES_NUM 6 + +typedef struct { + char *name; + MV_U8 cpuFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreq; + MV_U8 fabricFreqMode; +} MV_FREQ_MODE; + +MV_FREQ_MODE freq_modes[FREQ_MODES_NUM] = { +/* Freq Conf CPU Freq CPUFreqMode Fabric Freq FabricFreqMode */ +/* 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] */ + {"800 / 400 Mhz", 0x2, 0x1, 0x1, 0x0}, + {"1066 / 533 Mhz", 0x1, 0x0, 0x1, 0x0}, + {"1200 / 600 Mhz", 0x2, 0x0, 0x5, 0x0}, + {"1333 / 667 Mhz", 0x3, 0x0, 0x5, 0x0}, + {"1600 / 800 Mhz", 0x5, 0x0, 0x5, 0x0}, + {"667 / 667 Mhz", 0x1, 0x1, 0x3, 0x1} +}; + +static int do_sar_list(int argc, char *argv[]) +{ + const char *cmd; + int i; + + if (argc < 1) + goto usage; + cmd = argv[0]; + + if (strcmp(cmd, "cpufreq") == 0) { + + printf("Determines the frequency of CPU:\n"); + printf("\t0x0 = 1000Mhz\n"); + printf("\t0x1 = 1066Mhz\n"); + printf("\t0x2 = 1200Mhz\n"); + printf("\t0x3 = 1333Mhz\n"); + printf("\t0x4 = 1500Mhz\n"); + printf("\t0x5 = 1666Mhz\n"); + printf("\t0x6 = 1800Mhz\n"); + printf("\t0x7 = 2000Mhz\n"); + + } else if (strcmp(cmd, "fabfreq") == 0) { + + printf("Determines the ratios between PCLK0, XPCLK, HCLK and DRAM clock.\n"); + printf("For full deatails about the various options please refer to the clocking section in the HW spec.\n"); + + } else if (strcmp(cmd, "l2size") == 0) { + + printf("Determines the amount of L2 cache:\n"); + printf("\t0x0 = 0.5MB\n"); + printf("\t0x1 = 1MB\n"); + printf("\t0x2 = 0MB\n"); + printf("\t0x3 = 2MB\n"); + + } else if (strcmp(cmd, "bootsrc") == 0) { + + printf("Determines the Boot source device:\n"); + printf("\t0x0 = NOR\n"); + printf("\t0x1 = NAND\n"); + /*printf("\t0x2 = UART\n");*/ + printf("\t0x3 = SPI\n"); + printf("\t0x4 = PCI-E\n"); + printf("\t0x5 = SATA\n"); + /* printf("\t0x6 = NAND (legacy)\n"); + printf("\t0x7 = Debug prompt\n");*/ + + } else if (strcmp(cmd, "bootwidth") == 0) { + + printf("Determines the Boot device width:\n"); + printf("\t0x0 = 8bit\n"); + printf("\t0x1 = 16bit\n"); + printf("\t0x2 = 32bit\n"); + printf("\t0x3 = Reserved\n"); + + } else if (strcmp(cmd, "cpu0core") == 0) { + + printf("Determines the CPU core mode:\n"); + printf("\t0x0 = ARMv6 UP\n"); + printf("\t0x1 = ARMv7 UP\n"); + printf("\t0x2 = ARMv6 MP\n"); + printf("\t0x3 = ARMv7 MP\n"); + + } else if (strcmp(cmd, "cpusnum") == 0) { + + printf("Determines the number of CPU cores:\n"); + printf("\t0x0 = Single CPU\n"); + printf("\t0x1 = Dual CPU\n"); + printf("\t0x2 = Reserved\n"); + printf("\t0x3 = Quad CPU\n"); + + } else if (strcmp(cmd, "freq") == 0) { + printf("val Freq Conf CPU Freq CPUFreqMode Fabric Freq\n"); + printf(" 0x4d/[4:2] 0x4e[0] 0x4e/[4:1]\n"); + for (i=0; i=FREQ_MODES_NUM)) { + printf("invalid mode %d\n", mode); + goto write_fail; + } + + if (mvBoardCpuFreqSet(freq_modes[mode].cpuFreq) != MV_OK) + goto write_fail; + if (mvBoardCpuFreqModeSet(freq_modes[mode].cpuFreqMode) != MV_OK) + goto write_fail; + if (mvBoardFabFreqSet(freq_modes[mode].fabricFreq) != MV_OK) + goto write_fail; + if (mvBoardFabFreqModeSet(freq_modes[mode].fabricFreqMode) != MV_OK) + goto write_fail; + } + + return 0; + +write_fail: + printf("Write S@R failed!\n"); + return 1; + +usage: + printf("Usage: SatR write [options] (see help) \n", argv[0]); + return 1; +} + +int do_sar(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + MV_U8 freq; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "list") == 0) + return do_sar_list(argc - 2, argv + 2); + else if (strcmp(cmd, "write") == 0) { + + if (do_sar_write(argc - 2, argv + 2) == 0) + do_sar_read(argc - 2, argv + 2); + return 0; + + } else if (strcmp(cmd, "read") == 0) + return do_sar_read(argc - 2, argv + 2); + +usage: + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD(SatR, 6, 1, do_sar, + "Sample At Reset sub-system\n", + + "SatR list cpufreq - prints the S@R modes list\n" + "SatR list fabfreq - prints the S@R modes list\n" + "SatR list l2size - prints the S@R modes list\n" + "SatR list bootsrc - prints the S@R modes list\n" + "SatR list bootwidth - prints the S@R modes list\n" + "SatR list cpu0core - prints the S@R modes list\n" + "SatR list cpusnum - prints the S@R modes list\n" + "SatR list freq - prints the S@R modes list\n" + + "SatR read cpufreq - read and print the CPU frequency S@R value\n" + "SatR read fabfreq - read and print the Fabric frequency S@R value\n" + "SatR read l2size - read and print the L2 cache size S@R value\n" + "SatR read bootsrc - read and print the Boot source S@R value\n" + "SatR read bootwidthc - read and print the Boot device width S@R value\n" + "SatR read cpu0core - read and print the CPU0 core mode S@R value\n" + "SatR read cpusnum - read and print the number of CPU cores S@R value\n" + "SatR read freq - read and print the mode of cpu/ddr freq S@R value\n" + + "SatR write cpufreq - write the S@R with CPU frequency value\n" + "SatR write fabfreq - write the S@R with Fabric frequency value\n" + "SatR write l2size - write the S@R with L2 cache size value\n" + "SatR write bootsrc - write the S@R with Boot source value\n" + "SatR write bootwidth - write the S@R with Boot device width value\n" + "SatR write cpu0core - write the S@R with CPU0 core mode value\n" + "SatR write cpusnum - write the S@R with the number of CPU cores\n" + "SatR write freq - write the S@R with the cpu/ddr freq mode\n" + +); +#endif /*defined(CONFIG_CMD_SAR)*/ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,45 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCesaConfig.h - Marvell Cesa unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for cesa registers. +*/ +#define OLD_CESA_HAL + +#if defined OLD_CESA_HAL +#warning "Working with old CESA HAL (one channel only!)" +#define MV_CESA_REGS_BASE (MV_CESA_REGS_OFFSET(0)) +#define MV_CESA_TDMA_REGS_BASE (MV_CESA_TDMA_REGS_OFFSET(0)) +#else +#define MV_CESA_TDMA_REGS_BASE(port) (MV_CESA_TDMA_REGS_OFFSET(port)) +#define MV_CESA_REGS_BASE(port) (MV_CESA_REGS_OFFSET(port)) +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCntmrConfig.h - Marvell Counter Manager unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for counter manager registers. +*/ +#define MV_CNTMR_REGS_BASE (MV_CNTMR_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,43 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysDdrConfig.h - Marvell DRAM controller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for DDR registers. +*/ +#define MV_DDR_REGS_BASE (MV_DRAM_REGS_OFFSET) +#define MV_DDR_WIN_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_DDR_CTRL_REGS_BASE (MV_DRAM_REGS_OFFSET) + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,161 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthConfig.h - Marvell Ethernet unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvSysEthConfig_h__ +#define __mvSysEthConfig_h__ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* u-boot is running in legacy mode! */ +#define MV_ETH_LEGACY +#define MV_LEGACY_ETH_WA +#define CONFIG_MV_ETH_LEGACY + +/* +** Base address for ethernet registers. +*/ +#ifdef CONFIG_MV_PON +#define MV_PON_PORT(p) ((p) == MV_PON_PORT_ID) +#define MV_PON_REG_BASE MV_PON_REGS_OFFSET +#define MV_ETH_REGS_BASE(p) (MV_PON_PORT(p) ? MV_PON_REGS_OFFSET : MV_ETH_REGS_OFFSET(p)) +#else +#define MV_PON_PORT(p) MV_FALSE +#define MV_ETH_REGS_BASE(p) MV_ETH_REGS_OFFSET(p) +#endif /* CONFIG_MV_PON */ + +#define MV_BM_REG_BASE MV_BM_REGS_OFFSET +#define MV_PNC_REG_BASE MV_PNC_REGS_OFFSET +#define MV_ETH_COMPLEX_BASE (MV_ETH_COMPLEX_OFFSET) +#define MV_ETH_ONLY_REGS_BASE (MV_ETH_ONLY_REGS_OFFSET) + +#if defined(CONFIG_MV_INCLUDE_GIG_ETH) + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* port's default queueus */ +#define ETH_DEF_RXQ 0 + +#ifdef MV_ETH_LEGACY + +#ifdef MV_NFP_STATS +#define MV_FP_STATISTICS +#else +#undef MV_FP_STATISTICS +#endif + +/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ +#define MV_ETH_TX_EN_DEFAULT 0 + +/* un-comment if you want to perform tx_done from within the poll function */ +/* #define ETH_TX_DONE_ISR */ + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* Descriptors location: DRAM/internal-SRAM */ +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ + +#if defined(ETH_DESCR_IN_SRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" +#endif +#elif defined(ETH_DESCR_IN_SDRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" +#endif +#else + #error "Ethernet descriptors location undefined" +#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ + +/* SW Sync-Barrier: not relevant for 88fxx81*/ +/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ +/* In RX the CPU theoretically might see himself as the descriptor owner, */ +/* although the buffer hadn't been written to DRAM yet. Performance cost. */ +/* #define INCLUDE_SYNC_BARR */ + +/* Buffers cache coherency method (buffers in DRAM) */ +#ifndef MV_CACHE_COHER_SW +/* Taken from mvCommon.h */ +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +#endif + +#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) + #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "DRAM uncached" +#else + #error "Ethernet-DRAM undefined" +#endif /* ETHER_DRAM_COHER */ + + +/****************************************************************/ +/************* Ethernet driver configuration ********************/ +/****************************************************************/ + +/* port's default queueus */ +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 + +#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RXQ +#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TXQ + +/* interrupt coalescing setting */ +#define ETH_TX_COAL 200 +#define ETH_RX_COAL 200 + +/* Checksum offloading */ +#define TX_CSUM_OFFLOAD +#define RX_CSUM_OFFLOAD +#endif /* CONFIG_MV_ETH_LEGACY */ + +#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ + +#endif /* __mvSysEthConfig_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,32 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthPhyConfig.h - Marvell Ethernet-PHY specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysGppConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysGppConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysGppConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysGppConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysGppConfig.h - Marvell GPP unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for GPP registers. +*/ +#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) +#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysHwConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysHwConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysHwConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysHwConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,455 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + +#include + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#undef MV_MEM_OVER_PEX_WA + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_GIG_ETH +//#define MV_INCLUDE_CESA +#define OLD_CESA_HAL +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI +#define MV_INCLUDE_TDM +#define MV_INCLUDE_XOR +#define MV_INCLUDE_SATA +//#define MV_INCLUDE_TS +//#define MV_INCLUDE_AUDIO +#define MV_INCLUDE_SDIO +#define MV_INCLUDE_RTC +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_CLK_PWR_CNTRL + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/************************************************/ +/* U-Boot Specific */ +/************************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#endif + + +/************************************************/ +/* RD boards specifics */ +/************************************************/ + +#undef MV_INC_BOARD_DDIM + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif + +#if defined(RD_88F6281) +#define MV_INC_BOARD_QD_SWITCH +#endif + +#if defined(RD_88F6180) +#define MV_INC_BOARD_QD_SWITCH +#endif +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX 0.0 */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xe0000000 +#define PEX0_IO_SIZE _16M + +/* PEX 0.1 */ +#define PEX1_MEM_BASE 0x98000000 +#define PEX1_MEM_SIZE _128M + +#define PEX1_IO_BASE 0xe1000000 +#define PEX1_IO_SIZE _16M + +/* PEX 0.2 */ +#define PEX2_MEM_BASE 0xa0000000 +#define PEX2_MEM_SIZE _128M + +#define PEX2_IO_BASE 0xe2000000 +#define PEX2_IO_SIZE _16M + +/* PEX 0.3 */ +#define PEX3_MEM_BASE 0xa8000000 +#define PEX3_MEM_SIZE _128M + +#define PEX3_IO_BASE 0xe3000000 +#define PEX3_IO_SIZE _16M + +/* PEX 1.0 */ +#define PEX4_MEM_BASE 0xb0000000 +#define PEX4_MEM_SIZE _128M + +#define PEX4_IO_BASE 0xe4000000 +#define PEX4_IO_SIZE _16M + +/* PEX 1.1 */ +/* TODO: alior: still need to work on this PEX interface */ +#define PEX5_MEM_BASE 0xFFFFFFFF +#define PEX5_MEM_SIZE _128M + +#define PEX5_IO_BASE 0xe5000000 +#define PEX5_IO_SIZE _16M + +/* PEX 1.2 */ +#define PEX6_MEM_BASE 0xb8000000 +#define PEX6_MEM_SIZE _128M + +#define PEX6_IO_BASE 0xe6000000 +#define PEX6_IO_SIZE _16M + +/* PEX 1.3 */ +/* TODO: alior: still need to work on this PEX interface */ +#define PEX7_MEM_BASE 0xFFFFFFFF +#define PEX7_MEM_SIZE _128M + +#define PEX7_IO_BASE 0xe7000000 +#define PEX7_IO_SIZE _16M + +/* PEX 2 */ +#define PEX8_MEM_BASE 0xc0000000 +#define PEX8_MEM_SIZE _128M + +#define PEX8_IO_BASE 0xe8000000 +#define PEX8_IO_SIZE _16M + +/* PEX 3 */ +#define PEX9_MEM_BASE 0xd8000000 +#define PEX9_MEM_SIZE _128M + +#define PEX9_IO_BASE 0xe9000000 +#define PEX9_IO_SIZE _16M + +/* Device: CS0 - NAND, CS1 - SPI, CS2 - Boot ROM, CS3 - Boot device */ +/* Internal registers: size is defined in Controllerenvironment */ + +//#define INTER_REGS_BASE 0xF1000000 +#define INTER_REGS_BASE 0xD0000000 +#define ARMADAXP_SB_REGS_PHYS_BASE INTER_REGS_BASE + +#define DEVICE_CS0_BASE NFLASH_CS_BASE +#define DEVICE_CS0_SIZE NFLASH_CS_SIZE + +#define DEVICE_CS2_BASE 0xf2000000 /* 0xf4000000 */ +#define DEVICE_CS2_SIZE _1M + +#define PNC_BM_PHYS_BASE 0xf2100000 /*0xF5000000*/ +#define PNC_BM_SIZE _1M + +#define CRYPT_ENG_BASE 0xc8010000 +//fb300000 /*0xFB000000*/ +#define CRYPT_ENG_SIZE _64K + +#define SPI_CS_BASE 0xf4000000 /*0xf8000000*/ +#define SPI_CS_SIZE _16M + +#define DEVICE_CS1_BASE SPI_CS_BASE +#define DEVICE_CS1_SIZE _16M + + +#define NFLASH_CS_BASE 0xfd000000 /* not relevant for the new controller */ +#define NFLASH_CS_SIZE _2M + +#define NOR_CS_BASE 0xf8000000 /*0x80000000*/ +#define NOR_CS_SIZE _128M + + + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +#if !defined(MV_BOOTROM) && defined(MV_NAND_BOOT) +#define CONFIG_SYS_NAND_BASE BOOTDEV_CS_BASE +#else +#define CONFIG_SYS_NAND_BASE DEVICE_CS0_BASE +#endif + + + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE +#endif + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ +#define L2CLK_AUTO_DETECT /* Use L2 Clk auto detection */ + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" +#endif /* ETHER_DRAM_COHER */ + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ + /* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE, 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS0 */ \ + {{SDRAM_CS1_BASE, 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS1 */ \ + {{SDRAM_CS2_BASE, 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS2 */ \ + {{SDRAM_CS3_BASE, 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS3 */ \ + {{NOR_CS_BASE, 0, NOR_CS_SIZE }, TBL_UNUSED, DIS}, /* DEVICE_CS0 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS1 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS2 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS3 */\ + {{PEX0_MEM_BASE, 0, PEX0_MEM_SIZE }, 0, EN}, /* PEX0_MEM */ \ + {{PEX0_IO_BASE, 0, PEX0_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX0_IO */ \ + {{PEX1_MEM_BASE, 0, PEX1_MEM_SIZE }, 1, EN}, /* PEX1_MEM */ \ + {{PEX1_IO_BASE, 0, PEX1_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX1_IO */ \ + {{PEX2_MEM_BASE, 0, PEX2_MEM_SIZE }, 2, EN}, /* PEX2_MEM */ \ + {{PEX2_IO_BASE, 0, PEX2_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX2_IO */ \ + {{PEX3_MEM_BASE, 0, PEX3_MEM_SIZE }, 3, EN}, /* PEX3_MEM */ \ + {{PEX3_IO_BASE, 0, PEX3_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX3_IO */ \ + {{PEX4_MEM_BASE, 0, PEX4_MEM_SIZE }, 4, EN}, /* PEX4_MEM */ \ + {{PEX4_IO_BASE, 0, PEX4_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX4_IO */ \ + {{PEX5_MEM_BASE, 0, PEX5_MEM_SIZE }, TBL_UNUSED, DIS}, /* PEX5_MEM */ \ + {{PEX5_IO_BASE, 0, PEX5_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX5_IO */ \ + {{PEX6_MEM_BASE, 0, PEX6_MEM_SIZE }, 5, EN}, /* PEX6_MEM */ \ + {{PEX6_IO_BASE, 0, PEX6_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX6_IO */ \ + {{PEX7_MEM_BASE, 0, PEX7_MEM_SIZE }, TBL_UNUSED, DIS}, /* PEX7_MEM */ \ + {{PEX7_IO_BASE, 0, PEX7_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX7_IO */ \ + {{PEX8_MEM_BASE, 0, PEX8_MEM_SIZE }, 6, EN}, /* PEX8_MEM */ \ + {{PEX8_IO_BASE, 0, PEX8_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX8_IO */ \ + {{PEX9_MEM_BASE, 0, PEX9_MEM_SIZE }, 7, EN}, /* PEX9_MEM */ \ + {{PEX9_IO_BASE, 0, PEX9_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX9_IO */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, MV_AHB_TO_MBUS_INTREG_WIN, EN}, /* INTER_REGS */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DMA_UART */\ + {{SPI_CS_BASE, 0, SPI_CS_SIZE }, 8, EN}, /* SPI_CS0 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS1 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS2 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS3 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS4 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS5 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS6 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS7 */ \ + {{0xf8000000, 0, _1M }, 13, EN}, /* BOOT_ROM_CS */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEV_BOOCS */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* PMU_SCRATCHPAD */ \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE }, 9, EN}, /* CRYPT_ENG */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM }, TBL_TERM, TBL_TERM} \ +}; +#if 0 +{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE }, 0x4, DIS}, /* DEV_BOOCS */ +{{PNC_BM_PHYS_BASE, 0, PNC_BM_SIZE }, 3, DIS}, /* PNC_BM */ */ +#endif + +#define MV_CACHEABLE(address) ((address) | 0x80000000) + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + + +#if defined(MV_BOOTSIZE_256K) + +#define BOOTDEV_CS_SIZE _256K + +#elif defined(MV_BOOTSIZE_512K) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_4M) + +#define BOOTDEV_CS_SIZE _4M + +#elif defined(MV_BOOTSIZE_8M) + +#define BOOTDEV_CS_SIZE _8M + +#elif defined(MV_BOOTSIZE_16M) + +#define BOOTDEV_CS_SIZE _16M + +#elif defined(MV_BOOTSIZE_32M) + +#define BOOTDEV_CS_SIZE _32M + +#elif defined(MV_BOOTSIZE_64M) + +#define BOOTDEV_CS_SIZE _64M + +#elif defined(MV_NAND_BOOT) + +#define BOOTDEV_CS_SIZE _512K + +#else + +#define Error MV_BOOTSIZE undefined + +#endif + +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x30820 /* sdram config */ +#define DRAM_BUF_REG2 0x30830 /* sdram mode */ +#define DRAM_BUF_REG3 0x60bb0 /* dunit control low */ +#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ +#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ +#define DRAM_BUF_REG12 0x60bb4 /* sdram Ddr2 Time High Reg */ +#define DRAM_BUF_REG13 0x60ab0 /* dunit Ctrl High */ +#define DRAM_BUF_REG14 0x60ab4 /* sdram second DIMM exist */ + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG_DV 0 + +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 +#define MV_ETH_TX_Q_NUM 1 +#define MV_ETH_RX_Q_NUM 1 +#define ETH_NUM_OF_RX_DESCR 64 +#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2 + +#define MV_CESA_MAX_BUF_SIZE 1600 + +#endif /* __INCmvSysHwConfigh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysNfcConfig.h - Marvell NAND flash conroller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Nand Controller registers. +*/ +#define MV_NFC_REGS_BASE (MV_NFC_REGS_OFFSET + INTER_REGS_BASE) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,68 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysPciIfConfig.h - Marvell PCI / Pex units specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE +#endif + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPexConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPexConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPexConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPexConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,68 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysPciIfConfig.h - Marvell PCI / Pex units specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE +#endif + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysRtcConfig.h - Marvell Real-Time clock unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for RTC registers. +*/ +#define MV_RTC_REGS_BASE (MV_RTC_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSataConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSataConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSataConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSataConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSataConfig.h - Marvell Sata unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SATA_REGS_BASE (MV_SATA_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSdmmcConfig.h - Marvell SDMMC unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for audio registers. +*/ +#define MV_SDMMC_REGS_BASE (MV_SDMMC_REGS_OFFSET) + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSpiConfig.h - Marvell SPI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SPI_REGS_BASE(unit) (MV_SPI_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTdmConfig.h - Marvell TDM unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvOs.h" + +/****************************************************************/ +/*************** Telephony configuration ************************/ +/****************************************************************/ +/* U-Boot support*/ +#define MV_TDM_SUPPORT +//undef MV_TDM_SUPPORT for 32ch unit support (COMM unit) +#if defined(CONFIG_MV_TDM_SUPPORT) + #define MV_TDM_SUPPORT + #define MV_TDM_REGS_BASE MV_TDM_REGS_OFFSET +#elif defined(CONFIG_MV_COMM_UNIT_SUPPORT) + #define MV_COMM_UNIT_SUPPORT + #define MV_COMM_UNIT_REGS_BASE MV_COMM_UNIT_REGS_OFFSET +#endif + +/* SLIC vendor */ +#if defined(CONFIG_SILABS_SLIC_SUPPORT) + #define SILABS_SLIC_SUPPORT + #if defined(CONFIG_SILABS_SLIC_3215) + #define SILABS_SLIC_3215 + #elif defined(CONFIG_SILABS_SLIC_3217) + #define SILABS_SLIC_3217 + #endif +#elif defined(CONFIG_ZARLINK_SLIC_SUPPORT) + #define ZARLINK_SLIC_SUPPORT + #if defined(CONFIG_ZARLINK_SLIC_VE880) + #define ZARLINK_SLIC_VE880 + #define SLIC_TIMER_EVENT_SUPPORT + #elif defined(CONFIG_ZARLINK_SLIC_VE792) + #define ZARLINK_SLIC_VE792 + #endif +#else + #define SILABS_SLIC_3215_OLD_SUPPORT +#endif + +#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) + #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTsConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTsConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTsConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTsConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,39 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTsConfig.h - Marvell TS unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for TS registers. +*/ +#define MV_TSU_GLOBAL_REGS_BASE (MV_TSU_GLOBAL_REGS_OFFSET) +#define MV_TSU_REGS_BASE(port) (MV_TSU_REGS_OFFSET(port)) + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,41 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTwsiConfig.h - Marvell TWSI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +/* +** Base address for TWSI registers. +*/ +#define MV_TWSI_SLAVE_REGS_BASE(unit) (MV_TWSI_SLAVE_REGS_OFFSET(unit)) + +/* +** Specific definition for Main CPU interrupt cause register. +** Needed for TWSI operation completion monitoring. +*/ +#define MV_TWSI_CPU_MAIN_INT_CASUE(chNum) TWSI_CPU_MAIN_INT_CAUSE_REG diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysUsbConfig.h - Marvell USB unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for USB registers. +*/ +#define MV_USB_REGS_BASE(unit) (MV_USB_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysXorConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysXorConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysXorConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysXorConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysXorConfig.h - Marvell XOR unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for XOR registers. +*/ +#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_cmd.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_cmd.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_cmd.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_cmd.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,2235 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#if defined(MV_INC_BOARD_NOR_FLASH) +#include "norflash/mvFlash.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#include "eth-phy/mvEthPhy.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +#if defined(MV_INCLUDE_PDMA) +#include "pdma/mvPdma.h" +#include "mvSysPdmaApi.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXorRegs.h" +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_PMU) +#include "pmu/mvPmuRegs.h" +#endif + +#include "cntmr/mvCntmrRegs.h" + +#if defined(CONFIG_CMD_BSP) + +/****************************************************************************** +* Category - General +* Functionality- The commands allows the user to view the contents of the MV +* internal registers and modify them. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int ir_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_U32 regNum = 0x0, regVal, regValTmp, res; + MV_8 regValBin[40]; + MV_8 cmd[40]; + int i,j = 0, flagm = 0; + extern MV_8 console_buffer[]; + + if( argc == 2 ) { + regNum = simple_strtoul( argv[1], NULL, 16 ); + } + else { + printf( "Usage:\n%s\n", cmdtp->usage ); + return 0; + } + + regVal = MV_REG_READ( regNum + INTER_REGS_BASE); + regValTmp = regVal; + printf( "Internal register 0x%x value : 0x%x\n ",regNum, regVal ); + printf( "\n 31 24 16 8 0" ); + printf( "\n | | | | |\nOLD: " ); + + for( i = 31 ; i >= 0 ; i-- ) { + if( regValTmp > 0 ) { + res = regValTmp % 2; + regValTmp = (regValTmp - res) / 2; + if( res == 0 ) + regValBin[i] = '0'; + else + regValBin[i] = '1'; + } + else + regValBin[i] = '0'; + } + + for( i = 0 ; i < 32 ; i++ ) { + printf( "%c", regValBin[i] ); + if( (((i+1) % 4) == 0) && (i > 1) && (i < 31) ) + printf( "-" ); + } + + readline( "\nNEW: " ); + strcpy(cmd, console_buffer); + if( (cmd[0] == '0') && (cmd[1] == 'x') ) { + regVal = simple_strtoul( cmd, NULL, 16 ); + flagm=1; + } + else { + for( i = 0 ; i < 40 ; i++ ) { + if(cmd[i] == '\0') + break; + if( i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34 ) + continue; + if( cmd[i] == '1' ) { + regVal = regVal | (0x80000000 >> j); + flagm = 1; + } + else if( cmd[i] == '0' ) { + regVal = regVal & (~(0x80000000 >> j)); + flagm = 1; + } + j++; + } + } + + if( flagm == 1 ) { + MV_REG_WRITE( regNum + INTER_REGS_BASE, regVal ); + printf( "\nNew value = 0x%x\n\n", MV_REG_READ(regNum + + INTER_REGS_BASE) ); + } + return 1; +} + +U_BOOT_CMD( + ir, 2, 1, ir_cmd, + "ir - reading and changing MV internal register values.\n", + " address\n" + "\tDisplays the contents of the internal register in 2 forms, hex and binary.\n" + "\tIt's possible to change the value by writing a hex value beginning with \n" + "\t0x or by writing 0 or 1 in the required place. \n" + "\tPressing enter without any value keeps the value unchanged.\n" +); + +#if defined(MV_INCLUDE_PMU) +/****************************************************************************** +* Category - General +* Functionality- Display temperature from sensor. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int temperature_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 reg = 0, reg1 = 0; + MV_U32 value = 0; + int i = 0; + + /* Verify that the temperature is valid */ + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL1_REG); + if ((reg & PMU_TDC1_TEMP_VLID_MASK) == 0x0) + { + printf("Error reading temperature\n"); + } + else + { + for (i = 0; i < 16; i++) + { + /* Read the thermal sensor looking for two successive readings that differ in LSB only */ + reg = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg = ((reg >> 1) & 0x1FF); + value = ((2281638 - (7298*reg)) / 10000); + if (((reg ^ reg1) & 0x1FE) == 0x0) + break; + + /* save the current reading for the next iteration */ + reg1 = reg; + } + if (i == 16) + printf("Thermal sensor is unstable: could not get two identical successive readings\n"); + else + printf("Junction Temprature (Tj) = %d, Register Value = 0x%08X\n", value, reg); + } + return 1; +} + +U_BOOT_CMD( + temp, 1, 1, temperature_cmd, + "temp - Display the device temprature.\n", + " \n" + "\tDisplay the device temprature as read from the internal sensor.\n" +); +/****************************************************************************** +* Category - General +* Functionality- Display temperature from sensor. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int volt_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 reg = 0, reg1 = 0; + MV_U32 value = 0; + int i = 0; + char *cmd, *s; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strncmp(cmd, "cpu", 3) != 0 && strncmp(cmd, "core", 4) != 0) + goto usage; + + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg |= PMU_TDC0_SEL_IP_MODE_MASK; + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, PMU_TDC0_SEL_IP_MODE_MASK); + + if (strncmp(cmd, "cpu", 3) == 0) { + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg &= ~(PMU_TDC0_SEL_VSEN_MASK); + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, reg); + } + if (strncmp(cmd, "core", 3) == 0) { + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg |= PMU_TDC0_SEL_VSEN_MASK; + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, reg); + } + udelay(1000); + /* Verify that the temperature is valid */ + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL1_REG); + if ((reg & PMU_TDC1_TEMP_VLID_MASK) == 0x0) + { + printf("Error reading voltage\n"); + } + else + { + reg1 = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg1 = ((reg1 >> 1) & 0x1FF); + for (i = 0; i < 16; i++) + { + /* Read the thermal sensor looking for two successive readings that differ in LSB only */ + reg = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg = ((reg >> 1) & 0x1FF); + if (((reg ^ reg1) & 0x1FE) == 0x0) + break; + /* save the current reading for the next iteration */ + reg1 = reg; + } + value = ((reg + 241)*10000/39619); + if (i == 16) + printf("Voltage sensor is unstable: could not get two identical successive readings\n"); + else + printf("Voltage (V) = %d.%d, Register Value = 0x%08X\n", value/100, value%100, reg); + } + return 0; +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + volt, 2, 1, volt_cmd, + "volt - Display the cpu / core voltage.\n", + "volt cpu - display the cpu voltage\n" + "volt core - display the core voltage\n" +); +#endif /* #if defined(MV_INCLUDE_PMU) */ + +/****************************************************************************** +* Functional only when using Lauterbach to load image into DRAM +* Category - DEBUG +* Functionality- Display the array of registers the u-boot write to. +* +*****************************************************************************/ +#if defined(REG_DEBUG) +int reg_arry[4096][2]; +int reg_arry_index = 0; +int print_registers( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + printf("Register display\n"); + + for (i=0; i < reg_arry_index; i++) + printf("Reg no %d addr 0x%x = 0x%08x\n", i, reg_arry[i][0], reg_arry[i][1]); + + return 1; +} + +U_BOOT_CMD( + printreg, 1, 1, print_registers, + "printreg - Display the register array the u-boot write to.\n", + " \n" + "\tDisplay the register array the u-boot write to.\n" +); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int sg_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 port; + for( port = 0 ; port < mvCtrlEthMaxPortGet(); port++ ) { + + printf( "PHY %d :\n", port ); + printf( "---------\n" ); + + mvEthPhyPrintStatus( mvBoardPhyAddrGet(port) ); + + printf("\n"); + } + return 1; +} + +U_BOOT_CMD( + sg, 1, 1, sg_cmd, + "sg - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif /* #if defined(MV_INCLUDE_GIG_ETH) */ + +#if defined(MV_INCLUDE_PDMA) + +/****************************************************************************** +* Category - PDMA +* Functionality- Perform a PDMA transaction +* Need modifications (Yes/No) - No +*****************************************************************************/ +int mvPdma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20]; + extern MV_8 console_buffer[]; + MV_U32 src, dst, byteCount; + MV_PDMA_CHANNEL chan; + + /* get PDMA channel */ + + /* source address */ + while(1) { + readline( "Source Address: " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if( src == 0xffffffff ) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Destination Address: " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if( dst == 0xffffffff ) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to 8KByte (0 - 0x1FFF)): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount >= 0x2000) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + if (mvPdmaChanAlloc(MV_PDMA_MEMORY, 0, &chan) != MV_OK) { + printf("Error allocating PDMA channel\n"); + return 0; + } + /* wait for previous transfer completion */ + while(mvPdmaChannelStateGet(&chan) == MV_PDMA_CHANNEL_RUNNING); + /* issue the transfer */ + if (mvPdmaChanTransfer(&chan, MV_PDMA_MEM_TO_MEM, src, dst, byteCount, 0) != MV_OK) { + printf("Error with PDMA transfer\n"); + } + /* wait for completion */ + while(mvPdmaChannelStateGet(&chan) == MV_PDMA_CHANNEL_RUNNING); + if (mvPdmaChanFree(&chan) != MV_OK) { + printf("Error freeing PDMA channel\n"); + return 0; + } + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + pdma, 1, 1, mvPdma_cmd, + "pdma - Perform PDMA\n", + " \n" + "\tPerform PDMA memory to memory transaction with the parameters given by the user.\n" +); + +#endif /* #if defined(MV_INCLUDE_PDMA) */ + +#if defined(MV_INCLUDE_XOR) + +/****************************************************************************** +* Category - DMA +* Functionality- Perform a DMA transaction using the XOR engine +* Need modifications (Yes/No) - No +*****************************************************************************/ +#define XOR_TIMEOUT 0x8000000 + +struct xor_channel_t +{ + MV_CRC_DMA_DESC *pDescriptor; + MV_ULONG descPhyAddr; +}; + +#define XOR_CAUSE_DONE_MASK(chan) ((BIT0|BIT1) << (chan * 16) ) +void xor_waiton_eng(int chan) +{ + int timeout = 0; + + while(!(MV_REG_READ(XOR_CAUSE_REG(XOR_UNIT(chan))) & XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) + { + if(timeout > XOR_TIMEOUT) + goto timeout; + timeout++; + } + + timeout = 0; + while(mvXorStateGet(chan) != MV_IDLE) + { + if(timeout > XOR_TIMEOUT) + goto timeout; + timeout++; + } + /* Clear int */ + MV_REG_WRITE(XOR_CAUSE_REG(XOR_UNIT(chan)), ~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))); + +timeout: + if(timeout > XOR_TIMEOUT) + { + printf("ERR: XOR eng got timedout!!\n"); + } + return; +} +#if 0 +int mvDma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20]; + extern MV_8 console_buffer[]; + MV_U32 chan, src, dst, byteCount; + struct xor_channel_t channel; + MV_U8 *pVirt = (MV_U8*)mvOsIoUncachedAlignedMalloc(NULL, 32, sizeof(MV_XOR_DESC), + &(channel.descPhyAddr), NULL); + + chan = 0; + + /* source address */ + while(1) { + readline( "Physical Source Address (must be cache-line aligned): " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if ((src == 0xffffffff) || (src & 0x1F)) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Physical Destination Address (must be cache-line aligned): " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if ((dst == 0xffffffff) || (dst & 0x1F)) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to (16M-1), must be a multiple of the cache-line): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount > 0xffffff) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + /* wait for previous transfer completion */ + while (mvXorStateGet(chan) != MV_IDLE); + + /* build the channel descriptor */ + channel.pDescriptor = (MV_CRC_DMA_DESC *)pVirt; + channel.pDescriptor->srcAdd0 = src; + channel.pDescriptor->srcAdd1 = 0; + channel.pDescriptor->destAdd = dst; + channel.pDescriptor->byteCnt = byteCount; + channel.pDescriptor->nextDescPtr = 0; + channel.pDescriptor->status = BIT31; + channel.pDescriptor->descCommand = 0x0; + + /* issue the transfer */ + if (mvXorTransfer(chan, MV_DMA, channel.descPhyAddr) != MV_OK) + printf("Error in DMA(XOR) Operation\n"); + + /* wait for completion */ + xor_waiton_eng(chan); + + mvOsIoUncachedAlignedFree(NULL, sizeof(MV_XOR_DESC), channel.descPhyAddr, pVirt, 0); + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + dma, 1, 1, mvDma_cmd, + "dma - Perform DMA using the XOR engine\n", + " \n" + "\tPerform DMA transaction with the parameters given by the user.\n" +); +#endif +#endif /* #if defined(MV_INCLUDE_XOR) */ + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the MV's Memory map +* Need modifications (Yes/No) - Yes +*****************************************************************************/ +int displayMemoryMap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvCtrlAddrDecShow(); + return 1; +} + +U_BOOT_CMD( + map, 1, 1, displayMemoryMap_cmd, + "map - Diasplay address decode windows\n", + " \n" + "\tDisplay controller address decode windows: CPU, PCI, Gig, DMA, XOR and COMM\n" +); + + + +#include "ddr2/spd/mvSpd.h" +#if defined(MV_INC_BOARD_DDIM) + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the SPD information for a givven dimm +* Need modifications (Yes/No) - +*****************************************************************************/ + +int dimminfo_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int num = 0; + + if (argc > 1) { + num = simple_strtoul (argv[1], NULL, 10); + } + + printf("*********************** DIMM%d *****************************\n",num); + + dimmSpdPrint(num); + + printf("************************************************************\n"); + + return 1; +} + +U_BOOT_CMD( + ddimm, 2, 1, dimminfo_cmd, + "ddimm - Display SPD Dimm Info\n", + " [0/1]\n" + "\tDisplay Dimm 0/1 SPD information.\n" +); + +/****************************************************************************** +* Category - Memory +* Functionality- Copy the SPD information of dimm 0 to dimm 1 +* Need modifications (Yes/No) - +*****************************************************************************/ + +int spdcpy_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + printf("Copy DIMM 0 SPD data into DIMM 1 SPD..."); + + if (MV_OK != dimmSpdCpy()) + printf("\nDIMM SPD copy fail!\n"); + else + printf("Done\n"); + + return 1; +} + +U_BOOT_CMD( + spdcpy, 2, 1, spdcpy_cmd, + "spdcpy - Copy Dimm 0 SPD to Dimm 1 SPD \n", + "" + "" +); +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +/****************************************************************************** +* Functionality- Go to an address and execute the code there and return, +* defualt address is 0x40004 +*****************************************************************************/ +extern void cpu_dcache_flush_all(void); +extern void cpu_icache_flush_invalidate_all(void); + +void mv_go(unsigned long addr,int argc, char *argv[]) +{ + int rc; + addr = MV_CACHEABLE(addr); + char* envCacheMode = getenv("cacheMode"); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + } + else /*"write-back"*/ + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + /* Flush invalidate D-cache */ + cpu_dcache_flush_all(); + + + } + + + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + + return; +} + +int g_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0; + } + + addr = 0x40000; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + mv_go(addr,argc,&argv[0]); + return 1; +} + +U_BOOT_CMD( + g, CONFIG_SYS_MAXARGS, 1, g_cmd, + "g - start application at cached address 'addr'(default addr 0x40000)\n", + " addr [arg ...] \n" + "\tStart application at address 'addr' cachable!!!(default addr 0x40004/0x240004)\n" + "\tpassing 'arg' as arguments\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Searches for a value +*****************************************************************************/ +int fi_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData == value) + { + printf("Value: %x found at ",value); + printf("address: %x\n",i); + return 1; + } + } + printf("Value not found!!\n"); + return 1; +} + +U_BOOT_CMD( + fi, 4, 1, fi_cmd, + "fi - Find value in the memory.\n", + " value start_address end_address\n" + "\tSearch for a value 'value' in the memory from address 'start_address to\n" + "\taddress 'end_address'.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Compare the memory with Value. +*****************************************************************************/ +int cmpm_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData != value) + { + printf("Value: %x found at address: %x\n",tempData,i); + } + } + return 1; +} + +U_BOOT_CMD( + cmpm, 4, 1, cmpm_cmd, + "cmpm - Compare Memory\n", + " value start_address end_address.\n" + "\tCompare the memory from address 'start_address to address 'end_address'.\n" + "\twith value 'value'\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + + +#if 0 +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int eth_show_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ethRegs(argv[1]); + ethPortRegs(argv[1]); + ethPortStatus(argv[1]); + ethPortQueues(argv[1],0,0,1); + return 1; +} + +U_BOOT_CMD( + ethShow, 2, 2, eth_show_cmd, + "ethShow - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) + +#include "eth-phy/mvEthPhy.h" + +int phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + phyRead, 3, 3, phy_read_cmd, + "phyRead - Read Phy register\n", + " Phy_address Phy_offset. \n" + "\tRead the Phy register. \n" +); + + +int phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + phyWrite, 4, 4, phy_write_cmd, + "phyWrite - Write Phy register\n", + " Phy_address Phy_offset value.\n" + "\tWrite to the Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_GIG_ETH) */ + +#endif /* MV_TINY */ + +#if 0 +#if defined(CONFIG_CMD_RCVR) +extern void recoveryHandle(void); +int do_rcvr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + recoveryHandle(); + return 1; +} + +U_BOOT_CMD( + rcvr, 3, 1, do_rcvr, + "rcvr\t- Satrt recovery process (Distress Beacon with TFTP server)\n", + "\n" +); +#endif /* CFG_CMD_RCVR */ +#endif //0 +#if 0 +#include "nfc/mvNfc.h" +#include "mvSysPdmaApi.h" + +int mvNfcEWaitEvent(MV_NFC_CTRL * ctrl, MV_NFC_CMD_TYPE cmd, MV_U32 event, MV_U32 err) +{ + int i; + MV_U32 stat; + + for (i=0; i<10; i++) + { + stat = mvNfcStatusGet(ctrl, cmd, NULL); + //printf("Status = 0x%x, NDCR = %08x\n", stat, MV_REG_READ(0xc0000)); + if (stat & err) + { + printf("mvNfcEWaitEvent Error (%08x)\n", stat); + return -1; + } + if (stat & event) + return 0; + mvOsDelay(10); /*wait 10 ms */ + } + + printf("mvNfcEWaitEvent: Timeout\n"); + return -2; +} + +void mvNfcDataPrint(MV_U32 buff) +{ + MV_U8 * datptr; + MV_U32 i,j; + + datptr = (MV_U8*)buff; + for (i=0; i<128; i+=1) + { + printf("%08x: ", (i*16)); + for (j=0; j<16; j++) + { + printf("%02x ", *datptr); + datptr++; + } + printf("\n"); + } +} + +int mvNfcStatusRead(MV_NFC_CTRL * ctrl, MV_U32 * buff) +{ + if (mvNfcSelectChip(ctrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(ctrl, MV_NFC_CMD_READ_STATUS, 0, 0) != MV_OK) + { + printf("Read status command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(ctrl, MV_NFC_CMD_READ_STATUS, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcReadWrite(ctrl, MV_NFC_CMD_READ_STATUS, buff, (MV_U32)buff) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + if (mvNfcSelectChip(ctrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + return 0; +} + + +MV_U32 mvNfcDbgFlag = 0; +MV_U32 mvNfcPrintFlag = 0; +extern MV_NFC_CTRL * gDbgCtrl; +MV_NFC_CTRL nfcDbgCtrl; + +int mvNfc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 buff[1088]; + char *cmd; + cmd = argv[2]; + + if (strcmp(cmd, "help") == 0) + { + printf("nand dbg enable -> enable register read write log\n"); + printf("nand dbg disable -> disable register read write log\n"); + printf("nand dbg print -> enable read data print\n"); + printf("nand dbg noprint -> disable read data print\n"); + printf("nand dbg init -> initialize NFC\n"); + printf("nand dbg status -> read device status\n"); + printf("nand dbg id -> read device ID\n"); + printf("nand dbg read -> read \n"); + printf("nand dbg write -> program \n"); + printf("nand dbg erase -> erase\n"); + printf("nand dbg readchain -> Read in chained mode\n"); + } + else if (strcmp(cmd, "enable") == 0) + { + mvNfcDbgFlag = 1; + } + else if (strcmp(cmd, "disable") == 0) + { + mvNfcDbgFlag = 0; + } + else if (strcmp(cmd, "print") == 0) + { + mvNfcPrintFlag = 1; + } + else if (strcmp(cmd, "noprint") == 0) + { + mvNfcPrintFlag = 0; + } + else if (strcmp(cmd, "init") == 0) + { + MV_NFC_INFO nfcInfo; + + /* Override Control structure */ + gDbgCtrl = &nfcDbgCtrl; + + /*Fill info structure */ + nfcInfo.ioMode = MV_NFC_PDMA_ACCESS/*MV_NFC_PIO_ACCESS*/; + nfcInfo.eccMode = MV_NFC_ECC_HAMMING/*MV_NFC_ECC_BCH*/; +#if defined(MV_NAND_GANG_MODE) + nfcInfo.ifMode = MV_NFC_IF_2X8; +#else + nfcInfo.ifMode = MV_NFC_IF_1X8; +#endif + nfcInfo.autoStatusRead = MV_FALSE; + nfcInfo.tclk = 166666667; + nfcInfo.readyBypass = MV_FALSE; + + if (nfcInfo.ioMode == MV_NFC_PDMA_ACCESS) + { +#if 0 +/* Not needed here, mvPdmaInit() is performed in board_init() */ + printf("Initializing PDMA ... "); + if (mvPdmaInit() != MV_OK) + { + printf("FAILED\n"); + return -1; + } + printf("OK\n"); +#endif + } + + printf("Initializing NFC ... "); + if (mvNfcInit(&nfcInfo, gDbgCtrl) != MV_OK) + { + printf("FAILED\n"); + return -1; + } + printf("Flash detected %s\n", mvNfcFlashModelGet(gDbgCtrl)); + } + else if (gDbgCtrl == NULL) + { + printf("board_nand_init() was never called!\n"); + return -1; + } + else if (strcmp(cmd, "status") == 0) + { + if (mvNfcStatusRead(gDbgCtrl, buff) != 0) + return -1; + + printf("Status = %08x\n", buff[0]); + } + else if (strcmp(cmd, "id") == 0) + { + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_ID, 0, 0) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_ID, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + buff[0] = buff[1] = 0xFFFFFFFF; + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_ID, buff, (MV_U32)buff) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_ID, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + printf("ID = %08x\n", buff[0]); + } + else if (strcmp(cmd, "erase") == 0) + { + MV_U32 blkSize; + MV_8* endptr; + MV_U32 dest, size, offs, blk; + + if (mvNfcFlashBlockSizeGet(gDbgCtrl, &blkSize) != MV_OK) + { + printf("mvNfcFlashBlockSizeGet Failed!\n"); + return -1; + } + + if (argc != 5) + { + if (argc != 3) + printf("Illegal parameters, assuming single page 0\n"); + + dest = 0; + size = blkSize; + } + else + { + dest = simple_strtoul(argv[3], &endptr, 16); + size = simple_strtoul(argv[4], &endptr, 16); + + if (dest & (blkSize-1)) + printf("Offset not alligned to block boundaries (0x%x)\n", blkSize); + if (size & (blkSize-1)) + printf("Erase size not alligned to block size(0x%x)\n", blkSize); + } + + printf("NFC Erase: Erase Offset=0x%08x, Erase Size=0x%08x (Block Size = %08x)\n", dest, size, blkSize); + + /* Loop and write all space required */ + for (offs = dest; offs < (dest+size); offs+=blkSize) + { + printf("Erasing block offset %08x\n", offs); + + mvNfcAddress2BlockConvert(gDbgCtrl, offs, &blk); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_ERASE, blk, 0) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_ERASE, MV_NFC_STATUS_RDY/*MV_NFC_STATUS_CMDD*/, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + if (mvNfcStatusRead(gDbgCtrl, buff) != 0) + { + printf("Status Read Failed!\n"); + return -1; + } + + if (buff[0] & 0x1) + printf("SR0: Erase command Failed!\n"); + } + //printf("\n"); + } + else if (strcmp(cmd, "erasechain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 5) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + cnt = simple_strtoul(argv[4], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Erase: Block Number=0x%08x, Block Count=%08x\n", src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; icmdChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_ERASE, NULL); + if (stat & MV_NFC_STATUS_RDY) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopetimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Read: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; idataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", + ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stoptimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchaing") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/2)) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Ganaged Chained Read: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*2); i+=2) + { + desc[i].cmd = MV_NFC_CMD_READ_MONOLITHIC; + desc[i].pageAddr = (src + (i/2)); + desc[i].pageCount = 1; + desc[i].virtAddr = (MV_U32*)(dest + (i * 0x800)); + desc[i].physAddr = (dest + (i * 0x800)); + + desc[i+1].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+1].pageAddr = (src + (i/2)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(dest + ((i+1) * 0x800)); + desc[i+1].physAddr = (dest + ((i+1) * 0x800)); + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if (mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*2)) != MV_OK) + { + printf("Multiple Command Issue Failed!!\n"); + goto stopgtimer; + } + + /* wait for the command to finish */ + while(1) + { + + + if(mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopgtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchain1k") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + MV_U32 spare[8] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}; + MV_U32 err; + MV_PDMA_CHAN_STATE pdmastat; + MV_U32 reg; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/5)) + { + printf("Count exceeds allocated descriptor count (%d bigger than %d)\n", cnt, (MV_NFC_MAX_DESC_CHAIN/5)); + return -1; + } + + printf("NFS Ganaged Chained Read 1KB: DDR Dest=0x%08x, Source page # =0x%08x, Page Count=%08x\n", dest, src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*5); i+=5) + { + desc[i].cmd = MV_NFC_CMD_READ_MONOLITHIC; + desc[i].pageAddr = (src + (i/5)); + desc[i].pageCount = 1; + desc[i].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x0); + desc[i].physAddr = (dest + ((i/5)*0x1000) + 0x0); + desc[i].length = 0x400; + desc[i].numSgBuffs = 1; + + desc[i+1].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+1].pageAddr = (src + (i/5)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x400); + desc[i+1].physAddr = (dest + ((i/5)*0x1000) + 0x400); + desc[i+1].length = 0x400; + desc[i+1].numSgBuffs = 1; + + desc[i+2].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+2].pageAddr = (src + (i/5)); + desc[i+2].pageCount = 1; + desc[i+2].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x800); + desc[i+2].physAddr = (dest + ((i/5)*0x1000) + 0x800); + desc[i+2].length = 0x400; + desc[i+2].numSgBuffs = 1; + + desc[i+3].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+3].pageAddr = (src + (i/5)); + desc[i+3].pageCount = 1; + desc[i+3].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0xC00); + desc[i+3].physAddr = (dest + ((i/5)*0x1000) + 0xC00); + desc[i+3].length = 0x400; + desc[i+3].numSgBuffs = 1; + + desc[i+4].cmd = MV_NFC_CMD_READ_LAST_NAKED; + desc[i+4].pageAddr = (src + (i/5)); + desc[i+4].pageCount = 1; + desc[i+4].virtAddr = spare; + desc[i+4].physAddr = spare; + desc[i+4].length = 0x20; + desc[i+4].numSgBuffs = 1; + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if ((err = mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*5))) != MV_OK) + { + printf("Multiple Command Issue Failed (Error = %x!!\n", err); + goto stoprtimer; + } + + /* wait for the command to finish */ + while(1) + { + if((pdmastat = mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl)) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } + +stoprtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "read") == 0) + { + MV_U32 pgSize; + MV_8* endptr; + MV_U32 src, dest, size, offs, row, col; + MV_U32 totalsize; + + if (mvNfcFlashPageSizeGet(gDbgCtrl, &pgSize, &totalsize) != MV_OK) + { + printf("mvNfcFlashPageSizeGet Failed!\n"); + return -1; + } + + if (argc != 6) + { + if (argc != 3) + printf("Illegal parameters, assuming single page 0\n"); + + dest = (MV_U32) buff; + src = 0; + size = pgSize; + } + else + { + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + size = simple_strtoul(argv[5], &endptr, 16); + } + + printf("NFS Read: Source=0x%08x, DDR destination=0x%08x, Size=%08x\n (page Size = %x)", src, dest, size, pgSize); + + /* Loop and write all space required */ + for (offs = src; offs < (src+size); offs+=pgSize, dest+=pgSize) + { + mvNfcAddress2RowConvert(gDbgCtrl, offs, &row, &col); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (gDbgCtrl->ifMode == MV_NFC_IF_2X8) /* GANGED MODE */ + { + row = (row/2); + printf("READ-GNGD: row(%x), col(%x), dest(%x)\n", row, col, dest);\ + + //printf("STEP 1: Issue MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + //printf("STEP 2: Date read MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_U32*)dest, dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + + dest += (pgSize/2); + + // printf("dest2(%x)\n", dest); + + //printf("STEP 3: Issue MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_NAKED, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_NAKED, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + //printf("STEP 4: Date read MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_NAKED, (MV_U32*)dest, dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_NAKED, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + + dest -= (pgSize/2); + } + else /* NON-GANGED MODE */ + { + printf("Read: ROW=%x COL=%x DST=%x\n", row, col, dest); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_U32*)(dest), dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + } + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + } // read loop + } + else if (strcmp(cmd, "writechain1k") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + MV_U32 spare[8] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}; + MV_U32 err; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + dest = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/7)) + { + printf("Count exceeds allocated descriptor count (%d bigger than %d)\n", cnt, (MV_NFC_MAX_DESC_CHAIN/7)); + return -1; + } + + printf("NFS Ganaged Chained Write 1KB: DDR Source=0x%08x, Destination page # =0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*7); i+=7) + { + desc[i].cmd = MV_NFC_CMD_WRITE_DISPATCH_START; + desc[i].pageAddr = (dest + (i/7)); + desc[i].pageCount = 1; + desc[i].virtAddr = 0; + desc[i].physAddr = 0; + desc[i].length = 0; + desc[i].numSgBuffs = 1; + + desc[i+1].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+1].pageAddr = (dest + (i/7)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x4); + desc[i+1].physAddr = (src + ((i/7)*0x1000) + 0x0); + desc[i+1].length = 0x400; + desc[i+1].numSgBuffs = 1; + + desc[i+2].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+2].pageAddr = (dest + (i/7)); + desc[i+2].pageCount = 1; + desc[i+2].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x400); + desc[i+2].physAddr = (src + ((i/7)*0x1000) + 0x400); + desc[i+2].length = 0x400; + desc[i+2].numSgBuffs = 1; + + desc[i+3].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+3].pageAddr = (dest + (i/7)); + desc[i+3].pageCount = 1; + desc[i+3].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x800); + desc[i+3].physAddr = (src + ((i/7)*0x1000) + 0x800); + desc[i+3].length = 0x400; + desc[i+3].numSgBuffs = 1; + + desc[i+4].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+4].pageAddr = (dest + (i/7)); + desc[i+4].pageCount = 1; + desc[i+4].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0xC00); + desc[i+4].physAddr = (src + ((i/7)*0x1000) + 0xC00); + desc[i+4].length = 0x400; + desc[i+4].numSgBuffs = 1; + + desc[i+5].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+5].pageAddr = (dest + (i/7)); + desc[i+5].pageCount = 1; + desc[i+5].virtAddr = spare; + desc[i+5].physAddr = spare; + desc[i+5].length = 0x20; + desc[i+5].numSgBuffs = 1; + + desc[i+6].cmd = MV_NFC_CMD_WRITE_DISPATCH_END; + desc[i+6].pageAddr = (dest + (i/7)); + desc[i+6].pageCount = 1; + desc[i+6].virtAddr = 0; + desc[i+6].physAddr = 0; + desc[i+6].length = 0; + desc[i+6].numSgBuffs = 1; + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if ((err = mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*7))) != MV_OK) + { + printf("Multiple Command Issue Failed (Error = %x!!\n", err); + goto stopwtimer; + } + + /* wait for the command to finish */ + while(1) + { + if(mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, NULL); + printf("mvNfcStatusGet = %08x\n", stat); + if (stat & MV_NFC_STATUS_RDY) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopwtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "writechain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Program: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", dest, src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; idataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopptimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "write") == 0) + { + MV_U32 pgSize; + MV_8* endptr; + MV_U32 src, dest, size, offs, row, col; + MV_STATUS ret; + MV_U8 tmpbuff[2112]; + MV_U32 totalsize; + + memset(tmpbuff, 0xFF, 2112); + + if (mvNfcFlashPageSizeGet(gDbgCtrl, &pgSize, &totalsize) != MV_OK) + { + printf("mvNfcFlashPageSizeGet Failed!\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + dest = simple_strtoul(argv[4], &endptr, 16); + size = simple_strtoul(argv[5], &endptr, 16); + + printf("NFS Program: DDR Source=0x%08x, Flash Offset=0x%08x, Size=%08x (Page Size = %08x)\n", src, dest, size, pgSize); + + /* Loop and write all space required */ + for (offs = dest; offs < (dest+size); offs+=pgSize, src+=pgSize) + { + mvNfcAddress2RowConvert(gDbgCtrl, offs, &row, &col); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (gDbgCtrl->ifMode == MV_NFC_IF_2X8) /* GANGED MODE */ + { + row = (row/2); + + printf("PRGRM-GNGD: row(%x), col(%x), src1(%x)\n", row, col, src); + + /*****/ + /* 1 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 1: MV_NFC_CMD_WRITE_DISPATCH_START\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_START, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_START, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + + /*****/ + /* 2 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 2: Issue MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /*****/ + /* 3 */ + memcpy(tmpbuff, (MV_U8*)src, 2048); + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 3: Write Data MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /* increment address */ + src += (pgSize/2); + + // printf("src2(%x)\n", src); + + /*****/ + /* 4 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 4: Issue MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + + /*****/ + /* 5 */ + memcpy(tmpbuff, (MV_U8*)src, 2048); + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 5: Write Data MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /*****/ + /* 6 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 6: MV_NFC_CMD_WRITE_DISPATCH_END\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_END, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_END, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /* increment address */ + src -= (pgSize/2); + } + else /* NON-GANGED MODE */ + { + printf("Write: ROW=%x COL=%x SRC=%x\n", row, col, src); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + memcpy(tmpbuff, (MV_U8*)src, 2048); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + } + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + } /* page loop */ + } + + return 1; +} +#endif /* MV_NFC_DBG */ + +#if 0 +#if defined(CFG_NAND_BOOT) +extern int doNandScrub(struct nand_chip* nand, size_t ofs); + +/* Erase bad blocks - for internal use only */ +int do_nand_scrub(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char console_buffer[]; + + printf("\n**Warning**\n"); + printf("This command will erase NAND flash bad blocks ...\n"); + printf("Are you sure ? (y/n)"); + readline(" "); + + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + doNandScrub(nand_dev_desc + 0, 0); + } + return 1; +} + +U_BOOT_CMD( + nandScrub, 4, 4, do_nand_scrub, + "", + " " + "" +); + +#endif /* defined(CFG_NAND_BOOT) */ +#endif + +#if 0 +#include "twsi/mvTwsi.h" +#include "audio/mvAudioRegs.h" +#include "audio/mvAudio.h" +#include "audio/dac/mvCLAudioCodec.h" + + +static MV_U32 codec_init_values[][2] = { + /* Address Value */ + { 0x00, 0x0 }, + { 0x0c, 0x808 }, + { 0x1c, 0x2740 }, + { 0x6a, 0x46 }, + { 0x6c, 0xffff }, + { 0x40, 0x3700 }, + { 0x34, 0x8000 }, + { 0x3e, 0x96c1 }, + { 0x3c, 0x67f3 }, + { 0x3a, 0xcd70 }, + { 0x04, 0x0 }, + { 0x02, 0x0 }, + { 0x5e, 0x0 }, + { -1, -1 } +}; + +/* +** Initialize codec registers to enable audio playback. +*/ +void audio_init_codec(void) +{ + MV_TWSI_ADDR twsiAddr; + MV_U32 i; + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[2]; + int ADDRS = 0x4A; + + twsiAddr.address = ADDRS; + twsiAddr.type = ADDR7_BIT; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &twsiAddr, MV_FALSE); + + for(i = 0; codec_init_values[i][0] != 0xFFFFFFFF; i++) { + twsiSlave.slaveAddr.address = ADDRS; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = codec_init_values[i][0]; + twsiSlave.moreThen256 = MV_FALSE; + data[0] = (MV_U8)((codec_init_values[i][1] >> 8) & 0xFF); + data[1] = (MV_U8)(codec_init_values[i][1] & 0xFF); + if(mvTwsiWrite(0, &twsiSlave, data, 2) != MV_OK) { + printf("mvTwsiWrite() failed address [0x%x], value [0x%x] - FAILED\n", codec_init_values[i][0], codec_init_values[i][1]); + continue; + } else { + printf("address [0x%x], value [0x%x]\n", codec_init_values[i][0], codec_init_values[i][1]); + } + } + return; +} + +int audio_play_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 dataAddr; + MV_U32 dataSize; + MV_STATUS status; + MV_AUDIO_PLAYBACK_CTRL pbCtrl; + MV_I2S_PLAYBACK_CTRL i2sCtrl; + MV_AUDIO_FREQ_DATA dcoCtrl; + +// audio_init_codec(); + + dataAddr = simple_strtoul( argv[1], NULL, 16 ); + dataSize = simple_strtoul( argv[2], NULL, 16 ); + + /* Initialize Audio HAL */ + mvSysAudioInit(1); + + pbCtrl.burst = AUDIO_128BYTE_BURST; + pbCtrl.loopBack = MV_FALSE; + pbCtrl.monoMode = AUDIO_PLAY_BOTH_MONO; + pbCtrl.bufferPhyBase = dataAddr; /* Buffer holding PCM data */ + pbCtrl.bufferSize = dataSize; /* Size of buffer in bytes */ + pbCtrl.intByteCount = dataSize; /* N/A, no interrupts in Uboot */ + + /* Set default sample size to 16-non compact */ + pbCtrl.sampleSize = SAMPLE_16BIT_NON_COMPACT; + /* Check if user wants to override the default value */ + if(argc > 3) { + if(strcmp(argv[3],"16nc") == 0) + pbCtrl.sampleSize = SAMPLE_16BIT_NON_COMPACT; + else if(strcmp(argv[3],"16") == 0) + pbCtrl.sampleSize = SAMPLE_16BIT; + else if(strcmp(argv[3],"24") == 0) + pbCtrl.sampleSize = SAMPLE_24BIT; + else if(strcmp(argv[3],"32") == 0) + pbCtrl.sampleSize = SAMPLE_32BIT; + else { + printf("Bad sample size (16, 16nc, 24, 32).\n"); + return 0; + } + } + status = mvAudioPlaybackControlSet(1, &pbCtrl); + if(status != MV_OK) { + printf("mvAudioPlaybackControlSet() failed (%d).\n", status); + return 0; + } + + /* Get the current DCO config */ + mvAudioDCOCtrlGet(1,&dcoCtrl); + /* Set default sample rate. */ + dcoCtrl.baseFreq = AUDIO_FREQ_44_1KH; + /* Check if user wants to overried default sample rate */ + if(argc > 4) { + if(strcmp(argv[4],"44.1khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_44_1KH; + else if(strcmp(argv[4],"48khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_48KH; + else if(strcmp(argv[4],"96khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_96KH; + else { + printf("Bad sample rate.\n"); + return 0; + } + } + /* Set Sample rate */ + status = mvAudioDCOCtrlSet(1, &dcoCtrl); + if(status != MV_OK) { + printf("mvAudioDCOCtrlSet() failed (%d).\n", status); + return 0; + } + + /* Set I2S playback related parameters. */ + i2sCtrl.sampleSize = ((pbCtrl.sampleSize == SAMPLE_16BIT_NON_COMPACT) ? + SAMPLE_16BIT : pbCtrl.sampleSize); + i2sCtrl.justification = I2S_JUSTIFIED; + i2sCtrl.sendLastFrame = MV_FALSE; + status = mvI2SPlaybackCtrlSet(0, &i2sCtrl); + if(status != MV_OK) { + printf("mvI2SPlaybackCtrlSet() failed (%d).\n", status); + return 0; + } + + /* Clear interrupt cause bit */ + MV_REG_WRITE(MV_AUDIO_INT_CAUSE_REG(1),(1 << 7)); + + /* Unmute I2S */ + mvAudioI2SPlaybackMute(1, MV_FALSE); + /* Enable playback */ + mvAudioI2SPlaybackEnable(1, MV_TRUE); + /* Unpause I2S */ + mvAudioPlaybackPause(1, 0); + + /* + ** Wait till audio buffer is consumed. + ** Otherwise the playback will loop over the buffer forever. + */ + while(!(MV_REG_READ(MV_AUDIO_INT_CAUSE_REG(1)) & (1 << 7))) { + if(ctrlc()) + break; + } + /* Clear interrupt cause bit */ + MV_REG_WRITE(MV_AUDIO_INT_CAUSE_REG(1),(1 << 7)); + /* Stop playback */ + mvAudioI2SPlaybackMute(1, MV_TRUE); + mvAudioPlaybackPause(1, MV_TRUE); + mvAudioI2SPlaybackEnable(1, MV_FALSE); + + return 1; +} + +U_BOOT_CMD( + audioTest, 5, 1, audio_play_cmd, + "audioTest - Test audio playback\n", + " AuidTest address size sample_size sample_rate\n" + " \taddress\t - Address holding PCM data.\n" + " \tsize\t - data buffer size in bytes (< 16MB).\n" + " \tsample_size\t - 16, 16nc, 24 or 32 (default 16nc).\n" + " \tsample_rate\t - 44.1khz, 48khz or 96khz (default 44.1khz).\n" + "\tPlay audio buffer. \n" +); +#endif + +int whoAmI_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + printf("cpu #: %d", whoAmI()); + return 1; +} + +U_BOOT_CMD( + whoAmI, 2, 1, whoAmI_cmd, + "- reading CPU ID\n", + "" + ); \ No newline at end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_dram.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_dram.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_dram.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_dram.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,310 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "ddr2/mvDramIf.h" +#include "mvOs.h" +#include "mvBoardEnvLib.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCpuIf.h" + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +extern void _start(void); +extern void reset_cpu (ulong addr); +extern int dramBoot; + + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void); +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +#endif + +MV_VOID mvIntrfaceWidthPrint(MV_VOID) +{ + printf(" 16bit width"); +} + +MV_VOID mvIntrfaceParamPrint(MV_VOID) +{ + MV_U32 temp; + + printf("DRAM"); + switch((MV_REG_READ(0x141c) >> 4) & 0x7) { + case 0x3: + printf(" CAS Latency = 3"); + break; + case 0x4: + printf(" CAS Latency = 4"); + break; + case 0x5: + printf(" CAS Latency = 5"); + break; + case 0x6: + printf(" CAS Latency = 6"); + break; + default: + printf(" unknown CAL "); + break; + } + + temp = MV_REG_READ(0x1408); + printf(" tRP = %d tRAS = %d tRCD=%d\n", + ((temp >> 8) & 0xf) + 1, ((temp >> 16) & 0x10) + (temp & 0xf) + 1, ((temp >> 4) & 0xf) + 1); +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int i, dramTotalSize=0; + MV_32 memBase; + +#if defined(MV_INC_BOARD_DDIM) + /* Call dramInit */ + if (0 == (dramTotalSize = initdram(0))) { + printf("DRAM Initialization Failed\n"); + reset_cpu(0); + return (1); + } +#endif + + //mvIntrfaceParamPrint(); + + for(i = 0; i< MV_DRAM_MAX_CS; i++) { +#warning: not relevant to KW2? +#if !defined(MV_88F6082L) && defined(MV_88F6082) + if (mvCtrlModelRevGet() == MV_6082_A0_ID) { + gd->bd->bi_dram[i].start = (i)?_16M:0; + gd->bd->bi_dram[i].size = _8M; + } else { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + } +#else + MV_CPU_DEC_WIN addrDecWin; + if((mvCpuIfTargetWinGet(SDRAM_CS0 + i, &addrDecWin) == MV_OK) && + (addrDecWin.enable == MV_TRUE)) { + memBase = addrDecWin.addrWin.baseLow; + gd->bd->bi_dram[i].start = memBase; + gd->bd->bi_dram[i].size = addrDecWin.addrWin.size; + } +#endif + //dramTotalSize += gd->bd->bi_dram[i].size; +// if (gd->bd->bi_dram[i].size) +// { + //printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + //mvSizePrint(gd->bd->bi_dram[i].size); + //printf("\n"); +// } + } + +// printf("DRAM Total "); +// mvSizePrint(dramTotalSize); +// mvIntrfaceWidthPrint(); +// printf("\n"); + +#ifdef MV_INC_DRAM_MFG_TEST + mvDramMfgTrst(); +#endif + return 0; +} + +#if defined(MV_INC_BOARD_DDIM) + +/* u-boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram(int board_type) +{ + MV_VOIDFUNCPTR pRom; + MV_U32 forcedCl; /* Forced CAS Latency */ + MV_U32 totalSize; + char * env; + MV_TWSI_ADDR slave; + + /* r0 <- current position of code */ + /* test if we run from flash or RAM */ + if(dramBoot != 1) + { + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); + + /* Calculating MIN/MAX CAS latency according to user settings */ + env = getenv("CASset"); + + if(env && (strcmp(env,"1.5") == 0)) + { + forcedCl = 15; + } + else if(env && (strcmp(env,"2") == 0)) + { + forcedCl = 20; + } + else if(env && (strcmp(env,"2.5") == 0)) + { + forcedCl = 25; + } + else if(env && (strcmp(env,"3") == 0)) + { + forcedCl = 30; + } + else if(env && (strcmp(env,"4") == 0)) + { + forcedCl = 40; + } + else if(env && (strcmp(env,"5") == 0)) + { + forcedCl = 50; + } + else if(env && (strcmp(env,"6") == 0)) + { + forcedCl = 60; + } + else + { + forcedCl = 0; + } + + /* detect the dram configuartion parameters */ + if (MV_OK != mvDramIfDetect(forcedCl,1)) + { + printf("DRAM Auto Detection Failed! System Halt!\n"); + return 0; + } + + /* set the dram configuration */ + /* Calculate jump address of _mvDramIfConfig() */ + +#if defined(MV_BOOTROM) + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN); +#else + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE); +#endif + + + (*pRom) (); /* Jump to _mvDramIfConfig*/ + } + + totalSize = mvDramIfSizeGet(); + + + return(totalSize); +} + +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void) +{ + + /* Memory test */ + DECLARE_GLOBAL_DATA_PTR; + unsigned int mem_len,i,j, pattern; + unsigned int *mem_start; + char *env; + + env = getenv("enaPost"); + if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) ) + { + printf("Memory test pattern: "); + + for (j = 0 ; j<2 ; j++) + { + + switch(j){ + case 0: + pattern=0x55555555; + printf("0x%X, ",pattern); + break; + case 1: + pattern=0xAAAAAAAA; + printf("0x%X, ",pattern); + break; + default: + pattern=0x0; + printf("0x%X, ",pattern); + break; + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + mem_start = (unsigned int *)gd->bd->bi_dram[i].start; + mem_len = gd->bd->bi_dram[i].size; + if (i == 0) + { + mem_start+= _4M; + mem_len-= _4M; + } + mem_len/=4; + if (MV_OK != mv_mem_test(mem_start, pattern, mem_len)) + { + printf(" Fail!\n"); + while(1); + } + } + } + printf(" Pass\n"); + } +} + + +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + *(pMem + i) = pattern; + + if (MV_OK != mv_mem_cmp(pMem, pattern, count)) + { + return MV_ERROR; + } + return MV_OK; +} + +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + { + if (*(pMem + i) != pattern) + { + printf("Fail\n"); + printf("Test failed at 0x%x\n",(pMem + i)); + return MV_ERROR; + } + } + + return MV_OK; +} +#endif /* MV_INC_DRAM_MFG_TEST */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_CESA_API_H__ +#define __MV_SYS_CESA_API_H__ + + +MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,108 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cesa/mvCesa.h" + +extern u32 mv_crypto_base_get(void); + +/******************************************************************************* +* mvSysCesaInit - Initialize the Cesa subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle) +{ + MV_CESA_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvCesaTdmaWinInit(addrWinMap); + + if (status == MV_OK) { + halData.sramPhysBase = (MV_ULONG)mv_crypto_base_get(); + halData.sramVirtBase = (MV_U8 *)mv_crypto_base_get(); + halData.sramOffset = 0; + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + status = mvCesaHalInit(numOfSession, queueDepth, + osHandle, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,134 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + + +/******************************************************************************* +* mvSysDdrSpdRead +* +* DESCRIPTION: +* System interface for reading DDR SPD contents. +* +* INPUT: +* data: Buffer to read data into. +* size: Number of bytes to read. +* +* OUTPUT: +* data: SPD data. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdRead(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiRead(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} + + +/******************************************************************************* +* mvSysDdrSpdWrite +* +* DESCRIPTION: +* System interface for writing DDR SPD contents. +* +* INPUT: +* data: Buffer holding the data to be written. +* size: Number of bytes to write. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdWrite(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiWrite(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETH_API_H__ +#define __MV_SYS_ETH_API_H__ + + +MV_VOID mvSysEthInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,129 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "eth/mvEth.h" + + +/******************************************************************************* +* mvSysEthInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysEthInit(MV_VOID) +{ + MV_ETH_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + int i; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status != MV_OK) + return; + + for (i = 0; i < MAX_TARGETS; i++) { + if (addrWinMap[i].enable == MV_FALSE) + continue; + + } + + halData.maxPortNum = mvCtrlEthMaxPortGet(); + halData.cpuPclk = mvCpuPclkGet(); + halData.tclk = mvBoardTclkGet(); +#ifdef ETH_DESCR_IN_SRAM + halData.sramSize = mvCtrlSramSizeGet(); +#endif + + for (port = 0; port < halData.maxPortNum; port++) { + if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) { + halData.portData[port].powerOn = MV_FALSE; + continue; + } + status = mvEthWinInit(port, addrWinMap); + if (status == MV_OK) { + halData.portData[port].powerOn = MV_TRUE; + halData.portData[port].phyAddr = mvBoardPhyAddrGet(port); + halData.portData[port].isSgmii = mvBoardIsPortInSgmii(port); + halData.portData[port].macSpeed = mvBoardMacSpeedGet(port); + } + } + + mvEthHalInit(&halData); + + return; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETHPHY_API_H__ +#define __MV_SYS_ETHPHY_API_H__ + + +MV_STATUS mvSysEthPhyInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "eth-phy/mvEthPhy.h" + + +/******************************************************************************* +* mvSysEthPhyInit - Initialize the EthPhy subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysEthPhyInit(void) +{ + MV_ETHPHY_HAL_DATA halData; + MV_U32 port; + + for (port = 0; port < mvCtrlEthMaxPortGet(); port++) { + halData.phyAddr[port] = mvBoardPhyAddrGet(port); + halData.boardSpecInit = MV_FALSE; + } + + return mvEthPhyHalInit(&halData); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_NETA_API_H__ +#define __MV_SYS_NETA_API_H__ + + +void mvSysNetaInit(void); + +#endif /* __MV_SYS_NETA_API_H__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,136 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "neta/gbe/mvNeta.h" + + +/******************************************************************************* +* mvSysNetaInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +void mvSysNetaInit(void) +{ + MV_NETA_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + int i; + + memset(&halData, 0, sizeof(halData)); + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status != MV_OK) + return; + + for (i = 0; i < MAX_TARGETS; i++) { + if (addrWinMap[i].enable == MV_FALSE) + continue; + + printk(KERN_INFO "%d - Base 0x%08x , Size = 0x%08x.\n", i, + addrWinMap[i].addrWin.baseLow, addrWinMap[i].addrWin.size); + } + halData.maxPort = mvCtrlEthMaxPortGet(); + halData.pClk = mvCpuPclkGet(); + halData.tClk = mvBoardTclkGet(); + halData.isGpon = MV_FALSE; + +#ifdef CONFIG_MV_ETH_BM + halData.bmPhysBase = PNC_BM_PHYS_BASE; + halData.bmVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_BM */ + +#ifdef CONFIG_MV_ETH_PNC + halData.pncPhysBase = PNC_BM_PHYS_BASE; + halData.pncVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_PNC */ + + for (port = 0; port < halData.maxPort; port++) { + if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) + continue; + + mvNetaPortPowerUp(port); + status = mvNetaWinInit(port, addrWinMap); + if (status != MV_OK) + continue; + + } + + mvNetaHalInit(&halData); + + return; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_PEX_API_H__ +#define __MV_SYS_PEX_API_H__ +#include "pex/mvPex.h" + +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" + +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvSysPexInit - Initialize the Pex subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_PEX_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvPexWinInit(pexIf, pexType, addrWinMap); + + if (status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.maxPexIf = mvCtrlPexMaxIfGet(); + status = mvPexInit(pexIf, pexType, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SATA_API_H__ +#define __MV_SYS_SATA_API_H__ + +MV_STATUS mvSysSataWinInit(MV_VOID); + +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "sata/CoreDriver/mvSata.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +MV_STATUS mvSysSataWinInit(MV_VOID) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvSataWinInit(addrWinMap); + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,226 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "sflash/mvSysSFlash.h" + +#define MV_SYS_SFLASH_MAX_CMD_LEN 4 + +static struct { + MV_U8 buf[MV_SYS_SFLASH_MAX_CMD_LEN]; + MV_U32 bufLen; + MV_U8 transType; +} mvSysSflashCmd; + +/******************************************************************************* +* mvSysSflashCommandSet +* +* DESCRIPTION: +* System interface for sending a command to the SPI flash. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* cmdBuff: Command data to be written. +* cmdLen: Command length in bytes. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashCommandSet(MV_VOID *flashHandle, MV_U8* cmdBuff, MV_U32 cmdLen, + MV_U8 transType) +{ + if (cmdLen > MV_SYS_SFLASH_MAX_CMD_LEN) + return MV_ERROR; + + if (!(transType & SYS_SFLASH_TRANS_START) || (mvSysSflashCmd.transType != 0)) + return MV_ERROR; + + mvSpiParamsSet(0, 0, SPI_TYPE_FLASH); + + memcpy(mvSysSflashCmd.buf, cmdBuff, cmdLen); + mvSysSflashCmd.bufLen = cmdLen; + mvSysSflashCmd.transType = transType; + + if (transType & SYS_SFLASH_TRANS_END) + return mvSysSflashDataWrite(flashHandle, NULL, 0, transType); + + return MV_OK; +} + + +/******************************************************************************* +* mvSysSflashDataRead +* +* DESCRIPTION: +* System interface for reading SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer to read the data into. +* dataLen: Number of bytes to read. +* dummyBytes: Number of dummy bytes to read before reading the real +* data. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* dataBuff: The data as read from flash. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataRead(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U32 dummyBytes, MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + + ret = mvSpiWriteThenRead(0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, + dataBuff, dataLen, dummyBytes); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd, 0, sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashDataWrite +* +* DESCRIPTION: +* System interface for writing SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer holding the data to be written. +* dataLen: Number of bytes to write. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataWrite(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + ret = mvSpiWriteThenWrite(0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, dataBuff, dataLen); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd, 0, sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashFreqSet +* +* DESCRIPTION: +* System interface for controlling the SPI interface frequency. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* freq: The new frequency to be configured for the SPI IF. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashFreqSet(MV_VOID *flashHandle, MV_U32 freq) +{ + + return mvSpiBaudRateSet(0, freq); +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SPI_API_H__ +#define __MV_SYS_SPI_API_H__ + +#include "mvCommon.h" + +MV_STATUS mvSysSpiInit(MV_U8 spi_id, MV_U32 serialBaudRate); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,126 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "spi/mvSpi.h" +#include "spi/mvSysSpi.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/******************************************************************************* +* mvSysSpiInit - Initialize the SPI subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysSpiInit(MV_U8 spiId, MV_U32 serialBaudRate) +{ + MV_SPI_HAL_DATA halData; + + halData.ctrlModel = mvCtrlModelGet(); + halData.tclk = mvBoardTclkGet(); + + return mvSpiInit(spiId, serialBaudRate, &halData); +} + + +/******************************************************************************* +* mvSysSpiMppConfig +* +* DESCRIPTION: +* System interface for configuring the MPP's configuration to enable / +* disable SPI mode. +* +* INPUT: +* mode: The mode to be set into MPP unit. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSpiMppConfig(MV_U8 mode) +{ +#if 0 + if (mode == SYS_SPI_MPP_ENABLE) + mvMPPConfigToSPI(); + else + mvMPPConfigToDefault(); +#endif + return MV_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,78 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_TDM_API_H__ +#define __MV_SYS_TDM_API_H__ + +#include "mvSysTdmConfig.h" + +#ifdef MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else +#include "voiceband/commUnit/mvCommUnit.h" +#endif + +MV_STATUS mvSysTdmInit(MV_TDM_PARAMS *tdmParams); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,236 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" + +#ifdef CONFIG_MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else +#include "voiceband/commUnit/mvCommUnit.h" +#include "gpp/mvGpp.h" +#endif + +#include "voiceband/mvSysTdmSpi.h" +#include "spi/mvSpiCmnd.h" +#include "spi/mvSpi.h" + +#define MAX_DATA_LENGTH 255 + +/******************************************************************************* +* mvSysTdmInit - Initialize the TDM subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysTdmInit(MV_TDM_PARAMS *tdmParams) +{ + MV_TDM_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) +#ifdef MV_TDM_SUPPORT + status = mvTdmWinInit(addrWinMap); +#else + status = mvCommUnitWinInit(addrWinMap); +#endif + + if (status == MV_OK) { + halData.spiMode = mvBoardTdmSpiModeGet(); + halData.model = mvCtrlModelGet(); +#ifdef MV_TDM_SUPPORT + status = mvTdmHalInit(tdmParams, &halData); +#else + halData.maxCs = mvBoardTdmDevicesCountGet(); + status = mvCommUnitHalInit(tdmParams, &halData); + + /* Issue SLIC reset */ + mvGppValueSet(0, BIT24, 0); + mvOsDelay(1); + mvGppValueSet(0, BIT24, BIT24); +#endif + } + + return status; +} + +MV_VOID mvSysTdmSpiRead(MV_U16 lineId, MV_U8 *cmdBuff, MV_U8 cmdSize, MV_U8 *dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if ((cmdSize > 4) || (dataSize > MAX_DATA_LENGTH)) { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiRead(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(0, mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if (MV_OK != mvSpiWriteThenRead(0, cmdBuff, cmdSize, dataBuff, dataSize, 0)) + printk(KERN_ERR "SPI read failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmSpiWrite - telephony register write via SPI interface +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmSpiWrite(MV_U16 lineId, MV_U8 *cmdBuff, MV_U8 cmdSize, MV_U8 *dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if ((cmdSize > 3) || (dataSize > MAX_DATA_LENGTH)) { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiWrite(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(0, mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if (MV_OK != mvSpiWriteThenWrite(0, cmdBuff, cmdSize, dataBuff, dataSize)) + printk(KERN_ERR "SPI write failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmIntEnable - Enable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntEnable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntEnable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntEnable(deviceId); + +#endif +} + +/******************************************************************************* +* mvSysTdmIntDisable - Disable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntDisable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntDisable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntDisable(deviceId); + +#endif +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_USB_API_H__ +#define __MV_SYS_USB_API_H__ + +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,105 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "usb/mvUsb.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "usb/mvUsbRegs.h" + +/******************************************************************************* +* mvSysUsbHalInit - Initialize the USB subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost) +{ + MV_USB_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvUsbWinInit(dev, addrWinMap); + + if (dev == 0) + mvUsbPllInit(); + if (status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + status = mvUsbHalInit(dev, isHost, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_XOR_API_H__ +#define __MV_SYS_XOR_API_H__ + +MV_VOID mvSysXorInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,87 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "xor/mvXor.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "xor/mvXorRegs.h" + +MV_VOID mvSysXorInit(void) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvXorWinInit(addrWinMap); + + if (status == MV_OK) + mvXorHalInit(MV_XOR_MAX_CHAN); + return; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_main.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_main.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_main.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_main.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,1370 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include "mvTypes.h" +#include "mvBoardEnvLib.h" +#include "mvCpuIf.h" +#include "mvCtrlEnvLib.h" +#include "mv_mon_init.h" +#include "mvDebug.h" +#include "device/mvDevice.h" +#include "twsi/mvTwsi.h" +#include "eth/mvEth.h" +#include "pex/mvPex.h" +#include "gpp/mvGpp.h" +#include "gpp/mvGppRegs.h" +#include "mvSysHwConfig.h" +#include "mv_phy.h" + +#ifdef MV_INCLUDE_RTC +#include "rtc/integ_rtc/mvRtc.h" +#include "rtc.h" +#elif CONFIG_RTC_DS1338_DS1339 +#include "rtc/ext_rtc/mvDS133x.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#include "mvSysXorApi.h" +#endif +#if defined(MV_INCLUDE_IDMA) +#include "sys/mvSysIdma.h" +#include "idma/mvIdma.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#include "mvSysUsbApi.h" +#endif + +#include "cpu/mvCpu.h" +#include "nand.h" +#include "spi_flash.h" +#ifdef CONFIG_PCI + #include +#endif +//#include "pci/mvPciRegs.h" + +#include +#include +//#include +//#include + +#include +#include +#include +#include "mvCommon.h" +#include "uart/mvUart.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* CPU address decode table. */ +MV_CPU_DEC_WIN mvCpuAddrWinMap[] = MV_CPU_IF_ADDR_WIN_MAP_TBL; +/*extern MV_U32 dummyFlavour;*/ +#if 0 +static void mvHddPowerCtrl(void); +#endif +#if defined(CONFIG_CMD_RCVR) +extern void recoveryDetection(void); +#endif +void mv_cpu_init(void); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void); +#endif + +#if 0 +#ifdef CONFIG_FLASH_CFI_DRIVER +//MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID); +//int mv_board_num_flash_banks; +//extern flash_info_t flash_info[]; /* info for FLASH chips */ +//extern unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); +#endif /* CONFIG_FLASH_CFI_DRIVER */ +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +//extern MV_VOID mvBoardEgigaPhySwitchInit(void); +#endif + +#if defined(CONFIG_CMD_NAND) +/* Define for SDK 2.0 */ +int __aeabi_unwind_cpp_pr0(int a,int b,int c) {return 0;} +int __aeabi_unwind_cpp_pr1(int a,int b,int c) {return 0;} +#endif + +extern nand_info_t nand_info[]; /* info for NAND chips */ + +extern struct spi_flash *flash; +//MV_VOID mvMppModuleTypePrint(MV_VOID); + +#ifdef MV_NAND_BOOT +extern MV_U32 nandEnvBase; +#endif + +/* Define for SDK 2.0 */ +//int raise(void) {return 0;} + +void print_mvBanner(void) +{ +#ifdef CONFIG_SILENT_CONSOLE + DECLARE_GLOBAL_DATA_PTR; + gd->flags |= GD_FLG_SILENT; +#endif + printf("\n"); + printf(" __ __ _ _\n"); + printf("| \\/ | __ _ _ ____ _____| | |\n"); + printf("| |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n"); + printf("| | | | (_| | | \\ V / __/ | |\n"); + printf("|_| |_|\\__,_|_| \\_/ \\___|_|_|\n"); + printf(" _ _ ____ _\n"); + printf(" | | | | | __ ) ___ ___ | |_ \n"); + printf(" | | | |___| _ \\ / _ \\ / _ \\| __| \n"); + printf(" | |_| |___| |_) | (_) | (_) | |_ \n"); + printf(" \\___/ |____/ \\___/ \\___/ \\__| \n"); +//#if !defined(MV_NAND_BOOT) +#if defined(MV_INCLUDE_MONT_EXT) + //mvMPPConfigToSPI(); + if(!enaMonExt()) + printf(" ** LOADER **\n"); + else + printf(" ** MONITOR **\n"); + //mvMPPConfigToDefault(); +#else + + printf(" ** LOADER **\n"); +#endif /* MV_INCLUDE_MONT_EXT */ +//#endif + return; +} + +void maskAllInt(void) { + int i; + /* for all interrupts (0-115) reset bit 0:3 and 8:11 to disable IRQ and FIQ */ + for (i=0; i < MV_IRQ_NR; i++) + MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(i), MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(i)) & ~(0xF0F)); + +} + +/* init for the Master*/ +void misc_init_r_dec_win(void) +{ +#if defined(MV_INCLUDE_USB) + { + char *env, envname[10]; + int i; + + for (i = 0; i < mvCtrlUsbMaxGet(); i++) { + + sprintf(envname, "usb%dMode", i); + env = getenv(envname); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + printf("USB %d: Device Mode\n", i); + mvSysUsbInit(i, MV_FALSE); + } + else + { + printf("USB %d: Host Mode\n", i); + mvSysUsbInit(i, MV_TRUE); + } + } + } +#endif/* #if defined(MV_INCLUDE_USB) */ + +#if defined(MV_INCLUDE_XOR) + mvSysXorInit(); +#endif + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + //mv_set_power_scheme(); +#endif + + return; +} + + +/* + * Miscellaneous platform dependent initialisations + */ + +extern MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +extern MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); + +/* golabal mac address for yukon EC */ +unsigned char yuk_enetaddr[6]; + +extern int timer_init(void ); +extern void i2c_init(int speed, int slaveaddr); + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +/* TODO : Should disable this code after we finish debugging - we added this code to enable printing before console init */ +#if 1 + int clock_divisor = (CONFIG_SYS_TCLK / 16)/115200; + + /* muti-core support, initiate each Uart to each cpu */ + mvUartInit(whoAmI(), clock_divisor, mvUartBase(whoAmI())); +#endif + if (whoAmI() != 0) + return 0; + + mvCtrlUpdatePexId(); + +#ifdef CONFIG_FLASH_CFI_DRIVER + int portwidth; + MV_U32 devParam; +#endif +#if defined(MV_INCLUDE_TWSI) + MV_TWSI_ADDR slave; +#endif + MV_GPP_HAL_DATA *gppHalData; + + unsigned int i; + + maskAllInt(); + + /* must initialize the int in order for udelay to work */ + /* interrupt_init(); - no interrupt handling in u-boot */ + timer_init(); + + /* Init the Board environment module (device bank params init) */ + mvBoardEnvInit(); + +#if defined(MV_INCLUDE_TWSI) + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); +#endif + + /* Init the Controlloer environment module (MPP init) */ + mvCtrlEnvInit(); + + mvBoardDebugLed(2); + + /* Init the Controller CPU interface */ + mvCpuIfInit(mvCpuAddrWinMap); + + /* Init the GPIO sub-system */ + gppHalData->ctrlRev = mvCtrlRevGet(); + mvGppInit(gppHalData); + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = 3036; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* relocate the exception vectors */ + /* U-Boot is running from DRAM at this stage */ + for(i = 0; i < 0x100; i+=4) { + *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); + } + + /* Update NOR flash base address bank for CFI driver */ + +#ifdef CONFIG_FLASH_CFI_DRIVER + portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(0)); + devParam &= ~(DBP_DEVWIDTH_MASK); + switch (portwidth) { + case FLASH_CFI_8BIT: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case FLASH_CFI_16BIT: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case FLASH_CFI_32BIT: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + break; + } + MV_REG_WRITE(DEV_BANK_PARAM_REG(0),devParam); +#endif /* CONFIG_FLASH_CFI_DRIVER */ + + mvBoardDebugLed(4); + + return 0; +} + +void misc_init_r_env(void){ + char *env; + char tmp_buf[10]; + unsigned int malloc_len; + DECLARE_GLOBAL_DATA_PTR; + char buff[256]; + + env = getenv("console"); + if(!env) { +#ifdef RD_88F6510_SFU_ID + setenv("console","console=ttyS0,115200 mv_port1_config=disconnected"); +#else + setenv("console","console=ttyS0,115200"); +#endif + } + + /* update the CASset env parameter */ + env = getenv("CASset"); + if(!env ) { +#ifdef MV_MIN_CAL + setenv("CASset","min"); +#else + setenv("CASset","max"); +#endif + } + /* Monitor extension */ +#ifdef MV_INCLUDE_MONT_EXT + env = getenv("enaMonExt"); + if(/* !env || */ ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaMonExt","yes"); + else +#endif + setenv("enaMonExt","no"); + +#if defined (MV_INC_BOARD_NOR_FLASH) + env = getenv("enaFlashBuf"); + if( ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaFlashBuf","no"); + else + setenv("enaFlashBuf","yes"); +#endif + + /* CPU streaming */ + env = getenv("enaCpuStream"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaCpuStream","no"); + else + setenv("enaCpuStream","yes"); + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + setenv("enaWrAllo","yes"); + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + setenv("pexMode","RC"); + + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("disL2Cache","yes"); + else + setenv("disL2Cache","no"); + + env = getenv("MPmode"); + if(!env || ( (strcmp(env,"smp") == 0) || (strcmp(env,"SMP") == 0) ) ) + setenv("MPmode","SMP"); + else + setenv("MPmode","AMP"); + + /* Make address 0x80000000-0x8fffffff shared (set 'S' in pgd) */ + env = getenv("cacheShare"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("cacheShare","no"); + else + setenv("cacheShare","yes"); + + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("setL2CacheWT","no"); + else + setenv("setL2CacheWT","yes"); + + env = getenv("disL2Prefetch"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + setenv("disL2Prefetch","yes"); + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + else + { + setenv("disL2Prefetch","no"); + setenv("enaICPref","no"); + setenv("enaDCPref","no"); + } + + + env = getenv("sata_dma_mode"); + if( env && ((strcmp(env,"No") == 0) || (strcmp(env,"no") == 0) ) ) + setenv("sata_dma_mode","no"); + else + setenv("sata_dma_mode","yes"); + + + /* Malloc length */ + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0){ + sprintf(tmp_buf,"%d",CONFIG_SYS_MALLOC_LEN>>20); + setenv("MALLOC_len",tmp_buf); + } + + /* primary network interface */ + env = getenv("ethprime"); + if(!env) { +// if(mvBoardIdGet() == RD_88F6281A_ID) +// setenv("ethprime","egiga1"); +// else + setenv("ethprime",ENV_ETH_PRIME); + } + + /* netbsd boot arguments */ + env = getenv("netbsd_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) { + setenv("netbsd_en","no"); + } else { + setenv("netbsd_en","yes"); + env = getenv("netbsd_gw"); + if(!env) + setenv("netbsd_gw","192.168.0.254"); + env = getenv("netbsd_mask"); + if(!env) + setenv("netbsd_mask","255.255.255.0"); + + env = getenv("netbsd_fs"); + if(!env) + setenv("netbsd_fs","nfs"); + + env = getenv("netbsd_server"); + if(!env) + setenv("netbsd_server","192.168.0.1"); + + env = getenv("netbsd_ip"); + if(!env) { + env = getenv("ipaddr"); + setenv("netbsd_ip",env); + } + + env = getenv("netbsd_rootdev"); + if(!env) + setenv("netbsd_rootdev","mgi0"); + + env = getenv("netbsd_add"); + if(!env) + setenv("netbsd_add","0x800000"); + + env = getenv("netbsd_get"); + if(!env) + setenv("netbsd_get","tftpboot $netbsd_add $image_name"); + +#if defined(MV_INC_BOARD_QD_SWITCH) + env = getenv("netbsd_netconfig"); + if(!env) + setenv("netbsd_netconfig","mv_net_config=<((mgi0,00:00:11:22:33:44,0)(mgi1,00:00:11:22:33:55,1:2:3:4)),mtu=1500>"); +#endif + env = getenv("netbsd_set_args"); + if(!env) + setenv("netbsd_set_args","setenv bootargs nfsroot=$netbsd_server:$rootpath fs=$netbsd_fs \ + ip=$netbsd_ip serverip=$netbsd_server mask=$netbsd_mask gw=$netbsd_gw rootdev=$netbsd_rootdev \ + ethaddr=$ethaddr eth1addr=$eth1addr ethmtu=$ethmtu eth1mtu=$eth1mtu $netbsd_netconfig"); + + env = getenv("netbsd_boot"); + if(!env) + setenv("netbsd_boot","bootm $netbsd_add $bootargs"); + + env = getenv("netbsd_bootcmd"); + if(!env) + setenv("netbsd_bootcmd","run netbsd_get ; run netbsd_set_args ; run netbsd_boot"); + } + + /* vxWorks boot arguments */ + env = getenv("vxworks_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("vxworks_en","no"); + else { + char* buff = (char *)0x1100; + setenv("vxworks_en","yes"); + + sprintf(buff,"mgi(0,0) host:vxWorks.st"); + env = getenv("serverip"); + strcat(buff, " h="); + strcat(buff,env); + env = getenv("ipaddr"); + strcat(buff, " e="); + strcat(buff,env); + strcat(buff, ":ffff0000 u=anonymous pw=target "); + + setenv("vxWorks_bootargs",buff); + } + + /* linux boot arguments */ + env = getenv("bootargs_root"); + if(!env) + setenv("bootargs_root","root=/dev/nfs rw"); + + /* For open Linux we set boot args differently */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",":::orion:eth0:none"); + } else { + env = getenv("bootargs_end"); + if(!env) +#if defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootargs_end",MV_BOOTARGS_END_SWITCH); +#else + setenv("bootargs_end",MV_BOOTARGS_END); +#endif + } + + env = getenv("image_name"); + if(!env) + setenv("image_name","uImage"); + +#if (CONFIG_BOOTDELAY >= 0) + env = getenv("bootcmd"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000; "); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000; "); +#elif defined(MV_INCLUDE_TDM) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000; "); +#else + + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000; "); +#endif +#endif /* (CONFIG_BOOTDELAY >= 0) */ + + env = getenv("standalone"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000;"); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000;"); +#elif defined(MV_INCLUDE_TDM) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvPhoneConfig; bootm 0x2000000;"); +#else + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000;"); +#endif + + /* Set boodelay to 3 sec, if Monitor extension are disabled */ + if(!enaMonExt()) { + setenv("bootdelay","3"); + setenv("disaMvPnp","no"); + } + + /* Disable PNP config of Marvel memory controller devices. */ + env = getenv("disaMvPnp"); + if(!env) + setenv("disaMvPnp","no"); + +#if (defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH)) + /* Generate random ip and mac address */ + /* Read RTC to create pseudo-random data for enc */ + struct rtc_time tm; + unsigned int xi, xj, xk, xl, i; + char ethaddr_0[30]; + char ethaddr_1[30]; + char ethaddr_2[30]; + char ethaddr_3[30]; + char pon_addr[30]; + + rtc_get(&tm); + xi = ((tm.tm_yday + tm.tm_sec)% 254); + /* No valid ip with one of the fileds has the value 0 */ + if (xi == 0) + xi+=2; + + xj = ((tm.tm_yday + tm.tm_min)%254); + /* No valid ip with one of the fileds has the value 0 */ + if (xj == 0) + xj+=2; + + /* Check if the ip address is the same as the server ip */ + if ((xj == 1) && (xi == 11)) + xi+=2; + + xk = (tm.tm_min * tm.tm_sec)%254; + xl = (tm.tm_hour * tm.tm_sec)%254; + + sprintf(ethaddr_0,"00:50:43:%02x:%02x:%02x",xk,xi,xj); + sprintf(ethaddr_1,"00:50:43:%02x:%02x:%02x",xl,xi,xj); + sprintf(ethaddr_2,"00:50:43:%02x:%02x:%02x",xl,xk,xj); + sprintf(ethaddr_3,"00:50:43:%02x:%02x:%02x",xi,xk,xl); + sprintf(pon_addr,"00:50:43:%02x:%02x:%02x",xj,xk,xl); + + /* MAC addresses */ + env = getenv("ethaddr"); + if(!env) + setenv("ethaddr",ethaddr_0); + + env = getenv("eth1addr"); + if(!env) + setenv("eth1addr",ethaddr_1); + + env = getenv("eth2addr"); + if(!env) + setenv("eth2addr",ethaddr_2); + + env = getenv("eth3addr"); + if(!env) + setenv("eth3addr",ethaddr_3); + + env = getenv("mv_pon_addr"); + if(!env) + setenv("mv_pon_addr",pon_addr); + + env = getenv("ethmtu"); + if(!env) + setenv("ethmtu","1500"); + + env = getenv("eth1mtu"); + if(!env) + setenv("eth1mtu","1500"); + + env = getenv("eth2mtu"); + if(!env) + setenv("eth2mtu","1500"); + + env = getenv("eth3mtu"); + if(!env) + setenv("eth3mtu","1500"); + + /* Set mvNetConfig env parameter */ + env = getenv("mvNetConfig"); + if(!env ) { + switch (mvBoardIdGet()) { +#if defined(RD_88F6510_SFU_ID) || defined(RD_88F6530_MDU_ID) || defined(RD_88F6560_GW_ID) || defined(DB_88F6535_BP_ID) + case RD_88F6510_SFU_ID: + case RD_88F6530_MDU_ID: + setenv("mvNetConfig","mv_net_config=0"); + break; + case RD_88F6560_GW_ID: + case DB_88F6535_BP_ID: +#endif + default: + setenv("mvNetConfig","mv_net_config=4,(00:50:43:11:11:11,0:1:2:3),mtu=1500"); + break; + } + } +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(MV_INCLUDE_TDM) + /* Set mvPhoneConfig env parameter */ + env = getenv("mvPhoneConfig"); + if(!env ) + setenv("mvPhoneConfig","mv_phone_config=dev0:fxs,dev1:fxs"); +#endif + +#if defined(MV_INCLUDE_USB) + /* USB Host */ + env = getenv("usb0Mode"); + if(!env) + setenv("usb0Mode",ENV_USB0_MODE); + env = getenv("usb1Mode"); + if(!env) + setenv("usb1Mode",ENV_USB1_MODE); + env = getenv("usb2Mode"); + if(!env) + setenv("usb2Mode",ENV_USB2_MODE); +#endif /* (MV_INCLUDE_USB) */ + +#if defined(YUK_ETHADDR) + env = getenv("yuk_ethaddr"); + if(!env) + setenv("yuk_ethaddr",YUK_ETHADDR); + + { + int i; + char *tmp = getenv ("yuk_ethaddr"); + char *end; + + for (i=0; i<6; i++) { + yuk_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + } +#endif /* defined(YUK_ETHADDR) */ + +#if defined(MV_NAND) + env = getenv("nandEcc"); + if(!env) { + setenv("nandEcc", "1bit"); + } +#endif +#if 0 +#if defined(RD_88F6281A) || defined(RD_88F6192A) || defined(RD_88F6190A) + mvHddPowerCtrl(); +#endif +#endif +#if defined(CONFIG_CMD_RCVR) + env = getenv("netretry"); + if (!env) + setenv("netretry","no"); + + env = getenv("rcvrip"); + if (!env) + setenv("rcvrip",RCVR_IP_ADDR); + + env = getenv("loadaddr"); + if (!env) + setenv("loadaddr",RCVR_LOAD_ADDR); + + env = getenv("autoload"); + if (!env) + setenv("autoload","no"); + + /* Check the recovery trigger */ + recoveryDetection(); +#endif + env = getenv("eeeEnable"); + if (!env) + setenv("eeeEnable","no"); + + return; +} +#define MV_CPU_SW_RESET_CONTROL(cpu) (0x20800 + ((cpu) * 0x8)) + +void kick_next() { + int cpuNum; + MV_REG_WRITE(0x20988, 0x0); + MV_REG_WRITE(0x22224, 0x600000); + MV_REG_WRITE(0x22324, 0x600000); + MV_REG_WRITE(0x22424, 0x600000); + MV_REG_WRITE(0x22424, 0x600000); + MV_REG_WRITE(0x200b8, 0x07ff1d11); + + cpuNum = mvBoardCpuCoresNumGet()==2?(mvBoardCpuCoresNumGet()-1):(mvBoardCpuCoresNumGet()); + if (whoAmI() < cpuNum) { + MV_REG_WRITE(MV_CPU_SW_RESET_CONTROL(whoAmI()+1), 0x0); + } +} + +#ifdef BOARD_LATE_INIT +int board_late_init (void) +{ + char *env; + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ + + env = getenv("enaMP"); + if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + kick_next(); + + mvBoardDebugLed(0); + return 0; +} +#endif + +void pcie_tune(void) +{ + MV_REG_WRITE(0xF1041AB0, 0x100); + MV_REG_WRITE(0xF1041A20, 0x78000801); + MV_REG_WRITE(0xF1041A00, 0x4014022F); + MV_REG_WRITE(0xF1040070, 0x18110008); + + return; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_MARVELL +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) + /* move to the begining so in case we have a PCI NIC it will + read the env mac addresses correctlly. */ + mv_eth_initialize(bis); +#endif +#endif +#if defined(CONFIG_SK98) + skge_initialize(bis); +#endif +#if defined(CONFIG_E1000) + e1000_initialize(bis); +#endif + return 0; +} + +int print_cpuinfo (void) +{ + char name[50]; + + mvBoardNameGet(name); + printf("Board: %s\n", name); + mvCtrlModelRevNameGet(name); + printf("SoC: %s\n", name); + if (mvCtrlModelRevGet() != MV_6710_Z1_ID) + printf(" running %d CPUs\n", mvCtrlGetCpuNum()+1); + if (!mvCtrlIsValidSatR()) + printf(" Custom configuration\n"); + mvCpuNameGet(name); + printf("CPU: %s", name); +#ifdef MV_CPU_LE + printf(" LE\n"); +#else + printf(" BE\n"); +#endif + if (mvCtrlModelRevGet() != MV_6710_Z1_ID) + printf(" CPU # %d\n", whoAmI()); + printf(" CPU @ %dMhz, L2 @ %dMhz\n", mvCpuPclkGet()/1000000, mvCpuL2ClkGet()/1000000); + printf(" DDR @ %dMhz, TClock @ %dMhz\n", CONFIG_SYS_BUS_CLK/1000000, mvTclkGet()/1000000); + printf(" DDR %dBit Width, %s Memory Access\n", mvCtrlDDRBudWidth(), mvCtrlDDRThruXbar()?"XBAR":"FastPath"); + return 0; +} +int misc_init_r (void) +{ + char *env; + + mvBoardDebugLed(5); + + /* init special env variables */ + misc_init_r_env(); + + mv_cpu_init(); + +#if defined(MV_INCLUDE_MONT_EXT) + if(enaMonExt()) { + printf("Marvell monitor extension:\n"); + mon_extension_after_relloc(); + } +#endif /* MV_INCLUDE_MONT_EXT */ + + /* print detected modules */ +// mvMppModuleTypePrint(); + + /* init the units decode windows */ + misc_init_r_dec_win(); + +#if 0 +#ifdef CONFIG_PCI +#if !defined(MV_MEM_OVER_PCI_WA) && !defined(MV_MEM_OVER_PEX_WA) + pci_init(); +#endif +#endif +#endif + mvBoardDebugLed(6); + /* Prints the modules detected */ + mvBoardMppModuleTypePrint(); + + mvBoardDebugLed(7); + + /* pcie fine tunning */ + env = getenv("pcieTune"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"yes") == 0))) + pcie_tune(); + else + setenv("pcieTune","no"); + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + /* Init the PHY or Switch of the board */ + mvBoardEgigaPhyInit(); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + + return 0; +} + +MV_U32 mvTclkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->tclk == 0) + gd->tclk = mvBoardTclkGet(); + + return gd->tclk; +} + +MV_U32 mvSysClkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->bus_clk == 0) + gd->bus_clk = mvBoardSysClkGet(); + + return gd->bus_clk; +} + +/* exported for EEMBC */ +MV_U32 mvGetRtcSec(void) +{ + MV_RTC_TIME time; +#ifdef MV_INCLUDE_RTC + mvRtcTimeGet(&time); +#elif CONFIG_RTC_DS1338_DS1339 + mvRtcDS133xTimeGet(&time); +#endif + return (time.minutes * 60) + time.seconds; +} + +void reset_cpu (ulong addr) +{ + mvBoardReset(); +} + +void mv_cpu_init(void) +{ + char *env; + volatile unsigned int temp; + + /* enable access to CP10 and CP11 */ + temp = 0x00f00000; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 2" :: "r" (temp)); + + env = getenv("enaFPU"); + if((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0)){ + /* init and Enable FPU to Run Fast Mode */ + printf("FPU initialized to Run Fast Mode.\n"); + /* Enable */ + temp = FPEXC_ENABLE; + fmxr(FPEXC, temp); + /* Run Fast Mode */ + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + fmxr(FPSCR, temp); + }else{ + printf("FPU not initialized\n"); + /* Disable */ + temp = fmrx(FPEXC); + temp &= ~FPEXC_ENABLE; + fmxr(FPEXC, temp); + } + + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 1" : "=r" (temp)); + temp |= BIT16; /* Disable reac clean intv */ + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 2" : "=r" (temp)); + temp |= (BIT25 | BIT27 | BIT29 | BIT30); + /* removed BIT23 in order to enable fast LDR bypass */ + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 2\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + /* Enable speculative read miss from L1 to "line fill" L1 */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + + env = getenv("L1SpeculativeEn"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + temp |= BIT7; + else{ + temp &= ~BIT7; + } + + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + /* Multi-CPU managment */ + env = getenv("enaMP"); + if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + { + env = getenv("MPmode"); + if( (strcmp(env,"AMP") == 0) || (strcmp(env,"amp") == 0) ) + { + /* Set AMP in Auxilary control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (temp)); + temp &= ~(0x1 << 5); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Set AMP in Auxiliary Funcional Modes Control register */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + temp &= ~(0x1 << 1); + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + } + else + { + /* Set SMP in Auxilary control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (temp)); + temp |= (0x1 << 5); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Set SMP in Auxiliary Funcional Modes Control register */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + temp |= (0x1 << 1); + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Enable CPU respond to coherency fabric requests */ + /* Assaf: Note must be enabled for IO coherency as well */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CTRL_REG, (0x1 << (24 + whoAmI()))); + + /* Configure all Cores to be in SMP Group0 */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, (0x1 << (24 + whoAmI()))); + + /* In loader mode, set fabric regs for both CPUs.*/ + + env = getenv("enaMonExt"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) { + + /* Configure Core1 to be in SMP Group0 */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, (0x1 << 25)); + } + + /* Set number of CPUs=2 (for Linux) */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, 0x1); + } + } + +#if 1 + /* Set L2C WT mode */ + temp = MV_REG_READ(CPU_L2_AUX_CTRL_REG) & ~CL2ACR_WB_WT_ATTR_MASK; + env = getenv("setL2CacheWT"); + if(!env || ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) { + temp |= CL2ACR_WB_WT_ATTR_WT; + } + MV_REG_WRITE(CPU_L2_AUX_CTRL_REG, temp); +#endif + + /* enable L2C */ + temp = MV_REG_READ(CPU_L2_CTRL_REG); + + env = getenv("disL2Cache"); + if(!env || ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + temp |= CL2CR_L2_EN_MASK; + else + temp &= ~CL2CR_L2_EN_MASK; + + MV_REG_WRITE(CPU_L2_CTRL_REG, temp); + + /* Configure L2 options if L2 exists */ + if (MV_REG_READ(CPU_L2_CTRL_REG) & CL2CR_L2_EN_MASK) { + + /* Read L2 Auxilary control register */ + temp = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + /* Clear fields */ + temp &= ~(CL2ACR_WB_WT_ATTR_MASK | CL2ACR_FORCE_WA_MASK); + + /* Set "Force write policy" field */ + env = getenv("L2forceWrPolicy"); + if( (strcmp(env,"WB") == 0) || (strcmp(env,"wb") == 0) ) + temp |= CL2ACR_WB_WT_ATTR_WB; + else if( (strcmp(env,"WT") == 0) || (strcmp(env,"wt") == 0) ) + temp |= CL2ACR_WB_WT_ATTR_WT; + else + temp |= CL2ACR_WB_WT_ATTR_PAGE; + + /* Set "Force Write Allocate" field */ + env = getenv("L2forceWrAlloc"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + temp |= CL2ACR_FORCE_NO_WA; + else if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + temp |= CL2ACR_FORCE_WA; + else + temp |= CL2ACR_FORCE_WA_DISABLE; + + /* Set "ECC" */ + env = getenv("L2EccEnable"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp &= ~CL2ACR_ECC_EN; + else + temp |= CL2ACR_ECC_EN; + + /* Set other L2 configurations */ + temp |= (CL2ACR_PARITY_EN | CL2ACR_INVAL_UCE_EN); + + /* Write to L2 Auxilary control register */ + MV_REG_WRITE(CPU_L2_AUX_CTRL_REG, temp); + + env = getenv("L2SpeculativeRdEn"); + if((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + MV_REG_BIT_SET(0x20228, ((0x1 << 5))); + else + MV_REG_BIT_RESET(0x20228, ((0x1 << 5))); + + } + + /* Enable i cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (temp)); + temp |= BIT12; + /* Change reset vector to address 0x0 */ + temp &= ~BIT13; + asm ("mcr p15, 0, %0, c1, c0, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Disable MBUS Err Prop - inorder to avoid data aborts */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); +} +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +#if 0 +MV_VOID mvMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + if(devId != MV_6190_DEV_ID) + printf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TS\n", devClass); + break; + case MV_BOARD_MII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is MII\n", devClass); + break; + default: + break; + } + } +} +#endif + +/* Set unit in power off mode acording to the detection of MPP/SERDES */ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void) +{ + MV_U32 devId = mvCtrlModelGet(); + MV_U32 boardId = mvBoardIdGet(); + MV_BOARD_PEX_INFO *pexInfo = mvBoardPexInfoGet(); + MV_U32 unit, lane, pexIf; + + mvOsOutput("Shutting down unused interfaces:\n"); + + /* SERDES modules */ + if (mvBoardIsPexModuleConnected() == MV_TRUE) { +#if 1 /* TODO - check if SATA should be disabled if PEX(1) module is used */ + /* Sata */ + mvOsOutput(" SATA0\n"); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + mvOsOutput(" SATA1\n"); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); +#endif + /* Ethernet (SGMII/QSGMII) */ + mvOsOutput(" GBE2\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 2, MV_FALSE); + mvOsOutput(" GBE3\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 3, MV_FALSE); + } + + /* MPP modules */ + if (mvBoardIsLcdDviModuleConnected() == MV_TRUE) { + /* Ethernet (RGMII) */ + mvOsOutput(" GBE0\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 0, MV_FALSE); + mvOsOutput(" GBE1\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + } + + /* TDM */ + if(mvBoardTdmDevicesCountGet() == 0) { + mvOsOutput(" TDM\n"); + mvCtrlPwrClckSet(TDM_32CH_UNIT_ID, 0, MV_FALSE); + } + + /* PEX */ + pexIf = 0; + for (unit = 0; unit < mvCtrlPexMaxUnitGet(); unit++) { + if (pexInfo->pexUnitCfg[unit].pexCfg == PEX_BUS_DISABLED) { + if (unit < 2) {/* PEX unit 0,1 */ + for (lane = 0; lane < 4; lane++) { + mvOsOutput(" PEX%d.%d(%d)\n", unit, lane, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } else { /* PEX unit 2,3 */ + mvOsOutput(" PEX%d.0(%d)\n", unit, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } else if (pexInfo->pexUnitCfg[unit].pexCfg == PEX_BUS_MODE_X1) { + for (lane = 0; lane < 4; lane++) { + if (pexInfo->pexUnitCfg[unit].pexLaneStat[lane] != 1) { + mvOsOutput(" PEX%d.%d(%d)\n", unit, lane, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + } + pexIf++; + } + } else { /* x4 or x8 */ + mvOsOutput(" PEX%d.0(%d)\n", unit,pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } + +} +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +#if 0 +/******************************************************************************* +* mvHddPowerCtrl - +* +* DESCRIPTION: +* This function set HDD power on/off acording to env or wait for button push +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +static void mvHddPowerCtrl(void) +{ + MV_32 hddPowerBit; + MV_32 fanPowerBit; + MV_32 hddHigh = 0; + MV_32 fanHigh = 0; + char* env; + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + hddPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_HDD_POWER, 0); + fanPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_FAN_POWER, 0); + if (hddPowerBit > 31) + { + hddPowerBit = hddPowerBit % 32; + hddHigh = 1; + } + if (fanPowerBit > 31) + { + fanPowerBit = fanPowerBit % 32; + fanHigh = 1; + } + } + + if ((RD_88F6281A_ID == mvBoardIdGet()) || (RD_88F6192A_ID == mvBoardIdGet()) || + (RD_88F6190A_ID == mvBoardIdGet())) + { + env = getenv("hddPowerCtrl"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("hddPowerCtrl","no"); + else + setenv("hddPowerCtrl","yes"); + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + mvBoardFanPowerControl(MV_TRUE); + mvBoardHDDPowerControl(MV_TRUE); + } + else + { + /* FAN power on */ + MV_REG_BIT_SET(GPP_DATA_OUT_REG(fanHigh),(1<> 4)) +#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4)) + +/* NAND Flash Chip Capability */ +#ifdef MV_LARGE_PAGE +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 64 +#define PAGE_SIZE 2048 /* Bytes */ +#define SPARE_SIZE 64 +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#else /* ! LARGE PAGE NAND */ +/* NAND Flash Chip Capability */ +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 32 +#define PAGE_SIZE 512 /* Bytes */ +#define SPARE_SIZE 16 +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#endif + +/* NAND Flash Command. This appears to be generic across all NAND flash chips */ +#define CMD_READ 0x00 /* Read */ +#define CMD_READ1 0x01 /* Read1 */ +#define CMD_READ2 0x50 /* Read2 */ +#define CMD_START_READ 0x30 /* Read command after write addr */ +#define CMD_READID 0x90 /* ReadID */ +#define CMD_READID2 0x91 /* Read extended ID */ +#define CMD_WRITE 0x80 /* Write phase 1 */ +#define CMD_WRITE2 0x10 /* Write phase 2 */ +#define CMD_ERASE 0x60 /* Erase phase 1 */ +#define CMD_ERASE2 0xd0 /* Erase phase 2 */ +#define CMD_STATUS 0x70 /* Status read */ +#define CMD_RESET 0xff /* Reset */ + +/* Status bit pattern */ +#define STATUS_READY 0x40 /* Ready */ +#define STATUS_ERROR 0x01 /* Error */ + + +#define NFLASH_DEV_WIDTH 8 +#ifdef MV_LARGE_PAGE +#define BOOTER_PAGE_NUM 2 +#define BOOTER_BASE 0x00020000 + PAGE_SIZE +#else +#define BOOTER_PAGE_NUM 5 +#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE) +#endif /* MV_LARGE_PAGE */ +#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) + +#undef INTER_REGS_BASE +#define INTER_REGS_BASE 0xd0000000 + + +#if defined(MV_BOOTROM) +#if defined(MV_88F6082) +#define NAND_FLASH_BASE 0xD8000000 +#endif +#if defined(MV_88F5182) +#define NAND_FLASH_BASE 0xf0000000 +#endif +#else +#define NAND_FLASH_BASE 0xffff0000 +#endif /* defined(MV_BOOTROM) */ + +#if 0 +#define NBOOT_UART_CHAN 0 +#define NBOOT_BAUDRATE 115200 +#define NBOOT_TIMER_NUM 0 + + +/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */ +#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */ + +/* Load General Purpose Register (GPR) with 32-bit constant value */ +#define GPR_LOAD(reg, val) \ + mov reg, $(val & 0xFF) ;\ + orr reg, reg, $(val & 0xFF00) ;\ + orr reg, reg, $(val & 0xFF0000) ;\ + orr reg, reg, $(val & 0xFF000000) + +/* Register Read/Write */ +#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \ + ldr toReg, [baseReg, $(regOffs & 0xFFF)] + +#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \ + str fromReg, [baseReg, $(regOffs & 0xFFF)] + + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_32BIT_LE(X) (X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif +#endif + +#endif /* __INCnBootstraph */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap_LP.S u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap_LP.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap_LP.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap_LP.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,335 @@ +#define MV_ASMLANGUAGE +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "nBootstrap.h" + + +/* #define NAND_DEBUG */ +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + +#ifdef NAND_CTRL_88F528x + + /* Load CPU controller base address 0xD0020000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x20000 + + MV_REG_READ_ASM (r1, r2, INTER_REGS_BASE + 0x20120) + bic r1, r1, #MV_32BIT_LE(0x7F00) + orr r1, r1, #MV_32BIT_LE(0x8200) + bic r1, r1, #MV_32BIT_LE(0x007F) + orr r1, r1, #MV_32BIT_LE(0x001b) + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x20120) + + /* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */ + MV_REG_READ_ASM (r1, r2, INTER_REGS_BASE + 0x20100) + bic r1, r1, #MV_32BIT_LE(0xFF00) + orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK) + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x20100) + +#endif /* NAND_CTRL_88F528x */ + + /* lock I-Cache */ + mrc p15, 0, r8, c9, c0, 1 + orr r8, r8, #0xf + mcr p15, 0, r8, c9, c0, 1 + + /* Start load code into I-Cache */ + mov r2, #0x500 + mov r8, pc +.align 5 + bic r8, #0x1f + add r8, r8, #32 +load_loop: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0xf0ffffff + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x104) + mov r1, #0x1000000 + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x100) +#endif + + /* DRAM memory initialization */ + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Write to SDRAM coniguration register */ +#ifndef MV_88W8660 + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) +#else + GPR_LOAD(r1, MV_32BIT_LE((SDRAM_CONFIG_REG_DV & ~(0x40)))) +#endif /* MV_88W8660 */ + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG) + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 registers pad calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_CONFIG_REG) + tst r1, #SDRAM_DTYPE_DDR2 + beq ddr1PadCal + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV) + b next + +ddr1PadCal: + mov r3, #MV_32BIT_LE(DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR1_DATA_PAD_STRENGTH_TYPICAL_DV) + +next: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r1, r3, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r1, r4, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + +#ifndef MV_88W8660 + /* Write Dunit FTDLL Configuration Register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_FTDLL_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_FTDLL_CONFIG_REG) +#endif /* MV_88W8660 */ + + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0)) + + /* Close SDRAM bank 1,2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #BOOTER_BASE + +#ifdef DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* init */ + mov r2, #0x1 /* start with page 1 */ + mov r3, #BOOTER_BASE /* start of DRAM buffer */ + GPR_LOAD(r5, NAND_FLASH_BASE) + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r7, #CMD_START_READ + mov r9, #CMD_RESET + mov r4, #PAGE_SIZE /* Byte counter */ + + +startRead: + /* issue reset command */ + strb r9, [r5, #NAND_CMD_PORT] + + mov r9, #0x1000000 +loop_delay1: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay1 + + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r7, [r5, #NAND_CMD_PORT] + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x3000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + /* Delay of at least 25uSec (NAND flash tR) */ + mov r9, #0x1000000 +loop_delay3: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay3 + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x4000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + + /* now perform reading */ + mov r0, r5 + +copy_loop1: + sub r4, r4, #16 /* 4 dwords * 4 bytes */ + ldmia r0!, {r6-r9} + stmia r3!, {r6-r9} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x5000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* Set up the stack */ +stack_setup: + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + /* jump to new code */ + mov pc, lr + +.align 10 +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nandBoot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap.S u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,20 @@ +#define MV_ASMLANGUAGE +#include "nBootstrap.h" + + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + ldr r0, =BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nand_boot + mov pc, lr diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/platform.S u-boot-2009.08/board/marvell/mv_armada_xp/platform.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/platform.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/platform.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,95 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include +#include +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvAhbToMbusRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCtrlEnvAsm.h" + +.globl lowlevel_init + +/************************************************/ +/* lowlevel_init * +/************************************************/ + +lowlevel_init: + mov r2, lr + + /* Multicore support */ + mrc p15, 0, r0, c0, c0, 5 + /* Check if we are CPU0 or CPU1 */ + cmp r0, #0x0 + bne done_cpu1 + +#if 0 + /* change CPU0 reg base to 0xf1000000 */ + + /* First descrease size of CS[2] to prevent overlap with 0xF100.0000 */ + MV_DV_REG_READ_ASM(r4, r1, 0x200B0) + bic r4, r4, #0x07F00000 + MV_DV_REG_WRITE_ASM(r4, r1, 0x200B0) + + ldr r4, =MV_REGS + MV_DV_REG_WRITE_ASM(r4, r1, 0x20080) + /* This is kind of barrier... */ + ldr r4, =MV_REGS + MV_REG_WRITE_ASM (r4, r1, 0x20080) + + /* Set 7-Segment to '1' */ + /* By default, 7-segment connected to CS[2] base 0xF000.000 */ + mov r4, #0xf0000000 + ldr r4, [r4, #(1 << 4)] +#endif + +#if defined(MV_STATIC_DRAM_ON_BOARD) +/* TODO: alior: we still not supporting non bootrom mode on u-boot */ + bl _mvDramIfStaticInit + + bl _mvDramIfBasicInit +#endif + bl done + +done: + +#ifdef CFU_DRAM_BYPASS + /* allow accessing to DRAM from XBAR */ + ldr r4, =0x1fff0e01 /* Set DRAM CS[0] size in P-unit (default) */ + MV_REG_WRITE_ASM(r4, r1, 0x200e8) + ldr r4, =0x20000000 /* Set DRAM CS[1] base in P-unit */ + MV_REG_WRITE_ASM(r4, r1, 0x200e4) + ldr r4, =0x1fff0d01 /* Set DRAM CS[1] size in P-unit */ + MV_REG_WRITE_ASM(r4, r1, 0x200e0) +#endif + + /* Set 7-Segment to '2' */ + /* By default, 7-segment connected to CS[2] base 0xF000.000 */ + mov r4, #0xf0000000 + ldr r4, [r4, #(2 << 4)] + + mov lr, r2 + +done_cpu1: + mov pc, lr + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.c u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,341 @@ +/* rijndael-alg-ref.c v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvAesAlg.h" +#include "mvAesBoxes.dat" + +MV_U8 mul1(MV_U8 aa, MV_U8 bb); +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); +void ShiftRow128Enc(MV_U8 a[4][MAXBC]); +void ShiftRow128Dec(MV_U8 a[4][MAXBC]); +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); +void InvMixColumn(MV_U8 a[4][MAXBC]); + +#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) + +MV_U8 mul1(MV_U8 aa, MV_U8 bb) +{ + return mask[bb] & Alogtable[aa + Logtable[bb]]; +} + +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) +{ + /* Exor corresponding text input and round key input bytes + */ + ((MV_U32 *) (&(a[0][0])))[0] ^= ((MV_U32 *) (&(rk[0][0])))[0]; + ((MV_U32 *) (&(a[1][0])))[0] ^= ((MV_U32 *) (&(rk[1][0])))[0]; + ((MV_U32 *) (&(a[2][0])))[0] ^= ((MV_U32 *) (&(rk[2][0])))[0]; + ((MV_U32 *) (&(a[3][0])))[0] ^= ((MV_U32 *) (&(rk[3][0])))[0]; + +} + +void ShiftRow128Enc(MV_U8 a[4][MAXBC]) +{ + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][1]; + tmp[1] = a[1][2]; + tmp[2] = a[1][3]; + tmp[3] = a[1][0]; + + ((MV_U32 *) (&(a[1][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32 *) (&(a[2][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + tmp[0] = a[3][3]; + tmp[1] = a[3][0]; + tmp[2] = a[3][1]; + tmp[3] = a[3][2]; + + ((MV_U32 *) (&(a[3][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void ShiftRow128Dec(MV_U8 a[4][MAXBC]) +{ + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][3]; + tmp[1] = a[1][0]; + tmp[2] = a[1][1]; + tmp[3] = a[1][2]; + + ((MV_U32 *) (&(a[1][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32 *) (&(a[2][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + + tmp[0] = a[3][1]; + tmp[1] = a[3][2]; + tmp[2] = a[3][3]; + tmp[3] = a[3][0]; + + ((MV_U32 *) (&(a[3][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) +{ + /* Replace every byte of the input by the byte at that place + * in the nonlinear S-box + */ + int i, j; + + for (i = 0; i < 4; i++) + for (j = 0; j < 4; j++) + a[i][j] = box[a[i][j]]; +} + +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) +{ + /* Mix the four bytes of every column in a linear way + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for (j = 0; j < 4; j++) { + b[0][j] = mul(25, a[0][j]) ^ mul(1, a[1][j]) ^ a[2][j] ^ a[3][j]; + b[1][j] = mul(25, a[1][j]) ^ mul(1, a[2][j]) ^ a[3][j] ^ a[0][j]; + b[2][j] = mul(25, a[2][j]) ^ mul(1, a[3][j]) ^ a[0][j] ^ a[1][j]; + b[3][j] = mul(25, a[3][j]) ^ mul(1, a[0][j]) ^ a[1][j] ^ a[2][j]; + } + for (i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j]; */ + ((MV_U32 *)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; +} + +void InvMixColumn(MV_U8 a[4][MAXBC]) +{ + /* Mix the four bytes of every column in a linear way + * This is the opposite operation of Mixcolumn + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for (j = 0; j < 4; j++) { + b[0][j] = mul(223, a[0][j]) ^ mul(104, a[1][j]) ^ mul(238, a[2][j]) ^ mul(199, a[3][j]); + b[1][j] = mul(223, a[1][j]) ^ mul(104, a[2][j]) ^ mul(238, a[3][j]) ^ mul(199, a[0][j]); + b[2][j] = mul(223, a[2][j]) ^ mul(104, a[3][j]) ^ mul(238, a[0][j]) ^ mul(199, a[1][j]); + b[3][j] = mul(223, a[3][j]) ^ mul(104, a[0][j]) ^ mul(238, a[1][j]) ^ mul(199, a[2][j]); + } + for (i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j]; */ + ((MV_U32 *) (&(a[i][0])))[0] = ((MV_U32 *) (&(b[i][0])))[0]; +} + +int rijndaelKeySched(MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS + 1][4][MAXBC]) +{ + /* Calculate the necessary round keys + * The number of calculations depends on keyBits and blockBits + */ + int KC, BC, ROUNDS; + int i, j, t, rconpointer = 0; + MV_U8 tk[4][MAXKC]; + + switch (keyBits) { + case 128: + KC = 4; + break; + case 192: + KC = 6; + break; + case 256: + KC = 8; + break; + default: + return (-1); + } + + switch (blockBits) { + case 128: + BC = 4; + break; + case 192: + BC = 6; + break; + case 256: + BC = 8; + break; + default: + return (-2); + } + + switch (keyBits >= blockBits ? keyBits : blockBits) { + case 128: + ROUNDS = 10; + break; + case 192: + ROUNDS = 12; + break; + case 256: + ROUNDS = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + for (j = 0; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] = k[i][j]; + t = 0; + /* copy values into round key array */ + for (j = 0; (j < KC) && (t < (ROUNDS + 1) * BC); j++, t++) + for (i = 0; i < 4; i++) + W[t / BC][i][t % BC] = tk[i][j]; + + while (t < (ROUNDS + 1) * BC) { /* while not enough round key material calculated */ + /* calculate new values */ + for (i = 0; i < 4; i++) + tk[i][0] ^= S[tk[(i + 1) % 4][KC - 1]]; + tk[0][0] ^= rcon[rconpointer++]; + + if (KC != 8) + for (j = 1; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + else { + for (j = 1; j < KC / 2; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + for (i = 0; i < 4; i++) + tk[i][KC / 2] ^= S[tk[i][KC / 2 - 1]]; + for (j = KC / 2 + 1; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + } + /* copy values into round key array */ + for (j = 0; (j < KC) && (t < (ROUNDS + 1) * BC); j++, t++) + for (i = 0; i < 4; i++) + W[t / BC][i][t % BC] = tk[i][j]; + } + + return 0; +} + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds) +{ + /* Encryption of one block. + */ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* begin with a key addition + */ + + KeyAddition(a, rk[0], BC); + + /* ROUNDS-1 ordinary rounds + */ + for (r = 1; r < ROUNDS; r++) { + Substitution(a, S); + ShiftRow128Enc(a); + MixColumn(a, rk[r]); + /*KeyAddition(a,rk[r],BC); */ + } + + /* Last round is special: there is no MixColumn + */ + Substitution(a, S); + ShiftRow128Enc(a); + KeyAddition(a, rk[ROUNDS], BC); + + return 0; +} + +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds) +{ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* To decrypt: apply the inverse operations of the encrypt routine, + * in opposite order + * + * (KeyAddition is an involution: it 's equal to its inverse) + * (the inverse of Substitution with table S is Substitution with the inverse table of S) + * (the inverse of Shiftrow is Shiftrow over a suitable distance) + */ + + /* First the special round: + * without InvMixColumn + * with extra KeyAddition + */ + KeyAddition(a, rk[ROUNDS], BC); + ShiftRow128Dec(a); + Substitution(a, Si); + + /* ROUNDS-1 ordinary rounds + */ + for (r = ROUNDS - 1; r > 0; r--) { + KeyAddition(a, rk[r], BC); + InvMixColumn(a); + ShiftRow128Dec(a); + Substitution(a, Si); + + } + + /* End with the extra key addition + */ + + KeyAddition(a, rk[0], BC); + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.h u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,24 @@ +/* rijndael-alg-ref.h v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + */ +#ifndef __RIJNDAEL_ALG_H +#define __RIJNDAEL_ALG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXBC (128/32) +#define MAXKC (256/32) +#define MAXROUNDS 14 + + int rijndaelKeySched(MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS + 1][4][MAXBC]); + int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds); + int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds); + +#ifdef __cplusplus +} +#endif +#endif /* __RIJNDAEL_ALG_H */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesApi.c u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesApi.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesApi.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesApi.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,270 @@ +/* rijndael-api-ref.c v2.1 April 2000 + * Reference ANSI C code + * authors: v2.0 Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * v2.1 Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvCommon.h" +#include "mvOs.h" + +#include "mvAes.h" +#include "mvAesAlg.h" + +/* Defines: + Add any additional defines you need +*/ + +#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ +#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ +#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ + +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) +{ + MV_U8 W[MAXROUNDS + 1][4][MAXBC]; + MV_U8 k[4][MAXKC]; + MV_U8 j; + int i, rounds, KC; + + if (expandedKey == NULL) + return AES_BAD_KEY_INSTANCE; + + if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) + return AES_BAD_KEY_MAT; + + if (keyMaterial == NULL) + return AES_BAD_KEY_MAT; + + /* initialize key schedule: */ + for (i = 0; i < keyLen / 8; i++) { + j = keyMaterial[i]; + k[i % 4][i / 4] = j; + } + + rijndaelKeySched(k, keyLen, blockLen, W); +#ifdef MV_AES_DEBUG + { + MV_U8 *pW = &W[0][0][0]; + int x; + + mvOsPrintf("Expended Key: size = %d\n", sizeof(W)); + for (i = 0; i < sizeof(W); i++) + mvOsPrintf("%02x ", pW[i]); + + for (i = 0; i < MAXROUNDS + 1; i++) { + mvOsPrintf("\n Round #%02d: ", i); + for (x = 0; x < MAXBC; x++) + mvOsPrintf("%02x%02x%02x%02x ", W[i][0][x], W[i][1][x], W[i][2][x], W[i][3][x]); + mvOsPrintf("\n"); + } + } +#endif /* MV_AES_DEBUG */ + switch (keyLen) { + case 128: + rounds = 10; + KC = 4; + break; + case 192: + rounds = 12; + KC = 6; + break; + case 256: + rounds = 14; + KC = 8; + break; + default: + return (-1); + } + + for (i = 0; i < MAXBC; i++) + for (j = 0; j < 4; j++) + expandedKey[i * 4 + j] = W[rounds][j][i]; + + for (; i < KC; i++) + for (j = 0; j < 4; j++) + expandedKey[i * 4 + j] = W[rounds - 1][j][i + MAXBC - KC]; + + return 0; +} + +int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher) +{ + int i, j, t; + MV_U8 block[4][MAXBC]; + int rounds; + char *input, *outBuffer; + + input = (char *)plain; + outBuffer = (char *)cipher; + + /* check parameter consistency: */ + if ((expandedKey == NULL) || ((keyLen != 128) && (keyLen != 192) && (keyLen != 256))) + return AES_BAD_KEY_MAT; + + if ((mode != MODE_ECB && mode != MODE_CBC)) + return AES_BAD_CIPHER_STATE; + + switch (keyLen) { + case 128: + rounds = 10; + break; + case 192: + rounds = 12; + break; + case 256: + rounds = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + switch (mode) { + case MODE_ECB: + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse input stream into rectangular array */ + block[t][j] = input[16 * i + 4 * j + t] & 0xFF; + } + rijndaelEncrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + case MODE_CBC: + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse initial value into rectangular array */ + block[t][j] = IV[t + 4 * j] & 0xFF; + } + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse input stream into rectangular array and exor with + IV or the previous ciphertext */ + block[t][j] ^= input[16 * i + 4 * j + t] & 0xFF; + } + rijndaelEncrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + default: + return AES_BAD_CIPHER_STATE; + } + + return 0; +} + +int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *srcData, int numBlocks, MV_U32 *dstData) +{ + int i, j, t; + MV_U8 block[4][MAXBC]; + MV_U8 iv[4][MAXBC]; + int rounds; + char *input, *outBuffer; + + input = (char *)srcData; + outBuffer = (char *)dstData; + + if (expandedKey == NULL) + return AES_BAD_KEY_MAT; + + /* check parameter consistency: */ + if (keyLen != 128 && keyLen != 192 && keyLen != 256) + return AES_BAD_KEY_MAT; + + if ((mode != MODE_ECB && mode != MODE_CBC)) + return AES_BAD_CIPHER_STATE; + + switch (keyLen) { + case 128: + rounds = 10; + break; + case 192: + rounds = 12; + break; + case 256: + rounds = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + switch (mode) { + case MODE_ECB: + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + block[t][j] = input[16 * i + 4 * j + t] & 0xFF; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + case MODE_CBC: + /* first block */ + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + block[t][j] = input[4 * j + t] & 0xFF; + iv[t][j] = block[t][j]; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + + for (j = 0; j < 4; j++) { + /* exor the IV and parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) { + outBuffer[4 * j + t] = (MV_U8) (block[t][j] ^ IV[t + 4 * j]); + IV[t + 4 * j] = iv[t][j]; + } + } + + /* next blocks */ + for (i = 1; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + iv[t][j] = input[16 * i + 4 * j + t] & 0xFF; + block[t][j] = iv[t][j]; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + + for (j = 0; j < 4; j++) { + /* exor previous ciphertext block and parse rectangular array + into output ciphertext bytes */ + for (t = 0; t < 4; t++) { + outBuffer[16 * i + 4 * j + t] = (MV_U8) (block[t][j] ^ IV[t + 4 * j]); + IV[t + 4 * j] = iv[t][j]; + } + } + } + break; + + default: + return AES_BAD_CIPHER_STATE; + } + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,125 @@ +static MV_U8 mask[256] = { + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static MV_U8 Logtable[256] = { + 0, 0, 25, 1, 50, 2, 26, 198, 75, 199, 27, 104, 51, 238, 223, 3, + 100, 4, 224, 14, 52, 141, 129, 239, 76, 113, 8, 200, 248, 105, 28, 193, + 125, 194, 29, 181, 249, 185, 39, 106, 77, 228, 166, 114, 154, 201, 9, 120, + 101, 47, 138, 5, 33, 15, 225, 36, 18, 240, 130, 69, 53, 147, 218, 142, + 150, 143, 219, 189, 54, 208, 206, 148, 19, 92, 210, 241, 64, 70, 131, 56, + 102, 221, 253, 48, 191, 6, 139, 98, 179, 37, 226, 152, 34, 136, 145, 16, + 126, 110, 72, 195, 163, 182, 30, 66, 58, 107, 40, 84, 250, 133, 61, 186, + 43, 121, 10, 21, 155, 159, 94, 202, 78, 212, 172, 229, 243, 115, 167, 87, + 175, 88, 168, 80, 244, 234, 214, 116, 79, 174, 233, 213, 231, 230, 173, 232, + 44, 215, 117, 122, 235, 22, 11, 245, 89, 203, 95, 176, 156, 169, 81, 160, + 127, 12, 246, 111, 23, 196, 73, 236, 216, 67, 31, 45, 164, 118, 123, 183, + 204, 187, 62, 90, 251, 96, 177, 134, 59, 82, 161, 108, 170, 85, 41, 157, + 151, 178, 135, 144, 97, 190, 220, 252, 188, 149, 207, 205, 55, 63, 91, 209, + 83, 57, 132, 60, 65, 162, 109, 71, 20, 42, 158, 93, 86, 242, 211, 171, + 68, 17, 146, 217, 35, 32, 46, 137, 180, 124, 184, 38, 119, 153, 227, 165, + 103, 74, 237, 222, 197, 49, 254, 24, 13, 99, 140, 128, 192, 247, 112, 7, +}; + +static MV_U8 Alogtable[512] = { + 1, 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53, + 95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170, + 229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49, + 83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205, + 76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136, + 131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154, + 181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163, + 254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160, + 251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65, + 195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117, + 159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128, + 155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84, + 252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202, + 69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14, + 18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23, + 57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1, + + 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53, + 95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170, + 229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49, + 83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205, + 76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136, + 131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154, + 181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163, + 254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160, + 251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65, + 195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117, + 159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128, + 155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84, + 252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202, + 69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14, + 18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23, + 57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1, + +}; + +static MV_U8 S[256] = { + 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, + 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, + 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, + 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, + 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, + 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, + 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, + 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, + 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, + 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, + 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, + 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, + 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, + 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, + 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, + 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22, +}; + +static MV_U8 Si[256] = { + 82, 9, 106, 213, 48, 54, 165, 56, 191, 64, 163, 158, 129, 243, 215, 251, + 124, 227, 57, 130, 155, 47, 255, 135, 52, 142, 67, 68, 196, 222, 233, 203, + 84, 123, 148, 50, 166, 194, 35, 61, 238, 76, 149, 11, 66, 250, 195, 78, + 8, 46, 161, 102, 40, 217, 36, 178, 118, 91, 162, 73, 109, 139, 209, 37, + 114, 248, 246, 100, 134, 104, 152, 22, 212, 164, 92, 204, 93, 101, 182, 146, + 108, 112, 72, 80, 253, 237, 185, 218, 94, 21, 70, 87, 167, 141, 157, 132, + 144, 216, 171, 0, 140, 188, 211, 10, 247, 228, 88, 5, 184, 179, 69, 6, + 208, 44, 30, 143, 202, 63, 15, 2, 193, 175, 189, 3, 1, 19, 138, 107, + 58, 145, 17, 65, 79, 103, 220, 234, 151, 242, 207, 206, 240, 180, 230, 115, + 150, 172, 116, 34, 231, 173, 53, 133, 226, 249, 55, 232, 28, 117, 223, 110, + 71, 241, 26, 113, 29, 41, 197, 137, 111, 183, 98, 14, 170, 24, 190, 27, + 252, 86, 62, 75, 198, 210, 121, 32, 154, 219, 192, 254, 120, 205, 90, 244, + 31, 221, 168, 51, 136, 7, 199, 49, 177, 18, 16, 89, 39, 128, 236, 95, + 96, 81, 127, 169, 25, 181, 74, 13, 45, 229, 122, 159, 147, 201, 156, 239, + 160, 224, 59, 77, 174, 42, 245, 176, 200, 235, 187, 60, 131, 83, 153, 97, + 23, 43, 4, 126, 186, 119, 214, 38, 225, 105, 20, 99, 85, 33, 12, 125, +}; + +/* +static MV_U8 iG[4][4] = { +{0x0e, 0x09, 0x0d, 0x0b}, +{0x0b, 0x0e, 0x09, 0x0d}, +{0x0d, 0x0b, 0x0e, 0x09}, +{0x09, 0x0d, 0x0b, 0x0e}, +}; +*/ +static MV_U32 rcon[30] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, + 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, +}; diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAes.h u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAes.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAes.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAes.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,70 @@ +/* mvAes.h v2.0 August '99 +* Reference ANSI C code +*/ + +/* AES Cipher header file for ANSI C Submissions + Lawrence E. Bassham III + Computer Security Division + National Institute of Standards and Technology + + April 15, 1998 + + This sample is to assist implementers developing to the Cryptographic + API Profile for AES Candidate Algorithm Submissions. Please consult this + document as a cross-reference. + + ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE + MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH + THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT + BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE + IMPLEMENTATION SPECIFIC INFORMATION. +*/ + +/* Includes: + Standard include files +*/ + +#ifndef __mvAes_h__ +#define __mvAes_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvOs.h" + +/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ + +/* Key direction is invalid, e.g., unknown value */ +#define AES_BAD_KEY_DIR -1 + +/* Key material not of correct length */ +#define AES_BAD_KEY_MAT -2 + +/* Key passed is not valid */ +#define AES_BAD_KEY_INSTANCE -3 + +/* Params struct passed to cipherInit invalid */ +#define AES_BAD_CIPHER_MODE -4 + +/* Cipher in wrong state (e.g., not initialized) */ +#define AES_BAD_CIPHER_STATE -5 + +#define AES_BAD_CIPHER_INSTANCE -7 + +/* Function protoypes */ +/* CHANGED: makeKey(): parameter blockLen added + this parameter is absolutely necessary if you want to + setup the round keys in a variable block length setting + cipherInit(): parameter blockLen added (for obvious reasons) + */ + int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); + int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + +#ifdef __cplusplus +} +#endif +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaAddrDec.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaAddrDec.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,295 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvCesa.h" +#include "mvCesaRegs.h" + +#if (MV_CESA_VERSION >= 2) +MV_TARGET tdmaAddrDecPrioTable[] = { +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#ifdef MV_INCLUDE_PEX1 + PEX1_MEM, +#endif +#endif + + TBL_TERM +}; + +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvCesaWinRead. +* +* DESCRIPTION: +* Read TDMA target address window. +* +* INPUT: +* unit - The unit ID. +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCesaWinRead(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin) +{ + MV_U32 sizeReg, baseReg; + MV_U32 size; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", __func__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ(MV_CESA_TDMA_BASE_ADDR_REG(winNum)); + sizeReg = MV_REG_READ(MV_CESA_TDMA_WIN_CTRL_REG(winNum)); + + /* Check if window is enabled */ + if (sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + pDecWin->targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + pDecWin->attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + + size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + pDecWin->addrWin.size = (size + 1) * (1 << MV_CESA_TDMA_WIN_SIZE_OFFSET); + pDecWin->addrWin.baseLow = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + pDecWin->addrWin.baseHigh = 0; + } else { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaTdmaWinWrite +* +* DESCRIPTION: +* This function writes the address decoding registers according to the +* given window configuration. +* +* INPUT: +* unit - The unit ID. +* pAddrDecWin - CESA TDMA target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_BAD_PARAM if winNum is invalid or size is not a power of 2. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCesaTdmaWinWrite(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin) +{ + MV_U32 sizeReg, baseReg; + MV_U32 size; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) { + mvOsPrintf("%s: ERR. Window %d overlap\n", __func__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d.\n" + "Address 0x%08x is unaligned to size 0x%x.\n", + winNum, pDecWin->addrWin.baseLow, pDecWin->addrWin.size); + return MV_ERROR; + } + + if (!MV_IS_POWER_OF_2(pDecWin->addrWin.size)) { + mvOsPrintf("mvCesaTdmaWinWrite: Error setting CESA window %d. " + "Window size is not a power to 2.", winNum); + return MV_BAD_PARAM; + } + + size = (pDecWin->addrWin.size / (1 << MV_CESA_TDMA_WIN_SIZE_OFFSET)) - 1; + + /* set Size, Attributes and TargetID */ + sizeReg = (((pDecWin->targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((pDecWin->attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + else + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + + /* Update Base value */ + baseReg = (pDecWin->addrWin.baseLow & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE(MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE(MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_UNIT_WIN_INFO addrDecWin; + + for (winNumIndex = 0; winNumIndex < MV_CESA_TDMA_ADDR_DEC_WIN; winNumIndex++) { + /* Do not check window itself */ + if (winNumIndex == winNum) + continue; + + /* Get window parameters */ + if (MV_OK != mvCesaWinRead(0, winNumIndex, &addrDecWin)) { + mvOsPrintf("%s: ERR. TargetWinGet failed\n", __func__); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (addrDecWin.enable == MV_FALSE) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + return MV_TRUE; + } + return MV_FALSE; +} + +MV_STATUS mvCesaTdmaWinInit(MV_UNIT_WIN_INFO *addrWinMap) +{ + MV_U32 winNum; + MV_UNIT_WIN_INFO *addrDecWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for (winNum = 0; winNum < MV_CESA_TDMA_ADDR_DEC_WIN; winNum++) + MV_REG_BIT_RESET(MV_CESA_TDMA_WIN_CTRL_REG(winNum), MV_CESA_TDMA_WIN_ENABLE_MASK); + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while ((tdmaAddrDecPrioTable[winPrioIndex] != TBL_TERM) && (winNum < MV_CESA_TDMA_ADDR_DEC_WIN)) { + + addrDecWin = &addrWinMap[tdmaAddrDecPrioTable[winPrioIndex]]; + if (addrDecWin->enable == MV_TRUE) { + if (MV_OK != mvCesaTdmaWinWrite(0, winNum, addrDecWin)) { + mvOsPrintf("mvCesaTdmaWinSet FAILED: winNum=%d\n", winNum); + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} +#endif /* MV_CESA_VERSION >= 2 */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,2884 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysCesaConfig.h" +#include "mvCesaRegs.h" +#include "mvCesa.h" +#include "AES/mvAes.h" +#include "mvMD5.h" +#include "mvSHA1.h" + +#undef CESA_DEBUG + +/********** Global variables **********/ + +/* If request size is more than MV_CESA_MAX_BUF_SIZE the + * request is processed as fragmented request. + */ + +MV_CESA_STATS cesaStats; +short cesaLastSid = -1; +MV_CESA_SA **pCesaSAD = NULL; +MV_U32 cesaMaxSA = 0; +MV_CESA_REQ *pCesaReqFirst = NULL; +MV_CESA_REQ *pCesaReqLast = NULL; +MV_CESA_REQ *pCesaReqEmpty = NULL; +MV_CESA_REQ *pCesaReqProcess = NULL; +int cesaQueueDepth = 0; +int cesaReqResources = 0; + +MV_CESA_SRAM_MAP *cesaSramVirtPtr = NULL; +void *cesaOsHandle = NULL; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + +#if (MV_CESA_VERSION < 3) +#error "CHAIN mode supported only when MV_CESA_VERSION is 3 or larger" +#endif + +MV_U32 cesaChainLength = 0; +int chainReqNum = 0; +MV_U32 chainIndex = 0; +MV_CESA_REQ *pNextActiveChain = 0; +MV_CESA_REQ *pEndCurrChain = 0; +MV_BOOL isFirstReq = MV_TRUE; +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + +static MV_CESA_HAL_DATA cesaHalData; + +static INLINE MV_U8 *mvCesaSramAddrGet(void) +{ + return (MV_U8 *) cesaHalData.sramPhysBase; +} + +static INLINE MV_ULONG mvCesaSramVirtToPhys(void *pDev, MV_U8 *pSramVirt) +{ + return (MV_ULONG) (pSramVirt - cesaHalData.sramVirtBase) + cesaHalData.sramPhysBase; +} + +/* Internal Function prototypes */ + +static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, int macTotalLen, + MV_CESA_REQ *pCesaReq, MV_DMA_DESC *pDmaDesc); + +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); + +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush); + +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]); + +static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ *pReq, MV_CESA_SA *pSA, int macDataSize); + +static MV_CESA_COMMAND *mvCesaCtrModeInit(void); + +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); +static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); + +static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ *pReq); +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ *pReq, MV_U8 frag); + +static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd, MV_U8 *pFixOffset); +static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd); + +static INLINE void mvCesaFragSizeFind(MV_CESA_SA *pSA, MV_CESA_REQ *pReq, + int cryptoOffset, int macOffset, + int *pCopySize, int *pCryptoDataSize, int *pMacDataSize); +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF *pMbuf, int offset, int size); + +/* Go to the next request in the request queue */ +static INLINE MV_CESA_REQ *MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ *pReq) +{ + if (pReq == pCesaReqLast) + return pCesaReqFirst; + + return (pReq + 1); +} + +/* Go to the previous request in the request queue */ +static INLINE MV_CESA_REQ *MV_CESA_REQ_PREV_PTR(MV_CESA_REQ *pReq) +{ + if (pReq == pCesaReqFirst) + return pCesaReqLast; + + return (pReq - 1); +} + +static INLINE void mvCesaReqProcessStart(MV_CESA_REQ *pReq) +{ + int frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->state = MV_CESA_CHAIN; +#else + pReq->state = MV_CESA_PROCESS; +#endif + + cesaStats.startCount++; + + if (pReq->fragMode == MV_CESA_FRAG_NONE) { + frag = 0; + } else { + frag = pReq->frags.nextFrag; + pReq->frags.nextFrag++; + } +#if (MV_CESA_VERSION >= 2) + /* Enable TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, + (MV_U32) mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#else + /* Enable IDMA engine */ + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), + (MV_U32) mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#endif /* MV_CESA_VERSION >= 2 */ + +#if defined(MV_BRIDGE_SYNC_REORDER) + mvOsBridgeReorderWA(); +#endif + + /* Start Accelerator */ + MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); +} + +/******************************************************************************* +* mvCesaHalInit - Initialize the CESA driver +* +* DESCRIPTION: +* This function initialize the CESA driver. +* 1) Session database +* 2) Request queue +* 4) DMA descriptor lists - one list per request. Each list +* has MV_CESA_MAX_DMA_DESC descriptors. +* +* INPUT: +* numOfSession - maximum number of supported sessions +* queueDepth - number of elements in the request queue. +* osHandle - A handle used by the OS to allocate memory for the +* module (Passed to the OS Services layer) +* +* RETURN: +* MV_OK - Success +* MV_NO_RESOURCE - Fail, can't allocate resources: +* Session database, request queue, +* DMA descriptors list, LRU cache database. +* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. +* +*******************************************************************************/ +MV_STATUS mvCesaHalInit(int numOfSession, int queueDepth, void *osHandle, MV_CESA_HAL_DATA *halData) +{ + int i, req; + MV_U32 descOffsetReg, configReg; + + cesaOsHandle = osHandle; + cesaSramVirtPtr = (MV_CESA_SRAM_MAP *) (halData->sramVirtBase + halData->sramOffset); + + mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSramMap=%p\n", numOfSession, queueDepth, cesaSramVirtPtr); + + /* Create initial Session database */ + pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA *) * numOfSession); + if (pCesaSAD == NULL) { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", + sizeof(MV_CESA_SA *) * numOfSession, numOfSession); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaSAD, 0, sizeof(MV_CESA_SA *) * numOfSession); + cesaMaxSA = numOfSession; + + /* Create request queue */ + pCesaReqFirst = mvOsMalloc(sizeof(MV_CESA_REQ) * queueDepth); + if (pCesaReqFirst == NULL) { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d requests\n", + sizeof(MV_CESA_REQ) * queueDepth, queueDepth); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaReqFirst, 0, sizeof(MV_CESA_REQ) * queueDepth); + pCesaReqEmpty = pCesaReqFirst; + pCesaReqLast = pCesaReqFirst + (queueDepth - 1); + pCesaReqProcess = pCesaReqEmpty; + cesaQueueDepth = queueDepth; + cesaReqResources = queueDepth; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + cesaChainLength = MAX_CESA_CHAIN_LENGTH; +#endif + + /* pSramBase must be 8 byte aligned */ + if (MV_IS_NOT_ALIGN((MV_ULONG) cesaSramVirtPtr, 8)) { + mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", cesaSramVirtPtr); + mvCesaFinish(); + return MV_NOT_ALIGNED; + } + + /* Clear registers */ + MV_REG_WRITE(MV_CESA_CFG_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_MASK_REG, 0); + + /* Initialize DMA descriptor lists for all requests in Request queue */ + descOffsetReg = configReg = 0; + for (req = 0; req < queueDepth; req++) { + int frag; + MV_CESA_REQ *pReq; + MV_DMA_DESC *pDmaDesc; + + pReq = &pCesaReqFirst[req]; + + pReq->cesaDescBuf.bufSize = sizeof(MV_CESA_DESC) * MV_CESA_MAX_REQ_FRAGS + CPU_D_CACHE_LINE_SIZE; + + pReq->cesaDescBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle, pReq->cesaDescBuf.bufSize, + &pReq->cesaDescBuf.bufPhysAddr, + &pReq->cesaDescBuf.memHandle); + if (pReq->cesaDescBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", + req, pReq->cesaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); + pReq->pCesaDesc = (MV_CESA_DESC *) MV_ALIGN_UP((MV_ULONG) pReq->cesaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC) * MV_CESA_MAX_DMA_DESC * MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->dmaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle, pReq->dmaDescBuf.bufSize, + &pReq->dmaDescBuf.bufPhysAddr, &pReq->dmaDescBuf.memHandle); + + if (pReq->dmaDescBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", + req, pReq->dmaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); + pDmaDesc = (MV_DMA_DESC *) MV_ALIGN_UP((MV_ULONG) pReq->dmaDescBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + for (frag = 0; frag < MV_CESA_MAX_REQ_FRAGS; frag++) { + MV_CESA_DMA *pDma = &pReq->dma[frag]; + + pDma->pDmaFirst = pDmaDesc; + pDma->pDmaLast = NULL; + + for (i = 0; i < MV_CESA_MAX_DMA_DESC - 1; i++) { + /* link all DMA descriptors together */ + pDma->pDmaFirst[i].phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i + 1])); + } + pDma->pDmaFirst[i].phyNextDescPtr = 0; + mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC * sizeof(MV_DMA_DESC)); + + pDmaDesc += MV_CESA_MAX_DMA_DESC; + } + } + /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH); */ + descOffsetReg = (MV_U16)((MV_U8 *)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); + MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); + + configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; +#endif + +#if (MV_CESA_VERSION >= 2) + /* Initialize TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); + MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); +#else + /* Initialize IDMA #0 engine */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE +#ifdef MV_CPU_LE + | ICCHR_DESC_BYTE_SWAP_EN +#endif + ); + /* Clear Cause Byte of IDMA channel to be used */ + MV_REG_WRITE(IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); +#endif /* (MV_CESA_VERSION >= 2) */ + + /* Set CESA configuration registers */ + MV_REG_WRITE(MV_CESA_CFG_REG, configReg); + mvCesaDebugStatsClear(); + + mvOsMemcpy(&cesaHalData, halData, sizeof(MV_CESA_HAL_DATA)); + return MV_OK; +} + +/******************************************************************************* +* mvCesaFinish - Shutdown the CESA driver +* +* DESCRIPTION: +* This function shutdown the CESA driver and free all allocted resources. +* +* INPUT: None +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaFinish(void) +{ + int req, sid; + MV_CESA_REQ *pReq; + + mvOsPrintf("mvCesaFinish: \n"); + + cesaSramVirtPtr = NULL; + + /* Free all resources: DMA list, etc. */ + for (req = 0; req < cesaQueueDepth; req++) { + pReq = &pCesaReqFirst[req]; + if (pReq->dmaDescBuf.bufVirtPtr != NULL) { + mvOsIoCachedFree(cesaOsHandle, pReq->dmaDescBuf.bufSize, + pReq->dmaDescBuf.bufPhysAddr, + pReq->dmaDescBuf.bufVirtPtr, pReq->dmaDescBuf.memHandle); + } + if (pReq->cesaDescBuf.bufVirtPtr != NULL) { + mvOsIoCachedFree(cesaOsHandle, pReq->cesaDescBuf.bufSize, + pReq->cesaDescBuf.bufPhysAddr, + pReq->cesaDescBuf.bufVirtPtr, pReq->cesaDescBuf.memHandle); + } + } +#if (MV_CESA_VERSION < 2) + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); +#endif /* (MV_CESA_VERSION < 2) */ + + /* Free request queue */ + if (pCesaReqFirst != NULL) { + mvOsFree(pCesaReqFirst); + pCesaReqFirst = pCesaReqLast = NULL; + pCesaReqEmpty = pCesaReqProcess = NULL; + cesaQueueDepth = cesaReqResources = 0; + } + /* Free SA database */ + if (pCesaSAD != NULL) { + for (sid = 0; sid < cesaMaxSA; sid++) { + /* Free SRAM SA structure */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, + pCesaSAD[sid]->sramSABuff, pCesaSAD[sid]->memHandle); + /* Free SA structure */ + mvOsFree(pCesaSAD[sid]); + pCesaSAD[sid] = NULL; + } + + cesaMaxSA = 0; + } + MV_REG_WRITE(MV_CESA_CFG_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_MASK_REG, 0); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode +* +* DESCRIPTION: +* This function set IV value using by Crypto algorithms in CBC mode. +* Each channel has its own IV value. +* This function gets IV value from the caller. If no IV value passed from +* the caller or only part of IV passed, the function will init the rest part +* of IV value (or the whole IV) by random value. +* +* INPUT: +* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL +* the function will generate random IV value. +* int ivSize - size (in bytes) of IV provided by user. If ivSize is +* smaller than maximum IV size, the function will complete +* IV by random value. +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaCryptoIvSet(MV_U8 *pIV, int ivSize) +{ + MV_U8 *pSramIV; +#if defined(MV646xx) + mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); +#endif + pSramIV = cesaSramVirtPtr->cryptoIV; + if (ivSize > MV_CESA_MAX_IV_LENGTH) { + mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH; + } + if (pIV != NULL) { + memcpy(pSramIV, pIV, ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; + pSramIV += ivSize; + } + + while (ivSize > 0) { + int size, mv_random = mvOsRand(); + + size = MV_MIN(ivSize, sizeof(mv_random)); + memcpy(pSramIV, (void *)&mv_random, size); + + pSramIV += size; + ivSize -= size; + } +/* + mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH); + mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH); +*/ + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionOpen - Open new uni-directional crypto session +* +* DESCRIPTION: +* This function open new session. +* +* INPUT: +* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters +* +* OUTPUT: +* short *pSid - session ID, should be used for all future +* requests over this session. +* +* RETURN: +* MV_OK - Session opend successfully. +* MV_FULL - All sessions are in use, no free place in +* SA database. +* MV_BAD_PARAM - One of session input parameters is invalid. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short *pSid) +{ + short sid; + MV_U32 config = 0; + int digestSize; + MV_BUF_INFO cesaSramSaBuf; + + cesaStats.openedCount++; + + /* Find free entry in SAD */ + for (sid = 0; sid < cesaMaxSA; sid++) + if (pCesaSAD[sid] == NULL) + break; + + /* No more sessions left ? */ + if (sid == cesaMaxSA) { + if (MV_FAIL == mvCesaUpdateSADSize(cesaMaxSA * 2)) { + mvOsPrintf("mvCesaSessionOpen: SA Database is FULL\n"); + return MV_FULL; + } + } + + /* Allocate SA entry */ + pCesaSAD[sid] = mvOsMalloc(sizeof(MV_CESA_SA)); + if (pCesaSAD[sid] == NULL) { + mvOsPrintf("mvCesaSessionOpen: Can't allocate %d bytes for SA structures\n", sizeof(MV_CESA_SA)); + return MV_FULL; + } + memset(pCesaSAD[sid], 0, sizeof(MV_CESA_SA)); + + /* Allocate image of sramSA in DRAM */ + cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA) + CPU_D_CACHE_LINE_SIZE; + + cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(cesaOsHandle, cesaSramSaBuf.bufSize, + &cesaSramSaBuf.bufPhysAddr, &cesaSramSaBuf.memHandle); + + if (cesaSramSaBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaSessionOpen: Can't allocate %d bytes for sramSA structures\n", cesaSramSaBuf.bufSize); + return MV_FULL; + } + memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); + + /* Save allocation parameters */ + pCesaSAD[sid]->sramSABuff = cesaSramSaBuf.bufVirtPtr; + pCesaSAD[sid]->sramSABuffSize = cesaSramSaBuf.bufSize; + pCesaSAD[sid]->memHandle = cesaSramSaBuf.memHandle; + pCesaSAD[sid]->pSramSA = (MV_CESA_SRAM_SA *) MV_ALIGN_UP((MV_ULONG) cesaSramSaBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + /* Align physical address to the beginning of SRAM SA */ + pCesaSAD[sid]->sramSAPhysAddr = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pCesaSAD[sid]->pSramSA)); + + /* Check Input parameters for Open session */ + if (pSession->operation >= MV_CESA_MAX_OPERATION) { + mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", pSession->operation); + return MV_BAD_PARAM; + } + config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); + + if ((pSession->direction != MV_CESA_DIR_ENCODE) && (pSession->direction != MV_CESA_DIR_DECODE)) { + mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", pSession->direction); + return MV_BAD_PARAM; + } + config |= (pSession->direction << MV_CESA_DIRECTION_BIT); + /* Clear SA entry */ + /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ + + /* Check AUTH parameters and update SA entry */ + if (pSession->operation != MV_CESA_CRYPTO_ONLY) { + /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ + if ((pSession->macMode == MV_CESA_MAC_HMAC_MD5) || (pSession->macMode == MV_CESA_MAC_HMAC_SHA1)) { + if (pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) { + mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", pSession->macKeyLength); + return MV_BAD_PARAM; + } + mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, + pCesaSAD[sid]->pSramSA->macInnerIV, pCesaSAD[sid]->pSramSA->macOuterIV); + pCesaSAD[sid]->macKeyLength = pSession->macKeyLength; + } + switch (pSession->macMode) { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", pSession->macMode); + return MV_BAD_PARAM; + } + config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); + + /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ + /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ + if ((pSession->digestSize != digestSize) && (pSession->digestSize != 12)) { + mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", pSession->digestSize); + mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->digestSize = pSession->digestSize; + + if (pCesaSAD[sid]->digestSize == 12) { + /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ + config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); + } + } + + /* Check CRYPTO parameters and update SA entry */ + if (pSession->operation != MV_CESA_MAC_ONLY) { + switch (pSession->cryptoAlgorithm) { + case MV_CESA_CRYPTO_DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_3DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + /* Only EDE mode is supported */ + config |= (MV_CESA_CRYPTO_3DES_EDE << MV_CESA_CRYPTO_3DES_MODE_BIT); + break; + + case MV_CESA_CRYPTO_AES: + switch (pSession->cryptoKeyLength) { + case 16: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_128 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 24: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_192 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 32: + default: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_256 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + } + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", pSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); + + if (pSession->cryptoKeyLength != pCesaSAD[sid]->cryptoKeyLength) { + mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", + pSession->cryptoKeyLength, pCesaSAD[sid]->cryptoKeyLength); + return MV_BAD_PARAM; + } + + /* Copy Crypto key */ + if ((pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && (pSession->direction == MV_CESA_DIR_DECODE)) { + /* Crypto Key for AES decode is computed from original key material */ + /* and depend on cryptoKeyLength (128/192/256 bits) */ + aesMakeKey(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, + pSession->cryptoKeyLength * 8, MV_CESA_AES_BLOCK_SIZE * 8); + } else { + /*panic("mvCesaSessionOpen2"); */ + memcpy(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, pCesaSAD[sid]->cryptoKeyLength); + + } + + switch (pSession->cryptoMode) { + case MV_CESA_CRYPTO_ECB: + pCesaSAD[sid]->cryptoIvSize = 0; + break; + + case MV_CESA_CRYPTO_CBC: + pCesaSAD[sid]->cryptoIvSize = pCesaSAD[sid]->cryptoBlockSize; + break; + + case MV_CESA_CRYPTO_CTR: + /* Supported only for AES algorithm */ + if (pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) { + mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->cryptoIvSize = 0; + pCesaSAD[sid]->ctrMode = 1; + /* Replace to ECB mode for HW */ + pSession->cryptoMode = MV_CESA_CRYPTO_ECB; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", pSession->cryptoMode); + return MV_BAD_PARAM; + } + + config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); + } + pCesaSAD[sid]->config = config; + + mvOsCacheFlush(NULL, pCesaSAD[sid]->pSramSA, sizeof(MV_CESA_SRAM_SA)); + if (pSid != NULL) + *pSid = sid; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionClose - Close active crypto session +* +* DESCRIPTION: +* This function closes existing session +* +* INPUT: +* short sid - Unique identifier of the session to be closed +* +* RETURN: +* MV_OK - Session closed successfully. +* MV_BAD_PARAM - Session identifier is out of valid range. +* MV_NOT_FOUND - There is no active session with such ID. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionClose(short sid) +{ + cesaStats.closedCount++; + + if (sid >= cesaMaxSA) { + mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); + return MV_BAD_PARAM; + } + + if (pCesaSAD[sid] == NULL) { + mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); + return MV_NOT_FOUND; + } + if (cesaLastSid == sid) + cesaLastSid = -1; + + /* Free SA structures */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, pCesaSAD[sid]->sramSABuff, pCesaSAD[sid]->memHandle); + mvOsFree(pCesaSAD[sid]); + + pCesaSAD[sid] = NULL; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaAction - Perform crypto operation +* +* DESCRIPTION: +* This function set new CESA request FIFO queue for further HW processing. +* The function checks request parameters before set new request to the queue. +* If one of the CESA channels is ready for processing the request will be +* passed to HW. When request processing is finished the CESA interrupt will +* be generated by HW. The caller should call mvCesaReadyGet() function to +* complete request processing and get result. +* +* INPUT: +* MV_CESA_COMMAND *pCmd - pointer to new CESA request. +* It includes pointers to Source and Destination +* buffers, session identifier get from +* mvCesaSessionOpen() function, pointer to caller +* private data and all needed crypto parameters. +* +* RETURN: +* MV_OK - request successfully added to request queue +* and will be processed. +* MV_NO_MORE - request successfully added to request queue and will +* be processed, but request queue became Full and next +* request will not be accepted. +* MV_NO_RESOURCE - request queue is FULL and the request can not +* be processed. +* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is +* failed. Request can not be processed. +* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed +* as one request and should be splitted for two requests: +* CRYPTO_ONLY and MAC_ONLY. +* MV_BAD_PARAM - One of the request parameters is out of valid range. +* The request can not be processed. +* +*******************************************************************************/ +MV_STATUS mvCesaAction(MV_CESA_COMMAND *pCmd) +{ + MV_STATUS status; + MV_CESA_REQ *pReq = pCesaReqEmpty; + int sid = pCmd->sessionId; + MV_CESA_SA *pSA = pCesaSAD[sid]; +#ifdef CONFIG_MV_CESA_CHAIN_MODE + MV_CESA_REQ *pFromReq; + MV_CESA_REQ *pToReq; +#endif + cesaStats.reqCount++; + + /* Check that the request queue is not FULL */ + if (cesaReqResources == 0) + return MV_NO_RESOURCE; + + if ((sid >= cesaMaxSA) || (pSA == NULL)) { + mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); + return MV_BAD_PARAM; + } + pSA->count++; + + if (pSA->ctrMode) { + /* AES in CTR mode can't be mixed with Authentication */ + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); + return MV_NOT_ALLOWED; + } + /* All other request parameters should not be checked because key stream */ + /* (not user data) processed by AES HW engine */ + pReq->pOrgCmd = pCmd; + /* Allocate temporary pCmd structure for Key stream */ + pCmd = mvCesaCtrModeInit(); + if (pCmd == NULL) + return MV_OUT_OF_CPU_MEM; + + /* Prepare Key stream */ + mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); + pReq->fixOffset = 0; + } else { + /* Check request parameters and calculae fixOffset */ + status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); + if (status != MV_OK) + return status; + } + pReq->pCmd = pCmd; + + /* Check if the packet need fragmentation */ + if (pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf)) { + /* request size is smaller than single buffer size */ + pReq->fragMode = MV_CESA_FRAG_NONE; + + /* Prepare NOT fragmented packets */ + status = mvCesaReqProcess(pReq); + if (status != MV_OK) + mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", pReq, status); +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.numFrag = 1; +#endif + } else { + MV_U8 frag = 0; + + /* request size is larger than buffer size - needs fragmentation */ + + /* Check restrictions for processing fragmented packets */ + status = mvCesaFragParamCheck(pSA, pCmd); + if (status != MV_OK) + return status; + + pReq->fragMode = MV_CESA_FRAG_FIRST; + pReq->frags.nextFrag = 0; + + /* Prepare Process Fragmented packets */ + while (pReq->fragMode != MV_CESA_FRAG_LAST) { + if (frag >= MV_CESA_MAX_REQ_FRAGS) { + mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); + return MV_OUT_OF_CPU_MEM; + } + status = mvCesaFragReqProcess(pReq, frag); + if (status == MV_OK) { +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (frag) { + pReq->dma[frag - 1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); + mvOsCacheFlush(NULL, pReq->dma[frag - 1].pDmaLast, sizeof(MV_DMA_DESC)); + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + frag++; + } + } + pReq->frags.numFrag = frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (chainReqNum) { + chainReqNum += pReq->frags.numFrag; + if (chainReqNum >= MAX_CESA_CHAIN_LENGTH) + chainReqNum = MAX_CESA_CHAIN_LENGTH; + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + } + + pReq->state = MV_CESA_PENDING; + + pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources -= 1; + +/* #ifdef CESA_DEBUG */ + if ((cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) + cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); +/* #endif CESA_DEBUG */ + + cesaLastSid = sid; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + /* Are we within chain bounderies and follows the first request ? */ + if ((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { + if (chainIndex) { + pFromReq = MV_CESA_REQ_PREV_PTR(pReq); + pToReq = pReq; + pReq->state = MV_CESA_CHAIN; + /* assume concatenating is possible */ + pFromReq->dma[pFromReq->frags.numFrag - 1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); + mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag - 1].pDmaLast, sizeof(MV_DMA_DESC)); + + /* align active & next pointers */ + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); + } else { /* we have only one chain, start new one */ + chainReqNum = 0; + chainIndex++; + /* align active & next pointers */ + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + } + } else { + /* In case we concatenate full chain */ + if (chainReqNum == MAX_CESA_CHAIN_LENGTH) { + chainIndex++; + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + chainReqNum = 0; + } + + pReq = pCesaReqProcess; + if (pReq->state == MV_CESA_PENDING) { + pNextActiveChain = pReq; + pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } + } + + chainReqNum++; + + if ((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) + cesaStats.maxChainUsage = chainReqNum; + +#else + + /* Check status of CESA channels and process requests if possible */ + pReq = pCesaReqProcess; + if (pReq->state == MV_CESA_PENDING) { + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + /* If request queue became FULL - return MV_NO_MORE */ + if (cesaReqResources == 0) + return MV_NO_MORE; + + return MV_OK; + +} + +/******************************************************************************* +* mvCesaReadyGet - Get crypto request that processing is finished +* +* DESCRIPTION: +* This function complete request processing and return ready request to +* caller. To don't miss interrupts the caller must call this function +* while MV_OK or MV_TERMINATE values returned. +* +* INPUT: +* MV_U32 chanMap - map of CESA channels finished thier job +* accordingly with CESA Cause register. +* MV_CESA_RESULT* pResult - pointer to structure contains information +* about ready request. It includes pointer to +* user private structure "pReqPrv", session identifier +* for this request "sessionId" and return code. +* Return code set to MV_FAIL if calculated digest value +* on decode direction is different than digest value +* in the packet. +* +* RETURN: +* MV_OK - Success, ready request is returned. +* MV_NOT_READY - Next request is not ready yet. New interrupt will +* be generated for futher request processing. +* MV_EMPTY - There is no more request for processing. +* MV_BUSY - Fragmented request is not ready yet. +* MV_TERMINATE - Call this function once more to complete processing +* of fragmented request. +* +*******************************************************************************/ +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT *pResult) +{ + MV_STATUS status, readyStatus = MV_NOT_READY; + MV_U32 statusReg; + MV_CESA_REQ *pReq; + MV_CESA_SA *pSA; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (isFirstReq == MV_TRUE) { + if (chainIndex == 0) + chainReqNum = 0; + + isFirstReq = MV_FALSE; + + if (pNextActiveChain->state == MV_CESA_PENDING) { + /* Start request Process */ + mvCesaReqProcessStart(pNextActiveChain); + pEndCurrChain = pNextActiveChain; + if (chainIndex > 0) + chainIndex--; + /* Update pNextActiveChain to next chain head */ + while (pNextActiveChain->state == MV_CESA_CHAIN) + pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); + } + } + + /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ + if (pCesaReqProcess == pEndCurrChain) { + isFirstReq = MV_TRUE; + pEndCurrChain = pNextActiveChain; +#else + if (pCesaReqProcess->state != MV_CESA_PROCESS) { +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + return MV_EMPTY; + } +#ifdef CESA_DEBUG + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if (statusReg & MV_CESA_STATUS_ACTIVE_MASK) { + mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); + cesaStats.notReadyCount++; + return MV_NOT_READY; + } +#endif /* CESA_DEBUG */ + + cesaStats.readyCount++; + + pReq = pCesaReqProcess; + pSA = pCesaSAD[pReq->pCmd->sessionId]; + + pResult->retCode = MV_OK; + if (pReq->fragMode != MV_CESA_FRAG_NONE) { + MV_U8 *pNewDigest; + int frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.nextFrag = 1; + while (pReq->frags.nextFrag <= pReq->frags.numFrag) { +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + frag = (pReq->frags.nextFrag - 1); + + /* Restore DMA descriptor list */ + pReq->dma[frag].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); + pReq->dma[frag].pDmaLast = NULL; + + /* Special processing for finished fragmented request */ + if (pReq->frags.nextFrag >= pReq->frags.numFrag) { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Fragmented packet is ready */ + if ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; + + if (macDataSize != 0) { + /* Calculate all other blocks by SW */ + mvCesaFragAuthComplete(pReq, pSA, macDataSize); + } + + /* Copy new digest from SRAM to the Destination buffer */ + pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; + status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, + pReq->pCmd->digestOffset, pSA->digestSize); + + /* For decryption: Compare new digest value with original one */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + if (memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) { +/* + mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", + chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + } + readyStatus = MV_OK; + } +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.nextFrag++; + } +#endif + } else { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Restore DMA descriptor list */ + pReq->dma[0].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); + pReq->dma[0].pDmaLast = NULL; + if (((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT))) { + /* For AUTH on decode : Check Digest result in Status register */ + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if (statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) { +/* + mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", + chan, statusReg); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + readyStatus = MV_OK; + } + + if (readyStatus == MV_OK) { + /* If Request is ready - Prepare pResult structure */ + pResult->pReqPrv = pReq->pCmd->pReqPrv; + pResult->sessionId = pReq->pCmd->sessionId; + + pReq->state = MV_CESA_IDLE; + pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources++; + + if (pSA->ctrMode) { + /* For AES CTR mode - complete processing and free allocated resources */ + mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); + mvCesaCtrModeFinish(pReq->pCmd); + pReq->pOrgCmd = NULL; + } + } +#ifndef CONFIG_MV_CESA_CHAIN_MODE + if (pCesaReqProcess->state == MV_CESA_PROCESS) { + /* Start request Process */ + mvCesaReqProcessStart(pCesaReqProcess); + if (readyStatus == MV_NOT_READY) + readyStatus = MV_BUSY; + } else if (pCesaReqProcess != pCesaReqEmpty) { + /* Start process new request from the queue */ + mvCesaReqProcessStart(pCesaReqProcess); + } +#endif /* !CONFIG_MV_CESA_CHAIN_MODE */ + return readyStatus; +} + +/***************** Functions to work with CESA_MBUF structure ******************/ + +/******************************************************************************* +* mvCesaMbufOffset - Locate offset in the Mbuf structure +* +* DESCRIPTION: +* This function locates offset inside Multi-Bufeer structure. +* It get fragment number and place in the fragment where the offset +* is located. +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure +* int offset - Offset from the beginning of the data presented by +* the Mbuf structure. +* +* OUTPUT: +* int* pBufOffset - Offset from the beginning of the fragment where +* the offset is located. +* +* RETURN: +* int - Number of fragment, where the offset is located\ +* +*******************************************************************************/ +int mvCesaMbufOffset(MV_CESA_MBUF *pMbuf, int offset, int *pBufOffset) +{ + int frag = 0; + + while (offset > 0) { + if (frag >= pMbuf->numFrags) { + mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", frag, pMbuf->numFrags); + return MV_INVALID; + } + if (offset < pMbuf->pFrags[frag].bufSize) + break; + + offset -= pMbuf->pFrags[frag].bufSize; + frag++; + } + if (pBufOffset != NULL) + *pBufOffset = offset; + + return frag; +} + +/******************************************************************************* +* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pDstBuf - Pointer to continuous buffer, where data is +* copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_EMPTY - Multi-buffer structure has not enough data to copy +* Data from the offset to end of Mbuf data is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyFromMbuf(MV_U8 *pDstBuf, MV_CESA_MBUF *pSrcMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + memcpy(pDstBuf, pBuf, size); + return MV_OK; + } + memcpy(pDstBuf, pBuf, bufSize); + size -= bufSize; + frag++; + pDstBuf += bufSize; + if (frag >= pSrcMbuf->numFrags) + break; + + bufSize = pSrcMbuf->pFrags[frag].bufSize; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", size); + return MV_EMPTY; +} + +/******************************************************************************* +* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is +* copied from. +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_FULL - Multi-buffer structure has not enough place to copy +* all data. Data from the offset to end of Mbuf data +* is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyToMbuf(MV_U8 *pSrcBuf, MV_CESA_MBUF *pDstMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + memcpy(pBuf, pSrcBuf, size); + return MV_OK; + } + memcpy(pBuf, pSrcBuf, bufSize); + size -= bufSize; + frag++; + pSrcBuf += bufSize; + if (frag >= pDstMbuf->numFrags) + break; + + bufSize = pDstMbuf->pFrags[frag].bufSize; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", size); + return MV_FULL; +} + +/******************************************************************************* +* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int dstMbufOffset - Offset in the dstMbuf structure where first byte +* of data should be copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int srcMbufOffset - Offset in the srcMbuf structure where first byte +* of data should be copied from. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of +* srcMbuf or dstMbuf structure correspondently. +* No data is copied. +* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy +* all data. Partial data is copied +* +*******************************************************************************/ +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF *pMbufDst, int dstMbufOffset, + MV_CESA_MBUF *pMbufSrc, int srcMbufOffset, int size) +{ + int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; + int copySize; + MV_U8 *pSrc, *pDst; + + if (size == 0) + return MV_OK; + + srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); + if (srcFrag == MV_INVALID) { + mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); + return MV_OUT_OF_RANGE; + } + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; + + dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); + if (dstFrag == MV_INVALID) { + mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); + return MV_OUT_OF_RANGE; + } + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; + dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; + + while (size > 0) { + copySize = MV_MIN(srcSize, dstSize); + if (size <= copySize) { + memcpy(pDst, pSrc, size); + return MV_OK; + } + memcpy(pDst, pSrc, copySize); + size -= copySize; + srcSize -= copySize; + dstSize -= copySize; + + if (srcSize == 0) { + srcFrag++; + if (srcFrag >= pMbufSrc->numFrags) + break; + + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize; + } + + if (dstSize == 0) { + dstFrag++; + if (dstFrag >= pMbufDst->numFrags) + break; + + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pMbufDst->pFrags[dstFrag].bufSize; + } + } + mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", size); + + return MV_BAD_SIZE; +} + +MV_STATUS mvCesaUpdateSADSize(MV_U32 size) +{ + MV_CESA_SA **pNewCesaSAD = NULL; + + /*mvOsPrintf("mvCesaUpdateSADSize: Increasing SA Database to %d sessions\n",size); */ + + /* Allocate new buffer to hold larger SAD */ + pNewCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA *) * size); + if (pNewCesaSAD == NULL) { + mvOsPrintf("mvCesaUpdateSADSize: Can't allocate %d bytes for new SAD buffer\n", size); + return MV_FAIL; + } + memset(pNewCesaSAD, 0, (sizeof(MV_CESA_SA *) * size)); + mvOsMemcpy(pNewCesaSAD, pCesaSAD, (sizeof(MV_CESA_SA *) * cesaMaxSA)); + mvOsFree(pCesaSAD); + pCesaSAD = pNewCesaSAD; + cesaMaxSA = size; + + return MV_OK; +} + +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF *pMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); + return MV_OK; + } + + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); + size -= bufSize; + frag++; + if (frag >= pMbuf->numFrags) + break; + + bufSize = pMbuf->pFrags[frag].bufSize; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", __func__, size); + return MV_FULL; +} + +/*************************************** Local Functions ******************************/ + +/******************************************************************************* +* mvCesaFragReqProcess - Process fragmented request +* +* DESCRIPTION: +* This function processes a fragment of fragmented request (First, Middle or Last) +* +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The fragment is successfully passed to HW for processing. +* MV_TERMINATE - Means, that HW finished its work on this packet and no more +* interrupts will be generated for this request. +* Function mvCesaReadyGet() must be called to complete request +* processing and get request result. +* +*******************************************************************************/ +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ *pReq, MV_U8 frag) +{ + int i, copySize, cryptoDataSize, macDataSize, sid; + int cryptoIvOffset, digestOffset; + MV_U32 config; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + MV_CESA_SA *pSA; + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc = pReq->dma[frag].pDmaFirst; + MV_U8 *pSramBuf = cesaSramVirtPtr->buf; + int macTotalLen = 0; + int fixOffset, cryptoOffset, macOffset; + + cesaStats.fragCount++; + + sid = pReq->pCmd->sessionId; + + pSA = pCesaSAD[sid]; + + cryptoIvOffset = digestOffset = 0; + i = macDataSize = 0; + cryptoDataSize = 0; + + /* First fragment processing */ + if (pReq->fragMode == MV_CESA_FRAG_FIRST) { + /* pReq->frags monitors processing of fragmented request between fragments */ + pReq->frags.bufOffset = 0; + pReq->frags.cryptoSize = 0; + pReq->frags.macSize = 0; + + config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); + + /* fixOffset can be not equal to zero only for FIRST fragment */ + fixOffset = pReq->fixOffset; + /* For FIRST fragment crypto and mac offsets are taken from pCmd */ + cryptoOffset = pCmd->cryptoOffset; + macOffset = pCmd->macOffset; + + copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; + + /* Find fragment size: Must meet all requirements for CRYPTO and MAC + * cryptoDataSize - size of data will be encrypted/decrypted in this fragment + * macDataSize - size of data will be signed/verified in this fragment + * copySize - size of data will be copied from srcMbuf to SRAM and + * back to dstMbuf for this fragment + */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ©Size, &cryptoDataSize, &macDataSize); + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* CryptoIV special processing */ + if ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) { + /* In CBC mode for encode direction when IV from user */ + if ((pCmd->ivFromUser) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT))) { + + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, + pCmd->skipFlush); + } + + /* Special processing when IV is not located in the first fragment */ + if (pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) { + /* Prepare dummy place for cryptoIV in SRAM */ + cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); + + /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, + &pDmaDesc[i], MV_FALSE, pCmd->ivOffset, + pSA->cryptoIvSize, pCmd->skipFlush); + } else { + /* For Encryption when IV is NOT from User: */ + /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ + if (pCmd->ivFromUser == 0) { + /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, + &pDmaDesc[i], MV_TRUE, pCmd->ivOffset, + pSA->cryptoIvSize, pCmd->skipFlush); + } + } + } else { + cryptoIvOffset = pCmd->ivOffset; + } + } + } + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* MAC digest special processing on Decode direction */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + /* Save digest from pCmd->digestOffset */ + mvCesaCopyFromMbuf(pReq->frags.orgDigest, + pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* If pCmd->digestOffset is not located on the first */ + if (pCmd->digestOffset > (copySize - pSA->digestSize)) { + MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; + + /* Set zeros to pCmd->digestOffset (DRAM) */ + memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); + mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } else { + digestOffset = pCmd->digestOffset; + } + } + } + /* Update SA in SRAM */ + if (cesaLastSid != sid) { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + pReq->fragMode = MV_CESA_FRAG_MIDDLE; + } else { + /* Continue fragment */ + fixOffset = 0; + cryptoOffset = 0; + macOffset = 0; + if ((pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) { + /* Last fragment */ + config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); + pReq->fragMode = MV_CESA_FRAG_LAST; + copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + macDataSize = pCmd->macLength - pReq->frags.macSize; + + /* If pCmd->digestOffset is not located on last fragment */ + if (pCmd->digestOffset < pReq->frags.bufOffset) { + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } else { + digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; + } + pReq->frags.newDigestOffset = digestOffset; + macTotalLen = pCmd->macLength; + + /* HW can't calculate the Digest correctly for fragmented packets + * in the following cases: + * - MV88F5182 || + * - MV88F5181L when total macLength more that 16 Kbytes || + * - total macLength more that 64 Kbytes + */ + if ((cesaHalData.ctrlModel == MV_5182_DEV_ID) || + ((cesaHalData.ctrlModel == MV_5181_DEV_ID) && + (cesaHalData.ctrlRev >= MV_5181L_A0_REV) && (pCmd->macLength >= (1 << 14)))) { + return MV_TERMINATE; + } + } + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) + cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; + + /* cryptoIvOffset - don't care */ + } else { + /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ + if ((cesaHalData.ctrlModel == MV_5182_DEV_ID) && + (((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || + ((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET)))) { + pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + pReq->fragMode = MV_CESA_FRAG_LAST; + + return MV_TERMINATE; + } + /* Middle fragment */ + config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); + copySize = sizeof(cesaSramVirtPtr->buf); + /* digestOffset and cryptoIvOffset - don't care */ + + /* Find fragment size */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + } + } + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ + mvCesaSramDescrBuild(config, frag, + cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, + cryptoDataSize, macOffset + fixOffset, + digestOffset + fixOffset, macDataSize, macTotalLen, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i - 1].phyNextDescPtr = 0; + pReq->dma[frag].pDmaLast = &pDmaDesc[i - 1]; + mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, i * sizeof(MV_DMA_DESC)); + + /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]); */ + + pReq->frags.bufOffset += copySize; + pReq->frags.cryptoSize += cryptoDataSize; + pReq->frags.macSize += macDataSize; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaReqProcess - Process regular (Non-fragmented) request +* +* DESCRIPTION: +* This function processes the whole (not fragmented) request +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The request is successfully passed to HW for processing. +* Other - Failure. The request will not be processed +* +*******************************************************************************/ +static MV_STATUS mvCesaReqProcess(MV_CESA_REQ *pReq) +{ + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc; + MV_U8 *pSramBuf; + int sid, i, fixOffset; + MV_CESA_SA *pSA; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + + cesaStats.procCount++; + + sid = pCmd->sessionId; + pSA = pCesaSAD[sid]; + pDmaDesc = pReq->dma[0].pDmaFirst; + pSramBuf = cesaSramVirtPtr->buf; + fixOffset = pReq->fixOffset; + +/* + mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", + sid, pSA, pDmaDesc, pSramBuf); +*/ + i = 0; + + /* Crypto IV Special processing in CBC mode for Encryption direction */ + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && + (pCmd->ivFromUser)) { + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Update SA in SRAM */ + if (cesaLastSid != sid) { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ + mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, + pCmd->ivOffset + fixOffset, pCmd->cryptoLength, + pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, + pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i - 1].phyNextDescPtr = 0; + pReq->dma[0].pDmaLast = &pDmaDesc[i - 1]; + mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i * sizeof(MV_DMA_DESC)); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaSramDescrBuild - Set CESA descriptor in SRAM +* +* DESCRIPTION: +* This function builds CESA descriptor in SRAM from all Command parameters +* +* +* INPUT: +* int chan - CESA channel uses the descriptor +* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure +* int cryptoOffset - Offset from the beginning of SRAM buffer where +* data for encryption/decription is started. +* int ivOffset - Offset of crypto IV from the SRAM base. Valid only +* for first fragment. +* int cryptoLength - Size (in bytes) of data for encryption/descryption +* operation on this fragment. +* int macOffset - Offset from the beginning of SRAM buffer where +* data for Authentication is started +* int digestOffset - Offset from the beginning of SRAM buffer where +* digest is located. Valid for first and last fragments. +* int macLength - Size (in bytes) of data for Authentication +* operation on this fragment. +* int macTotalLen - Toatl size (in bytes) of data for Authentication +* operation on the whole request (packet). Valid for +* last fragment only. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, + int macTotalLen, MV_CESA_REQ *pReq, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_DESC *pCesaDesc = &pReq->pCesaDesc[frag]; + MV_CESA_DESC *pSramDesc = &cesaSramVirtPtr->desc; + MV_U16 sramBufOffset = (MV_U16)((MV_U8 *)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); + + pCesaDesc->config = MV_32BIT_LE(config); + + if ((config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* word 1 */ + pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + /* word 2 */ + pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); + /* word 3 */ + pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.cryptoKey - + mvCesaSramAddrGet())); + /* word 4 */ + pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->cryptoIV - mvCesaSramAddrGet())); + pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); + } + + if ((config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* word 5 */ + pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); + pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); + + /* word 6 */ + pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); + pCesaDesc->macDataLen = MV_16BIT_LE(macLength); + + /* word 7 */ + pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.macInnerIV - + mvCesaSramAddrGet())); + pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.macOuterIV - + mvCesaSramAddrGet())); + } + /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ + pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8 *) pSramDesc)); + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); + + /* flush Source buffer */ + mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); +} + +/******************************************************************************* +* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. +* +* DESCRIPTION: +* Copy to SRAM values of the required SA. +* +* +* INPUT: +* short sid - Session ID needs SRAM Cache update +* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to +* copy SA values from DRAM to SRAM. +* +* RETURN: +* MV_OK - Cache entry for this SA copied to SRAM. +* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM +* +*******************************************************************************/ +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_SA *pSA = pCesaSAD[sid]; + + /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); + pDmaDesc->phySrcAdd = pSA->sramSAPhysAddr; + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8 *)&cesaSramVirtPtr->sramSA)); + + /* Source buffer is already flushed during OpenSession */ + /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA)); */ +} + +/******************************************************************************* +* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by +* Mbuf structure from DRAM to SRAM +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request +* data in DRAM +* MV_U8* pSramBuf - pointer to buffer in SRAM where data should +* be copied to. +* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. +* The function set number of DMA descriptors needed +* to copy the copySize bytes from Mbuf. +* MV_BOOL isToMbuf - Copy direction. +* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. +* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. +* int offset - Offset in the Mbuf structure that copy should be +* started from. +* int copySize - Size of data should be copied. +* +* RETURN: +* int - number of DMA descriptors used for the copy. +* +*******************************************************************************/ +#ifndef MV_NETBSD +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, size, frag, i; + MV_U8 *pBuf; + + i = 0; + + /* Calculate start place for copy: fragment number and offset in the fragment */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + + /* Size accumulate total copy size */ + size = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* Find copy size for each DMA descriptor */ + bufSize = MV_MIN(bufSize, (copySize - size)); + pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); + if (isToMbuf) { + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* invalidate the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, bufSize); + } else { + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* flush the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, bufSize); + } + + /* Count number of used DMA descriptors */ + i++; + size += bufSize; + + /* go to next fragment in the Mbuf */ + frag++; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + bufSize = pMbuf->pFrags[frag].bufSize; + } + return i; +} +#else /* MV_NETBSD */ +static int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, thisSize, size, frag, i; + MV_ULONG bufPhys, sramPhys; + MV_U8 *pBuf; + + /* + * Calculate start place for copy: fragment number and offset in + * the fragment + */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + + /* + * Get SRAM physical address only once. We can update it in-place + * as we build the descriptor chain. + */ + sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); + + /* + * 'size' accumulates total copy size, 'i' counts desccriptors. + */ + size = i = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* + * Calculate # of bytes to copy from the current fragment, + * and the pointer to the start of data + */ + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + bufOffset = 0; /* First frag may be non-zero */ + frag++; + + /* + * As long as there is data in the current fragment... + */ + while (bufSize > 0) { + /* + * Ensure we don't cross an MMU page boundary. + * XXX: This is NetBSD-specific, but it is a + * quick and dirty way to fix the problem. + * A true HAL would rely on the OS-specific + * driver to do this... + */ + thisSize = PAGE_SIZE - (((MV_ULONG) pBuf) & (PAGE_SIZE - 1)); + thisSize = MV_MIN(bufSize, thisSize); + /* + * Make sure we don't copy more than requested + */ + if (thisSize > (copySize - size)) { + thisSize = copySize - size; + bufSize = 0; + } + + /* + * Physicall address of this fragment + */ + bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + + /* + * Set up the descriptor + */ + pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); + if (isToMbuf) { + pDmaDesc[i].phyDestAdd = bufPhys; + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); + /* invalidate the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, thisSize); + } else { + pDmaDesc[i].phySrcAdd = bufPhys; + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); + /* flush the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, thisSize); + } + + pDmaDesc[i].phyNextDescPtr = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, (&pDmaDesc[i + 1]))); + + /* flush the DMA desc */ + mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); + + /* Update state */ + bufSize -= thisSize; + sramPhys += thisSize; + pBuf += thisSize; + size += thisSize; + i++; + } + } + + return i; +} +#endif /* MV_NETBSD */ +/******************************************************************************* +* mvCesaHmacIvGet - Calculate Inner and Outte