diff -Naur u-boot-2009.08.orig/board/marvell/common/mv802_3.h u-boot-2009.08/board/marvell/common/mv802_3.h --- u-boot-2009.08.orig/board/marvell/common/mv802_3.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mv802_3.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,244 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmv802_3h +#define __INCmv802_3h + +/* includes */ +#include "mvTypes.h" + +/* Defines */ +#define MV_MAX_ETH_DATA 1500 + +/* 802.3 types */ +#define MV_IP_TYPE 0x0800 +#define MV_IP_ARP_TYPE 0x0806 +#define MV_IP6_TYPE 0x86dd +#define MV_APPLE_TALK_ARP_TYPE 0x80F3 +#define MV_NOVELL_IPX_TYPE 0x8137 +#define MV_EAPOL_TYPE 0x888e +#define MV_VLAN_TYPE 0x8100 +#define MV_PPPOE_TYPE 0x8864 + +/* Encapsulation header for RFC1042 and Ethernet_tunnel */ + +#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00} + +#define MV_ETH_SNAP_LSB 0xF8 + +#define MV_MAC_ADDR_SIZE (6) +#define MV_MAC_STR_SIZE (20) +#define MV_LLC_HLEN (6) +#define MV_VLAN_HLEN (4) +#define MV_ETH_TYPE_LEN (2) +#define MV_ETH_ALEN (MV_MAC_ADDR_SIZE + MV_MAC_ADDR_SIZE + MV_ETH_TYPE_LEN) +#define MV_PPP_HDR_SIZE (2) +#define MV_PPPOE_HDR_SIZE (8) /* PPP header is 2, PPPoE header is 6 */ + +/* This macro checks for a multicast mac address */ +#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1) + +/* IPv4 */ +#define MV_INET 2 +/* IPv6 */ +#define MV_INET6 10 + +#define MV_MAX_L3_ADDR_SIZE (16) /* IPv4: 4, IPv6: 16 */ + +/* This macro checks for an broadcast mac address */ +#define MV_IS_BROADCAST_MAC(mac) \ + (((mac)[0] == 0xFF) && \ + ((mac)[1] == 0xFF) && \ + ((mac)[2] == 0xFF) && \ + ((mac)[3] == 0xFF) && \ + ((mac)[4] == 0xFF) && \ + ((mac)[5] == 0xFF)) + +/* Typedefs */ +typedef struct { + MV_U8 pDA[MV_MAC_ADDR_SIZE]; + MV_U8 pSA[MV_MAC_ADDR_SIZE]; + MV_U16 typeOrLen; + +} MV_802_3_HEADER; + +/* 8 bytes - PPPoE header + PPP header */ +typedef struct { + MV_U8 version; + MV_U8 code; + MV_U16 session; + MV_U16 len; + MV_U16 proto; +} PPPoE_HEADER; + +enum { + MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */ + MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */ + MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */ + MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */ + MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */ + MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */ + MV_IP_PROTO_PUP = 12, /* PUP protocol */ + MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */ + MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */ + MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */ + MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */ + MV_IP_PROTO_RSVP = 46, /* RSVP protocol */ + MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */ + MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */ + MV_IP_PROTO_AH = 51, /* Authentication Header protocol */ + MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */ + MV_IP_PROTO_PIM = 103, + MV_IP_PROTO_COMP = 108, /* Compression Header protocol */ + MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */ + MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */ + MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */ + + MV_IP_PROTO_RAW = 255, /* Raw IP packets */ + MV_IP_PROTO_MAX +}; + +typedef struct { + MV_U8 version; + MV_U8 tos; + MV_U16 totalLength; + MV_U16 identifier; + MV_U16 fragmentCtrl; + MV_U8 ttl; + MV_U8 protocol; + MV_U16 checksum; + MV_U32 srcIP; + MV_U32 dstIP; + +} MV_IP_HEADER; + +typedef struct { + MV_U32 verClassFlow; + MV_U16 payloadLength; + MV_U8 protocol; + MV_U8 hoplimit; + MV_U8 srcAddr[16]; + MV_U8 dstAddr[16]; + +} MV_IP6_HEADER; + +typedef struct +{ + MV_U8 protocol; + MV_U8 length; + MV_U16 reserverd; + MV_U32 spi; + MV_U32 seqNum; +} MV_AH_HEADER; + + +typedef struct { + MV_U32 spi; + MV_U32 seqNum; +} MV_ESP_HEADER; + +#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */ +#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */ +#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */ +#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */ +#define MV_ICMP_ECHO 8 /* Echo Request */ +#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */ +#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */ +#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */ +#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */ +#define MV_ICMP_INFO_REQUEST 15 /* Information Request */ +#define MV_ICMP_INFO_REPLY 16 /* Information Reply */ +#define MV_ICMP_ADDRESS 17 /* Address Mask Request */ +#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */ + +typedef struct { + MV_U8 type; + MV_U8 code; + MV_U16 checksum; + MV_U16 id; + MV_U16 sequence; + +} MV_ICMP_ECHO_HEADER; + +typedef struct { + MV_U16 source; + MV_U16 dest; + MV_U32 seq; + MV_U32 ack_seq; + MV_U16 flags; + MV_U16 window; + MV_U16 chksum; + MV_U16 urg_offset; + +} MV_TCP_HEADER; + +typedef struct { + MV_U16 source; + MV_U16 dest; + MV_U16 len; + MV_U16 check; + +} MV_UDP_HEADER; + +#endif /* __INCmv802_3h */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCommon.c u-boot-2009.08/board/marvell/common/mvCommon.c --- u-boot-2009.08.orig/board/marvell/common/mvCommon.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCommon.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,355 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" + +int mvCharToHex(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + + if ((ch >= 'a') && (ch <= 'f')) + return (ch - 'a') + 10; + + if ((ch >= 'A') && (ch <= 'F')) + return (ch - 'A') + 10; + + return -1; +} + +int mvCharToDigit(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + + return -1; +} + +/******************************************************************************* +* mvMacStrToHex - Convert MAC format string to hex. +* +* DESCRIPTION: +* This function convert MAC format string to hex. +* +* INPUT: +* macStr - MAC address string. Fornat of address string is +* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter. +* +* OUTPUT: +* macHex - MAC in hex format. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacStrToHex(const char *macStr, MV_U8 *macHex) +{ + int i; + char tmp[3]; + + for (i = 0; i < MV_MAC_ADDR_SIZE; i++) { + tmp[0] = macStr[(i * 3) + 0]; + tmp[1] = macStr[(i * 3) + 1]; + tmp[2] = '\0'; + macHex[i] = (MV_U8) (strtol(tmp, NULL, 16)); + } + return MV_OK; +} + +/******************************************************************************* +* mvMacHexToStr - Convert MAC in hex format to string format. +* +* DESCRIPTION: +* This function convert MAC in hex format to string format. +* +* INPUT: +* macHex - MAC in hex format. +* +* OUTPUT: +* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacHexToStr(MV_U8 *macHex, char *macStr) +{ + int i; + + for (i = 0; i < MV_MAC_ADDR_SIZE; i++) + mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]); + + macStr[(i * 3) - 1] = '\0'; + + return MV_OK; +} + +/******************************************************************************* +* mvSizePrint - Print the given size with size unit description. +* +* DESCRIPTION: +* This function print the given size with size unit description. +* FOr example when size paramter is 0x180000, the function prints: +* "size 1MB+500KB" +* +* INPUT: +* size - Size in bytes. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSizePrint(MV_U32 size) +{ + mvOsOutput("size "); + + if (size >= _1G) { + mvOsOutput("%3dGB ", size / _1G); + size %= _1G; + if (size) + mvOsOutput("+"); + } + if (size >= _1M) { + mvOsOutput("%3dMB ", size / _1M); + size %= _1M; + if (size) + mvOsOutput("+"); + } + if (size >= _1K) { + mvOsOutput("%3dKB ", size / _1K); + size %= _1K; + if (size) + mvOsOutput("+"); + } + if (size > 0) + mvOsOutput("%3dB ", size); + +} + +/******************************************************************************* +* mvHexToBin - Convert hex to binary +* +* DESCRIPTION: +* This function Convert hex to binary. +* +* INPUT: +* pHexStr - hex buffer pointer. +* size - Size to convert. +* +* OUTPUT: +* pBin - Binary buffer pointer. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvHexToBin(const char *pHexStr, MV_U8 *pBin, int size) +{ + int j, i; + char tmp[3]; + MV_U8 byte; + + for (j = 0, i = 0; j < size; j++, i += 2) { + tmp[0] = pHexStr[i]; + tmp[1] = pHexStr[i + 1]; + tmp[2] = '\0'; + byte = (MV_U8) (strtol(tmp, NULL, 16) & 0xFF); + pBin[j] = byte; + } +} + +void mvAsciiToHex(const char *asciiStr, char *hexStr) +{ + int i = 0; + + while (asciiStr[i] != 0) { + mvOsSPrintf(&hexStr[i * 2], "%02x", asciiStr[i]); + i++; + } + hexStr[i * 2] = 0; +} + +void mvBinToHex(const MV_U8 *bin, char *hexStr, int size) +{ + int i; + + for (i = 0; i < size; i++) + mvOsSPrintf(&hexStr[i * 2], "%02x", bin[i]); + + hexStr[i * 2] = '\0'; +} + +void mvBinToAscii(const MV_U8 *bin, char *asciiStr, int size) +{ + int i; + + for (i = 0; i < size; i++) + mvOsSPrintf(&asciiStr[i * 2], "%c", bin[i]); + + asciiStr[i * 2] = '\0'; +} + +/******************************************************************************* +* mvLog2 - +* +* DESCRIPTION: +* Calculate the Log2 of a given number. +* +* INPUT: +* num - A number to calculate the Log2 for. +* +* OUTPUT: +* None. +* +* RETURN: +* Log 2 of the input number, or 0xFFFFFFFF if input is 0. +* +*******************************************************************************/ +MV_U32 mvLog2(MV_U32 num) +{ + MV_U32 result = 0; + if (num == 0) + return 0xFFFFFFFF; + while (num != 1) { + num = num >> 1; + result++; + } + return result; +} + +/******************************************************************************* +* mvWinOverlapTest +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS mvWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + /* check if we have overflow than 4G */ + if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size - 1) || + ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size - 1)) { + return MV_TRUE; + } + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size - 1; + winTop2 = winBase2 + pAddrWin2->size - 1; + + if (((winBase1 <= winTop2) && (winTop2 <= winTop1)) || ((winBase1 <= winBase2) && (winBase2 <= winTop1))) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvWinWithinWinTest +* +* DESCRIPTION: +* This function checks the given win1 boundries is within win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS mvWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size - 1; + winTop2 = winBase2 + pAddrWin2->size - 1; + + if (((winBase1 >= winBase2) && (winBase1 <= winTop2)) || ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + return MV_TRUE; + else + return MV_FALSE; +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCommon.h u-boot-2009.08/board/marvell/common/mvCommon.h --- u-boot-2009.08.orig/board/marvell/common/mvCommon.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCommon.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,359 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCommonh +#define __INCmvCommonh + +#include "mvTypes.h" +#include "mvDeviceId.h" +#ifndef MV_ASMLANGUAGE +#include "mv802_3.h" +#include "mvVideo.h" +#endif + +/* Swap tool */ + +/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ +#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4)) + +/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ +#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4) | \ + ((X&0xf0000) << 4) | \ + ((X&0xf00000) >> 4) | \ + ((X&0xf000000) << 4) | \ + ((X&0xf0000000) >> 4)) + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) + +/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ +#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ + (((X)&0xff00ULL)<<40) | \ + (((X)&0xff0000ULL)<<24) | \ + (((X)&0xff000000ULL)<<8) | \ + (((X)&0xff00000000ULL)>>8) | \ + (((X)&0xff0000000000ULL)>>24) | \ + (((X)&0xff000000000000ULL)>>40) | \ + (((X)&0xff00000000000000ULL)>>56))) + +/* Endianess macros. */ +#if defined(MV_CPU_LE) +#define MV_16BIT_LE(X) (X) +#define MV_32BIT_LE(X) (X) +#define MV_64BIT_LE(X) (X) +#define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) +#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) +#elif defined(MV_CPU_BE) +#define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) +#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) +#define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) +#define MV_16BIT_BE(X) (X) +#define MV_32BIT_BE(X) (X) +#define MV_64BIT_BE(X) (X) +#else +#error "CPU endianess isn't defined!\n" +#endif + +/* Bit field definitions */ +#define NO_BIT 0x00000000 + +/* avoid redefinition of bits */ +#ifndef BIT0 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT0 */ +/* Handy sizes */ +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/* Tclock and Sys clock define */ +#define _100MHz 100000000 +#define _125MHz 125000000 +#define _133MHz 133333334 +#define _150MHz 150000000 +#define _160MHz 160000000 +#define _166MHz 166666667 +#define _175MHz 175000000 +#define _178MHz 178000000 +#define _183MHz 183333334 +#define _187MHz 187000000 +#define _192MHz 192000000 +#define _194MHz 194000000 +#define _200MHz 200000000 +#define _233MHz 233333334 +#define _250MHz 250000000 +#define _266MHz 266666667 +#define _300MHz 300000000 + +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333333 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 +#define MV_BOARD_TCLK_250MHZ 250000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333333 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_233MHZ 233333333 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 +#define MV_BOARD_SYSCLK_300MHZ 300000000 +#define MV_BOARD_SYSCLK_333MHZ 333333334 +#define MV_BOARD_SYSCLK_400MHZ 400000000 + +#define MV_BOARD_REFCLK_25MHZ 25000000 + +/* For better address window table readability */ +#define EN MV_TRUE +#define DIS MV_FALSE +#define N_A -1 /* Not applicable */ + +/* Cache configuration options for memory (DRAM, SRAM, ... ) */ + +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +/* Macro for testing aligment. Positive if number is NOT aligned */ +#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) + +/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ +#define MV_ALIGN_UP(number, align) \ +(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) + +/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ +#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) + +/* This macro returns absolute value */ +#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) + +/* Bit fields manipulation macros */ + +/* An integer word which its 'x' bit is set */ +#define MV_BIT_MASK(bitNum) (1 << (bitNum)) + +/* Checks wheter bit 'x' in integer word is set */ +#define MV_BIT_CHECK(word, bitNum) ((word) & MV_BIT_MASK(bitNum)) + +/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ +#define MV_BIT_CLEAR(word, bitNum) ((word) &= ~(MV_BIT_MASK(bitNum))) + +/* Set bit 'x' in integer word (RMW) */ +#define MV_BIT_SET(word, bitNum) ((word) |= MV_BIT_MASK(bitNum)) + +/* Invert bit 'x' in integer word (RMW) */ +#define MV_BIT_INV(word, bitNum) ((word) ^= MV_BIT_MASK(bitNum)) + +/* Get the min between 'a' or 'b' */ +#define MV_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/* Get the max between 'a' or 'b' */ +#define MV_MAX(a, b) (((a) < (b)) ? (b) : (a)) + +#define mvOsDivide(num, div) \ +({ \ + int i = 0, rem = (num); \ + while (rem >= (div)) { \ + rem -= (div); \ + i++; \ + } \ + (i); \ +}) + +#define mvOsReminder(num, div) \ +({ \ + int rem = (num); \ + while (rem >= (div)) \ + rem -= (div); \ + (rem); \ +}) + +#define MV_MACQUAD_FMT "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x" + +#define MV_MACQUAD(addr) \ + ((unsigned char *)addr)[0], \ + ((unsigned char *)addr)[1], \ + ((unsigned char *)addr)[2], \ + ((unsigned char *)addr)[3], \ + ((unsigned char *)addr)[4], \ + ((unsigned char *)addr)[5] + +#define MV_IPQUAD_FMT "%u.%u.%u.%u" +#define MV_IPQUAD(ip) (ip&0xFF), ((ip>>8)&0xFF), ((ip>>16)&0xFF), ((ip>>24)&0xFF) +#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) + +#define MV_IP6_FMT "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x" +#define MV_IP6_ARG(L3) L3[0], L3[1], L3[2], L3[3], \ + L3[4], L3[5], L3[6], L3[7], \ + L3[8], L3[9], L3[10], L3[11], \ + L3[12], L3[13], L3[14], L3[15] + +#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) + +#define MV_GET_BIT(word, bitNum) (((word) & (1 << (bitNum))) >> (bitNum)) + +#define MV_SET_BIT(word, bitNum, bitVal) (((word) & ~(1 << (bitNum))) | (bitVal << bitNum)) + +#ifndef MV_ASMLANGUAGE +/* mvCommon API list */ + +int mvCharToHex(char ch); +int mvCharToDigit(char ch); + +MV_VOID mvHexToBin(const char *pHexStr, MV_U8 *pBin, int size); +void mvAsciiToHex(const char *asciiStr, char *hexStr); +void mvBinToHex(const MV_U8 *bin, char *hexStr, int size); +void mvBinToAscii(const MV_U8 *bin, char *asciiStr, int size); + +MV_STATUS mvMacStrToHex(const char *macStr, MV_U8 *macHex); +MV_STATUS mvMacHexToStr(MV_U8 *macHex, char *macStr); +void mvSizePrint(MV_U32); + +MV_U32 mvLog2(MV_U32 num); + +MV_STATUS mvWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS mvWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCommonh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvCompVer.txt u-boot-2009.08/board/marvell/common/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/common/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvCompVer.txt 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,2 @@ +Global HAL Version:FEROCEON_HAL_3_1_7 + Unit HAL Version:3.1 .4 Description:This component includes an implementation of the unit HAL drivers diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDebug.c u-boot-2009.08/board/marvell/common/mvDebug.c --- u-boot-2009.08.orig/board/marvell/common/mvDebug.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDebug.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,275 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mv802_3.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "mvDebug.h" + +/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros + * mvDebug - map of bits (one for each module) bit=1 means enable + * debug code and messages for this module + * mvModuleDebug - array of 32 bits varables one for each module + */ +MV_U32 mvDebug = 0; +MV_U32 mvDebugModules[MV_MODULE_MAX]; + +/* Init mvModuleDebug array to default values */ +void mvDebugInit(void) +{ + int bit; + + mvDebug = 0; + for (bit = 0; bit < MV_MODULE_MAX; bit++) { + mvDebugModules[bit] = MV_DEBUG_FLAG_ERR | MV_DEBUG_FLAG_STATS; + mvDebug |= MV_BIT_MASK(bit); + } +} + +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable) +{ + if (isEnable) + MV_BIT_SET(mvDebug, module); + else + MV_BIT_CLEAR(mvDebug, module); +} + +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags) +{ + mvDebugModules[module] |= flags; +} + +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags) +{ + mvDebugModules[module] &= ~flags; +} + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void *addr, int size, int access) +{ + int i, j; + MV_U32 memAddr = (MV_U32) addr; + + if (access == 0) + access = 1; + + if ((access != 4) && (access != 2) && (access != 1)) { + mvOsPrintf("%d wrong access size. Access must be 1 or 2 or 4\n", access); + return; + } + memAddr = MV_ALIGN_DOWN((unsigned int)addr, 4); + size = MV_ALIGN_UP(size, 4); + addr = (void *)MV_ALIGN_DOWN((unsigned int)addr, access); + while (size > 0) { + mvOsPrintf("%08x: ", memAddr); + i = 0; + /* 32 bytes in the line */ + while (i < 32) { + if (memAddr >= (MV_U32) addr) { + switch (access) { + case 1: + mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); + break; + + case 2: + mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); + break; + + case 4: + mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); + break; + } + } else { + for (j = 0; j < (access * 2 + 1); j++) + mvOsPrintf(" "); + } + i += access; + memAddr += access; + size -= access; + if (size <= 0) + break; + } + mvOsPrintf("\n"); + } +} + +void mvDebugPrintBufInfo(BUF_INFO *pBufInfo, int size, int access) +{ + if (pBufInfo == NULL) { + mvOsPrintf("\n!!! pBufInfo = NULL\n"); + return; + } + mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", + (unsigned int)pBufInfo, + (unsigned int)pBufInfo->cmdSts, (unsigned int)pBufInfo->pBuff, (unsigned int)pBufInfo->bufSize); + mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", + (unsigned int)pBufInfo->pData, + (unsigned int)pBufInfo->byteCnt, + (unsigned int)pBufInfo->pNextBufInfo, + (unsigned int)pBufInfo->userInfo1, (unsigned int)pBufInfo->userInfo2); + if (pBufInfo->pData != NULL) { + if (size > pBufInfo->byteCnt) + size = pBufInfo->byteCnt; + mvDebugMemDump(pBufInfo->pData, size, access); + } +} + +void mvDebugPrintPktInfo(MV_PKT_INFO *pPktInfo, int size, int access) +{ + int frag, len; + + if (pPktInfo == NULL) { + mvOsPrintf("\n!!! pPktInfo = NULL\n"); + return; + } + mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", + pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, + pPktInfo->pFrags, pPktInfo->osInfo); + + for (frag = 0; frag < pPktInfo->numFrags; frag++) { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pPktInfo->pFrags[frag].bufVirtPtr, pPktInfo->pFrags[frag].bufSize); + if (size > 0) { + len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); + mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); + size -= len; + } + } + +} + +void mvDebugPrintIpAddr(MV_U32 ipAddr) +{ + mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); +} + +void mvDebugPrintMacAddr(const MV_U8 *pMacAddr) +{ + int i; + + mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); + for (i = 1; i < MV_MAC_ADDR_SIZE; i++) + mvOsPrintf(":%02x", pMacAddr[i]); + + /* mvOsPrintf("\n"); */ +} + +/******* There are three functions deals with MV_DEBUG_TIMES structure ********/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES *pTimeEntry, int count, char *pName) +{ + pTimeEntry->begin = 0; + pTimeEntry->count = count; + pTimeEntry->end = 0; + pTimeEntry->left = pTimeEntry->count; + pTimeEntry->total = 0; + pTimeEntry->min = 0xFFFFFFFF; + pTimeEntry->max = 0x0; + strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name) - 1); + pTimeEntry->name[sizeof(pTimeEntry->name) - 1] = '\0'; +} + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES *pTimeEntry, MV_BOOL isTitle) +{ + int num; + + if (isTitle == MV_TRUE) + mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); + + num = pTimeEntry->count - pTimeEntry->left; + if (num > 0) { + mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", + pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total / num, + pTimeEntry->min, pTimeEntry->max); + } +} + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES *pTimeEntry) +{ + MV_U32 delta; + + if (pTimeEntry->left > 0) { + if (pTimeEntry->end <= pTimeEntry->begin) + delta = pTimeEntry->begin - pTimeEntry->end; + else + delta = ((MV_U32) 0x10000 - pTimeEntry->end) + pTimeEntry->begin; + + pTimeEntry->total += delta; + + if (delta < pTimeEntry->min) + pTimeEntry->min = delta; + + if (delta > pTimeEntry->max) + pTimeEntry->max = delta; + + pTimeEntry->left--; + } +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDebug.h u-boot-2009.08/board/marvell/common/mvDebug.h --- u-boot-2009.08.orig/board/marvell/common/mvDebug.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDebug.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,169 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDebugh +#define __INCmvDebugh + +/* includes */ +#include "mvTypes.h" + +typedef enum { + MV_MODULE_INVALID = -1, + MV_MODULE_ETH = 0, + MV_MODULE_IDMA, + MV_MODULE_XOR, + MV_MODULE_TWASI, + MV_MODULE_MGI, + MV_MODULE_USB, + MV_MODULE_CESA, + + MV_MODULE_MAX +} MV_MODULE_ID; + +/* Define generic flags useful for most of modules */ +#define MV_DEBUG_FLAG_ALL (0) +#define MV_DEBUG_FLAG_INIT (1 << 0) +#define MV_DEBUG_FLAG_RX (1 << 1) +#define MV_DEBUG_FLAG_TX (1 << 2) +#define MV_DEBUG_FLAG_ERR (1 << 3) +#define MV_DEBUG_FLAG_TRACE (1 << 4) +#define MV_DEBUG_FLAG_DUMP (1 << 5) +#define MV_DEBUG_FLAG_CACHE (1 << 6) +#define MV_DEBUG_FLAG_IOCTL (1 << 7) +#define MV_DEBUG_FLAG_STATS (1 << 8) + +extern MV_U32 mvDebug; +extern MV_U32 mvDebugModules[MV_MODULE_MAX]; + +#ifdef MV_DEBUG +# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) code +#elif defined(MV_RT_DEBUG) +# define MV_DEBUG_PRINT(module, flags, msg) \ + if ((mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags))) \ + mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) \ + if ((mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags))) \ + code +#else +# define MV_DEBUG_PRINT(module, flags, msg) +# define MV_DEBUG_CODE(module, flags, code) +#endif + +/* typedefs */ + +/* time measurement structure used to check how much time pass between + * two points + */ +typedef struct { + char name[20]; /* name of the entry */ + unsigned long begin; /* time measured on begin point */ + unsigned long end; /* time measured on end point */ + unsigned long total; /* Accumulated time */ + unsigned long left; /* The rest measurement actions */ + unsigned long count; /* Maximum measurement actions */ + unsigned long min; /* Minimum time from begin to end */ + unsigned long max; /* Maximum time from begin to end */ +} MV_DEBUG_TIMES; + +/* mvDebug.h API list */ + +/****** Error Recording ******/ + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void *addr, int size, int access); + +void mvDebugPrintBufInfo(BUF_INFO *pBufInfo, int size, int access); + +void mvDebugPrintPktInfo(MV_PKT_INFO *pPktInfo, int size, int access); + +void mvDebugPrintIpAddr(MV_U32 ipAddr); + +void mvDebugPrintMacAddr(const MV_U8 *pMacAddr); + +/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES *pTimeEntry, int count, char *name); + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES *pTimeEntry); + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES *pTimeEntry, MV_BOOL isTitle); + +/******** General ***********/ + +/* Change value of mvDebugPrint global variable */ + +void mvDebugInit(void); +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); + +#endif /* __INCmvDebug.h */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvDeviceId.h u-boot-2009.08/board/marvell/common/mvDeviceId.h --- u-boot-2009.08.orig/board/marvell/common/mvDeviceId.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvDeviceId.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,293 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceIdh +#define __INCmvDeviceIdh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MARVELL_VEN_ID 0x11ab + +/* Disco-3 */ +#define MV64460_DEV_ID 0x6480 +#define MV64460B_DEV_ID 0x6485 +#define MV64430_DEV_ID 0x6420 + +/* Disco-5 */ +#define MV64560_DEV_ID 0x6450 + +/* Disco-6 */ +#define MV64660_DEV_ID 0x6460 + +/* Orion */ +#define MV_1181_DEV_ID 0x1181 +#define MV_5181_DEV_ID 0x5181 +#define MV_5281_DEV_ID 0x5281 +#define MV_5182_DEV_ID 0x5182 +#define MV_8660_DEV_ID 0x8660 +#define MV_5180_DEV_ID 0x5180 +#define MV_5082_DEV_ID 0x5082 +#define MV_1281_DEV_ID 0x1281 +#define MV_6082_DEV_ID 0x6082 +#define MV_6183_DEV_ID 0x6183 +#define MV_6183L_DEV_ID 0x6083 + +#define MV_5281_D0_REV 0x4 +#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) +#define MV_5281_D0_NAME "88F5281 D0" + +#define MV_5281_D1_REV 0x5 +#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) +#define MV_5281_D1_NAME "88F5281 D1" + +#define MV_5281_D2_REV 0x6 +#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) +#define MV_5281_D2_NAME "88F5281 D2" + +#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ +#define MV_5181_A1_REV 0x1 /* for USB Er .. */ +#define MV_5181_B0_REV 0x2 +#define MV_5181_B1_REV 0x3 +#define MV_5182_A1_REV 0x1 +#define MV_5180N_B1_REV 0x3 +#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) + +/* kw */ +#define MV_6281_DEV_ID 0x6281 +#define MV_6282_DEV_ID 0x1155 +#define MV_6192_DEV_ID 0x6192 +#define MV_6190_DEV_ID 0x6190 +#define MV_6180_DEV_ID 0x6180 +#define MV_6280_DEV_ID 0x6280 + +#define MV_6281_A0_REV 0x2 +#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) +#define MV_6281_A0_NAME "88F6281 A0" + +#define MV_6192_A0_REV 0x2 +#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) +#define MV_6192_A0_NAME "88F6192 A0" + +#define MV_6190_A0_REV 0x2 +#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) +#define MV_6190_A0_NAME "88F6190 A0" + +#define MV_6180_A0_REV 0x2 +#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) +#define MV_6180_A0_NAME "88F6180 A0" + +#define MV_6281_A1_REV 0x3 +#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) +#define MV_6281_A1_NAME "88F6281 A1" + +#define MV_6282_A1_REV 0x3 +#define MV_6282_A1_ID ((MV_6282_DEV_ID << 16) | MV_6282_A1_REV) +#define MV_6282_A1_NAME "88F6282 A1" + +#define MV_6280_A1_REV 0x3 +#define MV_6280_A1_ID ((MV_6280_DEV_ID << 16) | MV_6280_A0_REV) +#define MV_6280_A1_NAME "88F6280 A1" + +#define MV_6192_A1_REV 0x3 +#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) +#define MV_6192_A1_NAME "88F6192 A1" + +#define MV_6190_A1_REV 0x3 +#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) +#define MV_6190_A1_NAME "88F6190 A1" + +#define MV_6180_A1_REV 0x3 +#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) +#define MV_6180_A1_NAME "88F6180 A1" + +#define MV_88F6XXX_A0_REV 0x2 +#define MV_88F6XXX_A1_REV 0x3 +/* Disco-Duo */ +#define MV_78XX0_ZY_DEV_ID 0x6381 +#define MV_78XX0_ZY_NAME "MV78X00" + +#define MV_78XX0_Z0_REV 0x1 +#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) +#define MV_78XX0_Z0_NAME "78X00 Z0" + +#define MV_78XX0_Y0_REV 0x2 +#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) +#define MV_78XX0_Y0_NAME "78X00 Y0" + +#define MV_78XX0_DEV_ID 0x7800 +#define MV_78XX0_NAME "MV78X00" + +#define MV_76100_DEV_ID 0x7610 +#define MV_78200_DEV_ID 0x7820 +#define MV_78100_DEV_ID 0x7810 +#define MV_78XX0_A0_REV 0x1 +#define MV_78XX0_A1_REV 0x2 + +#define MV_76100_NAME "MV76100" +#define MV_78100_NAME "MV78100" +#define MV_78200_NAME "MV78200" + +#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) + +#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) + +#define MV_76100_A0_NAME "MV76100 A0" +#define MV_78100_A0_NAME "MV78100 A0" +#define MV_78200_A0_NAME "MV78200 A0" +#define MV_78XX0_A0_NAME "MV78XX0 A0" + +#define MV_76100_A1_NAME "MV76100 A1" +#define MV_78100_A1_NAME "MV78100 A1" +#define MV_78200_A1_NAME "MV78200 A1" +#define MV_78XX0_A1_NAME "MV78XX0 A1" + +/*MV88F632X family*/ +#define MV_6321_DEV_ID 0x6321 +#define MV_6322_DEV_ID 0x6322 +#define MV_6323_DEV_ID 0x6323 + +#define MV_6321_NAME "88F6321" +#define MV_6322_NAME "88F6322" +#define MV_6323_NAME "88F6323" + +#define MV_632X_A1_REV 0x2 + +#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) + +#define MV_6321_A1_NAME "88F6321 A1" +#define MV_6322_A1_NAME "88F6322 A1" +#define MV_6323_A1_NAME "88F6323 A1" + +/*MV88F6500 family*/ +#define MV_65XX_DEV_ID 0x6500 +#define MV_6510_DEV_ID 0x6510 +#define MV_6530_DEV_ID 0x6530 +#define MV_6550_DEV_ID 0x6550 +#define MV_6560_DEV_ID 0x6560 + +#define MV_6510_Z0_REV 0x1 +#define MV_6510_Z0_ID ((MV_6510_DEV_ID << 16) | MV_6510_Z0_REV) +#define MV_6510_Z0_NAME "88F6510 Z0" + +#define MV_6530_Z0_REV 0x1 +#define MV_6530_Z0_ID ((MV_6530_DEV_ID << 16) | MV_6530_Z0_REV) +#define MV_6530_Z0_NAME "88F6530 Z0" + +#define MV_6550_Z0_REV 0x1 +#define MV_6550_Z0_ID ((MV_6550_DEV_ID << 16) | MV_6550_Z0_REV) +#define MV_6550_Z0_NAME "88F6550 Z0" + +#define MV_6560_Z0_REV 0x1 +#define MV_6560_Z0_ID ((MV_6560_DEV_ID << 16) | MV_6560_Z0_REV) +#define MV_6560_Z0_NAME "88F6560 Z0" + + +/* KW40 */ +#define MV_6710_DEV_ID 0x6710 + +#define MV_6710_Z1_REV 0x0 +#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV) +#define MV_6710_Z1_NAME "MV6710 Z1" + +/* Armada XP Family */ +#define MV_78130_DEV_ID 0x7813 +#define MV_78160_DEV_ID 0x7816 +#define MV_78230_DEV_ID 0x7823 +#define MV_78260_DEV_ID 0x7826 +#define MV_78460_DEV_ID 0x7846 +#define MV_78000_DEV_ID 0x7888 + +#define MV_FPGA_DEV_ID 0x2107 + +#define MV_78XX0_Z1_REV 0x0 + +#define MV_78130_Z1_ID ((MV_78130_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78130_Z1_NAME "MV78130 Z1" + +#define MV_78160_Z1_ID ((MV_78160_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78160_Z1_NAME "MV78160 Z1" + +#define MV_78230_Z1_ID ((MV_78230_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78230_Z1_NAME "MV78230 Z1" + +#define MV_78260_Z1_ID ((MV_78260_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78260_Z1_NAME "MV78260 Z1" + +#define MV_78460_Z1_ID ((MV_78460_DEV_ID << 16) | MV_78XX0_Z1_REV) +#define MV_78460_Z1_NAME "MV78460 Z1" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDeviceIdh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvHalVer.h u-boot-2009.08/board/marvell/common/mvHalVer.h --- u-boot-2009.08.orig/board/marvell/common/mvHalVer.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvHalVer.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvHalVerh +#define __INCmvHalVerh + +/* Defines */ +#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" +#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" + +#endif /* __INCmvHalVerh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvList.h u-boot-2009.08/board/marvell/common/mvList.h --- u-boot-2009.08.orig/board/marvell/common/mvList.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvList.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,78 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvList_h__ +#define __mvList_h__ + +#include "mvCommon.h" +#include "mvOs.h" + +typedef struct mv_list { + struct mv_list *prev; + struct mv_list *next; + unsigned long data; + +} MV_LIST; + +static INLINE MV_LIST *mvListFind(MV_LIST *head, MV_ULONG data) +{ + return NULL; +} + +/* Add new element before head */ +static INLINE MV_LIST *mvListAddHead(MV_LIST **head, MV_ULONG data) +{ + MV_LIST *element; + + element = mvOsMalloc(sizeof(MV_LIST)); + if (element) { + element->data = data; + element->next = (*head); + element->prev = NULL; + if (*head) + (*head)->prev = element; + + *head = element; + } + return element; +} + +static INLINE MV_LIST *mvListDel(MV_LIST **list) +{ + MV_LIST *prev = (*list)->prev; + MV_LIST *next = (*list)->next; + + mvOsFree(*list); + + if (prev) + prev->next = next; + else + (*list) = next; + + if (next) + next->prev = prev; + + return next; +} + +#endif /* __mvList_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvStack.c u-boot-2009.08/board/marvell/common/mvStack.c --- u-boot-2009.08.orig/board/marvell/common/mvStack.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvStack.c 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvQueue.c +* +* FILENAME: $Workfile: mvStack.c $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file implements simple Stack LIFO functionality. +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvStack.h" + +/* defines */ + +/* Public functions */ + +/* Purpose: Create new stack + * Inputs: + * - MV_U32 noOfElements - maximum number of elements in the stack. + * Each element 4 bytes size + * Return: void* - pointer to created stack. + */ +void *mvStackCreate(int numOfElements) +{ + MV_STACK *pStack; + MV_U32 *pStackElements; + + pStack = (MV_STACK *) mvOsMalloc(sizeof(MV_STACK)); + pStackElements = (MV_U32 *) mvOsMalloc(numOfElements * sizeof(MV_U32)); + if ((pStack == NULL) || (pStackElements == NULL)) { + mvOsPrintf("mvStack: Can't create new stack\n"); + if (pStack) + mvOsFree(pStack); + if (pStackElements) + mvOsFree(pStackElements); + return NULL; + } + memset(pStackElements, 0, numOfElements * sizeof(MV_U32)); + pStack->numOfElements = numOfElements; + pStack->stackIdx = 0; + pStack->stackElements = pStackElements; + + return pStack; +} + +/* Purpose: Delete existing stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function + * + * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. + * MV_OK - Success. + */ +MV_STATUS mvStackDelete(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if ((pStack == NULL) || (pStack->stackElements == NULL)) + return MV_NOT_FOUND; + + mvOsFree(pStack->stackElements); + mvOsFree(pStack); + + return MV_OK; +} + +/* PrintOut status of the stack */ +void mvStackStatus(void *stackHndl, MV_BOOL isPrintElements) +{ + int i; + MV_STACK *pStack = (MV_STACK *) stackHndl; + + mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", + stackHndl, pStack->stackElements, pStack->numOfElements, pStack->stackIdx); + if (isPrintElements == MV_TRUE) { + for (i = 0; i < pStack->stackIdx; i++) + mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); + } +} diff -Naur u-boot-2009.08.orig/board/marvell/common/mvStack.h u-boot-2009.08/board/marvell/common/mvStack.h --- u-boot-2009.08.orig/board/marvell/common/mvStack.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvStack.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,133 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvStack_h__ +#define __mvStack_h__ + +/* includes */ +#include "mvTypes.h" + +/* defines */ + +/* typedefs */ +/* Data structure describes general purpose Stack */ +typedef struct { + int stackIdx; + int numOfElements; + MV_U32 *stackElements; +} MV_STACK; + +static INLINE MV_BOOL mvStackIsFull(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if (pStack->stackIdx == pStack->numOfElements) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE MV_BOOL mvStackIsEmpty(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + if (pStack->stackIdx == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Purpose: Push new element to stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - New element. + * + * Return: MV_STATUS MV_FULL - Failure. Stack is full. + * MV_OK - Success. Element is put to stack. + */ +static INLINE void mvStackPush(void *stackHndl, MV_U32 value) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + +#ifdef MV_RT_DEBUG + if (pStack->stackIdx == pStack->numOfElements) { + mvOsPrintf("mvStackPush: Stack is FULL\n"); + return; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackElements[pStack->stackIdx] = value; + pStack->stackIdx++; +} + +/* Purpose: Pop element from the top of stack and copy it to "pValue" + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - Element in the top of stack. + * + * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. + * MV_OK - Success. Element is removed from the stack and + * copied to pValue argument + */ +static INLINE MV_U32 mvStackPop(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + +#ifdef MV_RT_DEBUG + if (pStack->stackIdx == 0) { + mvOsPrintf("mvStackPop: Stack is EMPTY\n"); + return 0; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackIdx--; + return pStack->stackElements[pStack->stackIdx]; +} + +static INLINE int mvStackIndex(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + return pStack->stackIdx; +} + +static INLINE int mvStackFreeElements(void *stackHndl) +{ + MV_STACK *pStack = (MV_STACK *) stackHndl; + + return (pStack->numOfElements - pStack->stackIdx); +} + +/* mvStack.h API list */ + +/* Create new Stack */ +void *mvStackCreate(int numOfElements); + +/* Delete existing stack */ +MV_STATUS mvStackDelete(void *stackHndl); + +/* Print status of the stack */ +void mvStackStatus(void *stackHndl, MV_BOOL isPrintElements); + +#endif /* __mvStack_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvTypes.h u-boot-2009.08/board/marvell/common/mvTypes.h --- u-boot-2009.08.orig/board/marvell/common/mvTypes.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvTypes.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,269 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTypesh +#define __INCmvTypesh + +/* Defines */ + +/* The following is a list of Marvell status */ +#define MV_ERROR (-1) +#define MV_OK (0) /* Operation succeeded */ +#define MV_FAIL (1) /* Operation failed */ +#define MV_BAD_VALUE (2) /* Illegal value (general) */ +#define MV_OUT_OF_RANGE (3) /* The value is out of range */ +#define MV_BAD_PARAM (4) /* Illegal parameter in function called */ +#define MV_BAD_PTR (5) /* Illegal pointer value */ +#define MV_BAD_SIZE (6) /* Illegal size */ +#define MV_BAD_STATE (7) /* Illegal state of state machine */ +#define MV_SET_ERROR (8) /* Set operation failed */ +#define MV_GET_ERROR (9) /* Get operation failed */ +#define MV_CREATE_ERROR (10) /* Fail while creating an item */ +#define MV_NOT_FOUND (11) /* Item not found */ +#define MV_NO_MORE (12) /* No more items found */ +#define MV_NO_SUCH (13) /* No such item */ +#define MV_TIMEOUT (14) /* Time Out */ +#define MV_NO_CHANGE (15) /* Parameter(s) is already in this value */ +#define MV_NOT_SUPPORTED (16) /* This request is not support */ +#define MV_NOT_IMPLEMENTED (17) /* Request supported but not implemented */ +#define MV_NOT_INITIALIZED (18) /* The item is not initialized */ +#define MV_NO_RESOURCE (19) /* Resource not available (memory ...) */ +#define MV_FULL (20) /* Item is full (Queue or table etc...) */ +#define MV_EMPTY (21) /* Item is empty (Queue or table etc...) */ +#define MV_INIT_ERROR (22) /* Error occured while INIT process */ +#define MV_HW_ERROR (23) /* Hardware error */ +#define MV_TX_ERROR (24) /* Transmit operation not succeeded */ +#define MV_RX_ERROR (25) /* Recieve operation not succeeded */ +#define MV_NOT_READY (26) /* The other side is not ready yet */ +#define MV_ALREADY_EXIST (27) /* Tried to create existing item */ +#define MV_OUT_OF_CPU_MEM (28) /* Cpu memory allocation failed. */ +#define MV_NOT_STARTED (29) /* Not started yet */ +#define MV_BUSY (30) /* Item is busy. */ +#define MV_TERMINATE (31) /* Item terminates it's work. */ +#define MV_NOT_ALIGNED (32) /* Wrong alignment */ +#define MV_NOT_ALLOWED (33) /* Operation NOT allowed */ +#define MV_WRITE_PROTECT (34) /* Write protected */ +#define MV_DROPPED (35) /* Packet dropped */ +#define MV_STOLEN (36) /* Packet stolen */ + +#define MV_INVALID (int)(-1) + +#define MV_FALSE 0 +#define MV_TRUE (!(MV_FALSE)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef MV_ASMLANGUAGE +/* typedefs */ + +typedef char MV_8; +typedef unsigned char MV_U8; + +typedef int MV_32; +typedef unsigned int MV_U32; + +typedef short MV_16; +typedef unsigned short MV_U16; + +#ifdef MV_PPC64 +typedef long MV_64; +typedef unsigned long MV_U64; +#else +typedef long long MV_64; +typedef unsigned long long MV_U64; +#endif + +typedef long MV_LONG; /* 32/64 */ +typedef unsigned long MV_ULONG; /* 32/64 */ + +typedef int MV_STATUS; +typedef int MV_BOOL; +typedef void MV_VOID; +typedef float MV_FLOAT; +/*typedef _Bool MV_STD_BOOL;*/ + +typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ +typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double */ +typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ + +typedef MV_U32 MV_KHZ; +typedef MV_U32 MV_MHZ; +typedef MV_U32 MV_HZ; + +/* This enumerator describes the set of commands that can be applied on */ +/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ +/* status (see MV_STATE enumerator) */ +/* Start can be applied only when status is IDLE */ +/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ +/* Pause can be applied only when status is ACTIVE */ +/* Restart can be applied only when status is PAUSED */ +typedef enum _mvCommand { + MV_START, /* Start */ + MV_STOP, /* Stop */ + MV_PAUSE, /* Pause */ + MV_RESTART /* Restart */ +} MV_COMMAND; + +/* This enumerator describes the set of state conditions. */ +/* Moving from one state to other is stricted. */ +typedef enum _mvState { + MV_IDLE, + MV_ACTIVE, + MV_PAUSED, + MV_UNDEFINED_STATE +} MV_STATE; + +typedef enum { + ETH_MAC_SPEED_10M, + ETH_MAC_SPEED_100M, + ETH_MAC_SPEED_1000M, + ETH_MAC_SPEED_AUTO, + +} MV_ETH_MAC_SPEED; + +/* This structure describes address space window. Window base can be */ +/* 64 bit, window size up to 4GB */ +typedef struct _mvAddrWin { + MV_U32 baseLow; /* 32bit base low */ + MV_U32 baseHigh; /* 32bit base high */ + MV_U32 size; /* 32bit size */ +} MV_ADDR_WIN; + +/* This binary enumerator describes protection attribute status */ +typedef enum _mvProtRight { + ALLOWED, /* Protection attribute allowed */ + FORBIDDEN /* Protection attribute forbidden */ +} MV_PROT_RIGHT; + +/* Unified struct for Rx and Tx packet operations. The user is required to */ +/* be familier only with Tx/Rx descriptor command status. */ +typedef struct _bufInfo { + MV_U32 cmdSts; /* Tx/Rx command status */ + MV_U16 byteCnt; /* Size of valid data in the buffer */ + MV_U16 bufSize; /* Total size of the buffer */ + MV_U8 *pBuff; /* Pointer to Buffer */ + MV_U8 *pData; /* Pointer to data in the Buffer */ + MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ + MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ + struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ +} BUF_INFO; + +/* This structure contains information describing one of buffers + * (fragments) they are built Ethernet packet. + */ +typedef struct { + MV_U8 *bufVirtPtr; + MV_ULONG bufPhysAddr; + MV_U32 bufSize; + MV_U32 dataSize; + MV_U32 memHandle; + MV_32 bufAddrShift; +} MV_BUF_INFO; + +/* This structure contains information describing Ethernet packet. + * The packet can be divided for few buffers (fragments) + */ +typedef struct { + MV_ULONG osInfo; + MV_BUF_INFO *pFrags; + MV_U32 status; + MV_U16 pktSize; + MV_U16 numFrags; + MV_U32 ownerId; + MV_U32 fragIP; + MV_U32 txq; +} MV_PKT_INFO; + +/* This structure describes SoC units address decode window */ +typedef struct { + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + MV_U8 attrib; /* chip select attributes */ + MV_U8 targetId; /* Target Id of this MV_TARGET */ +} MV_UNIT_WIN_INFO; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights { + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +} MV_ACCESS_RIGHTS; + +typedef struct _mvDecRegs { + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 ctrlReg; +} MV_DEC_REGS; + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvTypesh */ diff -Naur u-boot-2009.08.orig/board/marvell/common/mvVideo.h u-boot-2009.08/board/marvell/common/mvVideo.h --- u-boot-2009.08.orig/board/marvell/common/mvVideo.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/common/mvVideo.h 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvVideoh +#define __INCmvVideoh + +/* includes */ + +/* Defines */ + +typedef struct mvVideoResolution { + MV_U32 width; + MV_U32 height; + char *name; +} MV_VIDEO_RESOLUTION; + +/* + * Basic window sizes. + */ + +#define VGA_WIDTH 640 +#define VGA_HEIGHT 480 +#define QVGA_WIDTH 320 +#define QVGA_HEIGHT 240 +#define CIF_WIDTH 352 +#define CIF_HEIGHT 288 +#define QCIF_WIDTH 176 +#define QCIF_HEIGHT 144 + +#define MV_VIDEO_RESOLUTION_VGA {VGA_WIDTH, VGA_HEIGHT, "VGA"} +#define MV_VIDEO_RESOLUTION_QVGA {QVGA_WIDTH, QVGA_HEIGHT, "QVGA"} +#define MV_VIDEO_RESOLUTION_CIF {CIF_WIDTH, CIF_HEIGHT, "CIF"} +#define MV_VIDEO_RESOLUTION_QCIF {QCIF_WIDTH, QCIF_HEIGHT, "QCIF"} + +/* Pixel format */ +typedef enum mvPixFormatId { + MV_PIX_FORMAT_ID_RGB444 = 0x444, + MV_PIX_FORMAT_ID_RGB555 = 0x555, + MV_PIX_FORMAT_ID_RGB565 = 0x565, + MV_PIX_FORMAT_ID_YUV422 = 0x422, + MV_PIX_FORMAT_ID_RAW_BAYER = 0x111, +} MV_PIX_FORMAT_ID; + +typedef struct mvPixelFormat { + MV_PIX_FORMAT_ID id; + char *name; +} MV_PIXEL_FORMAT; + +/* known formats */ +#define MV_PIXEL_FORMAT_RGB444 {MV_PIX_FORMAT_ID_RGB444, "RGB444"} +#define MV_PIXEL_FORMAT_RGB555 {MV_PIX_FORMAT_ID_RGB555, "RGB555"} +#define MV_PIXEL_FORMAT_RGB565 {MV_PIX_FORMAT_ID_RGB565, "RGB565"} +#define MV_PIXEL_FORMAT_YUV422 {MV_PIX_FORMAT_ID_YUV422, "YUV422"} +#define MV_PIXEL_FORMAT_RAW_BAYER {MV_PIX_FORMAT_ID_RAW_BAYER, "RAW BAYER"} + +typedef struct { + MV_PIXEL_FORMAT pixelFormat; + MV_VIDEO_RESOLUTION resolution; +} MV_IMAGE_FORMAT; + +#endif /* __INCmvVideoh */ diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config_def.mk u-boot-2009.08/board/marvell/config_armada_xp/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config_def.mk 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config.mk u-boot-2009.08/board/marvell/config_armada_xp/config.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config.mk 2011-04-04 13:57:34.874345176 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/config_nand.mk u-boot-2009.08/board/marvell/config_armada_xp/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/marvell/mv_dove/nBootstrap.o +NAND_OBJS += ./board/marvell/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/Makefile u-boot-2009.08/board/marvell/config_armada_xp/Makefile --- u-boot-2009.08.orig/board/marvell/config_armada_xp/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,113 @@ +include mvRules.mk + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +##$(HAL_SYS_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysCesa.o +##$(HAL_SYS_DIR)/mvSysAudio.o $(HAL_SYS_DIR)/mvSysCamController.o $(HAL_IF_DIR)/mvSysTdm.o + +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSpi.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + +# ## $(HAL_AC97_DIR)/mvAc97.o +# ## $(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/dac/mvCLAudioCodec.o +# ## $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +# ## $(HAL_CAMERA_DIR)/mvCamController.o $(HAL_CAMERA_DIR)/mvCamAddrDec.o +# ## $(HAL_CAMERA_DIR)/OV7680CamSensor.o +## $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o + +HAL_OBJS = $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o \ + $(HAL_NFC_DIR)/mvNfc.o + + +SOC_OBJS = $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o \ + $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o \ + $(SOC_DIR)/mv_phy.o $(SOC_DIR)/cmd_bubt.o $(SOC_DIR)/cmd_bios.o \ + $(SOC_DIR)/cmd_resetenv.o $(SOC_DIR)/cmd_pcie.o $(SOC_DIR)/cmd_ddr.o $(SOC_DIR)/cmd_sar.o + +##ifneq ($(MV_TINY_IMAGE), y) +##SOC_OBJS += $(HAL_PCIIF_DIR)/pci_util/mvPciUtils.o +##endif $(USP_DIR)/cmd_rcvr +## $(USP_DIR)/mv_nfc_nand.o +##$(USP_DIR)/cmd_loadnet.o + +USP_OBJS = $(USP_DIR)/mv_serial.o $(USP_DIR)/nand_nfc.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o \ + $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_flash.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o \ + $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o \ + $(USP_DIR)/mv_tsc2005.o \ + $(USP_DIR)/mv_sdhci.o $(USP_DIR)/mv_spi.o \ + $(USP_DIR)/mv_usb.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + + + +# ## $(HAL_SFLASH_DIR)/mvSFlash.o \ +# ## $(HAL_FLASH_DIR)/mvFlash.o $(HAL_FLASH_DIR)/mvAmdFlash.o \ +# ## $(HAL_FLASH_DIR)/mvIntelFlash.o $(HAL_FLASH_DIR)/mvFlashCom.o +# ## $(HAL_MFLASH_DIR)/mvMFlash.o +# ## $(HAL_MFLASH_DIR)/mvSMFlash.o $(HAL_MFLASH_DIR)/mvPMFlash.o + +# ##ifeq ($(NAND_BOOT), y) +# ##USP_OBJS += $(USP_DIR)/nBootloader.o +# ##endif + + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ +# $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o + + +## $(SOC_SYS_DIR)/mvCpuIfInit.o - do we need this?? + +# ifeq ($(NAND_BOOT), y) +# SOBJS += ../mv_dsmp/nBootstrap.o +# endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/mvRules.mk u-boot-2009.08/board/marvell/config_armada_xp/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_armada_xp/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,89 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = armada_xp +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/marvell +HAL_DIR = $(SRC_PATH)/mv_hal + +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +#HAL_DRAM_DIR = $(HAL_DIR)/ddr2_3 +#HAL_SPD_DIR = $(HAL_DIR)/ddr2_3/spd +HAL_DRAM_DIR = $(HAL_DIR)/ddr2_3/bak +HAL_SPD_DIR = $(HAL_DIR)/ddr2_3/bak/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +#HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa +HAL_NFC_DIR = $(HAL_DIR)/nfc + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_IF_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) -I$(USP_ETH_SWITCH_DIR) -I$(HAL_IF_DIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_SYS_DIR) -I$(SOC_ENV_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(CONFIG_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) -I$(TOPDIR) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-nand.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0xA0000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0xAFFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k-header.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/marvell/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_armada_xp/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_armada_xp/u-boot-sec64k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0xA0000; + .reset_vector_sect : { board/marvell/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0xAFFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_16mb.mk u-boot-2009.08/board/marvell/config_kw/config_16mb.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_16mb.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_16mb.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_def.mk u-boot-2009.08/board/marvell/config_kw/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_def.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config.mk u-boot-2009.08/board/marvell/config_kw/config.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,13 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_nand.mk u-boot-2009.08/board/marvell/config_kw/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/config_prpmc.mk u-boot-2009.08/board/marvell/config_kw/config_prpmc.mk --- u-boot-2009.08.orig/board/marvell/config_kw/config_prpmc.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/config_prpmc.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/Makefile u-boot-2009.08/board/marvell/config_kw/Makefile --- u-boot-2009.08.orig/board/marvell/config_kw/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,86 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o +##$(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +##$(HAL_TS_DIR)/mvTsu.o $(HAL_TS_DIR)/mvTsuAddrDec.o + +HAL_OBJS = $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o + +#$(HAL_IF_DIR)/mvSysTs.o +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysCesa.o $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysSpi.o $(HAL_IF_DIR)/mvSysTdm.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_service.o \ + $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +USP_OBJS = $(USP_DIR)/cmd_rcvr.o $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o $(USP_DIR)/mv_spi.o\ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o $(USP_DIR)/mv_mmc.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o $(USP_DIR)/mv_usb.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + +#ifeq ($(NAND_BOOT), y) +#USP_OBJS += $(USP_DIR)/nBootloader.o +#endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += ../mv_kw/nBootstrap.o +endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/mvRules.mk u-boot-2009.08/board/marvell/config_kw/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_kw/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,85 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = kw +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DIR)/ddr2/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) -I$(HAL_PCIIF_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(CONFIG_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot_16mb.lds u-boot-2009.08/board/marvell/config_kw/u-boot_16mb.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot_16mb.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot_16mb.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot.lds u-boot-2009.08/board/marvell/config_kw/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-nand.lds u-boot-2009.08/board/marvell/config_kw/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec128k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec128k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-header-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec4k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec4k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header-nand.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-header-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-header-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-tiny.lds u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw/u-boot-sec64k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw/u-boot-sec64k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_16mb.mk u-boot-2009.08/board/marvell/config_kw2/config_16mb.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_16mb.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_16mb.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_def.mk u-boot-2009.08/board/marvell/config_kw2/config_def.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_def.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_def.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config.mk u-boot-2009.08/board/marvell/config_kw2/config.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_nand.mk u-boot-2009.08/board/marvell/config_kw2/config_nand.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_nand.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_nand.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/config_prpmc.mk u-boot-2009.08/board/marvell/config_kw2/config_prpmc.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/config_prpmc.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/config_prpmc.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/Makefile u-boot-2009.08/board/marvell/config_kw2/Makefile --- u-boot-2009.08.orig/board/marvell/config_kw2/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/Makefile 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,86 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +##$(HAL_AUDIO_DIR)/mvAudio.o $(HAL_AUDIO_DIR)/mvAudioAddrDec.o mvDramIf.c +##$(HAL_TS_DIR)/mvTsu.o $(HAL_TS_DIR)/mvTsuAddrDec.o +HAL_OBJS = $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaAddrDec.o $(HAL_CESA_DIR)/mvMD5.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o \ + $(HAL_DRAM_DIR)/mvDramIf.o $(HAL_SPD_DIR)/mvSpd.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o \ + $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o \ + $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvSataAddrDec.o \ + $(HAL_SATA_CORE_DIR)/mvStorageDev.o $(HAL_SATA_CORE_DIR)/mvLog.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o \ + $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PCIIF_UTIL_DIR)/mvPciUtils.o + +##$(HAL_IF_DIR)/mvSysTs.o +HAL_IF_OBJS = $(HAL_IF_DIR)/mvSysCesa.o $(HAL_IF_DIR)/mvSysDdr.o \ + $(HAL_IF_DIR)/mvSysEth.o \ + $(HAL_IF_DIR)/mvSysEthPhy.o $(HAL_IF_DIR)/mvSysPex.o $(HAL_IF_DIR)/mvSysSata.o \ + $(HAL_IF_DIR)/mvSysSFlash.o $(HAL_IF_DIR)/mvSysSpi.o $(HAL_IF_DIR)/mvSysTdm.o \ + $(HAL_IF_DIR)/mvSysUsb.o $(HAL_IF_DIR)/mvSysXor.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_phy.o \ + $(SOC_DIR)/cmd_sar.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_ENV_DIR)/mvCtrlEthCompLib.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +USP_OBJS = $(USP_DIR)/cmd_rcvr.o $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o $(USP_DIR)/mv_spi.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o $(USP_DIR)/mv_mmc.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o $(USP_DIR)/mv_usb.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + +#ifeq ($(NAND_BOOT), y) +#USP_OBJS += $(USP_DIR)/nBootloader.o +#endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += ../mv_kw2/nBootstrap.o +endif + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(HAL_IF_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/mvRules.mk u-boot-2009.08/board/marvell/config_kw2/mvRules.mk --- u-boot-2009.08.orig/board/marvell/config_kw2/mvRules.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/mvRules.mk 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,85 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = kw2 +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +HAL_IF_DIR = $(SOC_DIR)/mv_hal_if +CONFIG_DIR = $(SOC_DIR)/config +FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(FAM_DIR)/cpu +SOC_DEVICE_DIR = $(FAM_DIR)/device +BOARD_ENV_DIR = $(FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DIR)/ddr2/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +#HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_PCIIF_UTIL_DIR = $(HAL_DIR)/pci-if/pci_util +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +#HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) -I$(TOPDIR) -I$(USP_ETH_SWITCH_DIR) +SOC_PATH = -I$(FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(CONFIG_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) -I$(HAL_IF_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +CPPFLAGS += $(CFLAGS) + diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot_16mb.lds u-boot-2009.08/board/marvell/config_kw2/u-boot_16mb.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot_16mb.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot_16mb.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot.lds u-boot-2009.08/board/marvell/config_kw2/u-boot.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-nand.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-nand.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec128k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec128k-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec256k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec256k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec256k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec256k.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-header-tiny.lds 2011-04-04 13:57:34.885596912 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec4k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec4k-tiny.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-header-nand.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff -Naur u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-tiny.lds u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-tiny.lds --- u-boot-2009.08.orig/board/marvell/config_kw2/u-boot-sec64k-tiny.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/config_kw2/u-boot-sec64k-tiny.lds 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,1950 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "eth/gbe/mvEthRegs.h" +#include "gpp/mvGppRegs.h" + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +extern MV_BOARD_INFO *boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; +extern MV_U8 mvDbDisableModuleDetection; + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_U32 nandDev; + MV_U32 reg; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + } + + nandDev = boardGetDevCSNum(0, BOARD_DEV_NAND_FLASH); + if (nandDev != 0xFFFFFFFF) { + /* Set NAND interface access parameters */ + nandDev = BOOT_CS; + MV_REG_WRITE(DEV_BANK_PARAM_REG(nandDev), BOARD_INFO(boardId)->nandFlashReadParams); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(nandDev), BOARD_INFO(boardId)->nandFlashWriteParams); + MV_REG_WRITE(DEV_NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl); + } + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValMid); + MV_REG_WRITE(GPP_DATA_OUT_REG(2), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValMid); + mvGppPolaritySet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Set GPP Out Enable */ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValMid); + mvGppTypeSet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); + + /* TODO FIXME */ +#if 0 + reg = MV_REG_READ(0x184e0); + reg &= ~0x3; + MV_REG_WRITE(0x184e0, reg); +#endif + +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsSPrintf(pNameBuff, "Board unknown.\n"); + return MV_ERROR; + } + if (mvCtrlModelRevGet() == MV_6710_Z1_ID) { + mvOsSPrintf(pNameBuff, "%s", "DB-6710-Z1"); + } else { + mvOsSPrintf(pNameBuff, "%s", BOARD_INFO(boardId)->boardName); + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + /* MV_U32 boardId = mvBoardIdGet(); */ + if (ethPortNum > 1) + return MV_TRUE; +#if 0 + if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod == MV_BOARD_MII_GMII) { + if (ethPortNum < 1) /* Port 0 and 1 can be connected as GMII module */ + return MV_TRUE; + } +#endif + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ +#ifdef TCLK_AUTO_DETECT + MV_U8 coreClock = 0; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_TCLCK0_MASK) != 0) + coreClock = 1; + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & MSAR_TCLCK1_MASK) != 0) + coreClock += 2; + + switch (coreClock) { + case 1: + return MV_BOARD_TCLK_166MHZ; + case 3: + return MV_BOARD_TCLK_200MHZ; + default: + return MV_BOARD_TCLK_250MHZ; + } +#else + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + return MV_BOARD_TCLK_250MHZ; +#endif +} + +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock , i.e. DDR clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardSysClkGet(MV_VOID) +{ +#ifdef SYSCLK_AUTO_DETECT + MV_U32 idx; + MV_U32 cpuFreqMhz, ddrFreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */ + cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */ + cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */ + ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr; + /* round up to integer MHz */ + if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5) + ddrFreqMhz++; + + return ddrFreqMhz * 1000000; + } else + return 0; +#else + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return 25000000; /* FPGA is limited to 25Mhz */ + + return MV_BOARD_DEFAULT_SYSCLK; +#endif +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displied in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val[MV_GPP_MAX_GROUP] = {0}; + MV_U32 mask[MV_GPP_MAX_GROUP] = {0}; + MV_U32 digitMask; + MV_U32 i, pinNum, gppGroup; + MV_U32 boardId = mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + hexNum &= (1 << BOARD_INFO(boardId)->activeLedsNumber) - 1; + + for (i = 0, digitMask = 1; i < BOARD_INFO(boardId)->activeLedsNumber; i++, digitMask <<= 1) { + if (hexNum & digitMask) { + pinNum = BOARD_INFO(boardId)->pLedGppPin[i]; + gppGroup = pinNum / 32; + val[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + mask[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + } + } + + for (gppGroup = 0; gppGroup < MV_GPP_MAX_GROUP; gppGroup++) { + mvGppValueSet(gppGroup, mask[gppGroup], + BOARD_INFO(boardId)->ledsPolarity == 0 ? val[gppGroup] : ~val[gppGroup]); + } +} + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* gppClass - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS gppClass, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == gppClass) { + if (indexFound == index) + return (MV_U32) BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + } + } + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) { + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(0), (1 << resetPin)); + MV_REG_BIT_RESET(GPP_DATA_OUT_EN_REG(0), (1 << resetPin)); + } else { + /* No gpp reset pin was found, try to reset ussing + ** system reset out */ + MV_REG_BIT_SET(CPU_RSTOUTN_MASK_REG, BIT2); + MV_REG_BIT_SET(CPU_SYS_SOFT_RST_REG, BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); +} + +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* type - Type of SDIO GPP to get. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type) +{ + if ((type != BOARD_GPP_SDIO_POWER) && (type != BOARD_GPP_SDIO_DETECT) && (type != BOARD_GPP_SDIO_WP)) + return MV_FAIL; + + return mvBoarGpioPinNumGet(type, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + } + + switch (gppGrp) { + case (0): + return BOARD_INFO(boardId)->intsGppMaskLow; + break; + case (1): + return BOARD_INFO(boardId)->intsGppMaskMid; + break; + case (2): + return BOARD_INFO(boardId)->intsGppMaskHigh; + break; + default: + return MV_ERROR; + } +} + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represents MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + MV_U32 mppMod; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + } + + mppMod = BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod; + if (mppMod >= BOARD_INFO(boardId)->numBoardMppConfigValue) + mppMod = 0; /* default */ + + return BOARD_INFO(boardId)->pBoardMppConfigValue[mppMod].mppGroup[mppGroupNum]; +} + +/******************************************************************************* +* mvBoardGppConfigGet +* +* DESCRIPTION: +* Get board configuration according to the input configuration GPP's. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The value of the board configuration GPP's. +* +*******************************************************************************/ +MV_U32 mvBoardGppConfigGet(void) +{ + MV_U32 boardId, i; + MV_U32 result = 0; + MV_U32 gpp; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGppConfigGet: Board unknown.\n"); + return 0; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_GPP_CONF) { + gpp = BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + result <<= 1; + result |= (mvGppValueGet(gpp >> 5, 1 << (gpp & 0x1F)) >> (gpp & 0x1F)); + } + } + return result; + +} + +/******************************************************************************* +* mvBoardTdmSpiModeGet - return SLIC/DAA connection +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardTdmSpiModeGet(MV_VOID) +{ + return DUAL_CHIP_SELECT_MODE; +} + +/******************************************************************************* +* mvBoardTdmDevicesCountGet +* +* DESCRIPTION: +* Return the number of TDM devices on board. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Number of devices. +* +*******************************************************************************/ +MV_U8 mvBoardTdmDevicesCountGet(void) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return 0; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + return BOARD_INFO(boardId)->numBoardTdmInfo[index]; +} + +/******************************************************************************* +* mvBoardTdmSpiCsGet +* +* DESCRIPTION: +* Return the SPI Chip-select number for a given device. +* +* INPUT: +* devId - The Slic device ID to get the SPI CS for. +* +* OUTPUT: +* None. +* +* RETURN: +* The SPI CS if found, -1 otherwise. +* +*******************************************************************************/ +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return -1; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + if (devId >= BOARD_INFO(boardId)->numBoardTdmInfo[index]) + return -1; + + return BOARD_INFO(boardId)->pBoardTdmInt2CsInfo[index][devId].spiCs; +} + +/******************************************************************************* +* mvBoardModuleTypePrint +* +* DESCRIPTION: +* Print on-board detected modules. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + mvOsOutput("Modules Detected:\n"); + + /* TDM */ + if (mvBoardTdmDevicesCountGet() > 0) + mvOsOutput(" TDM module.\n"); + + return; +} + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devNum; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + foundIndex++; + } + + return foundIndex; +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devIndex; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) { + if (foundIndex == devNum) + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/******************************************************************************* +* boardGetDevCSNum +* +* DESCRIPTION: +* Return the device's chip-select number. +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardTwsiAddrTypeGet - +* +* DESCRIPTION: +* Return the TWSI address type for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address type. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + } + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiAddrGet - +* +* DESCRIPTION: +* Return the TWSI address for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + } + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in bytes +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId = mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; + +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + if (gBoardId == -1) { + /* Use DB as default */ + gBoardId = DB_88F78XX0_BP_ID; + } + + return gBoardId; +} + +/******************************************************************************* +* mvBoardTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + + twsiSlave.validOffset = MV_TRUE; + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + + if (MV_OK != mvTwsiRead(0, &twsiSlave, &data, 1)) { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoardTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", + twsiSlave.slaveAddr.address, twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + if (MV_OK != mvTwsiWrite(0, &twsiSlave, ®Val, 1)) { + DB(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* SatR Configuration functions +*******************************************************************************/ +MV_U8 mvBoardFabFreqGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + return ((sar0 & 0x1E) >> 1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + sar0 &= ~(0xF << 1); + sar0 |= (freqVal & 0xF) << 1; + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardFabFreqModeGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(3, 0); + return (sar0 & 0x1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqModeSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(3, 0); + sar0 &= ~(0x1); + sar0 |= (freqVal & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqModeGet(MV_VOID) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + return (sar0 & 0x1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqModeSet(MV_U8 freqVal) +{ + MV_U8 sar0; + + sar0 = mvBoardTwsiSatRGet(2, 0); + sar0 &= ~(0x1); + sar0 |= (freqVal & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + return ((sar & 0x1C) >> 2); +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + sar &= ~(0x7 << 2); + sar |= (freqVal & 0x7) << 2; + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuFreq S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + return (sar & 0x7); +} + +/*******************************************************************************/ +MV_STATUS mvBoardBootDevSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + sar &= ~(0x7); + sar |= (val & 0x7); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB(mvOsPrintf("Board: Write BootDev S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDev S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevWidthGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + return (sar & 0x18) >> 3; +} + +/*******************************************************************************/ +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + sar &= ~(0x3 << 3); + sar |= ((val & 0x3) << 3); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB(mvOsPrintf("Board: Write BootDevWidth S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDevWidth S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardCpu0CoreModeGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + return (sar & 0x18) >> 3; +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpu0CoreModeSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + sar &= ~(0x3 << 3); + sar |= ((val & 0x3) << 3); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB(mvOsPrintf("Board: Write Cpu0CoreMode S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write Cpu0CoreMode S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardL2SizeGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + return (sar & 0x3); +} + +/*******************************************************************************/ +MV_STATUS mvBoardL2SizeSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + sar &= ~(0x3); + sar |= (val & 0x3); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB(mvOsPrintf("Board: Write L2Size S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write L2Size S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardCpuCoresNumGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(3, 0); + return (sar & 0x6) >> 1; +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val) +{ + MV_U8 sar, temp; + + sar = mvBoardTwsiSatRGet(3, 0); + sar &= ~(0x3 << 1); + sar |= ((val & 0x3) << 1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB(mvOsPrintf("Board: Write CpuCoreNum S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuCoreNum S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvBoardConfIdSet(MV_U16 conf) +{ + if (MV_OK != mvBoardTwsiSatRSet(0, 1, conf)) { + DB(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardConfIdGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 1); + return (sar & 0xFF); +} +/******************************************************************************* +* End of SatR Configuration functions +*******************************************************************************/ + +/******************************************************************************* +* mvBoardMppModulesScan +* +* DESCRIPTION: +* Scan for modules connected through MPP lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardMppModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if (boardId == DB_88F78XX0_BP_ID) { + twsiSlave.slaveAddr.address = MV_BOARD_MPP_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_MPP_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + switch (regVal) { + case MV_BOARD_LCD_DVI_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_LCD_DVI; + return MV_OK; + + case MV_BOARD_MII_GMII_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_MII_GMII; + return MV_OK; + + case MV_BOARD_TDM_MODULE_ID: + /* + TODO - how to distinguish between SLIC types? + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_3215; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_880; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_792; + return MV_OK; + */ + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_OTHER; + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_TDM_32CH; + return MV_OK; + + default: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_OTHER; + DB(mvOsPrintf("mvBoardMppModulesScan: Unsupported module!\n")); + break; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardOtherModulesScan +* +* DESCRIPTION: +* Scan for modules connected through SERDES/LVDS/... lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardOtherModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if (boardId == DB_88F78XX0_BP_ID) { + /* reset modules flags */ + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_NONE; + + /* SERDES module (only PEX moduel is supported now) */ + twsiSlave.slaveAddr.address = MV_BOARD_PEX_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_PEX_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_PEX_MODULE_ID) { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "PEX module DETECTED!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_PEX; + } else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ PEX module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + + /* LVDS (LCD) module */ + twsiSlave.slaveAddr.address = MV_BOARD_LVDS_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_LVDS_MODULE_ADDR_TYPE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_LVDS_MODULE_ID) + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_LVDS; + else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ LVDS module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPexModuleConnected +* +* DESCRIPTION: +* Check if PEX module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsPexModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + /* TODO - remove this after finishing debug */ + /*return MV_TRUE;*/ + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsPexModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_PEX) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLvdsModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLvdsModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsLvdsModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_LVDS) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLcdDviModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLcdDviModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) + DB(mvOsPrintf("mvBoardIsLcdDviModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod & MV_BOARD_LCD_DVI) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTwsiMuxChannelSet +* +* DESCRIPTION: +* Set the channel number of the on-board TWSI mux. +* +* INPUT: +* chNum - The channel number to set. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum) +{ + static MV_U8 currChNum = 0xFF; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if (currChNum == muxChNum) + return MV_OK; + + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_TWSI_MUX, 0); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_TWSI_MUX, 0); + twsiSlave.validOffset = 0; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + muxChNum += 4; + return mvTwsiWrite(0, &twsiSlave, &muxChNum, 1); +} + +/******************************************************************************* +* mvBoardTwsiReadByteThruMux +* +* DESCRIPTION: +* Read a single byte from a TWSI device through the TWSI Mux. +* +* INPUT: +* muxChNum - The Twsi Mux channel number to read through. +* chNum - The TWSI channel number. +* pTwsiSlave - The TWSI slave address. +* data - Buffer to read into (1 byte). +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data) +{ + MV_STATUS res; + + /* Set Mux channel */ + res = mvBoardTwsiMuxChannelSet(muxChNum); + if (res == MV_OK) + res = mvTwsiRead(chNum, pTwsiSlave, data, 1); + + return res; +} + +/******************************************************************************* +* mvBoardMppGet - Get board SERDES configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* SERDES configuration structure or NULL on error +* +*******************************************************************************/ +MV_SERDES_CFG *mvBoardSerdesCfgGet(void) +{ + MV_U32 boardId; + MV_U32 serdesCfg = 0; /* default */ + + boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) { + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return NULL; + } + + if (mvBoardIsPexModuleConnected()) + serdesCfg = 1; + + return &BOARD_INFO(boardId)->pBoardSerdesConfigValue[serdesCfg]; +} + + +/******************************************************************************* +* mvBoardPexInfoGet - Get board PEX Info +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +*******************************************************************************/ +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (boardId != DB_88F78XX0_BP_ID) { + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return NULL; + } + + return &BOARD_INFO(boardId)->boardPexInfo; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvLib.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,401 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + +/* +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +*/ +#define MV_BOARD_MAX_USB_IF 3 +#define MV_BOARD_MAX_MPP 9 /* number of MPP conf registers */ +#define MV_BOARD_NAME_LEN 0x20 + +/* EPPROM Modules detection information */ + +#define MV_BOARD_EEPROM_MODULE_ADDR 0x50 +#define MV_BOARD_EEPROM_MODULE_ADDR_TYPE ADDR7_BIT + +#define MV_BOARD_PEX_MODULE_ADDR 0x23 +#define MV_BOARD_PEX_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_PEX_MODULE_ID 0 + +#define MV_BOARD_LVDS_MODULE_ADDR 0x41 +#define MV_BOARD_LVDS_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LVDS_MODULE_ID 0 + +#define MV_BOARD_MPP_MODULE_ADDR 0x40 +#define MV_BOARD_MPP_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LCD_DVI_MODULE_ID 0 +#define MV_BOARD_TDM_MODULE_ID 1 +#define MV_BOARD_MII_GMII_MODULE_ID 4 + +typedef enum { + BOARD_EPON_CONFIG, + BOARD_GPON_CONFIG, + BOARD_PON_NONE, + BOARD_PON_AUTO +} MV_BOARD_PON_CONFIG; + +typedef struct _boardData { + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; +} BOARD_DATA; + +typedef enum _devBoardMppGroupClass { + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MPP_GROUP_3, + MV_BOARD_MAX_MPP_GROUP +} MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass { + MV_BOARD_AUTO = 0, + MV_BOARD_TDM_32CH, + MV_BOARD_LCD_DVI, + MV_BOARD_MII_GMII, + MV_BOARD_OTHER +} MV_BOARD_MPP_TYPE_CLASS; + +typedef enum _devBoardOtherTypeClass { + MV_BOARD_NONE = 0x00000000, + MV_BOARD_LVDS = 0x00000001, + MV_BOARD_PEX = 0x00000002, + MV_BOARD_UNKNOWN = 0x80000000 +} MV_BOARD_OTHER_TYPE_CLASS; + +#define MV_BOARD_TDM MV_BOARD_TDM_32CH + +typedef struct _boardModuleTypeInfo { + MV_BOARD_MPP_TYPE_CLASS boardMppMod; + MV_BOARD_OTHER_TYPE_CLASS boardOtherMod; +} MV_BOARD_MODULE_TYPE_INFO; + +typedef enum _devBoardClass { + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER, +} MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass { + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_MUX, + BOARD_TWSI_OTHER +} MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass { + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_CONF, + BOARD_GPP_OTHER +} MV_BOARD_GPP_CLASS; + +typedef struct _devCsInfo { + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; +} MV_DEV_CS_INFO; + +typedef struct _boardLedInfo { + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8 *gppPinNum; /* Pointer to GPP values */ +} MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo { + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; +} MV_BOARD_GPP_INFO; + +typedef struct _boardTwsiInfo { + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; +} MV_BOARD_TWSI_INFO; + +typedef enum _boardMacSpeed { + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, +} MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo { + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; +} MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo { + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; +} MV_BOARD_MPP_INFO; + +typedef struct { + MV_U8 spiCs; +} MV_BOARD_TDM_INFO; + +typedef struct _boardPexUnitCfg { + MV_PEX_UNIT_CFG pexCfg; + MV_U8 pexLaneStat[4]; /* 1: enabled, 2: disabled */ +} MV_BOARD_PEX_UNIT_CFG; + +typedef struct _boardPexInfo { + MV_PEXIF_INDX pexMapping[MV_PEX_MAX_IF]; + MV_BOARD_PEX_UNIT_CFG pexUnitCfg[MV_PEX_MAX_UNIT]; + MV_U32 boardPexIfNum; +} MV_BOARD_PEX_INFO; + +typedef enum { + BOARD_TDM_SLIC_880 = 0, + BOARD_TDM_SLIC_792, + BOARD_TDM_SLIC_3215, + BOARD_TDM_SLIC_OTHER, + BOARD_TDM_SLIC_COUNT +} MV_BOARD_TDM_SLIC_TYPE; + +typedef struct _boardInfo { + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MODULE_TYPE_INFO *pBoardModTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO *pBoardMppConfigValue; + MV_U8 numBoardSerdesConfigValue; + MV_SERDES_CFG *pBoardSerdesConfigValue; + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskMid; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO *pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO *pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO *pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO *pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8 *pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValMid; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValMid; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValMid; + MV_U32 gppPolarityValHigh; + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + MV_U8 numBoardTdmInfo[BOARD_TDM_SLIC_COUNT]; + MV_BOARD_TDM_INFO *pBoardTdmInt2CsInfo[BOARD_TDM_SLIC_COUNT]; + MV_16 boardTdmInfoIndex; + + /* NAND init params */ + MV_U32 nandFlashReadParams; + MV_U32 nandFlashWriteParams; + MV_U32 nandFlashControl; + MV_BOARD_PEX_INFO boardPexInfo; /* filled in runtime */ + +} MV_BOARD_INFO; + +/* For backward compatability with Legacy mode */ +#define mvBoardSwitchConnectedPortGet(port) (-1) +#define mvBoardIsSwitchConnected(port) (mvBoardSwitchConnectedPortGet(port) != -1) +/*#define mvBoardLinkStatusIrqGet(port) mvBoardSwitchIrqGet()*/ + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); + +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); +MV_VOID mvBoardReset(MV_VOID); +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type); +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId); +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); +MV_U32 mvBoardGppConfigGet(void); +MV_32 mvBoardTdmSpiModeGet(MV_VOID); +MV_U8 mvBoardTdmDevicesCountGet(void); +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId); +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_32 mvBoardNandWidthGet(void); +MV_U32 mvBoardIdGet(MV_VOID); + +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_U8 mvBoardFabFreqGet(MV_VOID); +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqGet(MV_VOID); +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqModeGet(MV_VOID); +MV_STATUS mvBoardCpuFreqModeSet(MV_U8 freqVal); +MV_U8 mvBoardFabFreqModeGet(MV_VOID); +MV_STATUS mvBoardFabFreqModeSet(MV_U8 freqVal); +MV_U8 mvBoardBootDevGet(MV_VOID); +MV_STATUS mvBoardBootDevSet(MV_U8 val); +MV_U8 mvBoardBootDevWidthGet(MV_VOID); +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val); +MV_U8 mvBoardCpu0CoreModeGet(MV_VOID); +MV_STATUS mvBoardCpu0CoreModeSet(MV_U8 val); +MV_U8 mvBoardL2SizeGet(MV_VOID); +MV_STATUS mvBoardL2SizeSet(MV_U8 val); +MV_U8 mvBoardCpuCoresNumGet(MV_VOID); +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val); +MV_STATUS mvBoardConIdSet(MV_U16 conf); +MV_U16 mvBoardConfIdGet(MV_VOID); + + +MV_STATUS mvBoardMppModulesScan(void); +MV_STATUS mvBoardOtherModulesScan(void); +MV_BOOL mvBoardIsPexModuleConnected(void); +MV_BOOL mvBoardIsLvdsModuleConnected(void); +MV_BOOL mvBoardIsLcdDviModuleConnected(void); +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum); +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_SERDES_CFG *mvBoardSerdesCfgGet(void); +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void); + +#endif /* __INCmvBoardEnvLibh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,404 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPexRegs.h" +/**********************/ +/* ARMADA-XP DB BOARD */ +/**********************/ + +#define DB_88F78XX0_BOARD_TWSI_DEF_NUM 0x5 +#define DB_88F78XX0_BOARD_SWITCH_NUM 0x1 +#define DB_88F78XX0_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F78XX0_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F78XX0_BOARD_MPP_CONFIG_NUM 0x5 +#define DB_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define DB_88F78XX0_BOARD_SERDES_CONFIG_NUM 0x2 + +#if defined(MV_NAND) && defined(MV_SPI) +#define DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x2 +#else +#define DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif + +#define DB_88F78XX0_BOARD_DEBUG_LED_NUM 0x3 + +#define DB_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +MV_U8 mvDbDisableModuleDetection = 0; + +MV_U8 db88f6781InfoBoardDebugLedIf[] = + {26, 27, 48}; + +MV_BOARD_TWSI_INFO db88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO db88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0}, + {BOARD_MAC_SPEED_AUTO, 0x1}, + {BOARD_MAC_SPEED_AUTO, 0x19}, + {BOARD_MAC_SPEED_AUTO, 0x1B} +}; + +MV_BOARD_MODULE_TYPE_INFO db88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO db88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) /* TODO - which CS if any? */ +/* {NFLASH_CS, N_A, BOARD_DEV_NAND_FLASH, 8} */ /* NAND DEV */ +#endif +#if defined(MV_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f78XX0InfoBoardMppConfigValue[] = { + { { + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_TDM_32CH */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + (DB_88F78XX0_MPP24_31 & 0x00000000) | 0x33333333, + (DB_88F78XX0_MPP32_39 & 0xFFFF0000) | 0x00003333, + (DB_88F78XX0_MPP40_47 & 0xFFFFF0FF) | 0x00000300, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_LCD_DVI */ + (DB_88F78XX0_MPP0_7 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP8_15 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP16_23 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP24_31 & 0xFFFF0000) | 0x00004444, + DB_88F78XX0_MPP32_39, + (DB_88F78XX0_MPP40_47 & 0xFFFFFF00) | 0x00000044, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_MII_GMII */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_OTHER */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, +}; + +MV_SERDES_CFG db88f78XX0InfoBoardSerdesConfigValue[] = { +/* {0x32221111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 0x00000030}, */ /* Default */ + {0x32221111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 0x00000030}, /* Default */ +/* {0x11111111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, 0x00000030} */ /* PEX module */ + {0x31211111, 0x11111111, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, 0x00000030} /* PEX module */ +}; + +MV_BOARD_TDM_INFO db88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO db88f78XX0Info = { + .boardName = "DB-78460-BP", + .numBoardMppTypeValue = DB_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM, + .pBoardModTypeValue = db88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = DB_88F78XX0_BOARD_MPP_CONFIG_NUM, + .pBoardMppConfigValue = db88f78XX0InfoBoardMppConfigValue, + .numBoardSerdesConfigValue = DB_88F78XX0_BOARD_SERDES_CONFIG_NUM, + .pBoardSerdesConfigValue = db88f78XX0InfoBoardSerdesConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = DB_88F78XX0_BOARD_DEVICE_CONFIG_NUM, + .pDevCsInfo = db88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = DB_88F78XX0_BOARD_TWSI_DEF_NUM, + .pBoardTwsiDev = db88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = DB_88F78XX0_BOARD_MAC_INFO_NUM, + .pBoardMacInfo = db88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = DB_88F78XX0_BOARD_GPP_INFO_NUM, + .pBoardGppInfo = db88f78XX0InfoBoardGppInfo, + .activeLedsNumber = DB_88F78XX0_BOARD_DEBUG_LED_NUM, + .pLedGppPin = db88f6781InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = DB_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = DB_88F78XX0_GPP_POL_HIGH, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = { 2, 6, 1 }, + .pBoardTdmInt2CsInfo = { db88f78XX0Tdm880, + db88f78XX0Tdm792, + db88f78XX0Tdm3215 + }, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_88F78XX0_BOARD_NAND_CONTROL +}; + +/************************/ +/* ARMADA-XP FPGA BOARD */ +/************************/ + +#define FPGA_88F78XX0_BOARD_TWSI_DEF_NUM 0x5 +#define FPGA_88F78XX0_BOARD_SWITCH_NUM 0x1 +#define FPGA_88F78XX0_BOARD_MAC_INFO_NUM 0x2 +#define FPGA_88F78XX0_BOARD_GPP_INFO_NUM 0x3 +#define FPGA_88F78XX0_BOARD_MPP_CONFIG_NUM 0x1 +#define FPGA_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define FPGA_88F78XX0_BOARD_SERDES_CONFIG_NUM 0x2 + +#if defined(MV_NAND) && defined(MV_SPI) +#define FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x2 +#else +#define FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif + +#define FPGA_88F78XX0_BOARD_DEBUG_LED_NUM 0x0 + +#define FPGA_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define FPGA_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +MV_BOARD_TWSI_INFO fpga88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO fpga88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1}, + {BOARD_MAC_SPEED_AUTO, 0x2}, + {BOARD_MAC_SPEED_AUTO, 0x3}, + {BOARD_MAC_SPEED_AUTO, 0x4} +}; + +MV_BOARD_MODULE_TYPE_INFO fpga88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO fpga88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO fpga88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) /* TODO - which CS if any? */ +/* {NFLASH_CS, N_A, BOARD_DEV_NAND_FLASH, 8} */ /* NAND DEV */ +#endif +#if defined(MV_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO fpga88f78XX0InfoBoardMppConfigValue[] = { + { { + FPGA_88F78XX0_MPP0_7, + FPGA_88F78XX0_MPP8_15, + FPGA_88F78XX0_MPP16_23, + FPGA_88F78XX0_MPP24_31, + FPGA_88F78XX0_MPP32_39, + FPGA_88F78XX0_MPP40_47, + FPGA_88F78XX0_MPP48_55, + FPGA_88F78XX0_MPP56_63, + FPGA_88F78XX0_MPP64_67, + } } +}; + +MV_SERDES_CFG fpga88f78XX0InfoBoardSerdesConfigValue[] = { + {0x00000000, 0x00000000, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, 0x00000000} /* No PEX in FPGA */ +}; + +MV_BOARD_TDM_INFO fpga88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO fpga88f78XX0Info = { + .boardName = "FPGA-88F78XX0", + .numBoardMppTypeValue = FPGA_88F78XX0_BOARD_MPP_GROUP_TYPE_NUM, + .pBoardModTypeValue = fpga88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = FPGA_88F78XX0_BOARD_MPP_CONFIG_NUM, + .pBoardMppConfigValue = fpga88f78XX0InfoBoardMppConfigValue, + .numBoardSerdesConfigValue = FPGA_88F78XX0_BOARD_SERDES_CONFIG_NUM, + .pBoardSerdesConfigValue = fpga88f78XX0InfoBoardSerdesConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = FPGA_88F78XX0_BOARD_DEVICE_CONFIG_NUM, + .pDevCsInfo = fpga88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = FPGA_88F78XX0_BOARD_TWSI_DEF_NUM, + .pBoardTwsiDev = fpga88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = FPGA_88F78XX0_BOARD_MAC_INFO_NUM, + .pBoardMacInfo = fpga88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = FPGA_88F78XX0_BOARD_GPP_INFO_NUM, + .pBoardGppInfo = fpga88f78XX0InfoBoardGppInfo, + .activeLedsNumber = FPGA_88F78XX0_BOARD_DEBUG_LED_NUM, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = FPGA_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = FPGA_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = FPGA_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = FPGA_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = FPGA_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = FPGA_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = FPGA_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = FPGA_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = FPGA_88F78XX0_GPP_POL_HIGH, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = { 2, 6, 1 }, + .pBoardTdmInt2CsInfo = { fpga88f78XX0Tdm880, + fpga88f78XX0Tdm792, + fpga88f78XX0Tdm3215 + }, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = FPGA_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = FPGA_88F78XX0_BOARD_NAND_CONTROL +}; + +MV_BOARD_INFO *boardInfoTbl[] = { + &db88f78XX0Info, + &fpga88f78XX0Info +}; diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/boardEnv/mvBoardEnvSpec.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +/* I2C bus addresses TODO - take from board design */ +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x57 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + + +/* Board specific configuration */ +/* ============================ */ + +/* boards ID numbers */ +#define BOARD_ID_BASE 0 + +/* New board ID numbers */ +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define FPGA_88F78XX0_ID (DB_88F78XX0_BP_ID + 1) +#define MV_MAX_BOARD_ID (FPGA_88F78XX0_ID + 1) + +/******************/ +/* DB-88F78XX0-BP */ +/******************/ +#define DB_88F78XX0_MPP0_7 0x11111111 +#define DB_88F78XX0_MPP8_15 0x22221111 +#define DB_88F78XX0_MPP16_23 0x22222222 +/* TODO Kostap - change MPP29 (CPU0 Vdd) back to default value 5 + when PM configuration changed to have it as active "high" + Otherwise setting it to default value will shut down CPU0 */ +/*#define DB_88F78XX0_MPP24_31 0x11540000 */ +#define DB_88F78XX0_MPP24_31 0x11040000 +#define DB_88F78XX0_MPP32_39 0x11111111 +#define DB_88F78XX0_MPP40_47 0x34221130 /* TODO set to 0x34221133 to enable PM for CPU1 */ +#define DB_88F78XX0_MPP48_55 0x11111110 +#define DB_88F78XX0_MPP56_63 0x11111101 /* TODO set to 0x11111111 to enable PM for CPU2/3 */ +#define DB_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define DB_88F78XX0_GPP_OUT_ENA_LOW ~(BIT26 | BIT27) +#define DB_88F78XX0_GPP_OUT_ENA_MID ~(BIT16) +#define DB_88F78XX0_GPP_OUT_ENA_HIGH ~(0x0) + +#define DB_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define DB_88F78XX0_GPP_OUT_VAL_MID 0x0 +#define DB_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F78XX0_GPP_POL_LOW 0x0 +#define DB_88F78XX0_GPP_POL_MID 0x0 +#define DB_88F78XX0_GPP_POL_HIGH 0x0 + +/********************/ +/* FPGA-88F78XX0-BP */ +/********************/ +#define FPGA_88F78XX0_MPP0_7 0x11111111 +#define FPGA_88F78XX0_MPP8_15 0x22221111 +#define FPGA_88F78XX0_MPP16_23 0x22222222 +#define FPGA_88F78XX0_MPP24_31 0x11500000 +#define FPGA_88F78XX0_MPP32_39 0x11111111 +#define FPGA_88F78XX0_MPP40_47 0x44221133 +#define FPGA_88F78XX0_MPP48_55 0x11111111 +#define FPGA_88F78XX0_MPP56_63 0x11111111 +#define FPGA_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define FPGA_88F78XX0_GPP_OUT_ENA_LOW (BIT26 | BIT27) +#define FPGA_88F78XX0_GPP_OUT_ENA_MID (BIT16) +#define FPGA_88F78XX0_GPP_OUT_ENA_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_MID 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_POL_LOW 0x0 +#define FPGA_88F78XX0_GPP_POL_MID 0x0 +#define FPGA_88F78XX0_GPP_POL_HIGH 0x0 + +#endif /* __INCmvBoardEnvSpech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.c 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,320 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in MHertz. +* +*******************************************************************************/ +MV_U32 mvCpuPclkGet(MV_VOID) +{ +#if defined(PCLCK_AUTO_DETECT) + MV_U32 idx; + MV_U32 cpuClk[] = MV_CPU_CLK_TBL; + + idx = MSAR_CPU_CLK_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)), MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + return cpuClk[idx] * 1000000; +#else + return MV_DEFAULT_PCLK; +#endif +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ +#ifdef L2CLK_AUTO_DETECT + MV_U32 idx; + MV_U32 freqMhz, l2FreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { + freqMhz = mvCpuPclkGet() / 1000000; /* CPU freq */ + freqMhz *= clockRatioTbl[idx].vco2cpu; /* VCO freq */ + l2FreqMhz = freqMhz / clockRatioTbl[idx].vco2l2c; + /* round up to integer MHz */ + if (((freqMhz % clockRatioTbl[idx].vco2l2c) * 10 / clockRatioTbl[idx].vco2l2c) >= 5) + l2FreqMhz++; + + return l2FreqMhz * 1000000; + } else + return (MV_U32)-1; +#else + return MV_BOARD_DEFAULT_L2CLK; +#endif +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch (cpuModel) { + case CPU_PART_MRVLPJ4B_V6UP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v6 UP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V7UP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v7 UP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V6MP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v6 MP", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_V7MP: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v7 MP", mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff, "??? (0x%04x) (Rev %d)", cpuModel, mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_ECC_MASK) == CL2ACR_ECC_EN) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2ParityMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PARITY_MASK) == CL2ACR_PARITY_EN) + mvOsSPrintf(buf, "L2 Parity Enabled"); + else + mvOsSPrintf(buf, "L2 Parity Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CTRL_REG); + if (regVal & CL2CR_L2_EN_MASK) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PFU_MASK) == CL2ACR_PFU_DIS) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_FORCE_WA_MASK) == CL2ACR_FORCE_NO_WA) + mvOsSPrintf(buf, "L2 Write Allocate Disabled"); + else + mvOsSPrintf(buf, "L2 Write Allocate Enabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register0 */ + mvOsPrintf("Extra Features Reg[0] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 1, %0, c15, c1, 1" : "=r" (regVal)); /* Read Marvell extra features register1 */ + mvOsPrintf("Extra Features Reg[1] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read Main ID register */ + mvOsPrintf("Main ID Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_CTRL_REG); + mvOsPrintf("L2 Control Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + mvOsPrintf("L2 Auxilary Control Reg = 0x%x\n", regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + MV_8 L2_Parity_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2ParityMode(L2_Parity_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Parity_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + +/******************************************************************************* +* whoAmI - Get the CPU ID +* +* DESCRIPTION: +* This function returns CPU ID in multiprocessor system +* +* INPUT: +* None. +* +* OUTPUT: +* none. +* +* RETURN: +* CPU ID. +*******************************************************************************/ +unsigned int whoAmI(void) +{ + MV_U32 value; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5 @ read CPUID reg\n" : "=r"(value) : : "memory"); + return (value & 0x7); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/cpu/mvCpu.h 2011-04-04 13:57:34.895595444 -0400 @@ -0,0 +1,130 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#ifndef MV_ASMLANGUAGE +#include "mvOs.h" +#endif +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#define MASTER_CPU 0 +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#if 0 +/* TODO: alior, need to be removed after moving to MRVL ID */ +#define CPU_PART_ARM1176 0xB76 +#define CPU_PART_MRVLPJ4MP 0xB02 +#define CPU_PART_MRVL_A8 0xC08 +#endif +#define CPU_PART_MRVL_A9 0xC09 +#define CPU_PART_MRVL571 0x571 +#define CPU_PART_MRVL521 0x521 + + +#define CPU_PART_MRVLPJ4B_V6UP 0xb76 +#define CPU_PART_MRVLPJ4B_V7UP 0xc08 +#define CPU_PART_MRVLPJ4B_V6MP 0xb02 +/* TODO: alior, need to update the v7MP id */ +#define CPU_PART_MRVLPJ4B_V7MP 0xaaa + +#if 0 +#define CPU_PART_ARM_V6UP 0xb76 +#define CPU_PART_ARM_V7UP 0xc08 +#define CPU_PART_ARM_V6MP 0xb02 + +#define CPU_PART_MRVLPJ4B_V6UP 0x581 +#define CPU_PART_MRVLPJ4B_V7UP 0xc00 +#define CPU_PART_MRVLPJ4B_V6MP 0x584 +/* TODO: alior, need to update the v7MP id */ +#define CPU_PART_MRVLPJ4B_V7MP 0xaaa +#endif + +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClkRatio { + MV_U32 vco2cpu; /* VCO:PCLK0(CPU) clock ratio */ + MV_U32 vco2l2c; /* VCO:NB(L2 cache) clock ratio */ + MV_U32 vco2hcl; /* VCO:HCLK(DDR controller) clock ratio */ + MV_U32 vco2ddr; /* VCO:DDR(DDR memory) clock ratio */ + +} MV_CPU_ARM_CLK_RATIO; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCpuh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,271 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "sys/mvCpuIf.h" + +#undef MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET sampleAtResetTargetArray[]; + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlTargetByWinInfoGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == unitWinInfo->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlAddrWinMapBuild +* +* DESCRIPTION: +* Build the windows address decoding table, to be used for initializing +* the unit's address decoding windows. +* +* INPUT: +* pAddrWinMap: An array to hold the address decoding windows parameters. +* len: Number of entries in pAddrWinMap. +* +* OUTPUT: +* pAddrWinMap: Address window information. +* +* RETURN: +* MV_BAD_PARAM: input array is smaller than needed to store all window +* addresses. +* MV_ERROR: Otherwise. +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + /* Check size of CPU address win table */ + if (len <= MAX_TARGETS) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - Table size too small.\n"); + return MV_BAD_PARAM; + } + + /* Fill in the pAddrWinMap fields */ + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) { + if (status == MV_NO_SUCH) { + pAddrWinMap[i].enable = MV_FALSE; + continue; + } else { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCpuIfTargetWinGet() failed.\n"); + return MV_ERROR; + } + } + + pAddrWinMap[i].addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinMap[i].addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinMap[i].addrWin.size = cpuAddrDecWin.addrWin.size; + pAddrWinMap[i].enable = cpuAddrDecWin.enable; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinMap[i].attrib = targetAttrib.attrib; + pAddrWinMap[i].targetId = targetAttrib.targetId; + } + pAddrWinMap[i].addrWin.baseLow = TBL_TERM; + pAddrWinMap[i].addrWin.baseHigh = TBL_TERM; + pAddrWinMap[i].addrWin.size = TBL_TERM; + pAddrWinMap[i].enable = TBL_TERM; + pAddrWinMap[i].attrib = TBL_TERM; + pAddrWinMap[i].targetId = TBL_TERM; + + return MV_OK; +} + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) + continue; + + if ((physAddr >= cpuAddrDecWin.addrWin.baseLow) && + (physAddr < cpuAddrDecWin.addrWin.baseLow + cpuAddrDecWin.addrWin.size)) { + /* Found */ + pAddrWinInfo->addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinInfo->addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinInfo->addrWin.size = cpuAddrDecWin.addrWin.size; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinInfo->attrib = targetAttrib.attrib; + pAddrWinInfo->targetId = targetAttrib.targetId; + return MV_OK; + } + } + /* not found */ + return MV_NOT_FOUND; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,183 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvTargetAttrib { + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ +} MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin { + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +} MV_DEC_WIN; + +typedef struct _mvDecWinParams { + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +} MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo); + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, MV_DEC_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len); + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr); + +#endif /* __INCmvCtrlEnvAddrDech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +#endif /* __INCmvCtrlEnvAsmh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,2218 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "gpp/mvGpp.h" +#include "mvSysEthConfig.h" + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) +#include "eth/mvEth.h" +#else +#include "neta/gbe/mvNeta.h" +#endif /* MV_ETH_LEGACY or MV_ETH_NETA */ +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "sata/CoreDriver/mvSata.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#if defined(MV_INCLUDE_TDM) +#include "mvSysTdmConfig.h" +#endif + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif +MV_U32 dummyFlavour = 0; +MV_BIOS_MODE bios_modes[BIOS_MODES_NUM] = { +/* DB Conf Conf ID Plat Code L2 size CPU Freq CpuFreqMode Fabric Freq FabricFreqMode CPU1/2/3 Enable CPU Mode v7UP/v6MP */ +/* 0x4d/[1:0] 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] 0x4f/[2:1] 0x4f/[4:3] */ + {"78130", 0x10, 0x7813, 0x1, 0x3, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"6710", 0x11, 0x6710, 0x0, 0x2, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"78160", 0x12, 0x7816, 0x1, 0x3, 0x0, 0x5, 0x0, 0x0, 0x1}, + {"78230", 0x13, 0x7823, 0x1, 0x3, 0x0, 0x5, 0x0, 0x2, 0x2}, + {"78260", 0x14, 0x7826, 0x1, 0x3, 0x0, 0x5, 0x0, 0x2, 0x2}, + {"78460", 0x15, 0x7846, 0x3, 0x3, 0x0, 0x5, 0x0, 0x3, 0x2}, + {"78480", 0x16, 0x7846, 0x3, 0x5, 0x0, 0x5, 0x0, 0x3, 0x2} +}; + +#if 0 +table below before moving all flavour to 1333/667 mode only +MV_BIOS_MODE bios_modes[BIOS_MODES_NUM] = { +/* DB Conf Code L2 size CPU Freq Fabric Freq CPU1/2/3 Enable CPU Mode v6UP/v6MP + 0x4d/[1:0] 0x4d/[4:2] 0x4e/[4:1] 0x4f/[2:1] 4f/[4:3]*/ + {"78130", 0x7813, 0x1, 0x1, 0x1, 0x0, 0x0}, + {"KW40", 0x6710, 0x1, 0x1, 0x1, 0x0, 0x0}, + {"78160", 0x7816, 0x1, 0x3, 0x5, 0x0, 0x0}, + {"78230", 0x7823, 0x1, 0x1, 0x1, 0x2, 0x2}, + {"78260", 0x7826, 0x1, 0x3, 0x5, 0x2, 0x2}, + {"78460", 0x7846, 0x3, 0x3, 0x5, 0x3, 0x2}, + {"78480", 0x7846, 0x3, 0x5, 0x5, 0x3, 0x2} +}; +#endif +MV_U32 mvCtrlGetCpuNum(MV_VOID) +{ + return ((MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET); +} +MV_BOOL mvCtrlIsValidSatR(MV_VOID) +{ + int i=0; + MV_U32 tmpSocCores; + MV_U8 cpuEna; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 fabricFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreqMode; + + MV_U32 confId = mvBoardConfIdGet(); + + l2size = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_L2_SIZE_MASK) >> SAR0_L2_SIZE_OFFSET; + cpuFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_CPU_FREQ_MASK) >> SAR0_CPU_FREQ_OFFSET; + fabricFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET; + tmpSocCores = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET; + cpuFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_MODE_MASK) >> SAR1_CPU_MODE_OFFSET; + fabricFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_FABRIC_MODE_MASK) >> SAR1_FABRIC_MODE_OFFSET; + /* Bug fix in HW, bit0 & bit1 are swapped */ + cpuEna |= (tmpSocCores & 0x2) >> 1; + cpuEna |= (tmpSocCores & 0x1) << 1; + + /* Find out what is programmed in SAR and change device ID accordingly */ + for (i = 0; i < BIOS_MODES_NUM; i++) { + if (bios_modes[i].confId == confId) { + DB(mvOsPrintf("confId = 0x%x\n", confId)); + DB(mvOsPrintf("cpuFreq [0x%x] = 0x%x\n", cpuFreq, bios_modes[i].cpuFreq)); + DB(mvOsPrintf("fabricFreq [0x%x] = 0x%x\n", fabricFreq, bios_modes[i].fabricFreq)); + DB(mvOsPrintf("cpuEna [0x%x] = 0x%x\n", cpuEna, bios_modes[i].cpuEna)); + DB(mvOsPrintf("cpuFreqMode [0x%x] = 0x%x\n", cpuFreqMode, bios_modes[i].cpuFreqMode)); + DB(mvOsPrintf("fabricFreqMode [0x%x] = 0x%x\n", fabricFreqMode, bios_modes[i].fabricFreqMode)); + DB(mvOsPrintf("l2size [0x%x] = 0x%x\n", l2size, bios_modes[i].l2size)); + if ((cpuFreq == bios_modes[i].cpuFreq) && + (fabricFreq == bios_modes[i].fabricFreq) && + (cpuEna == bios_modes[i].cpuEna) && + (cpuFreqMode == bios_modes[i].cpuFreqMode) && + (fabricFreqMode == bios_modes[i].fabricFreqMode) && + (l2size == bios_modes[i].l2size)) { + return MV_TRUE; + } else { + return MV_FALSE; + } + } + } +} +MV_STATUS mvCtrlUpdatePexId(MV_VOID) +{ + //MV_U32 socFreq, tmpSocCores; + //MV_U32 socCores = 0; + MV_U32 pmCtrl; + MV_U32 devVendId; + int i; + MV_U16 confId; + + /* if PEX0 clock is disabled - enable it for reading the device ID */ + pmCtrl = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((pmCtrl & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + MV_REG_WRITE(POWER_MNG_CTRL_REG, + (pmCtrl & ~PMC_PEXSTOPCLOCK_MASK(0))| PMC_PEXSTOPCLOCK_EN(0)); + } + + devVendId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + //socFreq = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_DDR3_FREQ_MASK; + //tmpSocCores = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET; + confId = mvBoardConfIdGet(); + + /* Bug fix in HW, bit0 & bit1 are swapped */ +/* socCores |= (tmpSocCores & 0x2) >> 1; + socCores |= (tmpSocCores & 0x1) << 1; +*/ + /* Find out what is programmed in SAR and change device ID accordingly */ +/* if ((socFreq == SAR_CPU_FAB_GET(bios_modes[i].cpuFreq, bios_modes[i].fabricFreq)) && + (socCores == bios_modes[i].cpuEna)) { +*/ + for (i = 0; i < BIOS_MODES_NUM; i++) { + if (bios_modes[i].confId == confId) { + devVendId &= 0x0000FFFF; + devVendId |= bios_modes[i].code << 16; + MV_REG_WRITE(MV_PEX_IF_REGS_OFFSET(0), devVendId); + } + } + + /* Reset the original value of PEX0 clock */ + if ((pmCtrl & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) + MV_REG_WRITE(POWER_MNG_CTRL_REG, pmCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 mppVal; + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + MV_U32 pexUnit = 0; + + /* Disable MBus Error Propagation */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); + + /* Use Background sync barrier (polling) for I/O cache coherency */ + MV_REG_BIT_SET(SOC_CIB_CTRL_CFG_REG, BIT8); + + /* MPP Init - scan which modeule is connected */ + /* mvBoardMppModulesScan(); */ + + /* Read MPP config values from board level and write MPP options to HW */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) { + mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */ + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Scan for other modules (SERDES/LVDS/...) */ + mvBoardOtherModulesScan(); + + /* Update interfaces configuration based on above scan */ + if (MV_OK != mvCtrlSerdesPhyConfig()) + mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n"); + + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + /* PEX enabling */ + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg != PEX_BUS_DISABLED) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); + else + MV_REG_BIT_RESET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); + } + + mvOsDelay(100); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + if (mppGroup >= MV_MPP_MAX_GROUP) + mppGroup = 0; + + ret = MPP_CONTROL_REG(mppGroup); + + return ret; +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; +/* TODO: alior fix PexMaxIfGet for KW40... */ + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_IF; + + default: + return 0; + } +} +/******************************************************************************* +* mvCtrlPexMaxUnitGet - Get Marvell controller number of PEX units. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 2; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 3; + + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_UNIT; + + default: + return 0; + } +} + +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) + { + case MV_FPGA_DEV_ID: + return 1; + + default: + return 0; + } +} +#endif + +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); +#if 0 + /* FIXME - assuming MV_78460_DEV_ID */ + devId = MV_78460_DEV_ID; +#endif + switch (devId) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return MV_78130_ETH_MAX_PORT; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_78460_ETH_MAX_PORT; + + default: + return 0; + } +} + +/******************************************************************************* +* mvCtrlEthMaxCPUsGet - Get Marvell controller number of CPUs. +* +* DESCRIPTION: +* This function returns Marvell controller number of CPUs. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of CPUs. +* +*******************************************************************************/ +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + /* FIXME - assuming MV_78460_DEV_ID */ + devId = MV_78460_DEV_ID; + + switch (devId) { + case MV_78130_DEV_ID: + case MV_78230_DEV_ID: + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + return 4; + + default: + return 0; + } +} + + +#if defined(MV_INCLUDE_SATA) +/******************************************************************************* +* mvCtrlSataMaxPortGet - Get Marvell controller number of Sata ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of Sata ports. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of Sata ports. +* +*******************************************************************************/ +MV_U32 mvCtrlSataMaxPortGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_SATA_MAX_CHAN; + break; + } + return res; +} +#endif + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_CHAN; + break; + } + return res; +} + +/******************************************************************************* +* mvCtrlXorMaxUnitGet - Get Marvell controller number of XOR units. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR units. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_UNIT; + break; + } + return res; +} + +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_FPGA_DEV_ID: + res = 0; + break; + + default: + res = ARMADA_XP_MAX_USB_PORTS; + break; + } + + return res; +} +#endif + +#if defined(MV_INCLUDE_LEGACY_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + return ARMADA_XP_NAND; +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + return ARMADA_XP_SDIO; +} +#endif + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + return ARMADA_XP_TDM; +} + +/******************************************************************************* +* mvCtrlTdmMaxGet - Return the maximum number of TDM ports. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of TDM ports in device. +* +*******************************************************************************/ +MV_U32 mvCtrlTdmMaxGet(MV_VOID) +{ + return ARMADA_XP_MAX_TDM_PORTS; +} + +/******************************************************************************* +* mvCtrlTdmTypeGet +* +* DESCRIPTION: +* Return the TDM unit type being compiled in. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The TDM unit type. +* +*******************************************************************************/ +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID) +{ + return TDM_UNIT_32CH; +} + +/******************************************************************************* +* mvCtrlTdmUnitIrqGet +* +* DESCRIPTION: +* Return the TDM unit IRQ number depending on the TDM unit compilation +* options. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +******************************************************************************/ +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID) +{ + return MV_TDM_IRQ_NUM; +} + +#endif /* if defined(MV_INCLUDE_TDM) */ + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 devId; + MV_U16 model = 0; + MV_U32 reg, reg2; + /* if PEX0 clocks are disabled - enabled it to read */ + reg = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + reg2 = ((reg & ~PMC_PEXSTOPCLOCK_MASK(0)) | PMC_PEXSTOPCLOCK_EN(0)); + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2); + } + + devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + + /* Reset the original value of the PEX0 clock */ + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg); + } + + model = (MV_U16) ((devId >> 16) & 0xFFFF); +#if 0 + /* FIXME */ + /* Temperarely override model numebr for Z1 */ + switch (model) { + case MV_78130_DEV_ID: + case MV_78160_DEV_ID: + case MV_78230_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + model = MV_78460_DEV_ID; + break; + + /* Fallback: assume 78460 */ + default: + model = MV_78460_DEV_ID; + } +#endif + return model; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8) MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + if (mvCtrlModelGet() == 0x7800) + mvOsSPrintf(pNameBuff, "%s78XX", SOC_NAME_PREFIX); + else + mvOsSPrintf(pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, mvCtrlModelGet(), mvCtrlRevGet()); + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + switch (mvCtrlModelRevGet()) { + case MV_78130_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78130_Z1_NAME); + break; + + case MV_6710_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6710_Z1_NAME); + break; + + case MV_78230_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78230_Z1_NAME); + break; + case MV_78160_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78160_Z1_NAME); + break; + case MV_78260_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78260_Z1_NAME); + break; + case MV_78460_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78460_Z1_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} + +static const char *cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target) +{ + if (target >= MAX_TARGETS) + return "target unknown"; + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvCtrlPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar, winNum; + + for (pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++) { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) + continue; + mvOsOutput("\n"); + mvOsOutput("PEX%d:\n", pexIf); + mvOsOutput("-----\n"); + + mvOsOutput("\nPex Bars \n\n"); + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + memset(&pexBar, 0, sizeof(MV_PEX_BAR)); + + mvOsOutput("%s ", pexBarNameGet(bar)); + + if (mvPexBarGet(pexIf, bar, &pexBar) == MV_OK) { + if (pexBar.enable) { + mvOsOutput("base %08x, ", pexBar.addrWin.baseLow); + mvSizePrint(pexBar.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + mvOsOutput("\nPex Decode Windows\n\n"); + + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) { + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvPexTargetWinRead(pexIf, winNum, &win) == MV_OK) { + if (win.winInfo.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win.winInfo)), + win.winInfo.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.winInfo.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("default win - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("Expansion ROM - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + } +} + +/******************************************************************************* +* mvUnitAddrDecShow - Print the Unit's address decode map. +* +* DESCRIPTION: +* This is a generic function for printing the different unit's address +* decode map. +* +* INPUT: +* unit - The unit to print the address decode for. +* name - The unit's name. +* winGetFuncPtr - A pointer to the HAL's window get function. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvUnitAddrDecShow(MV_U8 numUnits, MV_UNIT_ID unitId, const char *name, MV_WIN_GET_FUNC_PTR winGetFuncPtr) +{ + MV_UNIT_WIN_INFO win; + MV_U32 unit, i; + + for (unit = 0; unit < numUnits; unit++) { + + if (MV_FALSE == mvCtrlPwrClckGet(unitId, unit)) + continue; + mvOsOutput("\n"); + mvOsOutput("%s %d:\n", name, unit); + mvOsOutput("----\n"); + + for (i = 0; i < 16; i++) { + memset(&win, 0, sizeof(MV_UNIT_WIN_INFO)); + + mvOsOutput("win%d - ", i); + + if (winGetFuncPtr(unit, i, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win)), + win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + } + return; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvCtrlPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUnitAddrDecShow(mvCtrlUsbMaxGet(), USB_UNIT_ID, "USB", mvUsbWinRead); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvEthWinRead); +#else + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvNetaWinRead); +#endif /* MV_ETH_LEGACY */ +#endif /* MV_INCLUDE_GIG_ETH */ + +#if defined(MV_INCLUDE_XOR) + mvUnitAddrDecShow(mvCtrlXorMaxChanGet(), XOR_UNIT_ID, "XOR", mvXorTargetWinRead); +#endif +#if defined(MV_INCLUDE_SATA) + mvUnitAddrDecShow(mvCtrlSataMaxPortGet(), SATA_UNIT_ID, "Sata", mvSataWinRead); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while (alignment & 1) { /* Check that alignmet LSB is set */ + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", (MV_U32) alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + retVal = size; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while (size & 1) /* Check that LSB is set */ + size = (size >> 1); /* If LSB is set, move one bit to the right */ + + if (size) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", size)); + return -1; + } + return retVal; +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while (temp & 1) /* Check that LSB is set */ + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + + if (temp) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", regSize)); + return -1; + } + + /* Check that aligment is a power of two */ + temp = alignment - 1; /* Now the alignmet is a sequance of '1' (0xffff) */ + + while (temp & 1) /* Check that alignmet LSB is set */ + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while (alignment & 1) { /* Check that alignmet LSB is set */ + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + return size; + + while (size) { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + return alignment; + else + return retSize; +} + +/******************************************************************************* +* mvCtrlIsBootFromNOR +* +* DESCRIPTION: +* Check if device is configured to boot from NOR flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_NOR) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromSPI +* +* DESCRIPTION: +* Check if device is configured to boot from SPI flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_SPI) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromNAND +* +* DESCRIPTION: +* Check if device is confiogured to boot from NAND flash according to the SAR +* registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from NAND. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if ((satr == MSAR_BOOT_DOVE_NAND) || (satr == MSAR_BOOT_LEGACY_NAND)) + return MV_TRUE; + else + return MV_FALSE; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + + break; +#endif + case TDM_32CH_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + + break; + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK(index)) == PMC_PEXSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_CESASTOPCLOCK_MASK) == PMC_CESASTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK(index)) == PMC_USBSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_32CH_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} + +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_MASK); + + break; +#endif + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg; + MV_BOOL state = MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX)); + if ((reg & PMC_PEXSTOPMEM_MASK(index)) == PMC_PEXSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE)); + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA)); + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA)); + if ((reg & PMC_CESASTOPMEM_MASK) == PMC_CESASTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB)); + if ((reg & PMC_USBSTOPMEM_MASK(index)) == PMC_USBSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR)); + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM)); + if ((reg & PMC_BMSTOPMEM_MASK) == PMC_BMSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC)); + if ((reg & PMC_PNCSTOPMEM_MASK) == PMC_PNCSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + return; +} + +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + return MV_TRUE; +} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvCtrlSerdesMaxLinesGet - Get Marvell controller number of SERDES lines. +* +* DESCRIPTION: +* This function returns Marvell controller number of SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 12; + break; + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return 16; + default: + return 0; + } +} + +MV_U32 mvCtrlDDRBudWidth(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x1400); + + return (reg & 0x8000)?64:32; +} +MV_BOOL mvCtrlDDRThruXbar(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x20184); + + return (reg & 0x1)?MV_FALSE:MV_TRUE; +} + +static const MV_U8 serdesCfg[][8] = SERDES_CFG; + +/******************************************************************************* +* mvCtrlSerdesPhyConfig +* +* DESCRIPTION: +* Configure Serdes MUX and init PHYs connected to SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Status +* +*******************************************************************************/ +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID) +{ + MV_U32 serdesLineCfg; + MV_U8 serdesLineNum; + MV_U32 regAddr[16][10], regVal[16][10]; /* addr/value for each line @ every setup step */ + MV_U8 pexUnit, pexLineNum; + MV_U8 step; + MV_U8 maxSerdesLines = mvCtrlSerdesMaxLinesGet(); + MV_SERDES_CFG *pSerdesInfo = mvBoardSerdesCfgGet(); + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + MV_STATUS status = MV_OK; + MV_U32 tmp; + + /* Check if no SERDESs available - FPGA */ + if (maxSerdesLines == 0) + return MV_OK; + + if (pSerdesInfo == NULL) { + DB(mvOsPrintf("%s: Error reading SERDES configuration!\n", __FUNCTION__)); + return MV_ERROR; + } + + memset(regAddr, 0, sizeof(regAddr)); + memset(regVal, 0, sizeof(regVal)); + memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO)); + + /* Prepare PHY parameters for each step according to MUX selection */ + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + /* for each serdes lane*/ + MV_U32 *pRegVal = regVal[serdesLineNum]; + MV_U32 *pRegAddr = regAddr[serdesLineNum]; + MV_U8 sgmiiPort = 0; + + if (serdesLineNum < 8) + serdesLineCfg = (pSerdesInfo->serdesLine0_7 >> (serdesLineNum << 2)) & 0xF; + else + serdesLineCfg = (pSerdesInfo->serdesLine8_15 >> ((serdesLineNum - 8) << 2)) & 0xF; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_PEX]) { + pexUnit = serdesLineNum >> 2; + pexLineNum = serdesLineNum % 4; + + /* Map the PCI-E interfaces according to their HW mapping + Map PCI-E virtual intrefaces in an array where we have information about + every interface (e.g. HW mapping, x1,x4,x8 ( disabled) .. ) + */ + switch (pexUnit) { + case 0: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex0Mod; + break; + case 1: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex1Mod; + break; + case 2: + if (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X4) + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_MODE_X4; + else + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_DISABLED; + break; + case 3: + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = pSerdesInfo->pex3Mod; + break; + } + if ((pexUnit < 2) && (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1)) { + + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexUnit * 4 + pexLineNum; + boardPexInfo->boardPexIfNum++; + boardPexInfo->pexUnitCfg[pexUnit].pexLaneStat[pexLineNum] = 0x1; + + } else if ((pexUnit < 4) && + (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) && + (pexLineNum == 0)) { + + switch (pexUnit) { + case 0: + case 1: + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexUnit*4 + pexLineNum; + break; + case 2: + case 3: + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = PEX2_0x4 + (pexUnit - 2); + break; + } + + boardPexInfo->boardPexIfNum++; + + } else if ((pexUnit == 3) && + (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X8) && + (pexLineNum == 0)) { + + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = PEX3_0x4; + boardPexInfo->boardPexIfNum++; + } + + /* Needed for PEX_PHY_ACCESS_REG macro */ + if ((serdesLineNum > 7) && (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X8)) + pexUnit = 3; /* lines 8 - 15 are belong to PEX3 in x8 mode */ + + /* regVal bits: + bit[31] - 0:write, 1:read + bit[23:16] - PHY REG offset + bit[29:24] - PEX line + bit[15:0] - value to be set in PHY REG + */ + pRegAddr[0] = PEX_PHY_ACCESS_REG(pexUnit); + pRegAddr[1] = 0; /*PEX_PHY_ACCESS_REG(pexUnit); */ + pRegAddr[2] = PEX_PHY_ACCESS_REG(pexUnit); + pRegAddr[3] = 0; + pRegAddr[4] = 0; + + /* PHY_MODE [7:5] - 3 (PCIe) + REF_FREF_SEL [4:0] - 0 (100MHz) */ + pRegVal[0] = (0x01 << 16) | (pexLineNum << 24) | 0xFC60; + +#if 0 + /* SEL_BITS [11:10] + For 2.5G: 0 (10bit) + For 5G: 1 (20bit) */ + pRegVal[1] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x0400 : 0x0; + pRegVal[1] |= (0x23 << 16) | (pexLineNum << 24); +#endif + /* SEL_BITS [11:10] - NA */ + pRegVal[1] = 0; + + /* REFCLK_SEL [10] - 0 */ + pRegVal[2] = (0x46 << 16) | (pexLineNum << 24); + + /* PIN_PHY_GEN [12:5] - NA */ + pRegVal[3] = 0; + pRegVal[4] = 0; + + + } else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SATA]) { + + MV_U8 sataPort; + + if ((serdesLineNum == 4) || (serdesLineNum == 8)) + sataPort = 0; + else if ((serdesLineNum == 5) || (serdesLineNum == 9)) + sataPort = 1; + else + goto err_cfg; + + pRegAddr[0] = SATA_PWR_PLL_CTRL_REG(sataPort); + pRegAddr[1] = SATA_DIG_LP_ENA_REG(sataPort); + pRegAddr[2] = SATA_REF_CLK_SEL_REG(sataPort); + pRegAddr[3] = SATA_LP_PHY_EXT_CTRL_REG(sataPort); + pRegAddr[4] = SATA_LP_PHY_EXT_STAT_REG(sataPort); + pRegVal[0] = 0xF801; + pRegVal[1] = 0x400; + pRegVal[2] = 0x400; + pRegVal[3] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x227 : 0x7; + pRegVal[4] = 0x7; + + } else { + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII0]) { + sgmiiPort = 0; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII1]) { + sgmiiPort = 1; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII2]) { + sgmiiPort = 2; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII3]) { + sgmiiPort = 3; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII]) { + sgmiiPort = 0; + } + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_UNCONNECTED]) + continue; + + pRegAddr[0] = SGMII_PWR_PLL_CTRL_REG(sgmiiPort); + pRegAddr[1] = SGMII_DIG_LP_ENA_REG(sgmiiPort); + pRegAddr[2] = SGMII_REF_CLK_SEL_REG(sgmiiPort); + pRegAddr[3] = SGMII_SERDES_CFG_REG(sgmiiPort); + pRegAddr[4] = SGMII_SERDES_STAT_REG(sgmiiPort); + pRegVal[0] = 0xF881; + pRegVal[1] = 0; + pRegVal[2] = 0x400; + pRegVal[3] = (pSerdesInfo->busSpeed & (1 << serdesLineNum)) != 0 ? 0x1547 : 0xCC7; + pRegVal[4] = 0x7; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII]) { + pRegVal[1] = 0x400; + pRegVal[3] = 0x667; + } + } + + } /* for each serdes lane*/ + + + /* Step 0 - configure SERDES MUXes */ + MV_REG_WRITE(SERDES_LINE_MUX_REG_0_7, pSerdesInfo->serdesLine0_7); + MV_REG_WRITE(SERDES_LINE_MUX_REG_8_15, pSerdesInfo->serdesLine8_15); + DB(mvOsPrintf("\nStep[0].1 Addr[0x%08x] Value[0x%08x]\n", SERDES_LINE_MUX_REG_0_7, pSerdesInfo->serdesLine0_7)); + DB(mvOsPrintf("Step[0].2 Addr[0x%08x] Value[0x%08x]\n\n", SERDES_LINE_MUX_REG_8_15, pSerdesInfo->serdesLine8_15)); + + /* Step 1 [PEX-Only] PEX-Main configuration (X4 or X1): */ + /* First disable all PEXs in SoC Control Reg */ + MV_REG_WRITE(SOC_CTRL_REG, 0x0); + + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + /* SoC Control + 0x18204 [7,8] + 0x0 X4-Link. + 0x1 n*X1-Link’s */ + if (pexUnit < 2) { + tmp = MV_REG_READ(SOC_CTRL_REG); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + tmp |= SCR_PEX_4BY1_MASK(pexUnit); + + DB(mvOsPrintf("Step[1].1 Addr[0x%08x] pexUnit [%d] value [0x%x]\n", SOC_CTRL_REG, pexUnit, tmp)); + MV_REG_WRITE(SOC_CTRL_REG, tmp); + } + } + + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + + if (serdesLineNum < 8) + serdesLineCfg = (pSerdesInfo->serdesLine0_7 >> (serdesLineNum << 2)) & 0xF; + else + serdesLineCfg = (pSerdesInfo->serdesLine8_15 >> ((serdesLineNum - 8) << 2)) & 0xF; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_PEX]) { + /* PCI Express Control + 0xX1A00 [0]: + 0x0 X4-Link. + 0x1 X1-Link */ + tmp = MV_REG_READ(PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum))); + tmp &= ~(0x3F0); + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X1) + tmp |= (0x1 << 4); + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X4) + tmp |= (0x4 << 4); + MV_REG_WRITE(PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum)), tmp); + DB(mvOsPrintf("Step[1].2 Addr[0x%08x] serdesLine [%d] value [0x%x]\n", PEX_LINK_CAPABILITIES_REG(MV_SERDES_NUM_TO_PEX_NUM(serdesLineNum)), serdesLineNum, tmp)); + /* if pex is X4, no need to pass thru the other 3X1 serdes lines */ + if (boardPexInfo->pexUnitCfg[serdesLineNum >> 2].pexCfg == PEX_BUS_MODE_X4) + serdesLineNum += 3; + } + } + DB(mvOsPrintf("\n")); + + /* Step 2 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you need to config the register SOC_Misc/General Purpose2 (Address= 182F8)*/ + tmp = MV_REG_READ(GEN_PURP_RES_2_REG); + + if (pSerdesInfo->pex0Mod == PEX_BUS_MODE_X4) + tmp |= 0x0000000F; +/* else + tmp &= 0xFFFFFFF0; +*/ + if (pSerdesInfo->pex1Mod == PEX_BUS_MODE_X4) + tmp |= 0x000000F0; +/* else + tmp &= 0xFFFFFF0F; */ + + if (pSerdesInfo->pex3Mod == PEX_BUS_MODE_X4) + tmp |= 0x0000FF00; +/* else + tmp &= 0xFFFF00FF; */ + + DB(mvOsPrintf("Step[2] Addr[0x%08x] Value[0x%08x]\n\n", GEN_PURP_RES_2_REG, tmp)); + + MV_REG_WRITE(GEN_PURP_RES_2_REG, tmp); + + /* STEP 3 [PEX-Only] First phase of PEX-PIPE Configuration:*/ + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + DB(mvOsPrintf("Step[3].1 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA5)); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) + DB(mvOsPrintf("Step[3].2 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC2 << 16) | 0x200)); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + DB(mvOsPrintf("Step[3].3 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC3 << 16) | 0x0F)); + + DB(mvOsPrintf("Step[3].4 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC8 << 16) | 0x05)); + DB(mvOsPrintf("Step[3].5 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xD0 << 16) | 0x100)); + DB(mvOsPrintf("Step[3].6 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xD1 << 16) | 0x3014)); + DB(mvOsPrintf("Step[3].7 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC5 << 16) | 0x11F)); + DB(mvOsPrintf("Step[3].8 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0x80 << 16) | 0x1000)); + DB(mvOsPrintf("Step[3].9 Addr[0x%08x] Value[0x%08x]\n\n", PEX_PHY_ACCESS_REG(pexUnit), (0x81 << 16) | 0x11)); + + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0x25); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC2 << 16) | 0x200); + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X1) + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC3 << 16) | 0x0F); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC8 << 16) | 0x05); + /* MV_REG_WRITE(PEX_PHY_ACCESS_REG(0), (0xC2 << 16) | 0x200); *//* BC was disabled per HW team request */ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xD0 << 16) | 0x100); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xD1 << 16) | 0x3014); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC5 << 16) | 0x11F); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x80 << 16) | 0x1000); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x81 << 16) | 0x11); + } + + /* Steps 4, 5, 6, 7 - use prepared REG addresses and values */ + for (step = 0; step < 4; step++) { + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + if (regAddr[serdesLineNum][step] != 0) { + DB(mvOsPrintf("Step[%d] Lane[%d] Addr[0x%08x] Value[0x%08x]\n", + step + 4, serdesLineNum, regAddr[serdesLineNum][step], regVal[serdesLineNum][step])); + MV_REG_WRITE(regAddr[serdesLineNum][step], regVal[serdesLineNum][step]); + } + } + DB(mvOsPrintf("\n")); + } + + /*Step 8 [PEX-Only] Last phase of PEX-PIPE Configuration */ + for (pexUnit = 0; pexUnit < mvCtrlPexMaxUnitGet(); pexUnit++) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_DISABLED) + continue; + DB(mvOsPrintf("Step[8].1 Addr[0x%08x] Value[0x%08x]\n", PEX_PHY_ACCESS_REG(pexUnit), (0x2 << 16) | 0x40)); + DB(mvOsPrintf("Step[8].2 Addr[0x%08x] Value[0x%08x]\n\n", PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA4)); + + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0x2 << 16) | 0x40); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexUnit), (0xC1 << 16) | 0xA4); + } + + /* Wait 5ms before checking results */ + mvOsDelay(15); + + /* Step 9 - check that PLL RX/TX is ready and RX init done */ + for (serdesLineNum = 0; serdesLineNum < maxSerdesLines; serdesLineNum++) { + MV_U32 tmp; + if (regAddr[serdesLineNum][4] != 0) { /* SATA, QSGMII, SGMII */ + tmp = MV_REG_READ(regAddr[serdesLineNum][4]); + if ((tmp & 0x7)!= regVal[serdesLineNum][4]) { /* check bits[2:0] */ + DB(mvOsPrintf("%s: PHY on SERDES lane %d is not ready!\n", + __FUNCTION__, serdesLineNum)); + status = MV_ERROR; + } +#if 1 + } else if (regAddr[serdesLineNum][0] != 0){ /* PEX that is enabled and passed step1 */ + /* First step writes into Power and PLL control register. + It's possible to read it back now for checking the PLL lock status */ + MV_REG_WRITE(regAddr[serdesLineNum][0], (regVal[serdesLineNum][0] | BIT31) & 0xFFFF0000); + tmp = MV_REG_READ(regAddr[serdesLineNum][0]); + if ((tmp & BIT8) == 0) { + DB(mvOsPrintf("%s: PEX PHY PLL on SERDES lane %d is not locked!\n", + __FUNCTION__, serdesLineNum)); + status = MV_ERROR; + } +#endif + } + } + + return status; + +err_cfg: + DB(mvOsPrintf("%s: Wrong CFG (%#x) for SERDES line %d.\n", + __FUNCTION__, serdesLineCfg, serdesLineNum)); + return MV_ERROR; + +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,243 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +/*#include "boardEnv/mvBoardEnvLib.h"*/ + +/* 0 for Auto scan mode, 1 for manual. */ +#define MV_INTERNAL_SWITCH_SMI_SCAN_MODE 0 + +/* typedefs */ +typedef MV_STATUS (*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*); + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy { + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +} MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType { + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +} MV_SWAP_TYPE; + +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7, + SERDES_UNIT_LAST +} MV_SERDES_UNIT_INDX; + +typedef enum { + PEX_BUS_DISABLED = 0, + PEX_BUS_MODE_X1 = 1, + PEX_BUS_MODE_X4 = 2, + PEX_BUS_MODE_X8 = 3 +} MV_PEX_UNIT_CFG; + +/* Configuration per SERDES line. + Each nibble is MV_SERDES_LINE_TYPE */ +typedef struct _boardSerdesConf { + MV_U32 serdesLine0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */ + MV_U32 serdesLine8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */ + MV_PEX_UNIT_CFG pex0Mod; + MV_PEX_UNIT_CFG pex1Mod; + MV_PEX_UNIT_CFG pex3Mod; + MV_U32 busSpeed; /* Bus speed - one bit per SERDES line: + Low speed (0) High speed (1) + PEX 2.5 G (10 bit) 5 G (20 bit) + SATA 1.5 G 3 G + SGMII 1.25 Gbps 3.125 Gbps */ +} MV_SERDES_CFG; + + + +/* BIOS Modes related defines */ +#define SAR0_CPU_FREQ_MASK 0x00E00000 +#define SAR0_CPU_FREQ_OFFSET 21 +#define SAR0_FABRIC_FREQ_MASK 0x0F000000 +#define SAR0_FABRIC_FREQ_OFFSET 24 +#define SAR0_L2_SIZE_MASK 0x00180000 +#define SAR0_L2_SIZE_OFFSET 19 +#define SAR1_CPU_CORE_MASK 0x00000018 +#define SAR1_CPU_CORE_OFFSET 3 +#define SAR1_CPU_MODE_MASK 0x00100000 +#define SAR1_CPU_MODE_OFFSET 20 +#define SAR1_FABRIC_MODE_MASK 0x00080000 +#define SAR1_FABRIC_MODE_OFFSET 19 + + +#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) +#define BIOS_MODES_NUM 7 + +typedef struct { + char *name; + MV_U16 confId; + MV_U16 code; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreq; + MV_U8 fabricFreqMode; + MV_U8 cpuEna; + MV_U8 cpuMode; +}MV_BIOS_MODE; + +extern MV_BIOS_MODE bios_modes[]; + +/* mcspLib.h API list */ +MV_U32 mvCtrlGetCpuNum(MV_VOID); +MV_STATUS mvCtrlUpdatePexId(MV_VOID); + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif + +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +#else +#define mvCtrlPciIfMaxIfGet() (mvCtrlPexMaxIfGet()) +#endif + +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID); +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_LEGACY_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmSupport(MV_VOID); +MV_U32 mvCtrlTdmMaxGet(MV_VOID); +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID); +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID); +#endif + +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID); +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); + +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID); +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID); +MV_U32 mvCtrlDDRBudWidth(MV_VOID); +MV_BOOL mvCtrlDDRThruXbar(MV_VOID); + +#endif /* __INCmvCtrlEnvLibh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,523 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + : : "memory"); +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ +#define MV_TDM_IRQ_NUM 56 + +/* Power Management Memory Power Down Registers 1 - 6 */ +#define POWER_MNG_MEM_CTRL_REG(num) ((num) < 6 ? 0x1821 + (num) * 4 : 0x18228) +#define PMC_MCR_NUM_COMM 6 +#define PMC_MCR_NUM_PEX 2 +#define PMC_MCR_NUM_USB 4 +#define PMC_MCR_NUM_DUNIT 3 +#define PMC_MCR_NUM_DEVB 4 +#define PMC_MCR_NUM_NF 4 +#define PMC_MCR_NUM_XOR 4 +#define PMC_MCR_NUM_SATA 5 +#define PMC_MCR_NUM_CESA 4 +#define PMC_MCR_NUM_GE 5 +#define PMC_MCR_NUM_PNC 5 +#define PMC_MCR_NUM_BM 5 +#define PMC_MCR_NUM_PDMA 1 +#define PMC_MCR_NUM_NCS 3 +#define PMC_MCR_NUM_CFU 3 +#define PMC_MCR_NUM_L2 3 +#define PMC_MCR_NUM_CIB 3 +#define PMC_MCR_NUM_CPU 3 +#define PMC_MCR_NUM_IDMA 4 +#define PMC_MCR_NUM_LCD 4 +#define PMC_MCR_NUM_PMU 6 + +#define PMC_COMMSTOPMEM_OFFS 4 +#define PMC_COMMSTOPMEM_MASK (7 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_EN (0 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_STOP (1 << PMC_COMMSTOPMEM_OFFS) + +#define PMC_PEXSTOPMEM_OFFS(port) ((port) < 10 ? ((port) * 3) : 0) +#define PMC_PEXSTOPMEM_MASK(port) (7 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_EN(port) (0 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_STOP(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) + +#define PMC_USBSTOPMEM_OFFS(port) ((port) < 3 ? (3 + (port) * 3) : 0) +#define PMC_USBSTOPMEM_MASK(port) (7 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_EN(port) (0 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_STOP(port) (1 << PMC_USBSTOPMEM_OFFS(port)) + +#define PMC_DUNITSTOPMEM_OFFS 12 +#define PMC_DUNITSTOPMEM_MASK (7 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +#define PMC_NFSTOPMEM_OFFS 27 +#define PMC_NFSTOPMEM_MASK (7 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_EN (0 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_STOP (1 << PMC_NFSTOPMEM_OFFS) + +#define PMC_DEVBSTOPMEM_OFFS 21 +#define PMC_DEVBSTOPMEM_MASK (7 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_EN (0 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_STOP (1 << PMC_DEVBSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) ((port) == 0 ? 15 : 24) +#define PMC_XORSTOPMEM_MASK(port) (7 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_SATASTOPMEM_OFFS(port) ((port) == 0 ? 18 : 24) +#define PMC_SATASTOPMEM_MASK(port) (0x3F << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (9 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_CESASTOPMEM_OFFS 18 +#define PMC_CESASTOPMEM_MASK (7 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_EN (0 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_STOP (1 << PMC_CESASTOPMEM_OFFS) + +#define PMC_GESTOPMEM_OFFS(port) ((port) < 4 ? (9 - (port) * 3) : 0) +#define PMC_GESTOPMEM_MASK(port) (7 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +#define PMC_PNCSTOPMEM_OFFS 12 +#define PMC_PNCSTOPMEM_MASK (7 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_EN (0 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_STOP (1 << PMC_PNCSTOPMEM_OFFS) + +#define PMC_BMSTOPMEM_OFFS 15 +#define PMC_BMSTOPMEM_MASK (7 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_EN (0 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_STOP (1 << PMC_BMSTOPMEM_OFFS) + +#define PMC_PDMASTOPMEM_OFFS 0 +#define PMC_PDMATOPMEM_MASK (7 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_EN (0 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_STOP (1 << PMC_PDMASTOPMEM_OFFS) + +#define PMC_NCSSTOPMEM_OFFS 24 +#define PMC_NCSSTOPMEM_MASK (7 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_EN (0 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_STOP (1 << PMC_NCSSTOPMEM_OFFS) + +#define PMC_CFUSTOPMEM_OFFS 21 +#define PMC_CFUSTOPMEM_MASK (7 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_EN (0 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_STOP (1 << PMC_CFUSTOPMEM_OFFS) + +#define PMC_L2STOPMEM_OFFS 18 +#define PMC_L2STOPMEM_MASK (7 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_EN (0 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_STOP (1 << PMC_L2STOPMEM_OFFS) + +#define PMC_CIBSTOPMEM_OFFS 15 +#define PMC_CIBSTOPMEM_MASK (7 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_EN (0 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_STOP (1 << PMC_CIBSTOPMEM_OFFS) + +/* TODO - verify, the manual has no description */ +#define PMC_CPUSTOPMEM_OFFS(id) ((id) < 4 ? (id) * 3 : 0) +#define PMC_CPUSTOPMEM_MASK(id) (7 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_EN(id) (0 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_STOP(id) (1 << PMC_CPUSTOPMEM_OFFS(id)) + +#define PMC_IDMASTOPMEM_OFFS 12 +#define PMC_IDMASTOPMEM_MASK (7 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_EN (0 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_STOP (1 << PMC_IDMASTOPMEM_OFFS) + +#define PMC_LCDSTOPMEM_OFFS 0 +#define PMC_LCDSTOPMEM_MASK (7 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_EN (0 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_STOP (1 << PMC_LCDSTOPMEM_OFFS) + +#define PMC_PMUSTOPMEM_OFFS 0 +#define PMC_PMUSTOPMEM_MASK (7 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_EN (0 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_STOP (1 << PMC_PMUSTOPMEM_OFFS) + + +/* Power Management Clock Gating Control Register */ +#define POWER_MNG_CTRL_REG 0x18220 + +#define PMC_TDMSTOPCLOCK_OFFS 25 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) +#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) + +#define PMC_USBSTOPCLOCK_OFFS(port) ((port) < 3 ? (18 + (port)) : 0) +#define PMC_USBSTOPCLOCK_MASK(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_EN(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_STOP(port) (0 << PMC_USBSTOPCLOCK_OFFS(port)) + +#define PMC_SDIOSTOPCLOCK_OFFS 17 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_RUNITSTOPCLOCK_OFFS 24 +#define PMC_RUNITSTOPCLOCK_MASK (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_EN (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_STOP (0 << PMC_RUNITSTOPCLOCK_OFFS) + +#define PMC_XORSTOPCLOCK_OFFS 22 +#define PMC_XORSTOPCLOCK_MASK (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_EN (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_STOP (0 << PMC_XORSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS(ch) (ch == 0 ? 14 : 29) +#define PMC_SATASTOPCLOCK_MASK(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_EN(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_STOP(ch) (0 << PMC_SATASTOPCLOCK_OFFS(ch)) + +#define PMC_CESASTOPCLOCK_OFFS 23 +#define PMC_CESASTOPCLOCK_MASK (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_EN (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_STOP (0 << PMC_CESASTOPCLOCK_OFFS) + +#define PMC_GESTOPCLOCK_OFFS(port) ((port) < 4 ? (4 - (port)) : 0) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_NETASTOPCLOCK_OFFS 13 +#define PMC_NETASTOPCLOCK_MASK (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_EN (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_STOP (0 << PMC_NETASTOPCLOCK_OFFS) + +#define PMC_LCDSTOPCLOCK_OFFS 16 +#define PMC_LCDSTOPCLOCK_MASK (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_EN (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_STOP (0 << PMC_LCDSTOPCLOCK_OFFS) + +#define PMC_IDMASTOPCLOCK_OFFS 21 +#define PMC_IDMASTOPCLOCK_MASK (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_EN (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_STOP (0 << PMC_IDMASTOPCLOCK_OFFS) + +#define PMC_DDRSTOPCLOCK_OFFS 28 +#define PMC_DDRSTOPCLOCK_MASK (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_EN (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_STOP (0 << PMC_DDRSTOPCLOCK_OFFS) + +#define SATA_PWR_PLL_CTRL_REG(port) (0xA2804 + (port)*0x2000) +#define SATA_DIG_LP_ENA_REG(port) (0xA288C + (port)*0x2000) +#define SATA_REF_CLK_SEL_REG(port) (0xA2918 + (port)*0x2000) +#define SATA_LP_PHY_EXT_CTRL_REG(port) (0xA2058 + (port)*0x2000) +#define SATA_LP_PHY_EXT_STAT_REG(port) (0xA205C + (port)*0x2000) + +#define SGMII_PWR_PLL_CTRL_REG(port) (0x72E04 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_DIG_LP_ENA_REG(port) (0x72E8C + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_REF_CLK_SEL_REG(port) (0x72F18 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_CFG_REG(port) (0x724A0 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_STAT_REG(port) (0x724A4 + ((port)%2)*0x4000 - ((port)/2)*0x40000) + +#define SERDES_LINE_MUX_REG_0_7 0x18270 +#define SERDES_LINE_MUX_REG_8_15 0x18274 + +/* Controler environment registers offsets */ +#define GEN_PURP_RES_1_REG 0x182F4 +#define GEN_PURP_RES_2_REG 0x182F8 + +#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) + +/* Sample at Reset */ +#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) + +/* SYSRSTn Length Counter */ +#define SYSRST_LENGTH_COUNTER_REG 0x18250 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) + +/* Device ID */ +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK 0x3 + +#define MPP_OUTPUT_DRIVE_REG 0x184E4 +#define MPP_GE_A_OUTPUT_DRIVE_OFFS 6 +#define MPP_GE_A_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_A_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_OUTPUT_DRIVE_OFFS 14 +#define MPP_GE_B_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_B_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_B_OUTPUT_DRIVE_OFFS) + +#define MSAR_BOOT_MODE_OFFS 5 +#define MSAR_BOOT_MODE_MASK (0xF << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NOR (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI (0x3 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_DOVE_NAND (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_LEGACY_NAND (0x6 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLCK0_OFFS 24 +#define MSAR_TCLCK1_OFFS 8 +#define MSAR_TCLCK0_MASK (0x1 << MSAR_TCLCK0_OFFS) +#define MSAR_TCLCK1_MASK (0x1 << MSAR_TCLCK1_OFFS) + + +/* Extract CPU, L2, DDR clocks SAR value from +** SAR bits 24-27 +*/ +#define MSAR_CPU_CLK_IDX(sar0, sar1) ((((sar0) >> 21) & 0x7) + ((((sar1) >> 20) & 1) << 3)) +#define MSAR_CPU_CLK_TWSI(sar0, sar1) ((((sar0) >> 2) & 0x7) + (((sar1) & 1) << 3)) +#define MSAR_DDR_L2_CLK_RATIO_IDX(sar0,sar1) ((((sar0) >> 24) & 0xF) + ((((sar1) >> 19) & 1) << 4)) +#define MSAR_DDR_L2_CLK_RATIO_TWSI(sar0) (((sar0) >> 1) & 0xF) + +#ifndef MV_ASMLANGUAGE + +#define MV_CPU_CLK_TBL { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000,\ + 600, 667, 800, 1600, 2133, 2200, 2400, 0 } + +#define MV_DEFAULT_PCLK 1333000000 +#define MV_BOARD_DEFAULT_SYSCLK MV_DEFAULT_PCLK +#define MV_BOARD_DEFAULT_L2CLK 667000000 + +/* cpu l2c hclk ddr */ +#define MV_DDR_L2_CLK_RATIO_TBL { \ +/*00*/ { 1, 1, 4, 2 },\ +/*01*/ { 1, 2, 2, 2 },\ +/*02*/ { 2, 2, 6, 3 },\ +/*03*/ { 2, 2, 3, 3 },\ +/*04*/ { 1, 2, 3, 3 },\ +/*05*/ { 1, 2, 4, 2 },\ +/*06*/ { 1, 1, 2, 2 },\ +/*07*/ { 2, 3, 6, 6 },\ +/*08*/ { 2, 3, 5, 5 },\ +/*09*/ { 1, 2, 6, 3 },\ +/*10*/ { 2, 4, 10, 5 },\ +/*11*/ { 1, 3, 6, 6 },\ +/*12*/ { 1, 2, 5, 5 },\ +/*13*/ { 1, 3, 6, 3 },\ +/*14*/ { 1, 2, 5, 5 },\ +/*15*/ { 2, 2, 5, 5 },\ +/*16*/ { 1, 1, 3, 3 },\ +/*17*/ { 2, 5, 10, 10 },\ +/*18*/ { 1, 3, 8, 4 },\ +/*19*/ { 1, 1, 2, 1 },\ +/*20*/ { 2, 3, 6, 3 },\ +/*21*/ { 1, 2, 8, 4 },\ +/*22*/ { 2, 5, 10, 5 } \ +} + +/* These macros help units to identify a target Mport Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) +#define MV_TARGET_IS_PEX2(target) \ + ((target >= PEX2_MEM) && (target <= PEX2_IO)) +#define MV_TARGET_IS_PEX3(target) \ + ((target >= PEX3_MEM) && (target <= PEX3_IO)) +#define MV_TARGET_IS_PEX4(target) \ + ((target >= PEX4_MEM) && (target <= PEX4_IO)) +#define MV_TARGET_IS_PEX5(target) \ + ((target >= PEX5_MEM) && (target <= PEX5_IO)) +#define MV_TARGET_IS_PEX6(target) \ + ((target >= PEX6_MEM) && (target <= PEX6_IO)) +#define MV_TARGET_IS_PEX7(target) \ + ((target >= PEX7_MEM) && (target <= PEX7_IO)) +#define MV_TARGET_IS_PEX8(target) \ + ((target >= PEX8_MEM) && (target <= PEX8_IO)) +#define MV_TARGET_IS_PEX9(target) \ + ((target >= PEX9_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_PEX(target) ((target >= PEX0_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_DEVICE(target) ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == BOOT_ROM_CS) + +#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS) ? \ + sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) \ + & MSAR_BOOT_MODE_MASK) \ + >> MSAR_BOOT_MODE_OFFS)] : (target)) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + + +#define BOOT_TARGETS_NAME_ARRAY { \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS \ +} + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + START_DEV_CS) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +/* This enumerator defines the Marvell controller target ID (see Address map) */ +typedef enum _mvTargetId { + DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */ + PEX0_2_TARGET_ID = 4, /* Port 4 -> PCI Express 0 and 2 */ + PEX1_3_TARGET_ID = 8, /* Port 4 -> PCI Express 1 and 3 */ + CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */ + PNC_BM_TARGET_ID = 12, /* Port 12 -> PNC + BM Unit */ + MAX_TARGETS_ID +} MV_TARGET_ID; + +/* +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7 +} MV_SERDES_UNIT_INDX; +*/ + +/* + This structure refrect registers: + Serdes 0-7 selectors 0x18270 + and Serdes 8-15 selectors 0x18274 +*/ +#define SERDES_CFG { \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 0 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 1 */ \ + {0, 1, -1 , 2, -1, -1, -1, -1}, /* Lane 2 */ \ + {0, 1, -1 , -1, 2, -1, -1, -1}, /* Lane 3 */ \ + {0, 1, 2 , -1, -1, 3, -1, -1}, /* Lane 4 */ \ + {0, 1, 2 , -1, 3, -1, -1, 4}, /* Lane 5 */ \ + {0, 1, -1 , -1, -1, 2, 3, -1}, /* Lane 6 */ \ + {0, 1, -1 , 2, -1, -1, 3, -1}, /* Lane 7*/ \ + {0, 1, 2 , -1, -1, -1, 3, 4}, /* Lane 8 */ \ + {0, 1, 2 , 3, -1, -1, -1, -1}, /* Lane 9 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 10 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 11 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 12 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 13 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 14 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1} /* Lane 15 */ \ +} + +/* + This enum should reflect the units numbers in register + space which we will need when accessing the HW +*/ + +typedef enum { + PEX0_0x4 = 0, + PEX0_1x4 = 1, + PEX0_2x4 = 2, + PEX0_3x4 = 3, + PEX1_0x4 = 4, + PEX1_1x4 = 5, + PEX1_2x4 = 6, + PEX1_3x4 = 7, + PEX2_0x4 = 8, + PEX3_0x4 = 9, + PEXIF_MAX = 10 +} MV_PEXIF_INDX; + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,457 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +#include "cpu/mvCpu.h" /* whoAmI() */ + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define OLD_CESA_HAL +/* #if defined OLD_CESA_HAL +#warning "Workign with old CESA HAL (one channel only!)" +#endif +*/ +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* + * Armada-XP Units Address decoding + */ +#define MV_DRAM_REGS_OFFSET (0x0) +#define MV_AURORA_L2_REGS_OFFSET (0x8000) +#define MV_RTC_REGS_OFFSET (0x10300) +#define MV_DEV_BUS_REGS_OFFSET (0x10400) +#define MV_SPI_REGS_OFFSET(unit) (0x10600) +#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100)) +#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100)) +#define MV_MPP_REGS_OFFSET (0x18000) +#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x20)) +#define MV_MISC_REGS_OFFSET (0x18200) +#define MV_MBUS_REGS_OFFSET (0x20000) +#define MV_COHERENCY_FABRIC_OFFSET (0x20200) +#define MV_CNTMR_REGS_OFFSET (0x20300) +#define MV_CPUIF_REGS_OFFSET(cpu) (0x21000 + (cpu) * 0x100) +#if defined(MV_ETH_LEGACY) + #define MV_ETH_BASE_ADDR (0x72000) +#else + #define MV_ETH_BASE_ADDR (0x70000) +#endif +#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * 0x40000 + ((port) % 2) * 0x4000) +#define MV_PEX_IF_REGS_OFFSET(pexIf) (pexIf < 8 ? (0x40000 + ((pexIf) / 4) * 0x40000 + ((pexIf) % 4) * 0x4000)\ + : (0X42000 + ((pexIf) % 8) * 0x40000)) +#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000)) +#define MV_XOR_REGS_OFFSET(unit) (0x60900) +#define MV_CESA_TDMA_REGS_OFFSET (0x90000) +#define MV_CESA_REGS_OFFSET (0x9D000) +#define MV_SATA_REGS_OFFSET (0xA0000) +#define MV_COMM_UNIT_REGS_OFFSET (0xB0000) +#define MV_NFC_REGS_OFFSET (0xC0000) +#define MV_BM_REGS_OFFSET (0xC0000) +#define MV_PNC_REGS_OFFSET (0xC8000) +#define MV_SDMMC_REGS_OFFSET (0xD4000) + +#define MV_SERDES_NUM_TO_PEX_NUM(sernum) ((sernum < 8) ? (sernum) : (8 + (sernum/12))) +/* + * Miscellanuous Controller Configurations + */ +#define INTER_REGS_SIZE _1M + +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG CPU_MAIN_INT_CAUSE_REG(1, whoAmI()) +#define TWSI0_CPU_MAIN_INT_BIT(ch) ((ch) + 3) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_PINS 68 +#define MV_GPP_MAX_GROUP 3 /* group == configuration register? */ +#define MV_CNTMR_MAX_COUNTER 8 /* 4 global + 2 per CPU + 2*WD*/ +#define MV_UART_MAX_CHAN 4 + +#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ + +#define MV_SATA_MAX_CHAN 2 + +#define MV_MPP_MAX_GROUP 9 + +#define MV_DRAM_MAX_CS 4 +#define MV_SPI_MAX_CS 8 +/* This define describes the maximum number of supported PCI\PCIX Interfaces */ +#ifdef MV_INCLUDE_PCI + #define MV_PCI_MAX_IF 1 + #define MV_PCI_START_IF 0 + #define PCI_HOST_BUS_NUM(pciIf) (pciIf) + #define PCI_HOST_DEV_NUM(pciIf) 0 +#else + #define MV_PCI_MAX_IF 0 + #define MV_PCI_START_IF 0 +#endif + +/* This define describes the maximum number of supported PEX Interfaces */ +#ifdef MV_INCLUDE_PEX +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR + +#define MV_PEX_MAX_IF 10 +#define MV_PEX_START_IF MV_PCI_MAX_IF +#define MV_PEX_MAX_UNIT 4 + #define PEX_HOST_BUS_NUM(pciIf) (pciIf) + #define PEX_HOST_DEV_NUM(pciIf) 0 +#else + #undef MV_INCLUDE_PEX0 +#endif + +#define PCI_IO(pciIf) (PEX0_IO + 2 * (pciIf)) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM0 + 2 * (pciIf)) +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_IDMA_MAX_CHAN 4 +#define ARMADA_XP_MAX_USB_PORTS 3 +#define ARMADA_XP_NAND 1 +#define ARMADA_XP_SDIO 1 +#define ARMADA_XP_MAX_TDM_PORTS 32 +#define ARMADA_XP_TDM 1 +#define MV_DEVICE_MAX_CS 4 + +#ifndef MV_USB_MAX_PORTS +#define MV_USB_MAX_PORTS (ARMADA_XP_MAX_USB_PORTS) +#endif + + +/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */ +#define MV_CESA_VERSION 3 /*TODO verify */ +#define MV_CESA_SRAM_SIZE (2 * 1024) +#ifndef OLD_CESA_HAL +#define MV_CESA_ENGINES 2 +#endif + +/* This define describes the maximum number of supported Ethernet ports */ +/* TODO - verify all these numbers */ +#define MV_ETH_VERSION 4 /* for Legacy mode */ +#define MV_NETA_VERSION 1 /* for NETA mode */ +#define MV_ETH_MAX_PORTS 4 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_TX_CSUM_MAX_SIZE 9800 +#define MV_ETH_TCAM_LINES 1024 /* TCAM num of entries */ + +#define MV_78130_ETH_MAX_PORT 3 +#define MV_78460_ETH_MAX_PORT 4 + +/* This define describes the the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_SPI_VERSION 2 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#ifndef MV_ASMLANGUAGE + +#define TBL_UNUSED 0 /* Used to mark unused entry */ + +typedef enum { + TDM_UNIT_32CH +} MV_TDM_UNIT_TYPE; + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId { + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_32CH_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + SDIO_UNIT_ID, + BM_UNIT_ID, + PNC_UNIT_ID, + MAX_UNITS_ID +} MV_UNIT_ID; + +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice { +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif + BOOT_CS, /* Device connected to BOOT dev */ + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +} MV_DEVICE; + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget { + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /*0 SDRAM chip select 0 */ + SDRAM_CS1, /*1 SDRAM chip select 1 */ + SDRAM_CS2, /*2 SDRAM chip select 2 */ + SDRAM_CS3, /*3 SDRAM chip select 3 */ + DEVICE_CS0, /*4 Device chip select 0 */ + DEVICE_CS1, /*5 Device chip select 1 */ + DEVICE_CS2, /*6 Device chip select 2 */ + DEVICE_CS3, /*7 Device chip select 3 */ + PEX0_MEM, /*8 PCI Express 0 Memory */ + PEX0_IO, /*9 PCI Express 0 IO */ + PEX1_MEM, /*10 PCI Express 1 Memory */ + PEX1_IO, /*11 PCI Express 1 IO */ + PEX2_MEM, /*12 PCI Express 2 Memory */ + PEX2_IO, /*13 PCI Express 2 IO */ + PEX3_MEM, /*14 PCI Express 3 Memory */ + PEX3_IO, /*15 PCI Express 3 IO */ + PEX4_MEM, /*16 PCI Express 4 Memory */ + PEX4_IO, /*17 PCI Express 4 IO */ + PEX5_MEM, /*18 PCI Express 5 Memory */ + PEX5_IO, /*19 PCI Express 5 IO */ + PEX6_MEM, /*20 PCI Express 6 Memory */ + PEX6_IO, /*21 PCI Express 6 IO */ + PEX7_MEM, /*22 PCI Express 7 Memory */ + PEX7_IO, /*23 PCI Express 7 IO */ + PEX8_MEM, /*24 PCI Express 8 Memory */ + PEX8_IO, /*25 PCI Express 8 IO */ + PEX9_MEM, /*26 PCI Express 9 Memory */ + PEX9_IO, /*27 PCI Express 9 IO */ + INTER_REGS, /*28 Internal registers */ + DMA_UART, /*29 DMA based UART request */ + SPI_CS0, /*30 SPI_CS0 */ + SPI_CS1, /*31 SPI_CS1 */ + SPI_CS2, /*32 SPI_CS2 */ + SPI_CS3, /*33 SPI_CS3 */ + SPI_CS4, /*34 SPI_CS4 */ + SPI_CS5, /*35 SPI_CS5 */ + SPI_CS6, /*36 SPI_CS6 */ + SPI_CS7, /*37 SPI_CS7 */ + BOOT_ROM_CS, /*38 BOOT_ROM_CS */ + DEV_BOOCS, /*39 DEV_BOOCS */ + PMU_SCRATCHPAD, /*40 PMU Scratchpad */ +#ifdef MV_INCLUDE_LEGACY_NAND + LEGACY_NAND, /* Legacy NAND controller */ +#endif + CRYPT_ENG, /*41 Crypto Engine */ +#ifndef OLD_CESA_HAL + CRYPT_ENG1, /* Crypto Engine1 */ +#endif +#ifdef CONFIG_MV_ETH_BM + PNC_BM, /* PNC + BM */ +#endif + MAX_TARGETS +} MV_TARGET; + +#if defined OLD_CESA_HAL +#define CESA_TARGET_ID_DEF {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG */ +#else +#define CESA_TARGET_ID_DEF {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG0 */ \ + {0x05, CRYPT_TARGET_ID }, /* CRYPT_ENG1 */ +#endif + +#ifdef AURORA_IO_CACHE_COHERENCY +#define DRAM_CS0_ATTR 0x1E +#define DRAM_CS1_ATTR 0x1D +#define DRAM_CS2_ATTR 0x1B +#define DRAM_CS3_ATTR 0x17 +#else +#define DRAM_CS0_ATTR 0x0E +#define DRAM_CS1_ATTR 0x0D +#define DRAM_CS2_ATTR 0x0B +#define DRAM_CS3_ATTR 0x07 +#endif + +#define TARGETS_DEF_ARRAY { \ + {DRAM_CS0_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS1_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {DRAM_CS2_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS3_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0x3E, DEV_TARGET_ID }, /* DEVICE_CS0 */ \ + {0x3D, DEV_TARGET_ID }, /* DEVICE_CS1 */ \ + {0x3B, DEV_TARGET_ID }, /* DEVICE_CS2 */ \ + {0x37, DEV_TARGET_ID }, /* DEVICE_CS3 */ \ + {0xE8, PEX0_2_TARGET_ID }, /* PEX0_LANE0_MEM */ \ + {0xE0, PEX0_2_TARGET_ID }, /* PEX0_LANE0_IO */ \ + {0xD8, PEX0_2_TARGET_ID }, /* PEX0_LANE1_MEM */ \ + {0xD0, PEX0_2_TARGET_ID }, /* PEX0_LANE1_IO */ \ + {0xB8, PEX0_2_TARGET_ID }, /* PEX0_LANE2_MEM */ \ + {0xB0, PEX0_2_TARGET_ID }, /* PEX0_LANE2_IO */ \ + {0x78, PEX0_2_TARGET_ID }, /* PEX0_LANE3_MEM */ \ + {0x70, PEX0_2_TARGET_ID }, /* PEX0_LANE3_IO */ \ + {0xE8, PEX1_3_TARGET_ID }, /* PEX1_LANE0_MEM */ \ + {0xE0, PEX1_3_TARGET_ID }, /* PEX1_LANE0_IO */ \ + {0xD8, PEX1_3_TARGET_ID }, /* PEX1_LANE1_MEM */ \ + {0xD0, PEX1_3_TARGET_ID }, /* PEX1_LANE1_IO */ \ + {0xB8, PEX1_3_TARGET_ID }, /* PEX1_LANE2_MEM */ \ + {0xB0, PEX1_3_TARGET_ID }, /* PEX1_LANE2_IO */ \ + {0x78, PEX1_3_TARGET_ID }, /* PEX1_LANE3_MEM */ \ + {0x70, PEX1_3_TARGET_ID }, /* PEX1_LANE3_IO */ \ + {0xF8, PEX0_2_TARGET_ID }, /* PEX2_LANE0_MEM */ \ + {0xF0, PEX0_2_TARGET_ID }, /* PEX2_LANE0_IO */ \ + {0xF8, PEX1_3_TARGET_ID }, /* PEX3_LANE0_MEM */ \ + {0xF0, PEX1_3_TARGET_ID }, /* PEX3_LANE0_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x01, DEV_TARGET_ID }, /* DMA_UART */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS0 */ \ + {0x5E, DEV_TARGET_ID }, /* SPI_CS1 */ \ + {0x9E, DEV_TARGET_ID }, /* SPI_CS2 */ \ + {0xDE, DEV_TARGET_ID }, /* SPI_CS3 */ \ + {0x1F, DEV_TARGET_ID }, /* SPI_CS4 */ \ + {0x5F, DEV_TARGET_ID }, /* SPI_CS5 */ \ + {0x9F, DEV_TARGET_ID }, /* SPI_CS6 */ \ + {0xDF, DEV_TARGET_ID }, /* SPI_CS7 */ \ + {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ + {0x2F, DEV_TARGET_ID }, /* DEV_BOOT_CS */ \ + {0x2D, DEV_TARGET_ID }, /* PMU_SCRATCHPAD */ \ + CESA_TARGET_ID_DEF \ + {0x00, PNC_BM_TARGET_ID }, /* PNC_BM */ \ +} + +#if defined OLD_CESA_HAL +#define CESA_TARGET_NAME_DEF "CRYPT_ENG" +#else +#define CESA_TARGET_NAME_DEF "CRYPT_ENG0", "CRYPT_ENG1" +#endif + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS1 */ \ + "SDRAM_CS3", /* SDRAM_CS1 */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEVICE_CS3", /* DEVICE_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "PEX2_MEM", /* PEX2_MEM */ \ + "PEX2_IO", /* PEX2_IO */ \ + "PEX3_MEM", /* PEX3_MEM */ \ + "PEX3_IO", /* PEX3_IO */ \ + "PEX4_MEM", /* PEX4_MEM */ \ + "PEX4_IO", /* PEX4_IO */ \ + "PEX5_MEM", /* PEX5_MEM */ \ + "PEX5_IO", /* PEX5_IO */ \ + "PEX6_MEM", /* PEX6_MEM */ \ + "PEX6_IO", /* PEX6_IO */ \ + "PEX7_MEM", /* PEX7_MEM */ \ + "PEX7_IO", /* PEX7_IO */ \ + "PEX8_MEM", /* PEX8_MEM */ \ + "PEX8_IO", /* PEX8_IO */ \ + "PEX9_MEM", /* PEX9_MEM */ \ + "PEX9_IO", /* PEX9_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DMA_UART", /* DMA_UART */ \ + "SPI_CS0", /* SPI_CS0 */ \ + "SPI_CS1", /* SPI_CS1 */ \ + "SPI_CS2", /* SPI_CS2 */ \ + "SPI_CS3", /* SPI_CS3 */ \ + "SPI_CS4", /* SPI_CS4 */ \ + "SPI_CS5", /* SPI_CS5 */ \ + "SPI_CS6", /* SPI_CS6 */ \ + "SPI_CS7", /* SPI_CS7 */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */ \ + CESA_TARGET_NAME_DEF, \ + "PNC_BM" /* PNC_BM */ \ +} + + + + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvSpech */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,750 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "mvCpuIfRegs.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* typedefs */ + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs { + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +} AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + MV_U32 sizeToReg; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to " + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* Size parameter validity check. */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.size, ATMWCR_WIN_SIZE_ALIGNMENT)) { + mvOsPrintf("mvAhbToMbusWinSet: Failed, size not aligned to 0x%x.\n", ATMWCR_WIN_SIZE_ALIGNMENT); + return MV_BAD_PARAM; + } + + /* Write to address decode Base Address Register */ + decRegs.baseReg = (pAddrDecWin->addrWin.baseLow & ATMWBR_BASE_MASK); + + /* Get size register value according to window size */ + sizeToReg = (pAddrDecWin->addrWin.size / ATMWCR_WIN_SIZE_ALIGNMENT) - 1; + + /* set size */ + decRegs.ctrlReg = (sizeToReg << ATMWCR_WIN_SIZE_OFFS); + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + decRegs.ctrlReg |= ATMWCR_WIN_ENABLE; + else + decRegs.ctrlReg &= ~ATMWCR_WIN_ENABLE; + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.ctrlReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.ctrlReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.ctrlReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.ctrlReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + mvAhbToMbusWinEnable(winNum, MV_FALSE); +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + } else { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + } + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.ctrlReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 sizeRegVal; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal register space size have no size register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.ctrlReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + else + decRegs.ctrlReg = 0; + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + else + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + + pAddrDecWin->addrWin.baseHigh = 0; + pAddrDecWin->addrWin.baseLow = decRegs.baseReg & ATMWBR_BASE_MASK; + sizeRegVal = (decRegs.ctrlReg & ATMWCR_WIN_SIZE_MASK) >> ATMWCR_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * ATMWCR_WIN_SIZE_ALIGNMENT; + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + if (decRegs.ctrlReg & ATMWCR_WIN_ENABLE) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + + if (-1 == pAddrDecWin->addrWin.size) + return MV_ERROR; + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.ctrlReg & ATMWCR_WIN_ATTR_MASK) >> ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.ctrlReg & ATMWCR_WIN_TARGET_MASK) >> ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is illegal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + return MV_AHB_TO_MBUS_INTREG_WIN; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) { + if (decWin.target == target) + return winNum; + } + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_FALSE) + return winNum; + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + return (enable ? MV_OK : MV_ERROR); + + + if (enable == MV_TRUE) { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } else { + /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + MV_U32 effectiveBaseAddress = 0, baseAddrValue = 0, windowSizeValue = 0; + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + return 0xffffffff; + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &= ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2) +{ + MV_U32 winNum1, winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1, winDec2, winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1, remapRegs2; + MV_U32 remapBaseLow1 = 0, remapBaseLow2 = 0; + MV_U32 remapBaseHigh1 = 0, remapBaseHigh2 = 0; + + /* Check parameters */ + if (target1 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target1, winNum1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + if (winNum2 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target2, winNum2); + return MV_ERROR; + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1, &winDec1)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinGet(winNum2, &winDec2)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum2); + return MV_ERROR; + } + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", winNum2); + return MV_ERROR; + } + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + /* now set the new values */ + mvAhbToMbusWinSet(winNum1, &winDec1); + mvAhbToMbusWinSet(winNum2, &winDec2); + + /* now we will treat the remap windows if exist */ + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows */ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs, remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs, remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs, remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs, remapBaseLow2); + } else { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs, winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs, winDec1.addrWin.baseLow); + } + } else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs, winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs, winDec2.addrWin.baseLow); + } + + return MV_OK; +} + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + case 4: + case 5: + case 6: + case 7: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + default: + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput("\n"); + mvOsOutput("AHB To MBUS Bridge:\n"); + mvOsOutput("-------------------\n"); + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + memset(&win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvAhbToMbusWinGet(winNum, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +typedef struct _mvAhbtoMbusDecWin { + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2); + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + +#endif /* __INCmvAhbToMbush */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,142 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +#define MAX_AHB_TO_MBUS_WINS 21 +#define MAX_AHB_TO_MBUS_REMAP_WINS 8 +#define MV_AHB_TO_MBUS_INTREG_WIN 20 + +/***********************/ +/* AHB TO MBUS WINDOWS */ +/***********************/ +/* Window-X Control Registers */ +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + winNum * 0x10): \ + (MV_MBUS_REGS_OFFSET + 0x90 + (winNum-8)*0x08)) +#define ATMWCR_WIN_ENABLE BIT0 +#define ATMWCR_WIN_TARGET_OFFS 4 +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) +#define ATMWCR_WIN_ATTR_OFFS 8 +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) +#define ATMWCR_WIN_SIZE_OFFS 16 +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window-X Base Register */ +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0x4 + winNum*0x10): \ + (MV_MBUS_REGS_OFFSET + 0x94 + (winNum-8)*0x08)) +#define ATMWBR_BASE_OFFS 16 +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window-X Remap Low Register */ +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0x8 + winNum*0x10): \ + (0)) +#define ATMWRLR_REMAP_LOW_OFFS 16 +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window-X Remap Hi Register */ +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS)? \ + (MV_MBUS_REGS_OFFSET + 0xC + winNum*0x10): \ + (0)) +#define ATMWRHR_REMAP_HIGH_OFFS 0 +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + +/*****************************/ +/* INTERNAL REGISTERS WINDOW */ +/*****************************/ +/* Internal Registers Base Address in set to be window 20 */ +#define AHB_TO_MBUS_WIN_INTEREG_REG (MV_MBUS_REGS_OFFSET + 0x80) + +/************************/ +/* SDRAM DECODE WINDOWS */ +/************************/ +/* All DRAM Window definitions are declared under the ddr2_3 HAL */ + +/****************************/ +/* SRAM (L2) DECODE WINDOWS */ +/****************************/ +#define SRAM_WIN_CTRL_REG(winNum) (MV_MBUS_REGS_OFFSET + 0x240 + winNum * 0x4) +#define SRAMWCR_ENABLE BIT0 +#define SRAMWCR_SIZE_OFFS 8 +#define SRAMWCR_SIZE_MASK (0x7 << SRAMWCR_SIZE_OFFS) +#define SRAMWCR_BASE_OFFS 16 +#define SRAMWCR_BASE_MASK (0xFFFF << SRAMWCR_BASE_OFFS) + +/**********************/ +/* MBUS BRIDGE WINDOW */ +/**********************/ +#define MBUS_BRIDGE_WIN_CTRL_REG (MV_MBUS_REGS_OFFSET + 0x250) +#define BRIDGWCR_ENABLE BIT0 +#define BRIDGWCR_SIZE_OFFS 16 +#define BRIDGWCR_SIZE_MASK (0xFFFF << BRIDGWCR_SIZE_OFFS) + +#endif /* __INCmvAhbToMbusRegsh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,875 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +/*#include "cpu/mvCpu.h" *//* whoAmI() */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "ddr2_3/mvDramIf.h" +#include "pex/mvPexRegs.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +/******************************************************************************* +* mvCpuIfInitForCpu - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* cpu - CPU id. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInitForCpu(MV_U32 cpu, MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal, i; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set CPU Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG(cpu)); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG(cpu), regVal); + + for (i = 0; i < MAX_AHB_TO_MBUS_WINS-2; i++) + mvAhbToMbusWinEnable(i, MV_FALSE); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS)) + continue; + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target), MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + continue; +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ + if (MV_TARGET_IS_AS_BOOT(target)) + continue; + + if ((0 == cpuAddrWinMap[target].addrWin.size) || (DIS == cpuAddrWinMap[target].enable)) { + #if 0 /* TODO: windows are already disabled above, we need to skip only*/ + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + #else + {continue;} + #endif + } else { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + } + } +#warning TODO: this is not needed anymore cause pex enabled is already at CtrlEnvInit +#if 0 +#ifdef MV_INCLUDE_PEX + if (cpu == 0) { /* Not needed for all CPUs */ + MV_U32 pexUnits = mvCtrlPexMaxUnitGet(); + for (i = 0; i < pexUnits; i++) + mvCpuIfEnablePex(i); + } +#endif +#endif + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + return mvCpuIfInitForCpu(whoAmI(), cpuAddrWinMap); +} + +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is illegal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + if (mvDramIfWinSet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + } else { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS) && (existingWinNum != pAddrDecWin->winNum)) { + /* if we want to enable the new window number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum, MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum, &decWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_U32 winNum = 0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is illegal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinGet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = target; + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return MV_NO_SUCH; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", __func__, winNum); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is illegal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) { + return (enable ? MV_ERROR : MV_OK); + } else if (MV_OK != temp) { + mvOsPrintf("%s: ERR. Getting target %d failed.\n", __func__, target); + return MV_ERROR; + } + + /* check overlap */ + if (MV_TRUE == enable) { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n", __func__, target)); + return MV_ERROR; + } + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinEnable(target, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + } + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return (enable ? MV_ERROR : MV_OK); + + if (mvAhbToMbusWinEnable(winNum, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", winNum); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is illegal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + return (addrDecWin.addrWin.size); + else + return 0; /* Window disabled. return 0 */ +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0xffffffff; + + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0; + + return (addrDecWin.addrWin.baseHigh); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (mvCtrlPexMaxIfGet() > 1) { + if ((!MV_TARGET_IS_PEX0(pexTarget)) && + (!MV_TARGET_IS_PEX1(pexTarget)) && + (!MV_TARGET_IS_PEX2(pexTarget)) && + (!MV_TARGET_IS_PEX3(pexTarget)) && + (!MV_TARGET_IS_PEX4(pexTarget)) && + (!MV_TARGET_IS_PEX5(pexTarget)) && + (!MV_TARGET_IS_PEX6(pexTarget)) && + (!MV_TARGET_IS_PEX7(pexTarget)) && + (!MV_TARGET_IS_PEX8(pexTarget)) && + (!MV_TARGET_IS_PEX9(pexTarget))) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } else { + if (!MV_TARGET_IS_PEX0(pexTarget)) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciIfTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for (target = 0; target < MAX_TARGETS; target++) { + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) + break; + } + } else + return MAX_TARGETS; + } + + return target; +} + +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + for (targetNum = 0; targetNum < MAX_TARGETS; targetNum++) { +#if defined(MV_RUN_FROM_FLASH) + if (MV_TARGET_IS_AS_BOOT(target)) { + if (MV_CHANGE_BOOT_CS(targetNum) == target) + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* don't check our target or illegal targets */ + if (targetNum == target) + continue; + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if (MV_NO_SUCH == status) + continue; + + if (MV_OK != status) { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) { + DB(mvOsPrintf("cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + mvOsOutput("\n"); + mvOsOutput("CPU Interface\n"); + mvOsOutput("-------------\n"); + + for (target = 0; target < MAX_TARGETS; target++) { + memset(&win, 0, sizeof(MV_CPU_DEC_WIN)); + + mvOsOutput("%s ", mvCtrlTargetNameGet(target)); + mvOsOutput("...."); + + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("base %08x, ", win.addrWin.baseLow); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } else if (mvCpuIfTargetWinGet(target, &win) == MV_NO_SUCH) { + mvOsOutput("no such\n"); + } + } +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfEnablePex - Enable PCI Express unit. +* +* DESCRIPTION: +* This function enables PCI Express access to the device address +* space. +* +* INPUT: +* pexUnit - PEX unit (0 - 3). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfEnablePex(MV_U32 pexUnit) +{ + MV_U32 socMaxPexUnit = mvCtrlPexMaxUnitGet(); + + if (pexUnit > socMaxPexUnit) { + DB(mvOsPrintf("mvCpuIfEnablePex: Bad PEX unit ID (%x)\n", pexUnit)); + return; + } + + /* SOC config register Pex enable */ + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX_ENA_MASK(pexUnit)); +} + +/******************************************************************************* +* mvCpuIfPex4x1Enable - Enable/Disable the 4x1 mode on PCI Express unit. +* +* DESCRIPTION: +* This function enables/disables 4x1 mode on PCI Express unit 0 or 1 +* +* INPUT: +* pexUnit - PEX unit (0 or 1). +* enable - enable (MV_TRUE) or disable (MV_FALSE) 4x1 mode +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfPex4x1Enable(MV_U32 pexUnit, MV_BOOL enable) +{ + if (pexUnit == 0) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX0_4BY1_MASK); + else if (pexUnit == 1) + MV_REG_BIT_SET(SOC_CTRL_REG, SCR_PEX1_4BY1_MASK); + else + DB(mvOsPrintf("mvCpuIfPex4x1Enable: Bad PEX unit ID (%x)\n", pexUnit)); +} + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_CPU_DEC_WIN; + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_VOID mvCpuIfEnablePex(MV_U32 pexUnit); +MV_VOID mvCpuIfPex4x1Enable(MV_U32 pexUnit, MV_BOOL enable); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +#endif /* __INCmvCpuIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,167 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvCommon.h" +#include "mvOsAsm.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + b done +#if 0 + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281/6282 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) +#endif + +done: + mov PC, r11 /* r11 is saved link register */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-04-04 13:57:34.905597180 -0400 @@ -0,0 +1,299 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + +#define MV_CPUIF_REGS_BASE(cpu) (MV_CPUIF_REGS_OFFSET(cpu)) +#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) +#define MV_L2C_REGS_BASE (MV_AURORA_L2_REGS_OFFSET) +#define MV_CPUIF_SHARED_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_COHERENCY_FABRIC_REGS_BASE (MV_COHERENCY_FABRIC_OFFSET) + +#define CPU_CONFIG_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x800) +#define CPU_CTRL_STAT_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x808) +#define CPU_RSTOUTN_MASK_REG (MV_MISC_REGS_BASE + 0x60) +#define CPU_SYS_SOFT_RST_REG (MV_MISC_REGS_BASE + 0x64) +#define CPU_L2_CTRL_REG (MV_L2C_REGS_BASE + 0x100) +#define CPU_L2_AUX_CTRL_REG (MV_L2C_REGS_BASE + 0x104) +#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) +#define SOC_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_REGS_BASE) +#define SOC_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x4) +#define SOC_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x80) + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK (1 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK (1 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + +#define CCR_ARM_ID_SEL_OFFS 4 +#define CCR_CPU_ID_SEL_MASK (1 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_ARM (0 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_MRVL (1 << CCR_ARM_ID_SEL_OFFS) + +#define CCR_TE_INIT_OFFS 5 +#define CCR_TE_INIT_MASK (1 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_ARM (0 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_THUMB (1 << CCR_NCB_BLOCKING_OFFS) + +#define CCR_NFMI_EN_OFFS 6 +#define CCR_NFMI_EN_MASK (1 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_DIS (0 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_EN (1 << CCR_NFMI_EN_OFFS) + +#define CCR_CORE_MODE_OFFS 9 +#define CCR_CORE_MODE_MASK (3 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM1176 (0 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_CORTEX_A8 (1 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM11_MPC (2 << CCR_CORE_MODE_OFFS) + +#define CCR_UBIT_INIT_OFFS 11 +#define CCR_UBIT_INIT_MASK (1 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_DIS (0 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_EN (1 << CCR_UBIT_INIT_OFFS) + +#define CCR_PCLK_WFI_OFFS 15 +#define CCR_PCLK_WFI_MASK (1 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_DIS (0 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_EN (1 << CCR_PCLK_WFI_OFFS) + +#define CCR_SHARED_L2_OFFS 16 +#define CCR_SHARED_L2_MASK (1 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_DIS (0 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_EN (1 << CCR_SHARED_L2_OFFS) + +#define CCR_SP_IN_MP_OFFS 17 +#define CCR_SP_IN_MP_MASK (1 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_DIS (0 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_EN (1 << CCR_SP_IN_MP_OFFS) + +#define CCR_SRAM_LOW_LEAK_OFFS 19 +#define CCR_SRAM_LOW_LEAK_MASK (1 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_EN (0 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_DIS (1 << CCR_SRAM_LOW_LEAK_OFFS) + +#define CCR_CLUSTER_ID_OFFS 24 +#define CCR_CLUSTER_ID_MASK (0xF << CCR_SRAM_LOW_LEAK_OFFS) + + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + +#define CCSR_SMP_N_AMP_OFFS 0 +#define CCSR_SMP_N_AMP_MASK (1 << CCSR_SMP_N_AMP_OFFS) + +#define CCSR_ENDIAN_STATUS_OFFS 0 +#define CCSR_ENDIAN_STATUS_MASK (1 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_LITTLE (0 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_BIG (1 << CCSR_ENDIAN_STATUS_OFFS) + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_SOFT_RST_OUT_OFFS 0 +#define CRMR_SOFT_RST_OUT_MASK (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISABLE (0 << CRMR_SOFT_RST_OUT_OFFS) + +#define CRMR_PEX_SYSRST_OUT_OFFS(bus) (1 + ((bus) & 0x3)) +#define CRMR_PEX_SYSRST_OUT_MASK(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_ENABLE(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_DISABLE(bus) (0 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) + +#define CRMR_PEX_TRST_OUT_OFFS(bus) (5 + ((bus) & 0x3)) +#define CRMR_PEX_TRST_OUT_MASK(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_ENABLE(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_DISABLE(bus) (0 << CRMR_PEX_TRST_OUT_OFFS(bus)) + + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + + +/* CPU_L2_CTRL_REG fields */ + +#define CL2CR_L2_EN_OFFS 0 +#define CL2CR_L2_EN_MASK (1 << CL2CR_L2_EN_OFFS) + +/* CPU_L2_AUX_CTRL_REG fields */ + +#define CL2ACR_WB_WT_ATTR_OFFS 0 +#define CL2ACR_WB_WT_ATTR_MASK (3 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_PAGE (0 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WB (1 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WT (2 << CL2ACR_WB_WT_ATTR_OFFS) + +#define CL2ACR_PFU_OFFS 2 +#define CL2ACR_PFU_MASK (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_EN (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_DIS (0 << CL2ACR_PFU_OFFS) + +#define CL2ACR_L2_SIZE_OFFS 10 +#define CL2ACR_L2_SIZE_MASK (3 << CL2ACR_L2_SIZE_OFFS) +#define CL2ACR_L2_SIZE_KB(reg) ((((((reg) & 0x3) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_PFU_OFFS) + 1) * _512K) + +#define CL2ACR_ASSOC_OFFS 13 +#define CL2ACR_ASSOC_MASK (0xF << CL2ACR_ASSOC_OFFS) + +#define CL2ACR_L2_WAY_SZ_OFFS 17 +#define CL2ACR_L2_WAY_SZ_MASK (7 << CL2ACR_L2_WAY_SZ_OFFS) +#define CL2ACR_L2_WAY_SZ_KB(reg) (_16K << (((((reg) & 0x7) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_L2_WAY_SZ_OFFS))) + +#define CL2ACR_ECC_OFFS 20 +#define CL2ACR_ECC_MASK (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_EN (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_DIS (0 << CL2ACR_ECC_OFFS) + +#define CL2ACR_PARITY_OFFS 21 +#define CL2ACR_PARITY_MASK (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_EN (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_DIS (0 << CL2ACR_PARITY_OFFS) + +#define CL2ACR_INVAL_UCE_OFFS 22 +#define CL2ACR_INVAL_UCE_MASK (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_EN (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_DIS (0 << CL2ACR_INVAL_UCE_OFFS) + +#define CL2ACR_FORCE_WA_OFFS 23 +#define CL2ACR_FORCE_WA_MASK (3 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA_DISABLE (0 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_NO_WA (1 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA (2 << CL2ACR_FORCE_WA_OFFS) + +#define CL2ACR_REP_STRGY_OFFS 27 +#define CL2ACR_REP_STRGY_MASK (3 << CL2ACR_REP_STRGY_OFFS) + +/* SOC_CTRL_REG fields */ +#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) +#define SCR_PEX_ENA_MASK(pex) (1 << pex) + +#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) +#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) + +#define SCR_PEX0_4BY1_OFFS 7 +#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS) + +#define SCR_PEX1_4BY1_OFFS 8 +#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG(vec, cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x880 + (vec * 0x4)) +#define CPU_MAIN_INT_TWSI_OFFS(i) (2 + i) +#define CPU_MAIN_INT_CAUSE_TWSI(i) (31 + i) + +#define CPU_CF_LOCAL_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x8c4) +#define CPU_INT_SOURCE_CONTROL_REG(i) (MV_CPUIF_SHARED_REGS_BASE + 0xB00 + (i * 0x4)) + +#define CPU_INT_SOURCE_CONTROL_ENA_OFFS 28 +#define CPU_INT_SOURCE_CONTROL_ENA_MASK (1 << CPU_INT_SOURCE_CONTROL_ENA_OFFS) + + + +#define MV_IRQ_NR 116 + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x878) +#define CPU_HOST_TO_ARM_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x87C) +#define CPU_ARM_TO_HOST_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x870) +#define CPU_ARM_TO_HOST_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x874) + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK) +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +#endif /* __INCmvCpuIfRegsh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->turnOff out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->badrSkew out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8) && (pDevParams->deviceWidth != 16) && (pDevParams->deviceWidth != 32)) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } + + /* devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); */ + /* setting values */ + devParam |= DBP_TURNOFF_SET(pDevParams->turnOff); + devParam |= DBP_ACC2FIRST_SET(pDevParams->acc2First); + devParam |= DBP_ACC2NEXT_SET(pDevParams->acc2Next); + devParam |= ((pDevParams->badrSkew & DBP_BADRSKEW_MASK) << DBP_BADRSKEW_OFFS); + + switch (pDevParams->deviceWidth) { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + return MV_ERROR; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device), devParam); + + devParam = 0; + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(device), devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = DBP_TURNOFF_GET(devParam); + pDevParams->acc2First = DBP_ACC2FIRST_GET(devParam); + pDevParams->acc2Next = DBP_ACC2NEXT_GET(devParam); + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + switch (devParam & DBP_DEVWIDTH_MASK) { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth = 8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth = 16; + break; + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth = 32; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG_WR(device)); + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bits (8,16,32...). +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32) (0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandDevCsSet - Set NAND chip-select, care mode and init sequence +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(device)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(device)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(device)); + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDevice.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "device/mvDeviceRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam { + /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash control registers with NAND device- */ +/* select and care mode */ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode); + +#endif /* #ifndef __INCmvDeviceH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/armada_xp_family/device/mvDeviceRegs.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,269 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_DEVICE_MAX_XBAR_TIMEOUT 0x0FFF +/* TODO - usage of DEV_BANK_PARAM_REG_DV is unclear */ +/* #define DEV_BANK_PARAM_REG_DV 0x80000000 */ +/* registers offsets */ + +static INLINE MV_U32 DEV_BANK_PARAM_REG(int num) +{ + switch (num) { + case (BOOT_CS): + return MV_DEV_BUS_REGS_OFFSET + 0x400; + case (DEV_CS0): + return MV_DEV_BUS_REGS_OFFSET + 0x408; + case (DEV_CS1): + return MV_DEV_BUS_REGS_OFFSET + 0x410; +#ifdef MV_INCLUDE_DEVICE_CS2 + case (DEV_CS2): + return MV_DEV_BUS_REGS_OFFSET + 0x418; +#endif +#ifdef MV_INCLUDE_DEVICE_CS3 + case (DEV_CS3): + return MV_DEV_BUS_REGS_OFFSET + 0x420; +#endif + default: + return 0xFFFFFFFF; + } +} + +#define DEV_BANK_PARAM_REG_WR(num) (DEV_BANK_PARAM_REG(num)+0x4) +#define DEV_NAND_CTRL_REG (MV_DEV_BUS_REGS_OFFSET + 0x0470) + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ +/* DBP_XXX_MASK_HIGH is the offset of the extend bit from the msb of the input value */ + +#define DBP_TURNOFF_OFFS_LOW 0 +#define DBP_TURNOFF_MASK_LOW 0x3F +#define MAX_DBP_TURNOFF 0xf + + +#define DBP_TURNOFF_SET(value) \ +((value & DBP_TURNOFF_MASK_LOW) << DBP_TURNOFF_OFFS_LOW) + +#define DBP_TURNOFF_GET(value) \ +((value >> DBP_TURNOFF_OFFS_LOW) & DBP_TURNOFF_MASK_LOW) + +#define DBP_ACC2FIRST_OFFS_LOW 6 +#define DBP_ACC2FIRST_MASK_LOW 0x3f +#define MAX_DBP_ACC2FIRST 0x3f + +#define DBP_ACC2FIRST_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2FIRST_GET(value) \ +((value >> DBP_ACC2FIRST_OFFS_LOW) & DBP_ACC2FIRST_MASK_LOW) + +#define DBP_ACC2NEXT_OFFS_LOW 17 +#define DBP_ACC2NEXT_MASK_LOW 0x3f +#define MAX_DBP_ACC2NEXT 0x3f + +#define DBP_ACC2NEXT_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2NEXT_GET(value) \ +((value >> DBP_ACC2NEXT_OFFS_LOW) & DBP_ACC2NEXT_MASK_LOW) + +#define DBP_DEVWIDTH_OFFS 30 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + + +#define DBP_ALE2WR_OFFS_LOW 0 +#define DBP_ALE2WR_MASK_LOW 0x3f +#define MAX_DBP_ALE2WR 0x3F + +#define DBP_ALE2WR_SET(value) \ +((value & DBP_ALE2WR_MASK_LOW) << DBP_ALE2WR_OFFS_LOW) + +#define DBP_ALE2WR_GET(value) \ +((value >> DBP_ALE2WR_OFFS_LOW) & DBP_ALE2WR_MASK_LOW) + +#define DBP_WRLOW_OFFS_LOW 8 +#define DBP_WRLOW_MASK_LOW 0x3F +#define MAX_DBP_WRLOW 0x3F + +#define DBP_WRLOW_SET(value) \ +((value & DBP_WRLOW_MASK_LOW) << DBP_WRLOW_OFFS_LOW) + +#define DBP_WRLOW_GET(value) \ +((value >> DBP_WRLOW_OFFS_LOW) & DBP_WRLOW_MASK_LOW) + +#define DBP_WRHIGH_OFFS_LOW 16 +#define DBP_WRHIGH_MASK_LOW 0x3F +#define MAX_DBP_WRHIGH 0x3F + +#define DBP_WRHIGH_SET(value) \ +((value & DBP_WRHIGH_MASK_LOW) << DBP_WRHIGH_OFFS_LOW) + +#define DBP_WRHIGH_GET(value) \ +((value >> DBP_WRHIGH_OFFS_LOW) & DBP_WRHIGH_MASK_LOW) + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +/* NAND Flash Control register fields (NF) (NF_REG)*/ +#define NF_BOOTCS_OFFS 0 /* Define if BOOTCS is connected to NAND Flash */ +#define NF_BOOT_MASK (1 << NF_BOOTCS_OFFS) +#define NF_BOOT_NC (0 << NF_BOOTCS_OFFS) +#define NF_BOOT_C (1 << NF_BOOTCS_OFFS) + +#define NF_BOOTCS_CE_ACT_OFFS 1 /* Define if NAND Flash on BOOTCS is CE care or CE don't care */ +#define NF_BOOTCS_CE_ACT_MASK (1 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_NCARE (0 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_CARE (1 << NF_BOOTCS_CE_ACT_OFFS) + +#define NF_CS0_OFFS 2 /* Define if CS0 is connected to NAND Flash */ +#define NF_CS0_MASK (1 << NF_CS0_OFFS) +#define NF_CS0_NC (0 << NF_CS0_OFFS) +#define NF_CS0_C (1 << NF_CS0_OFFS) + +#define NF_CS0_CE_ACT_OFFS 3 /* Define if NAND Flash on CS0 is CE care or CE don't care */ +#define NF_CS0_CE_ACT_MASK (1 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_NCARE (0 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_CARE (1 << NF_CS0_CE_ACT_OFFS) + +#define NF_CS1_OFFS 4 /* Define if CS1 is connected to NAND Flash */ +#define NF_CS1_MASK (1 << NF_CS1_OFFS) +#define NF_CS1_NC (0 << NF_CS1_OFFS) +#define NF_CS1_C (1 << NF_CS1_OFFS) + +#define NF_CS1_CE_ACT_OFFS 5 /* Define if NAND Flash on CS1 is CE care or CE don't care */ +#define NF_CS1_CE_ACT_MASK (1 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_NCARE (0 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_CARE (1 << NF_CS1_CE_ACT_OFFS) + +#define NF_CS2_OFFS 6 /* Define if CS2 is connected to NAND Flash */ +#define NF_CS2_MASK (1 << NF_CS2_OFFS) +#define NF_CS2_NC (0 << NF_CS2_OFFS) +#define NF_CS2_C (1 << NF_CS2_OFFS) + +#define NF_CS2_CE_ACT_OFFS 7 /* Define if NAND Flash on CS2 is CE care or CE don't care */ +#define NF_CS2_CE_ACT_MASK (1 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_NCARE (0 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_CARE (1 << NF_CS2_CE_ACT_OFFS) + +#define NF_INIT_SEQ_OFFS 8 /* NAND Flash initialization sequence */ +#define NF_INIT_SEQ_MASK (1 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_EN (0 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_DIS (1 << NF_INIT_SEQ_OFFS) + +#define NF_OE_HIGHW_OFFS 9 /* NAND Flash OE high width in core clocks units (value + 1) */ +#define NF_OE_HIGHW_MASK (0x1f << NF_OE_HIGHW_OFFS) +#define MAX_OE_HIGHW (0x1f << NF_OE_HIGHW_OFFS) + +#define NF_TREADY_OFFS 14 /* NAND Flash time ready in core clocks units (value + 1) */ +#define NF_TREADY_MASK (0x1f << NF_TREADY_OFFS) +#define MAX_TREADY (0x1f << NF_TREADY_OFFS) + +#define NF_OE_TCTRL_OFFS 19 /* NAND Flash OE toggle control */ +#define NF_OE_TCTRL_MASK (1 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_1_CYC_AFT (0 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_SAME_CYC (1 << NF_OE_TCTRL_OFFS) + +#define NF_CS3_OFFS 20 /* Define if CS3 is connected to NAND Flash */ +#define NF_CS3_MASK (1 << NF_CS3_OFFS) +#define NF_CS3_NC (0 << NF_CS3_OFFS) +#define NF_CS3_C (1 << NF_CS3_OFFS) + +#define NF_CS3_CE_ACT_OFFS 21 /* Define if NAND Flash on CS3 is CE care or CE don't care */ +#define NF_CS3_CE_ACT_MASK (1 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_NCARE (0 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_CARE (1 << NF_CS3_CE_ACT_OFFS) + + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) \ +(csNum == BOOT_CS) ? 0x1 : ((csNum == DEV_CS3) ? (0x1 << 20) : (0x1 << (((csNum+1) % MV_DEV_MAX_CS) * 2))) + + +#define DINFCR_NF_ACT_CE_MASK(csNum) \ +(csNum == DEV_CS3) ? (0x2 << 20) : (0x2 << (((csNum+1) % MV_DEV_MAX_CS) * 2)) + +#define NAND_ACTCEBOOT_BIT BIT1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCmvDeviceRegsH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bios.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bios.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bios.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bios.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,138 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#include "mvCommon.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + + +static int do_bios_list() +{ + int i = 0; + MV_U8 confId = mvBoardConfIdGet(); + + printf("DB Conf Conf ID L2 size CPU Freq Fabric Freq CPU1/2/3 Enable CPU Mode V6UP/V6MP\n"); +#warning TODO: -1 is for not showing the 78480 problematic flavour + if (confId != 0x11) { + for (i=0; i < BIOS_MODES_NUM-1; i++) { + + printf("%s\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n", bios_modes[i].name, bios_modes[i].confId, bios_modes[i].l2size, bios_modes[i].cpuFreq, bios_modes[i].fabricFreq, bios_modes[i].cpuEna, bios_modes[i].cpuMode); + } + } else { + printf("%s\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n", bios_modes[1].name, bios_modes[1].confId, bios_modes[1].l2size, bios_modes[1].cpuFreq, bios_modes[1].fabricFreq, bios_modes[1].cpuEna, bios_modes[1].cpuMode); + } + + return 0; +} +static int do_bios_read() +{ + int i = 0; + int flag = 0; + MV_U8 l2size = mvBoardL2SizeGet(); + MV_U8 cpuFreq = mvBoardCpuFreqGet(); + MV_U8 fabricFreq = mvBoardFabFreqGet(); + MV_U8 cpuEna = mvBoardCpuCoresNumGet(); + MV_U8 cpuMode = mvBoardCpu0CoreModeGet(); + MV_U8 confId = mvBoardConfIdGet(); + + for (i=0; i < BIOS_MODES_NUM; i++) { + if ((bios_modes[i].l2size == l2size) && + (bios_modes[i].cpuFreq == cpuFreq) && + (bios_modes[i].fabricFreq == fabricFreq) && + (bios_modes[i].cpuEna == cpuEna) && + (bios_modes[i].cpuMode == cpuMode) && + (bios_modes[i].confId == confId)) { + + printf("Current BIOS mode is: %s\n", bios_modes[i].name); + flag = 1; + } + } + if (flag == 0) + printf("Current BIOS mode is invalid!\n"); + + return 0; +} +static int do_bios_write(int argc, char *argv[]) +{ + int i = 0; + int flag = 0; + const char *cmd; + + if (argc < 1) + goto usage; + cmd = argv[0]; + + for (i=0; i < BIOS_MODES_NUM; i++) { + if (strcmp(cmd, bios_modes[i].name) == 0) { + + printf("Setting BIOS mode : %s\n", bios_modes[i].name); + mvBoardL2SizeSet(bios_modes[i].l2size); + mvBoardCpuFreqSet(bios_modes[i].cpuFreq); + mvBoardCpuFreqModeSet(bios_modes[i].cpuFreqMode); + mvBoardFabFreqSet(bios_modes[i].fabricFreq); + mvBoardFabFreqModeSet(bios_modes[i].fabricFreqMode); + mvBoardCpuCoresNumSet(bios_modes[i].cpuEna); + mvBoardCpu0CoreModeSet(bios_modes[i].cpuMode); + mvBoardConfIdSet(bios_modes[i].confId); + flag = 1; + } + } + if (flag == 0) + printf("BIOS mode is invalid!, please use bios list to see all modes\n"); + + return 0; +usage: + printf("Usage: bios write (see help) \n", argv[0]); + return 1; +} +int do_bios(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "list") == 0) + return do_bios_list(); + if (strcmp(cmd, "write") == 0) { + if (do_bios_write(argc - 2, argv + 2) == 0) + do_bios_read(); + return 0; + } + if (strcmp(cmd, "read") == 0) + return do_bios_read(); + +usage: + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD(bios, 3, 1, do_bios, + "BIOS command to set the DB configuration.\n", + + "list - prints the BIOS modes list\n" + "bios read - read and print the BIOS value\n" + + "bios write - write the BIOS to , see list for all modes\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bubt.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bubt.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_bubt.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_bubt.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,440 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +extern nand_info_t nand_info[]; /* info for NAND chips */ +#endif + +#ifdef CONFIG_CMD_SF +#include +extern struct spi_flash *flash; +#endif + +#if 0 +#if !defined(MV_NAND_BOOT) || !defined(MV_SPI_BOOT) +static unsigned int flash_in_which_sec(flash_info_t *fl,unsigned int offset) +{ + unsigned int sec_num; + if(NULL == fl) + return 0xFFFFFFFF; + + for( sec_num = 0; sec_num < fl->sector_count ; sec_num++){ + /* If last sector*/ + if (sec_num == fl->sector_count -1) + { + if((offset >= fl->start[sec_num]) && + (offset <= (fl->size + fl->start[0] - 1)) ) + { + return sec_num; + } + + } + else + { + if((offset >= fl->start[sec_num]) && + (offset < fl->start[sec_num + 1]) ) + { + return sec_num; + } + + } + } + /* return illegal sector Number */ + return 0xFFFFFFFF; + +} + +#endif /* !defined(CONFIG_NAND_BOOT) */ + +#include "bootstrap_def.h" +#if defined(CONFIG_CMD_NET) +/* + * 8 bit checksum + */ +MV_U8 checksum8(MV_U32 start, MV_U32 len, MV_U8 csum) +{ + register MV_U8 sum = csum; + volatile MV_U8* startp = (volatile MV_U8*)start; + + do { + sum += *startp; + startp++; + } while(--len); + + return (sum); +} /* end of checksum8 */ + +#if 0 +/* + * Check the extended header and execute the image + */ +static MV_U32 verify_extheader(ExtBHR_t *extBHR) +{ + MV_U8 chksum; + + + /* Caclulate abd check the checksum to valid */ + chksum = checksum8((MV_U32)extBHR , EXT_HEADER_SIZE -1, 0); + if (chksum != (*(MV_U8*)((MV_U32)extBHR + EXT_HEADER_SIZE - 1))) + { + printf("Error! invalid extende header checksum\n"); + return MV_FAIL; + } + + return MV_OK; +} +#endif +/* + * Check the CSUM8 on the main header + */ +static MV_U32 verify_main_header(BHR_t *pBHR, MV_U8 headerID) +{ + MV_U8 chksum,chksumtemp; + + /* Verify Checksum */ + chksumtemp = pBHR->checkSum; + pBHR->checkSum = 0; + chksum = checksum8((MV_U32)pBHR, MAIN_HDR_GET_LEN(pBHR), 0); + pBHR->checkSum = chksumtemp; + if (chksum != chksumtemp) + { + printf("\t[Fail] invalid image header checksum\n"); + return MV_FAIL; + } + + /* Verify Header */ + if (pBHR->blockID != headerID) + { + printf("\t[Fail] invalid image header ID\n"); + return MV_FAIL; + } + + /* Verify Alignment */ + if (pBHR->blockSize & 0x3) + { + printf("\t[Fail] invalid image header alignment\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->destinationAddr) & 0x3) && (cpu_to_le32(pBHR->destinationAddr) != 0xffffffff)) + { + printf("\t[Fail] invalid image header destination\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->sourceAddr) & 0x3) && (pBHR->blockID != IBR_HDR_SATA_ID)) + { + printf("\t[Fail] invalid image header source\n"); + return MV_FAIL; + } + + return MV_OK; +} +#endif //0 +#endif //0 + +#if defined(MV_NAND_BOOT) +/* Boot from NAND flash */ +/* Write u-boot image into the nand flash */ +int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + //u_char *load_addr; + load_addr = CONFIG_SYS_LOAD_ADDR; + uint64_t size = CONFIG_ENV_OFFSET; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("Using default filename \"u-boot.bin\" \n"); + } + filesize = NetLoop(TFTP); + printf("Checking file size:"); + if (filesize == -1) + { + printf("\t[Fail]\n"); + return 0; + } + printf("\t[Done]\n"); +#if 0 +#ifdef MV_BOOTROM + printf("Checking header cksum:"); + BHR_t* tmpBHR = (BHR_t*) load_addr; + + /* Verify Main header checksum */ + if (verify_main_header(tmpBHR, IBR_HDR_NAND_ID)) + return 0; + + printf("\t[Done]\n"); +#endif +#endif //0 + printf("Override Env parameters to default? [y/N]"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_RANGE); + nand_erase(nand, CONFIG_ENV_OFFSET, CONFIG_ENV_RANGE); + printf("\t[Done]\n"); + } + + printf("Erasing 0x%x - 0x%x: ", 0, 0 + CONFIG_ENV_OFFSET); + nand_erase(nand, 0, CONFIG_ENV_OFFSET); + printf("\t[Done]\n"); + + printf("Writing image to NAND:"); + ret = nand_write(nand, 0, &size, load_addr); + if (ret) + printf("\t[Fail]\n"); + else + printf("\t[Done]\n"); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nand_burn_uboot_cmd, + "bubt - Burn an image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Nand Flash, default file-name is u-boot.bin .\n" +); +#endif /* defined(CONFIG_NAND_BOOT) */ + +#if defined(MV_SPI_BOOT) +/* Boot from SPI flash */ +/* Write u-boot image into the SPI flash */ +int spi_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + size_t len = CONFIG_SYS_MONITOR_LEN; + load_addr = CONFIG_SYS_LOAD_ADDR; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("Using default filename \"u-boot.bin\" \n"); + } + filesize = NetLoop(TFTP); + printf("Checking file size:"); + if (filesize == -1) + { + printf("\t\t[ERR!]\n"); + return 0; + } + printf("\t\t[Done]\n"); +#if 0 +#ifdef MV_BOOTROM + printf("Checking header cksum:"); + BHR_t* tmpBHR = (BHR_t*) load_addr; + + /* Verify Main header checksum */ + if (verify_main_header(tmpBHR, IBR_HDR_SPI_ID)) + return 0; + + printf("\t[Done]\n"); +#endif +#endif //0 + + printf("Override Env parameters to default? [y/N]"); + readline(" "); +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE); + spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + printf("\t[Done]\n"); + } + + printf("Erasing 0x%x - 0x%x: ",0, 0 + CONFIG_ENV_OFFSET); + spi_flash_erase(flash, 0, CONFIG_ENV_OFFSET); + printf("\t\t[Done]\n"); + + printf("Writing image to flash:"); + ret = spi_flash_write(flash, 0, filesize, load_addr); + + if (ret) + printf("\t\t[Err!]\n"); + else + printf("\t\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, spi_burn_uboot_cmd, + "bubt - Burn an image on the Boot SPI Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot SPI Flash, default file-name is u-boot.bin .\n" +); +#endif + +#if 0 +#ifdef MV_BOOTROM +/* Upgrade BootROM image */ +int spi_burn_bootrom_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 from, to; + ushort sector_count; + ulong sector_size; + extern char console_buffer[]; + + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + printf("Must provide image file name as a parameter.\n"); + return 0; + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + sector_count = flash_info[BOOT_FLASH_INDEX].sector_count; + sector_size = flash_info[BOOT_FLASH_INDEX].size / sector_count; + from = flash_info[BOOT_FLASH_INDEX].start[sector_count - 1]; + to = from + sector_size; + + printf("Un-Protecting 0x%X to 0x%X\n", from, to); + flash_protect (FLAG_PROTECT_CLEAR, from, to, &flash_info[BOOT_FLASH_INDEX]); + + printf("Erasing 0x%X to 0x%X\n", from, to); + flash_erase(&flash_info[BOOT_FLASH_INDEX], (sector_count-1), (sector_count-1)); + + printf("Copy to Flash... "); + + flash_write ( (char *)(CFG_LOAD_ADDR + CFG_MONITOR_IMAGE_OFFSET), from, sector_size); + + printf("done\nProtecting 0x%X to 0x%X\n", from, to); + flash_protect (FLAG_PROTECT_SET, from, to, &flash_info[BOOT_FLASH_INDEX]); + + return 1; +} + +U_BOOT_CMD( + bbrom, 2, 1, spi_burn_bootrom_cmd, + "bbrom - Upgrade the BootROM image on the SPI Flash.\n", + " file-name \n" + "\tBurn a binary BootrOM image on the SPI Flash. Must provide image file name as a parameter.\n" +); +#endif +#endif /*0*/ + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_ENV_IS_IN_NAND) + int ret = 0; + nand_erase_options_t nand_erase_options; + size_t offset = 0; + + +#if defined(CONFIG_SKIP_BAD_BLOCK) + int i = 0; + size_t blocksize; + blocksize = nand_info[0].erasesize; + while(i * blocksize < nand_info[0].size) { + if (!nand_block_isbad(&nand_info[0], offset)) + offset += blocksize; + if (offset >= CONFIG_ENV_OFFSET) + break; + i++; + } +#else + offset = CONFIG_ENV_OFFSET; +#endif + nand_erase_options.length = CONFIG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + nand_erase_options.offset = offset; + + puts ("Erasing Nand:\n"); + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + return 1; + puts ("[Done]\n"); +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + u32 sector = 1; + + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { + sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; + if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) + sector++; + } + + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + sector * CONFIG_ENV_SECT_SIZE); + if (spi_flash_erase(flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) + return 1; + puts("\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + +#endif + printf("Warning: Default Environment Variables will take effect Only after RESET\n"); + return 0; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - earse environment sector to reset all variables to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_ddr.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_ddr.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_ddr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_ddr.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,64 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include "ddr2_3/mvDramIf.h" + +int ddr_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvDdrPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + ddrPhyRead, 3, 3, ddr_phy_read_cmd, + "ddrPhyRead - Read DDR PHY register\n", + " \n" + "\t - register number in the PHY\n" + "\t - PuP number in the PHY\n" + +); + +int ddr_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvDdrPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + ddrPhyWrite, 4, 4, ddr_phy_write_cmd, + "ddrPhyWrite - Write DDR PHY register\n", + " \n" + "\t - register number in the PHY\n" + "\t - PuP number in the PHY\n" + "\t - the new register value to write\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_pcie.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_pcie.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_pcie.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_pcie.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,60 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include "pci-if/mvPciIf.h" + +int pcie_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvPexPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + pciePhyRead, 3, 3, pcie_phy_read_cmd, + "phyRead - Read PCI-E Phy register\n", + " PCI-E_interface Phy_offset. \n" + "\tRead the PCI-E Phy register. \n" +); + +int pcie_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvPexPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + pciePhyWrite, 4, 4, pcie_phy_write_cmd, + "pciePhyWrite - Write PCI-E Phy register\n", + " PCI-E_interface Phy_offset value.\n" + "\tWrite to the PCI-E Phy register.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_resetenv.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_resetenv.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_resetenv.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_resetenv.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "mvCommon.h" +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +extern nand_info_t nand_info[]; /* info for NAND chips */ +#endif + +#ifdef CONFIG_CMD_SF +#include +extern struct spi_flash *flash; +#endif + + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_ENV_IS_IN_NAND) + int ret = 0; + nand_erase_options_t nand_erase_options; + size_t offset = 0; + + +#if defined(CONFIG_SKIP_BAD_BLOCK) + int i = 0; + size_t blocksize; + blocksize = nand_info[0].erasesize; + while(i * blocksize < nand_info[0].size) { + if (!nand_block_isbad(&nand_info[0], offset)) + offset += blocksize; + if (offset >= CONFIG_ENV_OFFSET) + break; + i++; + } +#else + offset = CONFIG_ENV_OFFSET; +#endif + nand_erase_options.length = CONFIG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + nand_erase_options.offset = offset; + + puts ("Erasing Nand:\n"); + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + return 1; + puts ("[Done]\n"); +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + u32 sector = 1; + + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { + sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; + if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) + sector++; + } + + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Unprotecting flash:"); + spi_flash_protect(flash, 0); + printf("\t\t[Done]\n"); +#endif + + printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + sector * CONFIG_ENV_SECT_SIZE); + if (spi_flash_erase(flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) + return 1; + puts("\t[Done]\n"); + +#ifdef CONFIG_SPI_FLASH_PROTECTION + printf("Protecting flash:"); + spi_flash_protect(flash, 1); + printf("\t\t[Done]\n"); +#endif + +#endif + printf("Warning: Default Environment Variables will take effect Only after RESET\n"); + return 0; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - earse environment sector to reset all variables to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_sar.c u-boot-2009.08/board/marvell/mv_armada_xp/cmd_sar.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/cmd_sar.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/cmd_sar.c 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,336 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#if defined(CONFIG_CMD_SAR) +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +extern MV_BIOS_MODE bios_modes[BIOS_MODES_NUM]; + +#define FREQ_MODES_NUM 6 + +typedef struct { + char *name; + MV_U8 cpuFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreq; + MV_U8 fabricFreqMode; +} MV_FREQ_MODE; + +MV_FREQ_MODE freq_modes[FREQ_MODES_NUM] = { +/* Freq Conf CPU Freq CPUFreqMode Fabric Freq FabricFreqMode */ +/* 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] */ + {"800 / 400 Mhz", 0x2, 0x1, 0x1, 0x0}, + {"1066 / 533 Mhz", 0x1, 0x0, 0x1, 0x0}, + {"1200 / 600 Mhz", 0x2, 0x0, 0x5, 0x0}, + {"1333 / 667 Mhz", 0x3, 0x0, 0x5, 0x0}, + {"1600 / 800 Mhz", 0x5, 0x0, 0x5, 0x0}, + {"667 / 667 Mhz", 0x1, 0x1, 0x3, 0x1} +}; + +static int do_sar_list(int argc, char *argv[]) +{ + const char *cmd; + int i; + + if (argc < 1) + goto usage; + cmd = argv[0]; + + if (strcmp(cmd, "cpufreq") == 0) { + + printf("Determines the frequency of CPU:\n"); + printf("\t0x0 = 1000Mhz\n"); + printf("\t0x1 = 1066Mhz\n"); + printf("\t0x2 = 1200Mhz\n"); + printf("\t0x3 = 1333Mhz\n"); + printf("\t0x4 = 1500Mhz\n"); + printf("\t0x5 = 1666Mhz\n"); + printf("\t0x6 = 1800Mhz\n"); + printf("\t0x7 = 2000Mhz\n"); + + } else if (strcmp(cmd, "fabfreq") == 0) { + + printf("Determines the ratios between PCLK0, XPCLK, HCLK and DRAM clock.\n"); + printf("For full deatails about the various options please refer to the clocking section in the HW spec.\n"); + + } else if (strcmp(cmd, "l2size") == 0) { + + printf("Determines the amount of L2 cache:\n"); + printf("\t0x0 = 0.5MB\n"); + printf("\t0x1 = 1MB\n"); + printf("\t0x2 = 0MB\n"); + printf("\t0x3 = 2MB\n"); + + } else if (strcmp(cmd, "bootsrc") == 0) { + + printf("Determines the Boot source device:\n"); + printf("\t0x0 = NOR\n"); + printf("\t0x1 = NAND\n"); + /*printf("\t0x2 = UART\n");*/ + printf("\t0x3 = SPI\n"); + printf("\t0x4 = PCI-E\n"); + printf("\t0x5 = SATA\n"); + /* printf("\t0x6 = NAND (legacy)\n"); + printf("\t0x7 = Debug prompt\n");*/ + + } else if (strcmp(cmd, "bootwidth") == 0) { + + printf("Determines the Boot device width:\n"); + printf("\t0x0 = 8bit\n"); + printf("\t0x1 = 16bit\n"); + printf("\t0x2 = 32bit\n"); + printf("\t0x3 = Reserved\n"); + + } else if (strcmp(cmd, "cpu0core") == 0) { + + printf("Determines the CPU core mode:\n"); + printf("\t0x0 = ARMv6 UP\n"); + printf("\t0x1 = ARMv7 UP\n"); + printf("\t0x2 = ARMv6 MP\n"); + printf("\t0x3 = ARMv7 MP\n"); + + } else if (strcmp(cmd, "cpusnum") == 0) { + + printf("Determines the number of CPU cores:\n"); + printf("\t0x0 = Single CPU\n"); + printf("\t0x1 = Dual CPU\n"); + printf("\t0x2 = Reserved\n"); + printf("\t0x3 = Quad CPU\n"); + + } else if (strcmp(cmd, "freq") == 0) { + printf("val Freq Conf CPU Freq CPUFreqMode Fabric Freq\n"); + printf(" 0x4d/[4:2] 0x4e[0] 0x4e/[4:1]\n"); + for (i=0; i=FREQ_MODES_NUM)) { + printf("invalid mode %d\n", mode); + goto write_fail; + } + + if (mvBoardCpuFreqSet(freq_modes[mode].cpuFreq) != MV_OK) + goto write_fail; + if (mvBoardCpuFreqModeSet(freq_modes[mode].cpuFreqMode) != MV_OK) + goto write_fail; + if (mvBoardFabFreqSet(freq_modes[mode].fabricFreq) != MV_OK) + goto write_fail; + if (mvBoardFabFreqModeSet(freq_modes[mode].fabricFreqMode) != MV_OK) + goto write_fail; + } + + return 0; + +write_fail: + printf("Write S@R failed!\n"); + return 1; + +usage: + printf("Usage: SatR write [options] (see help) \n", argv[0]); + return 1; +} + +int do_sar(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + MV_U8 freq; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "list") == 0) + return do_sar_list(argc - 2, argv + 2); + else if (strcmp(cmd, "write") == 0) { + + if (do_sar_write(argc - 2, argv + 2) == 0) + do_sar_read(argc - 2, argv + 2); + return 0; + + } else if (strcmp(cmd, "read") == 0) + return do_sar_read(argc - 2, argv + 2); + +usage: + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD(SatR, 6, 1, do_sar, + "Sample At Reset sub-system\n", + + "SatR list cpufreq - prints the S@R modes list\n" + "SatR list fabfreq - prints the S@R modes list\n" + "SatR list l2size - prints the S@R modes list\n" + "SatR list bootsrc - prints the S@R modes list\n" + "SatR list bootwidth - prints the S@R modes list\n" + "SatR list cpu0core - prints the S@R modes list\n" + "SatR list cpusnum - prints the S@R modes list\n" + "SatR list freq - prints the S@R modes list\n" + + "SatR read cpufreq - read and print the CPU frequency S@R value\n" + "SatR read fabfreq - read and print the Fabric frequency S@R value\n" + "SatR read l2size - read and print the L2 cache size S@R value\n" + "SatR read bootsrc - read and print the Boot source S@R value\n" + "SatR read bootwidthc - read and print the Boot device width S@R value\n" + "SatR read cpu0core - read and print the CPU0 core mode S@R value\n" + "SatR read cpusnum - read and print the number of CPU cores S@R value\n" + "SatR read freq - read and print the mode of cpu/ddr freq S@R value\n" + + "SatR write cpufreq - write the S@R with CPU frequency value\n" + "SatR write fabfreq - write the S@R with Fabric frequency value\n" + "SatR write l2size - write the S@R with L2 cache size value\n" + "SatR write bootsrc - write the S@R with Boot source value\n" + "SatR write bootwidth - write the S@R with Boot device width value\n" + "SatR write cpu0core - write the S@R with CPU0 core mode value\n" + "SatR write cpusnum - write the S@R with the number of CPU cores\n" + "SatR write freq - write the S@R with the cpu/ddr freq mode\n" + +); +#endif /*defined(CONFIG_CMD_SAR)*/ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCesaConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,45 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCesaConfig.h - Marvell Cesa unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for cesa registers. +*/ +#define OLD_CESA_HAL + +#if defined OLD_CESA_HAL +#warning "Working with old CESA HAL (one channel only!)" +#define MV_CESA_REGS_BASE (MV_CESA_REGS_OFFSET(0)) +#define MV_CESA_TDMA_REGS_BASE (MV_CESA_TDMA_REGS_OFFSET(0)) +#else +#define MV_CESA_TDMA_REGS_BASE(port) (MV_CESA_TDMA_REGS_OFFSET(port)) +#define MV_CESA_REGS_BASE(port) (MV_CESA_REGS_OFFSET(port)) +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysCntmrConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCntmrConfig.h - Marvell Counter Manager unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for counter manager registers. +*/ +#define MV_CNTMR_REGS_BASE (MV_CNTMR_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysDdrConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,43 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysDdrConfig.h - Marvell DRAM controller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for DDR registers. +*/ +#define MV_DDR_REGS_BASE (MV_DRAM_REGS_OFFSET) +#define MV_DDR_WIN_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_DDR_CTRL_REGS_BASE (MV_DRAM_REGS_OFFSET) + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,161 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthConfig.h - Marvell Ethernet unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvSysEthConfig_h__ +#define __mvSysEthConfig_h__ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* u-boot is running in legacy mode! */ +#define MV_ETH_LEGACY +#define MV_LEGACY_ETH_WA +#define CONFIG_MV_ETH_LEGACY + +/* +** Base address for ethernet registers. +*/ +#ifdef CONFIG_MV_PON +#define MV_PON_PORT(p) ((p) == MV_PON_PORT_ID) +#define MV_PON_REG_BASE MV_PON_REGS_OFFSET +#define MV_ETH_REGS_BASE(p) (MV_PON_PORT(p) ? MV_PON_REGS_OFFSET : MV_ETH_REGS_OFFSET(p)) +#else +#define MV_PON_PORT(p) MV_FALSE +#define MV_ETH_REGS_BASE(p) MV_ETH_REGS_OFFSET(p) +#endif /* CONFIG_MV_PON */ + +#define MV_BM_REG_BASE MV_BM_REGS_OFFSET +#define MV_PNC_REG_BASE MV_PNC_REGS_OFFSET +#define MV_ETH_COMPLEX_BASE (MV_ETH_COMPLEX_OFFSET) +#define MV_ETH_ONLY_REGS_BASE (MV_ETH_ONLY_REGS_OFFSET) + +#if defined(CONFIG_MV_INCLUDE_GIG_ETH) + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* port's default queueus */ +#define ETH_DEF_RXQ 0 + +#ifdef MV_ETH_LEGACY + +#ifdef MV_NFP_STATS +#define MV_FP_STATISTICS +#else +#undef MV_FP_STATISTICS +#endif + +/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ +#define MV_ETH_TX_EN_DEFAULT 0 + +/* un-comment if you want to perform tx_done from within the poll function */ +/* #define ETH_TX_DONE_ISR */ + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* Descriptors location: DRAM/internal-SRAM */ +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ + +#if defined(ETH_DESCR_IN_SRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" +#endif +#elif defined(ETH_DESCR_IN_SDRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" +#endif +#else + #error "Ethernet descriptors location undefined" +#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ + +/* SW Sync-Barrier: not relevant for 88fxx81*/ +/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ +/* In RX the CPU theoretically might see himself as the descriptor owner, */ +/* although the buffer hadn't been written to DRAM yet. Performance cost. */ +/* #define INCLUDE_SYNC_BARR */ + +/* Buffers cache coherency method (buffers in DRAM) */ +#ifndef MV_CACHE_COHER_SW +/* Taken from mvCommon.h */ +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +#endif + +#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) + #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "DRAM uncached" +#else + #error "Ethernet-DRAM undefined" +#endif /* ETHER_DRAM_COHER */ + + +/****************************************************************/ +/************* Ethernet driver configuration ********************/ +/****************************************************************/ + +/* port's default queueus */ +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 + +#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RXQ +#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TXQ + +/* interrupt coalescing setting */ +#define ETH_TX_COAL 200 +#define ETH_RX_COAL 200 + +/* Checksum offloading */ +#define TX_CSUM_OFFLOAD +#define RX_CSUM_OFFLOAD +#endif /* CONFIG_MV_ETH_LEGACY */ + +#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ + +#endif /* __mvSysEthConfig_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysEthPhyConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,32 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthPhyConfig.h - Marvell Ethernet-PHY specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysGppConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysGppConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysGppConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysGppConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysGppConfig.h - Marvell GPP unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for GPP registers. +*/ +#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) +#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysHwConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysHwConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysHwConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysHwConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,455 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + +#include + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#undef MV_MEM_OVER_PEX_WA + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_GIG_ETH +//#define MV_INCLUDE_CESA +#define OLD_CESA_HAL +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI +#define MV_INCLUDE_TDM +#define MV_INCLUDE_XOR +#define MV_INCLUDE_SATA +//#define MV_INCLUDE_TS +//#define MV_INCLUDE_AUDIO +#define MV_INCLUDE_SDIO +#define MV_INCLUDE_RTC +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_CLK_PWR_CNTRL + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/************************************************/ +/* U-Boot Specific */ +/************************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#endif + + +/************************************************/ +/* RD boards specifics */ +/************************************************/ + +#undef MV_INC_BOARD_DDIM + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif + +#if defined(RD_88F6281) +#define MV_INC_BOARD_QD_SWITCH +#endif + +#if defined(RD_88F6180) +#define MV_INC_BOARD_QD_SWITCH +#endif +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX 0.0 */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xe0000000 +#define PEX0_IO_SIZE _16M + +/* PEX 0.1 */ +#define PEX1_MEM_BASE 0x98000000 +#define PEX1_MEM_SIZE _128M + +#define PEX1_IO_BASE 0xe1000000 +#define PEX1_IO_SIZE _16M + +/* PEX 0.2 */ +#define PEX2_MEM_BASE 0xa0000000 +#define PEX2_MEM_SIZE _128M + +#define PEX2_IO_BASE 0xe2000000 +#define PEX2_IO_SIZE _16M + +/* PEX 0.3 */ +#define PEX3_MEM_BASE 0xa8000000 +#define PEX3_MEM_SIZE _128M + +#define PEX3_IO_BASE 0xe3000000 +#define PEX3_IO_SIZE _16M + +/* PEX 1.0 */ +#define PEX4_MEM_BASE 0xb0000000 +#define PEX4_MEM_SIZE _128M + +#define PEX4_IO_BASE 0xe4000000 +#define PEX4_IO_SIZE _16M + +/* PEX 1.1 */ +/* TODO: alior: still need to work on this PEX interface */ +#define PEX5_MEM_BASE 0xFFFFFFFF +#define PEX5_MEM_SIZE _128M + +#define PEX5_IO_BASE 0xe5000000 +#define PEX5_IO_SIZE _16M + +/* PEX 1.2 */ +#define PEX6_MEM_BASE 0xb8000000 +#define PEX6_MEM_SIZE _128M + +#define PEX6_IO_BASE 0xe6000000 +#define PEX6_IO_SIZE _16M + +/* PEX 1.3 */ +/* TODO: alior: still need to work on this PEX interface */ +#define PEX7_MEM_BASE 0xFFFFFFFF +#define PEX7_MEM_SIZE _128M + +#define PEX7_IO_BASE 0xe7000000 +#define PEX7_IO_SIZE _16M + +/* PEX 2 */ +#define PEX8_MEM_BASE 0xc0000000 +#define PEX8_MEM_SIZE _128M + +#define PEX8_IO_BASE 0xe8000000 +#define PEX8_IO_SIZE _16M + +/* PEX 3 */ +#define PEX9_MEM_BASE 0xd8000000 +#define PEX9_MEM_SIZE _128M + +#define PEX9_IO_BASE 0xe9000000 +#define PEX9_IO_SIZE _16M + +/* Device: CS0 - NAND, CS1 - SPI, CS2 - Boot ROM, CS3 - Boot device */ +/* Internal registers: size is defined in Controllerenvironment */ + +//#define INTER_REGS_BASE 0xF1000000 +#define INTER_REGS_BASE 0xD0000000 +#define ARMADAXP_SB_REGS_PHYS_BASE INTER_REGS_BASE + +#define DEVICE_CS0_BASE NFLASH_CS_BASE +#define DEVICE_CS0_SIZE NFLASH_CS_SIZE + +#define DEVICE_CS2_BASE 0xf2000000 /* 0xf4000000 */ +#define DEVICE_CS2_SIZE _1M + +#define PNC_BM_PHYS_BASE 0xf2100000 /*0xF5000000*/ +#define PNC_BM_SIZE _1M + +#define CRYPT_ENG_BASE 0xc8010000 +//fb300000 /*0xFB000000*/ +#define CRYPT_ENG_SIZE _64K + +#define SPI_CS_BASE 0xf4000000 /*0xf8000000*/ +#define SPI_CS_SIZE _16M + +#define DEVICE_CS1_BASE SPI_CS_BASE +#define DEVICE_CS1_SIZE _16M + + +#define NFLASH_CS_BASE 0xfd000000 /* not relevant for the new controller */ +#define NFLASH_CS_SIZE _2M + +#define NOR_CS_BASE 0xf8000000 /*0x80000000*/ +#define NOR_CS_SIZE _128M + + + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +#if !defined(MV_BOOTROM) && defined(MV_NAND_BOOT) +#define CONFIG_SYS_NAND_BASE BOOTDEV_CS_BASE +#else +#define CONFIG_SYS_NAND_BASE DEVICE_CS0_BASE +#endif + + + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE +#endif + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ +#define L2CLK_AUTO_DETECT /* Use L2 Clk auto detection */ + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" +#endif /* ETHER_DRAM_COHER */ + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ + /* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE, 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS0 */ \ + {{SDRAM_CS1_BASE, 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS1 */ \ + {{SDRAM_CS2_BASE, 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS2 */ \ + {{SDRAM_CS3_BASE, 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS3 */ \ + {{NOR_CS_BASE, 0, NOR_CS_SIZE }, TBL_UNUSED, DIS}, /* DEVICE_CS0 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS1 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS2 */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEVICE_CS3 */\ + {{PEX0_MEM_BASE, 0, PEX0_MEM_SIZE }, 0, EN}, /* PEX0_MEM */ \ + {{PEX0_IO_BASE, 0, PEX0_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX0_IO */ \ + {{PEX1_MEM_BASE, 0, PEX1_MEM_SIZE }, 1, EN}, /* PEX1_MEM */ \ + {{PEX1_IO_BASE, 0, PEX1_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX1_IO */ \ + {{PEX2_MEM_BASE, 0, PEX2_MEM_SIZE }, 2, EN}, /* PEX2_MEM */ \ + {{PEX2_IO_BASE, 0, PEX2_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX2_IO */ \ + {{PEX3_MEM_BASE, 0, PEX3_MEM_SIZE }, 3, EN}, /* PEX3_MEM */ \ + {{PEX3_IO_BASE, 0, PEX3_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX3_IO */ \ + {{PEX4_MEM_BASE, 0, PEX4_MEM_SIZE }, 4, EN}, /* PEX4_MEM */ \ + {{PEX4_IO_BASE, 0, PEX4_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX4_IO */ \ + {{PEX5_MEM_BASE, 0, PEX5_MEM_SIZE }, TBL_UNUSED, DIS}, /* PEX5_MEM */ \ + {{PEX5_IO_BASE, 0, PEX5_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX5_IO */ \ + {{PEX6_MEM_BASE, 0, PEX6_MEM_SIZE }, 5, EN}, /* PEX6_MEM */ \ + {{PEX6_IO_BASE, 0, PEX6_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX6_IO */ \ + {{PEX7_MEM_BASE, 0, PEX7_MEM_SIZE }, TBL_UNUSED, DIS}, /* PEX7_MEM */ \ + {{PEX7_IO_BASE, 0, PEX7_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX7_IO */ \ + {{PEX8_MEM_BASE, 0, PEX8_MEM_SIZE }, 6, EN}, /* PEX8_MEM */ \ + {{PEX8_IO_BASE, 0, PEX8_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX8_IO */ \ + {{PEX9_MEM_BASE, 0, PEX9_MEM_SIZE }, 7, EN}, /* PEX9_MEM */ \ + {{PEX9_IO_BASE, 0, PEX9_IO_SIZE }, TBL_UNUSED, DIS}, /* PEX9_IO */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, MV_AHB_TO_MBUS_INTREG_WIN, EN}, /* INTER_REGS */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DMA_UART */\ + {{SPI_CS_BASE, 0, SPI_CS_SIZE }, 8, EN}, /* SPI_CS0 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS1 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS2 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS3 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS4 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS5 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS6 */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* SPI_CS7 */ \ + {{0xf8000000, 0, _1M }, 13, EN}, /* BOOT_ROM_CS */\ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* DEV_BOOCS */ \ + {{TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS}, /* PMU_SCRATCHPAD */ \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE }, 9, EN}, /* CRYPT_ENG */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM }, TBL_TERM, TBL_TERM} \ +}; +#if 0 +{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE }, 0x4, DIS}, /* DEV_BOOCS */ +{{PNC_BM_PHYS_BASE, 0, PNC_BM_SIZE }, 3, DIS}, /* PNC_BM */ */ +#endif + +#define MV_CACHEABLE(address) ((address) | 0x80000000) + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + + +#if defined(MV_BOOTSIZE_256K) + +#define BOOTDEV_CS_SIZE _256K + +#elif defined(MV_BOOTSIZE_512K) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_4M) + +#define BOOTDEV_CS_SIZE _4M + +#elif defined(MV_BOOTSIZE_8M) + +#define BOOTDEV_CS_SIZE _8M + +#elif defined(MV_BOOTSIZE_16M) + +#define BOOTDEV_CS_SIZE _16M + +#elif defined(MV_BOOTSIZE_32M) + +#define BOOTDEV_CS_SIZE _32M + +#elif defined(MV_BOOTSIZE_64M) + +#define BOOTDEV_CS_SIZE _64M + +#elif defined(MV_NAND_BOOT) + +#define BOOTDEV_CS_SIZE _512K + +#else + +#define Error MV_BOOTSIZE undefined + +#endif + +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x30820 /* sdram config */ +#define DRAM_BUF_REG2 0x30830 /* sdram mode */ +#define DRAM_BUF_REG3 0x60bb0 /* dunit control low */ +#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ +#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ +#define DRAM_BUF_REG12 0x60bb4 /* sdram Ddr2 Time High Reg */ +#define DRAM_BUF_REG13 0x60ab0 /* dunit Ctrl High */ +#define DRAM_BUF_REG14 0x60ab4 /* sdram second DIMM exist */ + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG_DV 0 + +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 +#define MV_ETH_TX_Q_NUM 1 +#define MV_ETH_RX_Q_NUM 1 +#define ETH_NUM_OF_RX_DESCR 64 +#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2 + +#define MV_CESA_MAX_BUF_SIZE 1600 + +#endif /* __INCmvSysHwConfigh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysNfcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysNfcConfig.h - Marvell NAND flash conroller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Nand Controller registers. +*/ +#define MV_NFC_REGS_BASE (MV_NFC_REGS_OFFSET + INTER_REGS_BASE) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPciIfConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,68 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysPciIfConfig.h - Marvell PCI / Pex units specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE +#endif + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPexConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPexConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysPexConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysPexConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,68 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysPciIfConfig.h - Marvell PCI / Pex units specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE +#endif + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysRtcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysRtcConfig.h - Marvell Real-Time clock unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for RTC registers. +*/ +#define MV_RTC_REGS_BASE (MV_RTC_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSataConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSataConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSataConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSataConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSataConfig.h - Marvell Sata unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SATA_REGS_BASE (MV_SATA_REGS_OFFSET) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSdmmcConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSdmmcConfig.h - Marvell SDMMC unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for audio registers. +*/ +#define MV_SDMMC_REGS_BASE (MV_SDMMC_REGS_OFFSET) + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysSpiConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSpiConfig.h - Marvell SPI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SPI_REGS_BASE(unit) (MV_SPI_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTdmConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTdmConfig.h - Marvell TDM unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvOs.h" + +/****************************************************************/ +/*************** Telephony configuration ************************/ +/****************************************************************/ +/* U-Boot support*/ +#define MV_TDM_SUPPORT +//undef MV_TDM_SUPPORT for 32ch unit support (COMM unit) +#if defined(CONFIG_MV_TDM_SUPPORT) + #define MV_TDM_SUPPORT + #define MV_TDM_REGS_BASE MV_TDM_REGS_OFFSET +#elif defined(CONFIG_MV_COMM_UNIT_SUPPORT) + #define MV_COMM_UNIT_SUPPORT + #define MV_COMM_UNIT_REGS_BASE MV_COMM_UNIT_REGS_OFFSET +#endif + +/* SLIC vendor */ +#if defined(CONFIG_SILABS_SLIC_SUPPORT) + #define SILABS_SLIC_SUPPORT + #if defined(CONFIG_SILABS_SLIC_3215) + #define SILABS_SLIC_3215 + #elif defined(CONFIG_SILABS_SLIC_3217) + #define SILABS_SLIC_3217 + #endif +#elif defined(CONFIG_ZARLINK_SLIC_SUPPORT) + #define ZARLINK_SLIC_SUPPORT + #if defined(CONFIG_ZARLINK_SLIC_VE880) + #define ZARLINK_SLIC_VE880 + #define SLIC_TIMER_EVENT_SUPPORT + #elif defined(CONFIG_ZARLINK_SLIC_VE792) + #define ZARLINK_SLIC_VE792 + #endif +#else + #define SILABS_SLIC_3215_OLD_SUPPORT +#endif + +#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) + #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTsConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTsConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTsConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTsConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,39 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTsConfig.h - Marvell TS unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for TS registers. +*/ +#define MV_TSU_GLOBAL_REGS_BASE (MV_TSU_GLOBAL_REGS_OFFSET) +#define MV_TSU_REGS_BASE(port) (MV_TSU_REGS_OFFSET(port)) + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysTwsiConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,41 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTwsiConfig.h - Marvell TWSI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +/* +** Base address for TWSI registers. +*/ +#define MV_TWSI_SLAVE_REGS_BASE(unit) (MV_TWSI_SLAVE_REGS_OFFSET(unit)) + +/* +** Specific definition for Main CPU interrupt cause register. +** Needed for TWSI operation completion monitoring. +*/ +#define MV_TWSI_CPU_MAIN_INT_CASUE(chNum) TWSI_CPU_MAIN_INT_CAUSE_REG diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysUsbConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysUsbConfig.h - Marvell USB unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for USB registers. +*/ +#define MV_USB_REGS_BASE(unit) (MV_USB_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysXorConfig.h u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysXorConfig.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/config/mvSysXorConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/config/mvSysXorConfig.h 2011-04-04 13:57:34.915600366 -0400 @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysXorConfig.h - Marvell XOR unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for XOR registers. +*/ +#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_cmd.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_cmd.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_cmd.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_cmd.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,2235 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#if defined(MV_INC_BOARD_NOR_FLASH) +#include "norflash/mvFlash.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#include "eth-phy/mvEthPhy.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +#if defined(MV_INCLUDE_PDMA) +#include "pdma/mvPdma.h" +#include "mvSysPdmaApi.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXorRegs.h" +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_PMU) +#include "pmu/mvPmuRegs.h" +#endif + +#include "cntmr/mvCntmrRegs.h" + +#if defined(CONFIG_CMD_BSP) + +/****************************************************************************** +* Category - General +* Functionality- The commands allows the user to view the contents of the MV +* internal registers and modify them. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int ir_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_U32 regNum = 0x0, regVal, regValTmp, res; + MV_8 regValBin[40]; + MV_8 cmd[40]; + int i,j = 0, flagm = 0; + extern MV_8 console_buffer[]; + + if( argc == 2 ) { + regNum = simple_strtoul( argv[1], NULL, 16 ); + } + else { + printf( "Usage:\n%s\n", cmdtp->usage ); + return 0; + } + + regVal = MV_REG_READ( regNum + INTER_REGS_BASE); + regValTmp = regVal; + printf( "Internal register 0x%x value : 0x%x\n ",regNum, regVal ); + printf( "\n 31 24 16 8 0" ); + printf( "\n | | | | |\nOLD: " ); + + for( i = 31 ; i >= 0 ; i-- ) { + if( regValTmp > 0 ) { + res = regValTmp % 2; + regValTmp = (regValTmp - res) / 2; + if( res == 0 ) + regValBin[i] = '0'; + else + regValBin[i] = '1'; + } + else + regValBin[i] = '0'; + } + + for( i = 0 ; i < 32 ; i++ ) { + printf( "%c", regValBin[i] ); + if( (((i+1) % 4) == 0) && (i > 1) && (i < 31) ) + printf( "-" ); + } + + readline( "\nNEW: " ); + strcpy(cmd, console_buffer); + if( (cmd[0] == '0') && (cmd[1] == 'x') ) { + regVal = simple_strtoul( cmd, NULL, 16 ); + flagm=1; + } + else { + for( i = 0 ; i < 40 ; i++ ) { + if(cmd[i] == '\0') + break; + if( i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34 ) + continue; + if( cmd[i] == '1' ) { + regVal = regVal | (0x80000000 >> j); + flagm = 1; + } + else if( cmd[i] == '0' ) { + regVal = regVal & (~(0x80000000 >> j)); + flagm = 1; + } + j++; + } + } + + if( flagm == 1 ) { + MV_REG_WRITE( regNum + INTER_REGS_BASE, regVal ); + printf( "\nNew value = 0x%x\n\n", MV_REG_READ(regNum + + INTER_REGS_BASE) ); + } + return 1; +} + +U_BOOT_CMD( + ir, 2, 1, ir_cmd, + "ir - reading and changing MV internal register values.\n", + " address\n" + "\tDisplays the contents of the internal register in 2 forms, hex and binary.\n" + "\tIt's possible to change the value by writing a hex value beginning with \n" + "\t0x or by writing 0 or 1 in the required place. \n" + "\tPressing enter without any value keeps the value unchanged.\n" +); + +#if defined(MV_INCLUDE_PMU) +/****************************************************************************** +* Category - General +* Functionality- Display temperature from sensor. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int temperature_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 reg = 0, reg1 = 0; + MV_U32 value = 0; + int i = 0; + + /* Verify that the temperature is valid */ + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL1_REG); + if ((reg & PMU_TDC1_TEMP_VLID_MASK) == 0x0) + { + printf("Error reading temperature\n"); + } + else + { + for (i = 0; i < 16; i++) + { + /* Read the thermal sensor looking for two successive readings that differ in LSB only */ + reg = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg = ((reg >> 1) & 0x1FF); + value = ((2281638 - (7298*reg)) / 10000); + if (((reg ^ reg1) & 0x1FE) == 0x0) + break; + + /* save the current reading for the next iteration */ + reg1 = reg; + } + if (i == 16) + printf("Thermal sensor is unstable: could not get two identical successive readings\n"); + else + printf("Junction Temprature (Tj) = %d, Register Value = 0x%08X\n", value, reg); + } + return 1; +} + +U_BOOT_CMD( + temp, 1, 1, temperature_cmd, + "temp - Display the device temprature.\n", + " \n" + "\tDisplay the device temprature as read from the internal sensor.\n" +); +/****************************************************************************** +* Category - General +* Functionality- Display temperature from sensor. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int volt_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 reg = 0, reg1 = 0; + MV_U32 value = 0; + int i = 0; + char *cmd, *s; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strncmp(cmd, "cpu", 3) != 0 && strncmp(cmd, "core", 4) != 0) + goto usage; + + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg |= PMU_TDC0_SEL_IP_MODE_MASK; + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, PMU_TDC0_SEL_IP_MODE_MASK); + + if (strncmp(cmd, "cpu", 3) == 0) { + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg &= ~(PMU_TDC0_SEL_VSEN_MASK); + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, reg); + } + if (strncmp(cmd, "core", 3) == 0) { + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL0_REG); + reg |= PMU_TDC0_SEL_VSEN_MASK; + MV_REG_WRITE(PMU_TEMP_DIOD_CTRL0_REG, reg); + } + udelay(1000); + /* Verify that the temperature is valid */ + reg = MV_REG_READ(PMU_TEMP_DIOD_CTRL1_REG); + if ((reg & PMU_TDC1_TEMP_VLID_MASK) == 0x0) + { + printf("Error reading voltage\n"); + } + else + { + reg1 = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg1 = ((reg1 >> 1) & 0x1FF); + for (i = 0; i < 16; i++) + { + /* Read the thermal sensor looking for two successive readings that differ in LSB only */ + reg = MV_REG_READ(PMU_THERMAL_MNGR_REG); + reg = ((reg >> 1) & 0x1FF); + if (((reg ^ reg1) & 0x1FE) == 0x0) + break; + /* save the current reading for the next iteration */ + reg1 = reg; + } + value = ((reg + 241)*10000/39619); + if (i == 16) + printf("Voltage sensor is unstable: could not get two identical successive readings\n"); + else + printf("Voltage (V) = %d.%d, Register Value = 0x%08X\n", value/100, value%100, reg); + } + return 0; +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + volt, 2, 1, volt_cmd, + "volt - Display the cpu / core voltage.\n", + "volt cpu - display the cpu voltage\n" + "volt core - display the core voltage\n" +); +#endif /* #if defined(MV_INCLUDE_PMU) */ + +/****************************************************************************** +* Functional only when using Lauterbach to load image into DRAM +* Category - DEBUG +* Functionality- Display the array of registers the u-boot write to. +* +*****************************************************************************/ +#if defined(REG_DEBUG) +int reg_arry[4096][2]; +int reg_arry_index = 0; +int print_registers( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + printf("Register display\n"); + + for (i=0; i < reg_arry_index; i++) + printf("Reg no %d addr 0x%x = 0x%08x\n", i, reg_arry[i][0], reg_arry[i][1]); + + return 1; +} + +U_BOOT_CMD( + printreg, 1, 1, print_registers, + "printreg - Display the register array the u-boot write to.\n", + " \n" + "\tDisplay the register array the u-boot write to.\n" +); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int sg_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 port; + for( port = 0 ; port < mvCtrlEthMaxPortGet(); port++ ) { + + printf( "PHY %d :\n", port ); + printf( "---------\n" ); + + mvEthPhyPrintStatus( mvBoardPhyAddrGet(port) ); + + printf("\n"); + } + return 1; +} + +U_BOOT_CMD( + sg, 1, 1, sg_cmd, + "sg - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif /* #if defined(MV_INCLUDE_GIG_ETH) */ + +#if defined(MV_INCLUDE_PDMA) + +/****************************************************************************** +* Category - PDMA +* Functionality- Perform a PDMA transaction +* Need modifications (Yes/No) - No +*****************************************************************************/ +int mvPdma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20]; + extern MV_8 console_buffer[]; + MV_U32 src, dst, byteCount; + MV_PDMA_CHANNEL chan; + + /* get PDMA channel */ + + /* source address */ + while(1) { + readline( "Source Address: " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if( src == 0xffffffff ) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Destination Address: " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if( dst == 0xffffffff ) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to 8KByte (0 - 0x1FFF)): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount >= 0x2000) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + if (mvPdmaChanAlloc(MV_PDMA_MEMORY, 0, &chan) != MV_OK) { + printf("Error allocating PDMA channel\n"); + return 0; + } + /* wait for previous transfer completion */ + while(mvPdmaChannelStateGet(&chan) == MV_PDMA_CHANNEL_RUNNING); + /* issue the transfer */ + if (mvPdmaChanTransfer(&chan, MV_PDMA_MEM_TO_MEM, src, dst, byteCount, 0) != MV_OK) { + printf("Error with PDMA transfer\n"); + } + /* wait for completion */ + while(mvPdmaChannelStateGet(&chan) == MV_PDMA_CHANNEL_RUNNING); + if (mvPdmaChanFree(&chan) != MV_OK) { + printf("Error freeing PDMA channel\n"); + return 0; + } + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + pdma, 1, 1, mvPdma_cmd, + "pdma - Perform PDMA\n", + " \n" + "\tPerform PDMA memory to memory transaction with the parameters given by the user.\n" +); + +#endif /* #if defined(MV_INCLUDE_PDMA) */ + +#if defined(MV_INCLUDE_XOR) + +/****************************************************************************** +* Category - DMA +* Functionality- Perform a DMA transaction using the XOR engine +* Need modifications (Yes/No) - No +*****************************************************************************/ +#define XOR_TIMEOUT 0x8000000 + +struct xor_channel_t +{ + MV_CRC_DMA_DESC *pDescriptor; + MV_ULONG descPhyAddr; +}; + +#define XOR_CAUSE_DONE_MASK(chan) ((BIT0|BIT1) << (chan * 16) ) +void xor_waiton_eng(int chan) +{ + int timeout = 0; + + while(!(MV_REG_READ(XOR_CAUSE_REG(XOR_UNIT(chan))) & XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) + { + if(timeout > XOR_TIMEOUT) + goto timeout; + timeout++; + } + + timeout = 0; + while(mvXorStateGet(chan) != MV_IDLE) + { + if(timeout > XOR_TIMEOUT) + goto timeout; + timeout++; + } + /* Clear int */ + MV_REG_WRITE(XOR_CAUSE_REG(XOR_UNIT(chan)), ~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))); + +timeout: + if(timeout > XOR_TIMEOUT) + { + printf("ERR: XOR eng got timedout!!\n"); + } + return; +} +#if 0 +int mvDma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20]; + extern MV_8 console_buffer[]; + MV_U32 chan, src, dst, byteCount; + struct xor_channel_t channel; + MV_U8 *pVirt = (MV_U8*)mvOsIoUncachedAlignedMalloc(NULL, 32, sizeof(MV_XOR_DESC), + &(channel.descPhyAddr), NULL); + + chan = 0; + + /* source address */ + while(1) { + readline( "Physical Source Address (must be cache-line aligned): " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if ((src == 0xffffffff) || (src & 0x1F)) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Physical Destination Address (must be cache-line aligned): " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if ((dst == 0xffffffff) || (dst & 0x1F)) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to (16M-1), must be a multiple of the cache-line): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount > 0xffffff) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + /* wait for previous transfer completion */ + while (mvXorStateGet(chan) != MV_IDLE); + + /* build the channel descriptor */ + channel.pDescriptor = (MV_CRC_DMA_DESC *)pVirt; + channel.pDescriptor->srcAdd0 = src; + channel.pDescriptor->srcAdd1 = 0; + channel.pDescriptor->destAdd = dst; + channel.pDescriptor->byteCnt = byteCount; + channel.pDescriptor->nextDescPtr = 0; + channel.pDescriptor->status = BIT31; + channel.pDescriptor->descCommand = 0x0; + + /* issue the transfer */ + if (mvXorTransfer(chan, MV_DMA, channel.descPhyAddr) != MV_OK) + printf("Error in DMA(XOR) Operation\n"); + + /* wait for completion */ + xor_waiton_eng(chan); + + mvOsIoUncachedAlignedFree(NULL, sizeof(MV_XOR_DESC), channel.descPhyAddr, pVirt, 0); + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + dma, 1, 1, mvDma_cmd, + "dma - Perform DMA using the XOR engine\n", + " \n" + "\tPerform DMA transaction with the parameters given by the user.\n" +); +#endif +#endif /* #if defined(MV_INCLUDE_XOR) */ + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the MV's Memory map +* Need modifications (Yes/No) - Yes +*****************************************************************************/ +int displayMemoryMap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvCtrlAddrDecShow(); + return 1; +} + +U_BOOT_CMD( + map, 1, 1, displayMemoryMap_cmd, + "map - Diasplay address decode windows\n", + " \n" + "\tDisplay controller address decode windows: CPU, PCI, Gig, DMA, XOR and COMM\n" +); + + + +#include "ddr2/spd/mvSpd.h" +#if defined(MV_INC_BOARD_DDIM) + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the SPD information for a givven dimm +* Need modifications (Yes/No) - +*****************************************************************************/ + +int dimminfo_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int num = 0; + + if (argc > 1) { + num = simple_strtoul (argv[1], NULL, 10); + } + + printf("*********************** DIMM%d *****************************\n",num); + + dimmSpdPrint(num); + + printf("************************************************************\n"); + + return 1; +} + +U_BOOT_CMD( + ddimm, 2, 1, dimminfo_cmd, + "ddimm - Display SPD Dimm Info\n", + " [0/1]\n" + "\tDisplay Dimm 0/1 SPD information.\n" +); + +/****************************************************************************** +* Category - Memory +* Functionality- Copy the SPD information of dimm 0 to dimm 1 +* Need modifications (Yes/No) - +*****************************************************************************/ + +int spdcpy_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + printf("Copy DIMM 0 SPD data into DIMM 1 SPD..."); + + if (MV_OK != dimmSpdCpy()) + printf("\nDIMM SPD copy fail!\n"); + else + printf("Done\n"); + + return 1; +} + +U_BOOT_CMD( + spdcpy, 2, 1, spdcpy_cmd, + "spdcpy - Copy Dimm 0 SPD to Dimm 1 SPD \n", + "" + "" +); +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +/****************************************************************************** +* Functionality- Go to an address and execute the code there and return, +* defualt address is 0x40004 +*****************************************************************************/ +extern void cpu_dcache_flush_all(void); +extern void cpu_icache_flush_invalidate_all(void); + +void mv_go(unsigned long addr,int argc, char *argv[]) +{ + int rc; + addr = MV_CACHEABLE(addr); + char* envCacheMode = getenv("cacheMode"); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + } + else /*"write-back"*/ + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + /* Flush invalidate D-cache */ + cpu_dcache_flush_all(); + + + } + + + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + + return; +} + +int g_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0; + } + + addr = 0x40000; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + mv_go(addr,argc,&argv[0]); + return 1; +} + +U_BOOT_CMD( + g, CONFIG_SYS_MAXARGS, 1, g_cmd, + "g - start application at cached address 'addr'(default addr 0x40000)\n", + " addr [arg ...] \n" + "\tStart application at address 'addr' cachable!!!(default addr 0x40004/0x240004)\n" + "\tpassing 'arg' as arguments\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Searches for a value +*****************************************************************************/ +int fi_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData == value) + { + printf("Value: %x found at ",value); + printf("address: %x\n",i); + return 1; + } + } + printf("Value not found!!\n"); + return 1; +} + +U_BOOT_CMD( + fi, 4, 1, fi_cmd, + "fi - Find value in the memory.\n", + " value start_address end_address\n" + "\tSearch for a value 'value' in the memory from address 'start_address to\n" + "\taddress 'end_address'.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Compare the memory with Value. +*****************************************************************************/ +int cmpm_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData != value) + { + printf("Value: %x found at address: %x\n",tempData,i); + } + } + return 1; +} + +U_BOOT_CMD( + cmpm, 4, 1, cmpm_cmd, + "cmpm - Compare Memory\n", + " value start_address end_address.\n" + "\tCompare the memory from address 'start_address to address 'end_address'.\n" + "\twith value 'value'\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + + +#if 0 +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int eth_show_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ethRegs(argv[1]); + ethPortRegs(argv[1]); + ethPortStatus(argv[1]); + ethPortQueues(argv[1],0,0,1); + return 1; +} + +U_BOOT_CMD( + ethShow, 2, 2, eth_show_cmd, + "ethShow - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) + +#include "eth-phy/mvEthPhy.h" + +int phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + phyRead, 3, 3, phy_read_cmd, + "phyRead - Read Phy register\n", + " Phy_address Phy_offset. \n" + "\tRead the Phy register. \n" +); + + +int phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + phyWrite, 4, 4, phy_write_cmd, + "phyWrite - Write Phy register\n", + " Phy_address Phy_offset value.\n" + "\tWrite to the Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_GIG_ETH) */ + +#endif /* MV_TINY */ + +#if 0 +#if defined(CONFIG_CMD_RCVR) +extern void recoveryHandle(void); +int do_rcvr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + recoveryHandle(); + return 1; +} + +U_BOOT_CMD( + rcvr, 3, 1, do_rcvr, + "rcvr\t- Satrt recovery process (Distress Beacon with TFTP server)\n", + "\n" +); +#endif /* CFG_CMD_RCVR */ +#endif //0 +#if 0 +#include "nfc/mvNfc.h" +#include "mvSysPdmaApi.h" + +int mvNfcEWaitEvent(MV_NFC_CTRL * ctrl, MV_NFC_CMD_TYPE cmd, MV_U32 event, MV_U32 err) +{ + int i; + MV_U32 stat; + + for (i=0; i<10; i++) + { + stat = mvNfcStatusGet(ctrl, cmd, NULL); + //printf("Status = 0x%x, NDCR = %08x\n", stat, MV_REG_READ(0xc0000)); + if (stat & err) + { + printf("mvNfcEWaitEvent Error (%08x)\n", stat); + return -1; + } + if (stat & event) + return 0; + mvOsDelay(10); /*wait 10 ms */ + } + + printf("mvNfcEWaitEvent: Timeout\n"); + return -2; +} + +void mvNfcDataPrint(MV_U32 buff) +{ + MV_U8 * datptr; + MV_U32 i,j; + + datptr = (MV_U8*)buff; + for (i=0; i<128; i+=1) + { + printf("%08x: ", (i*16)); + for (j=0; j<16; j++) + { + printf("%02x ", *datptr); + datptr++; + } + printf("\n"); + } +} + +int mvNfcStatusRead(MV_NFC_CTRL * ctrl, MV_U32 * buff) +{ + if (mvNfcSelectChip(ctrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(ctrl, MV_NFC_CMD_READ_STATUS, 0, 0) != MV_OK) + { + printf("Read status command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(ctrl, MV_NFC_CMD_READ_STATUS, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcReadWrite(ctrl, MV_NFC_CMD_READ_STATUS, buff, (MV_U32)buff) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + if (mvNfcSelectChip(ctrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + return 0; +} + + +MV_U32 mvNfcDbgFlag = 0; +MV_U32 mvNfcPrintFlag = 0; +extern MV_NFC_CTRL * gDbgCtrl; +MV_NFC_CTRL nfcDbgCtrl; + +int mvNfc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 buff[1088]; + char *cmd; + cmd = argv[2]; + + if (strcmp(cmd, "help") == 0) + { + printf("nand dbg enable -> enable register read write log\n"); + printf("nand dbg disable -> disable register read write log\n"); + printf("nand dbg print -> enable read data print\n"); + printf("nand dbg noprint -> disable read data print\n"); + printf("nand dbg init -> initialize NFC\n"); + printf("nand dbg status -> read device status\n"); + printf("nand dbg id -> read device ID\n"); + printf("nand dbg read -> read \n"); + printf("nand dbg write -> program \n"); + printf("nand dbg erase -> erase\n"); + printf("nand dbg readchain -> Read in chained mode\n"); + } + else if (strcmp(cmd, "enable") == 0) + { + mvNfcDbgFlag = 1; + } + else if (strcmp(cmd, "disable") == 0) + { + mvNfcDbgFlag = 0; + } + else if (strcmp(cmd, "print") == 0) + { + mvNfcPrintFlag = 1; + } + else if (strcmp(cmd, "noprint") == 0) + { + mvNfcPrintFlag = 0; + } + else if (strcmp(cmd, "init") == 0) + { + MV_NFC_INFO nfcInfo; + + /* Override Control structure */ + gDbgCtrl = &nfcDbgCtrl; + + /*Fill info structure */ + nfcInfo.ioMode = MV_NFC_PDMA_ACCESS/*MV_NFC_PIO_ACCESS*/; + nfcInfo.eccMode = MV_NFC_ECC_HAMMING/*MV_NFC_ECC_BCH*/; +#if defined(MV_NAND_GANG_MODE) + nfcInfo.ifMode = MV_NFC_IF_2X8; +#else + nfcInfo.ifMode = MV_NFC_IF_1X8; +#endif + nfcInfo.autoStatusRead = MV_FALSE; + nfcInfo.tclk = 166666667; + nfcInfo.readyBypass = MV_FALSE; + + if (nfcInfo.ioMode == MV_NFC_PDMA_ACCESS) + { +#if 0 +/* Not needed here, mvPdmaInit() is performed in board_init() */ + printf("Initializing PDMA ... "); + if (mvPdmaInit() != MV_OK) + { + printf("FAILED\n"); + return -1; + } + printf("OK\n"); +#endif + } + + printf("Initializing NFC ... "); + if (mvNfcInit(&nfcInfo, gDbgCtrl) != MV_OK) + { + printf("FAILED\n"); + return -1; + } + printf("Flash detected %s\n", mvNfcFlashModelGet(gDbgCtrl)); + } + else if (gDbgCtrl == NULL) + { + printf("board_nand_init() was never called!\n"); + return -1; + } + else if (strcmp(cmd, "status") == 0) + { + if (mvNfcStatusRead(gDbgCtrl, buff) != 0) + return -1; + + printf("Status = %08x\n", buff[0]); + } + else if (strcmp(cmd, "id") == 0) + { + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_ID, 0, 0) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_ID, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + buff[0] = buff[1] = 0xFFFFFFFF; + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_ID, buff, (MV_U32)buff) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_ID, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + printf("ID = %08x\n", buff[0]); + } + else if (strcmp(cmd, "erase") == 0) + { + MV_U32 blkSize; + MV_8* endptr; + MV_U32 dest, size, offs, blk; + + if (mvNfcFlashBlockSizeGet(gDbgCtrl, &blkSize) != MV_OK) + { + printf("mvNfcFlashBlockSizeGet Failed!\n"); + return -1; + } + + if (argc != 5) + { + if (argc != 3) + printf("Illegal parameters, assuming single page 0\n"); + + dest = 0; + size = blkSize; + } + else + { + dest = simple_strtoul(argv[3], &endptr, 16); + size = simple_strtoul(argv[4], &endptr, 16); + + if (dest & (blkSize-1)) + printf("Offset not alligned to block boundaries (0x%x)\n", blkSize); + if (size & (blkSize-1)) + printf("Erase size not alligned to block size(0x%x)\n", blkSize); + } + + printf("NFC Erase: Erase Offset=0x%08x, Erase Size=0x%08x (Block Size = %08x)\n", dest, size, blkSize); + + /* Loop and write all space required */ + for (offs = dest; offs < (dest+size); offs+=blkSize) + { + printf("Erasing block offset %08x\n", offs); + + mvNfcAddress2BlockConvert(gDbgCtrl, offs, &blk); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_ERASE, blk, 0) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_ERASE, MV_NFC_STATUS_RDY/*MV_NFC_STATUS_CMDD*/, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + + if (mvNfcStatusRead(gDbgCtrl, buff) != 0) + { + printf("Status Read Failed!\n"); + return -1; + } + + if (buff[0] & 0x1) + printf("SR0: Erase command Failed!\n"); + } + //printf("\n"); + } + else if (strcmp(cmd, "erasechain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 5) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + cnt = simple_strtoul(argv[4], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Erase: Block Number=0x%08x, Block Count=%08x\n", src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; icmdChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_ERASE, NULL); + if (stat & MV_NFC_STATUS_RDY) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopetimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Read: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; idataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", + ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stoptimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchaing") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/2)) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Ganaged Chained Read: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*2); i+=2) + { + desc[i].cmd = MV_NFC_CMD_READ_MONOLITHIC; + desc[i].pageAddr = (src + (i/2)); + desc[i].pageCount = 1; + desc[i].virtAddr = (MV_U32*)(dest + (i * 0x800)); + desc[i].physAddr = (dest + (i * 0x800)); + + desc[i+1].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+1].pageAddr = (src + (i/2)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(dest + ((i+1) * 0x800)); + desc[i+1].physAddr = (dest + ((i+1) * 0x800)); + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if (mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*2)) != MV_OK) + { + printf("Multiple Command Issue Failed!!\n"); + goto stopgtimer; + } + + /* wait for the command to finish */ + while(1) + { + + + if(mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopgtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "readchain1k") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + MV_U32 spare[8] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}; + MV_U32 err; + MV_PDMA_CHAN_STATE pdmastat; + MV_U32 reg; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/5)) + { + printf("Count exceeds allocated descriptor count (%d bigger than %d)\n", cnt, (MV_NFC_MAX_DESC_CHAIN/5)); + return -1; + } + + printf("NFS Ganaged Chained Read 1KB: DDR Dest=0x%08x, Source page # =0x%08x, Page Count=%08x\n", dest, src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*5); i+=5) + { + desc[i].cmd = MV_NFC_CMD_READ_MONOLITHIC; + desc[i].pageAddr = (src + (i/5)); + desc[i].pageCount = 1; + desc[i].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x0); + desc[i].physAddr = (dest + ((i/5)*0x1000) + 0x0); + desc[i].length = 0x400; + desc[i].numSgBuffs = 1; + + desc[i+1].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+1].pageAddr = (src + (i/5)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x400); + desc[i+1].physAddr = (dest + ((i/5)*0x1000) + 0x400); + desc[i+1].length = 0x400; + desc[i+1].numSgBuffs = 1; + + desc[i+2].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+2].pageAddr = (src + (i/5)); + desc[i+2].pageCount = 1; + desc[i+2].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0x800); + desc[i+2].physAddr = (dest + ((i/5)*0x1000) + 0x800); + desc[i+2].length = 0x400; + desc[i+2].numSgBuffs = 1; + + desc[i+3].cmd = MV_NFC_CMD_READ_NAKED; + desc[i+3].pageAddr = (src + (i/5)); + desc[i+3].pageCount = 1; + desc[i+3].virtAddr = (MV_U32*)(dest + ((i/5)*0x1000) + 0xC00); + desc[i+3].physAddr = (dest + ((i/5)*0x1000) + 0xC00); + desc[i+3].length = 0x400; + desc[i+3].numSgBuffs = 1; + + desc[i+4].cmd = MV_NFC_CMD_READ_LAST_NAKED; + desc[i+4].pageAddr = (src + (i/5)); + desc[i+4].pageCount = 1; + desc[i+4].virtAddr = spare; + desc[i+4].physAddr = spare; + desc[i+4].length = 0x20; + desc[i+4].numSgBuffs = 1; + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if ((err = mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*5))) != MV_OK) + { + printf("Multiple Command Issue Failed (Error = %x!!\n", err); + goto stoprtimer; + } + + /* wait for the command to finish */ + while(1) + { + if((pdmastat = mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl)) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } + +stoprtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "read") == 0) + { + MV_U32 pgSize; + MV_8* endptr; + MV_U32 src, dest, size, offs, row, col; + MV_U32 totalsize; + + if (mvNfcFlashPageSizeGet(gDbgCtrl, &pgSize, &totalsize) != MV_OK) + { + printf("mvNfcFlashPageSizeGet Failed!\n"); + return -1; + } + + if (argc != 6) + { + if (argc != 3) + printf("Illegal parameters, assuming single page 0\n"); + + dest = (MV_U32) buff; + src = 0; + size = pgSize; + } + else + { + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + size = simple_strtoul(argv[5], &endptr, 16); + } + + printf("NFS Read: Source=0x%08x, DDR destination=0x%08x, Size=%08x\n (page Size = %x)", src, dest, size, pgSize); + + /* Loop and write all space required */ + for (offs = src; offs < (src+size); offs+=pgSize, dest+=pgSize) + { + mvNfcAddress2RowConvert(gDbgCtrl, offs, &row, &col); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (gDbgCtrl->ifMode == MV_NFC_IF_2X8) /* GANGED MODE */ + { + row = (row/2); + printf("READ-GNGD: row(%x), col(%x), dest(%x)\n", row, col, dest);\ + + //printf("STEP 1: Issue MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + //printf("STEP 2: Date read MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_U32*)dest, dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + + dest += (pgSize/2); + + // printf("dest2(%x)\n", dest); + + //printf("STEP 3: Issue MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_NAKED, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_NAKED, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + //printf("STEP 4: Date read MV_NFC_CMD_READ_MONOLITHIC\n"); + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_NAKED, (MV_U32*)dest, dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_NAKED, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + + dest -= (pgSize/2); + } + else /* NON-GANGED MODE */ + { + printf("Read: ROW=%x COL=%x DST=%x\n", row, col, dest); + if (mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, row, col) != MV_OK) + { + printf("Command issue failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, MV_NFC_STATUS_RDD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_U32*)(dest), dest) != MV_OK) + { + printf("Read Status Failed!\n"); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_READ_MONOLITHIC, (MV_NFC_STATUS_CMDD | MV_NFC_STATUS_PAGED), + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + if (mvNfcPrintFlag) + mvNfcDataPrint(dest); + } + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + } // read loop + } + else if (strcmp(cmd, "writechain1k") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + MV_U32 spare[8] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}; + MV_U32 err; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + dest = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > (MV_NFC_MAX_DESC_CHAIN/7)) + { + printf("Count exceeds allocated descriptor count (%d bigger than %d)\n", cnt, (MV_NFC_MAX_DESC_CHAIN/7)); + return -1; + } + + printf("NFS Ganaged Chained Write 1KB: DDR Source=0x%08x, Destination page # =0x%08x, Page Count=%08x\n", src, dest, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; i<(cnt*7); i+=7) + { + desc[i].cmd = MV_NFC_CMD_WRITE_DISPATCH_START; + desc[i].pageAddr = (dest + (i/7)); + desc[i].pageCount = 1; + desc[i].virtAddr = 0; + desc[i].physAddr = 0; + desc[i].length = 0; + desc[i].numSgBuffs = 1; + + desc[i+1].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+1].pageAddr = (dest + (i/7)); + desc[i+1].pageCount = 1; + desc[i+1].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x4); + desc[i+1].physAddr = (src + ((i/7)*0x1000) + 0x0); + desc[i+1].length = 0x400; + desc[i+1].numSgBuffs = 1; + + desc[i+2].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+2].pageAddr = (dest + (i/7)); + desc[i+2].pageCount = 1; + desc[i+2].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x400); + desc[i+2].physAddr = (src + ((i/7)*0x1000) + 0x400); + desc[i+2].length = 0x400; + desc[i+2].numSgBuffs = 1; + + desc[i+3].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+3].pageAddr = (dest + (i/7)); + desc[i+3].pageCount = 1; + desc[i+3].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0x800); + desc[i+3].physAddr = (src + ((i/7)*0x1000) + 0x800); + desc[i+3].length = 0x400; + desc[i+3].numSgBuffs = 1; + + desc[i+4].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+4].pageAddr = (dest + (i/7)); + desc[i+4].pageCount = 1; + desc[i+4].virtAddr = (MV_U32*)(src + ((i/7)*0x1000) + 0xC00); + desc[i+4].physAddr = (src + ((i/7)*0x1000) + 0xC00); + desc[i+4].length = 0x400; + desc[i+4].numSgBuffs = 1; + + desc[i+5].cmd = MV_NFC_CMD_WRITE_NAKED; + desc[i+5].pageAddr = (dest + (i/7)); + desc[i+5].pageCount = 1; + desc[i+5].virtAddr = spare; + desc[i+5].physAddr = spare; + desc[i+5].length = 0x20; + desc[i+5].numSgBuffs = 1; + + desc[i+6].cmd = MV_NFC_CMD_WRITE_DISPATCH_END; + desc[i+6].pageAddr = (dest + (i/7)); + desc[i+6].pageCount = 1; + desc[i+6].virtAddr = 0; + desc[i+6].physAddr = 0; + desc[i+6].length = 0; + desc[i+6].numSgBuffs = 1; + } + + /* Start the timer */ + MV_REG_WRITE(CNTMR_VAL_REG(1), 0xFFFFFFFF); + MV_REG_BIT_SET(CNTMR_CTRL_REG, 0x4); /* enable Timer 1 */ + + if ((err = mvNfcCommandMultiple(gDbgCtrl, desc, (cnt*7))) != MV_OK) + { + printf("Multiple Command Issue Failed (Error = %x!!\n", err); + goto stopwtimer; + } + + /* wait for the command to finish */ + while(1) + { + if(mvPdmaChannelStateGet(&gDbgCtrl->dataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, NULL); + printf("mvNfcStatusGet = %08x\n", stat); + if (stat & MV_NFC_STATUS_RDY) + { + /* Stop the timer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopwtimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "writechain") == 0) + { + MV_NFC_MULTI_CMD desc[MV_NFC_MAX_DESC_CHAIN]; + MV_U32 src, dest, cnt, i; + MV_8* endptr; + MV_U32 stat; + + if (argc != 6) + { + printf("Illegal parameters, assuming single page 0\n"); + return -1; + } + + dest = simple_strtoul(argv[3], &endptr, 16); + src = simple_strtoul(argv[4], &endptr, 16); + cnt = simple_strtoul(argv[5], &endptr, 16); + + if (cnt > MV_NFC_MAX_DESC_CHAIN) + { + printf("Count exceeds allocated descriptor count\n"); + return -1; + } + + printf("NFS Chained Program: Page number=0x%08x, DDR destination=0x%08x, Page Count=%08x\n", dest, src, cnt); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + for (i=0; idataChanHndl) == MV_PDMA_CHANNEL_STOPPED) + { + stat = mvNfcStatusGet(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, NULL); + if (stat & (MV_NFC_STATUS_UNC_ERROR |MV_NFC_STATUS_BBD)) + { + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Error Detected (%08x)\n", stat); + printf("Time Elapsed %dus\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + + + if (stat & MV_NFC_STATUS_CMDD) + { + /* Stop the imer and calculate time */ + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 as fast as possible */ + printf("Command Finished OK (Time Elapsed %dus)\n", ((0xFFFFFFFF - MV_REG_READ(CNTMR_VAL_REG(1))) / 166)); + break; + } + } + } +stopptimer: + MV_REG_BIT_RESET(CNTMR_CTRL_REG, 0x4); /* disable Timer 1 */ + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + } + else if (strcmp(cmd, "write") == 0) + { + MV_U32 pgSize; + MV_8* endptr; + MV_U32 src, dest, size, offs, row, col; + MV_STATUS ret; + MV_U8 tmpbuff[2112]; + MV_U32 totalsize; + + memset(tmpbuff, 0xFF, 2112); + + if (mvNfcFlashPageSizeGet(gDbgCtrl, &pgSize, &totalsize) != MV_OK) + { + printf("mvNfcFlashPageSizeGet Failed!\n"); + return -1; + } + + src = simple_strtoul(argv[3], &endptr, 16); + dest = simple_strtoul(argv[4], &endptr, 16); + size = simple_strtoul(argv[5], &endptr, 16); + + printf("NFS Program: DDR Source=0x%08x, Flash Offset=0x%08x, Size=%08x (Page Size = %08x)\n", src, dest, size, pgSize); + + /* Loop and write all space required */ + for (offs = dest; offs < (dest+size); offs+=pgSize, src+=pgSize) + { + mvNfcAddress2RowConvert(gDbgCtrl, offs, &row, &col); + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_0) != MV_OK) + { + printf("CS Assert Failed!!\n"); + return -1; + } + + if (gDbgCtrl->ifMode == MV_NFC_IF_2X8) /* GANGED MODE */ + { + row = (row/2); + + printf("PRGRM-GNGD: row(%x), col(%x), src1(%x)\n", row, col, src); + + /*****/ + /* 1 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 1: MV_NFC_CMD_WRITE_DISPATCH_START\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_START, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_START, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + + /*****/ + /* 2 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 2: Issue MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /*****/ + /* 3 */ + memcpy(tmpbuff, (MV_U8*)src, 2048); + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 3: Write Data MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /* increment address */ + src += (pgSize/2); + + // printf("src2(%x)\n", src); + + /*****/ + /* 4 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 4: Issue MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + + /*****/ + /* 5 */ + memcpy(tmpbuff, (MV_U8*)src, 2048); + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 5: Write Data MV_NFC_CMD_WRITE_NAKED\n"); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_NAKED, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /*****/ + /* 6 */ + // printf(">>>>>>>>>>>>>>>>>>>>>>STEP 6: MV_NFC_CMD_WRITE_DISPATCH_END\n"); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_END, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_DISPATCH_END, MV_NFC_STATUS_CMDD, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + /* increment address */ + src -= (pgSize/2); + } + else /* NON-GANGED MODE */ + { + printf("Write: ROW=%x COL=%x SRC=%x\n", row, col, src); + if ((ret = mvNfcCommandIssue(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, row, col)) != MV_OK) + { + printf("Command issue failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, MV_NFC_STATUS_WRD_REQ, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + + memcpy(tmpbuff, (MV_U8*)src, 2048); + if ((ret = mvNfcReadWrite(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, (MV_U32*)tmpbuff, (MV_U32)tmpbuff)) != MV_OK) + { + printf("Read Status Failed (errCode = %d)!\n", ret); + return -1; + } + + mvNfcEWaitEvent(gDbgCtrl, MV_NFC_CMD_WRITE_MONOLITHIC, MV_NFC_STATUS_PAGED, + (MV_NFC_STATUS_COR_ERROR | MV_NFC_STATUS_UNC_ERROR | MV_NFC_STATUS_BBD)); + } + + if (mvNfcSelectChip(gDbgCtrl, MV_NFC_CS_NONE) != MV_OK) + { + printf("CS DEAssert Failed!!\n"); + return -1; + } + } /* page loop */ + } + + return 1; +} +#endif /* MV_NFC_DBG */ + +#if 0 +#if defined(CFG_NAND_BOOT) +extern int doNandScrub(struct nand_chip* nand, size_t ofs); + +/* Erase bad blocks - for internal use only */ +int do_nand_scrub(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char console_buffer[]; + + printf("\n**Warning**\n"); + printf("This command will erase NAND flash bad blocks ...\n"); + printf("Are you sure ? (y/n)"); + readline(" "); + + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + doNandScrub(nand_dev_desc + 0, 0); + } + return 1; +} + +U_BOOT_CMD( + nandScrub, 4, 4, do_nand_scrub, + "", + " " + "" +); + +#endif /* defined(CFG_NAND_BOOT) */ +#endif + +#if 0 +#include "twsi/mvTwsi.h" +#include "audio/mvAudioRegs.h" +#include "audio/mvAudio.h" +#include "audio/dac/mvCLAudioCodec.h" + + +static MV_U32 codec_init_values[][2] = { + /* Address Value */ + { 0x00, 0x0 }, + { 0x0c, 0x808 }, + { 0x1c, 0x2740 }, + { 0x6a, 0x46 }, + { 0x6c, 0xffff }, + { 0x40, 0x3700 }, + { 0x34, 0x8000 }, + { 0x3e, 0x96c1 }, + { 0x3c, 0x67f3 }, + { 0x3a, 0xcd70 }, + { 0x04, 0x0 }, + { 0x02, 0x0 }, + { 0x5e, 0x0 }, + { -1, -1 } +}; + +/* +** Initialize codec registers to enable audio playback. +*/ +void audio_init_codec(void) +{ + MV_TWSI_ADDR twsiAddr; + MV_U32 i; + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[2]; + int ADDRS = 0x4A; + + twsiAddr.address = ADDRS; + twsiAddr.type = ADDR7_BIT; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &twsiAddr, MV_FALSE); + + for(i = 0; codec_init_values[i][0] != 0xFFFFFFFF; i++) { + twsiSlave.slaveAddr.address = ADDRS; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = codec_init_values[i][0]; + twsiSlave.moreThen256 = MV_FALSE; + data[0] = (MV_U8)((codec_init_values[i][1] >> 8) & 0xFF); + data[1] = (MV_U8)(codec_init_values[i][1] & 0xFF); + if(mvTwsiWrite(0, &twsiSlave, data, 2) != MV_OK) { + printf("mvTwsiWrite() failed address [0x%x], value [0x%x] - FAILED\n", codec_init_values[i][0], codec_init_values[i][1]); + continue; + } else { + printf("address [0x%x], value [0x%x]\n", codec_init_values[i][0], codec_init_values[i][1]); + } + } + return; +} + +int audio_play_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 dataAddr; + MV_U32 dataSize; + MV_STATUS status; + MV_AUDIO_PLAYBACK_CTRL pbCtrl; + MV_I2S_PLAYBACK_CTRL i2sCtrl; + MV_AUDIO_FREQ_DATA dcoCtrl; + +// audio_init_codec(); + + dataAddr = simple_strtoul( argv[1], NULL, 16 ); + dataSize = simple_strtoul( argv[2], NULL, 16 ); + + /* Initialize Audio HAL */ + mvSysAudioInit(1); + + pbCtrl.burst = AUDIO_128BYTE_BURST; + pbCtrl.loopBack = MV_FALSE; + pbCtrl.monoMode = AUDIO_PLAY_BOTH_MONO; + pbCtrl.bufferPhyBase = dataAddr; /* Buffer holding PCM data */ + pbCtrl.bufferSize = dataSize; /* Size of buffer in bytes */ + pbCtrl.intByteCount = dataSize; /* N/A, no interrupts in Uboot */ + + /* Set default sample size to 16-non compact */ + pbCtrl.sampleSize = SAMPLE_16BIT_NON_COMPACT; + /* Check if user wants to override the default value */ + if(argc > 3) { + if(strcmp(argv[3],"16nc") == 0) + pbCtrl.sampleSize = SAMPLE_16BIT_NON_COMPACT; + else if(strcmp(argv[3],"16") == 0) + pbCtrl.sampleSize = SAMPLE_16BIT; + else if(strcmp(argv[3],"24") == 0) + pbCtrl.sampleSize = SAMPLE_24BIT; + else if(strcmp(argv[3],"32") == 0) + pbCtrl.sampleSize = SAMPLE_32BIT; + else { + printf("Bad sample size (16, 16nc, 24, 32).\n"); + return 0; + } + } + status = mvAudioPlaybackControlSet(1, &pbCtrl); + if(status != MV_OK) { + printf("mvAudioPlaybackControlSet() failed (%d).\n", status); + return 0; + } + + /* Get the current DCO config */ + mvAudioDCOCtrlGet(1,&dcoCtrl); + /* Set default sample rate. */ + dcoCtrl.baseFreq = AUDIO_FREQ_44_1KH; + /* Check if user wants to overried default sample rate */ + if(argc > 4) { + if(strcmp(argv[4],"44.1khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_44_1KH; + else if(strcmp(argv[4],"48khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_48KH; + else if(strcmp(argv[4],"96khz") == 0) + dcoCtrl.baseFreq = AUDIO_FREQ_96KH; + else { + printf("Bad sample rate.\n"); + return 0; + } + } + /* Set Sample rate */ + status = mvAudioDCOCtrlSet(1, &dcoCtrl); + if(status != MV_OK) { + printf("mvAudioDCOCtrlSet() failed (%d).\n", status); + return 0; + } + + /* Set I2S playback related parameters. */ + i2sCtrl.sampleSize = ((pbCtrl.sampleSize == SAMPLE_16BIT_NON_COMPACT) ? + SAMPLE_16BIT : pbCtrl.sampleSize); + i2sCtrl.justification = I2S_JUSTIFIED; + i2sCtrl.sendLastFrame = MV_FALSE; + status = mvI2SPlaybackCtrlSet(0, &i2sCtrl); + if(status != MV_OK) { + printf("mvI2SPlaybackCtrlSet() failed (%d).\n", status); + return 0; + } + + /* Clear interrupt cause bit */ + MV_REG_WRITE(MV_AUDIO_INT_CAUSE_REG(1),(1 << 7)); + + /* Unmute I2S */ + mvAudioI2SPlaybackMute(1, MV_FALSE); + /* Enable playback */ + mvAudioI2SPlaybackEnable(1, MV_TRUE); + /* Unpause I2S */ + mvAudioPlaybackPause(1, 0); + + /* + ** Wait till audio buffer is consumed. + ** Otherwise the playback will loop over the buffer forever. + */ + while(!(MV_REG_READ(MV_AUDIO_INT_CAUSE_REG(1)) & (1 << 7))) { + if(ctrlc()) + break; + } + /* Clear interrupt cause bit */ + MV_REG_WRITE(MV_AUDIO_INT_CAUSE_REG(1),(1 << 7)); + /* Stop playback */ + mvAudioI2SPlaybackMute(1, MV_TRUE); + mvAudioPlaybackPause(1, MV_TRUE); + mvAudioI2SPlaybackEnable(1, MV_FALSE); + + return 1; +} + +U_BOOT_CMD( + audioTest, 5, 1, audio_play_cmd, + "audioTest - Test audio playback\n", + " AuidTest address size sample_size sample_rate\n" + " \taddress\t - Address holding PCM data.\n" + " \tsize\t - data buffer size in bytes (< 16MB).\n" + " \tsample_size\t - 16, 16nc, 24 or 32 (default 16nc).\n" + " \tsample_rate\t - 44.1khz, 48khz or 96khz (default 44.1khz).\n" + "\tPlay audio buffer. \n" +); +#endif + +int whoAmI_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + printf("cpu #: %d", whoAmI()); + return 1; +} + +U_BOOT_CMD( + whoAmI, 2, 1, whoAmI_cmd, + "- reading CPU ID\n", + "" + ); \ No newline at end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_dram.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_dram.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_dram.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_dram.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,310 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "ddr2/mvDramIf.h" +#include "mvOs.h" +#include "mvBoardEnvLib.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCpuIf.h" + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +extern void _start(void); +extern void reset_cpu (ulong addr); +extern int dramBoot; + + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void); +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +#endif + +MV_VOID mvIntrfaceWidthPrint(MV_VOID) +{ + printf(" 16bit width"); +} + +MV_VOID mvIntrfaceParamPrint(MV_VOID) +{ + MV_U32 temp; + + printf("DRAM"); + switch((MV_REG_READ(0x141c) >> 4) & 0x7) { + case 0x3: + printf(" CAS Latency = 3"); + break; + case 0x4: + printf(" CAS Latency = 4"); + break; + case 0x5: + printf(" CAS Latency = 5"); + break; + case 0x6: + printf(" CAS Latency = 6"); + break; + default: + printf(" unknown CAL "); + break; + } + + temp = MV_REG_READ(0x1408); + printf(" tRP = %d tRAS = %d tRCD=%d\n", + ((temp >> 8) & 0xf) + 1, ((temp >> 16) & 0x10) + (temp & 0xf) + 1, ((temp >> 4) & 0xf) + 1); +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int i, dramTotalSize=0; + MV_32 memBase; + +#if defined(MV_INC_BOARD_DDIM) + /* Call dramInit */ + if (0 == (dramTotalSize = initdram(0))) { + printf("DRAM Initialization Failed\n"); + reset_cpu(0); + return (1); + } +#endif + + //mvIntrfaceParamPrint(); + + for(i = 0; i< MV_DRAM_MAX_CS; i++) { +#warning: not relevant to KW2? +#if !defined(MV_88F6082L) && defined(MV_88F6082) + if (mvCtrlModelRevGet() == MV_6082_A0_ID) { + gd->bd->bi_dram[i].start = (i)?_16M:0; + gd->bd->bi_dram[i].size = _8M; + } else { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + } +#else + MV_CPU_DEC_WIN addrDecWin; + if((mvCpuIfTargetWinGet(SDRAM_CS0 + i, &addrDecWin) == MV_OK) && + (addrDecWin.enable == MV_TRUE)) { + memBase = addrDecWin.addrWin.baseLow; + gd->bd->bi_dram[i].start = memBase; + gd->bd->bi_dram[i].size = addrDecWin.addrWin.size; + } +#endif + //dramTotalSize += gd->bd->bi_dram[i].size; +// if (gd->bd->bi_dram[i].size) +// { + //printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + //mvSizePrint(gd->bd->bi_dram[i].size); + //printf("\n"); +// } + } + +// printf("DRAM Total "); +// mvSizePrint(dramTotalSize); +// mvIntrfaceWidthPrint(); +// printf("\n"); + +#ifdef MV_INC_DRAM_MFG_TEST + mvDramMfgTrst(); +#endif + return 0; +} + +#if defined(MV_INC_BOARD_DDIM) + +/* u-boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram(int board_type) +{ + MV_VOIDFUNCPTR pRom; + MV_U32 forcedCl; /* Forced CAS Latency */ + MV_U32 totalSize; + char * env; + MV_TWSI_ADDR slave; + + /* r0 <- current position of code */ + /* test if we run from flash or RAM */ + if(dramBoot != 1) + { + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); + + /* Calculating MIN/MAX CAS latency according to user settings */ + env = getenv("CASset"); + + if(env && (strcmp(env,"1.5") == 0)) + { + forcedCl = 15; + } + else if(env && (strcmp(env,"2") == 0)) + { + forcedCl = 20; + } + else if(env && (strcmp(env,"2.5") == 0)) + { + forcedCl = 25; + } + else if(env && (strcmp(env,"3") == 0)) + { + forcedCl = 30; + } + else if(env && (strcmp(env,"4") == 0)) + { + forcedCl = 40; + } + else if(env && (strcmp(env,"5") == 0)) + { + forcedCl = 50; + } + else if(env && (strcmp(env,"6") == 0)) + { + forcedCl = 60; + } + else + { + forcedCl = 0; + } + + /* detect the dram configuartion parameters */ + if (MV_OK != mvDramIfDetect(forcedCl,1)) + { + printf("DRAM Auto Detection Failed! System Halt!\n"); + return 0; + } + + /* set the dram configuration */ + /* Calculate jump address of _mvDramIfConfig() */ + +#if defined(MV_BOOTROM) + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN); +#else + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE); +#endif + + + (*pRom) (); /* Jump to _mvDramIfConfig*/ + } + + totalSize = mvDramIfSizeGet(); + + + return(totalSize); +} + +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void) +{ + + /* Memory test */ + DECLARE_GLOBAL_DATA_PTR; + unsigned int mem_len,i,j, pattern; + unsigned int *mem_start; + char *env; + + env = getenv("enaPost"); + if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) ) + { + printf("Memory test pattern: "); + + for (j = 0 ; j<2 ; j++) + { + + switch(j){ + case 0: + pattern=0x55555555; + printf("0x%X, ",pattern); + break; + case 1: + pattern=0xAAAAAAAA; + printf("0x%X, ",pattern); + break; + default: + pattern=0x0; + printf("0x%X, ",pattern); + break; + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + mem_start = (unsigned int *)gd->bd->bi_dram[i].start; + mem_len = gd->bd->bi_dram[i].size; + if (i == 0) + { + mem_start+= _4M; + mem_len-= _4M; + } + mem_len/=4; + if (MV_OK != mv_mem_test(mem_start, pattern, mem_len)) + { + printf(" Fail!\n"); + while(1); + } + } + } + printf(" Pass\n"); + } +} + + +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + *(pMem + i) = pattern; + + if (MV_OK != mv_mem_cmp(pMem, pattern, count)) + { + return MV_ERROR; + } + return MV_OK; +} + +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + { + if (*(pMem + i) != pattern) + { + printf("Fail\n"); + printf("Test failed at 0x%x\n",(pMem + i)); + return MV_ERROR; + } + } + + return MV_OK; +} +#endif /* MV_INC_DRAM_MFG_TEST */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesaApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_CESA_API_H__ +#define __MV_SYS_CESA_API_H__ + + +MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysCesa.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,108 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cesa/mvCesa.h" + +extern u32 mv_crypto_base_get(void); + +/******************************************************************************* +* mvSysCesaInit - Initialize the Cesa subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle) +{ + MV_CESA_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvCesaTdmaWinInit(addrWinMap); + + if (status == MV_OK) { + halData.sramPhysBase = (MV_ULONG)mv_crypto_base_get(); + halData.sramVirtBase = (MV_U8 *)mv_crypto_base_get(); + halData.sramOffset = 0; + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + status = mvCesaHalInit(numOfSession, queueDepth, + osHandle, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysDdr.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,134 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + + +/******************************************************************************* +* mvSysDdrSpdRead +* +* DESCRIPTION: +* System interface for reading DDR SPD contents. +* +* INPUT: +* data: Buffer to read data into. +* size: Number of bytes to read. +* +* OUTPUT: +* data: SPD data. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdRead(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiRead(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} + + +/******************************************************************************* +* mvSysDdrSpdWrite +* +* DESCRIPTION: +* System interface for writing DDR SPD contents. +* +* INPUT: +* data: Buffer holding the data to be written. +* size: Number of bytes to write. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdWrite(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiWrite(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETH_API_H__ +#define __MV_SYS_ETH_API_H__ + + +MV_VOID mvSysEthInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEth.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,129 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "eth/mvEth.h" + + +/******************************************************************************* +* mvSysEthInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysEthInit(MV_VOID) +{ + MV_ETH_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + int i; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status != MV_OK) + return; + + for (i = 0; i < MAX_TARGETS; i++) { + if (addrWinMap[i].enable == MV_FALSE) + continue; + + } + + halData.maxPortNum = mvCtrlEthMaxPortGet(); + halData.cpuPclk = mvCpuPclkGet(); + halData.tclk = mvBoardTclkGet(); +#ifdef ETH_DESCR_IN_SRAM + halData.sramSize = mvCtrlSramSizeGet(); +#endif + + for (port = 0; port < halData.maxPortNum; port++) { + if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) { + halData.portData[port].powerOn = MV_FALSE; + continue; + } + status = mvEthWinInit(port, addrWinMap); + if (status == MV_OK) { + halData.portData[port].powerOn = MV_TRUE; + halData.portData[port].phyAddr = mvBoardPhyAddrGet(port); + halData.portData[port].isSgmii = mvBoardIsPortInSgmii(port); + halData.portData[port].macSpeed = mvBoardMacSpeedGet(port); + } + } + + mvEthHalInit(&halData); + + return; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhyApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETHPHY_API_H__ +#define __MV_SYS_ETHPHY_API_H__ + + +MV_STATUS mvSysEthPhyInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysEthPhy.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "eth-phy/mvEthPhy.h" + + +/******************************************************************************* +* mvSysEthPhyInit - Initialize the EthPhy subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysEthPhyInit(void) +{ + MV_ETHPHY_HAL_DATA halData; + MV_U32 port; + + for (port = 0; port < mvCtrlEthMaxPortGet(); port++) { + halData.phyAddr[port] = mvBoardPhyAddrGet(port); + halData.boardSpecInit = MV_FALSE; + } + + return mvEthPhyHalInit(&halData); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNetaApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_NETA_API_H__ +#define __MV_SYS_NETA_API_H__ + + +void mvSysNetaInit(void); + +#endif /* __MV_SYS_NETA_API_H__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysNeta.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,136 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "neta/gbe/mvNeta.h" + + +/******************************************************************************* +* mvSysNetaInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +void mvSysNetaInit(void) +{ + MV_NETA_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + int i; + + memset(&halData, 0, sizeof(halData)); + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status != MV_OK) + return; + + for (i = 0; i < MAX_TARGETS; i++) { + if (addrWinMap[i].enable == MV_FALSE) + continue; + + printk(KERN_INFO "%d - Base 0x%08x , Size = 0x%08x.\n", i, + addrWinMap[i].addrWin.baseLow, addrWinMap[i].addrWin.size); + } + halData.maxPort = mvCtrlEthMaxPortGet(); + halData.pClk = mvCpuPclkGet(); + halData.tClk = mvBoardTclkGet(); + halData.isGpon = MV_FALSE; + +#ifdef CONFIG_MV_ETH_BM + halData.bmPhysBase = PNC_BM_PHYS_BASE; + halData.bmVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_BM */ + +#ifdef CONFIG_MV_ETH_PNC + halData.pncPhysBase = PNC_BM_PHYS_BASE; + halData.pncVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_PNC */ + + for (port = 0; port < halData.maxPort; port++) { + if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) + continue; + + mvNetaPortPowerUp(port); + status = mvNetaWinInit(port, addrWinMap); + if (status != MV_OK) + continue; + + } + + mvNetaHalInit(&halData); + + return; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPexApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_PEX_API_H__ +#define __MV_SYS_PEX_API_H__ +#include "pex/mvPex.h" + +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysPex.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" + +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvSysPexInit - Initialize the Pex subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_PEX_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvPexWinInit(pexIf, pexType, addrWinMap); + + if (status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.maxPexIf = mvCtrlPexMaxIfGet(); + status = mvPexInit(pexIf, pexType, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSataApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SATA_API_H__ +#define __MV_SYS_SATA_API_H__ + +MV_STATUS mvSysSataWinInit(MV_VOID); + +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSata.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "sata/CoreDriver/mvSata.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +MV_STATUS mvSysSataWinInit(MV_VOID) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvSataWinInit(addrWinMap); + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSFlash.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,226 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "sflash/mvSysSFlash.h" + +#define MV_SYS_SFLASH_MAX_CMD_LEN 4 + +static struct { + MV_U8 buf[MV_SYS_SFLASH_MAX_CMD_LEN]; + MV_U32 bufLen; + MV_U8 transType; +} mvSysSflashCmd; + +/******************************************************************************* +* mvSysSflashCommandSet +* +* DESCRIPTION: +* System interface for sending a command to the SPI flash. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* cmdBuff: Command data to be written. +* cmdLen: Command length in bytes. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashCommandSet(MV_VOID *flashHandle, MV_U8* cmdBuff, MV_U32 cmdLen, + MV_U8 transType) +{ + if (cmdLen > MV_SYS_SFLASH_MAX_CMD_LEN) + return MV_ERROR; + + if (!(transType & SYS_SFLASH_TRANS_START) || (mvSysSflashCmd.transType != 0)) + return MV_ERROR; + + mvSpiParamsSet(0, 0, SPI_TYPE_FLASH); + + memcpy(mvSysSflashCmd.buf, cmdBuff, cmdLen); + mvSysSflashCmd.bufLen = cmdLen; + mvSysSflashCmd.transType = transType; + + if (transType & SYS_SFLASH_TRANS_END) + return mvSysSflashDataWrite(flashHandle, NULL, 0, transType); + + return MV_OK; +} + + +/******************************************************************************* +* mvSysSflashDataRead +* +* DESCRIPTION: +* System interface for reading SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer to read the data into. +* dataLen: Number of bytes to read. +* dummyBytes: Number of dummy bytes to read before reading the real +* data. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* dataBuff: The data as read from flash. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataRead(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U32 dummyBytes, MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + + ret = mvSpiWriteThenRead(0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, + dataBuff, dataLen, dummyBytes); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd, 0, sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashDataWrite +* +* DESCRIPTION: +* System interface for writing SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer holding the data to be written. +* dataLen: Number of bytes to write. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataWrite(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + ret = mvSpiWriteThenWrite(0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, dataBuff, dataLen); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd, 0, sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashFreqSet +* +* DESCRIPTION: +* System interface for controlling the SPI interface frequency. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* freq: The new frequency to be configured for the SPI IF. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashFreqSet(MV_VOID *flashHandle, MV_U32 freq) +{ + + return mvSpiBaudRateSet(0, freq); +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpiApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SPI_API_H__ +#define __MV_SYS_SPI_API_H__ + +#include "mvCommon.h" + +MV_STATUS mvSysSpiInit(MV_U8 spi_id, MV_U32 serialBaudRate); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysSpi.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,126 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "spi/mvSpi.h" +#include "spi/mvSysSpi.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/******************************************************************************* +* mvSysSpiInit - Initialize the SPI subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysSpiInit(MV_U8 spiId, MV_U32 serialBaudRate) +{ + MV_SPI_HAL_DATA halData; + + halData.ctrlModel = mvCtrlModelGet(); + halData.tclk = mvBoardTclkGet(); + + return mvSpiInit(spiId, serialBaudRate, &halData); +} + + +/******************************************************************************* +* mvSysSpiMppConfig +* +* DESCRIPTION: +* System interface for configuring the MPP's configuration to enable / +* disable SPI mode. +* +* INPUT: +* mode: The mode to be set into MPP unit. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSpiMppConfig(MV_U8 mode) +{ +#if 0 + if (mode == SYS_SPI_MPP_ENABLE) + mvMPPConfigToSPI(); + else + mvMPPConfigToDefault(); +#endif + return MV_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdmApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,78 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_TDM_API_H__ +#define __MV_SYS_TDM_API_H__ + +#include "mvSysTdmConfig.h" + +#ifdef MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else +#include "voiceband/commUnit/mvCommUnit.h" +#endif + +MV_STATUS mvSysTdmInit(MV_TDM_PARAMS *tdmParams); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysTdm.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,236 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" + +#ifdef CONFIG_MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else +#include "voiceband/commUnit/mvCommUnit.h" +#include "gpp/mvGpp.h" +#endif + +#include "voiceband/mvSysTdmSpi.h" +#include "spi/mvSpiCmnd.h" +#include "spi/mvSpi.h" + +#define MAX_DATA_LENGTH 255 + +/******************************************************************************* +* mvSysTdmInit - Initialize the TDM subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysTdmInit(MV_TDM_PARAMS *tdmParams) +{ + MV_TDM_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) +#ifdef MV_TDM_SUPPORT + status = mvTdmWinInit(addrWinMap); +#else + status = mvCommUnitWinInit(addrWinMap); +#endif + + if (status == MV_OK) { + halData.spiMode = mvBoardTdmSpiModeGet(); + halData.model = mvCtrlModelGet(); +#ifdef MV_TDM_SUPPORT + status = mvTdmHalInit(tdmParams, &halData); +#else + halData.maxCs = mvBoardTdmDevicesCountGet(); + status = mvCommUnitHalInit(tdmParams, &halData); + + /* Issue SLIC reset */ + mvGppValueSet(0, BIT24, 0); + mvOsDelay(1); + mvGppValueSet(0, BIT24, BIT24); +#endif + } + + return status; +} + +MV_VOID mvSysTdmSpiRead(MV_U16 lineId, MV_U8 *cmdBuff, MV_U8 cmdSize, MV_U8 *dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if ((cmdSize > 4) || (dataSize > MAX_DATA_LENGTH)) { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiRead(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(0, mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if (MV_OK != mvSpiWriteThenRead(0, cmdBuff, cmdSize, dataBuff, dataSize, 0)) + printk(KERN_ERR "SPI read failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmSpiWrite - telephony register write via SPI interface +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmSpiWrite(MV_U16 lineId, MV_U8 *cmdBuff, MV_U8 cmdSize, MV_U8 *dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if ((cmdSize > 3) || (dataSize > MAX_DATA_LENGTH)) { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiWrite(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(0, mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if (MV_OK != mvSpiWriteThenWrite(0, cmdBuff, cmdSize, dataBuff, dataSize)) + printk(KERN_ERR "SPI write failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmIntEnable - Enable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntEnable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntEnable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntEnable(deviceId); + +#endif +} + +/******************************************************************************* +* mvSysTdmIntDisable - Disable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntDisable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntDisable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntDisable(deviceId); + +#endif +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsbApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_USB_API_H__ +#define __MV_SYS_USB_API_H__ + +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysUsb.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,105 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "usb/mvUsb.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "usb/mvUsbRegs.h" + +/******************************************************************************* +* mvSysUsbHalInit - Initialize the USB subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost) +{ + MV_USB_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvUsbWinInit(dev, addrWinMap); + + if (dev == 0) + mvUsbPllInit(); + if (status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + status = mvUsbHalInit(dev, isHost, &halData); + } + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXorApi.h 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_XOR_API_H__ +#define __MV_SYS_XOR_API_H__ + +MV_VOID mvSysXorInit(void); + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_hal_if/mvSysXor.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,87 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "xor/mvXor.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "xor/mvXorRegs.h" + +MV_VOID mvSysXorInit(void) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvXorWinInit(addrWinMap); + + if (status == MV_OK) + mvXorHalInit(MV_XOR_MAX_CHAN); + return; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_main.c u-boot-2009.08/board/marvell/mv_armada_xp/mv_main.c --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/mv_main.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/mv_main.c 2011-04-04 13:57:34.925598332 -0400 @@ -0,0 +1,1370 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include "mvTypes.h" +#include "mvBoardEnvLib.h" +#include "mvCpuIf.h" +#include "mvCtrlEnvLib.h" +#include "mv_mon_init.h" +#include "mvDebug.h" +#include "device/mvDevice.h" +#include "twsi/mvTwsi.h" +#include "eth/mvEth.h" +#include "pex/mvPex.h" +#include "gpp/mvGpp.h" +#include "gpp/mvGppRegs.h" +#include "mvSysHwConfig.h" +#include "mv_phy.h" + +#ifdef MV_INCLUDE_RTC +#include "rtc/integ_rtc/mvRtc.h" +#include "rtc.h" +#elif CONFIG_RTC_DS1338_DS1339 +#include "rtc/ext_rtc/mvDS133x.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#include "mvSysXorApi.h" +#endif +#if defined(MV_INCLUDE_IDMA) +#include "sys/mvSysIdma.h" +#include "idma/mvIdma.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#include "mvSysUsbApi.h" +#endif + +#include "cpu/mvCpu.h" +#include "nand.h" +#include "spi_flash.h" +#ifdef CONFIG_PCI + #include +#endif +//#include "pci/mvPciRegs.h" + +#include +#include +//#include +//#include + +#include +#include +#include +#include "mvCommon.h" +#include "uart/mvUart.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* CPU address decode table. */ +MV_CPU_DEC_WIN mvCpuAddrWinMap[] = MV_CPU_IF_ADDR_WIN_MAP_TBL; +/*extern MV_U32 dummyFlavour;*/ +#if 0 +static void mvHddPowerCtrl(void); +#endif +#if defined(CONFIG_CMD_RCVR) +extern void recoveryDetection(void); +#endif +void mv_cpu_init(void); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void); +#endif + +#if 0 +#ifdef CONFIG_FLASH_CFI_DRIVER +//MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID); +//int mv_board_num_flash_banks; +//extern flash_info_t flash_info[]; /* info for FLASH chips */ +//extern unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); +#endif /* CONFIG_FLASH_CFI_DRIVER */ +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +//extern MV_VOID mvBoardEgigaPhySwitchInit(void); +#endif + +#if defined(CONFIG_CMD_NAND) +/* Define for SDK 2.0 */ +int __aeabi_unwind_cpp_pr0(int a,int b,int c) {return 0;} +int __aeabi_unwind_cpp_pr1(int a,int b,int c) {return 0;} +#endif + +extern nand_info_t nand_info[]; /* info for NAND chips */ + +extern struct spi_flash *flash; +//MV_VOID mvMppModuleTypePrint(MV_VOID); + +#ifdef MV_NAND_BOOT +extern MV_U32 nandEnvBase; +#endif + +/* Define for SDK 2.0 */ +//int raise(void) {return 0;} + +void print_mvBanner(void) +{ +#ifdef CONFIG_SILENT_CONSOLE + DECLARE_GLOBAL_DATA_PTR; + gd->flags |= GD_FLG_SILENT; +#endif + printf("\n"); + printf(" __ __ _ _\n"); + printf("| \\/ | __ _ _ ____ _____| | |\n"); + printf("| |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n"); + printf("| | | | (_| | | \\ V / __/ | |\n"); + printf("|_| |_|\\__,_|_| \\_/ \\___|_|_|\n"); + printf(" _ _ ____ _\n"); + printf(" | | | | | __ ) ___ ___ | |_ \n"); + printf(" | | | |___| _ \\ / _ \\ / _ \\| __| \n"); + printf(" | |_| |___| |_) | (_) | (_) | |_ \n"); + printf(" \\___/ |____/ \\___/ \\___/ \\__| \n"); +//#if !defined(MV_NAND_BOOT) +#if defined(MV_INCLUDE_MONT_EXT) + //mvMPPConfigToSPI(); + if(!enaMonExt()) + printf(" ** LOADER **\n"); + else + printf(" ** MONITOR **\n"); + //mvMPPConfigToDefault(); +#else + + printf(" ** LOADER **\n"); +#endif /* MV_INCLUDE_MONT_EXT */ +//#endif + return; +} + +void maskAllInt(void) { + int i; + /* for all interrupts (0-115) reset bit 0:3 and 8:11 to disable IRQ and FIQ */ + for (i=0; i < MV_IRQ_NR; i++) + MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(i), MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(i)) & ~(0xF0F)); + +} + +/* init for the Master*/ +void misc_init_r_dec_win(void) +{ +#if defined(MV_INCLUDE_USB) + { + char *env, envname[10]; + int i; + + for (i = 0; i < mvCtrlUsbMaxGet(); i++) { + + sprintf(envname, "usb%dMode", i); + env = getenv(envname); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + printf("USB %d: Device Mode\n", i); + mvSysUsbInit(i, MV_FALSE); + } + else + { + printf("USB %d: Host Mode\n", i); + mvSysUsbInit(i, MV_TRUE); + } + } + } +#endif/* #if defined(MV_INCLUDE_USB) */ + +#if defined(MV_INCLUDE_XOR) + mvSysXorInit(); +#endif + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + //mv_set_power_scheme(); +#endif + + return; +} + + +/* + * Miscellaneous platform dependent initialisations + */ + +extern MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +extern MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); + +/* golabal mac address for yukon EC */ +unsigned char yuk_enetaddr[6]; + +extern int timer_init(void ); +extern void i2c_init(int speed, int slaveaddr); + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +/* TODO : Should disable this code after we finish debugging - we added this code to enable printing before console init */ +#if 1 + int clock_divisor = (CONFIG_SYS_TCLK / 16)/115200; + + /* muti-core support, initiate each Uart to each cpu */ + mvUartInit(whoAmI(), clock_divisor, mvUartBase(whoAmI())); +#endif + if (whoAmI() != 0) + return 0; + + mvCtrlUpdatePexId(); + +#ifdef CONFIG_FLASH_CFI_DRIVER + int portwidth; + MV_U32 devParam; +#endif +#if defined(MV_INCLUDE_TWSI) + MV_TWSI_ADDR slave; +#endif + MV_GPP_HAL_DATA *gppHalData; + + unsigned int i; + + maskAllInt(); + + /* must initialize the int in order for udelay to work */ + /* interrupt_init(); - no interrupt handling in u-boot */ + timer_init(); + + /* Init the Board environment module (device bank params init) */ + mvBoardEnvInit(); + +#if defined(MV_INCLUDE_TWSI) + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); +#endif + + /* Init the Controlloer environment module (MPP init) */ + mvCtrlEnvInit(); + + mvBoardDebugLed(2); + + /* Init the Controller CPU interface */ + mvCpuIfInit(mvCpuAddrWinMap); + + /* Init the GPIO sub-system */ + gppHalData->ctrlRev = mvCtrlRevGet(); + mvGppInit(gppHalData); + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = 3036; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* relocate the exception vectors */ + /* U-Boot is running from DRAM at this stage */ + for(i = 0; i < 0x100; i+=4) { + *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); + } + + /* Update NOR flash base address bank for CFI driver */ + +#ifdef CONFIG_FLASH_CFI_DRIVER + portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(0)); + devParam &= ~(DBP_DEVWIDTH_MASK); + switch (portwidth) { + case FLASH_CFI_8BIT: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case FLASH_CFI_16BIT: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case FLASH_CFI_32BIT: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + break; + } + MV_REG_WRITE(DEV_BANK_PARAM_REG(0),devParam); +#endif /* CONFIG_FLASH_CFI_DRIVER */ + + mvBoardDebugLed(4); + + return 0; +} + +void misc_init_r_env(void){ + char *env; + char tmp_buf[10]; + unsigned int malloc_len; + DECLARE_GLOBAL_DATA_PTR; + char buff[256]; + + env = getenv("console"); + if(!env) { +#ifdef RD_88F6510_SFU_ID + setenv("console","console=ttyS0,115200 mv_port1_config=disconnected"); +#else + setenv("console","console=ttyS0,115200"); +#endif + } + + /* update the CASset env parameter */ + env = getenv("CASset"); + if(!env ) { +#ifdef MV_MIN_CAL + setenv("CASset","min"); +#else + setenv("CASset","max"); +#endif + } + /* Monitor extension */ +#ifdef MV_INCLUDE_MONT_EXT + env = getenv("enaMonExt"); + if(/* !env || */ ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaMonExt","yes"); + else +#endif + setenv("enaMonExt","no"); + +#if defined (MV_INC_BOARD_NOR_FLASH) + env = getenv("enaFlashBuf"); + if( ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaFlashBuf","no"); + else + setenv("enaFlashBuf","yes"); +#endif + + /* CPU streaming */ + env = getenv("enaCpuStream"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaCpuStream","no"); + else + setenv("enaCpuStream","yes"); + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + setenv("enaWrAllo","yes"); + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + setenv("pexMode","RC"); + + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("disL2Cache","yes"); + else + setenv("disL2Cache","no"); + + env = getenv("MPmode"); + if(!env || ( (strcmp(env,"smp") == 0) || (strcmp(env,"SMP") == 0) ) ) + setenv("MPmode","SMP"); + else + setenv("MPmode","AMP"); + + /* Make address 0x80000000-0x8fffffff shared (set 'S' in pgd) */ + env = getenv("cacheShare"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("cacheShare","no"); + else + setenv("cacheShare","yes"); + + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("setL2CacheWT","no"); + else + setenv("setL2CacheWT","yes"); + + env = getenv("disL2Prefetch"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + setenv("disL2Prefetch","yes"); + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + else + { + setenv("disL2Prefetch","no"); + setenv("enaICPref","no"); + setenv("enaDCPref","no"); + } + + + env = getenv("sata_dma_mode"); + if( env && ((strcmp(env,"No") == 0) || (strcmp(env,"no") == 0) ) ) + setenv("sata_dma_mode","no"); + else + setenv("sata_dma_mode","yes"); + + + /* Malloc length */ + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0){ + sprintf(tmp_buf,"%d",CONFIG_SYS_MALLOC_LEN>>20); + setenv("MALLOC_len",tmp_buf); + } + + /* primary network interface */ + env = getenv("ethprime"); + if(!env) { +// if(mvBoardIdGet() == RD_88F6281A_ID) +// setenv("ethprime","egiga1"); +// else + setenv("ethprime",ENV_ETH_PRIME); + } + + /* netbsd boot arguments */ + env = getenv("netbsd_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) { + setenv("netbsd_en","no"); + } else { + setenv("netbsd_en","yes"); + env = getenv("netbsd_gw"); + if(!env) + setenv("netbsd_gw","192.168.0.254"); + env = getenv("netbsd_mask"); + if(!env) + setenv("netbsd_mask","255.255.255.0"); + + env = getenv("netbsd_fs"); + if(!env) + setenv("netbsd_fs","nfs"); + + env = getenv("netbsd_server"); + if(!env) + setenv("netbsd_server","192.168.0.1"); + + env = getenv("netbsd_ip"); + if(!env) { + env = getenv("ipaddr"); + setenv("netbsd_ip",env); + } + + env = getenv("netbsd_rootdev"); + if(!env) + setenv("netbsd_rootdev","mgi0"); + + env = getenv("netbsd_add"); + if(!env) + setenv("netbsd_add","0x800000"); + + env = getenv("netbsd_get"); + if(!env) + setenv("netbsd_get","tftpboot $netbsd_add $image_name"); + +#if defined(MV_INC_BOARD_QD_SWITCH) + env = getenv("netbsd_netconfig"); + if(!env) + setenv("netbsd_netconfig","mv_net_config=<((mgi0,00:00:11:22:33:44,0)(mgi1,00:00:11:22:33:55,1:2:3:4)),mtu=1500>"); +#endif + env = getenv("netbsd_set_args"); + if(!env) + setenv("netbsd_set_args","setenv bootargs nfsroot=$netbsd_server:$rootpath fs=$netbsd_fs \ + ip=$netbsd_ip serverip=$netbsd_server mask=$netbsd_mask gw=$netbsd_gw rootdev=$netbsd_rootdev \ + ethaddr=$ethaddr eth1addr=$eth1addr ethmtu=$ethmtu eth1mtu=$eth1mtu $netbsd_netconfig"); + + env = getenv("netbsd_boot"); + if(!env) + setenv("netbsd_boot","bootm $netbsd_add $bootargs"); + + env = getenv("netbsd_bootcmd"); + if(!env) + setenv("netbsd_bootcmd","run netbsd_get ; run netbsd_set_args ; run netbsd_boot"); + } + + /* vxWorks boot arguments */ + env = getenv("vxworks_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("vxworks_en","no"); + else { + char* buff = (char *)0x1100; + setenv("vxworks_en","yes"); + + sprintf(buff,"mgi(0,0) host:vxWorks.st"); + env = getenv("serverip"); + strcat(buff, " h="); + strcat(buff,env); + env = getenv("ipaddr"); + strcat(buff, " e="); + strcat(buff,env); + strcat(buff, ":ffff0000 u=anonymous pw=target "); + + setenv("vxWorks_bootargs",buff); + } + + /* linux boot arguments */ + env = getenv("bootargs_root"); + if(!env) + setenv("bootargs_root","root=/dev/nfs rw"); + + /* For open Linux we set boot args differently */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",":::orion:eth0:none"); + } else { + env = getenv("bootargs_end"); + if(!env) +#if defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootargs_end",MV_BOOTARGS_END_SWITCH); +#else + setenv("bootargs_end",MV_BOOTARGS_END); +#endif + } + + env = getenv("image_name"); + if(!env) + setenv("image_name","uImage"); + +#if (CONFIG_BOOTDELAY >= 0) + env = getenv("bootcmd"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000; "); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000; "); +#elif defined(MV_INCLUDE_TDM) + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000; "); +#else + + setenv("bootcmd","tftpboot 0x2000000 $image_name;\ +setenv bootargs $console $bootargs_root nfsroot=$serverip:$rootpath \ +ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000; "); +#endif +#endif /* (CONFIG_BOOTDELAY >= 0) */ + + env = getenv("standalone"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig $mvPhoneConfig; bootm 0x2000000;"); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000;"); +#elif defined(MV_INCLUDE_TDM) + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end $mvPhoneConfig; bootm 0x2000000;"); +#else + setenv("standalone","fsload 0x2000000 $image_name;setenv bootargs $console root=/dev/mtdblock0 rw \ +ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000;"); +#endif + + /* Set boodelay to 3 sec, if Monitor extension are disabled */ + if(!enaMonExt()) { + setenv("bootdelay","3"); + setenv("disaMvPnp","no"); + } + + /* Disable PNP config of Marvel memory controller devices. */ + env = getenv("disaMvPnp"); + if(!env) + setenv("disaMvPnp","no"); + +#if (defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH)) + /* Generate random ip and mac address */ + /* Read RTC to create pseudo-random data for enc */ + struct rtc_time tm; + unsigned int xi, xj, xk, xl, i; + char ethaddr_0[30]; + char ethaddr_1[30]; + char ethaddr_2[30]; + char ethaddr_3[30]; + char pon_addr[30]; + + rtc_get(&tm); + xi = ((tm.tm_yday + tm.tm_sec)% 254); + /* No valid ip with one of the fileds has the value 0 */ + if (xi == 0) + xi+=2; + + xj = ((tm.tm_yday + tm.tm_min)%254); + /* No valid ip with one of the fileds has the value 0 */ + if (xj == 0) + xj+=2; + + /* Check if the ip address is the same as the server ip */ + if ((xj == 1) && (xi == 11)) + xi+=2; + + xk = (tm.tm_min * tm.tm_sec)%254; + xl = (tm.tm_hour * tm.tm_sec)%254; + + sprintf(ethaddr_0,"00:50:43:%02x:%02x:%02x",xk,xi,xj); + sprintf(ethaddr_1,"00:50:43:%02x:%02x:%02x",xl,xi,xj); + sprintf(ethaddr_2,"00:50:43:%02x:%02x:%02x",xl,xk,xj); + sprintf(ethaddr_3,"00:50:43:%02x:%02x:%02x",xi,xk,xl); + sprintf(pon_addr,"00:50:43:%02x:%02x:%02x",xj,xk,xl); + + /* MAC addresses */ + env = getenv("ethaddr"); + if(!env) + setenv("ethaddr",ethaddr_0); + + env = getenv("eth1addr"); + if(!env) + setenv("eth1addr",ethaddr_1); + + env = getenv("eth2addr"); + if(!env) + setenv("eth2addr",ethaddr_2); + + env = getenv("eth3addr"); + if(!env) + setenv("eth3addr",ethaddr_3); + + env = getenv("mv_pon_addr"); + if(!env) + setenv("mv_pon_addr",pon_addr); + + env = getenv("ethmtu"); + if(!env) + setenv("ethmtu","1500"); + + env = getenv("eth1mtu"); + if(!env) + setenv("eth1mtu","1500"); + + env = getenv("eth2mtu"); + if(!env) + setenv("eth2mtu","1500"); + + env = getenv("eth3mtu"); + if(!env) + setenv("eth3mtu","1500"); + + /* Set mvNetConfig env parameter */ + env = getenv("mvNetConfig"); + if(!env ) { + switch (mvBoardIdGet()) { +#if defined(RD_88F6510_SFU_ID) || defined(RD_88F6530_MDU_ID) || defined(RD_88F6560_GW_ID) || defined(DB_88F6535_BP_ID) + case RD_88F6510_SFU_ID: + case RD_88F6530_MDU_ID: + setenv("mvNetConfig","mv_net_config=0"); + break; + case RD_88F6560_GW_ID: + case DB_88F6535_BP_ID: +#endif + default: + setenv("mvNetConfig","mv_net_config=4,(00:50:43:11:11:11,0:1:2:3),mtu=1500"); + break; + } + } +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(MV_INCLUDE_TDM) + /* Set mvPhoneConfig env parameter */ + env = getenv("mvPhoneConfig"); + if(!env ) + setenv("mvPhoneConfig","mv_phone_config=dev0:fxs,dev1:fxs"); +#endif + +#if defined(MV_INCLUDE_USB) + /* USB Host */ + env = getenv("usb0Mode"); + if(!env) + setenv("usb0Mode",ENV_USB0_MODE); + env = getenv("usb1Mode"); + if(!env) + setenv("usb1Mode",ENV_USB1_MODE); + env = getenv("usb2Mode"); + if(!env) + setenv("usb2Mode",ENV_USB2_MODE); +#endif /* (MV_INCLUDE_USB) */ + +#if defined(YUK_ETHADDR) + env = getenv("yuk_ethaddr"); + if(!env) + setenv("yuk_ethaddr",YUK_ETHADDR); + + { + int i; + char *tmp = getenv ("yuk_ethaddr"); + char *end; + + for (i=0; i<6; i++) { + yuk_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + } +#endif /* defined(YUK_ETHADDR) */ + +#if defined(MV_NAND) + env = getenv("nandEcc"); + if(!env) { + setenv("nandEcc", "1bit"); + } +#endif +#if 0 +#if defined(RD_88F6281A) || defined(RD_88F6192A) || defined(RD_88F6190A) + mvHddPowerCtrl(); +#endif +#endif +#if defined(CONFIG_CMD_RCVR) + env = getenv("netretry"); + if (!env) + setenv("netretry","no"); + + env = getenv("rcvrip"); + if (!env) + setenv("rcvrip",RCVR_IP_ADDR); + + env = getenv("loadaddr"); + if (!env) + setenv("loadaddr",RCVR_LOAD_ADDR); + + env = getenv("autoload"); + if (!env) + setenv("autoload","no"); + + /* Check the recovery trigger */ + recoveryDetection(); +#endif + env = getenv("eeeEnable"); + if (!env) + setenv("eeeEnable","no"); + + return; +} +#define MV_CPU_SW_RESET_CONTROL(cpu) (0x20800 + ((cpu) * 0x8)) + +void kick_next() { + int cpuNum; + MV_REG_WRITE(0x20988, 0x0); + MV_REG_WRITE(0x22224, 0x600000); + MV_REG_WRITE(0x22324, 0x600000); + MV_REG_WRITE(0x22424, 0x600000); + MV_REG_WRITE(0x22424, 0x600000); + MV_REG_WRITE(0x200b8, 0x07ff1d11); + + cpuNum = mvBoardCpuCoresNumGet()==2?(mvBoardCpuCoresNumGet()-1):(mvBoardCpuCoresNumGet()); + if (whoAmI() < cpuNum) { + MV_REG_WRITE(MV_CPU_SW_RESET_CONTROL(whoAmI()+1), 0x0); + } +} + +#ifdef BOARD_LATE_INIT +int board_late_init (void) +{ + char *env; + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ + + env = getenv("enaMP"); + if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + kick_next(); + + mvBoardDebugLed(0); + return 0; +} +#endif + +void pcie_tune(void) +{ + MV_REG_WRITE(0xF1041AB0, 0x100); + MV_REG_WRITE(0xF1041A20, 0x78000801); + MV_REG_WRITE(0xF1041A00, 0x4014022F); + MV_REG_WRITE(0xF1040070, 0x18110008); + + return; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_MARVELL +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) + /* move to the begining so in case we have a PCI NIC it will + read the env mac addresses correctlly. */ + mv_eth_initialize(bis); +#endif +#endif +#if defined(CONFIG_SK98) + skge_initialize(bis); +#endif +#if defined(CONFIG_E1000) + e1000_initialize(bis); +#endif + return 0; +} + +int print_cpuinfo (void) +{ + char name[50]; + + mvBoardNameGet(name); + printf("Board: %s\n", name); + mvCtrlModelRevNameGet(name); + printf("SoC: %s\n", name); + if (mvCtrlModelRevGet() != MV_6710_Z1_ID) + printf(" running %d CPUs\n", mvCtrlGetCpuNum()+1); + if (!mvCtrlIsValidSatR()) + printf(" Custom configuration\n"); + mvCpuNameGet(name); + printf("CPU: %s", name); +#ifdef MV_CPU_LE + printf(" LE\n"); +#else + printf(" BE\n"); +#endif + if (mvCtrlModelRevGet() != MV_6710_Z1_ID) + printf(" CPU # %d\n", whoAmI()); + printf(" CPU @ %dMhz, L2 @ %dMhz\n", mvCpuPclkGet()/1000000, mvCpuL2ClkGet()/1000000); + printf(" DDR @ %dMhz, TClock @ %dMhz\n", CONFIG_SYS_BUS_CLK/1000000, mvTclkGet()/1000000); + printf(" DDR %dBit Width, %s Memory Access\n", mvCtrlDDRBudWidth(), mvCtrlDDRThruXbar()?"XBAR":"FastPath"); + return 0; +} +int misc_init_r (void) +{ + char *env; + + mvBoardDebugLed(5); + + /* init special env variables */ + misc_init_r_env(); + + mv_cpu_init(); + +#if defined(MV_INCLUDE_MONT_EXT) + if(enaMonExt()) { + printf("Marvell monitor extension:\n"); + mon_extension_after_relloc(); + } +#endif /* MV_INCLUDE_MONT_EXT */ + + /* print detected modules */ +// mvMppModuleTypePrint(); + + /* init the units decode windows */ + misc_init_r_dec_win(); + +#if 0 +#ifdef CONFIG_PCI +#if !defined(MV_MEM_OVER_PCI_WA) && !defined(MV_MEM_OVER_PEX_WA) + pci_init(); +#endif +#endif +#endif + mvBoardDebugLed(6); + /* Prints the modules detected */ + mvBoardMppModuleTypePrint(); + + mvBoardDebugLed(7); + + /* pcie fine tunning */ + env = getenv("pcieTune"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"yes") == 0))) + pcie_tune(); + else + setenv("pcieTune","no"); + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + /* Init the PHY or Switch of the board */ + mvBoardEgigaPhyInit(); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + + return 0; +} + +MV_U32 mvTclkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->tclk == 0) + gd->tclk = mvBoardTclkGet(); + + return gd->tclk; +} + +MV_U32 mvSysClkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->bus_clk == 0) + gd->bus_clk = mvBoardSysClkGet(); + + return gd->bus_clk; +} + +/* exported for EEMBC */ +MV_U32 mvGetRtcSec(void) +{ + MV_RTC_TIME time; +#ifdef MV_INCLUDE_RTC + mvRtcTimeGet(&time); +#elif CONFIG_RTC_DS1338_DS1339 + mvRtcDS133xTimeGet(&time); +#endif + return (time.minutes * 60) + time.seconds; +} + +void reset_cpu (ulong addr) +{ + mvBoardReset(); +} + +void mv_cpu_init(void) +{ + char *env; + volatile unsigned int temp; + + /* enable access to CP10 and CP11 */ + temp = 0x00f00000; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 2" :: "r" (temp)); + + env = getenv("enaFPU"); + if((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0)){ + /* init and Enable FPU to Run Fast Mode */ + printf("FPU initialized to Run Fast Mode.\n"); + /* Enable */ + temp = FPEXC_ENABLE; + fmxr(FPEXC, temp); + /* Run Fast Mode */ + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + fmxr(FPSCR, temp); + }else{ + printf("FPU not initialized\n"); + /* Disable */ + temp = fmrx(FPEXC); + temp &= ~FPEXC_ENABLE; + fmxr(FPEXC, temp); + } + + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 1" : "=r" (temp)); + temp |= BIT16; /* Disable reac clean intv */ + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 2" : "=r" (temp)); + temp |= (BIT25 | BIT27 | BIT29 | BIT30); + /* removed BIT23 in order to enable fast LDR bypass */ + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 2\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + /* Enable speculative read miss from L1 to "line fill" L1 */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + + env = getenv("L1SpeculativeEn"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + temp |= BIT7; + else{ + temp &= ~BIT7; + } + + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /*imb*/ + + /* Multi-CPU managment */ + env = getenv("enaMP"); + if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + { + env = getenv("MPmode"); + if( (strcmp(env,"AMP") == 0) || (strcmp(env,"amp") == 0) ) + { + /* Set AMP in Auxilary control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (temp)); + temp &= ~(0x1 << 5); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Set AMP in Auxiliary Funcional Modes Control register */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + temp &= ~(0x1 << 1); + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + } + else + { + /* Set SMP in Auxilary control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (temp)); + temp |= (0x1 << 5); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Set SMP in Auxiliary Funcional Modes Control register */ + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r" (temp)); + temp |= (0x1 << 1); + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Enable CPU respond to coherency fabric requests */ + /* Assaf: Note must be enabled for IO coherency as well */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CTRL_REG, (0x1 << (24 + whoAmI()))); + + /* Configure all Cores to be in SMP Group0 */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, (0x1 << (24 + whoAmI()))); + + /* In loader mode, set fabric regs for both CPUs.*/ + + env = getenv("enaMonExt"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) { + + /* Configure Core1 to be in SMP Group0 */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, (0x1 << 25)); + } + + /* Set number of CPUs=2 (for Linux) */ + MV_REG_BIT_SET(SOC_COHERENCY_FABRIC_CFG_REG, 0x1); + } + } + +#if 1 + /* Set L2C WT mode */ + temp = MV_REG_READ(CPU_L2_AUX_CTRL_REG) & ~CL2ACR_WB_WT_ATTR_MASK; + env = getenv("setL2CacheWT"); + if(!env || ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) { + temp |= CL2ACR_WB_WT_ATTR_WT; + } + MV_REG_WRITE(CPU_L2_AUX_CTRL_REG, temp); +#endif + + /* enable L2C */ + temp = MV_REG_READ(CPU_L2_CTRL_REG); + + env = getenv("disL2Cache"); + if(!env || ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + temp |= CL2CR_L2_EN_MASK; + else + temp &= ~CL2CR_L2_EN_MASK; + + MV_REG_WRITE(CPU_L2_CTRL_REG, temp); + + /* Configure L2 options if L2 exists */ + if (MV_REG_READ(CPU_L2_CTRL_REG) & CL2CR_L2_EN_MASK) { + + /* Read L2 Auxilary control register */ + temp = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + /* Clear fields */ + temp &= ~(CL2ACR_WB_WT_ATTR_MASK | CL2ACR_FORCE_WA_MASK); + + /* Set "Force write policy" field */ + env = getenv("L2forceWrPolicy"); + if( (strcmp(env,"WB") == 0) || (strcmp(env,"wb") == 0) ) + temp |= CL2ACR_WB_WT_ATTR_WB; + else if( (strcmp(env,"WT") == 0) || (strcmp(env,"wt") == 0) ) + temp |= CL2ACR_WB_WT_ATTR_WT; + else + temp |= CL2ACR_WB_WT_ATTR_PAGE; + + /* Set "Force Write Allocate" field */ + env = getenv("L2forceWrAlloc"); + if( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + temp |= CL2ACR_FORCE_NO_WA; + else if( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) + temp |= CL2ACR_FORCE_WA; + else + temp |= CL2ACR_FORCE_WA_DISABLE; + + /* Set "ECC" */ + env = getenv("L2EccEnable"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp &= ~CL2ACR_ECC_EN; + else + temp |= CL2ACR_ECC_EN; + + /* Set other L2 configurations */ + temp |= (CL2ACR_PARITY_EN | CL2ACR_INVAL_UCE_EN); + + /* Write to L2 Auxilary control register */ + MV_REG_WRITE(CPU_L2_AUX_CTRL_REG, temp); + + env = getenv("L2SpeculativeRdEn"); + if((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + MV_REG_BIT_SET(0x20228, ((0x1 << 5))); + else + MV_REG_BIT_RESET(0x20228, ((0x1 << 5))); + + } + + /* Enable i cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (temp)); + temp |= BIT12; + /* Change reset vector to address 0x0 */ + temp &= ~BIT13; + asm ("mcr p15, 0, %0, c1, c0, 0\n" \ + "mcr p15, 0, %0, c7, c5, 4": :"r" (temp)); /* imb */ + + /* Disable MBUS Err Prop - inorder to avoid data aborts */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); +} +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +#if 0 +MV_VOID mvMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + if(devId != MV_6190_DEV_ID) + printf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TS\n", devClass); + break; + case MV_BOARD_MII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is MII\n", devClass); + break; + default: + break; + } + } +} +#endif + +/* Set unit in power off mode acording to the detection of MPP/SERDES */ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void) +{ + MV_U32 devId = mvCtrlModelGet(); + MV_U32 boardId = mvBoardIdGet(); + MV_BOARD_PEX_INFO *pexInfo = mvBoardPexInfoGet(); + MV_U32 unit, lane, pexIf; + + mvOsOutput("Shutting down unused interfaces:\n"); + + /* SERDES modules */ + if (mvBoardIsPexModuleConnected() == MV_TRUE) { +#if 1 /* TODO - check if SATA should be disabled if PEX(1) module is used */ + /* Sata */ + mvOsOutput(" SATA0\n"); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + mvOsOutput(" SATA1\n"); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); +#endif + /* Ethernet (SGMII/QSGMII) */ + mvOsOutput(" GBE2\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 2, MV_FALSE); + mvOsOutput(" GBE3\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 3, MV_FALSE); + } + + /* MPP modules */ + if (mvBoardIsLcdDviModuleConnected() == MV_TRUE) { + /* Ethernet (RGMII) */ + mvOsOutput(" GBE0\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 0, MV_FALSE); + mvOsOutput(" GBE1\n"); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + } + + /* TDM */ + if(mvBoardTdmDevicesCountGet() == 0) { + mvOsOutput(" TDM\n"); + mvCtrlPwrClckSet(TDM_32CH_UNIT_ID, 0, MV_FALSE); + } + + /* PEX */ + pexIf = 0; + for (unit = 0; unit < mvCtrlPexMaxUnitGet(); unit++) { + if (pexInfo->pexUnitCfg[unit].pexCfg == PEX_BUS_DISABLED) { + if (unit < 2) {/* PEX unit 0,1 */ + for (lane = 0; lane < 4; lane++) { + mvOsOutput(" PEX%d.%d(%d)\n", unit, lane, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } else { /* PEX unit 2,3 */ + mvOsOutput(" PEX%d.0(%d)\n", unit, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } else if (pexInfo->pexUnitCfg[unit].pexCfg == PEX_BUS_MODE_X1) { + for (lane = 0; lane < 4; lane++) { + if (pexInfo->pexUnitCfg[unit].pexLaneStat[lane] != 1) { + mvOsOutput(" PEX%d.%d(%d)\n", unit, lane, pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + } + pexIf++; + } + } else { /* x4 or x8 */ + mvOsOutput(" PEX%d.0(%d)\n", unit,pexIf); + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + pexIf++; + } + } + +} +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +#if 0 +/******************************************************************************* +* mvHddPowerCtrl - +* +* DESCRIPTION: +* This function set HDD power on/off acording to env or wait for button push +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +static void mvHddPowerCtrl(void) +{ + MV_32 hddPowerBit; + MV_32 fanPowerBit; + MV_32 hddHigh = 0; + MV_32 fanHigh = 0; + char* env; + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + hddPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_HDD_POWER, 0); + fanPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_FAN_POWER, 0); + if (hddPowerBit > 31) + { + hddPowerBit = hddPowerBit % 32; + hddHigh = 1; + } + if (fanPowerBit > 31) + { + fanPowerBit = fanPowerBit % 32; + fanHigh = 1; + } + } + + if ((RD_88F6281A_ID == mvBoardIdGet()) || (RD_88F6192A_ID == mvBoardIdGet()) || + (RD_88F6190A_ID == mvBoardIdGet())) + { + env = getenv("hddPowerCtrl"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("hddPowerCtrl","no"); + else + setenv("hddPowerCtrl","yes"); + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + mvBoardFanPowerControl(MV_TRUE); + mvBoardHDDPowerControl(MV_TRUE); + } + else + { + /* FAN power on */ + MV_REG_BIT_SET(GPP_DATA_OUT_REG(fanHigh),(1<> 4)) +#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4)) + +/* NAND Flash Chip Capability */ +#ifdef MV_LARGE_PAGE +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 64 +#define PAGE_SIZE 2048 /* Bytes */ +#define SPARE_SIZE 64 +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#else /* ! LARGE PAGE NAND */ +/* NAND Flash Chip Capability */ +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 32 +#define PAGE_SIZE 512 /* Bytes */ +#define SPARE_SIZE 16 +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#endif + +/* NAND Flash Command. This appears to be generic across all NAND flash chips */ +#define CMD_READ 0x00 /* Read */ +#define CMD_READ1 0x01 /* Read1 */ +#define CMD_READ2 0x50 /* Read2 */ +#define CMD_START_READ 0x30 /* Read command after write addr */ +#define CMD_READID 0x90 /* ReadID */ +#define CMD_READID2 0x91 /* Read extended ID */ +#define CMD_WRITE 0x80 /* Write phase 1 */ +#define CMD_WRITE2 0x10 /* Write phase 2 */ +#define CMD_ERASE 0x60 /* Erase phase 1 */ +#define CMD_ERASE2 0xd0 /* Erase phase 2 */ +#define CMD_STATUS 0x70 /* Status read */ +#define CMD_RESET 0xff /* Reset */ + +/* Status bit pattern */ +#define STATUS_READY 0x40 /* Ready */ +#define STATUS_ERROR 0x01 /* Error */ + + +#define NFLASH_DEV_WIDTH 8 +#ifdef MV_LARGE_PAGE +#define BOOTER_PAGE_NUM 2 +#define BOOTER_BASE 0x00020000 + PAGE_SIZE +#else +#define BOOTER_PAGE_NUM 5 +#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE) +#endif /* MV_LARGE_PAGE */ +#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) + +#undef INTER_REGS_BASE +#define INTER_REGS_BASE 0xd0000000 + + +#if defined(MV_BOOTROM) +#if defined(MV_88F6082) +#define NAND_FLASH_BASE 0xD8000000 +#endif +#if defined(MV_88F5182) +#define NAND_FLASH_BASE 0xf0000000 +#endif +#else +#define NAND_FLASH_BASE 0xffff0000 +#endif /* defined(MV_BOOTROM) */ + +#if 0 +#define NBOOT_UART_CHAN 0 +#define NBOOT_BAUDRATE 115200 +#define NBOOT_TIMER_NUM 0 + + +/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */ +#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */ + +/* Load General Purpose Register (GPR) with 32-bit constant value */ +#define GPR_LOAD(reg, val) \ + mov reg, $(val & 0xFF) ;\ + orr reg, reg, $(val & 0xFF00) ;\ + orr reg, reg, $(val & 0xFF0000) ;\ + orr reg, reg, $(val & 0xFF000000) + +/* Register Read/Write */ +#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \ + ldr toReg, [baseReg, $(regOffs & 0xFFF)] + +#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \ + str fromReg, [baseReg, $(regOffs & 0xFFF)] + + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_32BIT_LE(X) (X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif +#endif + +#endif /* __INCnBootstraph */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap_LP.S u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap_LP.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap_LP.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap_LP.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,335 @@ +#define MV_ASMLANGUAGE +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "nBootstrap.h" + + +/* #define NAND_DEBUG */ +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + +#ifdef NAND_CTRL_88F528x + + /* Load CPU controller base address 0xD0020000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x20000 + + MV_REG_READ_ASM (r1, r2, INTER_REGS_BASE + 0x20120) + bic r1, r1, #MV_32BIT_LE(0x7F00) + orr r1, r1, #MV_32BIT_LE(0x8200) + bic r1, r1, #MV_32BIT_LE(0x007F) + orr r1, r1, #MV_32BIT_LE(0x001b) + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x20120) + + /* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */ + MV_REG_READ_ASM (r1, r2, INTER_REGS_BASE + 0x20100) + bic r1, r1, #MV_32BIT_LE(0xFF00) + orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK) + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x20100) + +#endif /* NAND_CTRL_88F528x */ + + /* lock I-Cache */ + mrc p15, 0, r8, c9, c0, 1 + orr r8, r8, #0xf + mcr p15, 0, r8, c9, c0, 1 + + /* Start load code into I-Cache */ + mov r2, #0x500 + mov r8, pc +.align 5 + bic r8, #0x1f + add r8, r8, #32 +load_loop: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0xf0ffffff + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x104) + mov r1, #0x1000000 + MV_REG_WRITE_ASM(r1, r2, INTER_REGS_BASE + 0x100) +#endif + + /* DRAM memory initialization */ + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Write to SDRAM coniguration register */ +#ifndef MV_88W8660 + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) +#else + GPR_LOAD(r1, MV_32BIT_LE((SDRAM_CONFIG_REG_DV & ~(0x40)))) +#endif /* MV_88W8660 */ + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG) + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 registers pad calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_CONFIG_REG) + tst r1, #SDRAM_DTYPE_DDR2 + beq ddr1PadCal + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV) + b next + +ddr1PadCal: + mov r3, #MV_32BIT_LE(DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR1_DATA_PAD_STRENGTH_TYPICAL_DV) + +next: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r1, r3, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r1, r4, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + +#ifndef MV_88W8660 + /* Write Dunit FTDLL Configuration Register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_FTDLL_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_FTDLL_CONFIG_REG) +#endif /* MV_88W8660 */ + + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0)) + + /* Close SDRAM bank 1,2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #BOOTER_BASE + +#ifdef DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* init */ + mov r2, #0x1 /* start with page 1 */ + mov r3, #BOOTER_BASE /* start of DRAM buffer */ + GPR_LOAD(r5, NAND_FLASH_BASE) + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r7, #CMD_START_READ + mov r9, #CMD_RESET + mov r4, #PAGE_SIZE /* Byte counter */ + + +startRead: + /* issue reset command */ + strb r9, [r5, #NAND_CMD_PORT] + + mov r9, #0x1000000 +loop_delay1: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay1 + + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r7, [r5, #NAND_CMD_PORT] + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x3000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + /* Delay of at least 25uSec (NAND flash tR) */ + mov r9, #0x1000000 +loop_delay3: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay3 + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x4000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + + /* now perform reading */ + mov r0, r5 + +copy_loop1: + sub r4, r4, #16 /* 4 dwords * 4 bytes */ + ldmia r0!, {r6-r9} + stmia r3!, {r6-r9} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x5000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* Set up the stack */ +stack_setup: + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + /* jump to new code */ + mov pc, lr + +.align 10 +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nandBoot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap.S u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/nBootstrap.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/nBootstrap.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,20 @@ +#define MV_ASMLANGUAGE +#include "nBootstrap.h" + + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + ldr r0, =BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nand_boot + mov pc, lr diff -Naur u-boot-2009.08.orig/board/marvell/mv_armada_xp/platform.S u-boot-2009.08/board/marvell/mv_armada_xp/platform.S --- u-boot-2009.08.orig/board/marvell/mv_armada_xp/platform.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_armada_xp/platform.S 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,95 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include +#include +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvAhbToMbusRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCtrlEnvAsm.h" + +.globl lowlevel_init + +/************************************************/ +/* lowlevel_init * +/************************************************/ + +lowlevel_init: + mov r2, lr + + /* Multicore support */ + mrc p15, 0, r0, c0, c0, 5 + /* Check if we are CPU0 or CPU1 */ + cmp r0, #0x0 + bne done_cpu1 + +#if 0 + /* change CPU0 reg base to 0xf1000000 */ + + /* First descrease size of CS[2] to prevent overlap with 0xF100.0000 */ + MV_DV_REG_READ_ASM(r4, r1, 0x200B0) + bic r4, r4, #0x07F00000 + MV_DV_REG_WRITE_ASM(r4, r1, 0x200B0) + + ldr r4, =MV_REGS + MV_DV_REG_WRITE_ASM(r4, r1, 0x20080) + /* This is kind of barrier... */ + ldr r4, =MV_REGS + MV_REG_WRITE_ASM (r4, r1, 0x20080) + + /* Set 7-Segment to '1' */ + /* By default, 7-segment connected to CS[2] base 0xF000.000 */ + mov r4, #0xf0000000 + ldr r4, [r4, #(1 << 4)] +#endif + +#if defined(MV_STATIC_DRAM_ON_BOARD) +/* TODO: alior: we still not supporting non bootrom mode on u-boot */ + bl _mvDramIfStaticInit + + bl _mvDramIfBasicInit +#endif + bl done + +done: + +#ifdef CFU_DRAM_BYPASS + /* allow accessing to DRAM from XBAR */ + ldr r4, =0x1fff0e01 /* Set DRAM CS[0] size in P-unit (default) */ + MV_REG_WRITE_ASM(r4, r1, 0x200e8) + ldr r4, =0x20000000 /* Set DRAM CS[1] base in P-unit */ + MV_REG_WRITE_ASM(r4, r1, 0x200e4) + ldr r4, =0x1fff0d01 /* Set DRAM CS[1] size in P-unit */ + MV_REG_WRITE_ASM(r4, r1, 0x200e0) +#endif + + /* Set 7-Segment to '2' */ + /* By default, 7-segment connected to CS[2] base 0xF000.000 */ + mov r4, #0xf0000000 + ldr r4, [r4, #(2 << 4)] + + mov lr, r2 + +done_cpu1: + mov pc, lr + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.c u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,341 @@ +/* rijndael-alg-ref.c v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvAesAlg.h" +#include "mvAesBoxes.dat" + +MV_U8 mul1(MV_U8 aa, MV_U8 bb); +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); +void ShiftRow128Enc(MV_U8 a[4][MAXBC]); +void ShiftRow128Dec(MV_U8 a[4][MAXBC]); +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); +void InvMixColumn(MV_U8 a[4][MAXBC]); + +#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) + +MV_U8 mul1(MV_U8 aa, MV_U8 bb) +{ + return mask[bb] & Alogtable[aa + Logtable[bb]]; +} + +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) +{ + /* Exor corresponding text input and round key input bytes + */ + ((MV_U32 *) (&(a[0][0])))[0] ^= ((MV_U32 *) (&(rk[0][0])))[0]; + ((MV_U32 *) (&(a[1][0])))[0] ^= ((MV_U32 *) (&(rk[1][0])))[0]; + ((MV_U32 *) (&(a[2][0])))[0] ^= ((MV_U32 *) (&(rk[2][0])))[0]; + ((MV_U32 *) (&(a[3][0])))[0] ^= ((MV_U32 *) (&(rk[3][0])))[0]; + +} + +void ShiftRow128Enc(MV_U8 a[4][MAXBC]) +{ + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][1]; + tmp[1] = a[1][2]; + tmp[2] = a[1][3]; + tmp[3] = a[1][0]; + + ((MV_U32 *) (&(a[1][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32 *) (&(a[2][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + tmp[0] = a[3][3]; + tmp[1] = a[3][0]; + tmp[2] = a[3][1]; + tmp[3] = a[3][2]; + + ((MV_U32 *) (&(a[3][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void ShiftRow128Dec(MV_U8 a[4][MAXBC]) +{ + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][3]; + tmp[1] = a[1][0]; + tmp[2] = a[1][1]; + tmp[3] = a[1][2]; + + ((MV_U32 *) (&(a[1][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32 *) (&(a[2][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + + tmp[0] = a[3][1]; + tmp[1] = a[3][2]; + tmp[2] = a[3][3]; + tmp[3] = a[3][0]; + + ((MV_U32 *) (&(a[3][0])))[0] = ((MV_U32 *) (&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) +{ + /* Replace every byte of the input by the byte at that place + * in the nonlinear S-box + */ + int i, j; + + for (i = 0; i < 4; i++) + for (j = 0; j < 4; j++) + a[i][j] = box[a[i][j]]; +} + +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) +{ + /* Mix the four bytes of every column in a linear way + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for (j = 0; j < 4; j++) { + b[0][j] = mul(25, a[0][j]) ^ mul(1, a[1][j]) ^ a[2][j] ^ a[3][j]; + b[1][j] = mul(25, a[1][j]) ^ mul(1, a[2][j]) ^ a[3][j] ^ a[0][j]; + b[2][j] = mul(25, a[2][j]) ^ mul(1, a[3][j]) ^ a[0][j] ^ a[1][j]; + b[3][j] = mul(25, a[3][j]) ^ mul(1, a[0][j]) ^ a[1][j] ^ a[2][j]; + } + for (i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j]; */ + ((MV_U32 *)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; +} + +void InvMixColumn(MV_U8 a[4][MAXBC]) +{ + /* Mix the four bytes of every column in a linear way + * This is the opposite operation of Mixcolumn + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for (j = 0; j < 4; j++) { + b[0][j] = mul(223, a[0][j]) ^ mul(104, a[1][j]) ^ mul(238, a[2][j]) ^ mul(199, a[3][j]); + b[1][j] = mul(223, a[1][j]) ^ mul(104, a[2][j]) ^ mul(238, a[3][j]) ^ mul(199, a[0][j]); + b[2][j] = mul(223, a[2][j]) ^ mul(104, a[3][j]) ^ mul(238, a[0][j]) ^ mul(199, a[1][j]); + b[3][j] = mul(223, a[3][j]) ^ mul(104, a[0][j]) ^ mul(238, a[1][j]) ^ mul(199, a[2][j]); + } + for (i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j]; */ + ((MV_U32 *) (&(a[i][0])))[0] = ((MV_U32 *) (&(b[i][0])))[0]; +} + +int rijndaelKeySched(MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS + 1][4][MAXBC]) +{ + /* Calculate the necessary round keys + * The number of calculations depends on keyBits and blockBits + */ + int KC, BC, ROUNDS; + int i, j, t, rconpointer = 0; + MV_U8 tk[4][MAXKC]; + + switch (keyBits) { + case 128: + KC = 4; + break; + case 192: + KC = 6; + break; + case 256: + KC = 8; + break; + default: + return (-1); + } + + switch (blockBits) { + case 128: + BC = 4; + break; + case 192: + BC = 6; + break; + case 256: + BC = 8; + break; + default: + return (-2); + } + + switch (keyBits >= blockBits ? keyBits : blockBits) { + case 128: + ROUNDS = 10; + break; + case 192: + ROUNDS = 12; + break; + case 256: + ROUNDS = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + for (j = 0; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] = k[i][j]; + t = 0; + /* copy values into round key array */ + for (j = 0; (j < KC) && (t < (ROUNDS + 1) * BC); j++, t++) + for (i = 0; i < 4; i++) + W[t / BC][i][t % BC] = tk[i][j]; + + while (t < (ROUNDS + 1) * BC) { /* while not enough round key material calculated */ + /* calculate new values */ + for (i = 0; i < 4; i++) + tk[i][0] ^= S[tk[(i + 1) % 4][KC - 1]]; + tk[0][0] ^= rcon[rconpointer++]; + + if (KC != 8) + for (j = 1; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + else { + for (j = 1; j < KC / 2; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + for (i = 0; i < 4; i++) + tk[i][KC / 2] ^= S[tk[i][KC / 2 - 1]]; + for (j = KC / 2 + 1; j < KC; j++) + for (i = 0; i < 4; i++) + tk[i][j] ^= tk[i][j - 1]; + } + /* copy values into round key array */ + for (j = 0; (j < KC) && (t < (ROUNDS + 1) * BC); j++, t++) + for (i = 0; i < 4; i++) + W[t / BC][i][t % BC] = tk[i][j]; + } + + return 0; +} + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds) +{ + /* Encryption of one block. + */ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* begin with a key addition + */ + + KeyAddition(a, rk[0], BC); + + /* ROUNDS-1 ordinary rounds + */ + for (r = 1; r < ROUNDS; r++) { + Substitution(a, S); + ShiftRow128Enc(a); + MixColumn(a, rk[r]); + /*KeyAddition(a,rk[r],BC); */ + } + + /* Last round is special: there is no MixColumn + */ + Substitution(a, S); + ShiftRow128Enc(a); + KeyAddition(a, rk[ROUNDS], BC); + + return 0; +} + +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds) +{ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* To decrypt: apply the inverse operations of the encrypt routine, + * in opposite order + * + * (KeyAddition is an involution: it 's equal to its inverse) + * (the inverse of Substitution with table S is Substitution with the inverse table of S) + * (the inverse of Shiftrow is Shiftrow over a suitable distance) + */ + + /* First the special round: + * without InvMixColumn + * with extra KeyAddition + */ + KeyAddition(a, rk[ROUNDS], BC); + ShiftRow128Dec(a); + Substitution(a, Si); + + /* ROUNDS-1 ordinary rounds + */ + for (r = ROUNDS - 1; r > 0; r--) { + KeyAddition(a, rk[r], BC); + InvMixColumn(a); + ShiftRow128Dec(a); + Substitution(a, Si); + + } + + /* End with the extra key addition + */ + + KeyAddition(a, rk[0], BC); + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.h u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesAlg.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesAlg.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,24 @@ +/* rijndael-alg-ref.h v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + */ +#ifndef __RIJNDAEL_ALG_H +#define __RIJNDAEL_ALG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXBC (128/32) +#define MAXKC (256/32) +#define MAXROUNDS 14 + + int rijndaelKeySched(MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS + 1][4][MAXBC]); + int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds); + int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS + 1][4][MAXBC], int rounds); + +#ifdef __cplusplus +} +#endif +#endif /* __RIJNDAEL_ALG_H */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesApi.c u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesApi.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesApi.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesApi.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,270 @@ +/* rijndael-api-ref.c v2.1 April 2000 + * Reference ANSI C code + * authors: v2.0 Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * v2.1 Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvCommon.h" +#include "mvOs.h" + +#include "mvAes.h" +#include "mvAesAlg.h" + +/* Defines: + Add any additional defines you need +*/ + +#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ +#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ +#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ + +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) +{ + MV_U8 W[MAXROUNDS + 1][4][MAXBC]; + MV_U8 k[4][MAXKC]; + MV_U8 j; + int i, rounds, KC; + + if (expandedKey == NULL) + return AES_BAD_KEY_INSTANCE; + + if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) + return AES_BAD_KEY_MAT; + + if (keyMaterial == NULL) + return AES_BAD_KEY_MAT; + + /* initialize key schedule: */ + for (i = 0; i < keyLen / 8; i++) { + j = keyMaterial[i]; + k[i % 4][i / 4] = j; + } + + rijndaelKeySched(k, keyLen, blockLen, W); +#ifdef MV_AES_DEBUG + { + MV_U8 *pW = &W[0][0][0]; + int x; + + mvOsPrintf("Expended Key: size = %d\n", sizeof(W)); + for (i = 0; i < sizeof(W); i++) + mvOsPrintf("%02x ", pW[i]); + + for (i = 0; i < MAXROUNDS + 1; i++) { + mvOsPrintf("\n Round #%02d: ", i); + for (x = 0; x < MAXBC; x++) + mvOsPrintf("%02x%02x%02x%02x ", W[i][0][x], W[i][1][x], W[i][2][x], W[i][3][x]); + mvOsPrintf("\n"); + } + } +#endif /* MV_AES_DEBUG */ + switch (keyLen) { + case 128: + rounds = 10; + KC = 4; + break; + case 192: + rounds = 12; + KC = 6; + break; + case 256: + rounds = 14; + KC = 8; + break; + default: + return (-1); + } + + for (i = 0; i < MAXBC; i++) + for (j = 0; j < 4; j++) + expandedKey[i * 4 + j] = W[rounds][j][i]; + + for (; i < KC; i++) + for (j = 0; j < 4; j++) + expandedKey[i * 4 + j] = W[rounds - 1][j][i + MAXBC - KC]; + + return 0; +} + +int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher) +{ + int i, j, t; + MV_U8 block[4][MAXBC]; + int rounds; + char *input, *outBuffer; + + input = (char *)plain; + outBuffer = (char *)cipher; + + /* check parameter consistency: */ + if ((expandedKey == NULL) || ((keyLen != 128) && (keyLen != 192) && (keyLen != 256))) + return AES_BAD_KEY_MAT; + + if ((mode != MODE_ECB && mode != MODE_CBC)) + return AES_BAD_CIPHER_STATE; + + switch (keyLen) { + case 128: + rounds = 10; + break; + case 192: + rounds = 12; + break; + case 256: + rounds = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + switch (mode) { + case MODE_ECB: + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse input stream into rectangular array */ + block[t][j] = input[16 * i + 4 * j + t] & 0xFF; + } + rijndaelEncrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + case MODE_CBC: + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse initial value into rectangular array */ + block[t][j] = IV[t + 4 * j] & 0xFF; + } + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) + /* parse input stream into rectangular array and exor with + IV or the previous ciphertext */ + block[t][j] ^= input[16 * i + 4 * j + t] & 0xFF; + } + rijndaelEncrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + default: + return AES_BAD_CIPHER_STATE; + } + + return 0; +} + +int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *srcData, int numBlocks, MV_U32 *dstData) +{ + int i, j, t; + MV_U8 block[4][MAXBC]; + MV_U8 iv[4][MAXBC]; + int rounds; + char *input, *outBuffer; + + input = (char *)srcData; + outBuffer = (char *)dstData; + + if (expandedKey == NULL) + return AES_BAD_KEY_MAT; + + /* check parameter consistency: */ + if (keyLen != 128 && keyLen != 192 && keyLen != 256) + return AES_BAD_KEY_MAT; + + if ((mode != MODE_ECB && mode != MODE_CBC)) + return AES_BAD_CIPHER_STATE; + + switch (keyLen) { + case 128: + rounds = 10; + break; + case 192: + rounds = 12; + break; + case 256: + rounds = 14; + break; + default: + return (-3); /* this cannot happen */ + } + + switch (mode) { + case MODE_ECB: + for (i = 0; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + block[t][j] = input[16 * i + 4 * j + t] & 0xFF; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + for (j = 0; j < 4; j++) { + /* parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) + outBuffer[16 * i + 4 * j + t] = (MV_U8) block[t][j]; + } + } + break; + + case MODE_CBC: + /* first block */ + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + block[t][j] = input[4 * j + t] & 0xFF; + iv[t][j] = block[t][j]; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + + for (j = 0; j < 4; j++) { + /* exor the IV and parse rectangular array into output ciphertext bytes */ + for (t = 0; t < 4; t++) { + outBuffer[4 * j + t] = (MV_U8) (block[t][j] ^ IV[t + 4 * j]); + IV[t + 4 * j] = iv[t][j]; + } + } + + /* next blocks */ + for (i = 1; i < numBlocks; i++) { + for (j = 0; j < 4; j++) { + for (t = 0; t < 4; t++) { + /* parse input stream into rectangular array */ + iv[t][j] = input[16 * i + 4 * j + t] & 0xFF; + block[t][j] = iv[t][j]; + } + } + rijndaelDecrypt128(block, (MV_U8(*)[4][MAXBC]) expandedKey, rounds); + + for (j = 0; j < 4; j++) { + /* exor previous ciphertext block and parse rectangular array + into output ciphertext bytes */ + for (t = 0; t < 4; t++) { + outBuffer[16 * i + 4 * j + t] = (MV_U8) (block[t][j] ^ IV[t + 4 * j]); + IV[t + 4 * j] = iv[t][j]; + } + } + } + break; + + default: + return AES_BAD_CIPHER_STATE; + } + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAesBoxes.dat 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,125 @@ +static MV_U8 mask[256] = { + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static MV_U8 Logtable[256] = { + 0, 0, 25, 1, 50, 2, 26, 198, 75, 199, 27, 104, 51, 238, 223, 3, + 100, 4, 224, 14, 52, 141, 129, 239, 76, 113, 8, 200, 248, 105, 28, 193, + 125, 194, 29, 181, 249, 185, 39, 106, 77, 228, 166, 114, 154, 201, 9, 120, + 101, 47, 138, 5, 33, 15, 225, 36, 18, 240, 130, 69, 53, 147, 218, 142, + 150, 143, 219, 189, 54, 208, 206, 148, 19, 92, 210, 241, 64, 70, 131, 56, + 102, 221, 253, 48, 191, 6, 139, 98, 179, 37, 226, 152, 34, 136, 145, 16, + 126, 110, 72, 195, 163, 182, 30, 66, 58, 107, 40, 84, 250, 133, 61, 186, + 43, 121, 10, 21, 155, 159, 94, 202, 78, 212, 172, 229, 243, 115, 167, 87, + 175, 88, 168, 80, 244, 234, 214, 116, 79, 174, 233, 213, 231, 230, 173, 232, + 44, 215, 117, 122, 235, 22, 11, 245, 89, 203, 95, 176, 156, 169, 81, 160, + 127, 12, 246, 111, 23, 196, 73, 236, 216, 67, 31, 45, 164, 118, 123, 183, + 204, 187, 62, 90, 251, 96, 177, 134, 59, 82, 161, 108, 170, 85, 41, 157, + 151, 178, 135, 144, 97, 190, 220, 252, 188, 149, 207, 205, 55, 63, 91, 209, + 83, 57, 132, 60, 65, 162, 109, 71, 20, 42, 158, 93, 86, 242, 211, 171, + 68, 17, 146, 217, 35, 32, 46, 137, 180, 124, 184, 38, 119, 153, 227, 165, + 103, 74, 237, 222, 197, 49, 254, 24, 13, 99, 140, 128, 192, 247, 112, 7, +}; + +static MV_U8 Alogtable[512] = { + 1, 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53, + 95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170, + 229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49, + 83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205, + 76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136, + 131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154, + 181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163, + 254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160, + 251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65, + 195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117, + 159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128, + 155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84, + 252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202, + 69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14, + 18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23, + 57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1, + + 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53, + 95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170, + 229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49, + 83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205, + 76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136, + 131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154, + 181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163, + 254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160, + 251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65, + 195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117, + 159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128, + 155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84, + 252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202, + 69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14, + 18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23, + 57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1, + +}; + +static MV_U8 S[256] = { + 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, + 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, + 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, + 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, + 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, + 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, + 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, + 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, + 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, + 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, + 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, + 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, + 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, + 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, + 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, + 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22, +}; + +static MV_U8 Si[256] = { + 82, 9, 106, 213, 48, 54, 165, 56, 191, 64, 163, 158, 129, 243, 215, 251, + 124, 227, 57, 130, 155, 47, 255, 135, 52, 142, 67, 68, 196, 222, 233, 203, + 84, 123, 148, 50, 166, 194, 35, 61, 238, 76, 149, 11, 66, 250, 195, 78, + 8, 46, 161, 102, 40, 217, 36, 178, 118, 91, 162, 73, 109, 139, 209, 37, + 114, 248, 246, 100, 134, 104, 152, 22, 212, 164, 92, 204, 93, 101, 182, 146, + 108, 112, 72, 80, 253, 237, 185, 218, 94, 21, 70, 87, 167, 141, 157, 132, + 144, 216, 171, 0, 140, 188, 211, 10, 247, 228, 88, 5, 184, 179, 69, 6, + 208, 44, 30, 143, 202, 63, 15, 2, 193, 175, 189, 3, 1, 19, 138, 107, + 58, 145, 17, 65, 79, 103, 220, 234, 151, 242, 207, 206, 240, 180, 230, 115, + 150, 172, 116, 34, 231, 173, 53, 133, 226, 249, 55, 232, 28, 117, 223, 110, + 71, 241, 26, 113, 29, 41, 197, 137, 111, 183, 98, 14, 170, 24, 190, 27, + 252, 86, 62, 75, 198, 210, 121, 32, 154, 219, 192, 254, 120, 205, 90, 244, + 31, 221, 168, 51, 136, 7, 199, 49, 177, 18, 16, 89, 39, 128, 236, 95, + 96, 81, 127, 169, 25, 181, 74, 13, 45, 229, 122, 159, 147, 201, 156, 239, + 160, 224, 59, 77, 174, 42, 245, 176, 200, 235, 187, 60, 131, 83, 153, 97, + 23, 43, 4, 126, 186, 119, 214, 38, 225, 105, 20, 99, 85, 33, 12, 125, +}; + +/* +static MV_U8 iG[4][4] = { +{0x0e, 0x09, 0x0d, 0x0b}, +{0x0b, 0x0e, 0x09, 0x0d}, +{0x0d, 0x0b, 0x0e, 0x09}, +{0x09, 0x0d, 0x0b, 0x0e}, +}; +*/ +static MV_U32 rcon[30] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, + 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, +}; diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAes.h u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAes.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/AES/mvAes.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/AES/mvAes.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,70 @@ +/* mvAes.h v2.0 August '99 +* Reference ANSI C code +*/ + +/* AES Cipher header file for ANSI C Submissions + Lawrence E. Bassham III + Computer Security Division + National Institute of Standards and Technology + + April 15, 1998 + + This sample is to assist implementers developing to the Cryptographic + API Profile for AES Candidate Algorithm Submissions. Please consult this + document as a cross-reference. + + ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE + MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH + THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT + BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE + IMPLEMENTATION SPECIFIC INFORMATION. +*/ + +/* Includes: + Standard include files +*/ + +#ifndef __mvAes_h__ +#define __mvAes_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvOs.h" + +/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ + +/* Key direction is invalid, e.g., unknown value */ +#define AES_BAD_KEY_DIR -1 + +/* Key material not of correct length */ +#define AES_BAD_KEY_MAT -2 + +/* Key passed is not valid */ +#define AES_BAD_KEY_INSTANCE -3 + +/* Params struct passed to cipherInit invalid */ +#define AES_BAD_CIPHER_MODE -4 + +/* Cipher in wrong state (e.g., not initialized) */ +#define AES_BAD_CIPHER_STATE -5 + +#define AES_BAD_CIPHER_INSTANCE -7 + +/* Function protoypes */ +/* CHANGED: makeKey(): parameter blockLen added + this parameter is absolutely necessary if you want to + setup the round keys in a variable block length setting + cipherInit(): parameter blockLen added (for obvious reasons) + */ + int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); + int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + +#ifdef __cplusplus +} +#endif +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaAddrDec.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaAddrDec.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,295 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvCesa.h" +#include "mvCesaRegs.h" + +#if (MV_CESA_VERSION >= 2) +MV_TARGET tdmaAddrDecPrioTable[] = { +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#ifdef MV_INCLUDE_PEX1 + PEX1_MEM, +#endif +#endif + + TBL_TERM +}; + +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvCesaWinRead. +* +* DESCRIPTION: +* Read TDMA target address window. +* +* INPUT: +* unit - The unit ID. +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCesaWinRead(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin) +{ + MV_U32 sizeReg, baseReg; + MV_U32 size; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", __func__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ(MV_CESA_TDMA_BASE_ADDR_REG(winNum)); + sizeReg = MV_REG_READ(MV_CESA_TDMA_WIN_CTRL_REG(winNum)); + + /* Check if window is enabled */ + if (sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + pDecWin->targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + pDecWin->attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + + size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + pDecWin->addrWin.size = (size + 1) * (1 << MV_CESA_TDMA_WIN_SIZE_OFFSET); + pDecWin->addrWin.baseLow = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + pDecWin->addrWin.baseHigh = 0; + } else { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaTdmaWinWrite +* +* DESCRIPTION: +* This function writes the address decoding registers according to the +* given window configuration. +* +* INPUT: +* unit - The unit ID. +* pAddrDecWin - CESA TDMA target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_BAD_PARAM if winNum is invalid or size is not a power of 2. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCesaTdmaWinWrite(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin) +{ + MV_U32 sizeReg, baseReg; + MV_U32 size; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) { + mvOsPrintf("%s: ERR. Window %d overlap\n", __func__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d.\n" + "Address 0x%08x is unaligned to size 0x%x.\n", + winNum, pDecWin->addrWin.baseLow, pDecWin->addrWin.size); + return MV_ERROR; + } + + if (!MV_IS_POWER_OF_2(pDecWin->addrWin.size)) { + mvOsPrintf("mvCesaTdmaWinWrite: Error setting CESA window %d. " + "Window size is not a power to 2.", winNum); + return MV_BAD_PARAM; + } + + size = (pDecWin->addrWin.size / (1 << MV_CESA_TDMA_WIN_SIZE_OFFSET)) - 1; + + /* set Size, Attributes and TargetID */ + sizeReg = (((pDecWin->targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((pDecWin->attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + else + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + + /* Update Base value */ + baseReg = (pDecWin->addrWin.baseLow & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE(MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE(MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_UNIT_WIN_INFO addrDecWin; + + for (winNumIndex = 0; winNumIndex < MV_CESA_TDMA_ADDR_DEC_WIN; winNumIndex++) { + /* Do not check window itself */ + if (winNumIndex == winNum) + continue; + + /* Get window parameters */ + if (MV_OK != mvCesaWinRead(0, winNumIndex, &addrDecWin)) { + mvOsPrintf("%s: ERR. TargetWinGet failed\n", __func__); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (addrDecWin.enable == MV_FALSE) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + return MV_TRUE; + } + return MV_FALSE; +} + +MV_STATUS mvCesaTdmaWinInit(MV_UNIT_WIN_INFO *addrWinMap) +{ + MV_U32 winNum; + MV_UNIT_WIN_INFO *addrDecWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for (winNum = 0; winNum < MV_CESA_TDMA_ADDR_DEC_WIN; winNum++) + MV_REG_BIT_RESET(MV_CESA_TDMA_WIN_CTRL_REG(winNum), MV_CESA_TDMA_WIN_ENABLE_MASK); + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while ((tdmaAddrDecPrioTable[winPrioIndex] != TBL_TERM) && (winNum < MV_CESA_TDMA_ADDR_DEC_WIN)) { + + addrDecWin = &addrWinMap[tdmaAddrDecPrioTable[winPrioIndex]]; + if (addrDecWin->enable == MV_TRUE) { + if (MV_OK != mvCesaTdmaWinWrite(0, winNum, addrDecWin)) { + mvOsPrintf("mvCesaTdmaWinSet FAILED: winNum=%d\n", winNum); + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} +#endif /* MV_CESA_VERSION >= 2 */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,2884 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysCesaConfig.h" +#include "mvCesaRegs.h" +#include "mvCesa.h" +#include "AES/mvAes.h" +#include "mvMD5.h" +#include "mvSHA1.h" + +#undef CESA_DEBUG + +/********** Global variables **********/ + +/* If request size is more than MV_CESA_MAX_BUF_SIZE the + * request is processed as fragmented request. + */ + +MV_CESA_STATS cesaStats; +short cesaLastSid = -1; +MV_CESA_SA **pCesaSAD = NULL; +MV_U32 cesaMaxSA = 0; +MV_CESA_REQ *pCesaReqFirst = NULL; +MV_CESA_REQ *pCesaReqLast = NULL; +MV_CESA_REQ *pCesaReqEmpty = NULL; +MV_CESA_REQ *pCesaReqProcess = NULL; +int cesaQueueDepth = 0; +int cesaReqResources = 0; + +MV_CESA_SRAM_MAP *cesaSramVirtPtr = NULL; +void *cesaOsHandle = NULL; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + +#if (MV_CESA_VERSION < 3) +#error "CHAIN mode supported only when MV_CESA_VERSION is 3 or larger" +#endif + +MV_U32 cesaChainLength = 0; +int chainReqNum = 0; +MV_U32 chainIndex = 0; +MV_CESA_REQ *pNextActiveChain = 0; +MV_CESA_REQ *pEndCurrChain = 0; +MV_BOOL isFirstReq = MV_TRUE; +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + +static MV_CESA_HAL_DATA cesaHalData; + +static INLINE MV_U8 *mvCesaSramAddrGet(void) +{ + return (MV_U8 *) cesaHalData.sramPhysBase; +} + +static INLINE MV_ULONG mvCesaSramVirtToPhys(void *pDev, MV_U8 *pSramVirt) +{ + return (MV_ULONG) (pSramVirt - cesaHalData.sramVirtBase) + cesaHalData.sramPhysBase; +} + +/* Internal Function prototypes */ + +static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, int macTotalLen, + MV_CESA_REQ *pCesaReq, MV_DMA_DESC *pDmaDesc); + +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); + +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush); + +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]); + +static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ *pReq, MV_CESA_SA *pSA, int macDataSize); + +static MV_CESA_COMMAND *mvCesaCtrModeInit(void); + +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); +static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); + +static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ *pReq); +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ *pReq, MV_U8 frag); + +static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd, MV_U8 *pFixOffset); +static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd); + +static INLINE void mvCesaFragSizeFind(MV_CESA_SA *pSA, MV_CESA_REQ *pReq, + int cryptoOffset, int macOffset, + int *pCopySize, int *pCryptoDataSize, int *pMacDataSize); +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF *pMbuf, int offset, int size); + +/* Go to the next request in the request queue */ +static INLINE MV_CESA_REQ *MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ *pReq) +{ + if (pReq == pCesaReqLast) + return pCesaReqFirst; + + return (pReq + 1); +} + +/* Go to the previous request in the request queue */ +static INLINE MV_CESA_REQ *MV_CESA_REQ_PREV_PTR(MV_CESA_REQ *pReq) +{ + if (pReq == pCesaReqFirst) + return pCesaReqLast; + + return (pReq - 1); +} + +static INLINE void mvCesaReqProcessStart(MV_CESA_REQ *pReq) +{ + int frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->state = MV_CESA_CHAIN; +#else + pReq->state = MV_CESA_PROCESS; +#endif + + cesaStats.startCount++; + + if (pReq->fragMode == MV_CESA_FRAG_NONE) { + frag = 0; + } else { + frag = pReq->frags.nextFrag; + pReq->frags.nextFrag++; + } +#if (MV_CESA_VERSION >= 2) + /* Enable TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, + (MV_U32) mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#else + /* Enable IDMA engine */ + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), + (MV_U32) mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#endif /* MV_CESA_VERSION >= 2 */ + +#if defined(MV_BRIDGE_SYNC_REORDER) + mvOsBridgeReorderWA(); +#endif + + /* Start Accelerator */ + MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); +} + +/******************************************************************************* +* mvCesaHalInit - Initialize the CESA driver +* +* DESCRIPTION: +* This function initialize the CESA driver. +* 1) Session database +* 2) Request queue +* 4) DMA descriptor lists - one list per request. Each list +* has MV_CESA_MAX_DMA_DESC descriptors. +* +* INPUT: +* numOfSession - maximum number of supported sessions +* queueDepth - number of elements in the request queue. +* osHandle - A handle used by the OS to allocate memory for the +* module (Passed to the OS Services layer) +* +* RETURN: +* MV_OK - Success +* MV_NO_RESOURCE - Fail, can't allocate resources: +* Session database, request queue, +* DMA descriptors list, LRU cache database. +* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. +* +*******************************************************************************/ +MV_STATUS mvCesaHalInit(int numOfSession, int queueDepth, void *osHandle, MV_CESA_HAL_DATA *halData) +{ + int i, req; + MV_U32 descOffsetReg, configReg; + + cesaOsHandle = osHandle; + cesaSramVirtPtr = (MV_CESA_SRAM_MAP *) (halData->sramVirtBase + halData->sramOffset); + + mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSramMap=%p\n", numOfSession, queueDepth, cesaSramVirtPtr); + + /* Create initial Session database */ + pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA *) * numOfSession); + if (pCesaSAD == NULL) { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", + sizeof(MV_CESA_SA *) * numOfSession, numOfSession); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaSAD, 0, sizeof(MV_CESA_SA *) * numOfSession); + cesaMaxSA = numOfSession; + + /* Create request queue */ + pCesaReqFirst = mvOsMalloc(sizeof(MV_CESA_REQ) * queueDepth); + if (pCesaReqFirst == NULL) { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d requests\n", + sizeof(MV_CESA_REQ) * queueDepth, queueDepth); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaReqFirst, 0, sizeof(MV_CESA_REQ) * queueDepth); + pCesaReqEmpty = pCesaReqFirst; + pCesaReqLast = pCesaReqFirst + (queueDepth - 1); + pCesaReqProcess = pCesaReqEmpty; + cesaQueueDepth = queueDepth; + cesaReqResources = queueDepth; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + cesaChainLength = MAX_CESA_CHAIN_LENGTH; +#endif + + /* pSramBase must be 8 byte aligned */ + if (MV_IS_NOT_ALIGN((MV_ULONG) cesaSramVirtPtr, 8)) { + mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", cesaSramVirtPtr); + mvCesaFinish(); + return MV_NOT_ALIGNED; + } + + /* Clear registers */ + MV_REG_WRITE(MV_CESA_CFG_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_MASK_REG, 0); + + /* Initialize DMA descriptor lists for all requests in Request queue */ + descOffsetReg = configReg = 0; + for (req = 0; req < queueDepth; req++) { + int frag; + MV_CESA_REQ *pReq; + MV_DMA_DESC *pDmaDesc; + + pReq = &pCesaReqFirst[req]; + + pReq->cesaDescBuf.bufSize = sizeof(MV_CESA_DESC) * MV_CESA_MAX_REQ_FRAGS + CPU_D_CACHE_LINE_SIZE; + + pReq->cesaDescBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle, pReq->cesaDescBuf.bufSize, + &pReq->cesaDescBuf.bufPhysAddr, + &pReq->cesaDescBuf.memHandle); + if (pReq->cesaDescBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", + req, pReq->cesaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); + pReq->pCesaDesc = (MV_CESA_DESC *) MV_ALIGN_UP((MV_ULONG) pReq->cesaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC) * MV_CESA_MAX_DMA_DESC * MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->dmaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle, pReq->dmaDescBuf.bufSize, + &pReq->dmaDescBuf.bufPhysAddr, &pReq->dmaDescBuf.memHandle); + + if (pReq->dmaDescBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", + req, pReq->dmaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); + pDmaDesc = (MV_DMA_DESC *) MV_ALIGN_UP((MV_ULONG) pReq->dmaDescBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + for (frag = 0; frag < MV_CESA_MAX_REQ_FRAGS; frag++) { + MV_CESA_DMA *pDma = &pReq->dma[frag]; + + pDma->pDmaFirst = pDmaDesc; + pDma->pDmaLast = NULL; + + for (i = 0; i < MV_CESA_MAX_DMA_DESC - 1; i++) { + /* link all DMA descriptors together */ + pDma->pDmaFirst[i].phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i + 1])); + } + pDma->pDmaFirst[i].phyNextDescPtr = 0; + mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC * sizeof(MV_DMA_DESC)); + + pDmaDesc += MV_CESA_MAX_DMA_DESC; + } + } + /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH); */ + descOffsetReg = (MV_U16)((MV_U8 *)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); + MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); + + configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; +#endif + +#if (MV_CESA_VERSION >= 2) + /* Initialize TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); + MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); +#else + /* Initialize IDMA #0 engine */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE +#ifdef MV_CPU_LE + | ICCHR_DESC_BYTE_SWAP_EN +#endif + ); + /* Clear Cause Byte of IDMA channel to be used */ + MV_REG_WRITE(IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); +#endif /* (MV_CESA_VERSION >= 2) */ + + /* Set CESA configuration registers */ + MV_REG_WRITE(MV_CESA_CFG_REG, configReg); + mvCesaDebugStatsClear(); + + mvOsMemcpy(&cesaHalData, halData, sizeof(MV_CESA_HAL_DATA)); + return MV_OK; +} + +/******************************************************************************* +* mvCesaFinish - Shutdown the CESA driver +* +* DESCRIPTION: +* This function shutdown the CESA driver and free all allocted resources. +* +* INPUT: None +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaFinish(void) +{ + int req, sid; + MV_CESA_REQ *pReq; + + mvOsPrintf("mvCesaFinish: \n"); + + cesaSramVirtPtr = NULL; + + /* Free all resources: DMA list, etc. */ + for (req = 0; req < cesaQueueDepth; req++) { + pReq = &pCesaReqFirst[req]; + if (pReq->dmaDescBuf.bufVirtPtr != NULL) { + mvOsIoCachedFree(cesaOsHandle, pReq->dmaDescBuf.bufSize, + pReq->dmaDescBuf.bufPhysAddr, + pReq->dmaDescBuf.bufVirtPtr, pReq->dmaDescBuf.memHandle); + } + if (pReq->cesaDescBuf.bufVirtPtr != NULL) { + mvOsIoCachedFree(cesaOsHandle, pReq->cesaDescBuf.bufSize, + pReq->cesaDescBuf.bufPhysAddr, + pReq->cesaDescBuf.bufVirtPtr, pReq->cesaDescBuf.memHandle); + } + } +#if (MV_CESA_VERSION < 2) + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); +#endif /* (MV_CESA_VERSION < 2) */ + + /* Free request queue */ + if (pCesaReqFirst != NULL) { + mvOsFree(pCesaReqFirst); + pCesaReqFirst = pCesaReqLast = NULL; + pCesaReqEmpty = pCesaReqProcess = NULL; + cesaQueueDepth = cesaReqResources = 0; + } + /* Free SA database */ + if (pCesaSAD != NULL) { + for (sid = 0; sid < cesaMaxSA; sid++) { + /* Free SRAM SA structure */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, + pCesaSAD[sid]->sramSABuff, pCesaSAD[sid]->memHandle); + /* Free SA structure */ + mvOsFree(pCesaSAD[sid]); + pCesaSAD[sid] = NULL; + } + + cesaMaxSA = 0; + } + MV_REG_WRITE(MV_CESA_CFG_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_MASK_REG, 0); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode +* +* DESCRIPTION: +* This function set IV value using by Crypto algorithms in CBC mode. +* Each channel has its own IV value. +* This function gets IV value from the caller. If no IV value passed from +* the caller or only part of IV passed, the function will init the rest part +* of IV value (or the whole IV) by random value. +* +* INPUT: +* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL +* the function will generate random IV value. +* int ivSize - size (in bytes) of IV provided by user. If ivSize is +* smaller than maximum IV size, the function will complete +* IV by random value. +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaCryptoIvSet(MV_U8 *pIV, int ivSize) +{ + MV_U8 *pSramIV; +#if defined(MV646xx) + mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); +#endif + pSramIV = cesaSramVirtPtr->cryptoIV; + if (ivSize > MV_CESA_MAX_IV_LENGTH) { + mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH; + } + if (pIV != NULL) { + memcpy(pSramIV, pIV, ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; + pSramIV += ivSize; + } + + while (ivSize > 0) { + int size, mv_random = mvOsRand(); + + size = MV_MIN(ivSize, sizeof(mv_random)); + memcpy(pSramIV, (void *)&mv_random, size); + + pSramIV += size; + ivSize -= size; + } +/* + mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH); + mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH); +*/ + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionOpen - Open new uni-directional crypto session +* +* DESCRIPTION: +* This function open new session. +* +* INPUT: +* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters +* +* OUTPUT: +* short *pSid - session ID, should be used for all future +* requests over this session. +* +* RETURN: +* MV_OK - Session opend successfully. +* MV_FULL - All sessions are in use, no free place in +* SA database. +* MV_BAD_PARAM - One of session input parameters is invalid. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short *pSid) +{ + short sid; + MV_U32 config = 0; + int digestSize; + MV_BUF_INFO cesaSramSaBuf; + + cesaStats.openedCount++; + + /* Find free entry in SAD */ + for (sid = 0; sid < cesaMaxSA; sid++) + if (pCesaSAD[sid] == NULL) + break; + + /* No more sessions left ? */ + if (sid == cesaMaxSA) { + if (MV_FAIL == mvCesaUpdateSADSize(cesaMaxSA * 2)) { + mvOsPrintf("mvCesaSessionOpen: SA Database is FULL\n"); + return MV_FULL; + } + } + + /* Allocate SA entry */ + pCesaSAD[sid] = mvOsMalloc(sizeof(MV_CESA_SA)); + if (pCesaSAD[sid] == NULL) { + mvOsPrintf("mvCesaSessionOpen: Can't allocate %d bytes for SA structures\n", sizeof(MV_CESA_SA)); + return MV_FULL; + } + memset(pCesaSAD[sid], 0, sizeof(MV_CESA_SA)); + + /* Allocate image of sramSA in DRAM */ + cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA) + CPU_D_CACHE_LINE_SIZE; + + cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(cesaOsHandle, cesaSramSaBuf.bufSize, + &cesaSramSaBuf.bufPhysAddr, &cesaSramSaBuf.memHandle); + + if (cesaSramSaBuf.bufVirtPtr == NULL) { + mvOsPrintf("mvCesaSessionOpen: Can't allocate %d bytes for sramSA structures\n", cesaSramSaBuf.bufSize); + return MV_FULL; + } + memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); + + /* Save allocation parameters */ + pCesaSAD[sid]->sramSABuff = cesaSramSaBuf.bufVirtPtr; + pCesaSAD[sid]->sramSABuffSize = cesaSramSaBuf.bufSize; + pCesaSAD[sid]->memHandle = cesaSramSaBuf.memHandle; + pCesaSAD[sid]->pSramSA = (MV_CESA_SRAM_SA *) MV_ALIGN_UP((MV_ULONG) cesaSramSaBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + /* Align physical address to the beginning of SRAM SA */ + pCesaSAD[sid]->sramSAPhysAddr = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pCesaSAD[sid]->pSramSA)); + + /* Check Input parameters for Open session */ + if (pSession->operation >= MV_CESA_MAX_OPERATION) { + mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", pSession->operation); + return MV_BAD_PARAM; + } + config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); + + if ((pSession->direction != MV_CESA_DIR_ENCODE) && (pSession->direction != MV_CESA_DIR_DECODE)) { + mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", pSession->direction); + return MV_BAD_PARAM; + } + config |= (pSession->direction << MV_CESA_DIRECTION_BIT); + /* Clear SA entry */ + /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ + + /* Check AUTH parameters and update SA entry */ + if (pSession->operation != MV_CESA_CRYPTO_ONLY) { + /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ + if ((pSession->macMode == MV_CESA_MAC_HMAC_MD5) || (pSession->macMode == MV_CESA_MAC_HMAC_SHA1)) { + if (pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) { + mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", pSession->macKeyLength); + return MV_BAD_PARAM; + } + mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, + pCesaSAD[sid]->pSramSA->macInnerIV, pCesaSAD[sid]->pSramSA->macOuterIV); + pCesaSAD[sid]->macKeyLength = pSession->macKeyLength; + } + switch (pSession->macMode) { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", pSession->macMode); + return MV_BAD_PARAM; + } + config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); + + /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ + /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ + if ((pSession->digestSize != digestSize) && (pSession->digestSize != 12)) { + mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", pSession->digestSize); + mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->digestSize = pSession->digestSize; + + if (pCesaSAD[sid]->digestSize == 12) { + /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ + config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); + } + } + + /* Check CRYPTO parameters and update SA entry */ + if (pSession->operation != MV_CESA_MAC_ONLY) { + switch (pSession->cryptoAlgorithm) { + case MV_CESA_CRYPTO_DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_3DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + /* Only EDE mode is supported */ + config |= (MV_CESA_CRYPTO_3DES_EDE << MV_CESA_CRYPTO_3DES_MODE_BIT); + break; + + case MV_CESA_CRYPTO_AES: + switch (pSession->cryptoKeyLength) { + case 16: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_128 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 24: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_192 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 32: + default: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_256 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + } + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", pSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); + + if (pSession->cryptoKeyLength != pCesaSAD[sid]->cryptoKeyLength) { + mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", + pSession->cryptoKeyLength, pCesaSAD[sid]->cryptoKeyLength); + return MV_BAD_PARAM; + } + + /* Copy Crypto key */ + if ((pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && (pSession->direction == MV_CESA_DIR_DECODE)) { + /* Crypto Key for AES decode is computed from original key material */ + /* and depend on cryptoKeyLength (128/192/256 bits) */ + aesMakeKey(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, + pSession->cryptoKeyLength * 8, MV_CESA_AES_BLOCK_SIZE * 8); + } else { + /*panic("mvCesaSessionOpen2"); */ + memcpy(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, pCesaSAD[sid]->cryptoKeyLength); + + } + + switch (pSession->cryptoMode) { + case MV_CESA_CRYPTO_ECB: + pCesaSAD[sid]->cryptoIvSize = 0; + break; + + case MV_CESA_CRYPTO_CBC: + pCesaSAD[sid]->cryptoIvSize = pCesaSAD[sid]->cryptoBlockSize; + break; + + case MV_CESA_CRYPTO_CTR: + /* Supported only for AES algorithm */ + if (pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) { + mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->cryptoIvSize = 0; + pCesaSAD[sid]->ctrMode = 1; + /* Replace to ECB mode for HW */ + pSession->cryptoMode = MV_CESA_CRYPTO_ECB; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", pSession->cryptoMode); + return MV_BAD_PARAM; + } + + config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); + } + pCesaSAD[sid]->config = config; + + mvOsCacheFlush(NULL, pCesaSAD[sid]->pSramSA, sizeof(MV_CESA_SRAM_SA)); + if (pSid != NULL) + *pSid = sid; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionClose - Close active crypto session +* +* DESCRIPTION: +* This function closes existing session +* +* INPUT: +* short sid - Unique identifier of the session to be closed +* +* RETURN: +* MV_OK - Session closed successfully. +* MV_BAD_PARAM - Session identifier is out of valid range. +* MV_NOT_FOUND - There is no active session with such ID. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionClose(short sid) +{ + cesaStats.closedCount++; + + if (sid >= cesaMaxSA) { + mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); + return MV_BAD_PARAM; + } + + if (pCesaSAD[sid] == NULL) { + mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); + return MV_NOT_FOUND; + } + if (cesaLastSid == sid) + cesaLastSid = -1; + + /* Free SA structures */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, pCesaSAD[sid]->sramSABuff, pCesaSAD[sid]->memHandle); + mvOsFree(pCesaSAD[sid]); + + pCesaSAD[sid] = NULL; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaAction - Perform crypto operation +* +* DESCRIPTION: +* This function set new CESA request FIFO queue for further HW processing. +* The function checks request parameters before set new request to the queue. +* If one of the CESA channels is ready for processing the request will be +* passed to HW. When request processing is finished the CESA interrupt will +* be generated by HW. The caller should call mvCesaReadyGet() function to +* complete request processing and get result. +* +* INPUT: +* MV_CESA_COMMAND *pCmd - pointer to new CESA request. +* It includes pointers to Source and Destination +* buffers, session identifier get from +* mvCesaSessionOpen() function, pointer to caller +* private data and all needed crypto parameters. +* +* RETURN: +* MV_OK - request successfully added to request queue +* and will be processed. +* MV_NO_MORE - request successfully added to request queue and will +* be processed, but request queue became Full and next +* request will not be accepted. +* MV_NO_RESOURCE - request queue is FULL and the request can not +* be processed. +* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is +* failed. Request can not be processed. +* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed +* as one request and should be splitted for two requests: +* CRYPTO_ONLY and MAC_ONLY. +* MV_BAD_PARAM - One of the request parameters is out of valid range. +* The request can not be processed. +* +*******************************************************************************/ +MV_STATUS mvCesaAction(MV_CESA_COMMAND *pCmd) +{ + MV_STATUS status; + MV_CESA_REQ *pReq = pCesaReqEmpty; + int sid = pCmd->sessionId; + MV_CESA_SA *pSA = pCesaSAD[sid]; +#ifdef CONFIG_MV_CESA_CHAIN_MODE + MV_CESA_REQ *pFromReq; + MV_CESA_REQ *pToReq; +#endif + cesaStats.reqCount++; + + /* Check that the request queue is not FULL */ + if (cesaReqResources == 0) + return MV_NO_RESOURCE; + + if ((sid >= cesaMaxSA) || (pSA == NULL)) { + mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); + return MV_BAD_PARAM; + } + pSA->count++; + + if (pSA->ctrMode) { + /* AES in CTR mode can't be mixed with Authentication */ + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); + return MV_NOT_ALLOWED; + } + /* All other request parameters should not be checked because key stream */ + /* (not user data) processed by AES HW engine */ + pReq->pOrgCmd = pCmd; + /* Allocate temporary pCmd structure for Key stream */ + pCmd = mvCesaCtrModeInit(); + if (pCmd == NULL) + return MV_OUT_OF_CPU_MEM; + + /* Prepare Key stream */ + mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); + pReq->fixOffset = 0; + } else { + /* Check request parameters and calculae fixOffset */ + status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); + if (status != MV_OK) + return status; + } + pReq->pCmd = pCmd; + + /* Check if the packet need fragmentation */ + if (pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf)) { + /* request size is smaller than single buffer size */ + pReq->fragMode = MV_CESA_FRAG_NONE; + + /* Prepare NOT fragmented packets */ + status = mvCesaReqProcess(pReq); + if (status != MV_OK) + mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", pReq, status); +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.numFrag = 1; +#endif + } else { + MV_U8 frag = 0; + + /* request size is larger than buffer size - needs fragmentation */ + + /* Check restrictions for processing fragmented packets */ + status = mvCesaFragParamCheck(pSA, pCmd); + if (status != MV_OK) + return status; + + pReq->fragMode = MV_CESA_FRAG_FIRST; + pReq->frags.nextFrag = 0; + + /* Prepare Process Fragmented packets */ + while (pReq->fragMode != MV_CESA_FRAG_LAST) { + if (frag >= MV_CESA_MAX_REQ_FRAGS) { + mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); + return MV_OUT_OF_CPU_MEM; + } + status = mvCesaFragReqProcess(pReq, frag); + if (status == MV_OK) { +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (frag) { + pReq->dma[frag - 1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); + mvOsCacheFlush(NULL, pReq->dma[frag - 1].pDmaLast, sizeof(MV_DMA_DESC)); + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + frag++; + } + } + pReq->frags.numFrag = frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (chainReqNum) { + chainReqNum += pReq->frags.numFrag; + if (chainReqNum >= MAX_CESA_CHAIN_LENGTH) + chainReqNum = MAX_CESA_CHAIN_LENGTH; + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + } + + pReq->state = MV_CESA_PENDING; + + pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources -= 1; + +/* #ifdef CESA_DEBUG */ + if ((cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) + cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); +/* #endif CESA_DEBUG */ + + cesaLastSid = sid; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + /* Are we within chain bounderies and follows the first request ? */ + if ((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { + if (chainIndex) { + pFromReq = MV_CESA_REQ_PREV_PTR(pReq); + pToReq = pReq; + pReq->state = MV_CESA_CHAIN; + /* assume concatenating is possible */ + pFromReq->dma[pFromReq->frags.numFrag - 1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); + mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag - 1].pDmaLast, sizeof(MV_DMA_DESC)); + + /* align active & next pointers */ + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); + } else { /* we have only one chain, start new one */ + chainReqNum = 0; + chainIndex++; + /* align active & next pointers */ + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + } + } else { + /* In case we concatenate full chain */ + if (chainReqNum == MAX_CESA_CHAIN_LENGTH) { + chainIndex++; + if (pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + chainReqNum = 0; + } + + pReq = pCesaReqProcess; + if (pReq->state == MV_CESA_PENDING) { + pNextActiveChain = pReq; + pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } + } + + chainReqNum++; + + if ((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) + cesaStats.maxChainUsage = chainReqNum; + +#else + + /* Check status of CESA channels and process requests if possible */ + pReq = pCesaReqProcess; + if (pReq->state == MV_CESA_PENDING) { + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + /* If request queue became FULL - return MV_NO_MORE */ + if (cesaReqResources == 0) + return MV_NO_MORE; + + return MV_OK; + +} + +/******************************************************************************* +* mvCesaReadyGet - Get crypto request that processing is finished +* +* DESCRIPTION: +* This function complete request processing and return ready request to +* caller. To don't miss interrupts the caller must call this function +* while MV_OK or MV_TERMINATE values returned. +* +* INPUT: +* MV_U32 chanMap - map of CESA channels finished thier job +* accordingly with CESA Cause register. +* MV_CESA_RESULT* pResult - pointer to structure contains information +* about ready request. It includes pointer to +* user private structure "pReqPrv", session identifier +* for this request "sessionId" and return code. +* Return code set to MV_FAIL if calculated digest value +* on decode direction is different than digest value +* in the packet. +* +* RETURN: +* MV_OK - Success, ready request is returned. +* MV_NOT_READY - Next request is not ready yet. New interrupt will +* be generated for futher request processing. +* MV_EMPTY - There is no more request for processing. +* MV_BUSY - Fragmented request is not ready yet. +* MV_TERMINATE - Call this function once more to complete processing +* of fragmented request. +* +*******************************************************************************/ +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT *pResult) +{ + MV_STATUS status, readyStatus = MV_NOT_READY; + MV_U32 statusReg; + MV_CESA_REQ *pReq; + MV_CESA_SA *pSA; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + if (isFirstReq == MV_TRUE) { + if (chainIndex == 0) + chainReqNum = 0; + + isFirstReq = MV_FALSE; + + if (pNextActiveChain->state == MV_CESA_PENDING) { + /* Start request Process */ + mvCesaReqProcessStart(pNextActiveChain); + pEndCurrChain = pNextActiveChain; + if (chainIndex > 0) + chainIndex--; + /* Update pNextActiveChain to next chain head */ + while (pNextActiveChain->state == MV_CESA_CHAIN) + pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); + } + } + + /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ + if (pCesaReqProcess == pEndCurrChain) { + isFirstReq = MV_TRUE; + pEndCurrChain = pNextActiveChain; +#else + if (pCesaReqProcess->state != MV_CESA_PROCESS) { +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + return MV_EMPTY; + } +#ifdef CESA_DEBUG + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if (statusReg & MV_CESA_STATUS_ACTIVE_MASK) { + mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); + cesaStats.notReadyCount++; + return MV_NOT_READY; + } +#endif /* CESA_DEBUG */ + + cesaStats.readyCount++; + + pReq = pCesaReqProcess; + pSA = pCesaSAD[pReq->pCmd->sessionId]; + + pResult->retCode = MV_OK; + if (pReq->fragMode != MV_CESA_FRAG_NONE) { + MV_U8 *pNewDigest; + int frag; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.nextFrag = 1; + while (pReq->frags.nextFrag <= pReq->frags.numFrag) { +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + frag = (pReq->frags.nextFrag - 1); + + /* Restore DMA descriptor list */ + pReq->dma[frag].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); + pReq->dma[frag].pDmaLast = NULL; + + /* Special processing for finished fragmented request */ + if (pReq->frags.nextFrag >= pReq->frags.numFrag) { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Fragmented packet is ready */ + if ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; + + if (macDataSize != 0) { + /* Calculate all other blocks by SW */ + mvCesaFragAuthComplete(pReq, pSA, macDataSize); + } + + /* Copy new digest from SRAM to the Destination buffer */ + pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; + status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, + pReq->pCmd->digestOffset, pSA->digestSize); + + /* For decryption: Compare new digest value with original one */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + if (memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) { +/* + mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", + chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + } + readyStatus = MV_OK; + } +#ifdef CONFIG_MV_CESA_CHAIN_MODE + pReq->frags.nextFrag++; + } +#endif + } else { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Restore DMA descriptor list */ + pReq->dma[0].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); + pReq->dma[0].pDmaLast = NULL; + if (((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT))) { + /* For AUTH on decode : Check Digest result in Status register */ + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if (statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) { +/* + mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", + chan, statusReg); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + readyStatus = MV_OK; + } + + if (readyStatus == MV_OK) { + /* If Request is ready - Prepare pResult structure */ + pResult->pReqPrv = pReq->pCmd->pReqPrv; + pResult->sessionId = pReq->pCmd->sessionId; + + pReq->state = MV_CESA_IDLE; + pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources++; + + if (pSA->ctrMode) { + /* For AES CTR mode - complete processing and free allocated resources */ + mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); + mvCesaCtrModeFinish(pReq->pCmd); + pReq->pOrgCmd = NULL; + } + } +#ifndef CONFIG_MV_CESA_CHAIN_MODE + if (pCesaReqProcess->state == MV_CESA_PROCESS) { + /* Start request Process */ + mvCesaReqProcessStart(pCesaReqProcess); + if (readyStatus == MV_NOT_READY) + readyStatus = MV_BUSY; + } else if (pCesaReqProcess != pCesaReqEmpty) { + /* Start process new request from the queue */ + mvCesaReqProcessStart(pCesaReqProcess); + } +#endif /* !CONFIG_MV_CESA_CHAIN_MODE */ + return readyStatus; +} + +/***************** Functions to work with CESA_MBUF structure ******************/ + +/******************************************************************************* +* mvCesaMbufOffset - Locate offset in the Mbuf structure +* +* DESCRIPTION: +* This function locates offset inside Multi-Bufeer structure. +* It get fragment number and place in the fragment where the offset +* is located. +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure +* int offset - Offset from the beginning of the data presented by +* the Mbuf structure. +* +* OUTPUT: +* int* pBufOffset - Offset from the beginning of the fragment where +* the offset is located. +* +* RETURN: +* int - Number of fragment, where the offset is located\ +* +*******************************************************************************/ +int mvCesaMbufOffset(MV_CESA_MBUF *pMbuf, int offset, int *pBufOffset) +{ + int frag = 0; + + while (offset > 0) { + if (frag >= pMbuf->numFrags) { + mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", frag, pMbuf->numFrags); + return MV_INVALID; + } + if (offset < pMbuf->pFrags[frag].bufSize) + break; + + offset -= pMbuf->pFrags[frag].bufSize; + frag++; + } + if (pBufOffset != NULL) + *pBufOffset = offset; + + return frag; +} + +/******************************************************************************* +* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pDstBuf - Pointer to continuous buffer, where data is +* copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_EMPTY - Multi-buffer structure has not enough data to copy +* Data from the offset to end of Mbuf data is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyFromMbuf(MV_U8 *pDstBuf, MV_CESA_MBUF *pSrcMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + memcpy(pDstBuf, pBuf, size); + return MV_OK; + } + memcpy(pDstBuf, pBuf, bufSize); + size -= bufSize; + frag++; + pDstBuf += bufSize; + if (frag >= pSrcMbuf->numFrags) + break; + + bufSize = pSrcMbuf->pFrags[frag].bufSize; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", size); + return MV_EMPTY; +} + +/******************************************************************************* +* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is +* copied from. +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_FULL - Multi-buffer structure has not enough place to copy +* all data. Data from the offset to end of Mbuf data +* is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyToMbuf(MV_U8 *pSrcBuf, MV_CESA_MBUF *pDstMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + memcpy(pBuf, pSrcBuf, size); + return MV_OK; + } + memcpy(pBuf, pSrcBuf, bufSize); + size -= bufSize; + frag++; + pSrcBuf += bufSize; + if (frag >= pDstMbuf->numFrags) + break; + + bufSize = pDstMbuf->pFrags[frag].bufSize; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", size); + return MV_FULL; +} + +/******************************************************************************* +* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int dstMbufOffset - Offset in the dstMbuf structure where first byte +* of data should be copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int srcMbufOffset - Offset in the srcMbuf structure where first byte +* of data should be copied from. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of +* srcMbuf or dstMbuf structure correspondently. +* No data is copied. +* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy +* all data. Partial data is copied +* +*******************************************************************************/ +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF *pMbufDst, int dstMbufOffset, + MV_CESA_MBUF *pMbufSrc, int srcMbufOffset, int size) +{ + int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; + int copySize; + MV_U8 *pSrc, *pDst; + + if (size == 0) + return MV_OK; + + srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); + if (srcFrag == MV_INVALID) { + mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); + return MV_OUT_OF_RANGE; + } + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; + + dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); + if (dstFrag == MV_INVALID) { + mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); + return MV_OUT_OF_RANGE; + } + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; + dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; + + while (size > 0) { + copySize = MV_MIN(srcSize, dstSize); + if (size <= copySize) { + memcpy(pDst, pSrc, size); + return MV_OK; + } + memcpy(pDst, pSrc, copySize); + size -= copySize; + srcSize -= copySize; + dstSize -= copySize; + + if (srcSize == 0) { + srcFrag++; + if (srcFrag >= pMbufSrc->numFrags) + break; + + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize; + } + + if (dstSize == 0) { + dstFrag++; + if (dstFrag >= pMbufDst->numFrags) + break; + + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pMbufDst->pFrags[dstFrag].bufSize; + } + } + mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", size); + + return MV_BAD_SIZE; +} + +MV_STATUS mvCesaUpdateSADSize(MV_U32 size) +{ + MV_CESA_SA **pNewCesaSAD = NULL; + + /*mvOsPrintf("mvCesaUpdateSADSize: Increasing SA Database to %d sessions\n",size); */ + + /* Allocate new buffer to hold larger SAD */ + pNewCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA *) * size); + if (pNewCesaSAD == NULL) { + mvOsPrintf("mvCesaUpdateSADSize: Can't allocate %d bytes for new SAD buffer\n", size); + return MV_FAIL; + } + memset(pNewCesaSAD, 0, (sizeof(MV_CESA_SA *) * size)); + mvOsMemcpy(pNewCesaSAD, pCesaSAD, (sizeof(MV_CESA_SA *) * cesaMaxSA)); + mvOsFree(pCesaSAD); + pCesaSAD = pNewCesaSAD; + cesaMaxSA = size; + + return MV_OK; +} + +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF *pMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8 *pBuf; + + if (size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while (MV_TRUE) { + if (size <= bufSize) { + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); + return MV_OK; + } + + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); + size -= bufSize; + frag++; + if (frag >= pMbuf->numFrags) + break; + + bufSize = pMbuf->pFrags[frag].bufSize; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", __func__, size); + return MV_FULL; +} + +/*************************************** Local Functions ******************************/ + +/******************************************************************************* +* mvCesaFragReqProcess - Process fragmented request +* +* DESCRIPTION: +* This function processes a fragment of fragmented request (First, Middle or Last) +* +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The fragment is successfully passed to HW for processing. +* MV_TERMINATE - Means, that HW finished its work on this packet and no more +* interrupts will be generated for this request. +* Function mvCesaReadyGet() must be called to complete request +* processing and get request result. +* +*******************************************************************************/ +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ *pReq, MV_U8 frag) +{ + int i, copySize, cryptoDataSize, macDataSize, sid; + int cryptoIvOffset, digestOffset; + MV_U32 config; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + MV_CESA_SA *pSA; + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc = pReq->dma[frag].pDmaFirst; + MV_U8 *pSramBuf = cesaSramVirtPtr->buf; + int macTotalLen = 0; + int fixOffset, cryptoOffset, macOffset; + + cesaStats.fragCount++; + + sid = pReq->pCmd->sessionId; + + pSA = pCesaSAD[sid]; + + cryptoIvOffset = digestOffset = 0; + i = macDataSize = 0; + cryptoDataSize = 0; + + /* First fragment processing */ + if (pReq->fragMode == MV_CESA_FRAG_FIRST) { + /* pReq->frags monitors processing of fragmented request between fragments */ + pReq->frags.bufOffset = 0; + pReq->frags.cryptoSize = 0; + pReq->frags.macSize = 0; + + config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); + + /* fixOffset can be not equal to zero only for FIRST fragment */ + fixOffset = pReq->fixOffset; + /* For FIRST fragment crypto and mac offsets are taken from pCmd */ + cryptoOffset = pCmd->cryptoOffset; + macOffset = pCmd->macOffset; + + copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; + + /* Find fragment size: Must meet all requirements for CRYPTO and MAC + * cryptoDataSize - size of data will be encrypted/decrypted in this fragment + * macDataSize - size of data will be signed/verified in this fragment + * copySize - size of data will be copied from srcMbuf to SRAM and + * back to dstMbuf for this fragment + */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ©Size, &cryptoDataSize, &macDataSize); + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* CryptoIV special processing */ + if ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) { + /* In CBC mode for encode direction when IV from user */ + if ((pCmd->ivFromUser) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT))) { + + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, + pCmd->skipFlush); + } + + /* Special processing when IV is not located in the first fragment */ + if (pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) { + /* Prepare dummy place for cryptoIV in SRAM */ + cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); + + /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, + &pDmaDesc[i], MV_FALSE, pCmd->ivOffset, + pSA->cryptoIvSize, pCmd->skipFlush); + } else { + /* For Encryption when IV is NOT from User: */ + /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ + if (pCmd->ivFromUser == 0) { + /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, + &pDmaDesc[i], MV_TRUE, pCmd->ivOffset, + pSA->cryptoIvSize, pCmd->skipFlush); + } + } + } else { + cryptoIvOffset = pCmd->ivOffset; + } + } + } + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* MAC digest special processing on Decode direction */ + if ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) { + /* Save digest from pCmd->digestOffset */ + mvCesaCopyFromMbuf(pReq->frags.orgDigest, + pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* If pCmd->digestOffset is not located on the first */ + if (pCmd->digestOffset > (copySize - pSA->digestSize)) { + MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; + + /* Set zeros to pCmd->digestOffset (DRAM) */ + memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); + mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } else { + digestOffset = pCmd->digestOffset; + } + } + } + /* Update SA in SRAM */ + if (cesaLastSid != sid) { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + pReq->fragMode = MV_CESA_FRAG_MIDDLE; + } else { + /* Continue fragment */ + fixOffset = 0; + cryptoOffset = 0; + macOffset = 0; + if ((pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) { + /* Last fragment */ + config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); + pReq->fragMode = MV_CESA_FRAG_LAST; + copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + macDataSize = pCmd->macLength - pReq->frags.macSize; + + /* If pCmd->digestOffset is not located on last fragment */ + if (pCmd->digestOffset < pReq->frags.bufOffset) { + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } else { + digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; + } + pReq->frags.newDigestOffset = digestOffset; + macTotalLen = pCmd->macLength; + + /* HW can't calculate the Digest correctly for fragmented packets + * in the following cases: + * - MV88F5182 || + * - MV88F5181L when total macLength more that 16 Kbytes || + * - total macLength more that 64 Kbytes + */ + if ((cesaHalData.ctrlModel == MV_5182_DEV_ID) || + ((cesaHalData.ctrlModel == MV_5181_DEV_ID) && + (cesaHalData.ctrlRev >= MV_5181L_A0_REV) && (pCmd->macLength >= (1 << 14)))) { + return MV_TERMINATE; + } + } + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) + cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; + + /* cryptoIvOffset - don't care */ + } else { + /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ + if ((cesaHalData.ctrlModel == MV_5182_DEV_ID) && + (((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || + ((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET)))) { + pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + pReq->fragMode = MV_CESA_FRAG_LAST; + + return MV_TERMINATE; + } + /* Middle fragment */ + config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); + copySize = sizeof(cesaSramVirtPtr->buf); + /* digestOffset and cryptoIvOffset - don't care */ + + /* Find fragment size */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + } + } + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ + mvCesaSramDescrBuild(config, frag, + cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, + cryptoDataSize, macOffset + fixOffset, + digestOffset + fixOffset, macDataSize, macTotalLen, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i - 1].phyNextDescPtr = 0; + pReq->dma[frag].pDmaLast = &pDmaDesc[i - 1]; + mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, i * sizeof(MV_DMA_DESC)); + + /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]); */ + + pReq->frags.bufOffset += copySize; + pReq->frags.cryptoSize += cryptoDataSize; + pReq->frags.macSize += macDataSize; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaReqProcess - Process regular (Non-fragmented) request +* +* DESCRIPTION: +* This function processes the whole (not fragmented) request +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The request is successfully passed to HW for processing. +* Other - Failure. The request will not be processed +* +*******************************************************************************/ +static MV_STATUS mvCesaReqProcess(MV_CESA_REQ *pReq) +{ + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc; + MV_U8 *pSramBuf; + int sid, i, fixOffset; + MV_CESA_SA *pSA; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + + cesaStats.procCount++; + + sid = pCmd->sessionId; + pSA = pCesaSAD[sid]; + pDmaDesc = pReq->dma[0].pDmaFirst; + pSramBuf = cesaSramVirtPtr->buf; + fixOffset = pReq->fixOffset; + +/* + mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", + sid, pSA, pDmaDesc, pSramBuf); +*/ + i = 0; + + /* Crypto IV Special processing in CBC mode for Encryption direction */ + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && + (pCmd->ivFromUser)) { + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Update SA in SRAM */ + if (cesaLastSid != sid) { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ + mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, + pCmd->ivOffset + fixOffset, pCmd->cryptoLength, + pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, + pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i - 1].phyNextDescPtr = 0; + pReq->dma[0].pDmaLast = &pDmaDesc[i - 1]; + mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i * sizeof(MV_DMA_DESC)); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaSramDescrBuild - Set CESA descriptor in SRAM +* +* DESCRIPTION: +* This function builds CESA descriptor in SRAM from all Command parameters +* +* +* INPUT: +* int chan - CESA channel uses the descriptor +* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure +* int cryptoOffset - Offset from the beginning of SRAM buffer where +* data for encryption/decription is started. +* int ivOffset - Offset of crypto IV from the SRAM base. Valid only +* for first fragment. +* int cryptoLength - Size (in bytes) of data for encryption/descryption +* operation on this fragment. +* int macOffset - Offset from the beginning of SRAM buffer where +* data for Authentication is started +* int digestOffset - Offset from the beginning of SRAM buffer where +* digest is located. Valid for first and last fragments. +* int macLength - Size (in bytes) of data for Authentication +* operation on this fragment. +* int macTotalLen - Toatl size (in bytes) of data for Authentication +* operation on the whole request (packet). Valid for +* last fragment only. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, + int macTotalLen, MV_CESA_REQ *pReq, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_DESC *pCesaDesc = &pReq->pCesaDesc[frag]; + MV_CESA_DESC *pSramDesc = &cesaSramVirtPtr->desc; + MV_U16 sramBufOffset = (MV_U16)((MV_U8 *)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); + + pCesaDesc->config = MV_32BIT_LE(config); + + if ((config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* word 1 */ + pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + /* word 2 */ + pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); + /* word 3 */ + pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.cryptoKey - + mvCesaSramAddrGet())); + /* word 4 */ + pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->cryptoIV - mvCesaSramAddrGet())); + pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); + } + + if ((config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + /* word 5 */ + pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); + pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); + + /* word 6 */ + pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); + pCesaDesc->macDataLen = MV_16BIT_LE(macLength); + + /* word 7 */ + pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.macInnerIV - + mvCesaSramAddrGet())); + pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16) (cesaSramVirtPtr->sramSA.macOuterIV - + mvCesaSramAddrGet())); + } + /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ + pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8 *) pSramDesc)); + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); + + /* flush Source buffer */ + mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); +} + +/******************************************************************************* +* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. +* +* DESCRIPTION: +* Copy to SRAM values of the required SA. +* +* +* INPUT: +* short sid - Session ID needs SRAM Cache update +* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to +* copy SA values from DRAM to SRAM. +* +* RETURN: +* MV_OK - Cache entry for this SA copied to SRAM. +* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM +* +*******************************************************************************/ +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_SA *pSA = pCesaSAD[sid]; + + /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); + pDmaDesc->phySrcAdd = pSA->sramSAPhysAddr; + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8 *)&cesaSramVirtPtr->sramSA)); + + /* Source buffer is already flushed during OpenSession */ + /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA)); */ +} + +/******************************************************************************* +* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by +* Mbuf structure from DRAM to SRAM +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request +* data in DRAM +* MV_U8* pSramBuf - pointer to buffer in SRAM where data should +* be copied to. +* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. +* The function set number of DMA descriptors needed +* to copy the copySize bytes from Mbuf. +* MV_BOOL isToMbuf - Copy direction. +* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. +* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. +* int offset - Offset in the Mbuf structure that copy should be +* started from. +* int copySize - Size of data should be copied. +* +* RETURN: +* int - number of DMA descriptors used for the copy. +* +*******************************************************************************/ +#ifndef MV_NETBSD +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, size, frag, i; + MV_U8 *pBuf; + + i = 0; + + /* Calculate start place for copy: fragment number and offset in the fragment */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + + /* Size accumulate total copy size */ + size = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* Find copy size for each DMA descriptor */ + bufSize = MV_MIN(bufSize, (copySize - size)); + pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); + if (isToMbuf) { + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* invalidate the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, bufSize); + } else { + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* flush the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, bufSize); + } + + /* Count number of used DMA descriptors */ + i++; + size += bufSize; + + /* go to next fragment in the Mbuf */ + frag++; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + bufSize = pMbuf->pFrags[frag].bufSize; + } + return i; +} +#else /* MV_NETBSD */ +static int mvCesaDmaCopyPrepare(MV_CESA_MBUF *pMbuf, MV_U8 *pSramBuf, + MV_DMA_DESC *pDmaDesc, MV_BOOL isToMbuf, int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, thisSize, size, frag, i; + MV_ULONG bufPhys, sramPhys; + MV_U8 *pBuf; + + /* + * Calculate start place for copy: fragment number and offset in + * the fragment + */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + + /* + * Get SRAM physical address only once. We can update it in-place + * as we build the descriptor chain. + */ + sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); + + /* + * 'size' accumulates total copy size, 'i' counts desccriptors. + */ + size = i = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* + * Calculate # of bytes to copy from the current fragment, + * and the pointer to the start of data + */ + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + bufOffset = 0; /* First frag may be non-zero */ + frag++; + + /* + * As long as there is data in the current fragment... + */ + while (bufSize > 0) { + /* + * Ensure we don't cross an MMU page boundary. + * XXX: This is NetBSD-specific, but it is a + * quick and dirty way to fix the problem. + * A true HAL would rely on the OS-specific + * driver to do this... + */ + thisSize = PAGE_SIZE - (((MV_ULONG) pBuf) & (PAGE_SIZE - 1)); + thisSize = MV_MIN(bufSize, thisSize); + /* + * Make sure we don't copy more than requested + */ + if (thisSize > (copySize - size)) { + thisSize = copySize - size; + bufSize = 0; + } + + /* + * Physicall address of this fragment + */ + bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + + /* + * Set up the descriptor + */ + pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); + if (isToMbuf) { + pDmaDesc[i].phyDestAdd = bufPhys; + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); + /* invalidate the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, thisSize); + } else { + pDmaDesc[i].phySrcAdd = bufPhys; + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); + /* flush the buffer */ + if (skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, thisSize); + } + + pDmaDesc[i].phyNextDescPtr = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, (&pDmaDesc[i + 1]))); + + /* flush the DMA desc */ + mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); + + /* Update state */ + bufSize -= thisSize; + sramPhys += thisSize; + pBuf += thisSize; + size += thisSize; + i++; + } + } + + return i; +} +#endif /* MV_NETBSD */ +/******************************************************************************* +* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key +* +* DESCRIPTION: +* This function calculate Inner and Outer values used for HMAC algorithm. +* This operation allows improve performance fro the whole HMAC processing. +* +* INPUT: +* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. +* unsigned char key[] - Pointer to HMAC key. +* int keyLength - Size of HMAC key (maximum 64 bytes) +* +* OUTPUT: +* unsigned char innerIV[] - HASH(key^inner) +* unsigned char outerIV[] - HASH(key^outter) +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]) +{ + unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; + unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; + int i, digestSize = 0; +#if defined(MV_CPU_LE) || defined(MV_PPC) + MV_U32 swapped32, val32, *pVal32; +#endif + for (i = 0; i < keyLength; i++) { + inner[i] = 0x36 ^ key[i]; + outer[i] = 0x5c ^ key[i]; + } + + for (i = keyLength; i < MV_CESA_MAX_MAC_KEY_LENGTH; i++) { + inner[i] = 0x36; + outer[i] = 0x5c; + } + if (macMode == MV_CESA_MAC_HMAC_MD5) { + MV_MD5_CONTEXT ctx; + + mvMD5Init(&ctx); + mvMD5Update(&ctx, inner, MV_CESA_MAX_MAC_KEY_LENGTH); + + memcpy(innerIV, ctx.buf, MV_CESA_MD5_DIGEST_SIZE); + memset(&ctx, 0, sizeof(ctx)); + + mvMD5Init(&ctx); + mvMD5Update(&ctx, outer, MV_CESA_MAX_MAC_KEY_LENGTH); + memcpy(outerIV, ctx.buf, MV_CESA_MD5_DIGEST_SIZE); + memset(&ctx, 0, sizeof(ctx)); + digestSize = MV_CESA_MD5_DIGEST_SIZE; + } else if (macMode == MV_CESA_MAC_HMAC_SHA1) { + MV_SHA1_CTX ctx; + + mvSHA1Init(&ctx); + mvSHA1Update(&ctx, inner, MV_CESA_MAX_MAC_KEY_LENGTH); + memcpy(innerIV, ctx.state, MV_CESA_SHA1_DIGEST_SIZE); + memset(&ctx, 0, sizeof(ctx)); + + mvSHA1Init(&ctx); + mvSHA1Update(&ctx, outer, MV_CESA_MAX_MAC_KEY_LENGTH); + memcpy(outerIV, ctx.state, MV_CESA_SHA1_DIGEST_SIZE); + memset(&ctx, 0, sizeof(ctx)); + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + } else { + mvOsPrintf("hmacGetIV: Unexpected macMode %d\n", macMode); + } +#if defined(MV_CPU_LE) || defined(MV_PPC) + /* 32 bits Swap of Inner and Outer values */ + pVal32 = (MV_U32 *) innerIV; + for (i = 0; i < digestSize / 4; i++) { + val32 = *pVal32; + swapped32 = MV_BYTE_SWAP_32BIT(val32); + *pVal32 = swapped32; + pVal32++; + } + pVal32 = (MV_U32 *) outerIV; + for (i = 0; i < digestSize / 4; i++) { + val32 = *pVal32; + swapped32 = MV_BYTE_SWAP_32BIT(val32); + *pVal32 = swapped32; + pVal32++; + } +#endif /* defined(MV_CPU_LE) || defined(MV_PPC) */ +} + +/******************************************************************************* +* mvCesaFragSha1Complete - Complete SHA1 authentication started by HW using SW +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to Mbuf structure where data +* for SHA1 is placed. +* int offset - Offset in the Mbuf structure where +* unprocessed data for SHA1 is started. +* MV_U8* pOuterIV - Pointer to OUTER for this session. +* If pOuterIV==NULL - MAC mode is HASH_SHA1 +* If pOuterIV!=NULL - MAC mode is HMAC_SHA1 +* int macLeftSize - Size of unprocessed data for SHA1. +* int macTotalSize - Total size of data for SHA1 in the +* request (processed + unprocessed) +* +* OUTPUT: +* MV_U8* pDigest - Pointer to place where calculated Digest will +* be stored. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaFragSha1Complete(MV_CESA_MBUF *pMbuf, int offset, + MV_U8 *pOuterIV, int macLeftSize, int macTotalSize, MV_U8 *pDigest) +{ + MV_SHA1_CTX ctx; + MV_U8 *pData; + int i, frag, fragOffset, size; + + /* Read temporary Digest from HW */ + for (i = 0; i < MV_CESA_SHA1_DIGEST_SIZE / 4; i++) + ctx.state[i] = MV_REG_READ(MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i)); + + /* Initialize MV_SHA1_CTX structure */ + memset(ctx.buffer, 0, 64); + /* Set count[0] in bits. 32 bits is enough for 512 MBytes */ + /* so count[1] is always 0 */ + ctx.count[0] = ((macTotalSize - macLeftSize) * 8); + ctx.count[1] = 0; + + /* If HMAC - add size of Inner block (64 bytes) ro count[0] */ + if (pOuterIV != NULL) + ctx.count[0] += (64 * 8); + + /* Get place of unprocessed data in the Mbuf structure */ + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return; + } + + pData = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while (macLeftSize > 0) { + if (macLeftSize <= size) { + mvSHA1Update(&ctx, pData, macLeftSize); + break; + } + mvSHA1Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvSHA1Final(pDigest, &ctx); +/* + mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); +*/ + + if (pOuterIV != NULL) { + /* If HMAC - Complete Outer part */ + for (i = 0; i < MV_CESA_SHA1_DIGEST_SIZE / 4; i++) { +#if defined(MV_CPU_LE) || defined(MV_ARM) + ctx.state[i] = MV_BYTE_SWAP_32BIT(((MV_U32 *) pOuterIV)[i]); +#else + ctx.state[i] = ((MV_U32 *) pOuterIV)[i]; +#endif + } + memset(ctx.buffer, 0, 64); + + ctx.count[0] = 64 * 8; + ctx.count[1] = 0; + mvSHA1Update(&ctx, pDigest, MV_CESA_SHA1_DIGEST_SIZE); + mvSHA1Final(pDigest, &ctx); + } +} + +/******************************************************************************* +* mvCesaFragMd5Complete - Complete MD5 authentication started by HW using SW +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to Mbuf structure where data +* for SHA1 is placed. +* int offset - Offset in the Mbuf structure where +* unprocessed data for MD5 is started. +* MV_U8* pOuterIV - Pointer to OUTER for this session. +* If pOuterIV==NULL - MAC mode is HASH_MD5 +* If pOuterIV!=NULL - MAC mode is HMAC_MD5 +* int macLeftSize - Size of unprocessed data for MD5. +* int macTotalSize - Total size of data for MD5 in the +* request (processed + unprocessed) +* +* OUTPUT: +* MV_U8* pDigest - Pointer to place where calculated Digest will +* be stored. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaFragMd5Complete(MV_CESA_MBUF *pMbuf, int offset, + MV_U8 *pOuterIV, int macLeftSize, int macTotalSize, MV_U8 *pDigest) +{ + MV_MD5_CONTEXT ctx; + MV_U8 *pData; + int i, frag, fragOffset, size; + + /* Read temporary Digest from HW */ + for (i = 0; i < MV_CESA_MD5_DIGEST_SIZE / 4; i++) + ctx.buf[i] = MV_REG_READ(MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i)); + + memset(ctx.in, 0, 64); + + /* Set count[0] in bits. 32 bits is enough for 512 MBytes */ + /* so count[1] is always 0 */ + ctx.bits[0] = ((macTotalSize - macLeftSize) * 8); + ctx.bits[1] = 0; + + /* If HMAC - add size of Inner block (64 bytes) ro count[0] */ + if (pOuterIV != NULL) + ctx.bits[0] += (64 * 8); + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return; + } + + pData = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while (macLeftSize > 0) { + if (macLeftSize <= size) { + mvMD5Update(&ctx, pData, macLeftSize); + break; + } + mvMD5Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvMD5Final(pDigest, &ctx); + +/* + mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); +*/ + if (pOuterIV != NULL) { + /* Complete Outer part */ + for (i = 0; i < MV_CESA_MD5_DIGEST_SIZE / 4; i++) { +#if defined(MV_CPU_LE) || defined(MV_ARM) + ctx.buf[i] = MV_BYTE_SWAP_32BIT(((MV_U32 *) pOuterIV)[i]); +#else + ctx.buf[i] = ((MV_U32 *) pOuterIV)[i]; +#endif + } + memset(ctx.in, 0, 64); + + ctx.bits[0] = 64 * 8; + ctx.bits[1] = 0; + mvMD5Update(&ctx, pDigest, MV_CESA_MD5_DIGEST_SIZE); + mvMD5Final(pDigest, &ctx); + } +} + +/******************************************************************************* +* mvCesaFragAuthComplete - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_REQ* pReq, +* MV_CESA_SA* pSA, +* int macDataSize +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ *pReq, MV_CESA_SA *pSA, int macDataSize) +{ + MV_CESA_COMMAND *pCmd = pReq->pCmd; + MV_U8 *pDigest; + MV_CESA_MAC_MODE macMode; + MV_U8 *pOuterIV = NULL; + + /* Copy data from Source fragment to Destination */ + if (pCmd->pSrc != pCmd->pDst) + mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + +/* + mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); +*/ + pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); + + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; +/* + mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", + macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); +*/ + switch (macMode) { + case MV_CESA_MAC_HMAC_MD5: + pOuterIV = pSA->pSramSA->macOuterIV; + /* fallthrough */ + + case MV_CESA_MAC_MD5: + mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + case MV_CESA_MAC_HMAC_SHA1: + pOuterIV = pSA->pSramSA->macOuterIV; + /* fallthrough */ + + case MV_CESA_MAC_SHA1: + mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + default: + mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); + return MV_BAD_PARAM; + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeInit - +* +* DESCRIPTION: +* +* +* INPUT: NONE +* +* +* RETURN: +* MV_CESA_COMMAND* +* +*******************************************************************************/ +static MV_CESA_COMMAND *mvCesaCtrModeInit(void) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf; + MV_CESA_COMMAND *pCmd; + + pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); + if (pBuf == NULL) { + mvOsPrintf("mvCesaCtrModeInit: Can't allocate %u bytes for CTR Mode\n", + sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO)); + return NULL; + } + pCmd = (MV_CESA_COMMAND *)pBuf; + pBuf += sizeof(MV_CESA_COMMAND); + + pMbuf = (MV_CESA_MBUF *)pBuf; + pBuf += sizeof(MV_CESA_MBUF); + + pMbuf->pFrags = (MV_BUF_INFO *)pBuf; + + pMbuf->numFrags = 1; + pCmd->pSrc = pMbuf; + pCmd->pDst = pMbuf; +/* + mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", pCmd, pCmd->pSrc, pCmd->pDst, + pMbuf->pFrags); +*/ + return pCmd; +} + +/******************************************************************************* +* mvCesaCtrModePrepare - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf, *pIV; + MV_U32 counter, *pCounter; + int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); +/* + mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); +*/ + pMbuf = pCtrModeCmd->pSrc; + + /* Allocate buffer for Key stream */ + pBuf = mvOsIoCachedMalloc(cesaOsHandle, cryptoSize, &pMbuf->pFrags[0].bufPhysAddr, &pMbuf->pFrags[0].memHandle); + if (pBuf == NULL) { + mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); + return MV_OUT_OF_CPU_MEM; + } + memset(pBuf, 0, cryptoSize); + mvOsCacheFlush(NULL, pBuf, cryptoSize); + + pMbuf->pFrags[0].bufVirtPtr = pBuf; + pMbuf->mbufSize = cryptoSize; + pMbuf->pFrags[0].bufSize = cryptoSize; + + pCtrModeCmd->pReqPrv = pCmd->pReqPrv; + pCtrModeCmd->sessionId = pCmd->sessionId; + + /* ivFromUser and ivOffset are don't care */ + pCtrModeCmd->cryptoOffset = 0; + pCtrModeCmd->cryptoLength = cryptoSize; + + /* digestOffset, macOffset and macLength are don't care */ + + mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); + pCounter = (MV_U32 *)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter = *pCounter; + counter = MV_32BIT_BE(counter); + pIV = pBuf; + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + + /* fill key stream */ + while (cryptoSize > 0) { + pBuf += MV_CESA_AES_BLOCK_SIZE; + memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); + pCounter = (MV_U32 *)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter++; + *pCounter = MV_32BIT_BE(counter); + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeComplete - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) +{ + int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; + int cryptoSize = pCmd->cryptoLength; + MV_U8 *pSrc, *pDst, *pKey; + MV_STATUS status = MV_OK; +/* + mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); +*/ + /* XOR source data with key stream to destination data */ + pKey = pCmd->pDst->pFrags[0].bufVirtPtr; + keyOffset = 0; + + if ((pOrgCmd->pSrc != pOrgCmd->pDst) && (pOrgCmd->cryptoOffset > 0)) { + /* Copy Prefix from source buffer to destination buffer */ + + status = mvCesaMbufCopy(pOrgCmd->pDst, 0, pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, 0, pOrgCmd->cryptoOffset); +*/ + } + + srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + + dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + + while (cryptoSize > 0) { + pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); + + cryptoSize--; + dstOffset++; + srcOffset++; + keyOffset++; + + if (srcOffset >= srcSize) { + srcFrag++; + srcOffset = 0; + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + } + + if (dstOffset >= dstSize) { + dstFrag++; + dstOffset = 0; + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + } + } + + if (pOrgCmd->pSrc != pOrgCmd->pDst) { + /* Copy Suffix from source buffer to destination buffer */ + srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; + + if ((pOrgCmd->pDst->mbufSize - srcOffset) > 0) { + status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, + pOrgCmd->pSrc, srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); + } + +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); +*/ + } + + /* Free buffer used for Key stream */ + mvOsIoCachedFree(cesaOsHandle, pCmd->pDst->pFrags[0].bufSize, + pCmd->pDst->pFrags[0].bufPhysAddr, + pCmd->pDst->pFrags[0].bufVirtPtr, pCmd->pDst->pFrags[0].memHandle); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeFinish - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND* pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd) +{ + mvOsFree(pCmd); +} + +/******************************************************************************* +* mvCesaParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd, MV_U8 *pFixOffset) +{ + MV_U8 fixOffset = 0xFF; + +/* + mvOsPrintf("mvCesaParamCheck:macOffset=%d digestOffset=%d cryptoOffset=%d ivOffset=%d" + "cryptoLength=%d cryptoBlockSize=%d mbufSize=%d\n", + pCmd->macOffset, pCmd->digestOffset, pCmd->cryptoOffset, pCmd->ivOffset, + pCmd->cryptoLength, pSA->cryptoBlockSize, pCmd->pSrc->mbufSize); +*/ + + /* Check AUTH operation parameters */ + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET))) { + /* MAC offset should be at least 4 byte aligned */ + if (MV_IS_NOT_ALIGN(pCmd->macOffset, 4)) { + mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", pCmd->macOffset); + return MV_BAD_PARAM; + } + /* Digest offset must be 4 byte aligned */ + if (MV_IS_NOT_ALIGN(pCmd->digestOffset, 4)) { + mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", pCmd->digestOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if (fixOffset == 0xFF) { + fixOffset = (pCmd->macOffset % 8); + } else { + if ((pCmd->macOffset % 8) != fixOffset) { + mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", + pCmd->macOffset, fixOffset); + return MV_BAD_PARAM; + } + } + if ((pCmd->digestOffset % 8) != fixOffset) { + mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", + pCmd->digestOffset, fixOffset); + return MV_BAD_PARAM; + } + } + /* Check CRYPTO operation parameters */ + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET))) { + /* CryptoOffset should be at least 4 byte aligned */ + if (MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4)) { + mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + /* cryptoLength should be the whole number of blocks */ + if (MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize)) { + mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", + pCmd->cryptoLength, pSA->cryptoBlockSize); + return MV_BAD_PARAM; + } + if (fixOffset == 0xFF) { + fixOffset = (pCmd->cryptoOffset % 8); + } else { + /* In addition all offsets should be the same alignment: 8 or 4 */ + if ((pCmd->cryptoOffset % 8) != fixOffset) { + mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", + pCmd->cryptoOffset, fixOffset); + return MV_BAD_PARAM; + } + } + + /* check for CBC mode */ + if (pSA->cryptoIvSize > 0) { + /* cryptoIV must not be part of CryptoLength */ + if (((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && + (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength))) { + mvOsPrintf + ("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); + return MV_BAD_PARAM; + } + + /* ivOffset must be 4 byte aligned */ + if (MV_IS_NOT_ALIGN(pCmd->ivOffset, 4)) { + mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", pCmd->ivOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if ((pCmd->ivOffset % 8) != fixOffset) { + mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", pCmd->ivOffset, fixOffset); + return MV_BAD_PARAM; + } + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA *pSA, MV_CESA_COMMAND *pCmd) +{ + int offset; + + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET))) { + /* macOffset must be less that SRAM buffer size */ + if (pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) { + mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", pCmd->macOffset); + return MV_BAD_PARAM; + } + /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ + if (((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= sizeof(cesaSramVirtPtr->buf))) { + mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", + pCmd->macLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + if (((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET))) { + /* cryptoOffset must be less that SRAM buffer size */ + /* 4 for possible fixOffset */ + if ((pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) { + mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + + /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ + if (((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= + (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize))) { + mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", + pCmd->cryptoLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ + if (((pSA->config & MV_CESA_OPERATION_MASK) == + (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || + ((pSA->config & MV_CESA_OPERATION_MASK) == (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET))) { + if ((cesaHalData.ctrlModel == MV_5182_DEV_ID) || + ((cesaHalData.ctrlModel == MV_5181_DEV_ID) && + (cesaHalData.ctrlRev >= MV_5181L_A0_REV) && (pCmd->macLength >= (1 << 14)))) { + return MV_NOT_ALLOWED; + } + + /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ + if (pCmd->cryptoOffset > pCmd->macOffset) + offset = pCmd->cryptoOffset - pCmd->macOffset; + else + offset = pCmd->macOffset - pCmd->cryptoOffset; + + if (MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize)) { +/* + mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", + pSA->cryptoBlockSize); +*/ + return MV_NOT_ALLOWED; + } + /* Digest must not be part of CryptoLength */ + if (((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && + (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength))) { +/* + mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); +*/ + return MV_NOT_ALLOWED; + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragSizeFind - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, +* int cryptoOffset, int macOffset, +* +* OUTPUT: +* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaFragSizeFind(MV_CESA_SA *pSA, MV_CESA_REQ *pReq, + int cryptoOffset, int macOffset, int *pCopySize, int *pCryptoDataSize, int *pMacDataSize) +{ + MV_CESA_COMMAND *pCmd = pReq->pCmd; + int cryptoDataSize, macDataSize, copySize; + + cryptoDataSize = macDataSize = 0; + copySize = *pCopySize; + + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) { + cryptoDataSize = MV_MIN((copySize - cryptoOffset), (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1))); + + /* cryptoSize for each fragment must be the whole number of blocksSize */ + if (MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize)) { + cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); + copySize = cryptoOffset + cryptoDataSize; + } + } + if ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) { + macDataSize = MV_MIN((copySize - macOffset), (pCmd->macLength - (pReq->frags.macSize + 1))); + + /* macSize for each fragment (except last) must be the whole number of blocksSize */ + if (MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE)) { + macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); + copySize = macOffset + macDataSize; + } + cryptoDataSize = copySize - cryptoOffset; + } + *pCopySize = copySize; + + if (pCryptoDataSize != NULL) + *pCryptoDataSize = cryptoDataSize; + + if (pMacDataSize != NULL) + *pMacDataSize = macDataSize; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaDebug.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaDebug.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaDebug.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaDebug.c 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,430 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvDebug.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesaRegs.h" +#include "cesa/mvCesa.h" +#include "cesa/AES/mvAes.h" + +static const char *mvCesaDebugStateStr(MV_CESA_STATE state) +{ + switch (state) { + case MV_CESA_IDLE: + return "Idle"; + + case MV_CESA_PENDING: + return "Pend"; + + case MV_CESA_PROCESS: + return "Proc"; + + case MV_CESA_READY: + return "Ready"; + + default: + break; + } + return "Unknown"; +} + +static const char *mvCesaDebugOperStr(MV_CESA_OPERATION oper) +{ + switch (oper) { + case MV_CESA_MAC_ONLY: + return "MacOnly"; + + case MV_CESA_CRYPTO_ONLY: + return "CryptoOnly"; + + case MV_CESA_MAC_THEN_CRYPTO: + return "MacCrypto"; + + case MV_CESA_CRYPTO_THEN_MAC: + return "CryptoMac"; + + default: + break; + } + return "Null"; +} + +static const char *mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) +{ + switch (cryptoAlg) { + case MV_CESA_CRYPTO_DES: + return "DES"; + + case MV_CESA_CRYPTO_3DES: + return "3DES"; + + case MV_CESA_CRYPTO_AES: + return "AES"; + + default: + break; + } + return "Null"; +} + +static const char *mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) +{ + switch (macMode) { + case MV_CESA_MAC_MD5: + return "MD5"; + + case MV_CESA_MAC_SHA1: + return "SHA1"; + + case MV_CESA_MAC_HMAC_MD5: + return "HMAC-MD5"; + + case MV_CESA_MAC_HMAC_SHA1: + return "HMAC_SHA1"; + + default: + break; + } + return "Null"; +} + +void mvCesaDebugCmd(MV_CESA_COMMAND *pCmd, int mode) +{ + mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", + pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, pCmd->pFuncCB, pCmd->sessionId); + mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", + pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, + pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); +} + +/* no need to use in tool */ +void mvCesaDebugMbuf(const char *str, MV_CESA_MBUF *pMbuf, int offset, int size) +{ + int frag, len, fragOffset; + + if (str != NULL) + mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if (frag == MV_INVALID) { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return; + } + + for (; frag < pMbuf->numFrags; frag++) { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pMbuf->pFrags[frag].bufVirtPtr, pMbuf->pFrags[frag].bufSize); + if (size > 0) { + len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); + mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr + fragOffset, len, 1); + size -= len; + fragOffset = 0; + } + } +} + +void mvCesaDebugRegs(void) +{ + mvOsPrintf("\t CESA Registers:\n"); + + mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", + MV_CESA_CMD_REG, MV_REG_READ(MV_CESA_CMD_REG)); + + mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", + MV_CESA_CHAN_DESC_OFFSET_REG, MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG)); + + mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", + MV_CESA_CFG_REG, MV_REG_READ(MV_CESA_CFG_REG)); + + mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", + MV_CESA_STATUS_REG, MV_REG_READ(MV_CESA_STATUS_REG)); + + mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_CAUSE_REG, MV_REG_READ(MV_CESA_ISR_CAUSE_REG)); + + mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_MASK_REG, MV_REG_READ(MV_CESA_ISR_MASK_REG)); +#if (MV_CESA_VERSION >= 2) + mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CTRL_REG, MV_REG_READ(MV_CESA_TDMA_CTRL_REG)); + + mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_BYTE_COUNT_REG, MV_REG_READ(MV_CESA_TDMA_BYTE_COUNT_REG)); + + mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_SRC_ADDR_REG, MV_REG_READ(MV_CESA_TDMA_SRC_ADDR_REG)); + + mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_DST_ADDR_REG, MV_REG_READ(MV_CESA_TDMA_DST_ADDR_REG)); + + mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_NEXT_DESC_PTR_REG, MV_REG_READ(MV_CESA_TDMA_NEXT_DESC_PTR_REG)); + + mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CURR_DESC_PTR_REG, MV_REG_READ(MV_CESA_TDMA_CURR_DESC_PTR_REG)); + + mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_CAUSE_REG, MV_REG_READ(MV_CESA_TDMA_ERROR_CAUSE_REG)); + + mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_MASK_REG, MV_REG_READ(MV_CESA_TDMA_ERROR_CAUSE_REG)); + +#endif +} + +void mvCesaDebugStatus(void) +{ + mvOsPrintf("\n\t CESA Status\n\n"); + + mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%d bytes, qRes=%d", + pCesaReqFirst, cesaQueueDepth, (int)sizeof(MV_CESA_REQ), cesaReqResources); + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + mvOsPrintf(", chainLength=%u", cesaChainLength); +#endif + + mvOsPrintf("\n"); + + mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%d bytes\n", pCesaSAD, cesaMaxSA, (int)sizeof(MV_CESA_SA)); + + mvOsPrintf("\n"); + + mvCesaDebugRegs(); + mvCesaDebugStats(); + mvCesaDebugStatsClear(); +} + +void mvCesaDebugDescriptor(MV_CESA_DESC *pDesc) +{ + mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", + pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); + + mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", + pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); + + mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", + pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, + pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); +} + +void mvCesaDebugQueue(int mode) +{ + mvOsPrintf("\n\t CESA Request Queue:\n\n"); + + mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%d bytes\n", + pCesaReqFirst, pCesaReqLast, cesaQueueDepth, (int)sizeof(MV_CESA_REQ)); + + mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", pCesaReqEmpty, pCesaReqProcess, cesaReqResources); + + if (mode != 0) { + int count = 0; + MV_CESA_REQ *pReq = pCesaReqFirst; + + for (count = 0; count < cesaQueueDepth; count++) { + /* Print out requsts */ + mvOsPrintf("%02d. pReq=%p, state=%s, frag=0x%x, pCmd=%p, pDma=%p, pDesc=%p\n", + count, pReq, mvCesaDebugStateStr(pReq->state), + pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); + if (pReq->fragMode != MV_CESA_FRAG_NONE) { + int frag; + + mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", + &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, + pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); + for (frag = 0; frag < pReq->frags.numFrag; frag++) { + mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, + pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); + } + } + if (mode > 1) { + /* Print out Command */ + mvCesaDebugCmd(pReq->pCmd, mode); + + /* Print out Descriptor */ + mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); + } + pReq++; + } + } +} + +void mvCesaDebugSramSA(MV_CESA_SRAM_SA *pSramSA, int mode) +{ + if (pSramSA == NULL) { + mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); + return; + } + mvOsPrintf("pSramSA=%p, sizeSramSA=%d bytes\n", pSramSA, (int)sizeof(MV_CESA_SRAM_SA)); + + if (mode != 0) { + mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); + mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); + + mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); + + mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); + } +} + +void mvCesaDebugSA(short sid, int mode) +{ + MV_CESA_OPERATION oper; + MV_CESA_DIRECTION dir; + MV_CESA_CRYPTO_ALG cryptoAlg; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_CESA_MAC_MODE macMode; + MV_CESA_SA *pSA = pCesaSAD[sid]; + + if (pSA != NULL) { + /*if(((pSA->count != 0) && (mode > 0)) || (mode >= 2)) + { */ + mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", + sid, pSA, (pSA != NULL) ? "Valid" : "Invalid", pSA->count); + + oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; + dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; + mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); + if (oper != MV_CESA_MAC_ONLY) { + cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; + cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; + mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), + (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); + } + if (oper != MV_CESA_CRYPTO_ONLY) { + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; + mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); + } + mvOsPrintf("\n"); + + if (mode > 0) { + mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", + pCesaSAD[sid]->config, pCesaSAD[sid]->cryptoKeyLength, pCesaSAD[sid]->digestSize); + + mvCesaDebugSramSA(pCesaSAD[sid]->pSramSA, mode); + } + /*} */ + } +} + + /**/ void mvCesaDebugSram(int mode) +{ + mvOsPrintf("\n\t SRAM contents: size=%d, pVirt=%p\n\n", (int)sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); + + mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); + if (mode != 0) + mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); + + mvOsPrintf("\n"); + mvOsPrintf("\n\t Sram descriptor: size=%d, pVirt=%p\n", (int)sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); + if (mode != 0) { + mvOsPrintf("\n"); + mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); + } + mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); + if (mode != 0) { + mvOsPrintf("\n"); + mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); + } + mvOsPrintf("\n"); + mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); +} + +void mvCesaDebugSAD(int mode) +{ + int sid; + + mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", pCesaSAD, cesaMaxSA); + + for (sid = 0; sid < cesaMaxSA; sid++) + mvCesaDebugSA(sid, mode); +} + +void mvCesaDebugStats(void) +{ + mvOsPrintf("\n\t Cesa Statistics\n"); + + mvOsPrintf("Opened=%u, Closed=%u\n", cesaStats.openedCount, cesaStats.closedCount); + mvOsPrintf("Req=%u, maxReq=%u, frags=%u, start=%u\n", + cesaStats.reqCount, cesaStats.maxReqCount, cesaStats.fragCount, cesaStats.startCount); + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + mvOsPrintf("maxChainUsage=%u\n", cesaStats.maxChainUsage); +#endif + + mvOsPrintf("\n"); + mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", + cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); +} + +void mvCesaDebugStatsClear(void) +{ + memset(&cesaStats, 0, sizeof(cesaStats)); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.h u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesa.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesa.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,380 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Marvell Cryptographic Engines and Security Accelerator. +* +*******************************************************************************/ + +#ifndef __mvCesa_h__ +#define __mvCesa_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysCesaConfig.h" +#include "mvCesaRegs.h" + + typedef struct { + MV_ULONG sramPhysBase; + MV_U8 *sramVirtBase; + MV_U16 sramOffset; + MV_U16 ctrlModel; /* Controller Model */ + MV_U8 ctrlRev; /* Controller Revision */ + } MV_CESA_HAL_DATA; + +#ifdef MV_INCLUDE_IDMA +#include "idma/mvIdma.h" +#include "idma/mvIdmaRegs.h" +#else +/* Redefine MV_DMA_DESC structure */ + typedef struct _mvDmaDesc { + MV_U32 byteCnt; /* The total number of bytes to transfer */ + MV_U32 phySrcAdd; /* The physical source address */ + MV_U32 phyDestAdd; /* The physical destination address */ + MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ + /* then this pointer should point to the */ + /* physical address of the next descriptor, */ + /* otherwise it should be NULL. */ + } MV_DMA_DESC; +#endif /* MV_INCLUDE_IDMA */ + +#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ + +#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ +#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ + +#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE + +#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ +#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ + +#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH + +#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ + +#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ + +#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE + +#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ + + typedef struct { + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; + MV_CESA_OPERATION operation; + MV_CESA_DIRECTION direction; + MV_CESA_CRYPTO_ALG cryptoAlgorithm; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_U8 cryptoKeyLength; + MV_CESA_MAC_MODE macMode; + MV_U8 macKeyLength; + MV_U8 digestSize; + } MV_CESA_OPEN_SESSION; + + typedef struct { + MV_BUF_INFO *pFrags; + MV_U16 numFrags; + MV_U16 mbufSize; + } MV_CESA_MBUF; + + typedef struct { + void *pReqPrv; /* instead of reqId */ + MV_U32 retCode; + MV_16 sessionId; + } MV_CESA_RESULT; + + typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT * pResult); + + typedef struct { + void *pReqPrv; /* instead of reqId */ + MV_CESA_MBUF *pSrc; + MV_CESA_MBUF *pDst; + MV_CESA_CALLBACK *pFuncCB; + MV_16 sessionId; + MV_U16 ivFromUser; + MV_U16 ivOffset; + MV_U16 cryptoOffset; + MV_U16 cryptoLength; + MV_U16 digestOffset; + MV_U16 macOffset; + MV_U16 macLength; + MV_BOOL skipFlush; + } MV_CESA_COMMAND; + + MV_STATUS mvCesaHalInit(int numOfSession, int queueDepth, void *osHandle, MV_CESA_HAL_DATA *halData); + MV_STATUS mvCesaTdmaWinInit(MV_UNIT_WIN_INFO *addrWinMap); + MV_STATUS mvCesaTdmaWinWrite(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin); + MV_STATUS mvCesaWinRead(MV_U32 unit, MV_U32 winNum, MV_UNIT_WIN_INFO *pDecWin); + MV_STATUS mvCesaFinish(void); + MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short *pSid); + MV_STATUS mvCesaSessionClose(short sid); + MV_STATUS mvCesaCryptoIvSet(MV_U8 *pIV, int ivSize); + + MV_STATUS mvCesaAction(MV_CESA_COMMAND *pCmd); + + MV_U32 mvCesaInProcessGet(void); + MV_STATUS mvCesaReadyDispatch(void); + MV_STATUS mvCesaReadyGet(MV_CESA_RESULT *pResult); + MV_BOOL mvCesaIsReady(void); + + int mvCesaMbufOffset(MV_CESA_MBUF *pMbuf, int offset, int *pBufOffset); + MV_STATUS mvCesaCopyFromMbuf(MV_U8 *pDst, MV_CESA_MBUF *pSrcMbuf, int offset, int size); + MV_STATUS mvCesaCopyToMbuf(MV_U8 *pSrc, MV_CESA_MBUF *pDstMbuf, int offset, int size); + MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF *pMbufDst, int dstMbufOffset, + MV_CESA_MBUF *pMbufSrc, int srcMbufOffset, int size); + MV_STATUS mvCesaUpdateSADSize(MV_U32 size); +/********** Debug functions ********/ + + void mvCesaDebugMbuf(const char *str, MV_CESA_MBUF *pMbuf, int offset, int size); + void mvCesaDebugSA(short sid, int mode); + void mvCesaDebugStats(void); + void mvCesaDebugStatsClear(void); + void mvCesaDebugRegs(void); + void mvCesaDebugStatus(void); + void mvCesaDebugQueue(int mode); + void mvCesaDebugSram(int mode); + void mvCesaDebugSAD(int mode); + +/******** CESA Private definitions ********/ +#if (MV_CESA_VERSION >= 2) +#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) +#define MV_CESA_TDMA_CTRL_VALUE (MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ + | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ + | MV_CESA_TDMA_ENABLE_MASK) +#else +#define MV_CESA_TDMA_CTRL_VALUE (MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ + | MV_CESA_TDMA_ENABLE_MASK) + +#endif +#else +#define MV_CESA_IDMA_CTRL_LOW_VALUE (ICCLR_DST_BURST_LIM_128BYTE \ + | ICCLR_SRC_BURST_LIM_128BYTE \ + | ICCLR_INT_MODE_MASK \ + | ICCLR_BLOCK_MODE \ + | ICCLR_CHAN_ENABLE \ + | ICCLR_DESC_MODE_16M) +#endif /* MV_CESA_VERSION >= 2 */ + +#define MV_CESA_MAX_PKT_SIZE (64 * 1024) +#define MV_CESA_MAX_MBUF_FRAGS 20 + +#define MV_CESA_MAX_REQ_FRAGS ((MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) + +#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) + +#define MAX_CESA_CHAIN_LENGTH 20 + + typedef enum { + MV_CESA_IDLE = 0, + MV_CESA_PENDING, + MV_CESA_PROCESS, + MV_CESA_READY, + MV_CESA_CHAIN, + } MV_CESA_STATE; + +/* Session database */ + +/* Map of Key materials of the session in SRAM. + * Each field must be 8 byte aligned + * Total size: 32 + 24 + 24 = 80 bytes + */ + typedef struct { + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedInner[4]; + MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedOuter[4]; + } MV_CESA_SRAM_SA; + + typedef struct { + MV_CESA_SRAM_SA *pSramSA; + MV_U8 *sramSABuff; /* holds initial allocation virtual address */ + MV_U32 sramSABuffSize; + MV_ULONG sramSAPhysAddr; /* holds initial allocation physical address */ + MV_U32 memHandle; + MV_U32 config; + MV_U8 cryptoKeyLength; + MV_U8 cryptoIvSize; + MV_U8 cryptoBlockSize; + MV_U8 digestSize; + MV_U8 macKeyLength; + MV_U8 ctrMode; + MV_U32 count; + } MV_CESA_SA; + +/* DMA list management */ + typedef struct { + MV_DMA_DESC *pDmaFirst; + MV_DMA_DESC *pDmaLast; + } MV_CESA_DMA; + + typedef struct { + MV_U8 numFrag; + MV_U8 nextFrag; + int bufOffset; + int cryptoSize; + int macSize; + int newDigestOffset; + MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; + } MV_CESA_FRAGS; + +/* Request queue */ + typedef struct { + MV_U8 state; + MV_U8 fragMode; + MV_U8 fixOffset; + MV_CESA_COMMAND *pCmd; + MV_CESA_COMMAND *pOrgCmd; + MV_BUF_INFO dmaDescBuf; + MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; + MV_BUF_INFO cesaDescBuf; + MV_CESA_DESC *pCesaDesc; + MV_CESA_FRAGS frags; + } MV_CESA_REQ; + +/* SRAM map */ +/* Total SRAM size calculation */ +/* SRAM size = + * MV_CESA_MAX_BUF_SIZE + + * sizeof(MV_CESA_DESC) + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_DIGEST_SIZE + + * sizeof(MV_CESA_SRAM_SA) + * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes + * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes + */ + typedef struct { + MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; + MV_CESA_DESC desc; + MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE + 4]; + MV_CESA_SRAM_SA sramSA; + } MV_CESA_SRAM_MAP; + + typedef struct { + MV_U32 openedCount; + MV_U32 closedCount; + MV_U32 fragCount; + MV_U32 reqCount; + MV_U32 maxReqCount; + MV_U32 procCount; + MV_U32 readyCount; + MV_U32 notReadyCount; + MV_U32 startCount; +#ifdef CONFIG_MV_CESA_CHAIN_MODE + MV_U32 maxChainUsage; +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + } MV_CESA_STATS; + +/* External variables */ + + extern MV_CESA_STATS cesaStats; + extern MV_CESA_FRAGS cesaFrags; + + extern MV_CESA_SA **pCesaSAD; + extern MV_U32 cesaMaxSA; + + extern MV_CESA_REQ *pCesaReqFirst; + extern MV_CESA_REQ *pCesaReqLast; + extern MV_CESA_REQ *pCesaReqEmpty; + extern MV_CESA_REQ *pCesaReqProcess; + extern int cesaQueueDepth; + extern int cesaReqResources; + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + extern MV_U32 cesaChainLength; +#endif /* CONFIG_MV_CESA_CHAIN_MODE */ + + extern MV_CESA_SRAM_MAP *cesaSramVirtPtr; + + static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO *pBufInfo, void *pVirt) + { + return (pBufInfo->bufPhysAddr + ((MV_U8 *)pVirt - pBufInfo->bufVirtPtr)); + } +/* Additional DEBUG functions */ void mvCesaDebugSramSA(MV_CESA_SRAM_SA *pSramSA, int mode); + void mvCesaDebugCmd(MV_CESA_COMMAND *pCmd, int mode); + void mvCesaDebugDescriptor(MV_CESA_DESC *pDesc); + +#ifdef __cplusplus +} +#endif + +#endif /* __mvCesa_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaRegs.h u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCesaRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCesaRegs.h 2011-04-04 13:57:34.935597073 -0400 @@ -0,0 +1,356 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvCesaRegs_h__ +#define __mvCesaRegs_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvSysCesaConfig.h" + + typedef struct { + /* word 0 */ + MV_U32 config; + /* word 1 */ + MV_U16 cryptoSrcOffset; + MV_U16 cryptoDstOffset; + /* word 2 */ + MV_U16 cryptoDataLen; + MV_U16 reserved1; + /* word 3 */ + MV_U16 cryptoKeyOffset; + MV_U16 reserved2; + /* word 4 */ + MV_U16 cryptoIvOffset; + MV_U16 cryptoIvBufOffset; + /* word 5 */ + MV_U16 macSrcOffset; + MV_U16 macTotalLen; + /* word 6 */ + MV_U16 macDigestOffset; + MV_U16 macDataLen; + /* word 7 */ + MV_U16 macInnerIvOffset; + MV_U16 macOuterIvOffset; + } MV_CESA_DESC; + +/* operation */ + typedef enum { + MV_CESA_MAC_ONLY = 0, + MV_CESA_CRYPTO_ONLY = 1, + MV_CESA_MAC_THEN_CRYPTO = 2, + MV_CESA_CRYPTO_THEN_MAC = 3, + MV_CESA_MAX_OPERATION + } MV_CESA_OPERATION; + +#define MV_CESA_OPERATION_OFFSET 0 +#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) + +/* mac algorithm */ + typedef enum { + MV_CESA_MAC_NULL = 0, + MV_CESA_MAC_MD5 = 4, + MV_CESA_MAC_SHA1 = 5, + MV_CESA_MAC_HMAC_MD5 = 6, + MV_CESA_MAC_HMAC_SHA1 = 7, + } MV_CESA_MAC_MODE; + +#define MV_CESA_MAC_MODE_OFFSET 4 +#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) + + typedef enum { + MV_CESA_MAC_DIGEST_FULL = 0, + MV_CESA_MAC_DIGEST_96B = 1, + } MV_CESA_MAC_DIGEST_SIZE; + +#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 +#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) + + typedef enum { + MV_CESA_CRYPTO_NULL = 0, + MV_CESA_CRYPTO_DES = 1, + MV_CESA_CRYPTO_3DES = 2, + MV_CESA_CRYPTO_AES = 3, + } MV_CESA_CRYPTO_ALG; + +#define MV_CESA_CRYPTO_ALG_OFFSET 8 +#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) + +/* direction */ + typedef enum { + MV_CESA_DIR_ENCODE = 0, + MV_CESA_DIR_DECODE = 1, + } MV_CESA_DIRECTION; + +#define MV_CESA_DIRECTION_BIT 12 +#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) + +/* crypto IV mode */ + typedef enum { + MV_CESA_CRYPTO_ECB = 0, + MV_CESA_CRYPTO_CBC = 1, + /* NO HW Support */ + MV_CESA_CRYPTO_CTR = 10, + } MV_CESA_CRYPTO_MODE; + +#define MV_CESA_CRYPTO_MODE_BIT 16 +#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) + +/* 3DES mode */ + typedef enum { + MV_CESA_CRYPTO_3DES_EEE = 0, + MV_CESA_CRYPTO_3DES_EDE = 1, + } MV_CESA_CRYPTO_3DES_MODE; + +#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 +#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) + +/* AES Key Length */ + typedef enum { + MV_CESA_CRYPTO_AES_KEY_128 = 0, + MV_CESA_CRYPTO_AES_KEY_192 = 1, + MV_CESA_CRYPTO_AES_KEY_256 = 2, + } MV_CESA_CRYPTO_AES_KEY_LEN; + +#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 +#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) + +/* Fragmentation mode */ + typedef enum { + MV_CESA_FRAG_NONE = 0, + MV_CESA_FRAG_FIRST = 1, + MV_CESA_FRAG_LAST = 2, + MV_CESA_FRAG_MIDDLE = 3, + } MV_CESA_FRAG_MODE; + +#define MV_CESA_FRAG_MODE_OFFSET 30 +#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) +/*---------------------------------------------------------------------------*/ + +/********** Security Accelerator Command Register **************/ +#define MV_CESA_CMD_REG (MV_CESA_REGS_BASE + 0xE00) + +#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 +#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) + +#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 +#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) + +/********** Security Accelerator Descriptor Pointers Register **********/ +#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REGS_BASE + 0xE04) + +/********** Security Accelerator Configuration Register **********/ +#define MV_CESA_CFG_REG (MV_CESA_REGS_BASE + 0xE08) + +#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 +#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) + +#define MV_CESA_CFG_WAIT_DMA_BIT 7 +#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) + +#define MV_CESA_CFG_ACT_DMA_BIT 9 +#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) + +#define MV_CESA_CFG_CHAIN_MODE_BIT 11 +#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) + +/********** Security Accelerator Status Register ***********/ +#define MV_CESA_STATUS_REG (MV_CESA_REGS_BASE + 0xE0C) + +#define MV_CESA_STATUS_ACTIVE_BIT 0 +#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) + +#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 +#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) + +/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ +#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REGS_BASE + 0xE20) + +/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ +#define MV_CESA_ISR_MASK_REG (MV_CESA_REGS_BASE + 0xE24) + +#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) +#define MV_CESA_CAUSE_DES_MASK (1 << 1) +#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) +#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) +#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) + +#define MV_CESA_CAUSE_ACC_BIT 5 +#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) + +#define MV_CESA_CAUSE_ACC_DMA_BIT 7 +#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) +#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) + +#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 +#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) + +#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 +#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) + +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) + +#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REGS_BASE + 0xd38) +#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REGS_BASE + 0xd20) +#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REGS_BASE + 0xd24) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REGS_BASE + 0xd00 + (i<<2)) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REGS_BASE + 0xd00) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REGS_BASE + 0xd04) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REGS_BASE + 0xd08) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REGS_BASE + 0xd0c) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REGS_BASE + 0xd10) +#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REGS_BASE + 0xd18) + +#define MV_CESA_AUTH_ALGORITHM_BIT 0 +#define MV_CESA_AUTH_ALGORITHM_MD5 (0< +wait_queue_head_t cesaTest_waitq; +spinlock_t cesaLock; + +#define CESA_TEST_LOCK(flags) spin_lock_irqsave(&cesaLock, flags) +#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore(&cesaLock, flags); + +#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) +#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) +#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) + +#define CESA_TEST_TICK_GET() jiffies +#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) + +#elif defined(MV_NETBSD) + +#include +#include +static int cesaLock; + +#define CESA_TEST_LOCK(flags) flags = splnet() +#define CESA_TEST_UNLOCK(flags) splx(flags) + +#define CESA_TEST_WAIT_INIT() /* nothing */ +#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) +#define CESA_TEST_WAIT(cond, ms) \ +do { \ + while (!(cond)) \ + tsleep(&cesaLock, PWAIT, "cesatest", mstohz(ms)); \ +} while (/*CONSTCOND*/0) + +#define CESA_TEST_TICK_GET() hardclock_ticks +#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) + +#define request_irq(i, h, t, n, a) \ + (!mv_intr_establish((i), IPL_NET, (int(*)(void *))(h), (a))) + +#else +#error "Only Linux, VxWorks, or NetBSD OS are supported" +#endif + +#include "mvDebug.h" + +#include "mvSysCesaConfig.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#if defined(CONFIG_MV646xx) +#include "marvell_pic.h" +#endif + +#define MV_CESA_USE_TIMER_ID 0 +#define CESA_DEF_BUF_SIZE 1500 +#define CESA_DEF_BUF_NUM 1 +#define CESA_DEF_SESSION_NUM 32 + +#define CESA_DEF_ITER_NUM 100 + +#define CESA_DEF_REQ_SIZE 256 + +/* CESA Tests Debug */ +#undef CESA_TEST_DEBUG + +#ifdef CESA_TEST_DEBUG + +# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg +# define CESA_TEST_DEBUG_CODE(code) code + +typedef struct { + int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ + MV_U32 timeStamp; + MV_U32 cause; + MV_U32 realCause; + MV_U32 dmaCause; + int resources; + MV_CESA_REQ *pReqReady; + MV_CESA_REQ *pReqEmpty; + MV_CESA_REQ *pReqProcess; +} MV_CESA_TEST_TRACE; + +#define MV_CESA_TEST_TRACE_SIZE 25 + +static int cesaTestTraceIdx = 0; +static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; + +static void cesaTestTraceAdd(int type, MV_U32 cause) +{ + cesaTestTrace[cesaTestTraceIdx].type = type; + cesaTestTrace[cesaTestTraceIdx].cause = cause; + cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; + cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; + cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; + cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; + cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); + cesaTestTraceIdx++; + if (cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) + cesaTestTraceIdx = 0; +} + +#else + +# define CESA_TEST_DEBUG_PRINT(msg) +# define CESA_TEST_DEBUG_CODE(code) + +#endif /* CESA_TEST_DEBUG */ + +int cesaExpReqId = 0; +int cesaCbIter = 0; + +int cesaIdx; +int cesaIteration; +int cesaRateSize; +int cesaReqSize; +unsigned long cesaTaskId; +int cesaBufNum; +int cesaBufSize; +int cesaCheckOffset; +int cesaCheckSize; +int cesaCheckMode; +int cesaTestIdx; +int cesaCaseIdx; + +MV_U32 cesaTestIsrCount = 0; +MV_U32 cesaTestIsrMissCount = 0; + +MV_U32 cesaCryptoError = 0; +MV_U32 cesaReqIdError = 0; +MV_U32 cesaError = 0; + +char *cesaHexBuffer = NULL; + +char *cesaBinBuffer = NULL; +char *cesaExpBinBuffer = NULL; + +char *cesaInputHexStr = NULL; +char *cesaOutputHexStr = NULL; + +MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; + +MV_CESA_COMMAND *cesaCmdRing; +MV_CESA_RESULT cesaResult; + +int cesaTestFull = 0; + +MV_BOOL cesaIsReady = MV_FALSE; +MV_U32 cesaCycles = 0; +MV_U32 cesaBeginTicks = 0; +MV_U32 cesaEndTicks = 0; +MV_U32 cesaRate = 0; +MV_U32 cesaRateAfterDot = 0; + +void *cesaTestOSHandle = NULL; + +enum { + CESA_FAST_CHECK_MODE = 0, + CESA_FULL_CHECK_MODE, + CESA_NULL_CHECK_MODE, + CESA_SHOW_CHECK_MODE, + CESA_SW_SHOW_CHECK_MODE, + CESA_SW_NULL_CHECK_MODE, + + CESA_MAX_CHECK_MODE +}; + +enum { + DES_TEST_TYPE = 0, + TRIPLE_DES_TEST_TYPE = 1, + AES_TEST_TYPE = 2, + MD5_TEST_TYPE = 3, + SHA_TEST_TYPE = 4, + COMBINED_TEST_TYPE = 5, + + MAX_TEST_TYPE +}; + +/* Tests data base */ +typedef struct { + short sid; + char cryptoAlgorithm; /* DES/3DES/AES */ + char cryptoMode; /* ECB or CBC */ + char macAlgorithm; /* MD5 / SHA1 */ + char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ + char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ + unsigned char *pCryptoKey; + int cryptoKeySize; + unsigned char *pMacKey; + int macKeySize; + const char *name; +} MV_CESA_TEST_SESSION; + +typedef struct { + MV_CESA_TEST_SESSION *pSessions; + int numSessions; +} MV_CESA_TEST_DB_ENTRY; + +typedef struct { + char *plainHexStr; + char *cipherHexStr; + unsigned char *pCryptoIV; + int cryptoLength; + int macLength; + int digestOffset; +} MV_CESA_TEST_CASE; + +typedef struct { + int size; + const char *outputHexStr; +} MV_CESA_SIZE_TEST; + +static unsigned char cryptoKey1[] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef +}; + +static unsigned char cryptoKey7[] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef }; +static unsigned char iv1[] = { 0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef }; + +static unsigned char cryptoKey2[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +}; + +static unsigned char cryptoKey3[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 +}; + +static unsigned char cryptoKey4[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f +}; + +static unsigned char cryptoKey5[] = { 0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, + 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49 +}; + +static unsigned char key3des1[] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, + 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23 +}; + +/* Input ASCII string: The quick brown fox jump */ +static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; +static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; + +static unsigned char key3des2[] = { 0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, + 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, + 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c +}; + +static unsigned char iv3des2[] = { 0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75 }; + +static char plain3des2[] = "326a494cd33fe756"; + +static char cipher3desCbc2[] = "8e29f75ea77e5475" "b22b8d66de970692"; + +static unsigned char key3des3[] = { 0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, + 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, + 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae +}; + +static unsigned char iv3des3[] = { 0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65 }; + +static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; + +static char cipher3desCbc3[] = "3d1de3cc132e3b65" "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; + +static unsigned char iv5[] = { 0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, + 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9 +}; + +static unsigned char aesCtrKey[] = { 0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC +}; + +static unsigned char mdKey1[] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b +}; + +static unsigned char mdKey2[] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa +}; + +static unsigned char shaKey1[] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b +}; + +static unsigned char shaKey2[] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa +}; + +static unsigned char mdKey4[] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 +}; + +static unsigned char shaKey4[] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, + 0x11, 0x12, 0x13, 0x14 +}; + +static MV_CESA_TEST_SESSION desTestSessions[] = { +/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7) / sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB encode", + } + , +/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7) / sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB decode", + } + , +/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7) / sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC encode"} + , +/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7) / sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC decode"} + , +/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, NULL, 0, + "NULL Crypto Algorithm encode"} + , +}; + +static MV_CESA_TEST_SESSION tripleDesTestSessions[] = { +/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB encode", + } + , +/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB decode", + } + , +/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC encode"} + , +/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC decode"} + , +/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des1, sizeof(key3des1), + NULL, 0, + "3DES ECB encode"} + , +/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des2, sizeof(key3des2), + NULL, 0, + "3DES ECB encode"} + , +/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des3, sizeof(key3des3), + NULL, 0, + "3DES ECB encode"} + , +}; + +static MV_CESA_TEST_SESSION aesTestSessions[] = { +/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey2, sizeof(cryptoKey2) / sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB encode"} + , +/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey2, sizeof(cryptoKey2) / sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB decode"} + , +/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5) / sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC encode"} + , +/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey5, sizeof(cryptoKey5) / sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC decode"} + , +/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey3, sizeof(cryptoKey3) / sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB encode"} + , +/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey3, sizeof(cryptoKey3) / sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB decode"} + , +/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey4, sizeof(cryptoKey4) / sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB encode"} + , +/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey4, sizeof(cryptoKey4) / sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB decode"} + , +/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + aesCtrKey, sizeof(aesCtrKey) / sizeof(aesCtrKey[0]), + NULL, 0, + "AES-128 CTR encode"} + , +}; + +static MV_CESA_TEST_SESSION md5TestSessions[] = { +/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Generate Signature"} + , +/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Verify Signature"} + , +/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Generate Signature"} + , +/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Verify Signature"} + , +/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey4, sizeof(mdKey4), + "HMAC-MD5 Generate Signature"} + , +/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-MD5 Generate Signature"} + , +}; + +static MV_CESA_TEST_SESSION shaTestSessions[] = { +/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Generate Signature"} + , +/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Verify Signature"} + , +/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Generate Signature"} + , +/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Verify Signature"} + , +/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey4, sizeof(shaKey4), + "HMAC-SHA1 Generate Signature"} + , +/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-SHA1 Generate Signature"} + , +}; + +static MV_CESA_TEST_SESSION combinedTestSessions[] = { +/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + mdKey4, sizeof(mdKey4), + "DES + MD5 encode"} + , +/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + shaKey4, sizeof(shaKey4), + "DES + SHA1 encode"} + , +/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES + MD5 encode"} + , +/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES + SHA1 encode"} + , +/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES CBC + MD5 encode"} + , +/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES CBC + SHA1 encode"} + , +/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5) / sizeof(cryptoKey5[0]), + mdKey4, sizeof(mdKey4), + "AES-128 CBC + MD5 encode"} + , +/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5) / sizeof(cryptoKey5[0]), + shaKey4, sizeof(shaKey4), + "AES-128 CBC + SHA1 encode"} + , +/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1) / sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "HMAC-MD5 + 3DES decode"} + , +}; + +static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE + 1] = { + {desTestSessions, sizeof(desTestSessions) / sizeof(desTestSessions[0])} + , + {tripleDesTestSessions, sizeof(tripleDesTestSessions) / sizeof(tripleDesTestSessions[0])} + , + {aesTestSessions, sizeof(aesTestSessions) / sizeof(aesTestSessions[0])} + , + {md5TestSessions, sizeof(md5TestSessions) / sizeof(md5TestSessions[0])} + , + {shaTestSessions, sizeof(shaTestSessions) / sizeof(shaTestSessions[0])} + , + {combinedTestSessions, sizeof(combinedTestSessions) / sizeof(combinedTestSessions[0])} + , + {NULL, 0} +}; + +char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; + +char cesaPlainAsciiText[] = "Now is the time for all "; +char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; +char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; + +char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; +char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; +char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; +char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; + +char cesaAsciiStr1[] = "Hi There"; +char cesaDataHexStr1[] = "4869205468657265"; +char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; +char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; +char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; +char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; + +char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" "35907aa632c3ffdf868bb7b29d3d46ad" "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" "35907aa632c3ffdf868bb7b29d3d46ad" "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" + "000102030405060708090A0B0C0D0E0F" "101112131415161718191A1B1C1D1E1F" "20212223"; + +char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" + "C1CF48A89F2FFDD9CF4652E9EFDB72D7" "4540A42BDE6D7836D59A5CEAAEF31053" "25B2072F"; + +/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ +char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; +char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; +char cesaDataHexStr3[50 * 2 + 1] = ""; +char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3) + sizeof(cesaHmacMd5digestHex3) + 8 * 2 + 1] = ""; +char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3) + sizeof(cesaHmacSha1digestHex3) + 8 * 2 + 1] = ""; + +/* Ascii string is "abc" */ +char hashHexStr3[] = "616263"; +char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; +char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; + +char hashHexStr80[] = "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" "31323334353637383930" "31323334353637383930" "31323334353637383930" "31323334353637383930"; + +char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; + +char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; +char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; + +char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; +char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; + +char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; +char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; + +static MV_CESA_TEST_CASE cesaTestCases[] = { + /* plainHexStr cipherHexStr IV crypto mac digest */ + /* Length Length Offset */ + /*0 */ {NULL, NULL, NULL, 0, 0, -1}, + /*1 */ {cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1}, + /*2 */ {cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1}, + /*3 */ {cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1}, + /*4 */ {cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1}, + /*5 */ {cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1}, + /*6 */ {cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1}, + /*7 */ {NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1}, + /*8 */ {cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1}, + /*9 */ {NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1}, +/*10*/ {cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1}, +/*11*/ {cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1}, +/*12*/ {NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1}, +/*13*/ {cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1}, +/*14*/ {NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1}, +/*15*/ {hashHexStr3, hashMd5digest3, NULL, 0, 3, -1}, +/*16*/ {hashHexStr3, hashSha1digest3, NULL, 0, 3, -1}, +/*17*/ {hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1}, +/*18*/ {hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1}, +/*19*/ {hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1}, +/*20*/ {hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1}, +/*21*/ {hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1}, +/*22*/ {hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1}, +/*23*/ {cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1}, +/*24*/ {cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1}, +/*25*/ {plain3des1, cipher3des1, NULL, 0, 0, -1}, +/*26*/ {plain3des2, cipher3desCbc2, iv3des2, 0, 0, -1}, +/*27*/ {plain3des3, cipher3desCbc3, iv3des3, 0, 0, -1}, +}; + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * Input 0xdd repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = { + {80, "7a031a640c14a4872814930b1ef3a5b2"}, + {512, "5488e6c5a14dc72a79f28312ca5b939b"}, + {1000, "d00814f586a8b78a05724239d2531821"}, + {1001, "bf07df7b7f49d3f5b5ecacd4e9e63281"}, + {1002, "1ed4a1a802e87817a819d4e37bb4d0f7"}, + {1003, "5972ab64a4f265ee371dac2f2f137f90"}, + {1004, "71f95e7ec3aa7df2548e90898abdb28e"}, + {1005, "e082790b4857fcfc266e92e59e608814"}, + {1006, "9500f02fd8ac7fde8b10e4fece9a920d"}, + {1336, "e42edcce57d0b75b01aa09d71427948b"}, + {1344, "bb5454ada0deb49ba0a97ffd60f57071"}, + {1399, "0f44d793e744b24d53f44f295082ee8c"}, + {1400, "359de8a03a9b707928c6c60e0e8d79f1"}, + {1401, "e913858b484cbe2b384099ea88d8855b"}, + {1402, "d9848a164af53620e0540c1d7d87629e"}, + {1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822"}, + {1404, "12edd4f609416e3c936170360561b064"}, + {1405, "7fc912718a05446395345009132bf562"}, + {1406, "882f17425e579ff0d85a91a59f308aa0"}, + {1407, "005cae408630a2fb5db82ad9db7e59da"}, + {1408, "64655f8b404b3fea7a3e3e609bc5088f"}, + {1409, "4a145284a7f74e01b6bb1a0ec6a0dd80"}, + {2048, "67caf64475650732def374ebb8bde3fd"}, + {2049, "6c84f11f472825f7e6cd125c2981884b"}, + {2050, "8999586754a73a99efbe4dbad2816d41"}, + {2051, "ba6946b610e098d286bc81091659dfff"}, + {2052, "d0afa01c92d4d13def2b024f36faed83"}, + {3072, "61d8beac61806afa2585d74a9a0e6974"}, + {3074, "f6501a28dcc24d1e4770505c51a87ed3"}, + {3075, "ea4a6929be67e33e61ff475369248b73"}, + {4048, "aa8c4d68f282a07e7385acdfa69f4bed"}, + {4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a"}, + {4058, "9e8553f9bdd43aebe0bd729f0e600c99"}, + {6144, "f628f3e5d183fe5cdd3a5abee39cf872"}, + {6150, "89a3efcea9a2f25f919168ad4a1fd292"}, + {6400, "cdd176b7fb747873efa4da5e32bdf88f"}, + {6528, "b1d707b027354aca152c45ee559ccd3f"}, + {8192, "c600ea4429ac47f9941f09182166e51a"}, + {16384, "16e8754bfbeb4c649218422792267a37"}, + {18432, "0fd0607521b0aa8b52219cfbe215f63e"}, + {0, NULL}, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = { + {80, "a456c4723fee6068530af5a2afa71627"}, + {512, "f85c2a2344f5de68b432208ad13e5794"}, + {1000, "35464d6821fd4a293a41eb84e274c8c5"}, + {1001, "c08eedbdce60cceb54bc2d732bb32c8b"}, + {1002, "5664f71800c011cc311cb6943339c1b8"}, + {1003, "779c723b044c585dc7802b13e8501bdc"}, + {1004, "55e500766a2c307bc5c5fdd15e4cacd4"}, + {1005, "d5f978954f5c38529d1679d2b714f068"}, + {1006, "cd3efc827ce628b7281b72172693abf9"}, + {1336, "6f04479910785878ae6335b8d1e87edf"}, + {1344, "b6d27b50c2bce1ba2a8e1b5cc4324368"}, + {1399, "65f70a1d4c86e5eaeb0704c8a7816795"}, + {1400, "3394b5adc4cb3ff98843ca260a44a88a"}, + {1401, "3a06f3582033a66a4e57e0603ce94e74"}, + {1402, "e4d97f5ed51edc48abfa46eeb5c31752"}, + {1403, "3d05e40b080ee3bedf293cb87b7140e7"}, + {1404, "8cf294fc3cd153ab18dccb2a52cbf244"}, + {1405, "d1487bd42f6edd9b4dab316631159221"}, + {1406, "0527123b6bf6936cf5d369dc18c6c70f"}, + {1407, "3224a06639db70212a0cd1ae1fcc570a"}, + {1408, "a9e13335612c0356f5e2c27086e86c43"}, + {1409, "a86d1f37d1ed8a3552e9a4f04dceea98"}, + {2048, "396905c9b961cd0f6152abfb69c4449c"}, + {2049, "49f39bff85d9dcf059fadb89efc4a70f"}, + {2050, "3a2b4823bc4d0415656550226a63e34a"}, + {2051, "dec60580d406c782540f398ad0bcc7e0"}, + {2052, "32f76610a14310309eb748fe025081bf"}, + {3072, "45edc1a42bf9d708a621076b63b774da"}, + {3074, "9be1b333fe7c0c9f835fb369dc45f778"}, + {3075, "8c06fcac7bd0e7b7a17fd6508c09a549"}, + {4048, "0ddaef848184bf0ad98507a10f1e90e4"}, + {4052, "81976bcaeb274223983996c137875cb8"}, + {4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22"}, + {6144, "1c24056f52725ede2dff0d7f9fc9855f"}, + {6150, "b7f4b65681c4e43ee68ca466ca9ca4ec"}, + {6400, "443bbaab9f7331ddd4bf11b659cd43c8"}, + {6528, "216f44f23047cfee03a7a64f88f9a995"}, + {8192, "ac7a993b2cad54879dba1bde63e39097"}, + {8320, "55ed7be9682d6c0025b3221a62088d08"}, + {16384, "c6c722087653b62007aea668277175e5"}, + {18432, "f1faca8e907872c809e14ffbd85792d6"}, + {0, NULL}, +}; + +/* HASH-MD5 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = { + {80, "57edf4a22be3c955ac49da2e2107b67a"}, + {512, "c729ae8f0736cc377a9767a660eaa04e"}, + {1000, "f1257a8659eb92d36fe14c6bf3852a6a"}, + {1001, "f8a46fe8ea04fdc8c7de0e84042d3878"}, + {1002, "da188dd67bff87d58aa3c02af2d0cc0f"}, + {1003, "961753017feee04c9b93a8e51658a829"}, + {1004, "dd68c4338608dcc87807a711636bf2af"}, + {1005, "e338d567d3ce66bf69ada29658a8759b"}, + {1006, "443c9811e8b92599b0b149e8d7ec700a"}, + {1336, "89a98511706008ba4cbd0b4a24fa5646"}, + {1344, "335a919805f370b9e402a62c6fe01739"}, + {1399, "5d18d0eddcd84212fe28d812b5e80e3b"}, + {1400, "6b695c240d2dffd0dffc99459ca76db6"}, + {1401, "49590f61298a76719bc93a57a30136f5"}, + {1402, "94c2999fa3ef1910a683d69b2b8476f2"}, + {1403, "37073a02ab00ecba2645c57c228860db"}, + {1404, "1bcd06994fce28b624f0c5fdc2dcdd2b"}, + {1405, "11b93671a64c95079e8cf9e7cddc8b3d"}, + {1406, "4b6695772a4c66313fa4871017d05f36"}, + {1407, "d1539b97fbfda1c075624e958de19c5b"}, + {1408, "b801b9b69920907cd018e8063092ede9"}, + {1409, "b765f1406cfe78e238273ed01bbcaf7e"}, + {2048, "1d7e2c64ac29e2b3fb4c272844ed31f5"}, + {2049, "71d38fac49c6b1f4478d8d88447bcdd0"}, + {2050, "141c34a5592b1bebfa731e0b23d0cdba"}, + {2051, "c5e1853f21c59f5d6039bd13d4b380d8"}, + {2052, "dd44a0d128b63d4b5cccd967906472d7"}, + {3072, "37d158e33b21390822739d13db7b87fe"}, + {3074, "aef3b209d01d39d0597fe03634bbf441"}, + {3075, "335ffb428eabf210bada96d74d5a4012"}, + {4048, "2434c2b43d798d2819487a886261fc64"}, + {4052, "ac2fa84a8a33065b2e92e36432e861f8"}, + {4058, "856781f85616c341c3533d090c1e1e84"}, + {6144, "e5d134c652c18bf19833e115f7a82e9b"}, + {6150, "a09a353be7795fac2401dac5601872e6"}, + {6400, "08b9033ac6a1821398f50af75a2dbc83"}, + {6528, "3d47aa193a8540c091e7e02f779e6751"}, + {8192, "d3164e710c0626f6f395b38f20141cb7"}, + {8320, "b727589d9183ff4e8491dd24466974a3"}, + {16384, "3f54d970793d2274d5b20d10a69938ac"}, + {18432, "f558511dcf81985b7a1bb57fad970531"}, + {0, NULL}, +}; + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * 0xaa, 0xaa, 0xaa, 0xaa + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = { + {80, "e812f370e659705a1649940d1f78cd7af18affd3"}, + {512, "e547f886b2c15d995ed76a8a924cb408c8080f66"}, + {1000, "239443194409f1a5342ecde1a092c8f3a3ed790a"}, + {1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5"}, + {1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72"}, + {1003, "0fae6046c7dc1d3e356b25af836f6077a363f338"}, + {1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a"}, + {1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1"}, + {1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c"}, + {1336, "f5950ee1d77c10e9011d2149699c9366fe52529c"}, + {1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838"}, + {1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218"}, + {1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51"}, + {1401, "23ae462a7a0cb440f7445791079a5d75a535dd33"}, + {1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa"}, + {1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95"}, + {1404, "867c79042e64f310628e219d8b85594cd0c7adc3"}, + {1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3"}, + {1406, "0df43daab2786172f9b8d07d61f14a070cf1287a"}, + {1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391"}, + {1408, "3987511182b18473a564436003139b808fa46343"}, + {1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901"}, + {2048, "921109c99f3fedaca21727156d5f2b4460175327"}, + {2049, "47188600dd165eb45f27c27196d3c46f4f042c1b"}, + {2050, "8831939904009338de10e7fa670847041387807d"}, + {2051, "2f8ebb5db2997d614e767be1050366f3641e7520"}, + {2052, "669e51cd730dae158d3bef8adba075bd95a0d011"}, + {3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5"}, + {3074, "216ea26f02976a261b7d21a4dd3085157bedfabd"}, + {3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0"}, + {4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8"}, + {4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6"}, + {4058, "db2a9be5ee8124f091c7ebd699266c5de223c164"}, + {6144, "855109903feae2ba3a7a05a326b8a171116eb368"}, + {6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78"}, + {6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7"}, + {6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36"}, + {8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c"}, + {8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329"}, + {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1"}, + {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1"}, + {0, NULL}, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = { + {80, "beaf20a34b06a87558d156c0949bc3957d40222e"}, + {512, "3353955358d886bc2940a3c7f337ff7dafb59c7b"}, + {1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f"}, + {1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4"}, + {1002, "a146d14a6fc3c274ff600568f4d75b977989e00d"}, + {1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5"}, + {1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7"}, + {1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3"}, + {1006, "6d875319049314b61855101a647b9ba3313428e6"}, + {1336, "c1631ea80bad9dc43a180712461b65a0598c711c"}, + {1344, "816069bf91d34581005746e2e0283d0f9c7b7605"}, + {1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af"}, + {1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723"}, + {1401, "ab00c12be62336964cbce31ae97fe2a0002984d5"}, + {1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6"}, + {1403, "3edbc0f61e435bc1317fa27d840076093fb79353"}, + {1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e"}, + {1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987"}, + {1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90"}, + {1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9"}, + {1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b"}, + {1409, "c700acd3ecd19014ea2bdb4d42510c467e088475"}, + {2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b"}, + {2049, "683762d7a02983b26a6d046e6451d9cd82c25932"}, + {2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f"}, + {2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7"}, + {2052, "452395ae05b3ec503eea34f86fc0832485ad97c1"}, + {3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a"}, + {3074, "4e24785ef080141ce4aab4675986d9acea624d7c"}, + {3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf"}, + {4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad"}, + {4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0"}, + {4058, "c800b9e562e1c91e1310116341a3c91d37f848ec"}, + {6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6"}, + {6150, "d957030e0f13c5df07d9eec298542d8f94a07f12"}, + {6400, "bb745313c3d7dc17b3f955e5534ad500a1082613"}, + {6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb"}, + {8192, "5237fd9a81830c974396f99f32047586612ff3c0"}, + {8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf"}, + {16384, "62e093fde467f0748087beea32e9af97d5c61241"}, + {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929"}, + {0, NULL}, +}; + +/* HASH-SHA1 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = { + {80, "50abf5706a150990a08b2c5ea40fa0e585554732"}, + {512, "f14516a08948fa27917a974d219741a697ba0087"}, + {1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4"}, + {1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2"}, + {1002, "d83bc973eaaedb8a31437994dabbb3304b0be086"}, + {1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c"}, + {1004, "e4375d09b1223385a8a393066f8209acfd936a80"}, + {1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99"}, + {1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680"}, + {1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d"}, + {1344, "b52096c6445e6c0a8355995c70dc36ae186c863c"}, + {1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b"}, + {1400, "e53ff664064bc09fe5054c650806bd42d8179518"}, + {1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64"}, + {1402, "34ede0e9a909dd84a2ae291539105c0507b958e1"}, + {1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0"}, + {1404, "29740fd2b04e7a8bfd32242db6233156ad699948"}, + {1405, "65b17397495b70ce4865dad93bf991b74c97cce1"}, + {1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3"}, + {1407, "3eebf82f7420188e23d328b7ce93580b279a5715"}, + {1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec"}, + {1409, "95d74df739181a4ff30b8c39e28793a36598e924"}, + {2048, "aa40262509c2abf84aab0197f83187fc90056d91"}, + {2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea"}, + {2050, "d2e30f77ec81197de20f56588a156094ecb88450"}, + {2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92"}, + {2052, "f843141e57875cd669af58744bc60aa9ea59549c"}, + {3072, "09c5fedeaa62c132e673cc3c608a00142273d086"}, + {3074, "b09e95eea9c7b1b007a58accec488301901a7f3d"}, + {3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc"}, + {4048, "e99394894f855821951ddddf5bfc628547435f5c"}, + {4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382"}, + {4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef"}, + {6144, "2e7f62d35a860988e1224dc0543204af19316041"}, + {6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51"}, + {6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976"}, + {6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8"}, + {8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992"}, + {8320, "91606a31b46afeaac965cecf87297e791b211013"}, + {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569"}, + {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = { + {64, "9586962a2aaaef28803dec2e17807a7f"}, + {80, "b7726a03aad490bd6c5a452a89a1b271"}, + {352, "f1ed9563aecc3c0d2766eb2bed3b4e4c"}, + {512, "0f9decb11ab40fe86f4d4d9397bc020e"}, + {1000, "3ba69deac12cab8ff9dff7dbd9669927"}, + {1336, "6cf47bf1e80e03e2c1d0945bc50d37d2"}, + {1344, "4be388dab21ceb3fa1b8d302e9b821f7"}, + {1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1"}, + {1408, "8bc97379fc2ac3237effcdd4f7a86528"}, + {2048, "1339f03ab3076f25a20bc4cba16eb5bf"}, + {3072, "731204d2d90c4b36ae41f5e1fb874288"}, + {4048, "c028d998cfda5642547b7e1ed5ea16e4"}, + {6144, "b1b19cd910cc51bd22992f1e59f1e068"}, + {6400, "44e4613496ba622deb0e7cb768135a2f"}, + {6528, "3b06b0a86f8db9cd67f9448dfcf10549"}, + {8192, "d581780b7163138a0f412be681457d82"}, + {16384, "03b8ac05527faaf1bed03df149c65ccf"}, + {18432, "677c8a86a41dab6c5d81b85b8fb10ff6"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = { + {64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2"}, + {80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"}, + {352, "4b91864c7ff629bdff75d9726421f76705452aaf"}, + {512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5"}, + {1000, "463661c30300be512a9df40904f0757cde5f1141"}, + {1336, "b931f831d9034fe59c65176400b039fe9c1f44a5"}, + {1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1"}, + {1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb"}, + {1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4"}, + {2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac"}, + {3072, "5b83625adb43a488b8d64fecf39bb766818547b7"}, + {4048, "d2c533678d26c970293af60f14c8279dc708bfc9"}, + {6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c"}, + {6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0"}, + {6528, "376792b8c8d18161d15579fb7829e6e3a27e9946"}, + {8192, "d890eabdca195b34ef8724b28360cffa92ae5655"}, + {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9"}, + {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = { + {64, "8d10e00802460ede0058c139ba48bd2d"}, + {80, "6f463057e1a90e0e91ae505b527bcec0"}, + {352, "4938d48bdf86aece2c6851e7c6079788"}, + {512, "516705d59f3cf810ebf2a13a23a7d42e"}, + {1000, "a5a000ee5c830e67ddc6a2d2e5644b31"}, + {1336, "44af60087b74ed07950088efbe3b126a"}, + {1344, "1f5b39e0577920af731dabbfcf6dfc2a"}, + {1400, "6804ea640e29b9cd39e08bc37dbce734"}, + {1408, "4fb436624b02516fc9d1535466574bf9"}, + {2048, "c909b0985c423d8d86719f701e9e83db"}, + {3072, "cfe0bc34ef97213ee3d3f8b10122db21"}, + {4048, "03ea10b5ae4ddeb20aed6af373082ed1"}, + {6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf"}, + {6400, "6995f85d9d4985dd99e974ec7dda9dd6"}, + {6528, "bbbb548ce2fa3d58467f6a6a5168a0e6"}, + {8192, "afe101fbe745bb449ae4f50d10801456"}, + {16384, "9741706d0b1c923340c4660ff97cacdf"}, + {18432, "b0217becb73cb8f61fd79c7ce9d023fb"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = { + {64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98"}, + {80, "1b002ed050be743aa98860cf35659646bb8efcc0"}, + {352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff"}, + {512, "cfb5253fb4bf72b743320c30c7e48c54965853b0"}, + {1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f"}, + {1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627"}, + {1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2"}, + {1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e"}, + {1408, "473a581c5f04f7527d50793c845471ac87e86430"}, + {2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb"}, + {3072, "275664afd7a561d804e6b0d204e53939cde653ae"}, + {4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3"}, + {6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5"}, + {6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347"}, + {6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41"}, + {8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7"}, + {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce"}, + {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = { + {16, "7ca4c2ba866751598720c5c4aa0d6786"}, + {64, "7dba7fb988e80da609b1fea7254bced8"}, + {80, "6b6e863ac5a71d15e3e9b1c86c9ba05f"}, + {352, "a1ceb9c2e3021002400d525187a9f38c"}, + {512, "596c055c1c55db748379223164075641"}, + {1008, "f920989c02f3b3603f53c99d89492377"}, + {1344, "2e496b73759d77ed32ea222dbd2e7b41"}, + {1408, "7178c046b3a8d772efdb6a71c4991ea4"}, + {2048, "a917f0099c69eb94079a8421714b6aad"}, + {3072, "693cd5033d7f5391d3c958519fa9e934"}, + {4048, "139dca91bcff65b3c40771749052906b"}, + {6144, "428d9cef6df4fb70a6e9b6bbe4819e55"}, + {6400, "9c0b909e76daa811e12b1fc17000a0c4"}, + {6528, "ad876f6297186a7be1f1b907ed860eda"}, + {8192, "479cbbaca37dd3191ea1f3e8134a0ef4"}, + {16384, "60fda559c74f91df538100c9842f2f15"}, + {18432, "4a3eb1cba1fa45f3981270953f720c42"}, + {0, NULL}, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = { + {16, "9aa8dc1c45f0946daf78057fa978759c625c1fee"}, + {64, "9f588fc1ede851e5f8b20256abc9979465ae2189"}, + {80, "13558472d1fc1c90dffec6e5136c7203452d509b"}, + {352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06"}, + {512, "096874951a77fbbf333e49d80c096ee2016e09bd"}, + {1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac"}, + {1344, "79bf77509935ccd3528caaac6a5eb6481f74029b"}, + {1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1"}, + {2048, "3d50d0c005feba92fe41502d609fced9c882b4d1"}, + {3072, "758807e5b983e3a91c06fb218fe0f73f77111e94"}, + {4048, "ca90e85242e33f005da3504416a52098d0d31fb2"}, + {6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf"}, + {6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43"}, + {6528, "0389016a39485d6e330f8b4215ddf718b404f7e9"}, + {8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b"}, + {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f"}, + {18432, "8dfad627922ce15df1eed10bdbed49244efa57db"}, + {0, NULL}, +}; + +void cesaTestPrintStatus(void); + +/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND *pCmd, + MV_CESA_TEST_SESSION *pTestSession, MV_U8 *pIV, int ivSize); +MV_STATUS testClose(int idx); +MV_STATUS testOpen(int idx); +void close_session(int sid); +void cesaTestCheckReady(const MV_CESA_RESULT *r); +void cesaCheckReady(MV_CESA_RESULT *r); +void printTestResults(int idx, MV_STATUS status, int checkMode); +void cesaLastResult(void); +void cesaTestPrintReq(int req, int offset, int size); + +void cesaTestPrintStatus(void); +void cesaTestPrintSession(int idx); +void sizeTest(int testIdx, int iter, int checkMode); +void multiTest(int iter, int reqSize, int checkMode); +void oneTest(int testIdx, int caseIdx, int iter, int reqSize, int checkMode); +void multiSizeTest(int idx, int iter, int checkMode, char *inputData); +void cesaTest(int iter, int reqSize, int checkMode); +void cesaOneTest(int testIdx, int caseIdx, int iter, int reqSize, int checkMode); +void combiTest(int iter, int reqSize, int checkMode); +void shaTest(int iter, int reqSize, int checkMode); +void mdTest(int iter, int reqSize, int checkMode); +void aesTest(int iter, int reqSize, int checkMode); +void tripleDesTest(int iter, int reqSize, int checkMode); +void desTest(int iter, int reqSize, int checkMode); +void cesaTestStop(void); +MV_STATUS testRun(int idx, int caseIdx, int iter, int reqSize, int checkMode); +void cesaTestStart(int bufNum, int bufSize); + +static MV_U32 getRate(MV_U32 *remainder) +{ + MV_U32 kBits, milliSec, rate; + + milliSec = 0; + if ((cesaEndTicks - cesaBeginTicks) > 0) + milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); + + if (milliSec == 0) { + if (remainder != NULL) + *remainder = 0; + return 0; + } + + kBits = (cesaIteration * cesaRateSize * 8) / 1000; + rate = kBits / milliSec; + if (remainder != NULL) + *remainder = ((kBits % milliSec) * 10) / milliSec; + + return rate; +} + +static char *extractMbuf(MV_CESA_MBUF *pMbuf, int offset, int size, char *hexStr) +{ + mvCesaCopyFromMbuf((MV_U8 *)cesaBinBuffer, pMbuf, offset, size); + mvBinToHex((const MV_U8 *)cesaBinBuffer, hexStr, size); + + return hexStr; +} + +static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, const char *hexString, int offset, int checkSize) +{ + MV_BOOL isFailed = MV_FALSE; + MV_STATUS status; + int size = strlen(hexString) / 2; + int checkedSize = 0; +/* + mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", + pMbuf, offset, checkSize, pMbuf->mbufSize); +*/ + if (pMbuf->mbufSize < (checkSize + offset)) { + mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", checkSize, offset, pMbuf->mbufSize); + return MV_TRUE; + } + status = mvCesaCopyFromMbuf((MV_U8 *)cesaBinBuffer, pMbuf, offset, checkSize); + if (status != MV_OK) { + mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", + checkSize, pMbuf, cesaBinBuffer); + return MV_TRUE; + } +/* + mvDebugMemDump(cesaBinBuffer, size, 1); +*/ + mvHexToBin(hexString, (MV_U8 *)cesaExpBinBuffer, size); + + /* Compare buffers */ + while (checkSize > checkedSize) { + size = MV_MIN(size, (checkSize - checkedSize)); + if (memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) { + mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", + checkSize, size, checkedSize); + mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); + mvDebugMemDump(cesaExpBinBuffer, size, 1); + + isFailed = MV_TRUE; + break; + } + checkedSize += size; + } + + return isFailed; +} + +static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, const char *hexString, int offset, int reqSize) +{ + MV_STATUS status = MV_OK; + int copySize, size = strlen(hexString) / 2; + + mvHexToBin(hexString, (MV_U8 *)cesaBinBuffer, size); + + copySize = 0; + while (reqSize > copySize) { + size = MV_MIN(size, (reqSize - copySize)); + + status = mvCesaCopyToMbuf((MV_U8 *)cesaBinBuffer, pMbuf, offset + copySize, size); + if (status != MV_OK) { + mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", copySize, reqSize); + break; + } + copySize += size; + } + pMbuf->mbufSize = offset + copySize; + return status; +} + +static MV_CESA_TEST_SESSION *getTestSessionDb(int idx, int *pTestIdx) +{ + int testIdx, dbIdx = idx / 100; + + if (dbIdx > MAX_TEST_TYPE) { + mvOsPrintf("Wrong index %d - No such test type\n", idx); + return NULL; + } + testIdx = idx % 100; + + if (testIdx >= cesaTestsDB[dbIdx].numSessions) { + mvOsPrintf("Wrong index %d - No such test\n", idx); + return NULL; + } + if (pTestIdx != NULL) + *pTestIdx = testIdx; + + return cesaTestsDB[dbIdx].pSessions; +} + +/* Debug */ +void cesaTestPrintReq(int req, int offset, int size) +{ + MV_CESA_MBUF *pMbuf; + + mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", req, offset, size); + mvDebugMemDump(cesaCmdRing, 128, 4); + + pMbuf = cesaCmdRing[req].pSrc; + mvCesaDebugMbuf("src", pMbuf, offset, size); + pMbuf = cesaCmdRing[req].pDst; + mvCesaDebugMbuf("dst", pMbuf, offset, size); + + cesaTestPrintStatus(); +} + +void cesaLastResult(void) +{ + mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", + (MV_U32) cesaResult.pReqPrv, cesaResult.sessionId, cesaResult.retCode); +} + +void printTestResults(int idx, MV_STATUS status, int checkMode) +{ + int testIdx; + MV_CESA_TEST_SESSION *pTestSessions = getTestSessionDb(idx, &testIdx); + + if (pTestSessions == NULL) + return; + + mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, cesaIteration, cesaReqSize); + if ((status == MV_OK) && (cesaCryptoError == 0) && (cesaError == 0) && (cesaReqIdError == 0)) { + mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", + cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); + } else { + mvOsPrintf("Failed, Status = 0x%x\n", status); + if (cesaCryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cesaCryptoError); + if (cesaReqIdError > 0) + mvOsPrintf("reqIdError : %d\n", cesaReqIdError); + if (cesaError > 0) + mvOsPrintf("cesaError : %d\n", cesaError); + } + if (cesaTestIsrMissCount > 0) + mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); +} + +void cesaCheckReady(MV_CESA_RESULT *r) +{ + int reqId; + MV_CESA_MBUF *pMbuf; + MV_BOOL isFailed; + + cesaResult = *r; + reqId = (int)cesaResult.pReqPrv; + pMbuf = cesaCmdRing[reqId].pDst; + +/* + mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaCheckOffset, cesaCheckSize); +*/ + /* Check expected reqId */ + if (reqId != cesaExpReqId) { + cesaReqIdError++; +/* + mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", + cesaCbIter, cesaIteration, reqId, cesaExpReqId); +*/ + } else { + if ((cesaCheckMode == CESA_FULL_CHECK_MODE) || (cesaCheckMode == CESA_FAST_CHECK_MODE)) { + if (cesaResult.retCode != MV_OK) { + cesaError++; + + mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", + cesaCbIter, cesaIteration, reqId, cesaResult.retCode); + } else { + if ((cesaCheckSize > 0) && (cesaOutputHexStr != NULL)) { + /* Check expected output */ + + isFailed = + cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); + if (isFailed) { + mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", + cesaCbIter, cesaIteration, reqId); + + CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); + + CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); + + CESA_TEST_DEBUG_CODE(mvCesaDebugMbuf + ("error", pMbuf, 0, + cesaCheckOffset + cesaCheckSize)); + + cesaCryptoError++; + } + } + } + } + } + if (cesaCheckMode == CESA_SHOW_CHECK_MODE) { + extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); + mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); + } + + cesaCbIter++; + if (cesaCbIter >= cesaIteration) { + cesaCbIter = 0; + cesaExpReqId = 0; + cesaIsReady = MV_TRUE; + + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + } else { + cesaExpReqId = reqId + 1; + if (cesaExpReqId == CESA_DEF_REQ_SIZE) + cesaExpReqId = 0; + } +} + +#ifdef MV_NETBSD +static int cesaTestReadyIsr(void *arg) +#else +#ifdef __KERNEL__ +static irqreturn_t cesaTestReadyIsr(int irq, void *dev_id) +#endif +#ifdef MV_VXWORKS +void cesaTestReadyIsr(void) +#endif +#endif +{ + MV_U32 cause; + MV_STATUS status; + MV_CESA_RESULT result; + + cesaTestIsrCount++; + /* Clear cause register */ + cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + if ((cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) { + mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); +#ifdef MV_NETBSD + return 0; +#else +#ifdef __KERNEL__ + return 1; +#else + return; +#endif +#endif + } + + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + + while (MV_TRUE) { + /* Get Ready requests */ + status = mvCesaReadyGet(&result); + if (status == MV_OK) + cesaCheckReady(&result); + + break; + } + if ((cesaTestFull == 1) && (status != MV_BUSY)) { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } +#ifdef __KERNEL__ + return 1; +#endif +} + +void cesaTestCheckReady(const MV_CESA_RESULT *r) +{ + MV_CESA_RESULT result = *r; + + cesaCheckReady(&result); + + if (cesaTestFull == 1) { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } +} + +static INLINE int open_session(MV_CESA_OPEN_SESSION *pOs) +{ + MV_U16 sid; + MV_STATUS status; + + status = mvCesaSessionOpen(pOs, (short *)&sid); + if (status != MV_OK) { + mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", status); + return -1; + } + + return (int)sid; +} + +void close_session(int sid) +{ + MV_STATUS status; + + status = mvCesaSessionClose(sid); + if (status != MV_OK) + mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", sid, status); + +} + +MV_STATUS testOpen(int idx) +{ + MV_CESA_OPEN_SESSION os; + int sid, i, testIdx; + MV_CESA_TEST_SESSION *pTestSession; + MV_U16 digestSize = 0; + + pTestSession = getTestSessionDb(idx, &testIdx); + if (pTestSession == NULL) { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if (pTestSession->sid != -1) { + mvOsPrintf("Session for test %d already created: sid=%d\n", idx, pTestSession->sid); + return MV_OK; + } + + os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; + os.macMode = pTestSession->macAlgorithm; + switch (os.macMode) { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + case MV_CESA_MAC_NULL: + digestSize = 0; + } + os.cryptoMode = pTestSession->cryptoMode; + os.direction = pTestSession->direction; + os.operation = pTestSession->operation; + + for (i = 0; i < pTestSession->cryptoKeySize; i++) + os.cryptoKey[i] = pTestSession->pCryptoKey[i]; + + os.cryptoKeyLength = pTestSession->cryptoKeySize; + + for (i = 0; i < pTestSession->macKeySize; i++) + os.macKey[i] = pTestSession->pMacKey[i]; + + os.macKeyLength = pTestSession->macKeySize; + os.digestSize = digestSize; + + sid = open_session(&os); + if (sid == -1) { + mvOsPrintf("Can't open session for test %d: rc=0x%x\n", idx, cesaResult.retCode); + return cesaResult.retCode; + } + CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); + pTestSession->sid = sid; + return MV_OK; +} + +MV_STATUS testClose(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION *pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if (pTestSession == NULL) { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if (pTestSession->sid == -1) { + mvOsPrintf("Test session %d is not opened\n", idx); + return MV_NO_SUCH; + } + + close_session(pTestSession->sid); + pTestSession->sid = -1; + + return MV_OK; +} + +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND *pCmd, + MV_CESA_TEST_SESSION *pTestSession, MV_U8 *pIV, int ivSize) +{ + int cmdReqId = 0; + int i; + MV_STATUS rc = MV_OK; + char ivZeroHex[] = "0000"; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + if (pCmd == NULL) { + mvOsPrintf("testCmd failed: pCmd=NULL\n"); + return MV_BAD_PARAM; + } + pCmd->sessionId = sid; + + cesaCryptoError = 0; + cesaReqIdError = 0; + cesaError = 0; + cesaTestIsrMissCount = 0; + cesaIsReady = MV_FALSE; + cesaIteration = iter; + + if (cesaInputHexStr == NULL) + cesaInputHexStr = cesaPlainHexEbc; + + for (i = 0; i < CESA_DEF_REQ_SIZE; i++) { + pCmd->pSrc = (MV_CESA_MBUF *) (cesaCmdRing[i].pSrc); + if (pIV != NULL) { + /* If IV from SA - set IV in Source buffer to zeros */ + cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, + (cesaReqSize - pCmd->cryptoOffset)); + } else { + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); + } + pCmd->pDst = (MV_CESA_MBUF *) (cesaCmdRing[i].pDst); + cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); + + memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); + } + + if (cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) { + MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + if (pTestSession->macAlgorithm == MV_CESA_MAC_MD5) { + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); + return MV_OK; + } + if (pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) { + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); + return MV_OK; + } + } + + cesaBeginTicks = CESA_TEST_TICK_GET(); + CESA_TEST_DEBUG_CODE(memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); cesaTestTraceIdx = 0;); + + if (cesaCheckMode == CESA_SW_NULL_CHECK_MODE) { + MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + for (i = 0; i < iter; i++) { + + if (pTestSession->macAlgorithm == MV_CESA_MAC_MD5) + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char *)pDigest); + + if (pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *) pDigest); + } + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + cesaIsReady = MV_TRUE; + + return MV_OK; + } + + /*cesaTestIsrCount = 0; */ + /*mvCesaDebugStatsClear(); */ + +#ifndef MV_NETBSD + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); +#endif + + for (i = 0; i < iter; i++) { + unsigned long flags; + + pCmd = &cesaCmdRing[cmdReqId]; + pCmd->pReqPrv = (void *)cmdReqId; + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + if (rc == MV_NO_RESOURCE) + cesaTestFull = 1; + + CESA_TEST_UNLOCK(flags); + + if (rc == MV_NO_RESOURCE) { + CESA_TEST_LOCK(flags); + CESA_TEST_WAIT((cesaTestFull == 0), 100); + CESA_TEST_UNLOCK(flags); + if (cesaTestFull == 1) { + mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", + i, iter, cesaTestFull); + cesaTestFull = 0; + return MV_TIMEOUT; + } + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + + CESA_TEST_UNLOCK(flags); + } + if ((rc != MV_OK) && (rc != MV_NO_MORE)) { + mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); + return rc; + } + + cmdReqId++; + if (cmdReqId >= CESA_DEF_REQ_SIZE) + cmdReqId = 0; + +#ifdef MV_LINUX + /* Reschedule each 16 requests */ + if ((i & 0xF) == 0) + schedule(); +#endif + } + return MV_OK; +} + +extern MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle); + +void cesaTestStart(int bufNum, int bufSize) +{ + int i, j, idx; + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + char *pBuf; +#ifndef MV_NETBSD + int numOfSessions, queueDepth; + MV_STATUS status; +#endif + + cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + if (cesaCmdRing == NULL) { + mvOsPrintf("testStart: Can't allocate %d bytes of memory\n", + (int)(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE)); + return; + } + memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + + if (bufNum == 0) + bufNum = CESA_DEF_BUF_NUM; + + if (bufSize == 0) + bufSize = CESA_DEF_BUF_SIZE; + + cesaBufNum = bufNum; + cesaBufSize = bufSize; + mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", bufNum, bufSize); + + cesaHexBuffer = mvOsMalloc(2 * bufNum * bufSize); + if (cesaHexBuffer == NULL) { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", 2 * bufNum * bufSize); + return; + } + memset(cesaHexBuffer, 0, (2 * bufNum * bufSize)); + + cesaBinBuffer = mvOsMalloc(bufNum * bufSize); + if (cesaBinBuffer == NULL) { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", bufNum * bufSize); + return; + } + memset(cesaBinBuffer, 0, (bufNum * bufSize)); + + cesaExpBinBuffer = mvOsMalloc(bufNum * bufSize); + if (cesaExpBinBuffer == NULL) { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", bufNum * bufSize); + return; + } + memset(cesaExpBinBuffer, 0, (bufNum * bufSize)); + + CESA_TEST_WAIT_INIT(); + + pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + if ((pMbufSrc == NULL) || (pFragsSrc == NULL) || (pMbufDst == NULL) || (pFragsDst == NULL)) { + mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); + /* !!!! Dima cesaTestCleanup(); */ + return; + } + + memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", + pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); + + idx = 0; + for (i = 0; i < CESA_DEF_REQ_SIZE; i++) { + pBuf = mvOsIoCachedMalloc(cesaTestOSHandle, bufSize * bufNum * 2, + &cesaReqBufs[i].bufPhysAddr, &cesaReqBufs[i].memHandle); + if (pBuf == NULL) { + mvOsPrintf("testStart: Can't malloc %d bytes for pBuf\n", bufSize * bufNum * 2); + return; + } + + memset(pBuf, 0, bufSize * bufNum * 2); + mvOsCacheFlush(cesaTestOSHandle, pBuf, bufSize * bufNum * 2); + if (pBuf == NULL) { + mvOsPrintf("cesaTestStart: Can't allocate %d bytes for req_%d buffers\n", + bufSize * bufNum * 2, i); + return; + } + + cesaReqBufs[i].bufVirtPtr = (MV_U8 *) pBuf; + cesaReqBufs[i].bufSize = bufSize * bufNum * 2; + + cesaCmdRing[i].pSrc = &pMbufSrc[i]; + cesaCmdRing[i].pSrc->pFrags = &pFragsSrc[idx]; + cesaCmdRing[i].pSrc->numFrags = bufNum; + cesaCmdRing[i].pSrc->mbufSize = 0; + + cesaCmdRing[i].pDst = &pMbufDst[i]; + cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; + cesaCmdRing[i].pDst->numFrags = bufNum; + cesaCmdRing[i].pDst->mbufSize = 0; + + for (j = 0; j < bufNum; j++) { + cesaCmdRing[i].pSrc->pFrags[j].bufVirtPtr = (MV_U8 *) pBuf; + cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8 *) pBuf; + cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + } + idx += bufNum; + } + +#ifndef MV_NETBSD + numOfSessions = CESA_DEF_SESSION_NUM; + queueDepth = CESA_DEF_REQ_SIZE; + + status = mvSysCesaInit(numOfSessions, queueDepth, NULL); + if (status != MV_OK) { + mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); + /* !!!! Dima cesaTestCleanup(); */ + return; + } +#endif /* !MV_NETBSD */ + + /* Prepare data for tests */ + for (i = 0; i < 50; i++) + strcat((char *)cesaDataHexStr3, "dd"); + + strcpy((char *)cesaDataAndMd5digest3, cesaDataHexStr3); + strcpy((char *)cesaDataAndSha1digest3, cesaDataHexStr3); + + /* Digest must be 8 byte aligned */ + for (; i < 56; i++) { + strcat((char *)cesaDataAndMd5digest3, "00"); + strcat((char *)cesaDataAndSha1digest3, "00"); + } + strcat((char *)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); + strcat((char *)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); + +#ifndef MV_NETBSD + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE(MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); +#endif + +#ifdef MV_VXWORKS + { + MV_STATUS status; + + status = intConnect((VOIDFUNCPTR *) INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); + if (status != OK) { + mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", INT_LVL_CESA, status); + /* !!!! Dima cesaTestCleanup(); */ + return; + } + cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); + if (cesaSemId == NULL) { + mvOsPrintf("cesaTestStart: Can't create semaphore\n"); + return; + } + intEnable(INT_LVL_CESA); + } +#endif /* MV_VXWORKS */ + +#if !defined(MV_NETBSD) && defined(__KERNEL__) + if (request_irq(CESA_IRQ, cesaTestReadyIsr, (IRQF_DISABLED), "cesa_test", NULL)) { + mvOsPrintf("cannot assign irq\n"); + /* !!!! Dima cesaTestCleanup(); */ + return; + } + spin_lock_init(&cesaLock); +#endif +} + +MV_STATUS testRun(int idx, int caseIdx, int iter, int reqSize, int checkMode) +{ + int testIdx, count, sid, digestSize; + int blockSize; + MV_CESA_TEST_SESSION *pTestSession; + MV_CESA_COMMAND cmd; + MV_STATUS status; + + memset(&cmd, 0, sizeof(cmd)); + + pTestSession = getTestSessionDb(idx, &testIdx); + if (pTestSession == NULL) { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + sid = pTestSession->sid; + if (sid == -1) { + mvOsPrintf("Test %d is not opened\n", idx); + return MV_BAD_STATE; + } + switch (pTestSession->cryptoAlgorithm) { + case MV_CESA_CRYPTO_DES: + case MV_CESA_CRYPTO_3DES: + blockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_AES: + blockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_NULL: + blockSize = 0; + break; + + default: + mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", pTestSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + switch (pTestSession->macAlgorithm) { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + default: + digestSize = 0; + } + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + if (pTestSession->direction == MV_CESA_DIR_ENCODE) { + cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; + } else { + cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; + } + + cmd.sessionId = sid; + if (checkMode == CESA_FAST_CHECK_MODE) { + cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; + cmd.macLength = cesaTestCases[caseIdx].macLength; + } else { + cmd.cryptoLength = reqSize; + cmd.macLength = reqSize; + } + cesaRateSize = cmd.cryptoLength; + cesaReqSize = cmd.cryptoLength; + cmd.cryptoOffset = 0; + if (pTestSession->operation != MV_CESA_MAC_ONLY) { + if ((pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || + (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR)) { + cmd.ivOffset = 0; + cmd.cryptoOffset = blockSize; + if (cesaTestCases[caseIdx].pCryptoIV == NULL) { + cmd.ivFromUser = 1; + } else { + cmd.ivFromUser = 0; + mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); + } + cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; + } + } + +/* + mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", + cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); +*/ + if (pTestSession->operation != MV_CESA_CRYPTO_ONLY) { + cmd.macOffset = cmd.cryptoOffset; + + if (cesaTestCases[caseIdx].digestOffset == -1) { + cmd.digestOffset = cmd.macOffset + cmd.macLength; + cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); + } else { + cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; + } + if ((cmd.digestOffset + digestSize) > cesaReqSize) + cesaReqSize = cmd.digestOffset + digestSize; + } + + cesaCheckMode = checkMode; + + if (checkMode == CESA_NULL_CHECK_MODE) { + cesaCheckSize = 0; + cesaCheckOffset = 0; + } else { + if (pTestSession->operation == MV_CESA_CRYPTO_ONLY) { + cesaCheckOffset = 0; + cesaCheckSize = cmd.cryptoLength; + } else { + cesaCheckSize = digestSize; + cesaCheckOffset = cmd.digestOffset; + } + } +/* + mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", + cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); + + mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", + blockSize, cmd.ivOffset, cmd.ivFromUser, + cmd.cryptoOffset, cmd.cryptoLength); + + mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", + cmd.macOffset, cmd.digestOffset, cmd.macLength); +*/ + status = testCmd(sid, iter, &cmd, pTestSession, cesaTestCases[caseIdx].pCryptoIV, blockSize); + + if (status != MV_OK) + return status; + + /* Wait when all callbacks is received */ + count = 0; + while (cesaIsReady == MV_FALSE) { + mvOsSleep(10); + count++; + if (count > 100) { + mvOsPrintf("testRun: Timeout occured\n"); + return MV_TIMEOUT; + } + } + + return MV_OK; +} + +void cesaTestStop(void) +{ + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + int i; + + /* Release all allocated memories */ + pMbufSrc = (MV_CESA_MBUF *) (cesaCmdRing[0].pSrc); + pFragsSrc = cesaCmdRing[0].pSrc->pFrags; + + pMbufDst = (MV_CESA_MBUF *) (cesaCmdRing[0].pDst); + pFragsDst = cesaCmdRing[0].pDst->pFrags; + + mvOsFree(pMbufSrc); + mvOsFree(pMbufDst); + mvOsFree(pFragsSrc); + mvOsFree(pFragsDst); + + for (i = 0; i < CESA_DEF_REQ_SIZE; i++) { + mvOsIoCachedFree(cesaTestOSHandle, cesaReqBufs[i].bufSize, + cesaReqBufs[i].bufPhysAddr, cesaReqBufs[i].bufVirtPtr, cesaReqBufs[i].memHandle); + } + cesaDataHexStr3[0] = '\0'; + + /* Free CESA HAL resources */ + mvCesaFinish(); +} + +void desTest(int iter, int reqSize, int checkMode) +{ + int mode, i; + MV_STATUS status; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + i = iter; + if (mode != CESA_NULL_CHECK_MODE) + i = 1; + + testOpen(0); + testOpen(1); + testOpen(2); + testOpen(3); + +/* DES / ECB mode / Encrypt only */ + status = testRun(0, 1, iter, reqSize, checkMode); + printTestResults(0, status, checkMode); + +/* DES / ECB mode / Decrypt only */ + status = testRun(1, 1, iter, reqSize, checkMode); + printTestResults(1, status, checkMode); + +/* DES / CBC mode / Encrypt only */ + status = testRun(2, 2, i, reqSize, mode); + printTestResults(2, status, mode); + +/* DES / CBC mode / Decrypt only */ + status = testRun(3, 2, iter, reqSize, mode); + printTestResults(3, status, mode); + + testClose(0); + testClose(1); + testClose(2); + testClose(3); +} + +void tripleDesTest(int iter, int reqSize, int checkMode) +{ + int mode, i; + MV_STATUS status; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + i = iter; + if (mode != CESA_NULL_CHECK_MODE) + i = 1; + + testOpen(100); + testOpen(101); + testOpen(102); + testOpen(103); + +/* 3DES / ECB mode / Encrypt only */ + status = testRun(100, 1, iter, reqSize, checkMode); + printTestResults(100, status, checkMode); + +/* 3DES / ECB mode / Decrypt only */ + status = testRun(101, 1, iter, reqSize, checkMode); + printTestResults(101, status, checkMode); + +/* 3DES / CBC mode / Encrypt only */ + status = testRun(102, 2, i, reqSize, mode); + printTestResults(102, status, mode); + +/* 3DES / CBC mode / Decrypt only */ + status = testRun(103, 2, iter, reqSize, mode); + printTestResults(103, status, mode); + + testClose(100); + testClose(101); + testClose(102); + testClose(103); +} + +void aesTest(int iter, int reqSize, int checkMode) +{ + MV_STATUS status; + int mode, i; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + + i = iter; + if (mode != CESA_NULL_CHECK_MODE) + i = 1; + + testOpen(200); + testOpen(201); + testOpen(202); + testOpen(203); + testOpen(204); + testOpen(205); + testOpen(206); + testOpen(207); + testOpen(208); + +/* AES-128 Encode ECB mode */ + status = testRun(200, 3, iter, reqSize, checkMode); + printTestResults(200, status, checkMode); + +/* AES-128 Decode ECB mode */ + status = testRun(201, 3, iter, reqSize, checkMode); + printTestResults(201, status, checkMode); + +/* AES-128 Encode CBC mode (IV from SA) */ + status = testRun(202, 10, i, reqSize, mode); + printTestResults(202, status, mode); + +/* AES-128 Encode CBC mode (IV from User) */ + status = testRun(202, 24, i, reqSize, mode); + printTestResults(202, status, mode); + +/* AES-128 Decode CBC mode */ + status = testRun(203, 24, iter, reqSize, mode); + printTestResults(203, status, checkMode); + +/* AES-192 Encode ECB mode */ + status = testRun(204, 4, iter, reqSize, checkMode); + printTestResults(204, status, checkMode); + +/* AES-192 Decode ECB mode */ + status = testRun(205, 4, iter, reqSize, checkMode); + printTestResults(205, status, checkMode); + +/* AES-256 Encode ECB mode */ + status = testRun(206, 5, iter, reqSize, checkMode); + printTestResults(206, status, checkMode); + +/* AES-256 Decode ECB mode */ + status = testRun(207, 5, iter, reqSize, checkMode); + printTestResults(207, status, checkMode); + +#if 0 +/* AES-128 Encode CTR mode */ + status = testRun(208, 23, iter, reqSize, mode); + printTestResults(208, status, checkMode); +#endif + + testClose(200); + testClose(201); + testClose(202); + testClose(203); + testClose(204); + testClose(205); + testClose(206); + testClose(207); + testClose(208); +} + +void mdTest(int iter, int reqSize, int checkMode) +{ + int mode; + MV_STATUS status; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + + testOpen(300); + testOpen(301); + testOpen(302); + testOpen(303); + testOpen(305); + +/* HMAC-MD5 Generate signature test */ + status = testRun(300, 6, iter, reqSize, mode); + printTestResults(300, status, checkMode); + +/* HMAC-MD5 Verify Signature test */ + status = testRun(301, 7, iter, reqSize, mode); + printTestResults(301, status, checkMode); + +/* HMAC-MD5 Generate signature test */ + status = testRun(302, 8, iter, reqSize, mode); + printTestResults(302, status, checkMode); + +/* HMAC-MD5 Verify Signature test */ + status = testRun(303, 9, iter, reqSize, mode); + printTestResults(303, status, checkMode); + +/* HASH-MD5 Generate signature test */ + status = testRun(305, 15, iter, reqSize, mode); + printTestResults(305, status, checkMode); + + testClose(300); + testClose(301); + testClose(302); + testClose(303); + testClose(305); +} + +void shaTest(int iter, int reqSize, int checkMode) +{ + int mode; + MV_STATUS status; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + + testOpen(400); + testOpen(401); + testOpen(402); + testOpen(403); + testOpen(405); + +/* HMAC-SHA1 Generate signature test */ + status = testRun(400, 11, iter, reqSize, mode); + printTestResults(400, status, checkMode); + +/* HMAC-SHA1 Verify Signature test */ + status = testRun(401, 12, iter, reqSize, mode); + printTestResults(401, status, checkMode); + +/* HMAC-SHA1 Generate signature test */ + status = testRun(402, 13, iter, reqSize, mode); + printTestResults(402, status, checkMode); + +/* HMAC-SHA1 Verify Signature test */ + status = testRun(403, 14, iter, reqSize, mode); + printTestResults(403, status, checkMode); + +/* HMAC-SHA1 Generate signature test */ + status = testRun(405, 16, iter, reqSize, mode); + printTestResults(405, status, checkMode); + + testClose(400); + testClose(401); + testClose(402); + testClose(403); + testClose(405); +} + +void combiTest(int iter, int reqSize, int checkMode) +{ + MV_STATUS status; + int mode, i; + + mode = checkMode; + if (checkMode == CESA_FULL_CHECK_MODE) + mode = CESA_FAST_CHECK_MODE; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + i = iter; + if (mode != CESA_NULL_CHECK_MODE) + i = 1; + + testOpen(500); + testOpen(501); + testOpen(502); + testOpen(503); + testOpen(504); + testOpen(505); + testOpen(506); + testOpen(507); + +/* DES ECB + MD5 encode test */ + status = testRun(500, 17, iter, reqSize, mode); + printTestResults(500, status, mode); + +/* DES ECB + SHA1 encode test */ + status = testRun(501, 18, iter, reqSize, mode); + printTestResults(501, status, mode); + +/* 3DES ECB + MD5 encode test */ + status = testRun(502, 17, iter, reqSize, mode); + printTestResults(502, status, mode); + +/* 3DES ECB + SHA1 encode test */ + status = testRun(503, 18, iter, reqSize, mode); + printTestResults(503, status, mode); + +/* 3DES CBC + MD5 encode test */ + status = testRun(504, 19, i, reqSize, mode); + printTestResults(504, status, mode); + +/* 3DES CBC + SHA1 encode test */ + status = testRun(505, 20, i, reqSize, mode); + printTestResults(505, status, mode); + +/* AES-128 CBC + MD5 encode test */ + status = testRun(506, 21, i, reqSize, mode); + printTestResults(506, status, mode); + +/* AES-128 CBC + SHA1 encode test */ + status = testRun(507, 22, i, reqSize, mode); + printTestResults(507, status, mode); + + testClose(500); + testClose(501); + testClose(502); + testClose(503); + testClose(504); + testClose(505); + testClose(506); + testClose(507); +} + +void cesaOneTest(int testIdx, int caseIdx, int iter, int reqSize, int checkMode) +{ + MV_STATUS status; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + mvOsPrintf("test=%d, case=%d, size=%d, iter=%d\n", testIdx, caseIdx, reqSize, iter); + + status = testOpen(testIdx); + + status = testRun(testIdx, caseIdx, iter, reqSize, checkMode); + printTestResults(testIdx, status, checkMode); + status = testClose(testIdx); + +} + +void cesaTest(int iter, int reqSize, int checkMode) +{ + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + mvOsPrintf("%d iteration\n", iter); + mvOsPrintf("%d size\n\n", reqSize); + +/* DES tests */ + desTest(iter, reqSize, checkMode); + +/* 3DES tests */ + tripleDesTest(iter, reqSize, checkMode); + +/* AES tests */ + aesTest(iter, reqSize, checkMode); + +/* MD5 tests */ + mdTest(iter, reqSize, checkMode); + +/* SHA-1 tests */ + shaTest(iter, reqSize, checkMode); +} + +void multiSizeTest(int idx, int iter, int checkMode, char *inputData) +{ + MV_STATUS status; + int i; + MV_CESA_SIZE_TEST *pMultiTest; + + if (testOpen(idx) != MV_OK) + return; + + if (iter == 0) + iter = CESA_DEF_ITER_NUM; + + if (checkMode == CESA_SHOW_CHECK_MODE) + iter = 1; + else + checkMode = CESA_FULL_CHECK_MODE; + + cesaTestCases[0].plainHexStr = inputData; + cesaTestCases[0].pCryptoIV = NULL; + + switch (idx) { + case 302: + pMultiTest = mdMultiSizeTest302; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = cesaDataHexStr3; + break; + + case 304: + pMultiTest = mdMultiSizeTest304; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 305: + pMultiTest = mdMultiSizeTest305; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 402: + pMultiTest = shaMultiSizeTest402; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 404: + pMultiTest = shaMultiSizeTest404; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 405: + pMultiTest = shaMultiSizeTest405; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 502: + pMultiTest = tripleDesMdMultiSizeTest502; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 503: + pMultiTest = tripleDesShaMultiSizeTest503; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 504: + iter = 1; + pMultiTest = cbc3desMdMultiSizeTest504; + cesaTestCases[0].pCryptoIV = iv1; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 505: + iter = 1; + pMultiTest = cbc3desShaMultiSizeTest505; + cesaTestCases[0].pCryptoIV = iv1; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 506: + iter = 1; + pMultiTest = cbcAes128md5multiSizeTest506; + cesaTestCases[0].pCryptoIV = iv5; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + case 507: + iter = 1; + pMultiTest = cbcAes128sha1multiSizeTest507; + cesaTestCases[0].pCryptoIV = iv5; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + break; + + default: + iter = 1; + checkMode = CESA_SHOW_CHECK_MODE; + pMultiTest = mdMultiSizeTest302; + if (inputData == NULL) + cesaTestCases[0].plainHexStr = hashHexStr80; + } + i = 0; + while (pMultiTest[i].outputHexStr != NULL) { + cesaTestCases[0].cipherHexStr = (char *)pMultiTest[i].outputHexStr; + status = testRun(idx, 0, iter, pMultiTest[i].size, checkMode); + if (checkMode != CESA_SHOW_CHECK_MODE) { + cesaReqSize = pMultiTest[i].size; + printTestResults(idx, status, checkMode); + } + if (status != MV_OK) + break; + i++; + } + testClose(idx); +/* + mvCesaDebugStatus(); + cesaTestPrintStatus(); +*/ +} + +void open_session_test(int idx, int caseIdx, int iter) +{ + int reqIdError, cryptoError, openErrors, i; + int openErrDisp[100]; + MV_STATUS status; + + memset(openErrDisp, 0, sizeof(openErrDisp)); + openErrors = 0; + reqIdError = 0; + cryptoError = 0; + for (i = 0; i < iter; i++) { + status = testOpen(idx); + if (status != MV_OK) { + openErrors++; + openErrDisp[status]++; + } else { + testRun(idx, caseIdx, 1, 0, CESA_FAST_CHECK_MODE); + if (cesaCryptoError > 0) + cryptoError++; + if (cesaReqIdError > 0) + reqIdError++; + + testClose(idx); + } + } + if (cryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cryptoError); + if (reqIdError > 0) + mvOsPrintf("reqIdError : %d\n", reqIdError); + + if (openErrors > 0) { + mvOsPrintf("Open Errors = %d\n", openErrors); + for (i = 0; i < 100; i++) { + if (openErrDisp[i] != 0) + mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); + } + } +} + +void loopback_test(int idx, int iter, int size, char *pPlainData) +{ +} + +#if defined(MV_VXWORKS) +int testMode = 0; +unsigned __TASKCONV cesaTask(void *args) +{ + int reqSize = cesaReqSize; + + if (testMode == 0) { + cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, reqSize, cesaCheckMode); + } else { + if (testMode == 1) { + cesaTest(cesaIteration, reqSize, cesaCheckMode); + combiTest(cesaIteration, reqSize, cesaCheckMode); + } else { + multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); + } + } + return 0; +} + +void oneTest(int testIdx, int caseIdx, int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaReqSize = cesaRateSize = reqSize; + cesaCheckMode = checkMode; + testMode = 0; + cesaTestIdx = testIdx; + cesaCaseIdx = caseIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4 * 1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %d\n", (int)rc); +} + +void multiTest(int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + cesaReqSize = reqSize; + testMode = 1; + rc = mvOsTaskCreate("CESA_T", 100, 4 * 1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %d\n", (int)rc); +} + +void sizeTest(int testIdx, int iter, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + testMode = 2; + cesaIdx = testIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4 * 1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + mvOsPrintf("hMW: Can't create CESA test task, rc = %d\n", (int)rc); +} + +#endif /* MV_VXWORKS */ + +extern void mvCesaDebugSA(short sid, int mode); +void cesaTestPrintSession(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION *pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if (pTestSession == NULL) { + mvOsPrintf("Test %d is not exist\n", idx); + return; + } + pTestSession = &pTestSession[testIdx]; + + if (pTestSession->sid == -1) { + mvOsPrintf("Test session %d is not opened\n", idx); + return; + } + + mvCesaDebugSA(pTestSession->sid, 1); +} + +void cesaTestPrintStatus(void) +{ + mvOsPrintf("\n\t Cesa Test Status\n\n"); + + mvOsPrintf("isrCount=%d\n", cesaTestIsrCount); + +#ifdef CESA_TEST_DEBUG + { + int i, j; + j = cesaTestTraceIdx; + mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); + for (i = 0; i < MV_CESA_TEST_TRACE_SIZE; i++) { + mvOsPrintf + ("%02d. %d 0x%04x 0x%04x 0x%04x 0x%02x 0x%02x %02d 0x%06x %p %p %p\n", j, + cesaTestTrace[j].type, cesaTestTrace[j].cause, cesaTestTrace[j].realCause, + cesaTestTrace[j].dmaCause, cesaTestTrace[j].resources, cesaTestTrace[j].timeStamp, + cesaTestTrace[j].pReqReady, cesaTestTrace[j].pReqProcess, cesaTestTrace[j].pReqEmpty); + j++; + if (j == MV_CESA_TEST_TRACE_SIZE) + j = 0; + } + } +#endif /* CESA_TEST_DEBUG */ +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/cesa/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvCompVer.txt 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvLru.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvLru.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvLru.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvLru.c 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,150 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvLru.h" +/* LRU Cache support */ + +/* Init LRU cache database */ +MV_LRU_CACHE *mvLruCacheInit(int numOfEntries) +{ + int i; + MV_LRU_CACHE *pLruCache; + + pLruCache = mvOsMalloc(sizeof(MV_LRU_CACHE)); + + if (pLruCache == NULL) + return NULL; + + memset(pLruCache, 0, sizeof(MV_LRU_CACHE)); + + pLruCache->table = mvOsMalloc(numOfEntries * sizeof(MV_LRU_ENTRY)); + if (pLruCache->table == NULL) { + mvOsFree(pLruCache); + return NULL; + } + memset(pLruCache->table, 0, numOfEntries * sizeof(MV_LRU_ENTRY)); + pLruCache->tableSize = numOfEntries; + + for (i = 0; i < numOfEntries; i++) { + pLruCache->table[i].next = i + 1; + pLruCache->table[i].prev = i - 1; + } + pLruCache->least = 0; + pLruCache->most = numOfEntries - 1; + + return pLruCache; +} + +void mvLruCacheFinish(MV_LRU_CACHE *pLruCache) +{ + mvOsFree(pLruCache->table); + mvOsFree(pLruCache); +} + +/* Update LRU cache database after using cache Index */ +void mvLruCacheIdxUpdate(MV_LRU_CACHE *pLruHndl, int cacheIdx) +{ + int prev, next; + + if (cacheIdx == pLruHndl->most) + return; + + next = pLruHndl->table[cacheIdx].next; + if (cacheIdx == pLruHndl->least) { + pLruHndl->least = next; + } else { + prev = pLruHndl->table[cacheIdx].prev; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + + pLruHndl->table[pLruHndl->most].next = cacheIdx; + pLruHndl->table[cacheIdx].prev = pLruHndl->most; + pLruHndl->most = cacheIdx; +} + +/* Delete LRU cache entry */ +void mvLruCacheIdxDelete(MV_LRU_CACHE *pLruHndl, int cacheIdx) +{ + int prev, next; + + if (cacheIdx == pLruHndl->least) + return; + + prev = pLruHndl->table[cacheIdx].prev; + if (cacheIdx == pLruHndl->most) { + pLruHndl->most = prev; + } else { + next = pLruHndl->table[cacheIdx].next; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + pLruHndl->table[pLruHndl->least].prev = cacheIdx; + pLruHndl->table[cacheIdx].next = pLruHndl->least; + pLruHndl->least = cacheIdx; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvLru.h u-boot-2009.08/board/marvell/mv_hal/cesa/mvLru.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvLru.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvLru.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,113 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvLru.h - Header File for Least Recently Used Cache algorithm +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Least Recently Used Cache algorithm. +* +*******************************************************************************/ + +#ifndef __mvLru_h__ +#define __mvLru_h__ + +#ifdef __cplusplus +extern "C" { +#endif + + typedef struct { + int next; + int prev; + } MV_LRU_ENTRY; + + typedef struct { + int least; + int most; + MV_LRU_ENTRY *table; + int tableSize; + } MV_LRU_CACHE; + +/* Find Cache index for replacement LRU */ + static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE * pLruHndl) + { + return pLruHndl->least; + } +/* Init LRU cache module */ + MV_LRU_CACHE *mvLruCacheInit(int numOfEntries); + +/* Finish LRU cache module */ + void mvLruCacheFinish(MV_LRU_CACHE *pLruHndl); + +/* Update LRU cache database after using cache Index */ + void mvLruCacheIdxUpdate(MV_LRU_CACHE *pLruHndl, int cacheIdx); + +/* Delete LRU cache entry */ + void mvLruCacheIdxDelete(MV_LRU_CACHE *pLruHndl, int cacheIdx); + +#ifdef __cplusplus +} +#endif + +#endif /* __mvLru_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvMD5.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvMD5.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvMD5.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvMD5.c 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,339 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvMD5.h" + +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); + +#ifdef MV_CPU_LE +#define mvByteReverse(buf, len) /* Nothing */ +#else +static void mvByteReverse(unsigned char *buf, unsigned longs); + +/* + * Note: this code is harmless on little-endian machines. + */ +static void mvByteReverse(unsigned char *buf, unsigned longs) +{ + MV_U32 t; + + do { + t = (MV_U32) ((unsigned)buf[3] << 8 | buf[2]) << 16 | ((unsigned)buf[1] << 8 | buf[0]); + *(MV_U32 *)buf = t; + buf += 4; + } while (--longs); +} +#endif + +/* + * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious + * initialization constants. + */ +void mvMD5Init(MV_MD5_CONTEXT *ctx) +{ + ctx->buf[0] = 0x67452301; + ctx->buf[1] = 0xefcdab89; + ctx->buf[2] = 0x98badcfe; + ctx->buf[3] = 0x10325476; + + ctx->bits[0] = 0; + ctx->bits[1] = 0; +} + +/* + * Update context to reflect the concatenation of another buffer full + * of bytes. + */ +void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) +{ + MV_U32 t; + + /* Update bitcount */ + + t = ctx->bits[0]; + ctx->bits[0] = t + ((MV_U32)len << 3); + if (ctx->bits[0] < t) + ctx->bits[1]++; /* Carry from low to high */ + ctx->bits[1] += len >> 29; + + t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ + + /* Handle any leading odd-sized chunks */ + + if (t) { + unsigned char *p = (unsigned char *)ctx->in + t; + + t = 64 - t; + if (len < t) { + memcpy(p, buf, len); + return; + } + memcpy(p, buf, t); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *)ctx->in); + buf += t; + len -= t; + } + /* Process data in 64-byte chunks */ + + while (len >= 64) { + memcpy(ctx->in, buf, 64); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *)ctx->in); + buf += 64; + len -= 64; + } + + /* Handle any remaining bytes of data. */ + + memcpy(ctx->in, buf, len); +} + +/* + * Final wrapup - pad to 64-byte boundary with the bit pattern + * 1 0* (64-bit count of bits processed, MSB-first) + */ +void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) +{ + unsigned count; + unsigned char *p; + + /* Compute number of bytes mod 64 */ + count = (ctx->bits[0] >> 3) & 0x3F; + + /* Set the first char of padding to 0x80. This is safe since there is + always at least one byte free */ + p = ctx->in + count; + *p++ = 0x80; + + /* Bytes of padding needed to make 64 bytes */ + count = 64 - 1 - count; + + /* Pad out to 56 mod 64 */ + if (count < 8) { + /* Two lots of padding: Pad the first block to 64 bytes */ + memset(p, 0, count); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *)ctx->in); + + /* Now fill the next block with 56 bytes */ + memset(ctx->in, 0, 56); + } else { + /* Pad block to 56 bytes */ + memset(p, 0, count - 8); + } + mvByteReverse(ctx->in, 14); + + /* Append length in bits and transform */ + ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; + ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; + + mvMD5Transform(ctx->buf, (MV_U32 *)ctx->in); + mvByteReverse((unsigned char *)ctx->buf, 4); + memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); + memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ +} + +/* The four core functions - F1 is optimized somewhat */ + +/* #define F1(x, y, z) (x & y | ~x & z) */ +#define F1(x, y, z) (z ^ (x & (y ^ z))) +#define F2(x, y, z) F1(z, x, y) +#define F3(x, y, z) (x ^ y ^ z) +#define F4(x, y, z) (y ^ (x | ~z)) + +/* This is the central step in the MD5 algorithm. */ +#define MD5STEP(f, w, x, y, z, data, s) \ + (w += f(x, y, z) + data, w = w<>(32-s), w += x) + +/* + * The core of the MD5 algorithm, this alters an existing MD5 hash to + * reflect the addition of 16 longwords of new data. MD5Update blocks + * the data and converts bytes into longwords for this routine. + */ +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) +{ + register MV_U32 a, b, c, d; + + a = buf[0]; + b = buf[1]; + c = buf[2]; + d = buf[3]; + + MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); + MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); + MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); + MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); + MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); + MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); + MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); + MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); + MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); + MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); + MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); + MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); + MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); + MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); + MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); + MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); + + MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); + MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); + MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); + MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); + MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); + MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); + MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); + MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); + MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); + MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); + MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); + MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); + MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); + MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); + MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); + MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); + + MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); + MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); + MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); + MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); + MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); + MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); + MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); + MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); + MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); + MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); + MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); + MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); + MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); + MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); + MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); + MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); + + MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); + MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); + MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); + MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); + MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); + MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); + MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); + MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); + MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); + MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); + MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); + MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); + MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); + MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); + MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); + MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +void mvMD5(unsigned char const *buf, unsigned len, unsigned char *digest) +{ + MV_MD5_CONTEXT ctx; + + mvMD5Init(&ctx); + mvMD5Update(&ctx, buf, len); + mvMD5Final(digest, &ctx); +} + +void mvHmacMd5(unsigned char const *text, int text_len, unsigned char const *key, int key_len, unsigned char *digest) +{ + int i; + MV_MD5_CONTEXT ctx; + unsigned char k_ipad[64 + 1]; /* inner padding - key XORd with ipad */ + unsigned char k_opad[64 + 1]; /* outer padding - key XORd with opad */ + + /* start out by storing key in pads */ + memset(k_ipad, 0, 64); + memcpy(k_ipad, key, key_len); + memset(k_opad, 0, 64); + memcpy(k_opad, key, key_len); + + /* XOR key with ipad and opad values */ + for (i = 0; i < 64; i++) { + k_ipad[i] ^= 0x36; + k_opad[i] ^= 0x5c; + } + + /* perform inner MD5 */ + mvMD5Init(&ctx); /* init ctx for 1st pass */ + mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ + mvMD5Update(&ctx, text, text_len); /* then text of datagram */ + mvMD5Final(digest, &ctx); /* finish up 1st pass */ + + /* perform outer MD5 */ + mvMD5Init(&ctx); /* init ctx for 2nd pass */ + mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ + mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ + mvMD5Final(digest, &ctx); /* finish up 2nd pass */ +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvMD5.h u-boot-2009.08/board/marvell/mv_hal/cesa/mvMD5.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvMD5.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvMD5.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,92 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvMD5_h__ +#define __mvMD5_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MV_MD5_MAC_LEN 16 + + typedef struct { + MV_U32 buf[4]; + MV_U32 bits[2]; + MV_U8 in[64]; + } MV_MD5_CONTEXT; + + void mvMD5Init(MV_MD5_CONTEXT *context); + void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, unsigned len); + void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); + + void mvMD5(unsigned char const *buf, unsigned len, unsigned char *digest); + + void mvHmacMd5(unsigned char const *text, int text_len, + unsigned char const *key, int key_len, unsigned char *digest); + +#ifdef __cplusplus +} +#endif +#endif /* __mvMD5_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvSHA1.c u-boot-2009.08/board/marvell/mv_hal/cesa/mvSHA1.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvSHA1.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvSHA1.c 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,288 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvSHA1.h" + +#define SHA1HANDSOFF + +typedef union { + MV_U8 c[64]; + MV_U32 l[16]; + +} CHAR64LONG16; + +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); + +#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) + +#ifdef MV_CPU_LE +#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ + (rol(block->l[i], 8) & 0x00FF00FF)) +#else +#define blk0(i) (block->l[i]) +#endif +#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ + block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) + +/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ +#define R0(v, w, x, y, z, i) \ + z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R1(v, w, x, y, z, i) \ + z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R2(v, w, x, y, z, i) \ + z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); +#define R3(v, w, x, y, z, i) \ + z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ + w = rol(w, 30); +#define R4(v, w, x, y, z, i) \ + z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ + w = rol(w, 30); + +/* Hash a single 512-bit block. This is the core of the algorithm. */ +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) +{ + MV_U32 a, b, c, d, e; + CHAR64LONG16 *block; + +#ifdef SHA1HANDSOFF + static MV_U32 workspace[16]; + + block = (CHAR64LONG16 *) workspace; + memcpy(block, buffer, 64); +#else + block = (CHAR64LONG16 *) buffer; +#endif + /* Copy context->state[] to working vars */ + a = state[0]; + b = state[1]; + c = state[2]; + d = state[3]; + e = state[4]; + /* 4 rounds of 20 operations each. Loop unrolled. */ + R0(a, b, c, d, e, 0); + R0(e, a, b, c, d, 1); + R0(d, e, a, b, c, 2); + R0(c, d, e, a, b, 3); + R0(b, c, d, e, a, 4); + R0(a, b, c, d, e, 5); + R0(e, a, b, c, d, 6); + R0(d, e, a, b, c, 7); + R0(c, d, e, a, b, 8); + R0(b, c, d, e, a, 9); + R0(a, b, c, d, e, 10); + R0(e, a, b, c, d, 11); + R0(d, e, a, b, c, 12); + R0(c, d, e, a, b, 13); + R0(b, c, d, e, a, 14); + R0(a, b, c, d, e, 15); + R1(e, a, b, c, d, 16); + R1(d, e, a, b, c, 17); + R1(c, d, e, a, b, 18); + R1(b, c, d, e, a, 19); + R2(a, b, c, d, e, 20); + R2(e, a, b, c, d, 21); + R2(d, e, a, b, c, 22); + R2(c, d, e, a, b, 23); + R2(b, c, d, e, a, 24); + R2(a, b, c, d, e, 25); + R2(e, a, b, c, d, 26); + R2(d, e, a, b, c, 27); + R2(c, d, e, a, b, 28); + R2(b, c, d, e, a, 29); + R2(a, b, c, d, e, 30); + R2(e, a, b, c, d, 31); + R2(d, e, a, b, c, 32); + R2(c, d, e, a, b, 33); + R2(b, c, d, e, a, 34); + R2(a, b, c, d, e, 35); + R2(e, a, b, c, d, 36); + R2(d, e, a, b, c, 37); + R2(c, d, e, a, b, 38); + R2(b, c, d, e, a, 39); + R3(a, b, c, d, e, 40); + R3(e, a, b, c, d, 41); + R3(d, e, a, b, c, 42); + R3(c, d, e, a, b, 43); + R3(b, c, d, e, a, 44); + R3(a, b, c, d, e, 45); + R3(e, a, b, c, d, 46); + R3(d, e, a, b, c, 47); + R3(c, d, e, a, b, 48); + R3(b, c, d, e, a, 49); + R3(a, b, c, d, e, 50); + R3(e, a, b, c, d, 51); + R3(d, e, a, b, c, 52); + R3(c, d, e, a, b, 53); + R3(b, c, d, e, a, 54); + R3(a, b, c, d, e, 55); + R3(e, a, b, c, d, 56); + R3(d, e, a, b, c, 57); + R3(c, d, e, a, b, 58); + R3(b, c, d, e, a, 59); + R4(a, b, c, d, e, 60); + R4(e, a, b, c, d, 61); + R4(d, e, a, b, c, 62); + R4(c, d, e, a, b, 63); + R4(b, c, d, e, a, 64); + R4(a, b, c, d, e, 65); + R4(e, a, b, c, d, 66); + R4(d, e, a, b, c, 67); + R4(c, d, e, a, b, 68); + R4(b, c, d, e, a, 69); + R4(a, b, c, d, e, 70); + R4(e, a, b, c, d, 71); + R4(d, e, a, b, c, 72); + R4(c, d, e, a, b, 73); + R4(b, c, d, e, a, 74); + R4(a, b, c, d, e, 75); + R4(e, a, b, c, d, 76); + R4(d, e, a, b, c, 77); + R4(c, d, e, a, b, 78); + R4(b, c, d, e, a, 79); + /* Add the working vars back into context.state[] */ + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + state[4] += e; + /* Wipe variables */ + a = b = c = d = e = 0; +} + +void mvSHA1Init(MV_SHA1_CTX *context) +{ + /* SHA1 initialization constants */ + context->state[0] = 0x67452301; + context->state[1] = 0xEFCDAB89; + context->state[2] = 0x98BADCFE; + context->state[3] = 0x10325476; + context->state[4] = 0xC3D2E1F0; + context->count[0] = context->count[1] = 0; +} + +/* Run your data through this. */ +void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, unsigned int len) +{ + MV_U32 i, j; + + j = (context->count[0] >> 3) & 63; + context->count[0] += len << 3; + if (context->count[0] < (len << 3)) + context->count[1]++; + context->count[1] += (len >> 29); + if ((j + len) > 63) { + memcpy(&context->buffer[j], data, (i = 64 - j)); + mvSHA1Transform(context->state, context->buffer); + for (; i + 63 < len; i += 64) + mvSHA1Transform(context->state, &data[i]); + j = 0; + } else { + i = 0; + } + memcpy(&context->buffer[j], &data[i], len - i); +} + +void mvSHA1Final(MV_U8 *digest, MV_SHA1_CTX *context) +{ + MV_U32 i; + MV_U8 finalcount[8]; + + for (i = 0; i < 8; i++) + finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> ((3 - (i & 3)) * 8)) & 255); + /* Endian independent */ + + mvSHA1Update(context, (const unsigned char *)"\200", 1); + while ((context->count[0] & 504) != 448) + mvSHA1Update(context, (const unsigned char *)"\0", 1); + + mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() + */ + for (i = 0; i < 20; i++) { + digest[i] = (unsigned char) + ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); + } + /* Wipe variables */ + i = 0; + memset(context->buffer, 0, 64); + memset(context->state, 0, 20); + memset(context->count, 0, 8); + memset(finalcount, 0, 8); + +#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ + mvSHA1Transform(context->state, context->buffer); +#endif +} + +void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8 *digest) +{ + MV_SHA1_CTX ctx; + + mvSHA1Init(&ctx); + mvSHA1Update(&ctx, buf, len); + mvSHA1Final(digest, &ctx); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvSHA1.h u-boot-2009.08/board/marvell/mv_hal/cesa/mvSHA1.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cesa/mvSHA1.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cesa/mvSHA1.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,89 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSHA1_h__ +#define __mvSHA1_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MV_SHA1_MAC_LEN 20 + + typedef struct { + MV_U32 state[5]; + MV_U32 count[2]; + MV_U8 buffer[64]; + } MV_SHA1_CTX; + + void mvSHA1Init(MV_SHA1_CTX *context); + void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); + void mvSHA1Final(MV_U8 *digest, MV_SHA1_CTX *context); + + void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8 *digest); + +#ifdef __cplusplus +} +#endif +#endif /* __mvSHA1_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmr.c u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmr.c --- u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmr.c 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,413 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysCntmrConfig.h" +#include "mvCntmrRegs.h" +#include "mvCntmr.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define CNTMR_EVENTS_STATUS_REG_GLOBAL (MV_CNTMR_REGS_OFFSET + 4) +#define TIMER_GLOBAL_BIT(timer) (1<<(timer*8-((timer==MAX_GLOBAL_TIMER)?1:0))) + +#define CNTMR_EVENTS_STATUS_REG_PRIVATE (MV_CPUIF_REGS_OFFSET(0) + 0x68) +#define TIMER_PRIVATE_BIT(timer) (1<<((timer-FIRST_PRIVATE_TIMER)*8+((timer==TIMER7)?8:0))) + + +/******************************************************************************* +* mvCntmrLoad - +* +* DESCRIPTION: +* Load an init Value to a given counter/timer +* +* INPUT: +* countNum - counter number +* value - value to be loaded +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) +{ + if (countNum >= MV_CNTMR_MAX_COUNTER) { + + mvOsPrintf(("mvCntmrLoad: Err. illegal counter number \n")); + return MV_BAD_PARAM;; + + } + + MV_REG_WRITE(CNTMR_RELOAD_REG(countNum), value); + MV_REG_WRITE(CNTMR_VAL_REG(countNum), value); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrRead - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter value +*******************************************************************************/ +MV_U32 mvCntmrRead(MV_U32 countNum) +{ + return MV_REG_READ(CNTMR_VAL_REG(countNum)); +} + +/******************************************************************************* +* mvCntmrWrite - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* countVal - value to write +* +* OUTPUT: +* None. +* +* RETURN: +* None +*******************************************************************************/ +void mvCntmrWrite(MV_U32 countNum, MV_U32 countVal) +{ + MV_REG_WRITE(CNTMR_VAL_REG(countNum), countVal); +} + +/******************************************************************************* +* mvCntmrCtrlSet - +* +* DESCRIPTION: +* Set the Control to a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrCtrlSet: Err. illegal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(countNum)); + + + if (pCtrl->enable) /* enable counter\timer */ + { + cntmrCtrl |= (CTCR_ARM_TIMER_EN(countNum)); + } + else /* disable counter\timer */ + { + cntmrCtrl &= ~(CTCR_ARM_TIMER_EN(countNum)); + } + + if ( pCtrl->autoEnable ) /* Auto mode */ + { + cntmrCtrl |= (CTCR_ARM_TIMER_AUTO_EN(countNum)); + + } + else /* no auto mode */ + { + cntmrCtrl &= ~(CTCR_ARM_TIMER_AUTO_EN(countNum)); + } + + MV_REG_WRITE(CNTMR_CTRL_REG(countNum),cntmrCtrl); + + return MV_OK; + +} + +/******************************************************************************* +* mvCntmrCtrlGet - +* +* DESCRIPTION: +* Get the Control value of a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* Counter\Timer control value +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + DB(mvOsPrintf(("mvCntmrCtrlGet: Err. illegal counter number \n"))); + return MV_BAD_PARAM;; + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(countNum)); + + /* enable counter\timer */ + if (cntmrCtrl & (CTCR_ARM_TIMER_EN(countNum))) + { + pCtrl->enable = MV_TRUE; + } + else + { + pCtrl->enable = MV_FALSE; + } + + /* counter mode */ + if (cntmrCtrl & (CTCR_ARM_TIMER_AUTO_EN(countNum))) + { + pCtrl->autoEnable = MV_TRUE; + } + else + { + pCtrl->autoEnable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrEnable - +* +* DESCRIPTION: +* Set the Enable-Bit to logic '1' ==> starting the counter +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrEnable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrEnable: Err. illegal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(countNum)); + + /* enable counter\timer */ + cntmrCtrl |= (CTCR_ARM_TIMER_EN(countNum)); + + + MV_REG_WRITE(CNTMR_CTRL_REG(countNum),cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrDisable - +* +* DESCRIPTION: +* Stop the counter/timer running, and returns its Value +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter\timer value +*******************************************************************************/ +MV_STATUS mvCntmrDisable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrDisable: Err. illegal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(countNum)); + + /* disable counter\timer */ + cntmrCtrl &= ~(CTCR_ARM_TIMER_EN(countNum)); + + MV_REG_WRITE(CNTMR_CTRL_REG(countNum),cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrStart - +* +* DESCRIPTION: +* Combined all the sub-operations above to one function: Load,setMode,Enable +* +* INPUT: +* countNum - counter number +* value - value of the counter\timer to be set +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, + MV_CNTMR_CTRL *pCtrl) +{ + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + mvOsPrintf(("mvCntmrDisable: Err. illegal counter number \n")); + return MV_BAD_PARAM;; + + } + + /* load value onto counter\timer */ + mvCntmrLoad(countNum, value); + + /* set control for timer \ cunter and enable */ + mvCntmrCtrlSet(countNum, pCtrl); + + return MV_OK; +} +/******************************************************************************* +* mvCntmrIntClear - Clear an Counter/Timer interrupt +* +* DESCRIPTION: +* This routine clears a specified Counter/Timer termination event in +* Counter/Timer cause register. +* The routine will preform argument validity check. +* +* INPUT: +* cntmrNum - Counter/Timer number. +* +* OUTPUT: +* None. +* +* RETURN: +* OK - If the bit was set +* ERROR - In case of invalid parameters. +* +*******************************************************************************/ +MV_STATUS mvCntmrIntClear(MV_U32 cntmrNum) +{ + if (INVALID_CNTMR(cntmrNum)) + return MV_ERROR; + + if (cntmrNum <= MAX_GLOBAL_TIMER) { + /* Reset cause bit to acknowledge interrupt */ + MV_REG_WRITE(CNTMR_EVENTS_STATUS_REG_GLOBAL, ~(TIMER_GLOBAL_BIT(cntmrNum))); + } else { + MV_REG_WRITE(CNTMR_EVENTS_STATUS_REG_PRIVATE, ~(TIMER_PRIVATE_BIT(cntmrNum))); + } + return MV_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmr.h u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmr.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmr.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmr.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,130 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrWtdgh +#define __INCmvTmrWtdgh + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes */ +#include "mvOs.h" +#include "cntmr/mvCntmrRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysCntmrConfig.h" + +/* This enumerator describe counters\watchdog numbers */ + typedef enum _mvCntmrID { + TIMER0 = 0, /* Global counter 0 */ + TIMER1, /* Global counter 1 */ + TIMER2, /* Global counter 2 */ + TIMER3, /* Global counter 3 */ + TIMER4, /* Global Watchdog 0*/ + TIMER5, /* CPU Timer 0 */ + TIMER6, /* CPU Timer 1 */ + TIMER7 /* CPU Watchdog */ + } MV_CNTMR_ID; +#define MAX_GLOBAL_TIMER TIMER4 +#define FIRST_PRIVATE_TIMER TIMER5 + +/* Counter / Timer control structure */ + typedef struct _mvCntmrCtrl { + MV_BOOL enable; /* enable */ + MV_BOOL autoEnable; /* counter/Timer */ + } MV_CNTMR_CTRL; + +/* Functions */ + +/* Load an init Value to a given counter/timer */ + MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); + +/* Returns the value of the given Counter/Timer */ + MV_U32 mvCntmrRead(MV_U32 countNum); + +/* Write a value of the given Counter/Timer */ + void mvCntmrWrite(MV_U32 countNum, MV_U32 countVal); + +/* Set the Control to a given counter/timer */ + MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Get the value of a given counter/timer */ + MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Set the Enable-Bit to logic '1' ==> starting the counter. */ + MV_STATUS mvCntmrEnable(MV_U32 countNum); + +/* Stop the counter/timer running, and returns its Value. */ + MV_STATUS mvCntmrDisable(MV_U32 countNum); + +/* Combined all the sub-operations above to one function: Load,setMode,Enable */ + MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, MV_CNTMR_CTRL *pCtrl); + +/* Clear an Counter/Timer interrupt (Ack) */ + MV_STATUS mvCntmrIntClear(MV_U32 cntmrNum); + +#ifdef __cplusplus +} +#endif +#endif /* __INCmvTmrWtdgh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmrRegs.h u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmrRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCntmrRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCntmrRegs.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,136 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrwtdgRegsh +#define __INCmvTmrwtdgRegsh + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvCntmr.h" +#include "mvSysCntmrConfig.h" + +/*******************************************/ +/* ARM Timers Registers Map */ +/*******************************************/ +/* + TIMER0 = Global counter 0 + TIMER1 = Global counter 1 + TIMER2 = Global counter 2 + TIMER3 = Global counter 3 + TIMER4 = Global Watchdog 0 + TIMER5 = CPU Timer 0 + TIMER6 = CPU Timer 1 + TIMER7 = CPU Watchdog +*/ +#define INVALID_CNTMR(cntmrNum) ((cntmrNum) >= MV_CNTMR_MAX_COUNTER) + +#define CNTMR_BASE(tmrNum) (tmrNum <=MAX_GLOBAL_TIMER)?(MV_CNTMR_REGS_OFFSET): (MV_CPUIF_REGS_OFFSET(0) + 0x40) + +#define CNTMR_RELOAD_REG(tmrNum) ((CNTMR_BASE(tmrNum))+0x10 + (((tmrNum <=MAX_GLOBAL_TIMER)?(tmrNum*8):((tmrNum-FIRST_PRIVATE_TIMER)*8)))) + +#define CNTMR_VAL_REG(tmrNum) ((CNTMR_BASE(tmrNum))+0x14 + (((tmrNum <=MAX_GLOBAL_TIMER)?(tmrNum*8):((tmrNum-FIRST_PRIVATE_TIMER)*8)))) + +/* #define CNTMR_CTRL_REG(tmrNum) (tmrNum <=MAX_GLOBAL_TIMER)?(MV_CNTMR_REGS_OFFSET): (MV_CPUIF_REGS_OFFSET(0) + 0x84) */ +#define CNTMR_CTRL_REG(tmrNum) CNTMR_BASE(tmrNum) + + +/* ARM Timers Registers Map */ +/*******************************************/ + + +/* ARM Timers Control Register */ +/* CPU_TIMERS_CTRL_REG (CTCR) */ + +#define CTCR_ARM_TIMER_EN_OFFS(timer) ((timer <=MAX_GLOBAL_TIMER)? (timer*2):((timer-FIRST_PRIVATE_TIMER)*2)) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(timer) ((timer <=MAX_GLOBAL_TIMER)? (1+(timer*2)):(1+(timer-FIRST_PRIVATE_TIMER)*2)) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + + +/* ARM Timer\Watchdog Reload Register */ +/* CNTMR_RELOAD_REG (TRR) */ + +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* ARM Timer\Watchdog Register */ +/* CNTMR_VAL_REG (TVRG) */ + +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff + +#ifdef __cplusplus +} +#endif + + +#endif /* __INCmvTmrwtdgRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/cntmr/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/cntmr/mvCompVer.txt 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/ddr2/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvCompVer.txt 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramCounters.h u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramCounters.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramCounters.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramCounters.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,268 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramCountersh +#define __INCmvDramCountersh + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" +#include "mvDramIfRegs.h" + +#define SDRAM_STAT_CNTRS_CTRL (MV_DDR_REGS_BASE + 0x1590) +#define SDRAM_STAT_CNTR_SELECT_OFFSET(c) ((c == 0) ? 0 : 8) +#define SDRAM_STAT_CNTR_SELECT_MASK(c) (0x1F << SDRAM_STAT_CNTR_SELECT_OFFSET(c)) +#define SDRAM_STAT_CNTR_RESET_OFFSET 16 +#define SDRAM_STAT_CNTR_RESET_MASK (0x1 << SDRAM_STAT_CNTR_RESET_OFFSET) +#define SDRAM_STAT_CNTR_START_OFFSET 17 +#define SDRAM_STAT_CNTR_START_MASK (0x1 << SDRAM_STAT_CNTR_START_OFFSET) + +#define SDRAM_STAT_CNTRS_VAL(set, idx) (MV_DDR_REGS_BASE + 0x1594 + (set << 3) + (idx << 2)) +#define SDRAM_STAT_HCLK_VAL(idx) (MV_DDR_REGS_BASE + 0x15A4 + (idx << 2)) + +typedef enum { + MBUSL_CACHE_READ = 0, + MBUSL_BURST_READ, + MBUSL_PAR_READ, + MBUSL_CACHE_WRITE, + MBUSL_BURST_WRITE, + MBUSL_UNSPEC_WRITE, + MBUSL_FULL_PAR_WRITE, + MBUSL_SEMI_PAR_WRITE, + MBUSL_TOTAL_READS, + MBUSL_TOTAL_WRITES, + MBUSL_TOTAL_TRANS, + MBUSL0_TOTAL_TRANS, + MBUSL1_TOTAL_TRANS, + MBUSL_LOOKUP_HIT, + MBUS_CACHE_READ, + MBUS_BURST_READ, + MBUS_PAR_READ, + MBUS_CACHE_WRITE, + MBUS_CACHE_WRITE_RMW, + MBUS_BURST_WRITE, + MBUS_BURST_WRITE_RMW, + MBUS_PAR_WRITE, + MBUS_PAR_WRITE_RMW, + MBUS_TOTAL_READS, + MBUS_TOTAL_WRITES, + MBUS_TOTAL_TRANS, + MBUS0_TOTAL_TRANS, + MBUS1_TOTAL_TRANS, + MBUS_BURST_CHOP, + NUM_BURSTS_128BIT, + DRAM_ACTIVE, + DRAM_PRECHARGE +} MV_DRAM_STAT_MODE; + +/******************************************************************************* +* mvDramStatStart +* +* DESCRIPTION: +* Start DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatStart(void) +{ + MV_REG_BIT_SET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_START_MASK); +} + +/******************************************************************************* +* mvDramStatStop +* +* DESCRIPTION: +* Stop DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatStop(void) +{ + MV_REG_BIT_RESET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_START_MASK); +} + +/******************************************************************************* +* mvDramStatClear +* +* DESCRIPTION: +* Clear the DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatClear(void) +{ + MV_U32 reg; + + MV_REG_BIT_SET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_RESET_MASK); + do { + reg = MV_REG_READ(SDRAM_STAT_CNTRS_CTRL); + } while (reg & SDRAM_STAT_CNTR_RESET_MASK); + + return; +} + +/******************************************************************************* +* mvDramStatConfig +* +* DESCRIPTION: +* Configure the DRAM statistics counters. +* +* INPUT: +* cntIdx - The counter index to configure. +* mode - The mode to configure the counter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_FAIL otherwise. +* +*******************************************************************************/ +static inline MV_STATUS mvDramStatConfig(MV_U8 cntIdx, MV_DRAM_STAT_MODE mode) +{ + MV_U32 reg; + + reg = MV_REG_READ(SDRAM_STAT_CNTRS_CTRL); + reg &= ~SDRAM_STAT_CNTR_SELECT_MASK(cntIdx); + reg |= (mode << SDRAM_STAT_CNTR_SELECT_OFFSET(cntIdx)); + MV_REG_WRITE(SDRAM_STAT_CNTRS_CTRL, reg); + + return MV_OK; +} + +/******************************************************************************* +* mvDramStatRead +* +* DESCRIPTION: +* Read the current DRAM statistics value. +* +* INPUT: +* None. +* +* OUTPUT: +* counter0 - Value of DRAM statistics counter #0. +* counter1 - Value of DRAM statistics counter #1. +* hclk - Value of HCLK counter. +* +* RETURN: +* MV_OK on success, +* MV_FAIL otherwise. +* +*******************************************************************************/ +static inline MV_STATUS mvDramStatRead(MV_U64 *counter0, MV_U64 *counter1, MV_U64 *hclk) +{ + MV_U32 val; + + if (counter0 != NULL) { + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(0, 0)); + *counter0 = val; + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(0, 1)); + *counter0 |= ((MV_U64) val << 32); + } + + if (counter1 != NULL) { + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(1, 0)); + *counter1 = val; + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(1, 1)); + *counter1 |= ((MV_U64) val << 32); + } + + if (hclk != NULL) { + val = MV_REG_READ(SDRAM_STAT_HCLK_VAL(0)); + *hclk = val; + val = MV_REG_READ(SDRAM_STAT_HCLK_VAL(1)); + *hclk |= ((MV_U64) val << 32); + } + + return MV_OK; +} + +#endif /* __INCmvDramCountersh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfBasicInit.S u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfBasicInit.S --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfBasicInit.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfBasicInit.S 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,1027 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAsm.h" +#include "mvCommon.h" + +/* defines */ +#if defined(MV_STATIC_DRAM_ON_BOARD) +/****************************************************************************** +* static definitions for several dimms +*******************************************************************************/ +#if defined(DB_MV78XX0) || defined(DB_MV88F632X) +#if defined(MV78100) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(MV78200) +/* 512MB per CD, 800Mhz cl5 */ +#define STATIC_DRAM_BANK_CS0 +#define STATIC_DRAM_BANK_CS2 + +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM1_BANK0_SIZE 0x1ffffff9 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x20000000 /* 0x1510 */ + + +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_DUNIT_CTRL_LOW 0x37543010 /* 0x1404 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ + +#define STATIC_SDRAM_ADDR_CTRL 0x00008888 /* 0x1410 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ + +#define STATIC_SDRAM_EXT_MODE 0x00000044 /* 0x1420 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FF7F /* 0x1424 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ + +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F40F /* 0x149c */ + +#endif + +#elif defined(RD_MV78XX0_AMC) +/* On board DDR2 512MB 400MHz CL5 */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM1_BANK0_SIZE 0x0FFFFFF1 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x10000000 /* 0x1510 */ + +#elif defined(RD_MV78XX0_H3C) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ + +#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_PCAC) +/* DDR2 boards 256MB 200MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#else +/* DDR2 MV88F6281 boards 256MB 400MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ +#endif /* MV78XX0 */ + +#endif /* MV_STATIC_DRAM_ON_BOARD */ + +.globl dramBoot1 +dramBoot1: + .word 0 +/************************************************************* +* basic timing init +**************************************************************/ + .globl _mvDramInitTiming +_mvDramInitTiming: + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) +#endif + + + /*DDR SDRAM Initialization Control */ + ldr r6, =DSICR_INIT_EN + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + and r6, r6, #DSICR_INIT_EN + cmp r6, #0 + bne 2b + mov pc, lr + + +#if defined(MV_STATIC_DRAM_ON_BOARD) +/************************************************************* +* basic init for static DRAM (on board dram no SPD) +**************************************************************/ + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + bl _mvDramInitTiming + + /* If we boot from NAND jump to DRAM address */ + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + +#ifdef STATIC_DRAM_BANK_CS2 + ldr r6, = STATIC_SDRAM1_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + ldr r6, = STATIC_SDRAM1_BANK0_BASE + MV_REG_WRITE_ASM(r6, r5, SDRAM_BASE_ADDR_REG (0,2)) +#endif + + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) +#ifndef MV_NAND_BOOT + ldr r6, = STATIC_DUNIT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) +#endif + + ldr sp,=0 + bl _mvDramIfConfig + ldr r0, =0 +#ifdef MV78XX0 + bl _mvDramIfEccMemInit +#ifdef STATIC_DRAM_BANK_CS2 + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + ldr r0, =0 +#endif +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define DIMM_TYPE_OFFSET 2 +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define DIMM_CONFIG_TYPE 11 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 +#define RANK_SIZE_OFFSET 31 + +#define DRAM_DEV_DENSITY_128M 128 +#define DRAM_DEV_DENSITY_256M 256 +#define DRAM_DEV_DENSITY_512M 512 +#define DRAM_DEV_DENSITY_1G 1024 +#define DRAM_DEV_DENSITY_2G 2048 + +#define DRAM_RANK_DENSITY_128M 0x20 +#define DRAM_RANK_DENSITY_256M 0x40 +#define DRAM_RANK_DENSITY_512M 0x80 +#define DRAM_RANK_DENSITY_1G 0x1 +#define DRAM_RANK_DENSITY_2G 0x2 + + .globl _mvDramIfBasicInit + .extern _i2cInit +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + bl _mvDramInitTiming + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM address */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + bl _i2cInit /* Initialize TWSI master */ + + /* Check if we have more then 1 dimm */ + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +#ifdef MV78XX0 + bl _is_Second_Dimm_Exist + beq single_dimm + ldr r6, =1 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +single_dimm: + bl _i2cInit /* Initialize TWSI master */ +#endif + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ +nonRegistered: +#if defined(MV78XX0) && !defined(MV632X) + /* Get ECC/non ECC info from DIMM */ + bl _is_Ecc + beq setConfigReg + +setEcc: + orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ +#endif +setConfigReg: + MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + +casDdr2: + ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x52 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x62 /* Assuming MAX CL = 6 */ + cmp r6, #6 /* If CL = 5 break */ + beq casDdr2Cont + + /* This is an error. return */ + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + + /* Get default SDRAM Mode values */ + MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) + bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ + orr r6, r6, r8 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) + + /* Set Dunit control register according to max CL detected */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + mov r7, r3 + +setDunitReg: +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + ble Clock333 + add r7, r7, #0x10 +Clock333: +#endif + + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + orr r6, r6, r7, LSL #20 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) + + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + /* Get bank 0 and 1 density */ + ldr r6, =0 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_bank_2_density + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_density: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne get_width + + /* Get bank 2 and 3 density */ + ldr r6, =2 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_width + + /* This is an error. return */ + b exit_ddrAutoConfig + + /* Get SDRAM width */ +get_width: + /* Get bank 0 and 1 width */ + ldr r6, =0 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq get_bank_2_width + + orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ + cmp r7, #16 + beq get_bank_2_width + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_width: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne densCont + + /* Get bank 2 and 3 width */ + ldr r6, =2 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq densCont + + orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ + cmp r7, #16 + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) + + /* Set SDRAM timing control low register */ + ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT + /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) + + /* Set SDRAM timing control high register */ + ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + blt timingHighClock333 + orr r6, r6, #BIT9 + +timingHighClock333: + /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne single_dimm_odt + + /* Set SDRAM ODT control low register for double DIMM*/ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register for double DIMM */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_267 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_300 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + beq fast_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_400 + cmp r4, r5 + beq fast_dram_clock_rtt + + b slow_dram_clock_rtt + +fast_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end +#endif +slow_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end + +single_dimm_odt: + /* Set SDRAM ODT control low register */ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + + /* Set SDRAM Extended Mode register */ + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + +odt_config_end: + /* SDRAM ODT control high register is left as default */ + MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) + + /*Read CL and set the DDR2 registers accordingly */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) + and r6, r6, #SDRAM_CL_MASK + mov r4, r6 + orr r4, r4, r6, LSL #4 + orr r4, r4, r6, LSL #8 + orr r4, r4, r6, LSL #12 + mov r5, #0x30000 + add r4, r4, r5 + sub r4, r4, #0x30 + /* Set SDRAM Ddr2 Timing Low register */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) + + /* Set SDRAM Ddr2 Timing High register */ + mov r4, r4, LSR #4 + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) + +timeParamDone: + /* Close all windows */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Set sdram bank 0 size and enable it */ + ldr r6, =0 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) + + /* Clear bank 2 size */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne defualt_order + + /* Set sdram bank 2 size */ + ldr r6, =2 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width2 + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width2: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) + + /* Close windows 1 and 3 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Check dimm size for setting dram bank order */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#SCSR_SIZE_MASK + and r4, r4,#SCSR_SIZE_MASK + cmp r6, r4 + bge defualt_order + + /* Bank 2 is biger then bank 0 */ + ldr r6,=0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) + + /* Open win 2 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 2 */ + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + mov PC, r11 /* r11 is saved link register */ + +defualt_order: + + /* Open win 0 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 0 */ + ldr r0, =0 + bl _mvDramIfEccMemInit +#endif +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + /* Get SDRAM width (SPD offset 13) */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ +#if defined(MV645xx) + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 + b exit +#endif +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +/**************************/ +/* Return value in flag if no-Ecc then Z-flag is set */ +_is_Ecc: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_CONFIG_TYPE + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 /* bit 1 -> Data ECC */ + mov PC, r13 + +/**************************/ +/* Return value in flag if no second DIMM then Z-flag is set */ +_is_Second_Dimm_Exist: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ + mov PC, r13 + +/******************************************************************************* +* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size +* +* DESCRIPTION: +* The function will read the bank 0 dram size(SPD version 1.0 and above ) +* +* INPUT: +* r6 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfGetDimmSizeFromSpd: + + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #RANK_SIZE_OFFSET /* offset 31 */ + bl _i2cRead + +pass_read: + ldr r8, =(0x7 << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_128M + beq endDimmSize + + ldr r8, =(0xf << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_256M + beq endDimmSize + + ldr r8, =(0x1f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_512M + beq endDimmSize + + ldr r8, =(0x3f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_1G + beq endDimmSize + + ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ +endDimmSize: + mov PC, r13 +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIf.c u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIf.c 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,1964 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" +#include "ddr2/mvDramIf.h" +#include "mvDramIfRegs.h" +/* #include "ctrlEnv/sys/mvCpuIf.h" */ +#include "ddr2/mvDramIfStaticInit.h" +#include "spd/mvSpd.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* DRAM bank presence encoding */ +#define BANK_PRESENT_CS0 0x1 +#define BANK_PRESENT_CS0_CS1 0x3 +#define BANK_PRESENT_CS0_CS2 0x5 +#define BANK_PRESENT_CS0_CS1_CS2 0x7 +#define BANK_PRESENT_CS0_CS2_CS3 0xd +#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf + +/* locals */ +#ifndef MV_STATIC_DRAM_ON_BOARD +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTmode); +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramModeRegCalc(MV_U32 minCas); +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1); +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk); +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl); +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk); +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas); +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas); +#endif +MV_32 DRAM_CS_Order[MV_DRAM_MAX_CS] = { N_A +#ifdef MV_INCLUDE_SDRAM_CS1 + , N_A +#endif +#ifdef MV_INCLUDE_SDRAM_CS2 + , N_A +#endif +#ifdef MV_INCLUDE_SDRAM_CS3 + , N_A +#endif +}; + +/* Get DRAM size of CS num */ +MV_U32 mvDramCsSizeGet(MV_U32 csNum) +{ + MV_DRAM_BANK_INFO bankInfo; + MV_U32 size, deviceW, dimmW; +#ifdef MV78XX0 + MV_U32 temp; +#endif + + if (MV_OK == mvDramBankInfoGet(csNum, &bankInfo)) { + if (0 == bankInfo.size) + return 0; + + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT) ? 32 : 64; +#else + deviceW = 16 /* KW family */ ; +#endif + dimmW = bankInfo.dataWidth - (bankInfo.dataWidth % 16); + size = ((bankInfo.size << 20) / (dimmW / deviceW)); + return size; + } else + return 0; +} + +/******************************************************************************* +* mvDramIfDetect - Prepare DRAM interface configuration values. +* +* DESCRIPTION: +* This function implements the full DRAM detection and timing +* configuration for best system performance. +* Since this routine runs from a ROM device (Boot Flash), its stack +* resides on RAM, that might be the system DRAM. Changing DRAM +* configuration values while keeping vital data in DRAM is risky. That +* is why the function does not preform the configuration setting but +* prepare those in predefined 32bit registers (in this case IDMA +* registers are used) for other routine to perform the settings. +* The function will call for board DRAM SPD information for each DRAM +* chip select. The function will then analyze those SPD parameters of +* all DRAM banks in order to decide on DRAM configuration compatible +* for all DRAM banks. +* The function will set the CPU DRAM address decode registers. +* Note: This routine prepares values that will overide configuration of +* mvDramBasicAsmInit(). +* +* INPUT: +* forcedCl - Forced CAL Latency. If equal to zero, do not force. +* eccDisable - Force down the ECC. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk) +{ +#ifndef MV_STATIC_DRAM_ON_BOARD + MV_32 MV_DRAM_CS_order[MV_DRAM_MAX_CS] = { + SDRAM_CS0 +#ifdef MV_INCLUDE_SDRAM_CS1 + , SDRAM_CS1 +#endif +#ifdef MV_INCLUDE_SDRAM_CS2 + , SDRAM_CS2 +#endif +#ifdef MV_INCLUDE_SDRAM_CS3 + , SDRAM_CS3 +#endif + }; +#endif + MV_U32 busClk; +#ifndef MV_STATIC_DRAM_ON_BOARD + MV_U32 deviceW, dimmW; + MV_U32 numOfAllDevices = 0; + MV_STATUS TTMode; + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + MV_U32 size, base = 0, i, j, temp, busClkPs; + MV_U8 minCas; + MV_DRAM_DEC_WIN dramDecWin; + dramDecWin.addrWin.baseHigh = 0; +#endif + + busClk = sysClk; + + if (0 == busClk) { + mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); + return MV_ERROR; + } +#ifndef MV_STATIC_DRAM_ON_BOARD + + busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + /* we will use bank 0 as the representative of the all the DRAM banks, */ + /* since bank 0 must exist. */ + for (i = 0; i < MV_DRAM_MAX_CS; i++) { + /* if Bank exist */ + if (MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) { + DB(mvOsPrintf("Dram: Find bank %d\n", i)); + /* check it isn't SDRAM */ + if (bankInfo[i].memoryType != MEM_TYPE_DDR2) { + mvOsOutput("Dram: ERR. SDRAM type not supported !!!\n"); + return MV_ERROR; + } + + /* All banks must support the Mclk freqency */ + if (bankInfo[i].minCycleTimeAtMaxCasLatPs > busClkPs) { + mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); + return MV_ERROR; + } + + /* All banks must support registry in order to activate it */ + if (bankInfo[i].registeredAddrAndControlInputs != bankInfo[0].registeredAddrAndControlInputs) { + mvOsOutput("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* All banks must support same ECC mode */ + if (bankInfo[i].errorCheckType != bankInfo[0].errorCheckType) { + mvOsOutput("Dram: ERR. different ECC settings !!!\n"); + return MV_ERROR; + } + } else { + /* bank 0 doesn't exist */ + if (i == 0) { + mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } else { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) { + MV_DRAM_CS_order[0] = SDRAM_CS2; + MV_DRAM_CS_order[1] = SDRAM_CS3; + MV_DRAM_CS_order[2] = SDRAM_CS0; + MV_DRAM_CS_order[3] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + } else +#endif + { + MV_DRAM_CS_order[0] = SDRAM_CS0; + MV_DRAM_CS_order[1] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + MV_DRAM_CS_order[2] = SDRAM_CS2; + MV_DRAM_CS_order[3] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + } + + for (j = 0; j < MV_DRAM_MAX_CS; j++) { + i = MV_DRAM_CS_order[j]; + + if (0 == bankInfo[i].size) + continue; + + /* Init the CPU window decode */ + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT) ? 32 : 64; +#else + deviceW = 16 /* KW family */ ; +#endif + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW / deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + + numOfAllDevices += bankInfo[i].numberOfDevices; + if (i == MV_DRAM_CS_order[0]) { + MV_U32 sizeToReg; + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + /* Size parameter validity check. */ + if (-1 == sizeToReg) { + mvOsOutput("DRAM: ctrlSizeToReg: ERR. Win %d size invalid.\n", i); + return MV_BAD_PARAM; + } + + DB(mvOsPrintf("Dram: Bank 0 Size - %x\n", sizeToReg); + ) + sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); + sizeToReg |= SCSR_WIN_EN; + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } else { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n", i, base, size)); + + /* Check if the DRAM size is more then 3GByte */ + if (base < 0xC0000000) { + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n", i, base, size)); + if (MV_OK != mvDramIfWinSet(i, &dramDecWin)) { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); + return MV_ERROR; + } + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); + if (0 == minCas) { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", (busClk / 1000000)); + + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsOutput("Set default CAS latency 4\n"); + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0], &bankInfo[2], busClk); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + + /* check if ECC is enabled by the user */ + if (eccDisable) { + /* turn off ECC */ + temp &= ~BIT18; + } + DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0], busClk); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + TTMode = MV_FALSE; + DB(mvOsPrintf("Dram: numOfAllDevices = %x\n", numOfAllDevices); + ) + if ((numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE)) { + if (((numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ)) || (numOfAllDevices > 18)) { + mvOsOutput("Enable 2T "); + TTMode = MV_TRUE; + } + } + + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode); + if (-1 == temp) { + mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ + temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); + if (-1 == temp) { + mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n", temp); + ) + /* check if ECC is enabled by the user */ + if (eccDisable) { + /* turn off sample stage if no ecc */ + temp &= ~SDRAM__D2P_EN;; + } + MV_REG_WRITE(DRAM_BUF_REG13, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0], &bankInfo[2]); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + sdramDDr2OdtConfig(bankInfo); + + /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ + temp = sdramDdr2TimeLoRegCalc(minCas); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG11, temp); + + /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ + temp = sdramDdr2TimeHiRegCalc(minCas); + if (-1 == temp) { + mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n", temp); + ) + MV_REG_WRITE(DRAM_BUF_REG12, temp); +#endif + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + MV_U32 result = 0xFFFFFFFF; + + if (mvDramIfWinGet(SDRAM_CS0 + bankNum, &addrDecWin) == MV_OK) { + if (addrDecWin.enable == MV_TRUE) + result = addrDecWin.addrWin.baseLow; + } + + DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", bankNum, result)); + return result; +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + MV_U32 result = 0; + + if (mvDramIfWinGet(SDRAM_CS0 + bankNum, &addrDecWin) == MV_OK) { + if (addrDecWin.enable == MV_TRUE) + result = addrDecWin.addrWin.size; + } + + DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", bankNum, result)); + return result; +} + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 size = 0, i; + + for (i = 0; i < MV_DRAM_MAX_CS; i++) + size += mvDramIfBankSizeGet(i); + + DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n", size)); + return size; +} + +/******************************************************************************* +* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. +* +* DESCRIPTION: +* The ECC single bit error threshold is the number of single bit +* errors to happen before the Dunit generates an interrupt. +* This function set single bit ECC threshold. +* +* INPUT: +* threshold - threshold. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) +{ + MV_U32 regVal; + + if (threshold > SECR_THRECC_MAX) + return MV_BAD_PARAM; + + regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); + regVal &= ~SECR_THRECC_MASK; + regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); + MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); + + return MV_OK; +} + +#ifndef MV_STATIC_DRAM_ON_BOARD +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ + +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + MV_U32 minCas0 = 0, minCas2 = 0; + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * + Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * + *********************************************************/ + + /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ + if (forcedCl) { + mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); + + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 50) + pBankInfo->suportedCasLatencies = 0x20; + else if (forcedCl == 60) + pBankInfo->suportedCasLatencies = 0x40; + else { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies, busClkPs)); + count = 1; + for (j = 7; j > 0; j--) { + if ((pBankInfo->suportedCasLatencies >> j) & BIT0) { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", pBankInfo->suportedCasLatencies)); + + count = 1; + DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo2->suportedCasLatencies, busClkPs)); + for (j = 7; j > 0; j--) { + if ((pBankInfo2->suportedCasLatencies >> j) & BIT0) { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) { + case 1: + if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", pBankInfo2->suportedCasLatencies)); + + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ + + for (j = startBit; j <= stopBit; j++) { + if ((pBankInfo->suportedCasLatencies >> j) & BIT0) { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n", (BIT0 << j))); + minCas0 = (BIT0 << j); + break; + } + } + + for (j = startBit; j <= stopBit; j++) { + if ((pBankInfo2->suportedCasLatencies >> j) & BIT0) { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n", (BIT0 << j))); + minCas2 = (BIT0 << j); + break; + } + } + + if (minCas2 > minCas0) + return minCas2; + else + return minCas0; + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if (refreshPeriod > SDRAM_REFRESH_MAX) { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if (pBankInfo->registeredAddrAndControlInputs) { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); + ) + } + + /* ECC and IERR support */ + sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ + sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ + + if (pBankInfo->errorCheckType) { + sdramConfig |= SDRAM_ECC_EN; + sdramConfig |= SDRAM_IERR_REPORTE; + DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); + } else { + sdramConfig |= SDRAM_ECC_DIS; + sdramConfig |= SDRAM_IERR_IGNORE; + DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); + } + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + DB(mvOsPrintf("DRAM CAS Latency ");) + + switch (minCas) { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + DB(mvOsPrintf("3.\n");) + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + DB(mvOsPrintf("4.\n");) + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + DB(mvOsPrintf("5.\n");) + break; + case DDR2_CL_6: + sdramMode |= SDRAM_DDR2_CL_6; + DB(mvOsPrintf("6.\n");) + break; + default: + mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + + DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode)); + + return sdramMode; +} + +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - DRAM frequency +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 populateBanks = 0; + int bankNum; + + /* Represent the populate banks in binary form */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) { + if (0 != pBankInfo[bankNum].size) + populateBanks |= (1 << bankNum); + } + + switch (populateBanks) { + case (BANK_PRESENT_CS0): + case (BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; + + case (BANK_PRESENT_CS0_CS2): + case (BANK_PRESENT_CS0_CS1_CS2): + case (BANK_PRESENT_CS0_CS2_CS3): + case (BANK_PRESENT_CS0_CS2_CS3_CS4): + if (busClk >= MV_BOARD_SYSCLK_267MHZ) + return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; + else + return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; + + default: + mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) +{ + MV_U32 dunitCtrlLow, cl; + MV_U32 sbOutR[4] = { 3, 5, 7, 9 }; + MV_U32 sbOutU[4] = { 1, 3, 5, 7 }; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* Clear StBurstOutDel field */ + dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; + + /* Clear StBurstInDel field */ + dunitCtrlLow &= ~SDRAM_SB_IN_MASK; + + /* Clear CtrlPos field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; + + /* Clear 2T field */ + dunitCtrlLow &= ~SDRAM_2T_MASK; + if (TTMode == MV_TRUE) + dunitCtrlLow |= SDRAM_2T_MODE; + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstInDel bits [27:24] */ + /* 200MHz - 267MHz None reg = CL + 1 */ + /* 200MHz - 267MHz reg = CL + 2 */ + /* > 267MHz None reg = CL + 2 */ + /* > 267MHz reg = CL + 3 */ + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstOutDel bits [23:20] */ + /********-********-********-********- + * CL=3 | CL=4 | CL=5 | CL=6 | + *********-********-********-********- + Not Reg. * 0001 | 0011 | 0101 | 0111 | + *********-********-********-********- + Registered * 0011 | 0101 | 0111 | 1001 | + *********-********-********-********/ + + /* Set Dunit Control low default value */ + dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; + + switch (minCas) { + case DDR2_CL_3: + cl = 3; + break; + case DDR2_CL_4: + cl = 4; + break; + case DDR2_CL_5: + cl = 5; + break; + case DDR2_CL_6: + cl = 6; + break; + default: + mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); + return -1; + } + + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= (sbOutR[cl - 3]) << SDRAM_SB_OUT_DEL_OFFS; + else + dunitCtrlLow |= (sbOutU[cl - 3]) << SDRAM_SB_OUT_DEL_OFFS; + + DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); + + if (busClk <= MV_BOARD_SYSCLK_267MHZ) { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 2; + else + cl = cl + 1; + } else { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 3; + else + cl = cl + 2; + } + + DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); + dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; + + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow)); + + return dunitCtrlLow; +} + +/******************************************************************************* +* dunitCtrlHighRegCalc - Calculate sdram dunit control high register +* +* DESCRIPTION: Calculate sdram dunit control high register optimized value based +* on the bus clock. +* +* INPUT: +* busClk - DRAM frequency. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control high reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 dunitCtrlHigh; + dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); + if (busClk > MV_BOARD_SYSCLK_300MHZ) + dunitCtrlHigh |= SDRAM__P2D_EN; + else + dunitCtrlHigh &= ~SDRAM__P2D_EN; + + if (busClk > MV_BOARD_SYSCLK_267MHZ) + dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); + + /* If ECC support we turn on D2P sample */ + dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ + if ((pBankInfo->errorCheckType) && (busClk > MV_BOARD_SYSCLK_267MHZ)) + dunitCtrlHigh |= SDRAM__D2P_EN; + + return dunitCtrlHigh; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) +{ + MV_U32 addrCtrl = 0; + + if (pBankInfoDIMM1->size) { + switch (pBankInfoDIMM1->sdramWidth) { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + } + + switch (pBankInfo->sdramWidth) { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); + break; + default: + mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", pBankInfo->deviceDensity); + return -1; + } + + if (pBankInfoDIMM1->size) { + switch (pBankInfoDIMM1->deviceDensity) { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); + break; + default: + mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfoDIMM1->deviceDensity); + return -1; + } + } + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + MV_U32 timeCtrlLow = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK) | + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | ((tRtp - 1) << SDRAM_TRTP_OFFS)); + + /* Check extended tRas bit */ + if ((tRas - 1) & BIT4) + timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); + + return timeCtrlLow; +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timingHigh; + MV_U32 timeNs = 0; + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Set DDR timing high register static configuration bits */ + timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); + + /* Set DDR timing high register default value */ + timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; + + /* Clear tRfc field */ + timingHigh &= ~SDRAM_TRFC_MASK; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) { + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", + pBankInfo[bankNum].minRefreshToActiveCmd)); + } + if (busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) + timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + + /* SDRAM timing high */ + DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); + + return timingHigh; +} + +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) { + if (0 != pBankInfo[bankNum].size) + populateBanks |= (1 << bankNum); + } + + switch (populateBanks) { + case (BANK_PRESENT_CS0): + case (BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; + break; + case (BANK_PRESENT_CS0_CS2): + case (BANK_PRESENT_CS0_CS1_CS2): + case (BANK_PRESENT_CS0_CS2_CS3): + case (BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; + break; + default: + DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); + return; + } + /* DDR2 SDRAM ODT ctrl low */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + + /* DDR2 SDRAM ODT ctrl high */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + + /* DDR2 DUNIT ODT ctrl */ + if (((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || (mvCtrlModelGet() == MV_78200_DEV_ID)) + dunitOdtCtrl &= ~(BIT9 | BIT8); /* Clear ODT always on */ + + DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} + +/******************************************************************************* +* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing low registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing low reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeLoReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); + ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | + SD2TLR_TODT_OFF_RD_MASK | SD2TLR_TODT_ON_CTRL_RD_MASK | SD2TLR_TODT_OFF_CTRL_RD_MASK); + + if (minCas == DDR2_CL_3) { + cl = 3; + } else if (minCas == DDR2_CL_4) { + cl = 4; + } else if (minCas == DDR2_CL_5) { + cl = 5; + } else if (minCas == DDR2_CL_6) { + cl = 6; + } else { + DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", minCas)); + cl = 4; + } + + ddr2TimeLoReg |= ((cl - 3) << SD2TLR_TODT_ON_RD_OFFS); + ddr2TimeLoReg |= (cl << SD2TLR_TODT_OFF_RD_OFFS); + ddr2TimeLoReg |= (cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); + ddr2TimeLoReg |= ((cl + 3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); + + /* DDR2 SDRAM timing low */ + DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); + + return ddr2TimeLoReg; +} + +/******************************************************************************* +* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing high registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing high reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeHiReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); + ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | + SD2THR_TODT_OFF_WR_MASK | SD2THR_TODT_ON_CTRL_WR_MASK | SD2THR_TODT_OFF_CTRL_WR_MASK); + + if (minCas == DDR2_CL_3) { + cl = 3; + } else if (minCas == DDR2_CL_4) { + cl = 4; + } else if (minCas == DDR2_CL_5) { + cl = 5; + } else if (minCas == DDR2_CL_6) { + cl = 6; + } else { + mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", minCas); + cl = 4; + } + + ddr2TimeHiReg |= ((cl - 3) << SD2THR_TODT_ON_WR_OFFS); + ddr2TimeHiReg |= (cl << SD2THR_TODT_OFF_WR_OFFS); + ddr2TimeHiReg |= (cl << SD2THR_TODT_ON_CTRL_WR_OFFS); + ddr2TimeHiReg |= ((cl + 3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); + + /* DDR2 SDRAM timin high */ + DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); + + return ddr2TimeHiReg; +} +#endif + +/******************************************************************************* +* mvDramIfCalGet - Get CAS Latency +* +* DESCRIPTION: +* This function get the CAS Latency. +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* CAS latency times 10 (to avoid using floating point). +* +*******************************************************************************/ +MV_U32 mvDramIfCalGet(void) +{ + MV_U32 sdramCasLat, casLatMask; + + casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); + + switch (casLatMask) { + case SDRAM_DDR2_CL_3: + sdramCasLat = 30; + break; + case SDRAM_DDR2_CL_4: + sdramCasLat = 40; + break; + case SDRAM_DDR2_CL_5: + sdramCasLat = 50; + break; + case SDRAM_DDR2_CL_6: + sdramCasLat = 60; + break; + default: + mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); + return -1; + } + + return sdramCasLat; +} + +/******************************************************************************* +* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - +* +* DESCRIPTION: +* add support in power management. +* +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvDramIfSelfRefreshSet() +{ + MV_U32 operReg; + + operReg = MV_REG_READ(SDRAM_OPERATION_REG); + MV_REG_WRITE(SDRAM_OPERATION_REG, operReg | SDRAM_CMD_SLF_RFRSH); + /* Read until register is reset to 0 */ + while (MV_REG_READ(SDRAM_OPERATION_REG)) + ; +} + +/******************************************************************************* +* mvDramIfDimGetSPDversion - return DIMM SPD version. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) +{ + MV_DIMM_INFO dimmInfo; + if (bankNum >= MV_DRAM_MAX_CS) { + DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); + return; + } + memset(&dimmInfo, 0, sizeof(dimmInfo)); + if (MV_OK != dimmSpdGet((MV_U32) (bankNum / 2), &dimmInfo)) { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return; + } + *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION] / 10; + *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION] % 10; +} + +/******************************************************************************* +* mvDramIfShow - Show DRAM controller information. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvDramIfShow(void) +{ + int i, sdramCasLat, sdramCsSize; + MV_U32 Major = 0, Minor = 0; + + mvOsOutput("DRAM Controller info:\n"); + + mvOsOutput("Total DRAM "); + mvSizePrint(mvDramIfSizeGet()); + mvOsOutput("\n"); + + for (i = 0; i < MV_DRAM_MAX_CS; i++) { + sdramCsSize = mvDramIfBankSizeGet(i); + if (sdramCsSize) { + if (0 == (i & 1)) { + mvDramIfDimGetSPDversion(&Major, &Minor, i); + mvOsOutput("DIMM %d version %d.%d\n", i / 2, Major, Minor); + } + mvOsOutput("\tDRAM CS[%d] ", i); + mvSizePrint(sdramCsSize); + mvOsOutput("\n"); + } + } + sdramCasLat = mvDramIfCalGet(); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) + mvOsOutput("ECC enabled, "); + else + mvOsOutput("ECC Disabled, "); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) + mvOsOutput("Registered DIMM\n"); + else + mvOsOutput("Non registered DIMM\n"); + + mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat / 10, sdramCasLat % 10); +} + +/******************************************************************************* +* mvDramIfGetFirstCS - find the DRAM bank on the lower address +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +*******************************************************************************/ +MV_U32 mvDramIfGetFirstCS(void) +{ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + + if (DRAM_CS_Order[0] == N_A) { + mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); +#ifdef MV_INCLUDE_SDRAM_CS2 + mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); +#endif + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) { + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + return SDRAM_CS2; + } +#endif + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + return SDRAM_CS0; + } + return DRAM_CS_Order[0]; +} + +/******************************************************************************* +* mvDramIfGetCSorder - +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* CS number. +* +* OUTPUT: +* CS order. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +* NOTE: mvDramIfGetFirstCS must be caled before this subroutine +*******************************************************************************/ +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder) +{ + return DRAM_CS_Order[csOrder]; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for (targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS; targetNum++) { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + continue; + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) { + mvOsPrintf("sdramIfWinOverlap: Required target %d overlap winNum %d\n", target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg = 0, sizeReg = 0; + MV_U32 sizeToReg = 0; + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d." + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register */ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0, target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0, target)); + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= (pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK); + + /* Translate the given window size to register format */ + sizeToReg = (pAddrDecWin->addrWin.size / SCSR_SIZE_ALIGNMENT) - 1; + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + sizeReg |= SCSR_WIN_EN; + else + sizeReg &= ~SCSR_WIN_EN; + + /* 3) Write to address decode Base Address Register. */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0, target), baseReg); + + /* Write to address decode Size Register. */ + MV_REG_WRITE(SDRAM_SIZE_REG(0, target), sizeReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg, sizeReg; + MV_U32 sizeRegVal; + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0, target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0, target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * SCSR_SIZE_ALIGNMENT; + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + if (sizeReg & SCSR_WIN_EN) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + if (enable == MV_TRUE) { + /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } else { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", target); + return MV_ERROR; + } + } else { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfConfig.h u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfConfig.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfConfig.h 2011-04-04 13:57:34.945596384 -0400 @@ -0,0 +1,155 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) + +#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ + (SDRAM_SRCLK_KEPT | \ + SDRAM_CLK1DRV_NORMAL | \ + (BIT28 | BIT29)) + +#define SDRAM_ADDR_CTRL_DV 2 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) + +/* Note: value of 0 in register means one cycle, 1 means two and so on */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ + ((0x0 << SDRAM_TR2R_OFFS) | \ + (0x0 << SDRAM_TR2W_W2R_OFFS) | \ + (0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 +#endif + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 +#endif + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) +/* DDR SDRAM Timing parameter default values */ +#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 +#define SDRAM_TRFC_DEFAULT_VALUE 0x34 +#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE +#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) + +#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) + +#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __INCmvDramIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfConfig.S u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfConfig.S --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfConfig.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfConfig.S 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,528 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCommon.h" +#include "mvSysXorConfig.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig +.text +.globl _mvDramIfMemInit + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4} +no_stack_s: + + /* Dunit FTDLL Configuration Register */ + /* 0) Write to SDRAM FTDLL coniguration register */ + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) + str r4, [r1] + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 2) Write Dunit control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] +#if defined(MV_STATIC_DRAM_ON_BOARD) + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) + str r4, [r1] +#endif + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Now its safe to write new value to SDRAM Extended Mode regist */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r4, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: +cmp sp, #0 + beq no_stack_l + mov r1, LR /* Save link register */ +#if defined(MV78XX0) + bl _mvDramIfMemInit +#endif + mov LR,r1 /* restore link register */ +load_from_stack: + /* Restore registers */ + ldmia sp!, {r1, r2, r3, r4} +no_stack_l: + + mov pc, lr + + +/******************************************************************************* +* _mvDramIfEccMemInit - Basic DRAM ECC initialization. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ +#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ +#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ +/* XOR engine register offsets macros */ +#define XOR_CONFIG_REG(chan) (MV_XOR_REGS_BASE(0) + 0x10 + ((chan) * 4)) +#define XOR_ACTIVATION_REG(chan) (MV_XOR_REGS_BASE(0) + 0x20 + ((chan) * 4)) +#define XOR_CAUSE_REG (MV_XOR_REGS_BASE(0) + 0x30) +#define XOR_ERROR_CAUSE_REG (MV_XOR_REGS_BASE(0) + 0x50) +#define XOR_ERROR_ADDR_REG (MV_XOR_REGS_BASE(0) + 0x60) +#define XOR_WINDOW_CTRL_REG(chan) (MV_XOR_REGS_BASE(0) + 0x240 + ((chan) * 4)) +#define XOR_BASE_ADDR_REG(winNum) (MV_XOR_REGS_BASE(0) + 0x250 + ((winNum) * 4)) +#define XOR_SIZE_MASK_REG(winNum) (MV_XOR_REGS_BASE(0) + 0x270 + ((winNum) * 4)) +#define XOR_INIT_VAL_LOW_REG (MV_XOR_REGS_BASE(0) + 0x2E0) +#define XOR_INIT_VAL_HIGH_REG (MV_XOR_REGS_BASE(0) + 0x2E4) +#define XOR_DST_PTR_REG(chan) (MV_XOR_REGS_BASE(0) + 0x2B0 + ((chan) * 4)) +#define XOR_BLOCK_SIZE_REG(chan) (MV_XOR_REGS_BASE(0) + 0x2C0 + ((chan) * 4)) + +.globl _mvDramIfEccMemInit +/******************************************************************************* +* _mvDramIfEccMemInit - mem init for dram cs +* +* DESCRIPTION: +* This function will clean the cs by ussing the XOR mem init. +* +* INPUT: +* r0 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfEccMemInit: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s1 +save_on_stack1: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} +no_stack_s1: + + ldr r1, = 0 + + /* Disable all XOR address decode windows to avoid possible overlap */ + MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_CHAN0))) + + /* Init r5 to first XOR_SIZE_MASK_REG */ + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_ADDR_DEC_WIN0)) + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + /* Update destination & size */ + MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) + HTOLL(r6,r5) + /* Init r6 to first XOR_BASE_ADDR_REG */ + ldr r4, = 0xf + ldr r5, = 0x1 + mov r5, r5, LSL r0 + bic r4, r4, r5 + mov r4, r4, LSL #8 + + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_ADDR_DEC_WIN0)) + + ldr r6, = 0xff0001 + MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_CHAN0)) + + /* Configure XOR engine for memory init function. */ + MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + and r6, r6, #~0x7 /* Clear operation mode field */ + orr r6, r6, #0x4 /* Set operation to memory init */ + MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + + /* Set initVal in the XOR Engine Initial Value Registers */ + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) + + /* Set block size using DRAM bank size */ + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + + ldr r6, [r5] + HTOLL(r6,r5) + and r6, r6, #SCSR_SIZE_MASK + mov r5, r6, LSR #SCSR_SIZE_OFFS + add r5, r5, #1 + mov r6, r5, LSL #SCSR_SIZE_OFFS + MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) + + /* Clean interrupt cause*/ + MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) + + /* Clean error interrupt cause*/ + MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) + MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) + + /* Start transfer */ + MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + orr r6, r6, #0x1 /* Preform start command */ + MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + + /* Wait for engine to finish */ +waitForComplete: + MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) + and r6, r6, #2 + cmp r6, #0 + beq waitForComplete + + /* Clear all error report registers */ + MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) + MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) + + MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) + + cmp sp, #0 + beq no_stack_l1 +load_from_stack1: + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} +no_stack_l1: + mov pc, lr + + +/******************************************************************************* +* mvDramIfMemInit - Use XOR to clear all memory. +* +* DESCRIPTION: +* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV78XX0) + +_mvDramIfMemInit: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} + mov r6, LR /* Save link register */ + /* Check if dram bank 0 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) + and r3, r0, #SCSR_WIN_EN + cmp r3, #0 + beq no_bank_0 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) + cmp r0, #0 + beq no_bank_0 + mov r0,#0 + bl _mvDramIfEccMemInit + +no_bank_0: + /* Check if dram bank 1 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_1 + mov r0,#1 + bl _mvDramIfEccMemInit +no_bank_1: + /* Check if dram bank 2 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_2 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) + cmp r0, #0 + beq no_bank_2 + mov r0,#2 + bl _mvDramIfEccMemInit + +no_bank_2: + /* Check if dram bank 3 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_3 + mov r0,#3 + bl _mvDramIfEccMemInit +no_bank_3: + mov LR ,r6 /* restore link register */ + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} + mov pc, lr +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIf.h u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIf.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIf.h 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,177 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/* includes */ +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ddr2/mvDramIfRegs.h" +#include "ddr2/mvDramIfConfig.h" +#include "mvSysDdrConfig.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ + +#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ +#define ECC_DISABLE 1 /* Force ECC to Disable */ +#define ECC_ENABLE 0 /* Force ECC to ENABLE */ + +/* typedefs */ +/* enumeration for memory types */ +typedef enum _mvMemoryType { + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +} MV_MEMORY_TYPE; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas { + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_6 = 0x40, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + +typedef struct _mvDramBankInfo { + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY.. */ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + MV_BOOL registeredDQMBinputs; + +} MV_DRAM_BANK_INFO; + +typedef struct _mvDramIfDecWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_DRAM_DEC_WIN; + +#include "ddr2/spd/mvSpd.h" + +/* mvDramIf.h API list */ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk); +MV_VOID _mvDramIfConfig(int entryNum); + +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); +MV_U32 mvDramIfCalGet(void); +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); +MV_VOID mvDramIfSelfRefreshSet(void); +void mvDramIfShow(void); +MV_U32 mvDramIfGetFirstCS(void); +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder); +MV_U32 mvDramCsSizeGet(MV_U32 csNum); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __INCmvDramIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfRegs.h u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/mvDramIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/mvDramIfRegs.h 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,424 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" + +/* DDR SDRAM Controller Address Decode Registers */ + /* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(cpu, csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(cpu, csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCSR_SIZE_OFFS 24 +#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x1000000 +#define SCSR_WIN_EN BIT0 + +/* configuration register */ +#define SDRAM_CONFIG_REG (MV_DDR_REGS_BASE + 0x1400) +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3FFF +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 15 +#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_ECC_OFFS 18 +#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) +#define SDRAM_IERR_OFFS 19 +#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) +#define SDRAM_SRMODE_OFFS 24 +#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) + +/* dunit control low register */ +#define SDRAM_DUNIT_CTRL_REG (MV_DDR_REGS_BASE + 0x1404) +#define SDRAM_2T_OFFS 4 +#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) +#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) + +#define SDRAM_SRCLK_OFFS 5 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK2DRV_OFFS 13 +#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_SB_OUT_DEL_OFFS 20 +#define SDRAM_SB_OUT_DEL_MAX 0xf +#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS)) { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if (MV_OK != dimmSpdGet((MV_U32) (bankNum / 2), &dimmInfo)) { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size / pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || (pDimmInfo->memoryType == MEM_TYPE_DDR1)) { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } else { /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} + +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + + if (MV_OK != mvSysDdrSpdRead(data, SPD_SIZE)) { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for (i = 0; i <= 62; i++) + spdChecksum += data[i]; + + if ((spdChecksum & 0xff) != data[63]) { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32) (spdChecksum & 0xff), data[63])); + } else { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + for (i = 0; i < SPD_SIZE; i++) { + if (MV_OK != mvSysDdrSpdWrite(&data[i], 1)) { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n", i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_U8 data[SPD_SIZE]; + + if ((NULL == pDimmInfo) || (dimmNum >= MAX_DIMM_NUM)) { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + if (MV_OK != mvSysDdrSpdRead(data, SPD_SIZE)) { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for (i = 0; i <= 62; i++) + spdChecksum += data[i]; + + if ((spdChecksum & 0xff) != data[63]) { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32) (spdChecksum & 0xff), data[63])); + } else { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure */ + for (i = 0; i < SPD_SIZE; i++) { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n", pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n", pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7) + 1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n", pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1 */ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2 */ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * pDimmInfo->numOfBanksOnEachDevice * pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n", pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth / pDimmInfo->sdramWidth) * pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } else { /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n", pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum, MV_U32 sysClock) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0, leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks, temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (sysClock / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if (MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for (i = 0; i < DIMM_MODULE_MANU_SIZE; i++) + mvOsOutput("%x", spdRawData[DIMM_MODULE_MANU_OFFS + i]); + + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for (i = 0; i < DIMM_MODULE_ID_SIZE; i++) + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for (i = 0; i < DIMM_MODULE_VEN_SIZE; i++) + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for (i = 0; i < sizeof(MV_U32); i++) + temp |= spdRawData[95 + i] << 8 * i; + + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", spdRawData[62] / 10, spdRawData[62] % 10); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for (i = 2; i <= 35; i++) + switch (i) { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch (spdRawData[i]) { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + rightOfPoint = 25; + if ((spdRawData[i] & 0x0f) == 0xB) + rightOfPoint = 33; + if ((spdRawData[i] & 0x0f) == 0xC) + rightOfPoint = 66; + if ((spdRawData[i] & 0x0f) == 0xD) + rightOfPoint = 75; + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10 : 100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || (dimmInfo.memoryType == MEM_TYPE_DDR1)) + mvOsOutput("Minimum Clk Delay back to back: %d\n", spdRawData[i]); + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || (dimmInfo.memoryType == MEM_TYPE_DDR1)) { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + for (k = 0; k <= 7; k++) { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k + 1); + } + } else if (dimmInfo.memoryType == MEM_TYPE_DDR1) { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } else if (dimmInfo.memoryType == MEM_TYPE_DDR2) { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } else if (dimmInfo.memoryType == MEM_TYPE_DDR1) { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } else { /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + if (spdRawData[i] & BIT0) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if (spdRawData[i] & BIT1) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if (spdRawData[i] & BIT2) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if (spdRawData[i] & BIT3) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if (spdRawData[i] & BIT4) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if (spdRawData[i] & BIT5) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } else if (dimmInfo.memoryType == MEM_TYPE_DDR1) { + if (spdRawData[i] & BIT0) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if (!(spdRawData[i] & BIT4)) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if (!(spdRawData[i] & BIT5)) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if (spdRawData[i] & BIT6) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if (spdRawData[i] & BIT7) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } else if (dimmInfo.memoryType == MEM_TYPE_DDR2) { + if (spdRawData[i] & BIT0) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + rightOfPoint = 25; + if ((spdRawData[i] & 0x0f) == 0xB) + rightOfPoint = 33; + if ((spdRawData[i] & 0x0f) == 0xC) + rightOfPoint = 66; + if ((spdRawData[i] & 0x0f) == 0xD) + rightOfPoint = 75; + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10 : 100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } else { /* DDR1 or DDR2 */ + + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + rightOfPoint = 25; + if ((spdRawData[i] & 0x0f) == 0xB) + rightOfPoint = 33; + if ((spdRawData[i] & 0x0f) == 0xC) + rightOfPoint = 66; + if ((spdRawData[i] & 0x0f) == 0xD) + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } else { /* DDR1 or DDR2 */ + + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0 : 2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + temp = ((leftOfPoint * 100) + rightOfPoint); /* in 10ps Intervals */ + trp_clocks = (temp + (busClkPs - 1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0 : 2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + temp = ((leftOfPoint * 100) + rightOfPoint); /* in 100ns Interval */ + trrd_clocks = (temp + (busClkPs - 1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0 : 2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + temp = ((leftOfPoint * 100) + rightOfPoint); /* in 100ns Interval */ + trcd_clocks = (temp + (busClkPs - 1)) / busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i]) + (busClkPs - 1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } else if (dimmInfo.memoryType == MEM_TYPE_DDR1) { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } else { /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if (leftOfPoint > 7) + leftOfPoint *= -1; + } else { /* DDR1 or DDR2 */ + + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if (leftOfPoint > 7) + leftOfPoint *= -1; + } else { /* DDR1 or DDR2 */ + + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if (leftOfPoint > 7) + leftOfPoint *= -1; + } else { /* DDR1 or DDR2 */ + + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if (leftOfPoint > 7) + leftOfPoint *= -1; + } else { /* DDR1 or DDR2 */ + + time_tmp = (((spdRawData[i] & 0xf0) >> 4) * 10) + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if (ns10 < 10) + ns10 *= 10; + else if (ns10 == 10) + ns10 = 25; + else if (ns10 == 11) + ns10 = 33; + else if (ns10 == 12) + ns10 = 66; + else if (ns10 == 13) + ns10 = 75; + else + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + + return (ns * 1000 + ns10 * 10); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/spd/mvSpd.h u-boot-2009.08/board/marvell/mv_hal/ddr2/spd/mvSpd.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2/spd/mvSpd.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2/spd/mvSpd.h 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,192 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ddr2/mvDramIf.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 +#define DIMM_SPD_VERSION 62 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf { + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas { + SD_CL_1 = 1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +} MV_DIMM_SDRAM_CAS; + +/* DIMM information structure */ +typedef struct _mvDimmInfo { + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY.. */ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum, MV_U32 sysClock); +MV_STATUS dimmSpdCpy(MV_VOID); + +#ifdef __cplusplus +} +#endif +#endif /* __INCmvDram */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramCounters.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramCounters.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramCounters.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramCounters.h 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,273 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramCountersh +#define __INCmvDramCountersh + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" +#include "mvDramIfRegs.h" + + + +#define SDRAM_STAT_CNTRS_CTRL (MV_DDR_REGS_BASE + 0x1590) +#define SDRAM_STAT_CNTR_SELECT_OFFSET(c) ((c == 0) ? 0 : 8) +#define SDRAM_STAT_CNTR_SELECT_MASK(c) (0x1F << SDRAM_STAT_CNTR_SELECT_OFFSET(c)) +#define SDRAM_STAT_CNTR_RESET_OFFSET 16 +#define SDRAM_STAT_CNTR_RESET_MASK (0x1 << SDRAM_STAT_CNTR_RESET_OFFSET) +#define SDRAM_STAT_CNTR_START_OFFSET 17 +#define SDRAM_STAT_CNTR_START_MASK (0x1 << SDRAM_STAT_CNTR_START_OFFSET) + +#define SDRAM_STAT_CNTRS_VAL(set, idx) (MV_DDR_REGS_BASE + 0x1594 + (set << 3) + (idx << 2)) +#define SDRAM_STAT_HCLK_VAL(idx) (MV_DDR_REGS_BASE + 0x15A4 + (idx << 2)) + + +typedef enum { + MBUSL_CACHE_READ = 0, + MBUSL_BURST_READ, + MBUSL_PAR_READ, + MBUSL_CACHE_WRITE, + MBUSL_BURST_WRITE, + MBUSL_UNSPEC_WRITE, + MBUSL_FULL_PAR_WRITE, + MBUSL_SEMI_PAR_WRITE, + MBUSL_TOTAL_READS, + MBUSL_TOTAL_WRITES, + MBUSL_TOTAL_TRANS, + MBUSL0_TOTAL_TRANS, + MBUSL1_TOTAL_TRANS, + MBUSL_LOOKUP_HIT, + MBUS_CACHE_READ, + MBUS_BURST_READ, + MBUS_PAR_READ, + MBUS_CACHE_WRITE, + MBUS_CACHE_WRITE_RMW, + MBUS_BURST_WRITE, + MBUS_BURST_WRITE_RMW, + MBUS_PAR_WRITE, + MBUS_PAR_WRITE_RMW, + MBUS_TOTAL_READS, + MBUS_TOTAL_WRITES, + MBUS_TOTAL_TRANS, + MBUS0_TOTAL_TRANS, + MBUS1_TOTAL_TRANS, + MBUS_BURST_CHOP, + NUM_BURSTS_128BIT, + DRAM_ACTIVE, + DRAM_PRECHARGE +} MV_DRAM_STAT_MODE; + +/******************************************************************************* +* mvDramStatStart +* +* DESCRIPTION: +* Start DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatStart(void) +{ + MV_REG_BIT_SET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_START_MASK); +} + +/******************************************************************************* +* mvDramStatStop +* +* DESCRIPTION: +* Stop DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatStop(void) +{ + MV_REG_BIT_RESET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_START_MASK); +} + +/******************************************************************************* +* mvDramStatClear +* +* DESCRIPTION: +* Clear the DRAM statistics counters. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static inline void mvDramStatClear(void) +{ + MV_U32 reg; + + MV_REG_BIT_SET(SDRAM_STAT_CNTRS_CTRL, SDRAM_STAT_CNTR_RESET_MASK); + do { + reg = MV_REG_READ(SDRAM_STAT_CNTRS_CTRL); + } while(reg & SDRAM_STAT_CNTR_RESET_MASK); + + return; +} + + +/******************************************************************************* +* mvDramStatConfig +* +* DESCRIPTION: +* Configure the DRAM statistics counters. +* +* INPUT: +* cntIdx - The counter index to configure. +* mode - The mode to configure the counter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_FAIL otherwise. +* +*******************************************************************************/ +static inline MV_STATUS mvDramStatConfig(MV_U8 cntIdx, MV_DRAM_STAT_MODE mode) +{ + MV_U32 reg; + + reg = MV_REG_READ(SDRAM_STAT_CNTRS_CTRL); + reg &= ~SDRAM_STAT_CNTR_SELECT_MASK(cntIdx); + reg |= (mode << SDRAM_STAT_CNTR_SELECT_OFFSET(cntIdx)); + MV_REG_WRITE(SDRAM_STAT_CNTRS_CTRL, reg); + + return MV_OK; +} + +/******************************************************************************* +* mvDramStatRead +* +* DESCRIPTION: +* Read the current DRAM statistics value. +* +* INPUT: +* None. +* +* OUTPUT: +* counter0 - Value of DRAM statistics counter #0. +* counter1 - Value of DRAM statistics counter #1. +* hclk - Value of HCLK counter. +* +* RETURN: +* MV_OK on success, +* MV_FAIL otherwise. +* +*******************************************************************************/ +static inline MV_STATUS mvDramStatRead(MV_U64 *counter0, MV_U64 *counter1, MV_U64 *hclk) +{ + MV_U32 val; + + if(counter0 != NULL) { + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(0, 0)); + *counter0 = val; + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(0, 1)); + *counter0 |= ((MV_U64)val << 32); + } + + if(counter1 != NULL) { + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(1, 0)); + *counter1 = val; + val = MV_REG_READ(SDRAM_STAT_CNTRS_VAL(1, 1)); + *counter1 |= ((MV_U64)val << 32); + } + + if(hclk != NULL) { + val = MV_REG_READ(SDRAM_STAT_HCLK_VAL(0)); + *hclk = val; + val = MV_REG_READ(SDRAM_STAT_HCLK_VAL(1)); + *hclk |= ((MV_U64)val << 32); + } + + return MV_OK; +} + +#endif /* __INCmvDramCountersh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfBasicInit.S u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfBasicInit.S --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfBasicInit.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfBasicInit.S 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,1027 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAsm.h" +#include "mvCommon.h" + +/* defines */ +#if defined(MV_STATIC_DRAM_ON_BOARD) +/****************************************************************************** +* static definitions for several dimms +*******************************************************************************/ +#if defined(DB_MV78XX0) || defined(DB_MV88F632X) +#if defined(MV78100) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(MV78200) +/* 512MB per CD, 800Mhz cl5 */ +#define STATIC_DRAM_BANK_CS0 +#define STATIC_DRAM_BANK_CS2 + +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM1_BANK0_SIZE 0x1ffffff9 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x20000000 /* 0x1510 */ + + +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_DUNIT_CTRL_LOW 0x37543010 /* 0x1404 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ + +#define STATIC_SDRAM_ADDR_CTRL 0x00008888 /* 0x1410 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ + +#define STATIC_SDRAM_EXT_MODE 0x00000044 /* 0x1420 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FF7F /* 0x1424 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ + +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F40F /* 0x149c */ + +#endif + +#elif defined(RD_MV78XX0_AMC) +/* On board DDR2 512MB 400MHz CL5 */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM1_BANK0_SIZE 0x0FFFFFF1 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x10000000 /* 0x1510 */ + +#elif defined(RD_MV78XX0_H3C) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ + +#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_PCAC) +/* DDR2 boards 256MB 200MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#else +/* DDR2 MV88F6281 boards 256MB 400MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ +#endif /* MV78XX0 */ + +#endif /* MV_STATIC_DRAM_ON_BOARD */ + +.globl dramBoot1 +dramBoot1: + .word 0 +/************************************************************* +* basic timing init +**************************************************************/ + .globl _mvDramInitTiming +_mvDramInitTiming: + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) +#endif + + + /*DDR SDRAM Initialization Control */ + ldr r6, =DSICR_INIT_EN + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + and r6, r6, #DSICR_INIT_EN + cmp r6, #0 + bne 2b + mov pc, lr + + +#if defined(MV_STATIC_DRAM_ON_BOARD) +/************************************************************* +* basic init for static DRAM (on board dram no SPD) +**************************************************************/ + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + bl _mvDramInitTiming + + /* If we boot from NAND jump to DRAM address */ + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + +#ifdef STATIC_DRAM_BANK_CS2 + ldr r6, = STATIC_SDRAM1_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + ldr r6, = STATIC_SDRAM1_BANK0_BASE + MV_REG_WRITE_ASM(r6, r5, SDRAM_BASE_ADDR_REG (0,2)) +#endif + + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) +#ifndef MTD_NAND_LNC_BOOT + ldr r6, = STATIC_DUNIT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) +#endif + + ldr sp,=0 + bl _mvDramIfConfig + ldr r0, =0 +#ifdef MV78XX0 + bl _mvDramIfEccMemInit +#ifdef STATIC_DRAM_BANK_CS2 + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + ldr r0, =0 +#endif +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define DIMM_TYPE_OFFSET 2 +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define DIMM_CONFIG_TYPE 11 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 +#define RANK_SIZE_OFFSET 31 + +#define DRAM_DEV_DENSITY_128M 128 +#define DRAM_DEV_DENSITY_256M 256 +#define DRAM_DEV_DENSITY_512M 512 +#define DRAM_DEV_DENSITY_1G 1024 +#define DRAM_DEV_DENSITY_2G 2048 + +#define DRAM_RANK_DENSITY_128M 0x20 +#define DRAM_RANK_DENSITY_256M 0x40 +#define DRAM_RANK_DENSITY_512M 0x80 +#define DRAM_RANK_DENSITY_1G 0x1 +#define DRAM_RANK_DENSITY_2G 0x2 + + .globl _mvDramIfBasicInit + .extern _i2cInit +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + bl _mvDramInitTiming + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM address */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + bl _i2cInit /* Initialize TWSI master */ + + /* Check if we have more then 1 dimm */ + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +#ifdef MV78XX0 + bl _is_Second_Dimm_Exist + beq single_dimm + ldr r6, =1 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +single_dimm: + bl _i2cInit /* Initialize TWSI master */ +#endif + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ +nonRegistered: +#if defined(MV78XX0) && !defined(MV632X) + /* Get ECC/non ECC info from DIMM */ + bl _is_Ecc + beq setConfigReg + +setEcc: + orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ +#endif +setConfigReg: + MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + +casDdr2: + ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x52 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x62 /* Assuming MAX CL = 6 */ + cmp r6, #6 /* If CL = 5 break */ + beq casDdr2Cont + + /* This is an error. return */ + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + + /* Get default SDRAM Mode values */ + MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) + bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ + orr r6, r6, r8 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) + + /* Set Dunit control register according to max CL detected */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + mov r7, r3 + +setDunitReg: +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + ble Clock333 + add r7, r7, #0x10 +Clock333: +#endif + + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + orr r6, r6, r7, LSL #20 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) + + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + /* Get bank 0 and 1 density */ + ldr r6, =0 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_bank_2_density + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_density: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne get_width + + /* Get bank 2 and 3 density */ + ldr r6, =2 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_width + + /* This is an error. return */ + b exit_ddrAutoConfig + + /* Get SDRAM width */ +get_width: + /* Get bank 0 and 1 width */ + ldr r6, =0 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq get_bank_2_width + + orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ + cmp r7, #16 + beq get_bank_2_width + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_width: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne densCont + + /* Get bank 2 and 3 width */ + ldr r6, =2 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq densCont + + orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ + cmp r7, #16 + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) + + /* Set SDRAM timing control low register */ + ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT + /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) + + /* Set SDRAM timing control high register */ + ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + blt timingHighClock333 + orr r6, r6, #BIT9 + +timingHighClock333: + /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne single_dimm_odt + + /* Set SDRAM ODT control low register for double DIMM*/ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register for double DIMM */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_267 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_300 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + beq fast_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_400 + cmp r4, r5 + beq fast_dram_clock_rtt + + b slow_dram_clock_rtt + +fast_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end +#endif +slow_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end + +single_dimm_odt: + /* Set SDRAM ODT control low register */ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + + /* Set SDRAM Extended Mode register */ + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + +odt_config_end: + /* SDRAM ODT control high register is left as default */ + MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) + + /*Read CL and set the DDR2 registers accordingly */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) + and r6, r6, #SDRAM_CL_MASK + mov r4, r6 + orr r4, r4, r6, LSL #4 + orr r4, r4, r6, LSL #8 + orr r4, r4, r6, LSL #12 + mov r5, #0x30000 + add r4, r4, r5 + sub r4, r4, #0x30 + /* Set SDRAM Ddr2 Timing Low register */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) + + /* Set SDRAM Ddr2 Timing High register */ + mov r4, r4, LSR #4 + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) + +timeParamDone: + /* Close all windows */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Set sdram bank 0 size and enable it */ + ldr r6, =0 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) + + /* Clear bank 2 size */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne defualt_order + + /* Set sdram bank 2 size */ + ldr r6, =2 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width2 + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width2: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) + + /* Close windows 1 and 3 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Check dimm size for setting dram bank order */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#SCSR_SIZE_MASK + and r4, r4,#SCSR_SIZE_MASK + cmp r6, r4 + bge defualt_order + + /* Bank 2 is biger then bank 0 */ + ldr r6,=0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) + + /* Open win 2 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 2 */ + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + mov PC, r11 /* r11 is saved link register */ + +defualt_order: + + /* Open win 0 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 0 */ + ldr r0, =0 + bl _mvDramIfEccMemInit +#endif +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + /* Get SDRAM width (SPD offset 13) */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ +#if defined(MV645xx) + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 + b exit +#endif +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +/**************************/ +/* Return value in flag if no-Ecc then Z-flag is set */ +_is_Ecc: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_CONFIG_TYPE + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 /* bit 1 -> Data ECC */ + mov PC, r13 + +/**************************/ +/* Return value in flag if no second DIMM then Z-flag is set */ +_is_Second_Dimm_Exist: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ + mov PC, r13 + +/******************************************************************************* +* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size +* +* DESCRIPTION: +* The function will read the bank 0 dram size(SPD version 1.0 and above ) +* +* INPUT: +* r6 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfGetDimmSizeFromSpd: + + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #RANK_SIZE_OFFSET /* offset 31 */ + bl _i2cRead + +pass_read: + ldr r8, =(0x7 << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_128M + beq endDimmSize + + ldr r8, =(0xf << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_256M + beq endDimmSize + + ldr r8, =(0x1f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_512M + beq endDimmSize + + ldr r8, =(0x3f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_1G + beq endDimmSize + + ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ +endDimmSize: + mov PC, r13 +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.c u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.c 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,2145 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" +#include "mvDramIf.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +/* #include "ctrlEnv/sys/mvCpuIf.h" */ +#include "mvDramIfStaticInit.h" +#include "spd/mvSpd.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* DRAM bank presence encoding */ +#define BANK_PRESENT_CS0 0x1 +#define BANK_PRESENT_CS0_CS1 0x3 +#define BANK_PRESENT_CS0_CS2 0x5 +#define BANK_PRESENT_CS0_CS1_CS2 0x7 +#define BANK_PRESENT_CS0_CS2_CS3 0xd +#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf + +/* locals */ +#ifndef MV_STATIC_DRAM_ON_BOARD +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTmode ); +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramModeRegCalc(MV_U32 minCas); +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1); +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk); +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl); +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk); +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas); +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas); +#endif +MV_32 DRAM_CS_Order[MV_DRAM_MAX_CS] = {N_A + +#ifdef MV_INCLUDE_SDRAM_CS1 + ,N_A +#endif +#ifdef MV_INCLUDE_SDRAM_CS2 + ,N_A +#endif +#ifdef MV_INCLUDE_SDRAM_CS3 + ,N_A +#endif + }; +/* Get DRAM size of CS num */ +MV_U32 mvDramCsSizeGet(MV_U32 csNum) +{ + MV_DRAM_BANK_INFO bankInfo; + MV_U32 size, deviceW, dimmW; +#ifdef MV78XX0 + MV_U32 temp; +#endif + + if(MV_OK == mvDramBankInfoGet(csNum, &bankInfo)) + { + if (0 == bankInfo.size) + return 0; + + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; +#else + deviceW = 16 /* KW family */; +#endif + dimmW = bankInfo.dataWidth - (bankInfo.dataWidth % 16); + size = ((bankInfo.size << 20) / (dimmW/deviceW)); + return size; + } + else + return 0; +} +/******************************************************************************* +* mvDramIfDetect - Prepare DRAM interface configuration values. +* +* DESCRIPTION: +* This function implements the full DRAM detection and timing +* configuration for best system performance. +* Since this routine runs from a ROM device (Boot Flash), its stack +* resides on RAM, that might be the system DRAM. Changing DRAM +* configuration values while keeping vital data in DRAM is risky. That +* is why the function does not preform the configuration setting but +* prepare those in predefined 32bit registers (in this case IDMA +* registers are used) for other routine to perform the settings. +* The function will call for board DRAM SPD information for each DRAM +* chip select. The function will then analyze those SPD parameters of +* all DRAM banks in order to decide on DRAM configuration compatible +* for all DRAM banks. +* The function will set the CPU DRAM address decode registers. +* Note: This routine prepares values that will overide configuration of +* mvDramBasicAsmInit(). +* +* INPUT: +* forcedCl - Forced CAL Latency. If equal to zero, do not force. +* eccDisable - Force down the ECC. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk) +{ +#ifndef MV_STATIC_DRAM_ON_BOARD + MV_32 MV_DRAM_CS_order[MV_DRAM_MAX_CS] = { + SDRAM_CS0 +#ifdef MV_INCLUDE_SDRAM_CS1 + ,SDRAM_CS1 +#endif +#ifdef MV_INCLUDE_SDRAM_CS2 + ,SDRAM_CS2 +#endif +#ifdef MV_INCLUDE_SDRAM_CS3 + ,SDRAM_CS3 +#endif + }; +#endif + MV_U32 busClk; +#ifndef MV_STATIC_DRAM_ON_BOARD + MV_U32 deviceW, dimmW; + MV_U32 numOfAllDevices = 0; + MV_STATUS TTMode; + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + MV_U32 size, base = 0, i, j, temp, busClkPs; + MV_U8 minCas; + MV_DRAM_DEC_WIN dramDecWin; + dramDecWin.addrWin.baseHigh = 0; +#endif + + busClk = sysClk; + + if (0 == busClk) + { + mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); + return MV_ERROR; + } + +#ifndef MV_STATIC_DRAM_ON_BOARD + + busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + /* we will use bank 0 as the representative of the all the DRAM banks, */ + /* since bank 0 must exist. */ + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + /* if Bank exist */ + if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) + { + DB(mvOsPrintf("Dram: Find bank %d\n", i)); + /* check it isn't SDRAM */ + if(bankInfo[i].memoryType != MEM_TYPE_DDR2) + { + mvOsOutput("Dram: ERR. SDRAM type not supported !!!\n"); + return MV_ERROR; + } + + /* All banks must support the Mclk freqency */ + if(bankInfo[i].minCycleTimeAtMaxCasLatPs > busClkPs) + { + mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); + return MV_ERROR; + } + + /* All banks must support registry in order to activate it */ + if(bankInfo[i].registeredAddrAndControlInputs != + bankInfo[0].registeredAddrAndControlInputs) + { + mvOsOutput("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* All banks must support same ECC mode */ + if(bankInfo[i].errorCheckType != + bankInfo[0].errorCheckType) + { + mvOsOutput("Dram: ERR. different ECC settings !!!\n"); + return MV_ERROR; + } + + } + else + { + if( i == 0 ) /* bank 0 doesn't exist */ + { + mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } + else + { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + MV_DRAM_CS_order[0] = SDRAM_CS2; + MV_DRAM_CS_order[1] = SDRAM_CS3; + MV_DRAM_CS_order[2] = SDRAM_CS0; + MV_DRAM_CS_order[3] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + } + else +#endif + { + MV_DRAM_CS_order[0] = SDRAM_CS0; + MV_DRAM_CS_order[1] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + MV_DRAM_CS_order[2] = SDRAM_CS2; + MV_DRAM_CS_order[3] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + } + + for(j = 0; j < MV_DRAM_MAX_CS; j++) + { + i = MV_DRAM_CS_order[j]; + + if (0 == bankInfo[i].size) + continue; + + /* Init the CPU window decode */ + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; +#else + deviceW = 16 /* KW family */; +#endif + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + + numOfAllDevices += bankInfo[i].numberOfDevices; + if (i == MV_DRAM_CS_order[0]) + { + MV_U32 sizeToReg; + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsOutput("DRAM: ctrlSizeToReg: ERR. Win %d size invalid.\n" + ,i); + return MV_BAD_PARAM; + } + + DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) + sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); + sizeToReg |= SCSR_WIN_EN; + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } + else + { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + + /* Check if the DRAM size is more then 3GByte */ + if (base < 0xC0000000) + { + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + if (MV_OK != mvDramIfWinSet(i, &dramDecWin)) + { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); + return MV_ERROR; + } + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); + if (0 == minCas) + { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", + (busClk / 1000000)); + + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsOutput("Set default CAS latency 4\n"); + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off ECC*/ + temp &= ~BIT18; + } + DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + TTMode = MV_FALSE; + DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) + if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) + { + if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || + (numOfAllDevices > 18) ) + { + mvOsOutput("Enable 2T "); + TTMode = MV_TRUE; + } + } + + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ + temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off sample stage if no ecc */ + temp &= ~SDRAM__D2P_EN;; + } + MV_REG_WRITE(DRAM_BUF_REG13, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + sdramDDr2OdtConfig(bankInfo); + + /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ + temp = sdramDdr2TimeLoRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG11, temp); + + /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ + temp = sdramDdr2TimeHiRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG12, temp); +#endif + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return MV_OK; +} + + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + MV_U32 result = 0xFFFFFFFF; + + if(mvDramIfWinGet(SDRAM_CS0 + bankNum, &addrDecWin) == MV_OK) { + if(addrDecWin.enable == MV_TRUE) + result = addrDecWin.addrWin.baseLow; + } + + DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", + bankNum, result)); + return result; +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + MV_U32 result = 0; + + if(mvDramIfWinGet(SDRAM_CS0 + bankNum, &addrDecWin) == MV_OK) { + if(addrDecWin.enable == MV_TRUE) + result = addrDecWin.addrWin.size; + } + + DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", + bankNum, result)); + return result; +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 size = 0, i; + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + size += mvDramIfBankSizeGet(i); + + DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); + return size; +} + +/******************************************************************************* +* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. +* +* DESCRIPTION: +* The ECC single bit error threshold is the number of single bit +* errors to happen before the Dunit generates an interrupt. +* This function set single bit ECC threshold. +* +* INPUT: +* threshold - threshold. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) +{ + MV_U32 regVal; + + if (threshold > SECR_THRECC_MAX) + { + return MV_BAD_PARAM; + } + + regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); + regVal &= ~SECR_THRECC_MASK; + regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); + MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); + + return MV_OK; +} + +#ifndef MV_STATIC_DRAM_ON_BOARD +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ + +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + MV_U32 minCas0 = 0, minCas2 = 0; + + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * + Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * + *********************************************************/ + + + /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ + if (forcedCl) + { + mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); + + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 50) + pBankInfo->suportedCasLatencies = 0x20; + else if (forcedCl == 60) + pBankInfo->suportedCasLatencies = 0x40; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies,busClkPs )); + count = 1; + for(j = 7; j > 0; j--) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo->suportedCasLatencies )); + + count = 1; + DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo2->suportedCasLatencies,busClkPs )); + for(j = 7; j > 0; j--) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo2->suportedCasLatencies )); + + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas0 = (BIT0 << j); + break; + } + } + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas2 = (BIT0 << j); + break; + } + } + + if (minCas2 > minCas0) + return minCas2; + else + return minCas0; + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) + { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", + refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if(refreshPeriod > SDRAM_REFRESH_MAX) + { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", + refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if ( pBankInfo->registeredAddrAndControlInputs ) + { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) + } + + /* ECC and IERR support */ + sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ + sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ + + if ( pBankInfo->errorCheckType ) + { + sdramConfig |= SDRAM_ECC_EN; + sdramConfig |= SDRAM_IERR_REPORTE; + DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); + } + else + { + sdramConfig |= SDRAM_ECC_DIS; + sdramConfig |= SDRAM_IERR_IGNORE; + DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); + } + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", + sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + DB(mvOsPrintf("DRAM CAS Latency ");) + + switch (minCas) + { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + DB(mvOsPrintf("3.\n");) + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + DB(mvOsPrintf("4.\n");) + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + DB(mvOsPrintf("5.\n");) + break; + case DDR2_CL_6: + sdramMode |= SDRAM_DDR2_CL_6; + DB(mvOsPrintf("6.\n");) + break; + default: + mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + + DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); + + return sdramMode; +} +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - DRAM frequency +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 populateBanks = 0; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; + + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + if (busClk >= MV_BOARD_SYSCLK_267MHZ) + return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; + else + return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; + + default: + mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) +{ + MV_U32 dunitCtrlLow, cl; + MV_U32 sbOutR[4]={3,5,7,9} ; + MV_U32 sbOutU[4]={1,3,5,7} ; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* Clear StBurstOutDel field */ + dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; + + /* Clear StBurstInDel field */ + dunitCtrlLow &= ~SDRAM_SB_IN_MASK; + + /* Clear CtrlPos field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; + + /* Clear 2T field */ + dunitCtrlLow &= ~SDRAM_2T_MASK; + if (TTMode == MV_TRUE) + { + dunitCtrlLow |= SDRAM_2T_MODE; + } + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstInDel bits [27:24] */ + /* 200MHz - 267MHz None reg = CL + 1 */ + /* 200MHz - 267MHz reg = CL + 2 */ + /* > 267MHz None reg = CL + 2 */ + /* > 267MHz reg = CL + 3 */ + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstOutDel bits [23:20] */ + /********-********-********-********- + * CL=3 | CL=4 | CL=5 | CL=6 | + *********-********-********-********- + Not Reg. * 0001 | 0011 | 0101 | 0111 | + *********-********-********-********- + Registered * 0011 | 0101 | 0111 | 1001 | + *********-********-********-********/ + + /* Set Dunit Control low default value */ + dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; + + switch (minCas) + { + case DDR2_CL_3: cl = 3; break; + case DDR2_CL_4: cl = 4; break; + case DDR2_CL_5: cl = 5; break; + case DDR2_CL_6: cl = 6; break; + default: + mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); + return -1; + } + + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + { + dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + else + { + dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + + DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); + + if (busClk <= MV_BOARD_SYSCLK_267MHZ) + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 2; + else + cl = cl + 1; + } + else + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 3; + else + cl = cl + 2; + } + + DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); + dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; + + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); + + return dunitCtrlLow; +} + +/******************************************************************************* +* dunitCtrlHighRegCalc - Calculate sdram dunit control high register +* +* DESCRIPTION: Calculate sdram dunit control high register optimized value based +* on the bus clock. +* +* INPUT: +* busClk - DRAM frequency. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control high reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 dunitCtrlHigh; + dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); + if(busClk > MV_BOARD_SYSCLK_300MHZ) + dunitCtrlHigh |= SDRAM__P2D_EN; + else + dunitCtrlHigh &= ~SDRAM__P2D_EN; + + if(busClk > MV_BOARD_SYSCLK_267MHZ) + dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); + + /* If ECC support we turn on D2P sample */ + dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ + if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) + dunitCtrlHigh |= SDRAM__D2P_EN; + + return dunitCtrlHigh; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) +{ + MV_U32 addrCtrl = 0; + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + } + + switch (pBankInfo->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); + break; + default: + mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfo->deviceDensity); + return -1; + } + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); + break; + default: + mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfoDIMM1->deviceDensity); + return -1; + } + } + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + MV_U32 timeCtrlLow = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | + ((tRtp - 1) << SDRAM_TRTP_OFFS)); + + /* Check extended tRas bit */ + if ((tRas - 1) & BIT4) + timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); + + return timeCtrlLow; +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timingHigh; + MV_U32 timeNs = 0; + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Set DDR timing high register static configuration bits */ + timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); + + /* Set DDR timing high register default value */ + timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; + + /* Clear tRfc field */ + timingHigh &= ~SDRAM_TRFC_MASK; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", + pBankInfo[bankNum].minRefreshToActiveCmd)); + } + if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) + { + timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; + } + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + + /* SDRAM timing high */ + DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); + + return timingHigh; +} +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; + break; + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; + break; + default: + DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); + return; + } + /* DDR2 SDRAM ODT ctrl low */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + + /* DDR2 SDRAM ODT ctrl high */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + + /* DDR2 DUNIT ODT ctrl */ + if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) ) + dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ + + DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} +/******************************************************************************* +* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing low registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing low reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeLoReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); + ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | + SD2TLR_TODT_OFF_RD_MASK | + SD2TLR_TODT_ON_CTRL_RD_MASK | + SD2TLR_TODT_OFF_CTRL_RD_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas)); + cl = 4; + } + + ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); + ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); + + /* DDR2 SDRAM timing low */ + DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); + + return ddr2TimeLoReg; +} + +/******************************************************************************* +* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing high registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing high reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeHiReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); + ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | + SD2THR_TODT_OFF_WR_MASK | + SD2THR_TODT_ON_CTRL_WR_MASK | + SD2THR_TODT_OFF_CTRL_WR_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas); + cl = 4; + } + + ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); + ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); + + /* DDR2 SDRAM timin high */ + DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); + + return ddr2TimeHiReg; +} +#endif + +/******************************************************************************* +* mvDramIfCalGet - Get CAS Latency +* +* DESCRIPTION: +* This function get the CAS Latency. +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* CAS latency times 10 (to avoid using floating point). +* +*******************************************************************************/ +MV_U32 mvDramIfCalGet(void) +{ + MV_U32 sdramCasLat, casLatMask; + + casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); + + switch (casLatMask) + { + case SDRAM_DDR2_CL_3: + sdramCasLat = 30; + break; + case SDRAM_DDR2_CL_4: + sdramCasLat = 40; + break; + case SDRAM_DDR2_CL_5: + sdramCasLat = 50; + break; + case SDRAM_DDR2_CL_6: + sdramCasLat = 60; + break; + default: + mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); + return -1; + } + + return sdramCasLat; +} + + +/******************************************************************************* +* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - +* +* DESCRIPTION: +* add support in power management. +* +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvDramIfSelfRefreshSet() +{ + MV_U32 operReg; + + operReg = MV_REG_READ(SDRAM_OPERATION_REG); + MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); + /* Read until register is reset to 0 */ + while(MV_REG_READ(SDRAM_OPERATION_REG)); +} +/******************************************************************************* +* mvDramIfDimGetSPDversion - return DIMM SPD version. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) +{ + MV_DIMM_INFO dimmInfo; + if (bankNum >= MV_DRAM_MAX_CS ) + { + DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); + return ; + } + memset(&dimmInfo,0,sizeof(dimmInfo)); + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return ; + } + *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; + *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; +} +/******************************************************************************* +* mvDramIfShow - Show DRAM controller information. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvDramIfShow(void) +{ + int i, sdramCasLat, sdramCsSize; + MV_U32 Major=0, Minor=0; + + mvOsOutput("DRAM Controller info:\n"); + + mvOsOutput("Total DRAM "); + mvSizePrint(mvDramIfSizeGet()); + mvOsOutput("\n"); + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + sdramCsSize = mvDramIfBankSizeGet(i); + if (sdramCsSize) + { + if (0 == (i & 1)) + { + mvDramIfDimGetSPDversion(&Major, &Minor,i); + mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); + } + mvOsOutput("\tDRAM CS[%d] ", i); + mvSizePrint(sdramCsSize); + mvOsOutput("\n"); + } + } + sdramCasLat = mvDramIfCalGet(); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) + { + mvOsOutput("ECC enabled, "); + } + else + { + mvOsOutput("ECC Disabled, "); + } + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) + { + mvOsOutput("Registered DIMM\n"); + } + else + { + mvOsOutput("Non registered DIMM\n"); + } + + mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); +} +/******************************************************************************* +* mvDramIfGetFirstCS - find the DRAM bank on the lower address +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +*******************************************************************************/ +MV_U32 mvDramIfGetFirstCS(void) +{ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + + if (DRAM_CS_Order[0] == N_A) + { + mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); +#ifdef MV_INCLUDE_SDRAM_CS2 + mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); +#endif + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + return SDRAM_CS2; + } +#endif + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + return SDRAM_CS0; + } + return DRAM_CS_Order[0]; +} +/******************************************************************************* +* mvDramIfGetCSorder - +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* CS number. +* +* OUTPUT: +* CS order. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +* NOTE: mvDramIfGetFirstCS must be caled before this subroutine +*******************************************************************************/ +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) +{ + return DRAM_CS_Order[csOrder]; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 sizeToReg=0; + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= (pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK); + + /* Translate the given window size to register format */ + sizeToReg = (pAddrDecWin->addrWin.size / SCSR_SIZE_ALIGNMENT) - 1; + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register. */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); + + /* Write to address decode Size Register. */ + MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * SCSR_SIZE_ALIGNMENT; + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + if (enable == MV_TRUE) + { + /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } + + return MV_OK; +} + +MV_VOID mvDdrPhyRegRead(MV_U8 regNum, MV_U8 pupNum, MV_U16 *value) +{ + MV_U32 regAddr; + MV_U32 reg; + + regAddr = (BIT31 | ((regNum & 0x3F) << 16) | ((pupNum & 0xF) << 22)); + MV_REG_WRITE(SDRAM_PHY_REGISTER_FILE_ACCESS, regAddr); + + do { + reg = MV_REG_READ(SDRAM_PHY_REGISTER_FILE_ACCESS); + } while ((reg & BIT31) != 0); + + *value = (reg & 0xFFFF); +} + +MV_VOID mvDdrPhyRegWrite(MV_U8 regNum, MV_U8 pupNum, MV_U16 value) +{ + MV_U32 regAddr; + MV_U32 reg; + + regAddr = (BIT31 | BIT30 | ((regNum & 0x3F) << 16) | ((pupNum & 0xF) << 22) | value); + MV_REG_WRITE(SDRAM_PHY_REGISTER_FILE_ACCESS, regAddr); + + do { + reg = MV_REG_READ(SDRAM_PHY_REGISTER_FILE_ACCESS); + } while ((reg & BIT31) != 0); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.h 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,157 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) + +#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ + (SDRAM_SRCLK_KEPT | \ + SDRAM_CLK1DRV_NORMAL | \ + (BIT28 | BIT29)) + +#define SDRAM_ADDR_CTRL_DV 2 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) + +/* Note: value of 0 in register means one cycle, 1 means two and so on */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ + ((0x0 << SDRAM_TR2R_OFFS) | \ + (0x0 << SDRAM_TR2W_W2R_OFFS) | \ + (0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 +#endif + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 +#endif + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) +/* DDR SDRAM Timing parameter default values */ +#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 +#define SDRAM_TRFC_DEFAULT_VALUE 0x34 +#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE +#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) + +#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) + +#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.S u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.S --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfConfig.S 2011-04-04 13:57:34.955597525 -0400 @@ -0,0 +1,528 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCommon.h" +#include "mvSysXorConfig.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig +.text +.globl _mvDramIfMemInit + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4} +no_stack_s: + + /* Dunit FTDLL Configuration Register */ + /* 0) Write to SDRAM FTDLL coniguration register */ + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) + str r4, [r1] + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 2) Write Dunit control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] +#if defined(MV_STATIC_DRAM_ON_BOARD) + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) + str r4, [r1] +#endif + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Now its safe to write new value to SDRAM Extended Mode regist */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r4, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: +cmp sp, #0 + beq no_stack_l + mov r1, LR /* Save link register */ +#if defined(MV78XX0) + bl _mvDramIfMemInit +#endif + mov LR,r1 /* restore link register */ +load_from_stack: + /* Restore registers */ + ldmia sp!, {r1, r2, r3, r4} +no_stack_l: + + mov pc, lr + + +/******************************************************************************* +* _mvDramIfEccMemInit - Basic DRAM ECC initialization. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ +#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ +#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ +/* XOR engine register offsets macros */ +#define XOR_CONFIG_REG(chan) (MV_XOR_REGS_BASE(0) + 0x10 + ((chan) * 4)) +#define XOR_ACTIVATION_REG(chan) (MV_XOR_REGS_BASE(0) + 0x20 + ((chan) * 4)) +#define XOR_CAUSE_REG (MV_XOR_REGS_BASE(0) + 0x30) +#define XOR_ERROR_CAUSE_REG (MV_XOR_REGS_BASE(0) + 0x50) +#define XOR_ERROR_ADDR_REG (MV_XOR_REGS_BASE(0) + 0x60) +#define XOR_WINDOW_CTRL_REG(chan) (MV_XOR_REGS_BASE(0) + 0x240 + ((chan) * 4)) +#define XOR_BASE_ADDR_REG(winNum) (MV_XOR_REGS_BASE(0) + 0x250 + ((winNum) * 4)) +#define XOR_SIZE_MASK_REG(winNum) (MV_XOR_REGS_BASE(0) + 0x270 + ((winNum) * 4)) +#define XOR_INIT_VAL_LOW_REG (MV_XOR_REGS_BASE(0) + 0x2E0) +#define XOR_INIT_VAL_HIGH_REG (MV_XOR_REGS_BASE(0) + 0x2E4) +#define XOR_DST_PTR_REG(chan) (MV_XOR_REGS_BASE(0) + 0x2B0 + ((chan) * 4)) +#define XOR_BLOCK_SIZE_REG(chan) (MV_XOR_REGS_BASE(0) + 0x2C0 + ((chan) * 4)) + +.globl _mvDramIfEccMemInit +/******************************************************************************* +* _mvDramIfEccMemInit - mem init for dram cs +* +* DESCRIPTION: +* This function will clean the cs by ussing the XOR mem init. +* +* INPUT: +* r0 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfEccMemInit: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s1 +save_on_stack1: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} +no_stack_s1: + + ldr r1, = 0 + + /* Disable all XOR address decode windows to avoid possible overlap */ + MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_CHAN0))) + + /* Init r5 to first XOR_SIZE_MASK_REG */ + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_ADDR_DEC_WIN0)) + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + /* Update destination & size */ + MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) + HTOLL(r6,r5) + /* Init r6 to first XOR_BASE_ADDR_REG */ + ldr r4, = 0xf + ldr r5, = 0x1 + mov r5, r5, LSL r0 + bic r4, r4, r5 + mov r4, r4, LSL #8 + + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_ADDR_DEC_WIN0)) + + ldr r6, = 0xff0001 + MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_CHAN0)) + + /* Configure XOR engine for memory init function. */ + MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + and r6, r6, #~0x7 /* Clear operation mode field */ + orr r6, r6, #0x4 /* Set operation to memory init */ + MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + + /* Set initVal in the XOR Engine Initial Value Registers */ + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) + + /* Set block size using DRAM bank size */ + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + + ldr r6, [r5] + HTOLL(r6,r5) + and r6, r6, #SCSR_SIZE_MASK + mov r5, r6, LSR #SCSR_SIZE_OFFS + add r5, r5, #1 + mov r6, r5, LSL #SCSR_SIZE_OFFS + MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) + + /* Clean interrupt cause*/ + MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) + + /* Clean error interrupt cause*/ + MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) + MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) + + /* Start transfer */ + MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + orr r6, r6, #0x1 /* Preform start command */ + MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + + /* Wait for engine to finish */ +waitForComplete: + MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) + and r6, r6, #2 + cmp r6, #0 + beq waitForComplete + + /* Clear all error report registers */ + MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) + MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) + + MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) + + cmp sp, #0 + beq no_stack_l1 +load_from_stack1: + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} +no_stack_l1: + mov pc, lr + + +/******************************************************************************* +* mvDramIfMemInit - Use XOR to clear all memory. +* +* DESCRIPTION: +* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV78XX0) + +_mvDramIfMemInit: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} + mov r6, LR /* Save link register */ + /* Check if dram bank 0 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) + and r3, r0, #SCSR_WIN_EN + cmp r3, #0 + beq no_bank_0 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) + cmp r0, #0 + beq no_bank_0 + mov r0,#0 + bl _mvDramIfEccMemInit + +no_bank_0: + /* Check if dram bank 1 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_1 + mov r0,#1 + bl _mvDramIfEccMemInit +no_bank_1: + /* Check if dram bank 2 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_2 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) + cmp r0, #0 + beq no_bank_2 + mov r0,#2 + bl _mvDramIfEccMemInit + +no_bank_2: + /* Check if dram bank 3 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_3 + mov r0,#3 + bl _mvDramIfEccMemInit +no_bank_3: + mov LR ,r6 /* restore link register */ + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} + mov pc, lr +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIf.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,186 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/* includes */ +#include "ctrlEnv/mvCtrlEnvSpec.h" +//#include "ddr2_3/mvDramIfRegs.h" +//#include "ddr2_3/mvDramIfConfig.h" +#include "mvSysDdrConfig.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ + +#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ +#define ECC_DISABLE 1 /* Force ECC to Disable */ +#define ECC_ENABLE 0 /* Force ECC to ENABLE */ + +/* typedefs */ +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +} MV_MEMORY_TYPE; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_6 = 0x40, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + MV_BOOL registeredDQMBinputs; + +}MV_DRAM_BANK_INFO; + +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +//#include "ddr2_3/spd/mvSpd.h" + +/* mvDramIf.h API list */ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk); +MV_VOID _mvDramIfConfig(int entryNum); + +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); +MV_U32 mvDramIfCalGet(void); +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); +MV_VOID mvDramIfSelfRefreshSet(void); +void mvDramIfShow(void); +MV_U32 mvDramIfGetFirstCS(void); +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); +MV_U32 mvDramCsSizeGet(MV_U32 csNum); +MV_VOID mvDdrPhyRegRead(MV_U8 regNum, MV_U8 pupNum, MV_U16 *value); +MV_VOID mvDdrPhyRegWrite(MV_U8 regNum, MV_U8 pupNum, MV_U16 value); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfRegs.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/mvDramIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/mvDramIfRegs.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,428 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" + +/* DDR SDRAM Controller Address Decode Registers */ + /* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCSR_SIZE_OFFS 24 +#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x1000000 +#define SCSR_WIN_EN BIT0 + +/* configuration register */ +#define SDRAM_CONFIG_REG (MV_DDR_REGS_BASE + 0x1400) +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3FFF +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 15 +#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_ECC_OFFS 18 +#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) +#define SDRAM_IERR_OFFS 19 +#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) +#define SDRAM_SRMODE_OFFS 24 +#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) + +/* dunit control low register */ +#define SDRAM_DUNIT_CTRL_REG (MV_DDR_REGS_BASE + 0x1404) +#define SDRAM_2T_OFFS 4 +#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) +#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) + +#define SDRAM_SRCLK_OFFS 5 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK2DRV_OFFS 13 +#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_SB_OUT_DEL_OFFS 20 +#define SDRAM_SB_OUT_DEL_MAX 0xf +#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / + pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || + (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) + { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + { + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + + if (MV_OK != mvSysDdrSpdRead(data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + for(i = 0 ; i < SPD_SIZE ; i++) + { + if( MV_OK != mvSysDdrSpdWrite(&data[i], 1) ) + { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_U8 data[SPD_SIZE]; + + if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + if( MV_OK != mvSysDdrSpdRead(data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure*/ + for(i = 0 ; i < SPD_SIZE ; i++) + { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) + { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", + pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", + pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", + pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", + pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", + pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", + pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", + pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", + pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", + pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", + pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", + pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", + pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", + pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", + pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", + pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", + pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", + pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", + pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * + pDimmInfo->numOfBanksOnEachDevice * + pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * + pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", + pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum, MV_U32 sysClock) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, + temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (sysClock / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) + { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) + { + mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); + } + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + } + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + } + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for(i = 0; i < sizeof(MV_U32); i++) + { + temp |= spdRawData[95+i] << 8*i; + } + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, + (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", + spdRawData[62]/10, spdRawData[62]%10); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for(i = 2 ; i <= 35 ; i++) + switch(i) + { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", + dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", + dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", + dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", + dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch(spdRawData[i]) + { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) + { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", + dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", + dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", + dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", + dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + mvOsOutput("Minimum Clk Delay back to back: %d\n", + spdRawData[i]); + } + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", + dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + for (k = 0; k <=7; k++) + { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k+1); + } + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } + else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", + ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if ( spdRawData[i] & BIT1 ) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if ( spdRawData[i] & BIT2 ) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if ( spdRawData[i] & BIT3 ) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if ( spdRawData[i] & BIT4 ) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if ( spdRawData[i] & BIT5 ) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if ( !(spdRawData[i] & BIT4) ) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if ( !(spdRawData[i] & BIT5) ) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if ( spdRawData[i] & BIT6 ) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if ( spdRawData[i] & BIT7 ) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ + trp_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trrd_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if( ns10 < 10 ) { + ns10 *= 10; + } + else if( ns10 == 10 ) + ns10 = 25; + else if( ns10 == 11 ) + ns10 = 33; + else if( ns10 == 12 ) + ns10 = 66; + else if( ns10 == 13 ) + ns10 = 75; + else + { + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + } + + return (ns*1000 + ns10*10); +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/spd/mvSpd.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/spd/mvSpd.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/bak/spd/mvSpd.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/bak/spd/mvSpd.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,199 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ddr2_3/mvDramIf.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 +#define DIMM_SPD_VERSION 62 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf +{ + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas +{ + SD_CL_1 =1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +}MV_DIMM_SDRAM_CAS; + + +/* DIMM information structure */ +typedef struct _mvDimmInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum, MV_U32 sysClock); +MV_STATUS dimmSpdCpy(MV_VOID); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCmvDram */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIf.c u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIf.c 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,431 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" +#include "ddr2_3/mvDramIf.h" +#include "mvDramIfRegs.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + MV_U32 result = 0; + + if(mvDramIfWinGet(SDRAM_CS0 + bankNum, &addrDecWin) == MV_OK) { + if(addrDecWin.enable == MV_TRUE) + result = addrDecWin.addrWin.size; + } + + DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", + bankNum, result)); + return result; +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 size = 0, i; + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + size += mvDramIfBankSizeGet(i); + + DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); + return size; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0, ctrlReg=0; + MV_U32 sizeToReg=0; + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + baseReg = MV_REG_READ(SDRAM_WIN_BASE_REG(target)); + ctrlReg = MV_REG_READ(SDRAM_WIN_CTRL_REG(target)); + + /* Write to address decode Base Address Register */ + baseReg &= ~SDRAMWBR_BASE_MASK; + baseReg |= (pAddrDecWin->addrWin.baseLow & SDRAMWBR_BASE_MASK); + + /* Translate the given window size to register format */ + sizeToReg = (pAddrDecWin->addrWin.size / SDRAMWCR_SIZE_ALLIGNMENT) - 1; + + /* set size */ + ctrlReg &= ~SDRAMWCR_SIZE_MASK; + ctrlReg |= (sizeToReg << SDRAMWCR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + ctrlReg |= SDRAMWCR_ENABLE; + else + ctrlReg &= ~SDRAMWCR_ENABLE; + + /* Set back registers */ + MV_REG_WRITE(SDRAM_WIN_BASE_REG(target), baseReg); + MV_REG_WRITE(SDRAM_WIN_CTRL_REG(target), ctrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_WIN_CTRL_REG(target)); + baseReg = MV_REG_READ(SDRAM_WIN_BASE_REG(target)); + + sizeRegVal = (sizeReg & SDRAMWCR_SIZE_MASK) >> SDRAMWCR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * SDRAMWCR_SIZE_ALLIGNMENT; + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SDRAMWBR_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + if (sizeReg & SDRAMWCR_ENABLE) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + if (enable == MV_TRUE) + { + /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_WIN_CTRL_REG(target), SDRAMWCR_ENABLE); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_WIN_CTRL_REG(target), SDRAMWCR_ENABLE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvDdrPhyRegRead - Read the content of a DDR PHY register +* +* DESCRIPTION: +* Perform register read of the indicated DDR Phy register +* +* INPUT: +* regNum: register offset +* pupNum: PUP number +* +* OUTPUT: +* value: 16bit register value +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvDdrPhyRegRead(MV_U8 regNum, MV_U8 pupNum, MV_U16 *value) +{ + MV_U32 regAddr; + MV_U32 reg; + + regAddr = (BIT31 | ((regNum & 0x3F) << 16) | ((pupNum & 0xF) << 22)); + MV_REG_WRITE(SDRAM_PHY_REGISTER_FILE_ACCESS, regAddr); + + do { + reg = MV_REG_READ(SDRAM_PHY_REGISTER_FILE_ACCESS); + } while ((reg & BIT31) != 0); + + *value = (reg & 0xFFFF); +} + +/******************************************************************************* +* mvDdrPhyRegWrite - Update the content of a DDR PHY register +* +* DESCRIPTION: +* Perform register write of the indicated DDR Phy register +* +* INPUT: +* regNum: register offset +* pupNum: PUP number +* value: 16bit register value +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvDdrPhyRegWrite(MV_U8 regNum, MV_U8 pupNum, MV_U16 value) +{ + MV_U32 regAddr; + MV_U32 reg; + + regAddr = (BIT31 | BIT30 | ((regNum & 0x3F) << 16) | ((pupNum & 0xF) << 22) | value); + MV_REG_WRITE(SDRAM_PHY_REGISTER_FILE_ACCESS, regAddr); + + do { + reg = MV_REG_READ(SDRAM_PHY_REGISTER_FILE_ACCESS); + } while ((reg & BIT31) != 0); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIf.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIf.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIf.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,186 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/* includes */ +#include "ctrlEnv/mvCtrlEnvSpec.h" +/*#include "ddr2_3/mvDramIfRegs.h" */ +/*#include "ddr2_3/mvDramIfConfig.h" */ +#include "mvSysDdrConfig.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ + +#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ +#define ECC_DISABLE 1 /* Force ECC to Disable */ +#define ECC_ENABLE 0 /* Force ECC to ENABLE */ + +/* typedefs */ +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +} MV_MEMORY_TYPE; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_6 = 0x40, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + MV_BOOL registeredDQMBinputs; + +}MV_DRAM_BANK_INFO; + +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +/* #include "ddr2_3/spd/mvSpd.h" */ + +/* mvDramIf.h API list */ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk); +MV_VOID _mvDramIfConfig(int entryNum); + +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); +MV_U32 mvDramIfCalGet(void); +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); +MV_VOID mvDramIfSelfRefreshSet(void); +void mvDramIfShow(void); +MV_U32 mvDramIfGetFirstCS(void); +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); +MV_U32 mvDramCsSizeGet(MV_U32 csNum); +MV_VOID mvDdrPhyRegRead(MV_U8 regNum, MV_U8 pupNum, MV_U16 *value); +MV_VOID mvDdrPhyRegWrite(MV_U8 regNum, MV_U8 pupNum, MV_U16 value); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIfRegs.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvDramIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvDramIfRegs.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,95 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysDdrConfig.h" + +#define SDRAM_WIN_BASE_REG(winNum) (MV_DDR_WIN_REGS_BASE + 0x180 + winNum * 0x8) +#define SDRAMWBR_BASE_OFFS 24 +#define SDRAMWBR_BASE_MASK (0xFF << SDRAMWBR_BASE_OFFS) +#define SDRAMWBR_BASE_ALIGNMENT 0x10000 + +#define SDRAM_WIN_CTRL_REG(winNum) (MV_DDR_WIN_REGS_BASE + 0x184 + winNum * 0x8) +#define SDRAMWCR_ENABLE BIT0 +#define SDRAMWCR_CS_OFFS 2 +#define SDRAMWCR_CS_MASK (0x7 << SDRAMWCR_CS_OFFS) +#define SDRAMWCR_SIZE_OFFS 24 +#define SDRAMWCR_SIZE_MASK (0xFF << SDRAMWCR_SIZE_OFFS) +#define SDRAMWCR_SIZE_ALLIGNMENT 0x1000000 + +/* sdram extended mode2 register (SEM2R) */ +#define SDRAM_PHY_REGISTER_FILE_ACCESS (MV_DDR_CTRL_REGS_BASE + 0x16A0) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvSysDdr.h u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvSysDdr.h --- u-boot-2009.08.orig/board/marvell/mv_hal/ddr2_3/mvSysDdr.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/ddr2_3/mvSysDdr.h 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,118 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSysDdr_h__ +#define __mvSysDdr_h__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* mvSysDdrSpdRead +* +* DESCRIPTION: +* System interface for reading DDR SPD contents. +* +* INPUT: +* data: Buffer to read data into. +* size: Number of bytes to read. +* +* OUTPUT: +* data: SPD data. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdRead(MV_U8 *data, MV_U32 size); + + +/******************************************************************************* +* mvSysDdrSpdWrite +* +* DESCRIPTION: +* System interface for writing DDR SPD contents. +* +* INPUT: +* data: Buffer holding the data to be written. +* size: Number of bytes to write. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdWrite(MV_U8 *data, MV_U32 size); + +#ifdef __cplusplus +} +#endif + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthAddrDec.c u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthAddrDec.c 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,449 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "../mvEth.h" +#include "mvEthRegs.h" + +MV_TARGET ethAddrDecPrioTab[] = { +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +#if defined(MV_INCLUDE_PEX) +#ifdef MV_INCLUDE_PEX0 + PEX0_IO, +#endif +#ifdef MV_INCLUDE_PEX1 + PEX1_IO, +#endif +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(MV_U32 port, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvEthWinInit +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the default +* address decode windows of the unit. +* +* INPUT: +* port : The port number to initialize the address decoding for. +* addWinMap: An array holding the address decoding information for the +* system. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +MV_STATUS mvEthWinInit(MV_U32 port, MV_UNIT_WIN_INFO *addrWinMap) +{ + MV_U32 winNum, winPrioIndex = 0, i, regVal = 0; + MV_UNIT_WIN_INFO *addrDecWin; + static MV_U32 accessProtReg; + +#if (MV_ETH_VERSION <= 1) + static MV_BOOL isFirst = MV_TRUE; + + if (isFirst == MV_FALSE) { + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + return MV_OK; + } + isFirst = MV_FALSE; +#endif /* MV_GIGA_ETH_VERSION */ + + /* Initiate Ethernet address decode */ + /* First disable all address decode windows */ + for (winNum = 0; winNum < ETH_MAX_DECODE_WIN; winNum++) + regVal |= MV_BIT_MASK(winNum); + + MV_REG_WRITE(ETH_BASE_ADDR_ENABLE_REG(port), regVal); + + /* Go through all windows in user table until table terminator */ + for (winNum = 0; ((ethAddrDecPrioTab[winPrioIndex] != TBL_TERM) && (winNum < ETH_MAX_DECODE_WIN));) { + addrDecWin = &addrWinMap[ethAddrDecPrioTab[winPrioIndex]]; + + if (addrDecWin->enable == MV_TRUE) { + if (MV_OK != mvEthWinWrite(port, winNum, addrDecWin)) { + mvOsPrintf("mvEthWinInit: ERR. mvEthWinWrite failed winNum=%d (%d, %d)\n", + winNum, winPrioIndex, ethAddrDecPrioTab[winPrioIndex]); + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + + /* set full access to all windows. */ + for (i = 0; i < winNum; i++) + accessProtReg |= (FULL_ACCESS << (i * 2)); + + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthWinWrite +* +* DESCRIPTION: +* This function writes the address decoding registers according to the +* given window configuration. +* +* INPUT: +* unit - The Ethernet unit number to configure. +* winNum - ETH target address decode window number. +* pAddrDecWin - ETH target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvEthWinWrite(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin) +{ + MV_U32 size, alignment; + MV_U32 baseReg, sizeReg; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvEthWinWrite: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d.\n" + "Address 0x%08x is unaligned to size 0x%x.\n", + winNum, pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + size = pAddrDecWin->addrWin.size; + if (!MV_IS_POWER_OF_2(size)) { + mvOsPrintf("mvEthWinWrite: Error setting AUDIO window %d. " "Window size is not a power to 2.", winNum); + return MV_BAD_PARAM; + } + + baseReg = (pAddrDecWin->addrWin.baseLow & ETH_WIN_BASE_MASK); + sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + /* set size */ + alignment = 1 << ETH_WIN_SIZE_OFFS; + sizeReg &= ~ETH_WIN_SIZE_MASK; + sizeReg |= (((size / alignment) - 1) << ETH_WIN_SIZE_OFFS); + + /* set attributes */ + baseReg &= ~ETH_WIN_ATTR_MASK; + baseReg |= pAddrDecWin->attrib << ETH_WIN_ATTR_OFFS; + + /* set target ID */ + baseReg &= ~ETH_WIN_TARGET_MASK; + baseReg |= pAddrDecWin->targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvEthWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + mvEthWinEnable(port, winNum, MV_TRUE); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(MV_U32 port, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_UNIT_WIN_INFO addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex = 0; winNumIndex < ETH_MAX_DECODE_WIN; winNumIndex++) { + /* Do not check window itself */ + if (winNumIndex == winNum) + continue; + + /* Do not check disabled windows */ + if (baseAddrEnableReg & (1 << winNumIndex)) + continue; + + /* Get window parameters */ + if (MV_OK != mvEthWinRead(port, winNumIndex, &addrDecWin)) { + mvOsPrintf("ethWinOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvEthWinRead +* +* DESCRIPTION: +* Read Ethernet peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvEthWinRead(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin) +{ + MV_U32 baseReg, sizeReg; + MV_U32 alignment, size; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + alignment = 1 << ETH_WIN_SIZE_OFFS; + size = (sizeReg & ETH_WIN_SIZE_MASK) >> ETH_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (size + 1) * alignment; + + /* Extract base address */ + pAddrDecWin->addrWin.baseLow = baseReg & ETH_WIN_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + /* attrib and targetId */ + pAddrDecWin->attrib = (baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + pAddrDecWin->targetId = (baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum)) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + return MV_OK; +} + +/******************************************************************************* +* mvEthWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvEthWinEnable(MV_U32 port, MV_U32 winNum, MV_BOOL enable) +{ + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n", winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) { + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } else { + /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvEthProtWinSet - Set access protection of Ethernet to target window. +* +* DESCRIPTION: +* Each Ethernet port can be configured with access attributes for each +* of the Ethenret to target windows (address decode windows). This +* function sets access attributes to a given window for the given channel. +* +* INPUTS: +* ethPort - ETH channel number. See MV_ETH_CHANNEL enumerator. +* winNum - IETH to target address decode window number. +* access - IETH access rights. See MV_ACCESS_RIGHTS enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case window number is invalid or access right reserved. +* +*******************************************************************************/ +MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS access) +{ + MV_U32 protReg; + + /* Parameter checking */ + if (portNo >= MV_ETH_MAX_PORTS) { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n", winNum); + return MV_ERROR; + } + + if ((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) { + mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEth.c u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEth.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEth.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEth.c 2011-04-04 13:57:34.965596912 -0400 @@ -0,0 +1,2739 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.c - Marvell's Gigabit Ethernet controller low level driver +* +* DESCRIPTION: +* This file introduce OS independent APIs to Marvell's Gigabit Ethernet +* controller. This Gigabit Ethernet Controller driver API controls +* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). +* 2) Data flow (i.e. port Send, Receive etc'). +* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) +* 4) MIB counters support (ethReadMibCounter) +* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) +* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. +* This struct includes configuration information as well as driver +* internal data needed for its operations. +* +* Supported Features: +* - OS independent. All required OS services are implemented via external +* OS dependent components (like osLayer or ethOsg) +* - The user is free from Rx/Tx queue managing. +* - Simple Gigabit Ethernet port operation API. +* - Simple Gigabit Ethernet port data flow API. +* - Data flow and operation API support per queue functionality. +* - Support cached descriptors for better performance. +* - PHY access and control API. +* - Port Configuration API. +* - Full control over Special and Other Multicast MAC tables. +* +*******************************************************************************/ +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysEthConfig.h" +#include "mvEthRegs.h" +#include "eth/mvEth.h" +#include "mvEthGbe.h" + +#ifdef MV_RT_DEBUG +# define ETH_DEBUG +#endif + +/* locals */ +MV_BOOL ethDescInSram; +MV_BOOL ethDescSwCoher; +MV_ETH_HAL_DATA ethHalData; + +/* This array holds the control structure of each port */ +ETH_PORT_CTRL *ethPortCtrl[MV_ETH_MAX_PORTS]; + +/* Ethernet Port Local routines */ + +static void ethInitRxDescRing(ETH_PORT_CTRL *pPortCtrl, int queue); + +static void ethInitTxDescRing(ETH_PORT_CTRL *pPortCtrl, int queue); + +static void ethSetUcastTable(int portNo, int queue); + +static MV_BOOL ethSetUcastAddr(int ethPortNum, MV_U8 lastNibble, int queue); +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); + +static void ethFreeDescrMemory(ETH_PORT_CTRL *pEthPortCtrl, MV_BUF_INFO *pDescBuf); +static MV_U8 *ethAllocDescrMemory(ETH_PORT_CTRL *pEthPortCtrl, int size, MV_ULONG * pPhysAddr, MV_U32 *memHandle); + +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); + +static void mvEthPortSgmiiConfig(int port); + +/******************************************************************************/ +/* EthDrv Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthHalInit - Initialize the Giga Ethernet unit +* +* DESCRIPTION: +* This function initialize the Giga Ethernet unit. +* 1) Configure Address decode windows of the unit +* 2) Set registers to HW default values. +* 3) Clear and Disable interrupts +* +* INPUT: NONE +* +* RETURN: NONE +* +* NOTE: this function is called once in the boot process. +*******************************************************************************/ +void mvEthHalInit(MV_ETH_HAL_DATA *halData) +{ + int port; + + mvOsMemcpy(ðHalData, halData, sizeof(MV_ETH_HAL_DATA)); + + /* Init static data structures */ + for (port = 0; port < MV_ETH_MAX_PORTS; port++) + ethPortCtrl[port] = NULL; + /* Power down all existing ports */ + for (port = 0; port < ethHalData.maxPortNum; port++) { + if (ethHalData.portData[port].powerOn == MV_FALSE) + continue; +#if defined(MV78200) + /* Skip ports mapped to another CPU */ + if (MV_FALSE == mvSocUnitIsMappedToThisCpu(GIGA0 + port)) + continue; +#endif + + /* Disable Giga Ethernet Unit interrupts */ + MV_REG_WRITE(ETH_UNIT_INTR_MASK_REG(port), 0); + + /* Clear ETH_UNIT_INTR_CAUSE_REG register */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + + } + + mvEthMemAttrGet(ðDescInSram, ðDescSwCoher); + +#if defined(ETH_DESCR_IN_SRAM) + if (ethDescInSram == MV_FALSE) + mvOsPrintf("ethDrv: WARNING! Descriptors will be allocated in DRAM instead of SRAM.\n"); +#endif /* ETH_DESCR_IN_SRAM */ +} + +/******************************************************************************* +* mvEthMemAttrGet - Define properties (SRAM/DRAM, SW_COHER / HW_COHER / UNCACHED) +* of of memory location for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, allocate from SRAM memory. +* - If ETH_DESCR_IN_SDRAM defined, allocate from SDRAM memory. +* +* INPUT: +* MV_BOOL* pIsSram - place of descriptors: +* MV_TRUE - in SRAM +* MV_FALSE - in DRAM +* MV_BOOL* pIsSwCoher - cache coherency of descriptors: +* MV_TRUE - driver is responsible for cache coherency +* MV_FALSE - driver is not responsible for cache coherency +* +* RETURN: +* +*******************************************************************************/ +void mvEthMemAttrGet(MV_BOOL *pIsSram, MV_BOOL *pIsSwCoher) +{ + MV_BOOL isSram, isSwCoher; + + isSram = MV_FALSE; + +#ifdef CONFIG_HW_CACHE_COHERENCY + isSwCoher = MV_FALSE; +#else + isSwCoher = MV_TRUE; +#endif + +#if defined(ETH_DESCR_IN_SRAM) + if (ethHalData.sramSize > 0) { + isSram = MV_TRUE; +#if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) + isSwCoher = MV_TRUE; +#else + isSwCoher = MV_FALSE; +#endif + } +#endif /* ETH_DESCR_IN_SRAM */ + + if (pIsSram != NULL) + *pIsSram = isSram; + + if (pIsSwCoher != NULL) + *pIsSwCoher = isSwCoher; +} + +/******************************************************************************/ +/* Port Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthPortInit - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function initialize the ethernet port. +* 1) Allocate and initialize internal port Control structure. +* 2) Create RX and TX descriptor rings for default RX and TX queues +* 3) Disable RX and TX operations, clear cause registers and +* mask all interrupts. +* 4) Set all registers to default values and clean all MAC tables. +* +* INPUT: +* int portNo - Ethernet port number +* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure +* +* RETURN: +* void* - ethernet port handler, that should be passed to the most other +* functions dealing with this port. +* +* NOTE: This function is called once per port when loading the eth module. +*******************************************************************************/ +void *mvEthPortInit(int portNo, MV_ETH_PORT_INIT * pEthPortInit) +{ + int queue, descSize; + ETH_PORT_CTRL *pPortCtrl; + + /* Check validity of parameters */ + if ((portNo >= (int)ethHalData.maxPortNum) || (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM)) { + mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); + return NULL; + } + if ((pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) { + mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", portNo, pEthPortInit->rxDefQ); + return NULL; + } + + pPortCtrl = (ETH_PORT_CTRL *) mvOsMalloc(sizeof(ETH_PORT_CTRL)); + if (pPortCtrl == NULL) { + mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", + (int)sizeof(ETH_PORT_CTRL), portNo); + return NULL; + } + + memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL)); + ethPortCtrl[portNo] = pPortCtrl; + + pPortCtrl->portState = MV_UNDEFINED_STATE; + + pPortCtrl->portNo = portNo; + + pPortCtrl->osHandle = pEthPortInit->osHandle; + + /* Copy Configuration parameters */ + pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; + pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; + pPortCtrl->portConfig.ejpMode = 0; + + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) + pPortCtrl->rxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) + pPortCtrl->txQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; + + mvEthPortDisable(pPortCtrl); + + /* Set the board information regarding PHY address */ + mvEthPhyAddrSet(pPortCtrl, ethHalData.portData[portNo].phyAddr); +#if 0 + /* TODO: alior: seems like it's not need anymore*/ + if (portNo < 2) { + printf("restart AN\n\n"); + mvEthPhyRestartAN(portNo, 0); + } +#endif + /* Create all requested RX queues */ + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) { + if (pPortCtrl->rxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for RX descriptors */ + descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->rxQueue[queue].descBuf.memHandle); + pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; + if (pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) { + mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", + pPortCtrl->portNo, queue, descSize, + ethDescInSram ? "SRAM" : "DRAM", pPortCtrl->rxQueueConfig[queue].descrNum); + return NULL; + } + + ethInitRxDescRing(pPortCtrl, queue); + } + /* Create TX queues */ + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) { + if (pPortCtrl->txQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for TX descriptors */ + descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->txQueue[queue].descBuf.memHandle); + pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; + if (pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) { + mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", + pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->txQueueConfig[queue].descrNum); + return NULL; + } + + ethInitTxDescRing(pPortCtrl, queue); + } + mvEthDefaultsSet(pPortCtrl); + + pPortCtrl->portState = MV_IDLE; + return pPortCtrl; +} + +/******************************************************************************* +* ethPortFinish - Finish the Ethernet port driver +* +* DESCRIPTION: +* This function finish the ethernet port. +* 1) Down ethernet port if needed. +* 2) Delete RX and TX descriptor rings for all created RX and TX queues +* 3) Free internal port Control structure. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: NONE. +* +*******************************************************************************/ +void mvEthPortFinish(void *pPortHndl) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + int queue, portNo = pPortCtrl->portNo; + + if (pPortCtrl->portState == MV_ACTIVE) { + mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", portNo); + mvEthPortDisable(pPortHndl); + } + + /* Free all allocated RX queues */ + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) + ethFreeDescrMemory(pPortCtrl, &pPortCtrl->rxQueue[queue].descBuf); + /* Free all allocated TX queues */ + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) + ethFreeDescrMemory(pPortCtrl, &pPortCtrl->txQueue[queue].descBuf); + + /* Free port control structure */ + mvOsFree(pPortCtrl); + + ethPortCtrl[portNo] = NULL; +} + +/******************************************************************************* +* mvEthDefaultsSet - Set defaults to the ethernet port +* +* DESCRIPTION: +* This function set default values to the ethernet port. +* 1) Clear Cause registers and Mask all interrupts +* 2) Clear all MAC tables +* 3) Set defaults to all registers +* 4) Reset all created RX and TX descriptors ring +* 5) Reset PHY +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* NOTE: +* This function update all the port configuration except those set +* Initialy by the OsGlue by MV_ETH_PORT_INIT. +* This function can be called after portDown to return the port setting +* to defaults. +*******************************************************************************/ +MV_STATUS mvEthDefaultsSet(void *pPortHndl) +{ + int ethPortNo, queue; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_U32 txPrio; + MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; + MV_ETH_MAC_SPEED boardMacCfg; + + ethPortNo = pPortCtrl->portNo; + + /* Clear Cause registers */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo), 0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo), 0); + + /* Mask all interrupts */ + MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo), 0); + MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo), 0); + + portCfgReg = PORT_CONFIG_VALUE; + portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; + + boardMacCfg = ethHalData.portData[ethPortNo].macSpeed; + + if (boardMacCfg == ETH_MAC_SPEED_100M) + portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; + else if (boardMacCfg == ETH_MAC_SPEED_1000M) + portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; + else + portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; + + /* build PORT_SDMA_CONFIG_REG */ + portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); + portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); + +#ifdef CONFIG_HW_CACHE_COHERENCY + /* some devices have restricted RX burst size when using HW coherency */ + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); +#else + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); +#endif + +#if defined(MV_CPU_BE) + /* big endian */ +# if defined(MV_ARM) + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ETH_TX_NO_DATA_SWAP_MASK | ETH_DESC_SWAP_MASK); +# elif defined(MV_PPC) + portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | ETH_TX_DATA_SWAP_MASK | ETH_NO_DESC_SWAP_MASK); +# else +# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" +# endif /* MV_ARM / MV_PPC */ + +#else /* MV_CPU_LE */ + /* little endian */ + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ETH_TX_NO_DATA_SWAP_MASK | ETH_NO_DESC_SWAP_MASK); +#endif /* MV_CPU_BE / MV_CPU_LE */ + + pPortCtrl->portRxQueueCmdReg = 0; + pPortCtrl->portTxQueueCmdReg = 0; + +#if (MV_ETH_VERSION >= 4) + if (pPortCtrl->portConfig.ejpMode == MV_TRUE) { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); + } else { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0); + } +#endif /* (MV_ETH_VERSION >= 4) */ + + ethSetUcastTable(ethPortNo, -1); + mvEthSetSpecialMcastTable(ethPortNo, -1); + mvEthSetOtherMcastTable(ethPortNo, -1); + + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + /* Update value of PortConfig register accordingly with all RxQueue types */ + pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; + + portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); + + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + /* Assignment of Tx CTRP of given queue */ + txPrio = 0; + + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) { + pQueueCtrl = &pPortCtrl->txQueue[queue]; + + if (pQueueCtrl->pFirstDescr != NULL) { + ethResetTxDescRing(pPortCtrl, queue); + + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x3fffffff); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x03ffffff); + } else { + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); + } + } + + /* Assignment of Rx CRDP of given queue */ + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) + ethResetRxDescRing(pPortCtrl, queue); + + /* Allow receiving packes with odd number of preamble nibbles */ + portSerialCtrl1Reg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(ethPortNo)); + portSerialCtrl1Reg |= ETH_EN_MII_ODD_PRE_MASK; + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(ethPortNo), portSerialCtrl1Reg); + + /* Assign port configuration and command. */ + MV_REG_WRITE(ETH_PORT_CONFIG_REG(ethPortNo), portCfgReg); + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(ethPortNo), portCfgExtReg); + + /* Assign port SDMA configuration */ + MV_REG_WRITE(ETH_SDMA_CONFIG_REG(ethPortNo), portSdmaCfgReg); + + /* Turn off the port/queue bandwidth limitation */ + MV_REG_WRITE(ETH_MAX_TRANSMIT_UNIT_REG(ethPortNo), 0x0); + + return MV_OK; +} + +/******************************************************************************* +* ethPortUp - Start the Ethernet port RX and TX activity. +* +* DESCRIPTION: +* This routine start Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link up. +*******************************************************************************/ +MV_STATUS mvEthPortUp(void *pEthPortHndl) +{ + int ethPortNo; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + + ethPortNo = pPortCtrl->portNo; + + if ((pPortCtrl->portState != MV_ACTIVE) && (pPortCtrl->portState != MV_PAUSED)) { + mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", ethPortNo, pPortCtrl->portState); + return MV_BAD_STATE; + } + + ethPortNo = pPortCtrl->portNo; + + /* WA for incompatability of NETA unit in legacy mode */ + { + int queue; + ETH_QUEUE_CTRL *pQueueCtrl; + + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) { + pQueueCtrl = &pPortCtrl->rxQueue[queue]; + + if (pQueueCtrl->pFirstDescr != NULL) { + MV_REG_WRITE(ETH_RX_CUR_DESC_PTR_REG(ethPortNo, queue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr)); + } + } + } + + /* Enable port RX. */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); + + /* Enable port TX. */ +/* MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; */ + + pPortCtrl->portState = MV_ACTIVE; + + return MV_OK; +} + +/******************************************************************************* +* ethPortDown - Stop the Ethernet port activity. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link down. +*******************************************************************************/ +MV_STATUS mvEthPortDown(void *pEthPortHndl) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int uDelay, mDelay; + + /* Stop Rx port activity. Check port Rx activity. */ + regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; + if (regData != 0) { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); + } + + /* Stop Tx port activity. Check port Tx activity. */ + regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; + if (regData != 0) { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_TXQ_DISABLE_OFFSET)); + } + + /* Force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait for all Rx activity to terminate. */ + mDelay = 0; + do { + if (mDelay >= RX_DISABLE_TIMEOUT_MSEC) { + mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port RX Command register that all Rx queues are stopped */ + regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); + } while (regData & 0xFF); + + /* Wait for all Tx activity to terminate. */ + mDelay = 0; + do { + if (mDelay >= TX_DISABLE_TIMEOUT_MSEC) { + mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port TX Command register that all Tx queues are stopped */ + regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); + } while (regData & 0xFF); + + /* Double check to Verify that TX FIFO is Empty */ + mDelay = 0; + while (MV_TRUE) { + do { + if (mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) { + mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + } while (((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || ((regData & ETH_TX_IN_PROGRESS_MASK) != 0)); + + if (mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + break; + + /* Double check */ + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + if (((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && ((regData & ETH_TX_IN_PROGRESS_MASK) == 0)) { + break; + } else + mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", + ethPortNum, mDelay, regData); + } + + /* Do NOT force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait about 2500 tclk cycles */ + uDelay = (PORT_DISABLE_WAIT_TCLOCKS / (ethHalData.tclk / 1000000)); + mvOsUDelay(uDelay); + + pPortCtrl->portState = MV_PAUSED; + + return MV_OK; +} + +/******************************************************************************* +* ethPortEnable - Enable the Ethernet port and Start RX and TX. +* +* DESCRIPTION: +* This routine enable the Ethernet port and Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to enable the port after ifconfig up. +*******************************************************************************/ +MV_STATUS mvEthPortEnable(void *pEthPortHndl) +{ + int ethPortNo; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + MV_U32 portSerialCtrlReg; + + ethPortNo = pPortCtrl->portNo; + + /* Enable port */ + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); + portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + mvEthMibCountersClear(pEthPortHndl); + + pPortCtrl->portState = MV_PAUSED; + + /* If Link is UP, Start RX and TX traffic */ + if (MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNo)) & ETH_LINK_UP_MASK) + return (mvEthPortUp(pEthPortHndl)); + + return MV_NOT_READY; +} + +/******************************************************************************* +* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to disable the port after ifconfig down. +*******************************************************************************/ +MV_STATUS mvEthPortDisable(void *pEthPortHndl) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int mvDelay; + + if (pPortCtrl->portState == MV_ACTIVE) { + /* Stop RX and TX activities */ + mvEthPortDown(pEthPortHndl); + } + + /* Reset the Enable bit in the Serial Control Register */ + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_PORT_ENABLE_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); + + /* Wait about 2500 tclk cycles */ + mvDelay = (PORT_DISABLE_WAIT_TCLOCKS * (ethHalData.cpuPclk / ethHalData.tclk)); + for (mvDelay; mvDelay > 0; mvDelay--) + ; + + pPortCtrl->portState = MV_IDLE; + return MV_OK; +} + +/******************************************************************************* +* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Tx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of TX queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pPktInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO *mvEthPortForceTxDone(void *pEthPortHndl, int txQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_PKT_INFO *pPktInfo; + ETH_TX_DESC *pTxDesc; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + while ((pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || (pQueueCtrl->resource == 0)) { + /* Free next descriptor */ + pQueueCtrl->resource++; + pTxDesc = (ETH_TX_DESC *) pQueueCtrl->pUsedDescr; + + /* pPktInfo is available only in descriptors which are last descriptors */ + pPktInfo = (MV_PKT_INFO *) pTxDesc->returnInfo; + if (pPktInfo) + pPktInfo->status = pTxDesc->cmdSts; + + pTxDesc->cmdSts = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + + if (pPktInfo) + if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) + return pPktInfo; + } + MV_REG_WRITE(ETH_TX_CUR_DESC_PTR_REG(port, txQueue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr)); + return NULL; +} + +/******************************************************************************* +* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pBufInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO *mvEthPortForceRx(void *pEthPortHndl, int rxQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + ETH_RX_DESC *pRxDesc; + MV_PKT_INFO *pPktInfo; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if (pQueueCtrl->resource == 0) { + MV_REG_WRITE(ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr)); + + return NULL; + } + /* Free next descriptor */ + pQueueCtrl->resource--; + pRxDesc = (ETH_RX_DESC *) pQueueCtrl->pCurrentDescr; + pPktInfo = (MV_PKT_INFO *) pRxDesc->returnInfo; + + pPktInfo->status = pRxDesc->cmdSts; + pRxDesc->cmdSts = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + return pPktInfo; +} + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ +/******************************************************************************* +* mvEthMruGet - Get MRU configuration for Max Rx packet size. +* +* INPUT: +* MV_U32 maxRxPktSize - max packet size. +* +* RETURN: MV_U32 - MRU configuration. +* +*******************************************************************************/ +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) +{ + MV_U32 portSerialCtrlReg = 0; + + if (maxRxPktSize > 9192) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; + else if (maxRxPktSize > 9022) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; + else if (maxRxPktSize > 1552) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; + else if (maxRxPktSize > 1522) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; + else if (maxRxPktSize > 1518) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; + else + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; + + return portSerialCtrlReg; +} + +/******************************************************************************* +* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path +* +* DESCRIPTION: +* This routine sets the RX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvEthRxCoalSet(void *pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + MV_U32 coal = ((uSec * (ethHalData.tclk / 1000000)) / 64); + MV_U32 portSdmaCfgReg; + + portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; + + portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); + +#if (MV_ETH_VERSION >= 2) + /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ + if (ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) + portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; +#endif /* MV_ETH_VERSION >= 2 */ + + MV_REG_WRITE(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); + return coal; +} + +/******************************************************************************* +* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path +* +* DESCRIPTION: +* This routine sets the TX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt +* occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_U32 mvEthTxCoalSet(void *pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + MV_U32 coal = ((uSec * (ethHalData.tclk / 1000000)) / 64); + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; + regVal |= ETH_TX_INTR_COAL_MASK(coal); + + /* Set TX Coalescing mechanism */ + MV_REG_WRITE(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); + return coal; +} + +/******************************************************************************* +* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds +* +* DESCRIPTION: +* This routine gets the RX and TX coalescing interrupt values. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the returned numbers are in micro seconds. +* +* INPUTs: +* void* pPortHndl - Ethernet Port handler. +* +* OUTPUTs: +* MV_U32* pRxCoal - Number of micro seconds between RX interrupts +* MV_U32* pTxCoal - Number of micro seconds between TX interrupts +* +* RETURN: +* MV_STATUS MV_OK - success +* Others - failure. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_STATUS mvEthCoalGet(void *pPortHndl, MV_U32 * pRxCoal, MV_U32 * pTxCoal) +{ + MV_U32 regVal, coal, usec; + + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + + /* get TX Coalescing */ + regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); + + usec = (coal * 64) / (ethHalData.tclk / 1000000); + if (pTxCoal != NULL) + *pTxCoal = usec; + + /* Get RX Coalescing */ + regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); + +#if (MV_ETH_VERSION >= 2) + if (regVal & ETH_RX_INTR_COAL_MSB_MASK) { + /* Add MSB */ + coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); + } +#endif /* MV_ETH_VERSION >= 2 */ + + usec = (coal * 64) / (ethHalData.tclk / 1000000); + if (pRxCoal != NULL) + *pRxCoal = usec; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* after next call of ethPortSetDefaults() function. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvEthMaxRxSizeSet(void *pPortHndl, int maxRxSize) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + MV_U32 portSerialCtrlReg; + + pPortCtrl->portConfig.maxRxPktSize = maxRxSize; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************/ +/* MAC Filtering functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* MV_BOOL isPromisc - Promiscous mode +* MV_TRUE - accept all Broadcast, Multicast +* and Unicast packets +* MV_FALSE - accept all Broadcast, +* specially added Multicast and +* single Unicast packets +* +* RETURN: MV_STATUS MV_OK - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthRxFilterModeSet(void *pEthPortHndl, MV_BOOL isPromisc) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + int queue; + MV_U32 portCfgReg; + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + /* Set / Clear UPM bit in port configuration register */ + if (isPromisc) { + /* Accept all multicast packets to RX default queue */ + queue = pPortCtrl->portConfig.rxDefQ; + portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; + memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), 0xFFFF); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), 0xFFFFFFFF); + } else { + /* Reject all Multicast addresses */ + queue = -1; + portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; + /* Clear all mcastCount */ + memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); + } + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + /* Set Special Multicast and Other Multicast tables */ + mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); + mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); + ethSetUcastTable(pPortCtrl->portNo, queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrSet - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. This address +* will be used to send Pause frames if enabled. Packets with this +* address will be accepted and dispatched to default RX queue +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* char* pAddr - Address to be set +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrSet(void *pPortHndl, unsigned char *pAddr, int queue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + unsigned int macH; + unsigned int macL; + + if (queue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); + return MV_BAD_PARAM; + } + + if (queue != -1) { + macL = (pAddr[4] << 8) | (pAddr[5]); + macH = (pAddr[0] << 24) | (pAddr[1] << 16) | (pAddr[2] << 8) | (pAddr[3] << 0); + + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); + } + + /* Accept frames of this address */ + ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrGet - This function returns the port Unicast address. +* +* DESCRIPTION: +* This function returns the port Ethernet MAC address. +* +* INPUT: +* int portNo - Ethernet port number. +* char* pAddr - Pointer where address will be written to +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) +{ + unsigned int macH; + unsigned int macL; + + if (pAddr == NULL) { + mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); + return MV_BAD_PARAM; + } + + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); + pAddr[0] = (macH >> 24) & 0xff; + pAddr[1] = (macH >> 16) & 0xff; + pAddr[2] = (macH >> 8) & 0xff; + pAddr[3] = macH & 0xff; + pAddr[4] = (macL >> 8) & 0xff; + pAddr[5] = macL & 0xff; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. +* +* DESCRIPTION: +* +* INPUT: +* MV_U8* pAddr - Address to calculate CRC-8 +* +* RETURN: MV_U8 - CRC-8 of this MAC address +* +*******************************************************************************/ +MV_U8 mvEthMcastCrc8Get(MV_U8 *pAddr) +{ + unsigned int macH; + unsigned int macL; + int macArray[48]; + int crc[8]; + int i; + unsigned char crcResult = 0; + + /* Calculate CRC-8 out of the given address */ + macH = (pAddr[0] << 8) | (pAddr[1]); + macL = (pAddr[2] << 24) | (pAddr[3] << 16) | (pAddr[4] << 8) | (pAddr[5] << 0); + + for (i = 0; i < 32; i++) + macArray[i] = (macL >> i) & 0x1; + + for (i = 32; i < 48; i++) + macArray[i] = (macH >> (i - 32)) & 0x1; + + crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ + macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ + macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ + macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ + macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; + + crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ + macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ + macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ + macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ + macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ + macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; + + crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ + macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ + macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ + macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ + macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ + macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; + + crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ + macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ + macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ macArray[3] ^ macArray[2] ^ macArray[1]; + + crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ + macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ + macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ + macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ macArray[3] ^ macArray[2]; + + crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ + macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ + macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ + macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ macArray[4] ^ macArray[3]; + + crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ + macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ + macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ + macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ macArray[4]; + + crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ + macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ + macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ + macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ + macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; + + for (i = 0; i < 8; i++) + crcResult = crcResult | (crc[i] << i); + + return crcResult; +} + +/******************************************************************************* +* mvEthMcastAddrSet - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls ethPortSmcAddr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* ethPortOmcAddr() routine to set the Other Multicast Table. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* MV_U8* pAddr - Address to be set +* int queue - RX queue to capture all packets with this +* Multicast MAC address. +* -1 means delete this Multicast address. +* +* RETURN: MV_STATUS +* MV_TRUE - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthMcastAddrSet(void *pPortHndl, MV_U8 * pAddr, int queue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + unsigned char crcResult = 0; + + if (queue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", pPortCtrl->portNo, queue); + return MV_BAD_PARAM; + } + + if ((pAddr[0] == 0x01) && (pAddr[1] == 0x00) && (pAddr[2] == 0x5E) && (pAddr[3] == 0x00) && (pAddr[4] == 0x00)) { + ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); + } else { + crcResult = mvEthMcastCrc8Get(pAddr); + + /* Check Add counter for this CRC value */ + if (queue == -1) { + if (pPortCtrl->mcastCount[crcResult] == 0) { + mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_SUCH; + } + + pPortCtrl->mcastCount[crcResult]--; + if (pPortCtrl->mcastCount[crcResult] != 0) { + mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], (unsigned)crcResult); + return MV_NO_CHANGE; + } + } else { + pPortCtrl->mcastCount[crcResult]++; + if (pPortCtrl->mcastCount[crcResult] > 1) { + mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); + } + return MV_OK; +} + +/******************************************************************************* +* ethSetUcastTable - Unicast address settings. +* +* DESCRIPTION: +* Set all entries in the Unicast MAC Table queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +static void ethSetUcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if (queue == -1) { + regValue = 0; + } else { + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* mvEthSetSpecialMcastTable - Special Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if (queue == -1) { + regValue = 0; + } else { + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xFC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + offset), regValue); + +} + +/******************************************************************************* +* mvEthSetOtherMcastTable - Other Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if (queue == -1) { + regValue = 0; + } else { + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xFC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* ethSetUcastAddr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* int ethPortNum - Port number. +* MV_U8 lastNibble - Unicast MAC Address last nibble. +* int queue - Rx queue number for this MAC address. +* value "-1" means remove address +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) +{ + unsigned int unicastReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the Unicast table entry */ + lastNibble = (0xf & lastNibble); + tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base */ + regOffset = lastNibble % 4; /* Entry offset within the above register */ + + unicastReg = MV_REG_READ((ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified unicast DA table entry */ + unicastReg &= ~(0xFF << (8 * regOffset)); + } else { + unicastReg &= ~(0xFF << (8 * regOffset)); + unicastReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), unicastReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetSpecialMcastAddr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* int ethPortNum Port number. +* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). +* int queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) +{ + unsigned int smcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the SMC table entry */ + tblOffset = (lastByte / 4); /* Register offset from SMC table base */ + regOffset = lastByte % 4; /* Entry offset within the above register */ + + smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset * 4)); + + if (queue == -1) { + /* Clear accepts frame bit at specified Special DA table entry */ + smcTableReg &= ~(0xFF << (8 * regOffset)); + } else { + smcTableReg &= ~(0xFF << (8 * regOffset)); + smcTableReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset * 4), smcTableReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetOtherMcastAddr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* int ethPortNum Port number. +* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* int queue Rx queue number for this MAC address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) +{ + unsigned int omcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the OMC table entry */ + tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + regOffset = crc8 % 4; /* Entry offset within the above register */ + + omcTableReg = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified Other DA table entry */ + omcTableReg &= ~(0xFF << (8 * regOffset)); + } else { + omcTableReg &= ~(0xFF << (8 * regOffset)); + omcTableReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), omcTableReg); + + return MV_TRUE; +} + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthMibCounterRead - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or +* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, +* so pHigh32 pointer should not be NULL in this case. +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* unsigned int mibOffset - MIB counter offset. +* +* OUTPUT: +* MV_U32* pHigh32 - pointer to place where 32 most significant bits +* of the counter will be stored. +* +* RETURN: +* 32 low sgnificant bits of MIB counter value. +* +*******************************************************************************/ +MV_U32 mvEthMibCounterRead(void *pPortHandle, unsigned int mibOffset, MV_U32 * pHigh32) +{ + int portNo; + MV_U32 valLow32, valHigh32; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + + portNo = pPortCtrl->portNo; + + valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); + + /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ + /* of a 64-bit MIB Counter. */ + if ((mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW)) { + valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); + if (pHigh32 != NULL) + *pHigh32 = valHigh32; + } + return valLow32; +} + +/******************************************************************************* +* mvEthMibCountersClear - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* +* +* RETURN: void +* +*******************************************************************************/ +void mvEthMibCountersClear(void *pPortHandle) +{ + int i, portNo; + unsigned int dummy; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + + portNo = pPortCtrl->portNo; + + /* Perform dummy reads from MIB counters */ + for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) + dummy = MV_REG_READ((ETH_MIB_COUNTERS_BASE(portNo) + i)); +} + +/******************************************************************************/ +/* RX Dispatching configuration routines */ +/******************************************************************************/ + +int mvEthTosToRxqGet(void *pPortHandle, int tos) +{ + MV_U32 regValue; + int regIdx, regOffs, rxq; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + + if (tos > 0xFF) { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return -1; + } + regIdx = mvOsDivide(tos >> 2, 10); + regOffs = mvOsReminder(tos >> 2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx)); + rxq = (regValue >> (regOffs * 3)); + rxq &= 0x7; + + return rxq; +} + +/******************************************************************************* +* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tos - TOS value in the IP header of the packet +* int rxq - RX Queue for packets with the configured TOS value +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +*******************************************************************************/ +MV_STATUS mvEthTosToRxqSet(void *pPortHandle, int tos, int rxq) +{ + MV_U32 regValue; + int regIdx, regOffs; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + + if ((rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM)) { + mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); + return MV_BAD_PARAM; + } + if (tos > 0xFF) { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return MV_BAD_PARAM; + } + regIdx = mvOsDivide(tos >> 2, 10); + regOffs = mvOsReminder(tos >> 2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx)); + regValue &= ~(0x7 << (regOffs * 3)); + regValue |= (rxq << (regOffs * 3)); + + MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); + return MV_OK; +} + +/******************************************************************************* +* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with +* special priority bits [0-2] +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture VLAN tagged packets with special +* priority. +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthVlanPrioRxQueue(void *pPortHandle, int vlanPrio, int vlanPrioQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + MV_U32 vlanPrioReg; + + if (vlanPrioQueue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); + return MV_BAD_PARAM; + } + if (vlanPrio >= 8) { + mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); + return MV_BAD_PARAM; + } + + vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); + vlanPrioReg &= ~(0x7 << (vlanPrio * 3)); + vlanPrioReg |= (vlanPrioQueue << (vlanPrio * 3)); + MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. +* +* DESCRIPTION: +* This function defines processing of BPDU packets. +* BPDU packets can be accepted and captured to one of RX queues +* or can be processing as regular Multicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture BPDU packets (DA is equal to +* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, +* except for the Flow-Control Pause packets). +* Negative value (-1) means no special processing for BPDU, +* packets so they will be processed as regular Multicast packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthBpduRxQueue(void *pPortHandle, int bpduQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + MV_U32 portCfgReg; + MV_U32 portCfgExtReg; + + if (bpduQueue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); + return MV_BAD_PARAM; + } + + portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + if (bpduQueue >= 0) { + pPortCtrl->portConfig.rxBpduQ = bpduQueue; + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; + } else { + pPortCtrl->portConfig.rxBpduQ = -1; + /* no special processing for BPDU packets */ + portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthArpRxQueue - Configure RX queue to capture ARP packets. +* +* DESCRIPTION: +* This function defines processing of ARP (type=0x0806) packets. +* ARP packets can be accepted and captured to one of RX queues +* or can be processed as other Broadcast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int arpQueue - Special queue to capture ARP packets (type=0x806). +* Negative value (-1) means discard ARP packets +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthArpRxQueue(void *pPortHandle, int arpQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + MV_U32 portCfgReg; + + if (arpQueue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if (arpQueue >= 0) { + pPortCtrl->portConfig.rxArpQ = arpQueue; + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); + } else { + pPortCtrl->portConfig.rxArpQ = -1; + portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. +* +* DESCRIPTION: +* This function defines processing of TCP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tcpQueue - Special queue to capture TCP packets. Value "-1" +* means no special processing for TCP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTcpRxQueue(void *pPortHandle, int tcpQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + MV_U32 portCfgReg; + + if (tcpQueue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); + return MV_BAD_PARAM; + } + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if (tcpQueue >= 0) { + pPortCtrl->portConfig.rxTcpQ = tcpQueue; + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; + } else { + pPortCtrl->portConfig.rxTcpQ = -1; + portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. +* +* DESCRIPTION: +* This function defines processing of UDP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int udpQueue - Special queue to capture UDP packets. Value "-1" +* means no special processing for UDP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthUdpRxQueue(void *pPortHandle, int udpQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + MV_U32 portCfgReg; + + if (udpQueue >= MV_ETH_RX_Q_NUM) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if (udpQueue >= 0) { + pPortCtrl->portConfig.rxUdpQ = udpQueue; + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } else { + pPortCtrl->portConfig.rxUdpQ = -1; + portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + +/******************************************************************************/ +/* Speed, Duplex, FlowControl routines */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and Speed. +* Changing of these parameters are allowed only when port is disabled. +* This function disable the port if was enabled, change duplex and speed +* and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* ETH_PORT_SPEED speed - Speed of the port. +* ETH_PORT_SPEED duplex - Duplex of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. +* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) +* is not valid +* +*******************************************************************************/ +MV_STATUS mvEthSpeedDuplexSet(void *pPortHandle, MV_ETH_PORT_SPEED speed, MV_ETH_PORT_DUPLEX duplex) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if ((port < 0) || (port >= (int)ethHalData.maxPortNum)) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if (pPortCtrl == NULL) + return MV_NOT_FOUND; + + /* Check validity */ + if ((speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF)) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + /* Set Speed */ + switch (speed) { + case MV_ETH_SPEED_AN: + portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; + break; + + case MV_ETH_SPEED_10: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_100: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_1000: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); + return MV_BAD_VALUE; + } + /* Set duplex */ + switch (duplex) { + case MV_ETH_DUPLEX_AN: + portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + break; + + case MV_ETH_DUPLEX_HALF: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; + break; + + case MV_ETH_DUPLEX_FULL: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and +* Speed. Changing of these parameters are allowed only when port is +* disabled. This function disable the port if was enabled, change +* duplex and speed and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvEthFlowCtrlSet(void *pPortHandle, MV_ETH_PORT_FC flowControl) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if ((port < 0) || (port >= (int)ethHalData.maxPortNum)) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if (pPortCtrl == NULL) + return MV_NOT_FOUND; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + switch (flowControl) { + case MV_ETH_FC_AN_ADV_DIS: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_AN_ADV_SYM: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_DISABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; + break; + + case MV_ETH_FC_ENABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthHeaderModeSet - Set port header mode. +* +* DESCRIPTION: +* This function configures the port to work in Marvell-Header mode. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_NOT_SUPPORTED- Feature not supported. +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. +* +*******************************************************************************/ +MV_STATUS mvEthHeaderModeSet(void *pPortHandle, MV_ETH_HEADER_MODE headerMode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 mvHeaderReg; + MV_U32 numRxQ = MV_ETH_RX_Q_NUM; + + if ((port < 0) || (port >= ethHalData.maxPortNum)) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if (pPortCtrl == NULL) + return MV_NOT_FOUND; + + mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); + /* Disable header mode. */ + mvHeaderReg &= ~ETH_MVHDR_EN_MASK; + + if (headerMode != MV_ETH_DISABLE_HEADER_MODE) { + /* Enable Header mode. */ + mvHeaderReg |= ETH_MVHDR_EN_MASK; + + /* Clear DA-Prefix & MHMask fields. */ + mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); + + if (numRxQ > 1) { + switch (headerMode) { + case (MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; + break; + case (MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; + break; + case (MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; + break; + default: + break; + } + + switch (numRxQ) { + case (4): + mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; + break; + case (8): + mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; + break; + default: + break; + } + } + } + + MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); + + return MV_OK; +} + +#if (MV_ETH_VERSION >= 4) +/******************************************************************************* +* mvEthEjpModeSet - Enable / Disable EJP policy for TX. +* +* DESCRIPTION: +* This function +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_BOOL TRUE - enable EJP mode +* FALSE - disable EJP mode +* +* OUTPUT: MV_STATUS +* MV_OK - Success +* Other - Failure +* +* RETURN: None. +* +*******************************************************************************/ +MV_STATUS mvEthEjpModeSet(void *pPortHandle, int mode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + + if ((port < 0) || (port >= ethHalData.maxPortNum)) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if (pPortCtrl == NULL) + return MV_NOT_FOUND; + + pPortCtrl->portConfig.ejpMode = mode; + if (mode) { + /* EJP enabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); + } else { + /* EJP disabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); + } + mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", + port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); + + return MV_OK; +} +#endif /* MV_ETH_VERSION >= 4 */ + +/******************************************************************************* +* mvEthStatusGet - Get major properties of the port . +* +* DESCRIPTION: +* This function get major properties of the port (link, speed, duplex, +* flowControl, etc) and return them using the single structure. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* OUTPUT: +* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status +* will be placed. +* +* RETURN: None. +* +*******************************************************************************/ +void mvEthStatusGet(void *pPortHandle, MV_ETH_PORT_STATUS * pStatus) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + + MV_U32 regValue; + + regValue = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + + if (regValue & ETH_GMII_SPEED_1000_MASK) + pStatus->speed = MV_ETH_SPEED_1000; + else if (regValue & ETH_MII_SPEED_100_MASK) + pStatus->speed = MV_ETH_SPEED_100; + else + pStatus->speed = MV_ETH_SPEED_10; + + if (regValue & ETH_LINK_UP_MASK) + pStatus->isLinkUp = MV_TRUE; + else + pStatus->isLinkUp = MV_FALSE; + + if (regValue & ETH_FULL_DUPLEX_MASK) + pStatus->duplex = MV_ETH_DUPLEX_FULL; + else + pStatus->duplex = MV_ETH_DUPLEX_HALF; + + if (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) + pStatus->flowControl = MV_ETH_FC_ENABLE; + else + pStatus->flowControl = MV_ETH_FC_DISABLE; +} + +/******************************************************************************/ +/* PHY Control Functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthPhyAddrSet - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int phyAddr - PHY address +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvEthPhyAddrSet(void *pPortHandle, int phyAddr) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + regData &= ~ETH_PHY_ADDR_MASK; + regData |= phyAddr; + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); + + return; +} + +/******************************************************************************* +* mvEthPhyAddrGet - Get the ethernet port PHY address. +* +* DESCRIPTION: +* This routine returns the given ethernet port PHY address. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* +* RETURN: int - PHY address. +* +*******************************************************************************/ +int mvEthPhyAddrGet(void *pPortHandle) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + return ((regData >> (5 * port)) & 0x1f); +} + +/******************************************************************************/ +/* Descriptor handling Functions */ +/******************************************************************************/ + +/******************************************************************************* +* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Rx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int rxQueue Number of Rx queue. +* int rxDescNum Number of Rx descriptors +* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Rx descriptors and buffers. +* +* RETURN: None +* +*******************************************************************************/ +static void ethInitRxDescRing(ETH_PORT_CTRL *pPortCtrl, int queue) +{ + ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; + int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pRxDescBase = (ETH_RX_DESC *) MV_ALIGN_UP((MV_ULONG) pQueueCtrl->descBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + pRxDesc = (ETH_RX_DESC *) pRxDescBase; + pRxPrevDesc = pRxDesc; + + /* initialize the Rx descriptors ring */ + for (ix = 0; ix < rxDescNum; ix++) { + pRxDesc->bufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + pRxPrevDesc = pRxDesc; + if (ix == (rxDescNum - 1)) { + /* Closing Rx descriptors ring */ + pRxPrevDesc->nextDescPtr = (MV_U32) ethDescVirtToPhy(pQueueCtrl, (void *)pRxDescBase); + } else { + pRxDesc = (ETH_RX_DESC *) ((MV_ULONG) pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); + pRxPrevDesc->nextDescPtr = (MV_U32) ethDescVirtToPhy(pQueueCtrl, (void *)pRxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pRxDescBase; + pQueueCtrl->pUsedDescr = pRxDescBase; + + pQueueCtrl->pFirstDescr = pRxDescBase; + pQueueCtrl->pLastDescr = pRxDesc; + pQueueCtrl->resource = 0; +} + +void ethResetRxDescRing(void *pPortHndl, int queue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; + ETH_RX_DESC *pRxDesc = (ETH_RX_DESC *) pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if (pQueueCtrl->pFirstDescr != NULL) { + while (MV_TRUE) { + pRxDesc->bufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + if ((void *)pRxDesc == pQueueCtrl->pLastDescr) + break; + pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + } + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg |= (1 << queue); + + /* update HW */ + MV_REG_WRITE(ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr)); + } else { + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); + + /* update HW */ + MV_REG_WRITE(ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); + } +} + +/******************************************************************************* +* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Tx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int txQueue Number of Tx queue. +* int txDescNum Number of Tx descriptors +* int txBuffSize Size of Tx buffer +* MV_U8* pTxDescBase Tx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Tx descriptors and buffers. +* +* RETURN: None. +* +*******************************************************************************/ +static void ethInitTxDescRing(ETH_PORT_CTRL *pPortCtrl, int queue) +{ + ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; + int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pTxDescBase = (ETH_TX_DESC *) MV_ALIGN_UP((MV_ULONG) pQueueCtrl->descBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + pTxDesc = (ETH_TX_DESC *) pTxDescBase; + pTxPrevDesc = pTxDesc; + + /* initialize the Tx descriptors ring */ + for (ix = 0; ix < txDescNum; ix++) { + pTxDesc->byteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + + pTxPrevDesc = pTxDesc; + + if (ix == (txDescNum - 1)) { +#ifdef MV_LEGACY_ETH_WA + /* Closing Tx descriptors ring */ + pTxPrevDesc->nextDescPtr = 0x0; +#else + pTxPrevDesc->nextDescPtr = (MV_U32) ethDescVirtToPhy(pQueueCtrl, (void *)pTxDescBase); +#endif + } else { + pTxDesc = (ETH_TX_DESC *) ((MV_ULONG) pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); +#ifdef MV_LEGACY_ETH_WA + pTxPrevDesc->nextDescPtr = 0x0; +#else + pTxPrevDesc->nextDescPtr = (MV_U32) ethDescVirtToPhy(pQueueCtrl, (void *)pTxDesc); +#endif + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pTxDescBase; + pQueueCtrl->pUsedDescr = pTxDescBase; + + pQueueCtrl->pFirstDescr = pTxDescBase; + pQueueCtrl->pLastDescr = pTxDesc; + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource = txDescNum - 1; +} + +void ethResetTxDescRing(void *pPortHndl, int queue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; + ETH_TX_DESC *pTxDesc = (ETH_TX_DESC *) pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if (pQueueCtrl->pFirstDescr != NULL) { + while (MV_TRUE) { + pTxDesc->byteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + pQueueCtrl->resource++; + if ((void *)pTxDesc == pQueueCtrl->pLastDescr) + break; + pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + } + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); + /* update HW */ + MV_REG_WRITE(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr)); + } else { + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); + /* update HW */ + MV_REG_WRITE(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); + } +} + +/******************************************************************************* +* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. +* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. +* +* INPUT: +* int size - size of memory should be allocated. +* +* RETURN: None +* +*******************************************************************************/ +static MV_U8 *ethAllocDescrMemory(ETH_PORT_CTRL * pPortCtrl, int descSize, MV_ULONG * pPhysAddr, MV_U32 * memHandle) +{ + MV_U8 *pVirt; + +#if defined(ETH_DESCR_IN_SRAM) + if (ethDescInSram == MV_TRUE) + pVirt = (MV_U8 *) mvSramMalloc(descSize, pPhysAddr); + else +#endif /* ETH_DESCR_IN_SRAM */ + { +#ifdef ETH_DESCR_UNCACHED + pVirt = (MV_U8 *) mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, pPhysAddr, memHandle); +#else + pVirt = (MV_U8 *) mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, pPhysAddr, memHandle); +#endif /* ETH_DESCR_UNCACHED */ + } + memset(pVirt, 0, descSize); + + return pVirt; +} + +/******************************************************************************* +* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function frees memory allocated for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. +* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. +* +* INPUT: +* void* pVirtAddr - virtual pointer to memory allocated for RX and TX +* desriptors. +* +* RETURN: None +* +*******************************************************************************/ +void ethFreeDescrMemory(ETH_PORT_CTRL *pPortCtrl, MV_BUF_INFO *pDescBuf) +{ + if ((pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL)) + return; + +#if defined(ETH_DESCR_IN_SRAM) + if (ethDescInSram) { + mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); + return; + } +#endif /* ETH_DESCR_IN_SRAM */ + +#ifdef ETH_DESCR_UNCACHED + mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr, pDescBuf->memHandle); +#else + mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr, pDescBuf->memHandle); +#endif /* ETH_DESCR_UNCACHED */ +} + +/******************************************************************************/ +/* Other Functions */ +/******************************************************************************/ + +void mvEthPortPowerUp(int port) +{ + MV_U32 regVal; + + /* MAC Cause register should be cleared */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + + if (ethHalData.portData[port].isSgmii) { + mvEthPortSgmiiConfig(port); + } + + /* Cancel Port Reset */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal &= (~ETH_PORT_RESET_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + while ((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0) + ; +} + +void mvEthPortPowerDown(int port) +{ + MV_U32 regVal; + + /* Port must be DISABLED */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + if ((regVal & ETH_PORT_ENABLE_MASK) != 0) { + mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", port, regVal); + return; + } + + /* Port Reset (Read after write the register as a precaution) */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); + while ((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0) + ; +} + +static void mvEthPortSgmiiConfig(int port) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal |= (/*ETH_SGMII_MODE_MASK |*/ ETH_PSC_ENABLE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); + //regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthDebug.c u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthDebug.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthDebug.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthDebug.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,651 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthDebug.c - Source file for user friendly debug functions +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysEthConfig.h" +#include "mvEthRegs.h" +#include "eth/mvEth.h" +#include "mvEthDebug.h" +#include "mvEthGbe.h" + +/* #define mvOsPrintf printf */ + +void mvEthPortShow(void *pHndl); +void mvEthQueuesShow(void *pHndl, int rxQueue, int txQueue, int mode); + +/******************************************************************************/ +/* Debug functions */ +/******************************************************************************/ +void ethRxCoal(int port, int usec) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthRxCoalSet(pHndl, usec); +} + +void ethTxCoal(int port, int usec) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthTxCoalSet(pHndl, usec); +} + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +{ + void *pHndl; + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthEjpModeSet(pHndl, mode); +} +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthBpduRxQueue(pHndl, bpduQueue); +} + +void ethArpRxQ(int port, int arpQueue) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthArpRxQueue(pHndl, arpQueue); +} + +void ethTcpRxQ(int port, int tcpQueue) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthTcpRxQueue(pHndl, tcpQueue); +} + +void ethUdpRxQ(int port, int udpQueue) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthUdpRxQueue(pHndl, udpQueue); +} + +void ethTxPolicyRegs(int port) +{ + int queue; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) mvEthPortHndlGet(port); + + if (pPortCtrl == NULL) + return; + + mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", port, pPortCtrl->portConfig.ejpMode); + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) { + if (pPortCtrl->txQueueConfig[queue].descrNum > 0) + mvOsPrintf("%d, ", queue); + } + mvOsPrintf("\n"); + + mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); + + mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_TX_QUEUE_COMMAND_REG(port), MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(port))); + + mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_FIXED_PRIO_CFG_REG(port), MV_REG_READ(ETH_TX_FIXED_PRIO_CFG_REG(port))); + + mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_RATE_CFG_REG(port), MV_REG_READ(ETH_TX_TOKEN_RATE_CFG_REG(port))); + + mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", + ETH_MAX_TRANSMIT_UNIT_REG(port), MV_REG_READ(ETH_MAX_TRANSMIT_UNIT_REG(port))); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_SIZE_REG(port), MV_REG_READ(ETH_TX_TOKEN_BUCKET_SIZE_REG(port))); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_COUNT_REG(port), MV_REG_READ(ETH_TX_TOKEN_BUCKET_COUNT_REG(port))); + + for (queue = 0; queue < MV_ETH_MAX_TXQ; queue++) { + mvOsPrintf("\n\t TX policy Port #%d, Queue #%d configuration registers\n", port, queue); + + mvOsPrintf("ETH_TXQ_TOKEN_COUNT_REG : 0x%X = 0x%08x\n", + ETH_TXQ_TOKEN_COUNT_REG(port, queue), MV_REG_READ(ETH_TXQ_TOKEN_COUNT_REG(port, queue))); + + mvOsPrintf("ETH_TXQ_TOKEN_CFG_REG : 0x%X = 0x%08x\n", + ETH_TXQ_TOKEN_CFG_REG(port, queue), MV_REG_READ(ETH_TXQ_TOKEN_CFG_REG(port, queue))); + + mvOsPrintf("ETH_TXQ_ARBITER_CFG_REG : 0x%X = 0x%08x\n", + ETH_TXQ_ARBITER_CFG_REG(port, queue), MV_REG_READ(ETH_TXQ_ARBITER_CFG_REG(port, queue))); + } + mvOsPrintf("\n"); +} + +/* Print important registers of Ethernet port */ +void ethPortRegs(int port) +{ + mvOsPrintf("\n\t ethGiga #%d port Registers:\n", port); + + mvOsPrintf("ETH_PORT_STATUS_REG : 0x%X = 0x%08x\n", + ETH_PORT_STATUS_REG(port), MV_REG_READ(ETH_PORT_STATUS_REG(port))); + + mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG : 0x%X = 0x%08x\n", + ETH_PORT_SERIAL_CTRL_REG(port), MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port))); + + mvOsPrintf("ETH_PORT_CONFIG_REG : 0x%X = 0x%08x\n", + ETH_PORT_CONFIG_REG(port), MV_REG_READ(ETH_PORT_CONFIG_REG(port))); + + mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG : 0x%X = 0x%08x\n", + ETH_PORT_CONFIG_EXTEND_REG(port), MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(port))); + + mvOsPrintf("ETH_SDMA_CONFIG_REG : 0x%X = 0x%08x\n", + ETH_SDMA_CONFIG_REG(port), MV_REG_READ(ETH_SDMA_CONFIG_REG(port))); + + mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG : 0x%X = 0x%08x\n", + ETH_TX_FIFO_URGENT_THRESH_REG(port), MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(port))); + + mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_RX_QUEUE_COMMAND_REG(port), MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(port))); + + mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_TX_QUEUE_COMMAND_REG(port), MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(port))); + + mvOsPrintf("ETH_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_INTR_CAUSE_REG(port), MV_REG_READ(ETH_INTR_CAUSE_REG(port))); + + mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_INTR_CAUSE_EXT_REG(port), MV_REG_READ(ETH_INTR_CAUSE_EXT_REG(port))); + + mvOsPrintf("ETH_INTR_MASK_REG : 0x%X = 0x%08x\n", + ETH_INTR_MASK_REG(port), MV_REG_READ(ETH_INTR_MASK_REG(port))); + + mvOsPrintf("ETH_INTR_EXTEND_MASK_REG : 0x%X = 0x%08x\n", + ETH_INTR_MASK_EXT_REG(port), MV_REG_READ(ETH_INTR_MASK_EXT_REG(port))); + + mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG : 0x%X = 0x%08x\n", + ETH_RX_DESCR_STAT_CMD_REG(port, 0), MV_REG_READ(ETH_RX_DESCR_STAT_CMD_REG(port, 0))); + + mvOsPrintf("ETH_RX_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + ETH_RX_BYTE_COUNT_REG(port, 0), MV_REG_READ(ETH_RX_BYTE_COUNT_REG(port, 0))); + + mvOsPrintf("ETH_RX_BUF_PTR_REG : 0x%X = 0x%08x\n", + ETH_RX_BUF_PTR_REG(port, 0), MV_REG_READ(ETH_RX_BUF_PTR_REG(port, 0))); + + mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, 0), MV_REG_READ(ETH_RX_CUR_DESC_PTR_REG(port, 0))); +} + +/* Print Giga Ethernet UNIT registers */ +void ethRegs(int port) +{ + mvOsPrintf("ETH_PHY_ADDR_REG : 0x%X = 0x%08x\n", + ETH_PHY_ADDR_REG(port), MV_REG_READ(ETH_PHY_ADDR_REG(port))); + + mvOsPrintf("ETH_UNIT_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INTR_CAUSE_REG(port), MV_REG_READ(ETH_UNIT_INTR_CAUSE_REG(port))); + + mvOsPrintf("ETH_UNIT_INTR_MASK_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INTR_MASK_REG(port), MV_REG_READ(ETH_UNIT_INTR_MASK_REG(port))); + + mvOsPrintf("ETH_UNIT_ERROR_ADDR_REG : 0x%X = 0x%08x\n", + ETH_UNIT_ERROR_ADDR_REG(port), MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(port))); + + mvOsPrintf("ETH_UNIT_INT_ADDR_ERROR_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INT_ADDR_ERROR_REG(port), MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(port))); + +} + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + +/******************************************************************************* +* ethClearMibCounters - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters of a specific ethernet port. +* A read from the MIB counter will reset the counter. +* +* INPUT: +* int port - Ethernet Port number. +* +* RETURN: None +* +*******************************************************************************/ +void ethClearCounters(int port) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthMibCountersClear(pHndl); + + return; +} + +/* Print counters of the Ethernet port */ +void ethPortCounters(int port) +{ + MV_U32 regValue, regValHigh; + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl == NULL) + return; + + mvOsPrintf("\n\t Port #%d MIB Counters\n\n", port); + + mvOsPrintf("GoodFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_RECEIVED, NULL)); + mvOsPrintf("BadFramesReceived = %u\n", mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FRAMES_RECEIVED, NULL)); + mvOsPrintf("BroadcastFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_RECEIVED, NULL)); + mvOsPrintf("MulticastFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_RECEIVED, NULL)); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, ®ValHigh); + mvOsPrintf("GoodOctetsReceived = 0x%08x%08x\n", regValHigh, regValue); + + mvOsPrintf("\n"); + mvOsPrintf("GoodFramesSent = %u\n", mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_SENT, NULL)); + mvOsPrintf("BroadcastFramesSent = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_SENT, NULL)); + mvOsPrintf("MulticastFramesSent = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_SENT, NULL)); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_SENT_LOW, ®ValHigh); + mvOsPrintf("GoodOctetsSent = 0x%08x%08x\n", regValHigh, regValue); + + mvOsPrintf("\n\t FC Control Counters\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED, NULL); + mvOsPrintf("UnrecogMacControlReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FC_RECEIVED, NULL); + mvOsPrintf("GoodFCFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FC_RECEIVED, NULL); + mvOsPrintf("BadFCFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FC_SENT, NULL); + mvOsPrintf("FCFramesSent = %u\n", regValue); + + mvOsPrintf("\n\t RX Errors\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_OCTETS_RECEIVED, NULL); + mvOsPrintf("BadOctetsReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNDERSIZE_RECEIVED, NULL); + mvOsPrintf("UndersizeFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FRAGMENTS_RECEIVED, NULL); + mvOsPrintf("FragmentsReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_OVERSIZE_RECEIVED, NULL); + mvOsPrintf("OversizeFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_JABBER_RECEIVED, NULL); + mvOsPrintf("JabbersReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_MAC_RECEIVE_ERROR, NULL); + mvOsPrintf("MacReceiveErrors = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_CRC_EVENT, NULL); + mvOsPrintf("BadCrcReceived = %u\n", regValue); + + mvOsPrintf("\n\t TX Errors\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR, NULL); + mvOsPrintf("TxMacErrors = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_EXCESSIVE_COLLISION, NULL); + mvOsPrintf("TxExcessiveCollisions = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_COLLISION, NULL); + mvOsPrintf("TxCollisions = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_LATE_COLLISION, NULL); + mvOsPrintf("TxLateCollisions = %u\n", regValue); + + mvOsPrintf("\n"); + regValue = MV_REG_READ(ETH_RX_DISCARD_PKTS_CNTR_REG(port)); + mvOsPrintf("Rx Discard packets counter = %u\n", regValue); + + regValue = MV_REG_READ(ETH_RX_OVERRUN_PKTS_CNTR_REG(port)); + mvOsPrintf("Rx Overrun packets counter = %u\n", regValue); +} + +/* Print RMON counters of the Ethernet port */ +void ethPortRmonCounters(int port) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl == NULL) + return; + + mvOsPrintf("\n\t Port #%d RMON MIB Counters\n\n", port); + + mvOsPrintf("64 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_64_OCTETS, NULL)); + mvOsPrintf("65...127 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_65_TO_127_OCTETS, NULL)); + mvOsPrintf("128...255 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_128_TO_255_OCTETS, NULL)); + mvOsPrintf("256...511 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_256_TO_511_OCTETS, NULL)); + mvOsPrintf("512...1023 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_512_TO_1023_OCTETS, NULL)); + mvOsPrintf("1024...Max ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_1024_TO_MAX_OCTETS, NULL)); +} + +/* Print port information */ +void ethPortStatus(int port) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthPortShow(pHndl); +} + +/* Print port queues information */ +void ethPortQueues(int port, int rxQueue, int txQueue, int mode) +{ + void *pHndl; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) + mvEthQueuesShow(pHndl, rxQueue, txQueue, mode); +} + +void ethUcastSet(int port, char *macStr, int queue) +{ + void *pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) { + mvMacStrToHex(macStr, macAddr); + mvEthMacAddrSet(pHndl, macAddr, queue); + } +} + +void ethPortUcastShow(int port) +{ + MV_U32 unicastReg, macL, macH; + int i, j; + + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(port)); + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(port)); + + mvOsPrintf("\n\t Port #%d Unicast MAC table: %02x:%02x:%02x:%02x:%02x:%02x\n\n", + port, ((macH >> 24) & 0xff), ((macH >> 16) & 0xff), + ((macH >> 8) & 0xff), (macH & 0xff), ((macL >> 8) & 0xff), (macL & 0xff)); + + for (i = 0; i < 4; i++) { + unicastReg = MV_REG_READ((ETH_DA_FILTER_UCAST_BASE(port) + i * 4)); + for (j = 0; j < 4; j++) { + MV_U8 macEntry = (unicastReg >> (8 * j)) & 0xFF; + + mvOsPrintf("%X: %8s, Q = %d\n", i * 4 + j, + (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); + } + } +} + +void ethMcastAdd(int port, char *macStr, int queue) +{ + void *pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if (pHndl != NULL) { + mvMacStrToHex(macStr, macAddr); + mvEthMcastAddrSet(pHndl, macAddr, queue); + } +} + +void ethPortMcast(int port) +{ + int tblIdx, regIdx; + MV_U32 regVal; + + mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", port); + + for (tblIdx = 0; tblIdx < (256 / 4); tblIdx++) { + regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx * 4)); + for (regIdx = 0; regIdx < 4; regIdx++) { + if ((regVal & (0x01 << (regIdx * 8))) != 0) { + mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", + tblIdx * 4 + regIdx, ((regVal >> (regIdx * 8 + 1)) & 0x07)); + } + } + } + mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); + for (tblIdx = 0; tblIdx < (256 / 4); tblIdx++) { + regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx * 4)); + for (regIdx = 0; regIdx < 4; regIdx++) { + if ((regVal & (0x01 << (regIdx * 8))) != 0) { + mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", + tblIdx * 4 + regIdx, ((regVal >> (regIdx * 8 + 1)) & 0x07)); + } + } + } +} + +/* Print status of Ethernet port */ +void mvEthPortShow(void *pHndl) +{ + MV_U32 regValue, rxCoal, txCoal; + int speed, queue, port; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pHndl; + + port = pPortCtrl->portNo; + + regValue = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + + mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", port, ETH_PORT_STATUS_REG(port), regValue); + + mvOsPrintf("descInSram=%d, descSwCoher=%d\n", ethDescInSram, ethDescSwCoher); + + if (regValue & ETH_GMII_SPEED_1000_MASK) + speed = 1000; + else if (regValue & ETH_MII_SPEED_100_MASK) + speed = 100; + else + speed = 10; + + mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); + + /* Link, Speed, Duplex, FlowControl */ + mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", + (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", + speed, + (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", + (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); + + mvOsPrintf("\n"); + + mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", rxCoal, txCoal); + + mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", + pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, + pPortCtrl->portConfig.rxBpduQ, pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); + + /* Print all RX and TX queues */ + for (queue = 0; queue < MV_ETH_RX_Q_NUM; queue++) { + mvOsPrintf("RX Queue #%d: base=0x%lx, free=%d\n", + queue, (MV_ULONG) pPortCtrl->rxQueue[queue].pFirstDescr, + mvEthRxResourceGet(pPortCtrl, queue)); + } + mvOsPrintf("\n"); + for (queue = 0; queue < MV_ETH_TX_Q_NUM; queue++) { + mvOsPrintf("TX Queue #%d: base=0x%lx, free=%d\n", + queue, (MV_ULONG) pPortCtrl->txQueue[queue].pFirstDescr, + mvEthTxResourceGet(pPortCtrl, queue)); + } +} + +/* Print RX and TX queue of the Ethernet port */ +void mvEthQueuesShow(void *pHndl, int rxQueue, int txQueue, int mode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_U32 regValue; + ETH_RX_DESC *pRxDescr; + ETH_TX_DESC *pTxDescr; + int i, port = pPortCtrl->portNo; + + if ((rxQueue >= 0) && (rxQueue < MV_ETH_RX_Q_NUM)) { + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); + + mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), MV_REG_READ(ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); + + if (pQueueCtrl->pFirstDescr != NULL) { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG) pQueueCtrl->pFirstDescr, (MV_ULONG) pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG) pQueueCtrl->pCurrentDescr, (MV_ULONG) pQueueCtrl->pUsedDescr); + + if (mode == 1) { + pRxDescr = (ETH_RX_DESC *) pQueueCtrl->pFirstDescr; + i = 0; + do { + mvOsPrintf + ("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32) pRxDescr, (MV_U32) ethDescVirtToPhy(pQueueCtrl, + (MV_U8 *) pRxDescr), + pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32) pRxDescr->bufSize, + (unsigned int)pRxDescr->bufPtr, (MV_ULONG) pRxDescr->returnInfo, + ((MV_PKT_INFO *) pRxDescr->returnInfo)->osInfo); + + ETH_DESCR_INV(pPortCtrl, pRxDescr); + pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); + i++; + } while (pRxDescr != pQueueCtrl->pFirstDescr); + } + } else + mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); + } + + if ((txQueue >= 0) && (txQueue < MV_ETH_TX_Q_NUM)) { + pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); + mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); + + regValue = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); + mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); + + if (pQueueCtrl->pFirstDescr != NULL) { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG) pQueueCtrl->pFirstDescr, + (MV_ULONG) pQueueCtrl->pLastDescr, pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG) pQueueCtrl->pCurrentDescr, (MV_ULONG) pQueueCtrl->pUsedDescr); + + if (mode == 1) { + pTxDescr = (ETH_TX_DESC *) pQueueCtrl->pFirstDescr; + i = 0; + do { + mvOsPrintf + ("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32) pTxDescr, (MV_U32) ethDescVirtToPhy(pQueueCtrl, + (MV_U8 *) pTxDescr), + pTxDescr->cmdSts, pTxDescr->byteCnt, (MV_U32) pTxDescr->bufPtr, + (MV_ULONG) pTxDescr->returnInfo, + pTxDescr->returnInfo ? (((MV_PKT_INFO *) pTxDescr->returnInfo)-> + osInfo) : 0x0); + + ETH_DESCR_INV(pPortCtrl, pTxDescr); + pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); + i++; + } while (pTxDescr != pQueueCtrl->pFirstDescr); + } + } else + mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthDebug.h u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthDebug.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthDebug.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthDebug.h 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,152 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_ETH_DEBUG_H__ +#define __MV_ETH_DEBUG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 +/* + ** Externs + */ +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int bpduQueue); +void ethTcpRxQ(int port, int bpduQueue); +void ethUdpRxQ(int port, int bpduQueue); +void ethMcastAdd(int port, char *macStr, int queue); + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolicy(int port); +void ethTxPolicy(int port); +void ethTxPolDA(int port, char *macStr, int txQ, char *headerHexStr); +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int rxQueue, int rxQuota); +#endif /* INCLUDE_MULTI_QUEUE */ + +void print_egiga_stat(void *sc, unsigned int port); +void ethPortStatus(int port); +void ethPortQueues(int port, int rxQueue, int txQueue, int mode); +void ethPortMcast(int port); +void ethPortRegs(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); + +void ethRegs(int port); +void ethClearCounters(int port); +void ethUcastSet(int port, char *macStr, int queue); +void ethPortUcastShow(int port); + +#ifdef CONFIG_MV_ETH_HEADER +void run_com_header(const char *buffer); +#endif + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int queue, int quota); +void ethRxPolicy(int port); +void ethTxPolDef(int port, int txQ, char *headerHexStr); +void ethTxPolDA(int port, char *macStr, int txQ, char *headerHexStr); +void ethTxPolicy(int port); +#endif /* INCLUDE_MULTI_QUEUE */ + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +#endif +#endif /* 0 */ + + + + +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int arpQueue); +void ethTcpRxQ(int port, int tcpQueue); +void ethUdpRxQ(int port, int udpQueue); +void ethTxPolicyRegs(int port); +void ethPortRegs(int port); +void ethRegs(int port); +void ethClearCounters(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethPortStatus(int port); +void ethPortQueues(int port, int rxQueue, int txQueue, int mode); +void ethUcastSet(int port, char *macStr, int queue); +void ethPortUcastShow(int port); +void ethMcastAdd(int port, char *macStr, int queue); +void ethPortMcast(int port); +void mvEthPortShow(void *pHndl); +void mvEthQueuesShow(void *pHndl, int rxQueue, int txQueue, int mode); + +#ifdef __cplusplus +} +#endif + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthGbe.h u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthGbe.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthGbe.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthGbe.h 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,739 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration specific to +* the Marvell Gigabit Ethernet Controller. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvEthGbe_h__ +#define __mvEthGbe_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "eth/mvEth.h" + +extern MV_BOOL ethDescInSram; +extern MV_BOOL ethDescSwCoher; +extern ETH_PORT_CTRL *ethPortCtrl[]; + +static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL * pQueueCtrl, MV_U8 * pDesc) { +#if defined(ETH_DESCR_IN_SRAM) +if (ethDescInSram) + return mvSramVirtToPhy(pDesc); +else +#endif /* ETH_DESCR_IN_SRAM */ +return (pQueueCtrl->descBuf.bufPhysAddr+(pDesc-pQueueCtrl->descBuf.bufVirtPtr)); +} + +/* Return port handler */ +#define mvEthPortHndlGet(port) ethPortCtrl[port] + +/* Used as WA for HW/SW race on TX */ + +static INLINE int mvEthPortTxEnable(void *pPortHndl, int queue, int max_deep) +{ +int deep = 0; +MV_U32 txCurrReg, txEnReg; +ETH_TX_DESC *pTxLastDesc; +ETH_QUEUE_CTRL *pQueueCtrl; +ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + +txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); +if ((txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) { + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return 0; +} +pQueueCtrl = &pPortCtrl->txQueue[queue]; +pTxLastDesc = pQueueCtrl->pCurrentDescr; +txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); +if (ethDescVirtToPhy(pQueueCtrl, (MV_U8 *) pTxLastDesc) == txCurrReg) { + /* All descriptors are processed, no chance for race */ + return 0; +} + +/* Check distance betwee HW and SW location: */ +/* If distance between HW and SW pointers is less than max_deep descriptors */ +/* Race condition is possible, so wait end of TX and restart TXQ */ +while (deep < max_deep) { + pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); + if (ethDescVirtToPhy(pQueueCtrl, (MV_U8 *) pTxLastDesc) == txCurrReg) { + int count = 0; + while ((txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) { + count++; + if (count > 10000) { + mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", + MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo))); + break; + } + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + } + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = + pPortCtrl->portTxQueueCmdReg; + return count; + } + deep++; + } + /* Distance between HW and SW pointers is more than max_deep descriptors, */ + /* So NO race condition - do nothing */ + return -1; + } + +/* defines */ +#define ETH_CSUM_MIN_BYTE_COUNT 72 + +/* Tailgate and Kirwood have only 2K TX FIFO */ +#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) +#define ETH_CSUM_MAX_BYTE_COUNT 1600 +#else +#define ETH_CSUM_MAX_BYTE_COUNT (9*1024) +#endif /* MV_ETH_VERSION */ + +#define ETH_MV_HEADER_SIZE 2 +#define ETH_MV_TX_EN + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define MIN_TX_BUFF_LOAD 8 +#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + (ETH_DEF_RX_QUEUE_MASK(0) | \ + ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ + ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ + ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ + ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ + ETH_RX_CHECKSUM_WITH_PSEUDO_HDR) + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE 0 + +#define PORT_SERIAL_CONTROL_VALUE \ + (ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_SET_FULL_DUPLEX_MASK) + +#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ + (ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_MII_SPEED_100_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE) + +#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ + (ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_GMII_SPEED_1000_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE) + +#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ + (ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_IN_BAND_AN_EN_MASK | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE) + +/* Function headers: */ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); +MV_STATUS mvEthArpRxQueue(void *pPortHandle, int arpQueue); +MV_STATUS mvEthUdpRxQueue(void *pPortHandle, int udpQueue); +MV_STATUS mvEthTcpRxQueue(void *pPortHandle, int tcpQueue); +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); +MV_STATUS mvEthHeaderModeSet(void *pPortHandle, MV_ETH_HEADER_MODE headerMode); +/* Interrupt Coalesting functions */ +MV_U32 mvEthRxCoalSet(void *pPortHndl, MV_U32 uSec); +MV_U32 mvEthTxCoalSet(void *pPortHndl, MV_U32 uSec); +MV_STATUS mvEthCoalGet(void *pPortHndl, MV_U32 * pRxCoal, MV_U32 * pTxCoal); + +/******************************************************************************/ +/* Data Flow functions */ +/******************************************************************************/ +static INLINE void mvEthPortTxRestart(void *pPortHndl) +{ +ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *)pPortHndl; + +MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; +} + +/* Get number of Free resources in specific TX queue */ +static INLINE int mvEthTxResourceGet(void *pPortHndl, int txQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + + return (pPortCtrl->txQueue[txQueue].resource); +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxResourceGet(void *pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + return (pPortCtrl->rxQueue[rxQueue].resource); +} + +static INLINE int mvEthTxQueueIsFull(void *pPortHndl, int txQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + + if (pPortCtrl->txQueue[txQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsFull(void *pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if ((pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && (pQueueCtrl->resource != 0)) + return MV_TRUE; + return MV_FALSE; +} + +static INLINE int mvEthTxQueueIsEmpty(void *pPortHndl, int txQueue) +{ +ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; +ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[txQueue]; +if ((pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && (pQueueCtrl->resource != 0)) + return MV_TRUE; +return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsEmpty(void *pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pPortHndl; + + if (pPortCtrl->rxQueue[rxQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPortTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pPktInfo parameter. +* Single buffer only. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortTx(void *pEthPortHndl, int txQueue, MV_PKT_INFO * pPktInfo) +{ + ETH_TX_DESC *pTxCurrDesc; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + int portNo; + MV_BUF_INFO *pBufInfo = pPktInfo->pFrags; + +#ifdef ETH_DEBUG + if (pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if (pQueueCtrl->resource == 0) + return MV_NO_RESOURCE; + +#ifdef MV_LEGACY_ETH_WA + while (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(portNo)) & (1 << txQueue)) +; + MV_REG_WRITE(ETH_TX_CUR_DESC_PTR_REG(portNo, txQueue), + (MV_U32) ethDescVirtToPhy(pQueueCtrl, pTxCurrDesc)); +#endif + + pTxCurrDesc->byteCnt = pBufInfo->dataSize; + + /* Flash Buffer */ + if (pPktInfo->pktSize != 0) { +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#else + pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#endif + pPktInfo->pktSize = 0; + } else + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + + pTxCurrDesc->returnInfo = (MV_ULONG) pPktInfo; + + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | ETH_TX_FIRST_DESC_MASK | ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; + } + +/******************************************************************************* +* mvEthPortSgTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pBufInfo parameter. It +* supports transmitting of a packet spaned over multiple buffers. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortSgTx(void *pEthPortHndl, int txQueue, MV_PKT_INFO * pPktInfo) +{ + ETH_TX_DESC *pTxFirstDesc; + ETH_TX_DESC *pTxCurrDesc; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + int portNo, bufCount; + MV_BUF_INFO *pBufInfo = pPktInfo->pFrags; + MV_U8 *pTxBuf; + +#ifdef ETH_DEBUG + if (pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if (pQueueCtrl->resource < pPktInfo->numFrags) + return MV_NO_RESOURCE; + + /* Remember first desc */ + pTxFirstDesc = pTxCurrDesc; + + bufCount = 0; + while (MV_TRUE) { + if (pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) { + /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ + /* to 64-bit boundary. Two options here: */ + /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ + /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ + /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ + pTxBuf = ((MV_U8 *) pTxCurrDesc) + TX_BUF_OFFSET_IN_DESC; + mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); + pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); + } else { + /* Flash Buffer */ +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#else + pTxCurrDesc->bufPtr = + ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#endif + } + + pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; + bufCount++; + + if (bufCount >= pPktInfo->numFrags) + break; + + if (bufCount > 1) { + /* There is middle buffer of the packet Not First and Not Last */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + /* Go to next descriptor and next buffer */ + pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + } + /* Set last desc with DMA ownership and interrupt enable. */ + pTxCurrDesc->returnInfo = (MV_ULONG) pPktInfo; + if (bufCount == 1) { + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | ETH_TX_FIRST_DESC_MASK | ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } else { + /* Last but not First */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_ENABLE_INTERRUPT_MASK | ETH_TX_ZERO_PADDING_MASK | ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + /* Update First when more than one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxFirstDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | ETH_TX_GENERATE_CRC_MASK | ETH_TX_FIRST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); + } + /* Update txQueue state */ + pQueueCtrl->resource -= bufCount; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; + } + +/******************************************************************************* +* mvEthPortTxDone - Free all used Tx descriptors and mBlks. +* +* DESCRIPTION: +* This routine returns the transmitted packet information to the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. +* MV_EMPTY - No transmitted packets to return. TX Queue is empty. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - There is transmitted packet in the queue, +* 'pPktInfo' filled with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO *mvEthPortTxDone(void *pEthPortHndl, int txQueue) +{ + ETH_TX_DESC *pTxCurrDesc; + ETH_TX_DESC *pTxUsedDesc; + ETH_QUEUE_CTRL *pQueueCtrl; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + MV_PKT_INFO *pPktInfo; + MV_U32 commandStatus; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + pTxUsedDesc = pQueueCtrl->pUsedDescr; + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + while (MV_TRUE) { + /* No more used descriptors */ + commandStatus = pTxUsedDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) { + ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); + return NULL; + } + if ((pTxUsedDesc == pTxCurrDesc) && (pQueueCtrl->resource != 0)) + return NULL; + + pQueueCtrl->resource++; + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); + if (commandStatus & (ETH_TX_LAST_DESC_MASK)) { + pPktInfo = (MV_PKT_INFO *) pTxUsedDesc->returnInfo; + pPktInfo->status = commandStatus; + return pPktInfo; + } + pTxUsedDesc = pQueueCtrl->pUsedDescr; + } + } + +/******************************************************************************* +* mvEthPortRx - Get new received packets from Rx queue. +* +* DESCRIPTION: +* This routine returns the received data to the caller. There is no +* data copying during routine operation. All information is returned +* using pointer to packet information struct passed from the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_NO_RESOURCE - No free resources in RX queue. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - New packet received and 'pBufInfo' structure filled +* with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO *mvEthPortRx(void *pEthPortHndl, int rxQueue) +{ + ETH_RX_DESC *pRxCurrDesc; + MV_U32 commandStatus; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_PKT_INFO *pPktInfo; + + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + + /* Check resources */ + if (pQueueCtrl->resource == 0) { + mvOsPrintf("ethPortRx: no more resources\n"); + return NULL; + } + while (MV_TRUE) { + /* Get the Rx Desc ring 'curr and 'used' indexes */ + pRxCurrDesc = pQueueCtrl->pCurrentDescr; + + commandStatus = pRxCurrDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) { + /* Nothing to receive... */ + ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); + return NULL; + } + + /* Valid RX only if FIRST and LAST bits are set */ + if ((commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == + (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) { + pPktInfo = (MV_PKT_INFO *) pRxCurrDesc->returnInfo; + pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; + pPktInfo->status = commandStatus; + pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; + + pQueueCtrl->resource--; + /* Update 'curr' in data structure */ + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + +#ifdef INCLUDE_SYNC_BARR + mvCpuIfSyncBarr(DRAM_TARGET); +#endif + return pPktInfo; + } else { + ETH_RX_DESC *pRxUsedDesc = pQueueCtrl->pUsedDescr; + +#ifdef ETH_DEBUG + mvOsPrintf("ethDrv: Unexpected Jumbo frame: " + "status=0x%08x, byteCnt=%d, pData=0x%x\n", + commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); +#endif /* ETH_DEBUG */ + + /* move buffer from pCurrentDescr position to pUsedDescr position */ + pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; + pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; + pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + } + } + } + +/******************************************************************************* +* mvEthPortRxDoneTest - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine performs a diagnostic for Rx buffer +* +*******************************************************************************/ +static INLINE void mvEthRxDoneTest(MV_BUF_INFO *pBuf, MV_U32 alignment) +{ + MV_U32 va = (MV_U32) pBuf->bufVirtPtr; + MV_U32 pa = (MV_U32) pBuf->bufPhysAddr; + + /* + * Check the manipulation of pBuf is properly done prior to RxDone + */ + if (((va & 0xFF) != alignment) || ((pa & 0xFF) != alignment) || pBuf->bufAddrShift) { + mvOsPrintf("mvRxDoneTest: pBuf=%p va=%x pa=%x shift=%d\n", pBuf, va, pa, pBuf->bufAddrShift); + /* dump_stack() */ + } + } + +/******************************************************************************* +* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine returns a Rx buffer back to the Rx ring. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_ERROR - Unexpected Fatal error. +* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be +* returned to this queue. +* MV_FULL - Buffer returned successfully and RX queue became full. +* More buffers should not be returned at the time. +* MV_OK - Buffer returned successfully and there are more free +* places in the queue. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortRxDone(void *pEthPortHndl, int rxQueue, MV_PKT_INFO * pPktInfo) +{ + ETH_RX_DESC *pRxUsedDesc; + ETH_QUEUE_CTRL *pQueueCtrl; + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL *) pEthPortHndl; + +/* + for debug: + mvEthRxDoneTest(pPktInfo->pFrags, CONFIG_NET_SKB_HEADROOM); +*/ + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + /* Get 'used' Rx descriptor */ + pRxUsedDesc = pQueueCtrl->pUsedDescr; + + /* Check that ring is not FULL */ + if ((pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && (pQueueCtrl->resource != 0)) { + mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", + __func__, pPortCtrl->portNo, pQueueCtrl->resource, + pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); + return MV_OUT_OF_RANGE; + } + + pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; + pRxUsedDesc->returnInfo = (MV_ULONG) pPktInfo; + pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; + + /* Invalidate data buffer accordingly with pktSize */ + if (pPktInfo->pktSize != 0) { + ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); + pPktInfo->pktSize = 0; + } + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + pQueueCtrl->resource++; + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + + /* If ring became Full return MV_FULL */ + if (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) + return MV_FULL; + + return MV_OK; + } + +#ifdef __cplusplus +} +#endif + +#endif /* __mvEthGbe_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthRegs.h u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/gbe/mvEthRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/gbe/mvEthRegs.h 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,723 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvEthRegsh +#define __INCmvEthRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvSysEthConfig.h" + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ +#define ETH_PHY_ADDR_REG(port) (MV_ETH_REGS_BASE(port) + 0x000) +#define ETH_SMI_REG(port) (MV_ETH_REGS_BASE(port) + 0x004) +#define ETH_UNIT_DEF_ADDR_REG(port) (MV_ETH_REGS_BASE(port) + 0x008) +#define ETH_UNIT_DEF_ID_REG(port) (MV_ETH_REGS_BASE(port) + 0x00c) +#define ETH_UNIT_RESERVED(port) (MV_ETH_REGS_BASE(port) + 0x014) +#define ETH_UNIT_INTR_CAUSE_REG(port) (MV_ETH_REGS_BASE(port) + 0x080) +#define ETH_UNIT_INTR_MASK_REG(port) (MV_ETH_REGS_BASE(port) + 0x084) + + +#define ETH_UNIT_ERROR_ADDR_REG(port) (MV_ETH_REGS_BASE(port) + 0x094) +#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (MV_ETH_REGS_BASE(port) + 0x098) +#define ETH_UNIT_CONTROL_REG(port) (MV_ETH_REGS_BASE(port) + 0x0B0) + +#define ETH_PORT_CONFIG_REG(port) (MV_ETH_REGS_BASE(port) + 0x400) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (MV_ETH_REGS_BASE(port) + 0x404) +#define ETH_MII_SERIAL_PARAM_REG(port) (MV_ETH_REGS_BASE(port) + 0x408) +#define ETH_GMII_SERIAL_PARAM_REG(port) (MV_ETH_REGS_BASE(port) + 0x40c) +#define ETH_VLAN_ETHER_TYPE_REG(port) (MV_ETH_REGS_BASE(port) + 0x410) +#define ETH_MAC_ADDR_LOW_REG(port) (MV_ETH_REGS_BASE(port) + 0x414) +#define ETH_MAC_ADDR_HIGH_REG(port) (MV_ETH_REGS_BASE(port) + 0x418) +#define ETH_SDMA_CONFIG_REG(port) (MV_ETH_REGS_BASE(port) + 0x41c) +#define ETH_DIFF_SERV_PRIO_REG(port, code) (MV_ETH_REGS_BASE(port) + 0x420 + ((code)<<2)) +#define ETH_PORT_SERIAL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0x43c) +#define ETH_VLAN_TAG_TO_PRIO_REG(port) (MV_ETH_REGS_BASE(port) + 0x440) +#define ETH_PORT_STATUS_REG(port) (MV_ETH_REGS_BASE(port) + 0x444) + +#define ETH_RX_QUEUE_COMMAND_REG(port) (MV_ETH_REGS_BASE(port) + 0x680) +#define ETH_TX_QUEUE_COMMAND_REG(port) (MV_ETH_REGS_BASE(port) + 0x448) + +#define ETH_PORT_SERIAL_CTRL_1_REG(port) (MV_ETH_REGS_BASE(port) + 0x44c) +#define ETH_PORT_STATUS_1_REG(port) (MV_ETH_REGS_BASE(port) + 0x450) +#define ETH_PORT_MARVELL_HEADER_REG(port) (MV_ETH_REGS_BASE(port) + 0x454) +#define ETH_PORT_FIFO_PARAMS_REG(port) (MV_ETH_REGS_BASE(port) + 0x458) +#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (MV_ETH_REGS_BASE(port) + 0x45c) +#define ETH_INTR_CAUSE_REG(port) (MV_ETH_REGS_BASE(port) + 0x460) +#define ETH_INTR_CAUSE_EXT_REG(port) (MV_ETH_REGS_BASE(port) + 0x464) +#define ETH_INTR_MASK_REG(port) (MV_ETH_REGS_BASE(port) + 0x468) +#define ETH_INTR_MASK_EXT_REG(port) (MV_ETH_REGS_BASE(port) + 0x46c) +#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (MV_ETH_REGS_BASE(port) + 0x474) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (MV_ETH_REGS_BASE(port) + 0x47c) +#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (MV_ETH_REGS_BASE(port) + 0x484) +#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (MV_ETH_REGS_BASE(port) + 0x488) +#define ETH_INTERNAL_ADDR_ERROR_REG(port) (MV_ETH_REGS_BASE(port) + 0x494) +#define ETH_TX_FIXED_PRIO_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4dc) +#define ETH_TX_TOKEN_RATE_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4e0) +#define ETH_TX_QUEUE_COMMAND1_REG(port) (MV_ETH_REGS_BASE(port) + 0x4e4) +#define ETH_MAX_TRANSMIT_UNIT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4e8) +#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (MV_ETH_REGS_BASE(port) + 0x4ec) +#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (MV_ETH_REGS_BASE(port) + 0x780) +#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x600 + ((q)<<4)) +#define ETH_RX_BYTE_COUNT_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x604 + ((q)<<4)) +#define ETH_RX_BUF_PTR_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x608 + ((q)<<4)) +#define ETH_RX_CUR_DESC_PTR_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x60c + ((q)<<4)) +#define ETH_TX_CUR_DESC_PTR_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x6c0 + ((q)<<2)) + +#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x700 + ((q)<<4)) +#define ETH_TXQ_TOKEN_CFG_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x704 + ((q)<<4)) +#define ETH_TXQ_ARBITER_CFG_REG(port, q) (MV_ETH_REGS_BASE(port) + 0x708 + ((q)<<4)) + +#if (MV_ETH_VERSION >= 4) +#define ETH_TXQ_CMD_1_REG(port) (MV_ETH_REGS_BASE(port) + 0x4E4) +#define ETH_EJP_TX_HI_IPG_REG(port) (MV_ETH_REGS_BASE(port) + 0x7A8) +#define ETH_EJP_TX_LO_IPG_REG(port) (MV_ETH_REGS_BASE(port) + 0x7B8) +#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (MV_ETH_REGS_BASE(port) + 0x7C0) +#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (MV_ETH_REGS_BASE(port) + 0x7C4) +#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (MV_ETH_REGS_BASE(port) + 0x7C8) +#define ETH_EJP_TX_SPEED_REG(port) (MV_ETH_REGS_BASE(port) + 0x7D0) +#endif /* MV_ETH_VERSION >= 4 */ + +#define ETH_MIB_COUNTERS_BASE(port) (MV_ETH_REGS_BASE(port) + 0x1000) +#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (MV_ETH_REGS_BASE(port) + 0x1400) +#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (MV_ETH_REGS_BASE(port) + 0x1500) +#define ETH_DA_FILTER_UCAST_BASE(port) (MV_ETH_REGS_BASE(port) + 0x1600) + +/* Phy address register definitions */ +#define ETH_PHY_ADDR_OFFS 0 +#define ETH_PHY_ADDR_MASK (0x1f << ETH_PHY_ADDR_OFFS) + +/* MIB Counters register definitions */ +#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 +#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 +#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 +#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc +#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 +#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 +#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 +#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c +#define ETH_MIB_FRAMES_64_OCTETS 0x20 +#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 +#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c +#define ETH_MIB_GOOD_FRAMES_SENT 0x40 +#define ETH_MIB_EXCESSIVE_COLLISION 0x44 +#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 +#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c +#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 +#define ETH_MIB_FC_SENT 0x54 +#define ETH_MIB_GOOD_FC_RECEIVED 0x58 +#define ETH_MIB_BAD_FC_RECEIVED 0x5c +#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 +#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 +#define ETH_MIB_OVERSIZE_RECEIVED 0x68 +#define ETH_MIB_JABBER_RECEIVED 0x6c +#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 +#define ETH_MIB_BAD_CRC_EVENT 0x74 +#define ETH_MIB_COLLISION 0x78 +#define ETH_MIB_LATE_COLLISION 0x7c + + +/****************************************/ +/* Ethernet Unit Register BITs */ +/****************************************/ + +#define ETH_RXQ_ENABLE_OFFSET 0 +#define ETH_RXQ_ENABLE_MASK (0x000000FF << ETH_RXQ_ENABLE_OFFSET) + +#define ETH_RXQ_DISABLE_OFFSET 8 +#define ETH_RXQ_DISABLE_MASK (0x000000FF << ETH_RXQ_DISABLE_OFFSET) + +/***** BITs of Transmit Queue Command (TQC) register *****/ +#define ETH_TXQ_ENABLE_OFFSET 0 +#define ETH_TXQ_ENABLE_MASK (0x000000FF << ETH_TXQ_ENABLE_OFFSET) + +#define ETH_TXQ_DISABLE_OFFSET 8 +#define ETH_TXQ_DISABLE_MASK (0x000000FF << ETH_TXQ_DISABLE_OFFSET) + +#if (MV_ETH_VERSION >= 4) +#define ETH_TX_EJP_RESET_BIT 0 +#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) + +#define ETH_TX_EJP_ENABLE_BIT 2 +#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) + +#define ETH_TX_LEGACY_WRR_BIT 3 +#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) +#endif /* (MV_ETH_VERSION >= 4) */ + +/***** BITs of Ethernet Port Status reg (PSR) *****/ +#define ETH_LINK_UP_BIT 1 +#define ETH_LINK_UP_MASK (1<= 4) + MV_STATUS mvEthEjpModeSet(void *pPortHandle, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + + void mvEthStatusGet(void *pPortHandle, MV_ETH_PORT_STATUS *pStatus); + +/* Marvell Header control */ + MV_STATUS mvEthHeaderModeSet(void *pPortHandle, MV_ETH_HEADER_MODE headerMode); + +/* PHY routines */ + void mvEthPhyAddrSet(void *pPortHandle, int phyAddr); + int mvEthPhyAddrGet(void *pPortHandle); + +/* Power management routines */ + void mvEthPortPowerDown(int port); + void mvEthPortPowerUp(int port); + + MV_STATUS mvEthWinInit(MV_U32 port, MV_UNIT_WIN_INFO *addrWinMap); + MV_STATUS mvEthWinWrite(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin); + MV_STATUS mvEthWinRead(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin); + MV_STATUS mvEthWinEnable(MV_U32 port, MV_U32 winNum, MV_BOOL enable); + +/******************** ETH PRIVATE ************************/ + +/*#define UNCACHED_TX_BUFFERS*/ +/*#define UNCACHED_RX_BUFFERS*/ + +/* Port attributes */ +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define ETH_RX_DESC_ALIGNED_SIZE 32 +#define ETH_TX_DESC_ALIGNED_SIZE 32 + +#define TX_DISABLE_TIMEOUT_MSEC 1000 +#define RX_DISABLE_TIMEOUT_MSEC 1000 +#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 +#define PORT_DISABLE_WAIT_TCLOCKS 5000 + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_RX_DESC *)((pQueueCtrl)->pFirstDescr) : \ + (ETH_RX_DESC *)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_TX_DESC *)((pQueueCtrl)->pFirstDescr) : \ + (ETH_TX_DESC *)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) + +#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_RX_DESC *)((pQueueCtrl)->pLastDescr) : \ + (ETH_RX_DESC *)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_TX_DESC *)((pQueueCtrl)->pLastDescr) : \ + (ETH_TX_DESC *)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) + +/* Queue specific information */ + typedef struct { + void *pFirstDescr; + void *pLastDescr; + void *pCurrentDescr; + void *pUsedDescr; + int resource; + MV_BUF_INFO descBuf; + } ETH_QUEUE_CTRL; + +/* Ethernet port specific infomation */ + typedef struct _ethPortCtrl { + int portNo; + ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ + ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ + + MV_ETH_PORT_CFG portConfig; + MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; + MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; + + /* Register images - For DP */ + MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ + MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ + + MV_STATE portState; + + MV_U8 mcastCount[256]; + MV_U32 *hashPtr; + void *osHandle; + } ETH_PORT_CTRL; + +/************** MACROs ****************/ + +/* MACROs to Flush / Invalidate TX / RX Buffers */ +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsCacheClear(NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH; */ +#else +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsIoVirtToPhy(NULL, (pAddr)); +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ + +#if ((ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS)) +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ + mvOsCacheInvalidate(NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH; */ +#else +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ + +#ifdef ETH_DESCR_UNCACHED + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) +#define ETH_DESCR_INV(pPortCtrl, pDescr) + +#else + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ + mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#define ETH_DESCR_INV(pPortCtrl, pDescr) \ + mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#endif /* ETH_DESCR_UNCACHED */ + +/* #include "eth/gbe/mvEthGbe.h" */ + +#ifdef __cplusplus +} +#endif +#endif /* __mvEth_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfp.c u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfp.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfp.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfp.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,987 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.c - Marvell Network Fast Processing (Routing and NAT) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/nfp/mvNfpSec.h" +#include "eth/mvEth.h" + +static struct ruleHashBucket *ruleDb; +static MV_U32 ruleDbSize; + +static MV_U32 nfpHashMaxDepth; +static MV_U32 nfpRuleSetCount; +static MV_U32 nfpRuleUpdateCount; +static MV_U32 nfpRuleDeleteCount; + +MV_U32 fp_ip_jhash_iv = 0; + +MV_STATUS mvFpInit(void) +{ + fp_ip_jhash_iv = mvOsRand(); + + return MV_OK; +} + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize) +{ + ruleDb = (struct ruleHashBucket *)mvOsMalloc(sizeof(struct ruleHashBucket) * dbSize); + if (ruleDb == NULL) { + mvOsPrintf("NFP Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + ruleDbSize = dbSize; + memset(ruleDb, 0, sizeof(struct ruleHashBucket) * ruleDbSize); + nfpRuleSetCount = nfpRuleUpdateCount = nfpRuleDeleteCount = 0; + + mvOsPrintf("mvFpRuleDb (%p): %d entries, %d bytes\n", + ruleDb, ruleDbSize, sizeof(struct ruleHashBucket) * ruleDbSize); + + return MV_OK; +} + +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void) +{ + MV_U32 i = 0; + MV_FP_RULE *currRule; + MV_FP_RULE *tmpRule; + + if (ruleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < ruleDbSize; i++) { + currRule = ruleDb[i].ruleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + ruleDb[i].ruleChain = NULL; + } + return MV_OK; +} + +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void) +{ + if (ruleDb != NULL) + mvOsFree(ruleDb); +} + +/* Print rule action type. Assume rule is not NULL. */ +static void mvFpActionTypePrint(const MV_FP_RULE *rule) +{ + switch (rule->mgmtInfo.actionType) { + case MV_FP_ROUTE_CMD: + mvOsPrintf("A=Route, "); + break; + case MV_FP_DROP_CMD: + mvOsPrintf("A=Drop, "); + break; + case MV_FP_TO_STACK_CMD: + mvOsPrintf("A=Stack, "); + break; + default: + mvOsPrintf("A=Unknown (%d), ", rule->mgmtInfo.actionType); + break; + } +} + +/* Print rule type (static or dynamic). Assume rule is not NULL. */ +static void mvFpRuleTypePrint(const MV_FP_RULE *rule) +{ + switch (rule->mgmtInfo.ruleType) { + case MV_FP_STATIC_RULE: + mvOsPrintf("T=Static"); + break; + case MV_FP_DYNAMIC_RULE: + mvOsPrintf("T=Dynamic"); + break; + default: + mvOsPrintf("T=Unknown"); + break; + } +} + +/* Print a NFP Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule) +{ + mvFpActionTypePrint(rule); + mvFpRuleTypePrint(rule); + mvOsPrintf(", SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.srcIp)); + mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.dstIp)); + mvOsPrintf(", GTW="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.defGtwIp)); + mvOsPrintf(", DA="); + mvDebugPrintMacAddr(rule->routingInfo.dstMac); + mvOsPrintf(", SA="); + mvDebugPrintMacAddr(rule->routingInfo.srcMac); + mvOsPrintf(", inIf=%d", rule->routingInfo.inIfIndex); + mvOsPrintf(", outIf=%d", rule->routingInfo.outIfIndex); + mvOsPrintf(", ToS=0x%x", rule->routingInfo.dscp); + mvOsPrintf(", TxQ=%d", rule->routingInfo.txq); + + mvOsPrintf(", count=%d, aware_flags=0x%X", rule->mgmtInfo.new_count, rule->routingInfo.aware_flags); + mvOsPrintf("\n"); +} + +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void) +{ + MV_U32 count, i; + MV_FP_RULE *currRule; + + mvOsPrintf("\nPrinting NFP Rule Database\n"); + count = 0; + + for (i = 0; i < ruleDbSize; i++) { + currRule = ruleDb[i].ruleChain; + + if (currRule != NULL) + mvOsPrintf("\n%03u: FP DB hash=0x%x", count, i); + + while (currRule != NULL) { + mvOsPrintf("\n%03u: Rule=%p: ", count, currRule); + mvFpRulePrint(currRule); + currRule = currRule->next; + count++; + } + } + return MV_OK; +} + +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *dstRule, const MV_FP_RULE *srcRule) +{ + dstRule->mgmtInfo.actionType = srcRule->mgmtInfo.actionType; + dstRule->mgmtInfo.new_count = srcRule->mgmtInfo.new_count; + dstRule->mgmtInfo.old_count = srcRule->mgmtInfo.old_count; + dstRule->mgmtInfo.ruleType = srcRule->mgmtInfo.ruleType; + dstRule->mgmtInfo.snat_aware_refcnt = srcRule->mgmtInfo.snat_aware_refcnt; + dstRule->mgmtInfo.dnat_aware_refcnt = srcRule->mgmtInfo.dnat_aware_refcnt; + + dstRule->routingInfo.aware_flags = srcRule->routingInfo.aware_flags; + dstRule->routingInfo.srcIp = srcRule->routingInfo.srcIp; + dstRule->routingInfo.dstIp = srcRule->routingInfo.dstIp; + dstRule->routingInfo.defGtwIp = srcRule->routingInfo.defGtwIp; + memcpy(dstRule->routingInfo.srcMac, srcRule->routingInfo.srcMac, MV_MAC_ADDR_SIZE); + memcpy(dstRule->routingInfo.dstMac, srcRule->routingInfo.dstMac, MV_MAC_ADDR_SIZE); + dstRule->routingInfo.inIfIndex = srcRule->routingInfo.inIfIndex; + dstRule->routingInfo.outIfIndex = srcRule->routingInfo.outIfIndex; + dstRule->routingInfo.txq = srcRule->routingInfo.txq; + dstRule->routingInfo.dscp = srcRule->routingInfo.dscp; +} + +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while (pRule) { + /* look for a matching rule */ + if ((pRule->routingInfo.dstIp == dstIp) && (pRule->routingInfo.srcIp == srcIp)) + return pRule->mgmtInfo.new_count; + + pRule = pRule->next; + } + return 0; +} + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while (pRule) { + if ((pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp) && + (pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp)) { + + pRule->routingInfo.aware_flags = pSetRule->routingInfo.aware_flags; +#ifdef MV_FP_DEBUG + mvOsPrintf("Update FP aware: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; + } + pRule = pRule->next; + } +#ifdef MV_FP_DEBUG + mvOsPrintf("FP aware NOT found: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_NOT_FOUND; +} + +/* Set a Routing ToS Rule: update an existing rule */ +#ifdef CONFIG_MV_ETH_NFP_TOS +MV_STATUS mvFpToSSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while (pRule) { + if ((pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp && + pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp)) { + pRule->routingInfo.txq = pSetRule->routingInfo.txq; + pRule->routingInfo.dscp = pSetRule->routingInfo.dscp; + nfpRuleUpdateCount++; +#ifdef MV_FP_DEBUG + mvOsPrintf("ToSNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x TOS=0x%x TxQ=%d\n", + nfpRuleUpdateCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, + pRule->routingInfo.dscp, pRule->routingInfo.txq); +#endif + return MV_OK; + } + pRule = pRule->next; + } + return MV_NOT_FOUND; +} +#endif +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + int depth = 0; + MV_FP_RULE *pRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while (pRule) { + if ((pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp && + pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp)) { + + mvFpRuleCopy(pRule, pSetRule); + nfpRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("UpdNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x TOS=0x%x TxQ=%d\n", + nfpRuleUpdateCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, + pRule->routingInfo.dscp, pRule->routingInfo.txq); +#endif + return MV_OK; + } + pRule = pRule->next; + } + + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_RULE)); + if (pNewRule == NULL) { + mvOsPrintf("mvFpRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + mvFpRuleCopy(pNewRule, pSetRule); + pNewRule->next = NULL; + + if (ruleDb[hash_tr].ruleChain == NULL) + ruleDb[hash_tr].ruleChain = pNewRule; + else { + pRule = ruleDb[hash_tr].ruleChain; + while (pRule->next != NULL) { + depth++; + pRule = pRule->next; + } + pRule->next = pNewRule; + } + if (depth > nfpHashMaxDepth) + nfpHashMaxDepth = depth; + nfpRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x, aware=0x%02x\n", + nfpRuleSetCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; +} + +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *currRule, *prevRule; + + nfpRuleDeleteCount++; + hash = mv_jhash_3words(rule->routingInfo.dstIp, rule->routingInfo.srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + prevRule = NULL; + for (currRule = ruleDb[hash_tr].ruleChain; currRule != NULL; prevRule = currRule, currRule = currRule->next) { + if ((currRule->routingInfo.srcIp == rule->routingInfo.srcIp) && + (currRule->routingInfo.dstIp == rule->routingInfo.dstIp)) { + if (prevRule == NULL) + ruleDb[hash_tr].ruleChain = currRule->next; + else + prevRule->next = currRule->next; +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x\n", + nfpRuleDeleteCount, MV_IP_QUAD(currRule->routingInfo.dstIp), + MV_IP_QUAD(currRule->routingInfo.srcIp), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +/* Find and return the first matching rule in the Routing + ARP information table */ +static INLINE MV_FP_RULE *mvFpRuleFind(MV_U32 dstIp, MV_U32 srcIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + int count = 0; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32) 0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + + while (pRule) { + /* look for a matching rule */ + if ((pRule->routingInfo.dstIp == dstIp) && (pRule->routingInfo.srcIp == srcIp)) { + pRule->mgmtInfo.new_count++; + return pRule; + } + pRule = pRule->next; + count++; + } + return NULL; +} + +#ifdef CONFIG_MV_ETH_NFP_FDB +static INLINE MV_U32 mvFpFdbMember(MV_U32 ifIndex) +{ + return (ifIndex < ETH_FP_IFINDEX_MAX) ? fdbMember[ifIndex] : 0; +} + +static MV_FP_FDB_RULE *mvFpFdbLookup(MV_U32 ifIndex, MV_U8 * pDA) +{ + MV_U32 hash, hash_tr; + MV_FP_FDB_RULE *pRule; + MV_U32 bridgeId; + int count = 0; + + if (ifIndex >= ETH_FP_IFINDEX_MAX) + return NULL; + bridgeId = fdbMember[ifIndex]; + if (!(bridgeId)) + return NULL; + + hash = mv_jhash_3words(bridgeId, 0, *(MV_U32 *) (pDA + 2), fp_ip_jhash_iv); + hash_tr = hash & (fdbRuleDbSize - 1); + + pRule = fdbRuleDb[hash_tr].ruleChain; + + while (pRule) { +/* + MV_NFP_DBG("%s: looking %d %02x:%02x:%02x:%02x:%02x:%02x\n", + __FUNCTION__, bridgeId, + pRule->fdbInfo.mac[0], + pRule->fdbInfo.mac[1], + pRule->fdbInfo.mac[2], + pRule->fdbInfo.mac[3], + pRule->fdbInfo.mac[4], + pRule->fdbInfo.mac[5]); +*/ + if ((bridgeId == pRule->fdbInfo.bridge) && + (*((MV_U16 *) (pDA + 0)) == *(MV_U16 *) (&pRule->fdbInfo.mac[0])) && + (*((MV_U16 *) (pDA + 2)) == *(MV_U16 *) (&pRule->fdbInfo.mac[2])) && + (*((MV_U16 *) (pDA + 4)) == *(MV_U16 *) (&pRule->fdbInfo.mac[4]))) { + pRule->mgmtInfo.new_count++; + break; + } + pRule = pRule->next; + count++; + } +/* + if (pRule) + MV_NFP_DBG("%s: lookup bridge=%d %02x:%02x:%02x:%02x:%02x:%02x => if=%d flags=%x\n", + __FUNCTION__, bridgeId, pDA[0],pDA[1],pDA[2],pDA[3],pDA[4],pDA[5], + pRule->fdbInfo.ifIndex, pRule->fdbInfo.flags); + else + MV_NFP_DBG("%s: lookup bridge=%d %02x:%02x:%02x:%02x:%02x:%02x => unknown\n", + __FUNCTION__, bridgeId, pDA[0],pDA[1],pDA[2],pDA[3],pDA[4],pDA[5]); + +*/ + return pRule; +} +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +/* + * PPPoE Support + */ +#ifdef CONFIG_MV_ETH_NFP_PPP +static INLINE void mvFpDecTTL(MV_IP_HEADER *pIpHdr) +{ + MV_U32 check = (MV_U32) pIpHdr->checksum; + check += (MV_U32) htons(0x0100); + pIpHdr->checksum = (MV_U16) (check + (check >= 0xFFFF)); + pIpHdr->ttl--; +} +static INLINE __wsum csum_unfold(__sum16 n) +{ + return (__force __wsum) n; +} + +static INLINE __sum16 csum_fold(__wsum sum) +{ + __asm__("add %0, %1, %1, ror #16 @ csum_fold" : "=r"(sum) + : "r"(sum) + : "cc"); + return (__force __sum16) (~(__force u32) sum >> 16); +} + +__u32 csum_partial(const char *src, int len, __u32 sum); + +static INLINE void mvFpCSumInc(MV_IP_HEADER *pIpHdr, MV_U32 srcIp, MV_U32 newIp) +{ + MV_TCP_HEADER *pTcpHdr; + MV_UDP_HEADER *pUdpHdr; + __be32 diff[] = { ~srcIp, newIp }; + + pIpHdr->checksum = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pIpHdr->checksum))); + + switch (pIpHdr->protocol) { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pTcpHdr->chksum = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pTcpHdr->chksum))); + break; + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pUdpHdr->check = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pUdpHdr->check))); + break; + } +} + +static INLINE MV_U32 mvFpPppLookup(MV_U32 ifIndex) +{ + return pppOpen[ifIndex].pppInfo.if_ppp; +} +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +/* Check that protocol supported for FP NAT and extract srcPort and dstPort + * (or their equivalents) from the packet. + */ +MV_U8 mvFpPortsGet(MV_IP_HEADER *pIpHdr, MV_U16 *pDstPort, MV_U16 *pSrcPort) +{ + MV_U8 proto = pIpHdr->protocol; + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + + switch (proto) { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pTcpHdr->dest; + *pSrcPort = pTcpHdr->source; + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pUdpHdr->dest; + *pSrcPort = pUdpHdr->source; + break; + + /* Other protocols supporting NAT only without ports + * case ???????: + * case ???????: + * *pDstPort = 0; + * *pSrcPort = 0; + * break + * + */ + + default: + /* Skip NAT processing at all */ + proto = MV_IP_PROTO_NULL; + } + return proto; +} + +int mvFpProcess(MV_U32 ifIndex, MV_PKT_INFO *pPkt, MV_IP_HEADER *pIpHdr, MV_FP_STATS *pFpStats) +{ + MV_FP_RULE *pRt; + MV_U32 dip, sip; + MV_U8 proto; + MV_U16 srcPort, dstPort; + MV_STATUS status; +#ifdef CONFIG_MV_ETH_NFP_NAT + MV_FP_NAT_RULE *pDnatRule, *pSnatRule; +#endif /* CONFIG_MV_ETH_NFP_NAT */ +#ifdef CONFIG_MV_ETH_NFP_FDB + MV_FP_FDB_RULE *pFdb; +#endif + MV_U8 *pEth = pPkt->pFrags->bufVirtPtr; +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_BUF_INFO *pBuf = pPkt->pFrags; +#endif +#ifdef CONFIG_MV_ETH_NFP_SEC + MV_NFP_SEC_SPD_RULE *pSpd; + MV_NFP_SEC_SA_ENTRY *pSAEntry; + MV_ESP_HEADER *pEspHdr; +#endif + + MV_NFP_STAT(pFpStats->process++); + + /* Check MAC address: + * WAN - non-promiscous mode. + * Unicast packets - NFP, + * Multicast, Broadcast - Linux + * LAN - Promiscous mode. + * LAN Unicast MAC - NFP, + * Multicast, Broadcast, Unknown Unicast - Linux + */ + if (pEth[ETH_MV_HEADER_SIZE] == 0x01) { + MV_NFP_STAT(pFpStats->multicast++); + return -1; + } +#ifdef CONFIG_MV_ETH_NFP_FDB + if (mvFpFdbMember(ifIndex)) { + pFdb = mvFpFdbLookup(ifIndex, pEth + ETH_MV_HEADER_SIZE); + if (!pFdb) { + MV_NFP_STAT(pFpStats->fdb_rx_unknown++); + return -1; + } + if (pFdb->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + /* DA is local, continue with routing */ + MV_NFP_STAT(pFpStats->fdb_rx_local++); + } else { + /* perform bridging */ + MV_NFP_STAT(pFpStats->fdb_bridged++); + return pFdb->fdbInfo.ifIndex; + } + } +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* Decapsulate PPPoE */ + if (!pIpHdr) { + MV_PPPoE_HEADER *pPPP = (MV_PPPoE_HEADER *) pEth; + if ((pPPP->ethertype == 0x6488) && (pPPP->proto == 0x2100)) { + pIpHdr = (MV_IP_HEADER *) (pEth + ETH_MV_HEADER_SIZE + + sizeof(MV_802_3_HEADER) + ETH_FP_PPPOE_HDR); + + /* do not process fragments */ + if (pIpHdr->fragmentCtrl & 0xFF3F) { + MV_NFP_STAT(pFpStats->ppp_rx_frag++); + goto out; + } + + pBuf->bufAddrShift -= ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr += ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr += ETH_FP_PPPOE_HDR; + pBuf->dataSize -= ETH_FP_PPPOE_HDR; + pEth += ETH_FP_PPPOE_HDR; + + pPkt->status = ETH_TX_IP_NO_FRAG | ETH_TX_GENERATE_IP_CHKSUM_MASK | + (0x5 << ETH_TX_IP_HEADER_LEN_OFFSET); + + switch (pIpHdr->protocol) { + case MV_IP_PROTO_TCP: + pPkt->status |= ETH_TX_L4_TCP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK; + break; + case MV_IP_PROTO_UDP: + pPkt->status |= ETH_TX_L4_UDP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK; + break; + } + + MV_NFP_STAT(pFpStats->ppp_rx++); + MV_NFP_STAT(pFpStats->ethertype_unknown--); + } + } + + if (!pIpHdr) + goto out; +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + proto = mvFpPortsGet(pIpHdr, &dstPort, &srcPort); + + /* Check TTL value */ + if (pIpHdr->ttl <= 1) { + /* TTL expired */ + MV_NFP_STAT(pFpStats->ip_ttl_expired++); + goto out; + } + + dip = pIpHdr->dstIP; + sip = pIpHdr->srcIP; + +#ifdef CONFIG_MV_ETH_NFP_SEC + /* TBD - Add statistics counters */ + /* inbound ipsec traffic */ + if (pIpHdr->protocol == MV_IP_PROTO_ESP) { + + /* extract esp header */ + pEspHdr = (MV_ESP_HEADER *) ((MV_U8 *) pIpHdr + sizeof(MV_IP_HEADER)); + + /* extract SA according to packet spi */ + pSAEntry = mvNfpSecSARuleFind(pEspHdr->spi); + if (pSAEntry != NULL) { + if (MV_OK == mvNfpSecIncoming(pPkt, pSAEntry)) { + MV_NFP_STAT(pFpStats->sec_in++); + return MV_NFP_STOLEN; + } else { + /* TDB- handle pkt gracefully */ + MV_NFP_STAT(pFpStats->sec_in_drop++); + return MV_NFP_DROP; + + } + } + mvOsPrintf("mvFpProcess: no SA found for ESP packet(spi=0x%x)\n", pEspHdr->spi); + } else { + /* outbound */ + pSpd = mvNfpSecSPDRuleFind(dip, sip, proto, dstPort, srcPort, MV_NFP_SEC_RULE_DB_OUT); + if (pSpd != NULL) { + switch (pSpd->actionType) { + case (MV_NFP_SEC_FWD): + break; + case (MV_NFP_SEC_SECURE): + status = mvNfpSecOutgoing(pPkt, pSpd->pSAEntry); + if (status == MV_OK) { + /* handled by cesa */ + MV_NFP_STAT(pFpStats->sec_out++); + return MV_NFP_STOLEN; + } else if (status == MV_OUT_OF_RANGE) { + /* slow path */ + MV_NFP_STAT(pFpStats->sec_out_slow++); + return MV_NFP_NONE; + } else { + /* drop packet */ + MV_NFP_STAT(pFpStats->sec_out_drop++); + return MV_NFP_DROP; + } + break; + case (MV_NFP_SEC_DROP): + MV_NFP_STAT(pFpStats->sec_out_drop++); + return MV_NFP_DROP; + break; + } + } + } +#endif + +#ifdef CONFIG_MV_ETH_NFP_NAT + proto = mvFpPortsGet(pIpHdr, &dstPort, &srcPort); + if (proto == MV_IP_PROTO_NULL) { + /* NAT not supported for this protocol */ + MV_NFP_STAT(pFpStats->nat_bad_proto++); + pDnatRule = NULL; + } else { + /* Lookup NAT database accordingly with 5 tuple key */ + pDnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } + if (pDnatRule != NULL) { + if (pDnatRule->flags & MV_FP_DIP_CMD_MAP) + dip = pDnatRule->newIp; + if (pDnatRule->flags & MV_FP_DPORT_CMD_MAP) + dstPort = pDnatRule->newPort; + } else { + MV_NFP_STAT(pFpStats->dnat_not_found++); + } + +#endif /* CONFIG_MV_ETH_NFP_NAT */ + + pRt = mvFpRuleFind(dip, sip); + if (pRt == NULL) { + /* IP Routing rule is not found: go to Linux IP stack */ + MV_NFP_STAT(pFpStats->route_miss++); + goto out; + } + + MV_NFP_STAT(pFpStats->route_hit++); + +#ifdef CONFIG_MV_ETH_NFP_NAT + if ((pDnatRule != NULL) && (pDnatRule->flags & MV_FP_DNAT_CMD_MAP)) { + MV_NFP_STAT(pFpStats->dnat_found++); + pSnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } else { + pSnatRule = pDnatRule; + } + + if ((pSnatRule != NULL) && (pSnatRule->flags & MV_FP_SNAT_CMD_MAP)) + MV_NFP_STAT(pFpStats->snat_found++); + else + MV_NFP_STAT(pFpStats->snat_not_found++); + + /* Check IP awareness */ + if ((pRt->routingInfo.aware_flags & MV_FP_DIP_CMD_MAP) && (pDnatRule == NULL)) { + MV_NFP_STAT(pFpStats->dnat_aware++); + goto out; + } + + if ((pRt->routingInfo.aware_flags & MV_FP_SIP_CMD_MAP) && (pSnatRule == NULL)) { + MV_NFP_STAT(pFpStats->snat_aware++); + goto out; + } + + /* Update packet accordingly with NAT rules */ + if ((pDnatRule != NULL) || (pSnatRule != NULL)) + mvFpNatPktUpdate(pIpHdr, pDnatRule, pSnatRule); +#endif /* CONFIG_MV_ETH_NFP_NAT */ + + ifIndex = pRt->routingInfo.outIfIndex; + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* Encapsulate PPPoE on Tx */ + if (mvFpPppLookup(ifIndex)) { + if (pBuf->dataSize > 1514 + ETH_MV_HEADER_SIZE - ETH_FP_PPPOE_HDR) { + MV_NFP_STAT(pFpStats->ppp_tx_slow++); + goto out; + } + + MV_NFP_STAT(pFpStats->ppp_tx++); + + /* FIXME: pktSize is left unchanged */ + pBuf->bufAddrShift += ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr -= ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr -= ETH_FP_PPPOE_HDR; + pBuf->dataSize += ETH_FP_PPPOE_HDR; + pEth -= ETH_FP_PPPOE_HDR; + + /* -6B aligment from 32B boundary */ + { + MV_U32 *d = (MV_U32 *) pEth; + MV_U32 *s = pppOpen[ifIndex].pppInfo.u.u32; + + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + } + + /* update payload len */ + *(MV_U16 *) (pEth + 20) = htons(pBuf->dataSize - 14 - ETH_FP_PPPOE_HDR); + + mvFpDecTTL(pIpHdr); +#ifdef CONFIG_MV_ETH_NFP_NAT + if (pSnatRule) + mvFpCSumInc(pIpHdr, pSnatRule->srcIp, pSnatRule->newIp); +#endif + pPkt->status = 0; + ifIndex = pppOpen[ifIndex].pppInfo.if_eth; + + /* invalidate 3rd cacheline */ + pEth = (MV_U32) pEth & ~(CPU_D_CACHE_LINE_SIZE - 1); + pEth += CPU_D_CACHE_LINE_SIZE * 2; + mvOsCacheLineFlushInv(NULL, pEth); + goto end; + } +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + *(MV_U16 *) (pEth + 2) = *(MV_U16 *) (&pRt->routingInfo.dstMac[0]); + *(MV_U32 *) (pEth + 4) = *(MV_U32 *) (&pRt->routingInfo.dstMac[2]); + *(MV_U32 *) (pEth + 8) = *(MV_U32 *) (&pRt->routingInfo.srcMac[0]); + *(MV_U16 *) (pEth + 12) = *(MV_U16 *) (&pRt->routingInfo.srcMac[4]); +#ifdef CONFIG_MV_ETH_NFP_PPP + *(MV_U16 *) (pEth + 14) = 0x0008; +#endif + + pIpHdr->ttl--; + +#ifdef CONFIG_MV_ETH_NFP_TOS + pIpHdr->tos = pRt->routingInfo.dscp; + pPkt->txq = pRt->routingInfo.txq; +#endif + +#ifdef CONFIG_MV_ETH_NFP_FDB + /* find actual port inside bridge, otherwise br->xmit is called */ + if (mvFpFdbMember(ifIndex)) { + pFdb = mvFpFdbLookup(ifIndex, pEth + ETH_MV_HEADER_SIZE); + if (pFdb) { + MV_NFP_STAT(pFpStats->fdb_tx_found++); + return pFdb->fdbInfo.ifIndex; + } + } +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +end: + return ifIndex; +out: +#ifdef CONFIG_MV_ETH_NFP_PPP + /* restore original packet */ + if (pBuf->bufAddrShift) { + pBuf->bufPhysAddr += pBuf->bufAddrShift; + pBuf->bufVirtPtr += pBuf->bufAddrShift; + pBuf->dataSize -= pBuf->bufAddrShift; + pBuf->bufAddrShift = 0; + MV_NFP_STAT(pFpStats->ppp_rx_slow++); + } +#endif + MV_NFP_STAT(pFpStats->slowpath++); + return -1; +} + +void mvFpStatsPrint(MV_FP_STATS *pFpStats) +{ +#ifdef MV_FP_STATISTICS + mvOsPrintf("\n====================================================\n"); + mvOsPrintf(" NFP statistics"); + mvOsPrintf("\n-------------------------------\n"); + + mvOsPrintf("nfp_parsing....................%10u\n", pFpStats->parsing); + mvOsPrintf("nfp_process....................%10u\n", pFpStats->process); + mvOsPrintf("nfp_route_hit..................%10u\n", pFpStats->route_hit); + mvOsPrintf("nfp_route_miss.................%10u\n", pFpStats->route_miss); + mvOsPrintf("nfp_ethertype_unknown..........%10u\n", pFpStats->ethertype_unknown); + mvOsPrintf("nfp_ip_frag....................%10u\n", pFpStats->ip_frag); + mvOsPrintf("nfp_slowpath...................%10u\n", pFpStats->slowpath); + mvOsPrintf("nfp_multicast..................%10u\n", pFpStats->multicast); + mvOsPrintf("nfp_vlan_tagged................%10u\n", pFpStats->vlan_tagged); + mvOsPrintf("nfp_ttl_expired................%10u\n", pFpStats->ip_ttl_expired); + +#ifdef CONFIG_MV_ETH_NFP_NAT + mvOsPrintf("nfp_nat_bad_proto..............%10u\n", pFpStats->nat_bad_proto); + mvOsPrintf("nfp_nat_dnat_found.............%10u\n", pFpStats->dnat_found); + mvOsPrintf("nfp_nat_snat_found.............%10u\n", pFpStats->snat_found); + mvOsPrintf("nfp_nat_dnat_not_found.........%10u\n", pFpStats->dnat_not_found); + mvOsPrintf("nfp_nat_snat_not_found.........%10u\n", pFpStats->snat_not_found); + mvOsPrintf("nfp_nat_dnat_aware.............%10u\n", pFpStats->dnat_aware); + mvOsPrintf("nfp_nat_snat_aware.............%10u\n", pFpStats->snat_aware); +#endif /* CONFIG_MV_ETH_NFP_NAT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB + mvOsPrintf("nfp_fdb_rx_local...............%10u\n", pFpStats->fdb_rx_local); + mvOsPrintf("nfp_fdb_rx_unknown.............%10u\n", pFpStats->fdb_rx_unknown); + mvOsPrintf("nfp_fdb_tx_found...............%10u\n", pFpStats->fdb_tx_found); + mvOsPrintf("nfp_fdb_bridged................%10u\n", pFpStats->fdb_bridged); +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + mvOsPrintf("nfp_ppp_rx.....................%10u\n", pFpStats->ppp_rx); + mvOsPrintf("nfp_ppp_tx.....................%10u\n", pFpStats->ppp_tx); + mvOsPrintf("nfp_ppp_err....................%10u\n", pFpStats->ppp_err); + mvOsPrintf("nfp_ppp_rx_slow................%10u\n", pFpStats->ppp_rx_slow); + mvOsPrintf("nfp_ppp_tx_slow................%10u\n", pFpStats->ppp_tx_slow); + mvOsPrintf("nfp_ppp_rx_frag................%10u\n", pFpStats->ppp_rx_frag); + mvOsPrintf("nfp_ppp_tx_esp.................%10u\n", pFpStats->ppp_tx_esp); + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC + mvOsPrintf("nfp_sec_in.....................%10u\n", pFpStats->sec_in); + mvOsPrintf("nfp_sec_in_drop................%10u\n", pFpStats->sec_in_drop); + mvOsPrintf("nfp_sec_out....................%10u\n", pFpStats->sec_out); + mvOsPrintf("nfp_sec_out_drop...............%10u\n", pFpStats->sec_out_drop); + mvOsPrintf("nfp_sec_out_slow...............%10u\n", pFpStats->sec_out_slow); +#endif /* CONFIG_MV_ETH_NFP_SEC */ + + memset(pFpStats, 0, sizeof(MV_FP_STATS)); +#endif /* MV_FP_STATISTICS */ + + mvOsPrintf("\n"); + mvOsPrintf("Routing rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + nfpRuleSetCount, nfpRuleUpdateCount, nfpRuleDeleteCount, nfpHashMaxDepth); + +#ifdef CONFIG_MV_ETH_NFP_NAT + mvOsPrintf("\n"); + mvOsPrintf("NAT rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + natRuleSetCount, natRuleUpdateCount, natRuleDeleteCount, natHashMaxDepth); +#endif /* CONFIG_MV_ETH_NFP_NAT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB + mvOsPrintf("\n"); + mvOsPrintf("FDB rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + fdbRuleSetCount, fdbRuleUpdateCount, fdbRuleDeleteCount, fdbHashMaxDepth); +#endif /* CONFIG_MV_ETH_NFP_FDB */ +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpFdb.c u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpFdb.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpFdb.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpFdb.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,309 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvFastPath.c - Marvell Fast Route Routing and Bridge +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + +struct fdbRuleHashBucket *fdbRuleDb; +MV_U32 fdbRuleDbSize; +MV_U32 fdbMember[ETH_FP_IFINDEX_MAX]; +MV_U32 fdbRuleUpdateCount = 0; +MV_U32 fdbRuleSetCount = 0; +MV_U32 fdbRuleDeleteCount = 0; +MV_U32 fdbHashMaxDepth; + +MV_STATUS mvFpFdbInit(MV_U32 dbSize) +{ + fdbRuleDb = (struct fdbRuleHashBucket *)mvOsMalloc(sizeof(struct fdbRuleHashBucket) * dbSize); + if (fdbRuleDb == NULL) { + mvOsPrintf("NFP (fdb): not enough memory\n"); + return MV_NO_RESOURCE; + } + fdbRuleDbSize = dbSize; + memset(fdbRuleDb, 0, sizeof(struct fdbRuleHashBucket) * fdbRuleDbSize); + memset(fdbMember, 0, sizeof(fdbMember)); + + mvOsPrintf("NFP (fdb) init %d entries, %d bytes\n", + fdbRuleDbSize, sizeof(struct fdbRuleHashBucket) * fdbRuleDbSize); + return MV_OK; +} + +/* Clear Fast Route Bridge Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpFdbClear(void) +{ + MV_U32 i = fdbRuleDbSize; + MV_FP_FDB_RULE *rule, *tmp; + + if (fdbRuleDb != NULL) + return MV_NOT_INITIALIZED; + + while (i--) { + rule = fdbRuleDb[i].ruleChain; + while (rule) { + tmp = rule; + rule = rule->next; + mvOsFree(tmp); + } + fdbRuleDb[i].ruleChain = NULL; + } + return MV_OK; +} + +void mvFpFdbDestroy(void) +{ + if (fdbRuleDb != NULL) + mvOsFree(fdbRuleDb); +} + +static INLINE int mvFpFdbRuleCmp(MV_FP_RULE_FDB_INFO *rule1, MV_FP_RULE_FDB_INFO *rule2) +{ + return !((rule1->bridge == rule2->bridge) && + (rule1->ifIndex == rule2->ifIndex) && !memcmp(rule1->mac, rule2->mac, 6)); +} + +static INLINE MV_U32 mvFpFdbRuleHash(MV_FP_FDB_RULE *rule) +{ + return mv_jhash_3words(rule->fdbInfo.bridge, 0, *(MV_U32 *) (rule->fdbInfo.mac + 2), fp_ip_jhash_iv); +} + +MV_STATUS mvFpFdbRuleSet(MV_FP_FDB_RULE *newrule) +{ + int depth = 0; + MV_U32 hash; + MV_FP_FDB_RULE *rule; + + /* ignore foreign ifindex */ + if (newrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return MV_OUT_OF_RANGE; + + hash = mvFpFdbRuleHash(newrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &newrule->fdbInfo)) { + fdbRuleUpdateCount++; + goto out; + } + depth++; + rule = rule->next; + } + fdbRuleSetCount++; + if (depth > fdbHashMaxDepth) + fdbHashMaxDepth = depth; + + rule = mvOsMalloc(sizeof(MV_FP_FDB_RULE)); + + if (!rule) { + mvOsPrintf("NFP (fdb): can't allocate new rule\n"); + return MV_FAIL; + } + + /* FIXME: No spinlocks */ + rule->next = fdbRuleDb[hash].ruleChain; + fdbRuleDb[hash].ruleChain = rule; +out: + mvOsMemcpy(rule, newrule, sizeof(MV_FP_FDB_RULE)); + + if (rule->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + fdbMember[rule->fdbInfo.ifIndex] = rule->fdbInfo.bridge; + fdbMember[rule->fdbInfo.bridge] = rule->fdbInfo.bridge; + } + + MV_NFP_DBG("NFP (fdb): new bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], rule->fdbInfo.flags); + + return MV_OK; +} + +MV_STATUS mvFpFdbRuleDel(MV_FP_FDB_RULE *oldrule) +{ + MV_U32 hash; + MV_FP_FDB_RULE *rule, *prev; + + /* ignore foreign ifindex */ + if (oldrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return MV_OUT_OF_RANGE; + + if (oldrule->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + fdbMember[oldrule->fdbInfo.ifIndex] = 0; + fdbMember[oldrule->fdbInfo.bridge] = 0; + MV_NFP_DBG("NFP (fdb): del member bridge=%d ifIndex=%d\n", + oldrule->fdbInfo.bridge, oldrule->fdbInfo.ifIndex); + } + + hash = mvFpFdbRuleHash(oldrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + prev = NULL; + + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &oldrule->fdbInfo)) { + + if (prev) + prev->next = rule->next; + else + fdbRuleDb[hash].ruleChain = rule->next; + + fdbRuleDeleteCount++; + MV_NFP_DBG + ("NFP (fdb): del bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x count=%d\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], + rule->fdbInfo.mac[2], rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); + + mvOsFree(rule); + return MV_OK; + } + + prev = rule; + rule = rule->next; + } + + return MV_NOT_FOUND; +} + +MV_U32 mvFpFdbRuleAge(MV_FP_FDB_RULE *oldrule) +{ + MV_U32 hash, age; + MV_FP_FDB_RULE *rule, *prev; + + /* ignore foreign ifindex */ + if (oldrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return 0; + + hash = mvFpFdbRuleHash(oldrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + prev = NULL; + + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &oldrule->fdbInfo)) { + + MV_NFP_DBG + ("NFP (fdb): age bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x age=%d\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], + rule->fdbInfo.mac[2], rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); + + age = rule->mgmtInfo.new_count; + rule->mgmtInfo.new_count = 0; + return age; + + } + + prev = rule; + rule = rule->next; + } + + return 0; +} + +static void mvFpFdbRulePrint(MV_FP_FDB_RULE *rule, MV_U32 hash) +{ + mvOsPrintf("NFP (fdb): 0x%x bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x count=%d\n", + mvFpFdbRuleHash((MV_FP_FDB_RULE *) rule), + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); +} + +MV_STATUS mvFpFdbPrint(void) +{ + MV_U32 i = fdbRuleDbSize; + MV_FP_FDB_RULE *rule; + + for (i = 0; i < ETH_FP_IFINDEX_MAX; i++) { + if (fdbMember[i]) + mvOsPrintf("NFP (fdb): bridge=%d ifIndex=%d\n", fdbMember[i], i); + } + + for (i = 0; i < fdbRuleDbSize; i++) { + rule = fdbRuleDb[i].ruleChain; + + while (rule) { + mvFpFdbRulePrint(rule, i); + rule = rule->next; + } + } + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfp.h u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfp.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfp.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfp.h 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,577 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.h - Header File for Marvell NFP (Routing and NAT) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing (Routing and NAT). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfp_h__ +#define __mvNfp_h__ + +/* includes */ +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvStack.h" +#include "mv802_3.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthGbe.h" +#include "mvSysHwConfig.h" + +/* defines */ +#define ETH_FP_IFINDEX_MAX 128 +#define ETH_FP_PPPOE_HDR 8 /* PPP header is 6, PPPoE header is 2 */ +#define ETH_FP_MTU (1518 + ETH_MV_HEADER_SIZE) /* maximum frame size incluing MH */ +#define ETH_FP_PPPOE_MTU (ETH_FP_MTU - ETH_FP_PPPOE_HDR) /* maximum frame size for PPPoE */ + +/* uncomment to open some debug prints on adding and updating NFP rules */ +#define MV_FP_DEBUG +#undef MV_FP_DEBUG + +#ifdef MV_FP_DEBUG +# define MV_NFP_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) +#else +# define MV_NFP_DBG(fmt, arg...) +#endif + +#ifdef MV_FP_STATISTICS +# define MV_NFP_STAT(CODE) CODE; +#else +# define MV_NFP_STAT(CODE) +#endif + +/* enumerations */ +typedef enum { + MV_FP_ROUTE_CMD, /* perform NFP routing */ + MV_FP_DROP_CMD, /* drop packet */ + MV_FP_TO_STACK_CMD, /* pass packet to linux stack */ + MV_FP_DIP_CMD, /* replace DIP */ + MV_FP_SIP_CMD, /* replace SIP */ + MV_FP_DPORT_CMD, /* replace DPORT */ + MV_FP_SPORT_CMD, /* replace SPORT */ + MV_FP_BRIDGE_CMD, /* perform fast path bridging */ + MV_FP_PPP_CMD, /* perform fast path pppoe */ +} MV_FP_CMD_TYPE; + +typedef enum { + MV_NFP_DROP = -3, + MV_NFP_STOLEN = -2, + MV_NFP_NONE = -1, + /* positive values are valid */ +} MV_NFP_IF_INDEX; + +#define MV_FP_NULL_BINDING 0 +#define MV_FP_NULL_BINDING_SET (1 << MV_FP_ROUTE_CMD) + +#define MV_FP_DIP_CMD_MAP (1 << MV_FP_DIP_CMD) +#define MV_FP_DPORT_CMD_MAP (1 << MV_FP_DPORT_CMD) +#define MV_FP_DNAT_CMD_MAP (MV_FP_DIP_CMD_MAP | MV_FP_DPORT_CMD_MAP) + +#define MV_FP_SIP_CMD_MAP (1 << MV_FP_SIP_CMD) +#define MV_FP_SPORT_CMD_MAP (1 << MV_FP_SPORT_CMD) +#define MV_FP_SNAT_CMD_MAP (MV_FP_SIP_CMD_MAP | MV_FP_SPORT_CMD_MAP) + +typedef enum { + MV_FP_STATIC_RULE, /* a static rule created by the user */ + MV_FP_DYNAMIC_RULE /* a dynamic rule */ +} MV_FP_RULE_TYPE; + +/* structure definitions (used by the NFP Manager and the NFP Database)*/ +typedef struct { + MV_FP_CMD_TYPE actionType; + MV_U32 old_count; + int new_count; + MV_FP_RULE_TYPE ruleType; + int dnat_aware_refcnt; + int snat_aware_refcnt; + +} MV_FP_RULE_MGMT_INFO; + +typedef struct { + MV_U32 dstIp; + MV_U32 srcIp; + MV_U32 defGtwIp; + MV_U8 dscp; + MV_U8 txq; + MV_U16 reserved1; + MV_U8 reserved2; + MV_U8 aware_flags; + /* dstMac should be 2 byte aligned */ + MV_U8 dstMac[MV_MAC_ADDR_SIZE]; + MV_U8 srcMac[MV_MAC_ADDR_SIZE]; + MV_U8 inIfIndex; /* Linux interface index */ + MV_U8 outIfIndex; /* Linux interface index */ +} MV_FP_RULE_ROUTING_INFO; + +typedef struct _mv_fp_rule { + struct _mv_fp_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_ROUTING_INFO routingInfo; + +} MV_FP_RULE; + +struct ruleHashBucket { + MV_FP_RULE *ruleChain; /* This is an entry in the rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +#define MV_JHASH_MIX(a, b, c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + +/* The golden ration: an arbitrary value */ +#define MV_JHASH_GOLDEN_RATIO 0x9e3779b9 + +extern MV_U32 fp_ip_jhash_iv; + +static INLINE MV_U32 mv_jhash_3words(MV_U32 a, MV_U32 b, MV_U32 c, MV_U32 initval) +{ + a += MV_JHASH_GOLDEN_RATIO; + b += MV_JHASH_GOLDEN_RATIO; + c += initval; + MV_JHASH_MIX(a, b, c); + + return c; +} + +#ifdef CONFIG_MV_ETH_NFP_NAT + +typedef struct _mv_fp_nat_rule { + struct _mv_fp_nat_rule *next; + MV_U32 old_count; + MV_U32 new_count; + + /* Original packet information */ + /* Fields will contain invalid values if they are irrelevant */ + MV_U32 srcIp; + MV_U32 dstIp; + MV_U16 srcPort; + MV_U16 dstPort; + MV_U8 proto; + + /* NAT information */ + MV_U8 flags; + MV_U32 newIp; + MV_U16 newPort; + +} MV_FP_NAT_RULE; + +struct natRuleHashBucket { + MV_FP_NAT_RULE *natRuleChain; /* This is an entry in the NAT rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +extern struct natRuleHashBucket *natRuleDb; +extern MV_U32 natRuleDbSize; +extern MV_U32 natRuleUpdateCount, natRuleSetCount, natRuleDeleteCount; +extern MV_U32 natHashMaxDepth; + +#endif /* CONFIG_MV_ETH_NFP_NAT */ + +/* + * PPPoE Support + */ +#ifdef CONFIG_MV_ETH_NFP_PPP + +typedef struct { + MV_U16 tag; + MV_U8 da[MV_MAC_ADDR_SIZE]; + MV_U8 sa[MV_MAC_ADDR_SIZE]; + MV_U16 ethertype; + MV_U8 version; + MV_U8 code; + MV_U16 session; + MV_U16 len; + MV_U16 proto; +} __attribute__ ((packed)) MV_PPPoE_HEADER; + +typedef struct { + union { + MV_PPPoE_HEADER ppp; + MV_U32 u32[6]; + } u; + MV_U32 if_ppp; /* e.g. ppp0 */ + MV_U32 if_eth; /* e.g. eth0 */ + MV_U32 channel; +} MV_FP_RULE_PPP_INFO; + +typedef struct _mv_fp_ppp_rule { + struct _mv_fp_ppp_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_PPP_INFO pppInfo; + +} MV_FP_PPP_RULE; + +extern MV_FP_PPP_RULE pppOpen[]; + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +/* + * 802.1D Support + */ +#ifdef CONFIG_MV_ETH_NFP_FDB + +#define MV_FP_FDB_IS_LOCAL 1 + +typedef struct { + MV_U16 flags; + MV_U8 mac[6]; + MV_U32 ifIndex; + MV_U32 bridge; +} MV_FP_RULE_FDB_INFO; + +typedef struct _mv_fp_fdb_rule { + struct _mv_fp_fdb_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_FDB_INFO fdbInfo; + +} MV_FP_FDB_RULE; + +struct fdbRuleHashBucket { + MV_FP_FDB_RULE *ruleChain; +}; + +extern struct fdbRuleHashBucket *fdbRuleDb; +extern MV_U32 fdbRuleDbSize; +extern MV_U32 fdbMember[]; +extern MV_U32 fdbRuleUpdateCount, fdbRuleSetCount, fdbRuleDeleteCount; +extern MV_U32 fdbHashMaxDepth; + +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +typedef struct { + MV_U32 parsing; + MV_U32 process; + MV_U32 route_miss; + MV_U32 route_hit; + MV_U32 ip_ttl_expired; + MV_U32 slowpath; + MV_U32 multicast; + MV_U32 ethertype_unknown; + MV_U32 ip_frag; + MV_U32 vlan_tagged; + +#ifdef CONFIG_MV_ETH_NFP_NAT + MV_U32 nat_bad_proto; + MV_U32 dnat_aware; + MV_U32 snat_aware; + MV_U32 dnat_found; + MV_U32 snat_found; + MV_U32 dnat_not_found; + MV_U32 snat_not_found; +#endif /* CONFIG_MV_ETH_NFP_NAT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB + MV_U32 fdb_rx_local; + MV_U32 fdb_rx_unknown; + MV_U32 fdb_tx_found; + MV_U32 fdb_bridged; +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_U32 ppp_rx; + MV_U32 ppp_rx_slow; + MV_U32 ppp_rx_frag; + MV_U32 ppp_tx; + MV_U32 ppp_tx_slow; + MV_U32 ppp_tx_esp; + MV_U32 ppp_err; +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC + MV_U32 sec_in; + MV_U32 sec_in_drop; + MV_U32 sec_out; + MV_U32 sec_out_drop; + MV_U32 sec_out_slow; +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +} MV_FP_STATS; + +static INLINE MV_IP_HEADER *mvFpParsing(MV_PKT_INFO *pPktInfo, MV_FP_STATS *pFpStats) +{ + MV_U8 *pData; + MV_IP_HEADER *pIpHdr; + MV_U32 tx_status; + + pData = (MV_U8 *) pPktInfo->pFrags[0].bufVirtPtr + ETH_MV_HEADER_SIZE; + + MV_NFP_STAT(pFpStats->parsing++); + + /* Check LLC/SNAP and IP header */ + if (((pPktInfo->status & ETH_RX_NOT_LLC_SNAP_FORMAT_MASK) == 0) || + ((pPktInfo->status & ETH_RX_IP_HEADER_OK_MASK) == 0)) { + /* Non IP packet: go to Linux IP stack */ + MV_NFP_STAT(pFpStats->ethertype_unknown++); + return NULL; + } + + if (pPktInfo->fragIP) { + MV_NFP_STAT(pFpStats->ip_frag++); + return NULL; + } + + tx_status = (ETH_TX_GENERATE_IP_CHKSUM_MASK | ETH_TX_IP_NO_FRAG | (5 << ETH_TX_IP_HEADER_LEN_OFFSET)); + + /* Calculate start of IP header */ + if ((pPktInfo->status & ETH_RX_VLAN_TAGGED_FRAME_MASK)) { + MV_NFP_STAT(pFpStats->vlan_tagged++); + pIpHdr = (MV_IP_HEADER *) (pData + sizeof(MV_802_3_HEADER) + MV_VLAN_HLEN); + tx_status |= ETH_TX_VLAN_TAGGED_FRAME_MASK; + } else { + pIpHdr = (MV_IP_HEADER *) (pData + sizeof(MV_802_3_HEADER)); + } + + if ((pPktInfo->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_TCP_TYPE) + tx_status |= (ETH_TX_L4_TCP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + else if ((pPktInfo->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_UDP_TYPE) + tx_status |= (ETH_TX_L4_UDP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + + pPktInfo->status = tx_status; + + return pIpHdr; +} + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize); +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void); +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void); +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void); +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *newRule, const MV_FP_RULE *srcRule); +/* Get the maximum count value for a rule with srcIp == given ip */ +MV_U32 mvFpMaxArpCountGet(MV_U32 ip); +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp); +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *rule); +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule); +/* Set a Routing ToS Rule */ +MV_STATUS mvFpToSSet(MV_FP_RULE *rule); +/* Print a Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule); +/* Enable NFP */ +void mvFpEnable(void); +/* Give all packets to Linux IP stack */ +void mvFpDisable(void); +MV_STATUS mvFpInit(void); +int mvFpProcess(MV_U32 ifIndex, MV_PKT_INFO *pPkt, MV_IP_HEADER *pIpHdr, MV_FP_STATS *pFpStats); +void mvFpStatsPrint(MV_FP_STATS *pFpStats); + +/* NAT SUPPORT Functions */ + +#ifdef CONFIG_MV_ETH_NFP_NAT +/* Find and return the first matching rule */ +static INLINE MV_FP_NAT_RULE *mvFpNatRuleFind(MV_U32 dstIp, MV_U32 srcIp, MV_U8 proto, MV_U16 dport, MV_U16 sport) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule; + int count = 0; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32) ((dport << 16) | sport), + (MV_U32) ((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); +/* + mvOsPrintf("mvFpNatRuleFind: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%08x (0x%x)\n", + dstIp, srcIp, proto, dport, sport, hash, hash_tr); +*/ + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule) { + /* look for a matching rule */ + if ((pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && (pNatRule->dstPort == dport) && (pNatRule->srcPort == sport)) { + pNatRule->new_count++; + return pNatRule; + } + pNatRule = pNatRule->next; + count++; + } + return NULL; +} + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize); + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void); + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void); + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *natRule); + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule); + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule); + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto); + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void); + +/* Print a NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule); + +/* Extract dstPort and srcPort values from the packet */ +MV_U8 mvFpNatPortsGet(MV_IP_HEADER *pIpHdr, MV_U16 *pDstPort, MV_U16 *pSrcPort); + +int mvFpNatPktUpdate(MV_IP_HEADER *pIpHdr, MV_FP_NAT_RULE *pDnatRule, MV_FP_NAT_RULE *pSnatRule); + +#endif /* CONFIG_MV_ETH_NFP_NAT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB + +/* Init NFP Bridge Rule Database */ +MV_STATUS mvFpFdbInit(MV_U32 dbSize); + +/* Clear NFP Bridge Rule Database */ +MV_STATUS mvFpFdbClear(void); + +/* Destroy NFP Bridge Rule Database */ +void mvFpFdbDestroy(void); + +/* Add NFP Bridge Rule */ +MV_STATUS mvFpFdbRuleSet(MV_FP_FDB_RULE *rule); + +/* Delete NFP Bridge Rule Database */ +MV_STATUS mvFpFdbRuleDel(MV_FP_FDB_RULE *rule); + +/* Aging NFP Bridge Rule Database */ +MV_U32 mvFpFdbRuleAge(MV_FP_FDB_RULE *rule); + +/* Print NFP Bridge Rule Database */ +MV_STATUS mvFpFdbPrint(void); + +#endif /* CONFIG_MV_ETH_NFP_FDB */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + +/* Init NFP PPPoE Rule Database */ +MV_STATUS mvFpPppInit(void); + +/* Clear NFP PPPoE Rule Database */ +MV_STATUS mvFpPppClear(void); + +/* Destroy NFP PPPoE Rule Database */ +void mvFpPppDestroy(void); + +/* Add NFP PPPoE Rule */ +MV_STATUS mvFpPppRuleSet(MV_FP_PPP_RULE *rule); + +/* Delete NFP PPPoE Rule Database */ +MV_STATUS mvFpPppRuleDel(MV_FP_PPP_RULE *rule); + +/* Aging NFP PPPoE Rule Database */ +MV_U32 mvFpPppRuleAge(MV_FP_PPP_RULE *rule); + +/* Print NFP PPPoE Rule Database */ +MV_STATUS mvFpPppPrint(void); + +/* Add PPPoE header */ +int mvFpPPPoE(MV_U32 ifIndex, MV_PKT_INFO *pPkt, MV_FP_STATS *pFpStats); + +/* Get physical interface the PPP runs over */ +MV_U32 mvFpPppPhyIf(MV_U32 ifIndex); + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC +MV_VOID mvNfpSecDbPrint(MV_VOID); +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +#endif /* __mvNfp_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpNat.c u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpNat.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpNat.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpNat.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,365 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvTypes.h" +#include "mvOs.h" +#include "mvStack.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + +struct natRuleHashBucket *natRuleDb; +MV_U32 natRuleDbSize; + +MV_U32 natRuleUpdateCount = 0; +MV_U32 natRuleSetCount = 0; +MV_U32 natRuleDeleteCount = 0; +MV_U32 natHashMaxDepth = 0; + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize) +{ + natRuleDb = (struct natRuleHashBucket *)mvOsMalloc(sizeof(struct natRuleHashBucket) * dbSize); + if (natRuleDb == NULL) { + mvOsPrintf("NFP NAT Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + natRuleDbSize = dbSize; + memset(natRuleDb, 0, sizeof(struct natRuleHashBucket) * natRuleDbSize); + + natRuleSetCount = natRuleDeleteCount = natRuleUpdateCount = 0; + + mvOsPrintf("mvFpNatDb (%p): %d entries, %d bytes\n", + natRuleDb, natRuleDbSize, sizeof(struct natRuleHashBucket) * natRuleDbSize); + + return MV_OK; +} + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void) +{ + MV_U32 i = 0; + MV_FP_NAT_RULE *currRule; + MV_FP_NAT_RULE *tmpRule; + + if (natRuleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < natRuleDbSize; i++) { + currRule = natRuleDb[i].natRuleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + natRuleDb[i].natRuleChain = NULL; + } + return MV_OK; +} + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void) +{ + if (natRuleDb != NULL) + mvOsFree(natRuleDb); +} + +static void mvFpNatRuleUpdate(MV_FP_NAT_RULE *dstRule, const MV_FP_NAT_RULE *srcRule) +{ + dstRule->flags = srcRule->flags; + dstRule->newIp = srcRule->newIp; + dstRule->newPort = srcRule->newPort; + dstRule->new_count = srcRule->new_count; + dstRule->old_count = srcRule->old_count; +} + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *pSetRule) +{ + int depth = 0; + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->dstIp, pSetRule->srcIp, + (MV_U32) ((pSetRule->dstPort << 16) | pSetRule->srcPort), + (MV_U32) ((fp_ip_jhash_iv << 8) | pSetRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule) { + /* look for a matching rule */ + if ((pNatRule->dstIp == pSetRule->dstIp) && + (pNatRule->srcIp == pSetRule->srcIp) && + (pNatRule->proto == pSetRule->proto) && + (pNatRule->dstPort == pSetRule->dstPort) && (pNatRule->srcPort == pSetRule->srcPort)) { + /* update rule */ + mvFpNatRuleUpdate(pNatRule, pSetRule); + natRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf + ("UpdNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleUpdateCount, pNatRule->dstIp, pNatRule->srcIp, pNatRule->proto, + MV_16BIT_BE(pNatRule->dstPort), MV_16BIT_BE(pNatRule->srcPort), hash_tr, pNatRule->flags); +#endif + return MV_OK; + } + pNatRule = pNatRule->next; + } + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_NAT_RULE)); + if (pNewRule == NULL) { + mvOsPrintf("mvFpNatRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + + memcpy(pNewRule, pSetRule, sizeof(*pNewRule)); + pNewRule->next = NULL; + + if (natRuleDb[hash_tr].natRuleChain == NULL) { + natRuleDb[hash_tr].natRuleChain = pNewRule; + } else { + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule->next != NULL) { + depth++; + pNatRule = pNatRule->next; + } + + pNatRule->next = pNewRule; + } + if (depth > natHashMaxDepth) + natHashMaxDepth = depth; + + natRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleSetCount, pNewRule->dstIp, pNewRule->srcIp, pNewRule->proto, + MV_16BIT_BE(pNewRule->dstPort), MV_16BIT_BE(pNewRule->srcPort), hash_tr, pNewRule->flags); +#endif + return MV_OK; +} + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *currRule, *prevRule; + + natRuleDeleteCount++; + + hash = mv_jhash_3words(natRule->dstIp, natRule->srcIp, + (MV_U32) ((natRule->dstPort << 16) | natRule->srcPort), + (MV_U32) ((fp_ip_jhash_iv << 8) | natRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + + prevRule = NULL; + for (currRule = natRuleDb[hash_tr].natRuleChain; + currRule != NULL; prevRule = currRule, currRule = currRule->next) { + if (currRule->srcIp == natRule->srcIp && + currRule->dstIp == natRule->dstIp && + currRule->srcPort == natRule->srcPort && + currRule->dstPort == natRule->dstPort && currRule->proto == natRule->proto) { + if (prevRule == NULL) + natRuleDb[hash_tr].natRuleChain = currRule->next; + else + prevRule->next = currRule->next; + +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x\n", + natRuleDeleteCount, currRule->dstIp, currRule->srcIp, currRule->proto, + MV_16BIT_BE(currRule->dstPort), MV_16BIT_BE(currRule->srcPort), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +int mvFpNatPktUpdate(MV_IP_HEADER *pIpHdr, MV_FP_NAT_RULE *pDnatRule, MV_FP_NAT_RULE *pSnatRule) +{ + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + MV_ICMP_ECHO_HEADER *pIcmpHdr; + int hdr_size = 0; + MV_U16 *pDstPort = NULL, *pSrcPort = NULL; + + switch (pIpHdr->protocol) { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pTcpHdr->dest; + pSrcPort = &pTcpHdr->source; + hdr_size = sizeof(MV_TCP_HEADER); + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pUdpHdr->dest; + pSrcPort = &pUdpHdr->source; + hdr_size = sizeof(MV_UDP_HEADER); + break; + + case MV_IP_PROTO_ICMP: + pIcmpHdr = (MV_ICMP_ECHO_HEADER *) ((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + if ((pIcmpHdr->type == MV_ICMP_ECHO) || (pIcmpHdr->type == MV_ICMP_ECHOREPLY)) { + pDstPort = &pIcmpHdr->id; + pSrcPort = &pIcmpHdr->id; + hdr_size = sizeof(MV_ICMP_ECHO_HEADER); + } else { + mvOsPrintf("Wrong ICMP type: 0x%x\n", pIcmpHdr->type & 0xFF); + } + break; + + case MV_IP_PROTO_ZERO_HOP: + /* Do nothing - only IP addresses are updated for this protocol */ + break; + + default: + mvOsPrintf("Unexpected IP protocol: 0x%x\n", pIpHdr->protocol); + } + if (pDnatRule != NULL) { + if (pDnatRule->flags & MV_FP_DIP_CMD_MAP) + pIpHdr->dstIP = pDnatRule->newIp; + if ((pDnatRule->flags & MV_FP_DPORT_CMD_MAP) && (pDstPort != NULL)) + *pDstPort = pDnatRule->newPort; + } + + if (pSnatRule != NULL) { + if (pSnatRule->flags & MV_FP_SIP_CMD_MAP) + pIpHdr->srcIP = pSnatRule->newIp; + + if ((pSnatRule->flags & MV_FP_SPORT_CMD_MAP) && (pSrcPort != NULL)) + *pSrcPort = pSnatRule->newPort; + } + return hdr_size; +} + +/* Print a NFP NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule) +{ + /* Note: some of the fields in the NAT rule may contain invalid values */ + mvOsPrintf("Original packet: "); + mvOsPrintf("SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->srcIp)), mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->dstIp)), mvOsPrintf(", SPort=%d", MV_16BIT_BE(rule->srcPort)); + mvOsPrintf(", DPort=%d", MV_16BIT_BE(rule->dstPort)); + mvOsPrintf("\nNAT Info: "); + mvOsPrintf("count=%u, flags=0x%x", rule->new_count, rule->flags); + mvOsPrintf(", newIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->newIp)); + mvOsPrintf(", newPort=%d", MV_16BIT_BE(rule->newPort)); + mvOsPrintf("\n"); +} + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void) +{ + MV_U32 count, i = 0; + MV_FP_NAT_RULE *currRule; + + mvOsPrintf("\nPrinting NFP NAT Rule Database: \n"); + count = 0; + for (i = 0; i < natRuleDbSize; i++) { + currRule = natRuleDb[i].natRuleChain; + + if (currRule != NULL) + mvOsPrintf("\n%03u: NAT DB hash=0x%x\n", count, i); + + while (currRule != NULL) { + if ((currRule->flags != MV_FP_NULL_BINDING) || (currRule->new_count > 0)) { + mvOsPrintf("%03u: Rule=%p, Next=%p\n", count, currRule, currRule->next); + mvFpNatRulePrint(currRule); + } + currRule = currRule->next; + count++; + } + } + return MV_OK; +} + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32) ((dstPort << 16) | srcPort), + (MV_U32) ((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule) { + /* look for a matching rule */ + if ((pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && (pNatRule->dstPort == dstPort) && (pNatRule->srcPort == srcPort)) { + return pNatRule->new_count; + } + pNatRule = pNatRule->next; + } + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpPpp.c u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpPpp.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpPpp.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpPpp.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,317 @@ +/******************************************************************************* +Copyright (C) Marvell Interpppional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interpppional Ltd. and/or its affiliates ("Marvell") under the following +alterpppive licensing terms. Once you have made an election to distribute the +File under one of the following license alterpppives, please (i) delete this +introductory statement regarding license alterpppives, (ii) delete the two +license alterpppives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvPPP.c - Marvell Fast Route PPP Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvTypes.h" +#include "mvOs.h" +#include "mvStack.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + +#define MACFMT "%02X:%02X:%02X:%02X:%02X:%02X" +#define MACSTR(m) m[0], m[1], m[2], m[3], m[4], m[5] + +MV_FP_PPP_RULE pppOpen[ETH_FP_IFINDEX_MAX]; /* connected pppoe sessions */ +MV_FP_PPP_RULE pppHalf[ETH_FP_IFINDEX_MAX]; /* half-open pppoe connections */ + +MV_STATUS mvFpPppInit(void) +{ + memset(pppOpen, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + memset(pppHalf, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + + mvOsPrintf("NFP (pppoe) init %d entries, %d bytes\n", ETH_FP_IFINDEX_MAX, + 2 * sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + return MV_OK; +} + +/* Clear Fast Route Bridge Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpPppClear(void) +{ + memset(pppOpen, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + return MV_OK; +} + +void mvFpPppDestroy(void) +{ + mvFpPppClear(); +} + +void mvFpPppRulePrint(char *text, MV_FP_PPP_RULE * rule) +{ + mvOsPrintf("NFP (pppoe): ppp %s (%s) if_ppp=%u if_eth=%u session=%u DA=" MACFMT " SA=" MACFMT " %x\n", + text, rule->pppInfo.if_ppp ? "open" : "half", + rule->pppInfo.if_ppp, + rule->pppInfo.if_eth, + rule->pppInfo.u.ppp.session, + MACSTR(rule->pppInfo.u.ppp.da), MACSTR(rule->pppInfo.u.ppp.sa), rule->pppInfo.channel); +} + +MV_STATUS mvFpPppRuleSet(MV_FP_PPP_RULE *rule) +{ + int if_ppp = rule->pppInfo.if_ppp; + int i = ETH_FP_IFINDEX_MAX; + +#ifdef MV_FP_DEBUG + mvFpPppRulePrint("new", rule); +#endif + + /* half open */ + if (!if_ppp) { + memcpy(&pppHalf[rule->pppInfo.if_eth], rule, sizeof(MV_FP_PPP_RULE)); + } else + while (i--) { + /* look for channel id match */ + if (pppHalf[i].pppInfo.channel == rule->pppInfo.channel) { + memcpy(&pppOpen[if_ppp], &pppHalf[i], sizeof(MV_FP_PPP_RULE)); + memset(&pppHalf[i], 0, sizeof(MV_FP_PPP_RULE)); + pppOpen[if_ppp].pppInfo.if_ppp = if_ppp; + break; + } + } + + return MV_OK; +} + +MV_STATUS mvFpPppRuleDel(MV_FP_PPP_RULE *rule) +{ + int i = ETH_FP_IFINDEX_MAX; + +#ifdef MV_FP_DEBUG + mvOsPrintf("NFP (pppoe): del ppp channel %x\n", rule->pppInfo.channel); +#endif + + while (i--) { + if (pppOpen[i].pppInfo.channel == rule->pppInfo.channel) { + mvFpPppRulePrint("del", &pppOpen[i]); + pppOpen[i].pppInfo.if_ppp = 0; + memset(&pppOpen[i], 0, sizeof(MV_FP_PPP_RULE)); + break; + } + } + + return MV_OK; +} + +MV_U32 mvFpPppRuleAge(MV_FP_PPP_RULE *rule) +{ + return MV_OK; +} + +MV_STATUS mvFpPppPrint(void) +{ + int i = ETH_FP_IFINDEX_MAX; + + while (i--) { + if (pppOpen[i].pppInfo.if_eth) + mvFpPppRulePrint("", &pppOpen[i]); + + if (pppHalf[i].pppInfo.if_eth) + mvFpPppRulePrint("", &pppHalf[i]); + + } + + return MV_OK; +} + +MV_U32 mvFpPppPhyIf(MV_U32 ifIndex) +{ + if (pppOpen[ifIndex].pppInfo.if_ppp) + return pppOpen[ifIndex].pppInfo.if_eth; + return ETH_FP_IFINDEX_MAX; +} + +/* IP header csum calculation */ +static inline unsigned short from32to16(unsigned long x) +{ + /* add up 16-bit and 16-bit for 16+c bit */ + x = (x & 0xffff) + (x >> 16); + /* add up carry.. */ + x = (x & 0xffff) + (x >> 16); + return x; +} + +static unsigned long do_csum(char *buff, int len) +{ + int odd, count; + unsigned long result = 0; + + if (len <= 0) + goto out; + odd = 1 & (unsigned long)buff; + if (odd) { + result = *buff; + len--; + buff++; + } + count = len >> 1; /* nr of 16-bit words.. */ + if (count) { + if (2 & (unsigned long)buff) { + result += *(unsigned short *)buff; + count--; + len -= 2; + buff += 2; + } + count >>= 1; /* nr of 32-bit words.. */ + if (count) { + unsigned long carry = 0; + do { + unsigned long w = *(unsigned long *)buff; + count--; + buff += 4; + result += carry; + result += w; + carry = (w > result); + } while (count); + result += carry; + result = (result & 0xffff) + (result >> 16); + } + if (len & 2) { + result += *(unsigned short *)buff; + buff += 2; + } + } + if (len & 1) + result += (*buff << 8); + result = from32to16(result); + if (odd) + result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); +out: + return result; +} + +static INLINE void mvFpCSumIP(MV_IP_HEADER *pIpHdr) +{ + pIpHdr->checksum = 0; + pIpHdr->checksum = ~do_csum((char *)pIpHdr, 20 /*iph->ihl */); +} + +static INLINE MV_U32 mvFpPppLookup(MV_U32 ifIndex) +{ + return pppOpen[ifIndex].pppInfo.if_ppp; +} + +/* NFP bottom half */ +int mvFpPPPoE(MV_U32 ifIndex, MV_PKT_INFO *pPkt, MV_FP_STATS *pFpStats) +{ + MV_U8 *pEth = pPkt->pFrags->bufVirtPtr; + MV_BUF_INFO *pBuf = pPkt->pFrags; + + MV_NFP_STAT(pFpStats->ppp_tx_esp++); + + /* Encapsulate PPPoE on Tx */ + if (!mvFpPppLookup(ifIndex)) { + MV_NFP_STAT(pFpStats->ppp_err++); + return MV_FAIL; + } + + if (pBuf->dataSize > ETH_FP_PPPOE_MTU) { + /* Bad, we check size in the mvNfpSecOutgoing() --BK */ + mvOsPrintf("PPPoE oversize %d > %d\n", pBuf->dataSize, ETH_FP_PPPOE_MTU); + MV_NFP_STAT(pFpStats->ppp_err++); + return MV_FAIL; + } + + pBuf->bufAddrShift += ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr -= ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr -= ETH_FP_PPPOE_HDR; + pBuf->dataSize += ETH_FP_PPPOE_HDR; + pEth -= ETH_FP_PPPOE_HDR; + + /* -6B aligment from 32B boundary */ + { + MV_U32 *d = (MV_U32 *) pEth; + MV_U32 *s = pppOpen[ifIndex].pppInfo.u.u32; + + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + } + + /* update payload len */ + *(MV_U16 *) (pEth + 20) = htons(pBuf->dataSize - 14 - ETH_FP_PPPOE_HDR); + + /* recalculate IP csum in sw */ + mvFpCSumIP((MV_IP_HEADER *) (pEth + 24)); + pPkt->status = 0; + + /* flush two cachelines */ + mvOsCacheLineFlushInv(NULL, pEth); + mvOsCacheLineFlushInv(NULL, pEth + 32); + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpSec.c u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpSec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpSec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpSec.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,581 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpSec.c - Marvell Network Fast Processing with IPSec(Routing only) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" +#include "eth/nfp/mvNfpSec.h" +#include "cesa/mvCesa.h" + +/* IPSec SA & SPD DBs */ +MV_NFP_SEC_SPD_RULE *spdInDb; +MV_NFP_SEC_SPD_RULE *spdOutDb; +MV_NFP_SEC_SA_ENTRY *saInDb; +MV_NFP_SEC_SA_ENTRY *saOutDb; + +static MV_CESA_MBUF cesaMbufArray[MV_NFP_SEC_Q_SIZE]; +static MV_CESA_COMMAND cesaCmdArray[MV_NFP_SEC_Q_SIZE]; +static MV_NFP_SEC_CESA_PRIV cesaPrivArray[MV_NFP_SEC_Q_SIZE + MV_NFP_SEC_REQ_Q_SIZE]; +static int cesaCmdIndx; /* static variable initialized automatically to 0 */ +static int cesaPrivIndx; /* static variable initialized automatically to 0 */ + +static MV_U32 spdInRuleCount; +static MV_U32 spdOutRuleCount; +static MV_U32 saInEntryCount; +static MV_U32 saOutEntryCount; +static MV_U32 secDbSize; + +extern int cesaReqResources; + +MV_STATUS mvNfpSecInit(MV_U32 dbSize) +{ + if (dbSize == 0) + return MV_BAD_PARAM; + + spdInDb = (struct _mv_nfp_sec_spd_rule *)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_spd_rule))); + spdOutDb = (struct _mv_nfp_sec_spd_rule *)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_spd_rule))); + saInDb = (struct _mv_nfp_sec_sa_entry *)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_sa_entry))); + saOutDb = (struct _mv_nfp_sec_sa_entry *)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_sa_entry))); + + if ((spdInDb == NULL) || (spdOutDb == NULL) || (saInDb == NULL) || (saOutDb == NULL)) { + mvOsPrintf("NFP-IPSec Rules DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + + secDbSize = dbSize; + spdInRuleCount = spdOutRuleCount = saInEntryCount = saOutEntryCount = 0; + + memset(spdInDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_spd_rule))); + memset(spdOutDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_spd_rule))); + memset(saInDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_sa_entry))); + memset(saOutDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_sa_entry))); + + return MV_OK; + +} + +MV_STATUS mvNfpSecDbClear(MV_VOID) +{ + MV_U32 i; + MV_NFP_SEC_SPD_RULE *pCurrSpdInRule, *pCurrSpdOutRule; + MV_NFP_SEC_SA_ENTRY *pCurrSAInEntery, *pCurrSAOutEntery; + + if ((spdInDb == NULL) && (spdOutDb == NULL) && (saInDb == NULL) && (saOutDb == NULL)) + return MV_NOT_INITIALIZED; + + /* assume all 4 DBs are initialized */ + for (i = 0; i < secDbSize; i++) { + pCurrSpdInRule = (spdInDb + i); + pCurrSpdOutRule = (spdOutDb + i); + pCurrSAInEntery = (saInDb + i); + pCurrSAOutEntery = (saOutDb + i); + mvOsFree(pCurrSpdInRule); + mvOsFree(pCurrSpdOutRule); + mvOsFree(pCurrSAInEntery); + mvOsFree(pCurrSAOutEntery); + } + + spdInDb = spdOutDb = NULL; + saInDb = saOutDb = NULL; + + return MV_OK; +} + +static INLINE MV_VOID mvNfpSecClearRange(MV_U8 *addr, MV_U32 size) +{ + MV_U32 i; + MV_U8 *align; + + align = (MV_U8 *) ((MV_U32) addr & ~0x1f); + + for (i = 0; align <= (addr + size); align += CPU_D_CACHE_LINE_SIZE) + mvOsCacheLineFlushInv(NULL, align); +} + +static INLINE MV_VOID mvNfpSecInvRange(MV_U8 *addr, MV_U32 size) +{ + MV_U32 i; + MV_U8 *align; + + align = (MV_U8 *) ((MV_U32) addr & ~0x1f); + + for (i = 0; align <= (addr + size); align += CPU_D_CACHE_LINE_SIZE) + mvOsCacheLineInv(NULL, align); +} + +/****************************************************/ +/* warning: need to replace DB list with hash table */ +/****************************************************/ +MV_NFP_SEC_SPD_RULE *mvNfpSecSPDRuleSet(MV_NFP_SEC_SPD_RULE *pSpdRule, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + MV_NFP_SEC_SPD_RULE *pCurrSpdRule; + MV_U32 currRuleIndex = 0, spdRuleCount; + + pCurrSpdRule = (inOut ? spdOutDb : spdInDb); + spdRuleCount = (inOut ? spdOutRuleCount : spdInRuleCount); + + if (spdRuleCount >= secDbSize) + return NULL; + + /* search if rule already exists */ + while (currRuleIndex < spdRuleCount) { + if ((pCurrSpdRule->sIp == pSpdRule->sIp) && (pCurrSpdRule->dIp == pSpdRule->dIp) +#ifdef MV_NFP_SEC_5TUPLE_KEY_SUPPORT + && (pCurrSpdRule->proto == pSpdRule->proto) && + (pCurrSpdRule->srcPort == pSpdRule->srcPort) && (pCurrSpdRule->dstPort == pSpdRule->dstPort) +#endif + ) { + /* rule exists - return */ + return pCurrSpdRule; + } + currRuleIndex++; + pCurrSpdRule++; + } + + pCurrSpdRule = (inOut ? (spdOutDb + spdRuleCount) : (spdInDb + spdRuleCount));; + memcpy(pCurrSpdRule, pSpdRule, sizeof(struct _mv_nfp_sec_spd_rule)); + inOut ? spdOutRuleCount++ : spdInRuleCount++; + + return pCurrSpdRule; + +} + +MV_NFP_SEC_SA_ENTRY *mvNfpSecSAEntrySet(MV_NFP_SEC_SA_ENTRY *pSAEntry, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + + MV_NFP_SEC_SA_ENTRY *pCurrSAEntery; + MV_U32 currEntryIndex = 0, saEntryCount; + + pCurrSAEntery = (inOut ? saOutDb : saInDb); + saEntryCount = (inOut ? saOutEntryCount : saInEntryCount); + + if (saEntryCount >= secDbSize) + return NULL; + + /* search if rule already exists */ + while (currEntryIndex < saEntryCount) { + if (pCurrSAEntery->spi == pSAEntry->spi) { + /* rule exists - return */ + return pCurrSAEntery; + } + currEntryIndex++; + pCurrSAEntery++; + } + + pCurrSAEntery = (inOut ? (saOutDb + saEntryCount) : (saInDb + saEntryCount)); + memcpy(pCurrSAEntery, pSAEntry, sizeof(struct _mv_nfp_sec_sa_entry)); + inOut ? saOutEntryCount++ : saInEntryCount++; + + return pCurrSAEntery; + +} + +MV_STATUS mvNfpSecOutCheck(MV_PKT_INFO *pPktInfo) +{ + if (pPktInfo->pFrags->dataSize > MV_NFP_SEC_MAX_PACKET) + return MV_OUT_OF_RANGE; + return MV_OK; +} + +INLINE MV_STATUS mvNfpSecInCheck(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + /* TBD - sequence number */ + return MV_OK; +} + +MV_NFP_SEC_SPD_RULE *mvNfpSecSPDRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + MV_NFP_SEC_SPD_RULE *pCurrSpdRule; + MV_U32 currRuleIndex = 0, spdRuleCount; + + pCurrSpdRule = (inOut ? spdOutDb : spdInDb); + spdRuleCount = (inOut ? spdOutRuleCount : spdInRuleCount); + + /* SPD DB is empty */ + if (!spdRuleCount) + return NULL; + + /* scan IN/OUT SPD database for matching rule */ + while (currRuleIndex < spdRuleCount) { + if ((pCurrSpdRule->sIp == srcIp) && (pCurrSpdRule->dIp == dstIp) +#ifdef MV_NFP_SEC_5TUPLE_KEY_SUPPORT + && (pCurrSpdRule->proto == proto) + (pCurrSpdRule->srcPort == sport) && (pCurrSpdRule->dstPort == dport) +#endif + ) { + /* rule found - return */ + return pCurrSpdRule; + } + currRuleIndex++; + pCurrSpdRule++; + } + + return NULL; + +} + +INLINE MV_VOID mvNfpSecBuildMac(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + MV_802_3_HEADER *pMacHdr; + + pMacHdr = (MV_802_3_HEADER *) ((MV_U8 *) (pPktInfo->pFrags[0].bufVirtPtr)); + memcpy(pMacHdr, &pSAEntry->tunnelHdr.dstMac, 12); + pMacHdr->typeOrLen = 0x08; /* stands for IP protocol code 16bit swapped */ + return; +} + +INLINE MV_VOID mvNfpSecBuildIPTunnel(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + MV_IP_HEADER *pIpHdr, *pIntIpHdr; + MV_U16 newIpTotalLength; + + newIpTotalLength = pPktInfo->pFrags[0].dataSize - sizeof(MV_802_3_HEADER); + + pIpHdr = (MV_IP_HEADER *) (pPktInfo->pFrags[0].bufVirtPtr + sizeof(MV_802_3_HEADER)); + pIntIpHdr = (MV_IP_HEADER *) ((MV_U8 *) (pIpHdr) + sizeof(MV_IP_HEADER) + sizeof(MV_ESP_HEADER) + + pSAEntry->ivSize); + + /* TBD - review below settings in RFC */ + pIpHdr->version = 0x45; + pIpHdr->tos = 0; + pIpHdr->checksum = 0; + pIpHdr->totalLength = MV_16BIT_BE(newIpTotalLength); + pIpHdr->identifier = 0; + pIpHdr->fragmentCtrl = 0; + pIpHdr->ttl = pIntIpHdr->ttl - 1; + pIpHdr->protocol = MV_IP_PROTO_ESP; + pIpHdr->srcIP = pSAEntry->tunnelHdr.sIp; + pIpHdr->dstIP = pSAEntry->tunnelHdr.dIp; + + pPktInfo->status = ETH_TX_IP_NO_FRAG | ETH_TX_GENERATE_IP_CHKSUM_MASK | (0x5 << ETH_TX_IP_HEADER_LEN_OFFSET); + + return; +} + +/* Append sequence number and spi, save some space for IV */ +INLINE MV_VOID mvNfpSecBuildEspHdr(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + MV_ESP_HEADER *pEspHdr; + + pEspHdr = (MV_ESP_HEADER *) (pPktInfo->pFrags[0].bufVirtPtr + sizeof(MV_802_3_HEADER) + sizeof(MV_IP_HEADER)); + pEspHdr->spi = pSAEntry->spi; + pSAEntry->seqNum = (pSAEntry->seqNum++); + pEspHdr->seqNum = MV_32BIT_BE(pSAEntry->seqNum); +} + +MV_STATUS mvNfpSecEspProcess(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + MV_CESA_COMMAND *pCesaCmd; + MV_CESA_MBUF *pCesaMbuf; + MV_NFP_SEC_CESA_PRIV *pCesaPriv; + MV_STATUS status; + MV_IP_HEADER *pIpHdr; + MV_BUF_INFO *pBuf; + + pCesaCmd = &cesaCmdArray[cesaCmdIndx]; + pCesaMbuf = &cesaMbufArray[cesaCmdIndx]; + cesaCmdIndx++; + cesaCmdIndx %= MV_NFP_SEC_Q_SIZE; + pCesaPriv = &cesaPrivArray[cesaPrivIndx++]; + cesaPrivIndx = cesaPrivIndx % (MV_NFP_SEC_Q_SIZE + MV_NFP_SEC_REQ_Q_SIZE); + + pCesaPriv->pPktInfo = pPktInfo; + pCesaPriv->pSaEntry = pSAEntry; + pCesaPriv->pCesaCmd = pCesaCmd; + + /* + * Fix, encrypt/decrypt the IP payload only, --BK 20091027 + */ + pBuf = pPktInfo->pFrags; + pIpHdr = (MV_IP_HEADER *) (pBuf->bufVirtPtr + sizeof(MV_802_3_HEADER)); + pBuf->dataSize = MV_16BIT_BE(pIpHdr->totalLength) + sizeof(MV_802_3_HEADER); + + pBuf->bufVirtPtr += MV_NFP_SEC_ESP_OFFSET; + pBuf->bufPhysAddr += MV_NFP_SEC_ESP_OFFSET; + pBuf->dataSize -= MV_NFP_SEC_ESP_OFFSET; + pBuf->bufAddrShift -= MV_NFP_SEC_ESP_OFFSET; + + pCesaMbuf->pFrags = pPktInfo->pFrags; + pCesaMbuf->numFrags = 1; + pCesaMbuf->mbufSize = pBuf->dataSize; + + pCesaCmd->pReqPrv = (MV_VOID *) pCesaPriv; + pCesaCmd->sessionId = pSAEntry->sid; + pCesaCmd->pSrc = pCesaMbuf; + pCesaCmd->pDst = pCesaMbuf; + pCesaCmd->skipFlush = MV_TRUE; + + /* Assume ESP */ + pCesaCmd->cryptoOffset = sizeof(MV_ESP_HEADER) + pSAEntry->ivSize; + pCesaCmd->cryptoLength = pBuf->dataSize - (sizeof(MV_ESP_HEADER) + + pSAEntry->ivSize + pSAEntry->digestSize); + pCesaCmd->ivFromUser = 0; /* relevant for encode only */ + pCesaCmd->ivOffset = sizeof(MV_ESP_HEADER); + pCesaCmd->macOffset = 0; + pCesaCmd->macLength = pBuf->dataSize - pSAEntry->digestSize; + pCesaCmd->digestOffset = pBuf->dataSize - pSAEntry->digestSize; + + /* save original digest in case of decrypt+auth */ + if (pSAEntry->secOp == MV_NFP_SEC_DECRYPT) { + memcpy(pCesaPriv->orgDigest, (pBuf->bufVirtPtr + pCesaCmd->digestOffset), pSAEntry->digestSize); + mvNfpSecInvRange((pBuf->bufVirtPtr + pCesaCmd->digestOffset), pSAEntry->digestSize); + } + + pSAEntry->stats.bytes += pBuf->dataSize; + if (pSAEntry->secOp == MV_NFP_SEC_DECRYPT) + pSAEntry->stats.decrypt++; + else + pSAEntry->stats.encrypt++; + + disable_irq(CESA_IRQ); + status = mvCesaAction(pCesaCmd); + enable_irq(CESA_IRQ); + if (status != MV_OK) { + pSAEntry->stats.rejected++; + mvOsPrintf("%s: mvCesaAction failed %d\n", __func__, status); + } + + return status; +} + +MV_STATUS mvNfpSecOutgoing(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + MV_U8 *pTmp; + MV_U32 cryptoSize, encBlockMod, dSize; + MV_BUF_INFO *pBuf = pPktInfo->pFrags; + + /* CESA Q is full drop. */ + if (cesaReqResources <= 1) { + pSAEntry->stats.rejected++; + return MV_NO_RESOURCE; + } + + /* encrypt payload */ + cryptoSize = pBuf->dataSize - sizeof(MV_802_3_HEADER) - ETH_MV_HEADER_SIZE; + + /* ignore Marvell header */ + pBuf->dataSize -= ETH_MV_HEADER_SIZE; + pBuf->bufVirtPtr += ETH_MV_HEADER_SIZE; + pBuf->bufPhysAddr += ETH_MV_HEADER_SIZE; + pBuf->bufAddrShift -= ETH_MV_HEADER_SIZE; + + /* Align buffer address to beginning of new packet - TBD handle VLAN tag, LLC */ + dSize = pSAEntry->ivSize + sizeof(MV_ESP_HEADER) + sizeof(MV_IP_HEADER); + pBuf->bufVirtPtr -= dSize; + pBuf->bufPhysAddr -= dSize; + pBuf->dataSize += dSize; + pBuf->bufAddrShift += dSize; + + encBlockMod = (cryptoSize % MV_NFP_SEC_ENC_BLOCK_SIZE); + /* leave space for padLen + Protocol */ + if (encBlockMod > 14) { + encBlockMod = MV_NFP_SEC_ENC_BLOCK_SIZE - encBlockMod; + encBlockMod += MV_NFP_SEC_ENC_BLOCK_SIZE; + } else + encBlockMod = MV_NFP_SEC_ENC_BLOCK_SIZE - encBlockMod; + + /* expected frame size */ + dSize = pBuf->dataSize + encBlockMod + pSAEntry->digestSize; + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* keep enough room for PPPoE header */ + if (ETH_FP_IFINDEX_MAX != mvFpPppPhyIf(pSAEntry->tunnelHdr.outIfIndex)) + dSize += ETH_FP_PPPOE_HDR; +#endif + + if (dSize > ETH_FP_MTU - ETH_MV_HEADER_SIZE) + goto rollback; + + pBuf->dataSize += encBlockMod; + pTmp = pBuf->bufVirtPtr + pBuf->dataSize; + memset(pTmp - encBlockMod, 0, encBlockMod - 2); + *((MV_U8 *) (pTmp - 2)) = (MV_U8) (encBlockMod - 2); + *((MV_U8 *) (pTmp - 1)) = (MV_U8) 4; + mvNfpSecClearRange(pTmp - encBlockMod, encBlockMod); + + pBuf->dataSize += pSAEntry->digestSize; + mvNfpSecBuildEspHdr(pPktInfo, pSAEntry); + mvNfpSecBuildIPTunnel(pPktInfo, pSAEntry); + mvNfpSecBuildMac(pPktInfo, pSAEntry); + + /* flush & invalidate new MAC, IP, & ESP headers + old ip */ + dSize = pBuf->bufAddrShift + sizeof(MV_IP_HEADER) + sizeof(MV_802_3_HEADER); + mvNfpSecClearRange(pBuf->bufVirtPtr, dSize); + + return mvNfpSecEspProcess(pPktInfo, pSAEntry); + +rollback: + /* slow path */ + pBuf->bufPhysAddr += pBuf->bufAddrShift; + pBuf->bufVirtPtr += pBuf->bufAddrShift; + pBuf->dataSize -= pBuf->bufAddrShift; + pBuf->bufAddrShift = 0; + + pSAEntry->stats.rejected++; + return MV_OUT_OF_RANGE; +} + +MV_STATUS mvNfpSecIncoming(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + + MV_BUF_INFO *pBuf = pPktInfo->pFrags; + MV_U32 invSize; + + /* CESA Q is full drop. */ + if (cesaReqResources <= 1) { + pSAEntry->stats.rejected++; + return MV_NO_RESOURCE; + } + + /* TBD - duplicate invalidatation */ + if (MV_OK != mvNfpSecInCheck(pPktInfo, pSAEntry)) { + pSAEntry->stats.rejected++; + return MV_ERROR; + } + + /* ignore Marvell header */ + pBuf->dataSize -= ETH_MV_HEADER_SIZE; + pBuf->bufVirtPtr += ETH_MV_HEADER_SIZE; + pBuf->bufPhysAddr += ETH_MV_HEADER_SIZE; + pBuf->bufAddrShift -= ETH_MV_HEADER_SIZE; + + /* update buffer address shift value */ + /* tracked by bufAddrShift, --BK 091022 */ + /* pBuf->bufAddrShift -= (pSAEntry->ivSize + sizeof(MV_ESP_HEADER) + sizeof(MV_IP_HEADER)); */ + + /* invalidate MAC, IP & ESP headers */ + invSize = sizeof(MV_802_3_HEADER) + sizeof(MV_IP_HEADER) + sizeof(MV_ESP_HEADER); + mvNfpSecInvRange(pBuf->bufVirtPtr, invSize); + + return mvNfpSecEspProcess(pPktInfo, pSAEntry); +} + +MV_NFP_SEC_SA_ENTRY *mvNfpSecSARuleFind(MV_U32 spiPkt) +{ + MV_NFP_SEC_SA_ENTRY *pCurrSAEntery = saInDb; + MV_U32 currEntryIndex = 0; + + while (currEntryIndex < saInEntryCount) { + if (pCurrSAEntery->spi == spiPkt) + return pCurrSAEntery; + currEntryIndex++; + pCurrSAEntery++; + } + + return NULL; + +} + +MV_VOID mvNfpSecSaPrint(MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + mvDebugPrintIpAddr(MV_32BIT_BE(pSAEntry->tunnelHdr.sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(pSAEntry->tunnelHdr.dIp)); + mvOsPrintf(" out_if=%d da=", pSAEntry->tunnelHdr.outIfIndex); + mvDebugPrintMacAddr(pSAEntry->tunnelHdr.dstMac); + mvOsPrintf(" spi=0x%x", MV_32BIT_BE(pSAEntry->spi)); + + if (pSAEntry) + mvOsPrintf("\tstats: encrypt:%d decrypt:%d reject:%d drop:%d bytes:%d", + pSAEntry->stats.encrypt, pSAEntry->stats.decrypt, + pSAEntry->stats.rejected, pSAEntry->stats.dropped, pSAEntry->stats.bytes); + mvOsPrintf("\n"); +} + +MV_VOID mvNfpSecDbPrint(MV_VOID) +{ + MV_U32 i; + + mvOsPrintf("NFP IPSec:\n"); + + for (i = 0; i < spdInRuleCount; i++) { + mvOsPrintf("inbound[%d] ", i); + mvDebugPrintIpAddr(MV_32BIT_BE(spdInDb[i].sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(spdInDb[i].dIp)); + mvOsPrintf(" "); + mvNfpSecSaPrint(spdInDb[i].pSAEntry); + } + for (i = 0; i < spdOutRuleCount; i++) { + mvOsPrintf("outbound[%d] ", i); + mvDebugPrintIpAddr(MV_32BIT_BE(spdOutDb[i].sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(spdOutDb[i].dIp)); + mvOsPrintf(" "); + mvNfpSecSaPrint(spdOutDb[i].pSAEntry); + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpSec.h u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpSec.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth/nfp/mvNfpSec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth/nfp/mvNfpSec.h 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,191 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpSec.h - Header File for Marvell NFP IPSec (Routing only) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing with IPSec(Routing only). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfpSec_h__ +#define __mvNfpSec_h__ + +#ifdef CONFIG_MV_ETH_NFP_SEC + +#include "mvCommon.h" +#include "cesa/mvCesa.h" + +/* IPSec defines */ +#define MV_NFP_SEC_MAX_PACKET 1540 +#define MV_NFP_SEC_ENC_BLOCK_SIZE 16 + +#define MV_NFP_SEC_ESP_OFFSET 34 + +/* IPSec Enumerators */ +typedef enum { + MV_NFP_SEC_TUNNEL = 0, + MV_NFP_SEC_TRANSPORT, +} MV_NFP_SEC_PROT; + +typedef enum { + MV_NFP_SEC_ESP = 0, + MV_NFP_SEC_AH, +} MV_NFP_SEC_ENCAP; + +typedef enum { + MV_NFP_SEC_RULE_DB_IN = 0, + MV_NFP_SEC_RULE_DB_OUT, +} MV_NFP_SEC_RULE_DB_DIR; + +typedef enum { + MV_NFP_SEC_DROP = 0, + MV_NFP_SEC_FWD, + MV_NFP_SEC_SECURE +} MV_NFP_SEC_ACTION; + +typedef enum { + MV_NFP_SEC_ENCRYPT = 0, + MV_NFP_SEC_DECRYPT, +} MV_NFP_SEC_OP; + +typedef struct _mv_nfp_sa_stats { + MV_U32 encrypt; + MV_U32 decrypt; + MV_U32 rejected; /* slow path */ + MV_U32 dropped; /* packet drop */ + MV_U32 bytes; +} MV_NFP_SA_STATS; + +/* IPSec Structures */ +typedef struct _mv_nfp_sec_tunnel_hdr { + MV_U32 sIp; /* BE */ + MV_U32 dIp; /* BE */ + /* dstMac should be 2 byte aligned */ + MV_U8 dstMac[MV_MAC_ADDR_SIZE]; /* BE */ + MV_U8 srcMac[MV_MAC_ADDR_SIZE]; /* BE */ + MV_U8 outIfIndex; +} MV_NFP_SEC_TUNNEL_HDR; + +typedef struct _mv_nfp_sec_sa_entry { + MV_U32 spi; /* BE */ + MV_NFP_SEC_PROT tunProt; + MV_NFP_SEC_ENCAP encap; + MV_U16 sid; + MV_U32 seqNum; /* LE */ + MV_NFP_SEC_TUNNEL_HDR tunnelHdr; + MV_U32 lifeTime; + MV_U8 ivSize; + MV_U8 cipherBlockSize; + MV_U8 digestSize; + MV_NFP_SEC_OP secOp; + MV_NFP_SA_STATS stats; +} MV_NFP_SEC_SA_ENTRY; + +typedef struct _mv_nfp_sec_spd_rule { + MV_U32 sIp; /* BE */ + MV_U32 dIp; /* BE */ + MV_U8 proto; + MV_U16 dstPort; /* BE */ + MV_U16 srcPort; /* BE */ + MV_NFP_SEC_ACTION actionType; + MV_NFP_SEC_SA_ENTRY *pSAEntry; +} MV_NFP_SEC_SPD_RULE; + +typedef struct _mv_nfp_sec_cesa_priv { + MV_NFP_SEC_SA_ENTRY *pSaEntry; + MV_PKT_INFO *pPktInfo; + MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; + MV_CESA_COMMAND *pCesaCmd; +} MV_NFP_SEC_CESA_PRIV; + +MV_NFP_SEC_SPD_RULE *mvNfpSecSPDRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_STATUS mvNfpSecOutCheck(MV_PKT_INFO *pPktInfo); + +MV_STATUS mvNfpSecOutgoing(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry); + +MV_STATUS mvNfpSecEspProcess(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry); + +MV_NFP_SEC_SA_ENTRY *mvNfpSecSARuleFind(MV_U32 spiPkt); + +MV_STATUS mvNfpSecIncoming(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY *pSAEntry); + +MV_NFP_SEC_SPD_RULE *mvNfpSecSPDRuleSet(MV_NFP_SEC_SPD_RULE *pSpdRule, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_NFP_SEC_SA_ENTRY *mvNfpSecSAEntrySet(MV_NFP_SEC_SA_ENTRY *pSAEntry, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_STATUS mvNfpSecInit(MV_U32 dbSize); /* global init */ + +MV_VOID mvNfpSecDbPrint(MV_VOID); + +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +#endif /* __mvNfpSec_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvCompVer.txt 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhy.c u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhy.c --- u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhy.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhy.c 2011-04-04 13:57:34.975596868 -0400 @@ -0,0 +1,1623 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysEthPhyConfig.h" +#include "mvEthPhyRegs.h" +#include "mvEthPhy.h" + +static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable); + +static MV_ETHPHY_HAL_DATA ethphyHalData; + +/******************************************************************************* +* mvEthPhyHalInit - +* +* DESCRIPTION: +* Initialize the ethernet phy unit HAL. +* +* INPUT: +* halData - Ethernet PHY HAL data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvEthPhyHalInit(MV_ETHPHY_HAL_DATA *halData) +{ + mvOsMemcpy(ðphyHalData, halData, sizeof(MV_ETHPHY_HAL_DATA)); + + return MV_OK; +} +/******************************************************************************* +* mvEthPhyInit - +* +* DESCRIPTION: +* Initialize the ethernet phy unit. +* +* INPUT: +* ethPortNum - The port number on which to initialize the PHY. +* eeeEnable - Whether to enable EEE or not. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvEthPhyInit(MV_U32 ethPortNum, MV_BOOL eeeEnable) +{ + MV_U32 phyAddr = 0; + MV_U16 deviceId; + MV_U16 id1, id2; + + if (ethPortNum != ((MV_U32) -1)) + phyAddr = ethphyHalData.phyAddr[ethPortNum]; + + /* Set page as 0 */ + if (mvEthPhyRegWrite(phyAddr, 22, 0) != MV_OK) + return MV_ERROR; + + /* Reads ID1 */ + if (mvEthPhyRegRead(phyAddr, 2, &id1) != MV_OK) + return MV_ERROR; + + /* Reads ID2 */ + if (mvEthPhyRegRead(phyAddr, 3, &id2) != MV_OK) + return MV_ERROR; + + if (!MV_IS_MARVELL_OUI(id1, id2)) { + mvOsPrintf("Cannot find Marvell Device id1 %x id2 %x\n", id1, id2); + return MV_ERROR; + } + + deviceId = (id2 & 0x3F0) >> 4; + switch (deviceId) { + case MV_PHY_88E1116: + case MV_PHY_88E1116R: + mvEthE1116PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E3061: + mvEthE3016PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E1111: + mvEthE1111PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E1112: + mvEthE1112PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E1011: + mvEthE1011PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E1121: + mvEth1121PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E114X: + mvEth1145PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E154X: + case MV_PHY_88E1340M: /* BUG IN THE 1543 IS RETURNING THE 1340 ID FOR PORTS 3-4 */ + /* case MV_PHY_KW2_INTERNAL_GE: + if (ethPortNum != ((MV_U32) -1)) + mvEthInternalGEPhyBasicInit(ethPortNum); + else + */ + mvEth1540PhyBasicInit(ethPortNum, eeeEnable); + break; + case MV_PHY_88E1340S: + case MV_PHY_88E1340: + mvEth1340PhyBasicInit(); + break; + case MV_PHY_88E1310: + mvEthE1310PhyBasicInit(ethPortNum); + break; + case MV_PHY_88E104X: + case MV_PHY_88E10X0: + case MV_PHY_88E10X0S: + case MV_PHY_88E3082: + case MV_PHY_88E1149: + case MV_PHY_88E1181: + case MV_PHY_88E3016_88E3019: + case MV_PHY_88E1240: + case MV_PHY_88E1149R: + case MV_PHY_88E1119R: + default: + mvOsPrintf("Unknown Device(%#x). Initialization failed\n", deviceId); + return MV_ERROR; + } + return MV_OK; +} + +void rdPhy(MV_U32 phyAddr, MV_U32 regOffs) +{ + MV_U16 data; + MV_STATUS status; + + status = mvEthPhyRegRead(phyAddr, regOffs, &data); + if (status == MV_OK) + mvOsPrintf("reg=%d: 0x%04x\n", regOffs, data); + else + mvOsPrintf("Read failed\n"); +} + + +/******************************************************************************* +* mvEthPhyRegRead - Read from ethernet phy register. +* +* DESCRIPTION: +* This function reads ethernet phy register. +* +* INPUT: +* phyAddr - Phy address. +* regOffs - Phy register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit phy register value, or 0xffff on error +* +*******************************************************************************/ +MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data) +{ + MV_U32 smiReg; + volatile MV_U32 timeout; + + /* check parameters */ + if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK) { + mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY device address %d\n", + phyAddr); + return MV_FAIL; + } + if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK) { + mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY register offset %d\n", + regOffs); + return MV_FAIL; + } + + timeout = ETH_PHY_TIMEOUT; + /* wait till the SMI is not busy*/ + do { + /* read smi register */ + smiReg = MV_REG_READ(ETH_PHY_SMI_REG); + if (timeout-- == 0) { + mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n"); + return MV_FAIL; + } + } while (smiReg & ETH_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and read opcode */ + smiReg = (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS)| + ETH_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg); + + timeout = ETH_PHY_TIMEOUT; + + /*wait till readed value is ready */ + do { + /* read smi register */ + smiReg = MV_REG_READ(ETH_PHY_SMI_REG); + + if (timeout-- == 0) { + mvOsPrintf("mvEthPhyRegRead: SMI read-valid timeout\n"); + return MV_FAIL; + } + } while (!(smiReg & ETH_PHY_SMI_READ_VALID_MASK)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < ETH_PHY_TIMEOUT; timeout++) + ; + + *data = (MV_U16)(MV_REG_READ(ETH_PHY_SMI_REG) & ETH_PHY_SMI_DATA_MASK); + + return MV_OK; +} + +/******************************************************************************* +* mvEthPhyRegWrite - Write to ethernet phy register. +* +* DESCRIPTION: +* This function write to ethernet phy register. +* +* INPUT: +* phyAddr - Phy address. +* regOffs - Phy register offset. +* data - 16bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if write succeed, MV_BAD_PARAM on bad parameters , MV_ERROR on error . +* MV_TIMEOUT on timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data) +{ + MV_U32 smiReg; + volatile MV_U32 timeout; + + /* check parameters */ + if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK) { + mvOsPrintf("mvEthPhyRegWrite: Err. Illegal phy address \n"); + return MV_BAD_PARAM; + } + if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK) { + mvOsPrintf("mvEthPhyRegWrite: Err. Illegal register offset \n"); + return MV_BAD_PARAM; + } + + timeout = ETH_PHY_TIMEOUT; + + /* wait till the SMI is not busy*/ + do { + /* read smi register */ + smiReg = MV_REG_READ(ETH_PHY_SMI_REG); + if (timeout-- == 0) { + mvOsPrintf("mvEthPhyRegWrite: SMI busy timeout\n"); + return MV_TIMEOUT; + } + } while (smiReg & ETH_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and write opcode and data*/ + smiReg = (data << ETH_PHY_SMI_DATA_OFFS); + smiReg |= (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS); + smiReg &= ~ETH_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthPhyReset - Reset ethernet Phy. +* +* DESCRIPTION: +* This function resets a given ethernet Phy. +* +* INPUT: +* phyAddr - Phy address. +* timeout - in millisec +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_TIMEOUT - Timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout) +{ + MV_U16 phyRegData; + + /* Reset the PHY */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + /* Set bit 15 to reset the PHY */ + phyRegData |= ETH_PHY_CTRL_RESET_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + /* Wait untill Reset completed */ + while (timeout > 0) { + mvOsSleep(100); + timeout -= 100; + + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + if ((phyRegData & ETH_PHY_CTRL_RESET_MASK) == 0) + return MV_OK; + } + return MV_TIMEOUT; +} + + +/******************************************************************************* +* mvEthPhyRestartAN - Restart ethernet Phy Auto-Negotiation. +* +* DESCRIPTION: +* This function resets a given ethernet Phy. +* +* INPUT: +* phyAddr - Phy address. +* timeout - in millisec; 0 - no timeout (don't wait) +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_TIMEOUT - Timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout) +{ + MV_U16 phyRegData; + + /* Reset the PHY */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + /* Set bit 12 to Enable autonegotiation of the PHY */ + phyRegData |= ETH_PHY_CTRL_AN_ENABLE_MASK; + + /* Set bit 9 to Restart autonegotiation of the PHY */ + phyRegData |= ETH_PHY_CTRL_AN_RESTART_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + if (timeout == 0) + return MV_OK; + + /* Wait untill Auotonegotiation completed */ + while (timeout > 0) { + mvOsSleep(100); + timeout -= 100; + + if (mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + if (phyRegData & ETH_PHY_STATUS_AN_DONE_MASK) + return MV_OK; + } + return MV_TIMEOUT; +} + + +/******************************************************************************* +* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex +* +* DESCRIPTION: +* This function disable AN and set duplex and speed. +* +* INPUT: +* phyAddr - Phy address. +* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps +* duplex - port duplex. 0 - Half duplex, 1 - Full duplex +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_FAIL - Failure +* +*******************************************************************************/ +MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex) +{ + MV_U16 phyRegData; + + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + switch (speed) { + case 0: /* 10 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 1: /* 100 Mbps */ + phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 2: /* 1000 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + default: + mvOsOutput("Unexpected speed = %d\n", speed); + return MV_FAIL; + } + + switch (duplex) { + case 0: /* half duplex */ + phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK; + break; + + case 1: /* full duplex */ + phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK; + break; + + default: + mvOsOutput("Unexpected duplex = %d\n", duplex); + } + /* Clear bit 12 to Disable autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK; + + /* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + return MV_OK; +} + +MV_STATUS mvEthPhyLoopback(MV_U32 phyAddr, MV_BOOL isEnable) +{ + MV_U16 regVal, ctrlVal; + MV_STATUS status; + + /* Set loopback speed and duplex accordingly with current */ + /* Bits: 6, 8, 13 */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &ctrlVal) != MV_OK) + return MV_FAIL; + + if (isEnable) { + /* Select page 2 */ + mvEthPhyRegWrite(phyAddr, 22, 2); + + mvEthPhyRegRead(phyAddr, 21, ®Val); + regVal &= ~(ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK | + ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK); + regVal |= (ctrlVal & (ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK | + ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK)); + mvEthPhyRegWrite(phyAddr, 21, regVal); + + /* Select page 0 */ + mvEthPhyRegWrite(phyAddr, 22, 0); + + /* Disable Energy detection R16[9:8] = 00 */ + /* Disable MDI/MDIX crossover R16[6:5] = 00 */ + mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val); + regVal &= ~(BIT5 | BIT6 | BIT8 | BIT9); + mvEthPhyRegWrite(phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal); + + status = mvEthPhyReset(phyAddr, 1000); + if (status != MV_OK) { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + + /* Set loopback */ + ctrlVal |= ETH_PHY_CTRL_LOOPBACK_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal); + } else { + /* Cancel Loopback */ + ctrlVal &= ~ETH_PHY_CTRL_LOOPBACK_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal); + + status = mvEthPhyReset(phyAddr, 1000); + if (status != MV_OK) { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + + /* Enable Energy detection R16[9:8] = 11 */ + /* Enable MDI/MDIX crossover R16[6:5] = 11 */ + mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val); + regVal |= (BIT5 | BIT6 | BIT8 | BIT9); + mvEthPhyRegWrite(phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal); + + status = mvEthPhyReset(phyAddr, 1000); + if (status != MV_OK) { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthPhyCheckLink - +* +* DESCRIPTION: +* check link in phy port +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: MV_TRUE if link is up, MV_FALSE if down +* +*******************************************************************************/ +MV_BOOL mvEthPhyCheckLink(MV_U32 phyAddr) +{ + MV_U16 val_st, val_ctrl, val_spec_st; + + /* read status reg */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &val_st) != MV_OK) + return MV_FALSE; + + /* read control reg */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &val_ctrl) != MV_OK) + return MV_FALSE; + + /* read special status reg */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_STATUS_REG, &val_spec_st) != MV_OK) + return MV_FALSE; + + /* Check for PHY exist */ + if ((val_ctrl == ETH_PHY_SMI_DATA_MASK) && (val_st & ETH_PHY_SMI_DATA_MASK)) + return MV_FALSE; + + + if (val_ctrl & ETH_PHY_CTRL_AN_ENABLE_MASK) { + if (val_st & ETH_PHY_STATUS_AN_DONE_MASK) + return MV_TRUE; + else + return MV_FALSE; + } else { + if (val_spec_st & ETH_PHY_SPEC_STATUS_LINK_MASK) + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPhyPrintStatus - +* +* DESCRIPTION: +* print port Speed, Duplex, Auto-negotiation, Link. +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: 16bit phy register value, or 0xffff on error +* +*******************************************************************************/ +MV_STATUS mvEthPhyPrintStatus(MV_U32 phyAddr) +{ + MV_U16 val; + + /* read control reg */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &val) != MV_OK) + return MV_ERROR; + + if (val & ETH_PHY_CTRL_AN_ENABLE_MASK) + mvOsOutput("Auto negotiation: Enabled\n"); + else + mvOsOutput("Auto negotiation: Disabled\n"); + + + /* read specific status reg */ + if (mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK) + return MV_ERROR; + + switch (val & ETH_PHY_SPEC_STATUS_SPEED_MASK) { + case ETH_PHY_SPEC_STATUS_SPEED_1000MBPS: + mvOsOutput("Speed: 1000 Mbps\n"); + break; + case ETH_PHY_SPEC_STATUS_SPEED_100MBPS: + mvOsOutput("Speed: 100 Mbps\n"); + break; + case ETH_PHY_SPEC_STATUS_SPEED_10MBPS: + mvOsOutput("Speed: 10 Mbps\n"); + default: + mvOsOutput("Speed: Uknown\n"); + break; + + } + + if (val & ETH_PHY_SPEC_STATUS_DUPLEX_MASK) + mvOsOutput("Duplex: Full\n"); + else + mvOsOutput("Duplex: Half\n"); + + + if (val & ETH_PHY_SPEC_STATUS_LINK_MASK) + mvOsOutput("Link: up\n"); + else + mvOsOutput("Link: down\n"); + + return MV_OK; +} + +/******************************************************************************* +* mvEthE1111PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Phy recv and tx delay */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 20, ®); + reg |= BIT1 | BIT7; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 20, reg); + + /* Leds link and activity*/ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 24, 0x4111); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); + + if (ethphyHalData.boardSpecInit == MV_TRUE) + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], + ethphyHalData.specRegOff , ethphyHalData.specData); + +} + +/******************************************************************************* +* mvEthE1112PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Set phy address */ + /*MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));*/ + + /* Implement PHY errata */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, 0x140); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, 0x8140); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 3); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, 0x103); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); + +} +/******************************************************************************* +* mvEthE1310PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1310PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Leds link and activity*/ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0x3); + /*mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®); + reg &= ~0xFF;*/ + reg = 0x0083; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0x0); + + /* Set RGMII delay */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 21, ®); + reg |= (BIT5 | BIT4); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 21, reg); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); +} +/******************************************************************************* +* mvEthE1116PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Leds link and activity*/ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0x3); + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®); + reg &= ~0xf; + reg |= 0x1; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0x0); + + /* Set RGMII delay */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 21, ®); + reg |= (BIT5 | BIT4); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 21, reg); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); +} + + +/******************************************************************************* +* mvEthE3016PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Leds link and activity*/ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 22, ®); + reg &= ~0xf; + reg |= 0xa; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, reg); + + /* Set RGMII (RX) delay and copper mode */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 28, ®); + reg &= ~(BIT3 | BIT10 | BIT11); + reg |= (BIT10); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 28, reg); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); +} + + +/******************************************************************************* +* mvEthE1011PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1011PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Phy recv and tx delay */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 20, ®); + reg &= ~(BIT1 | BIT7); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 20, reg); + + /* Leds link and activity*/ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 24, 0x4111); + + /* reset the phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 0, ®); + reg |= BIT15; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 0, reg); + +} + +/******************************************************************************* +* mvEthE1112PhyPowerDown - +* +* DESCRIPTION: +* Power down the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyPowerDown(MV_U32 ethPortNum) +{ + mvEthPhyPower(ethPortNum, MV_FALSE); +} + +/******************************************************************************* +* mvEthE1112PhyPowerUp - +* +* DESCRIPTION: +* Power up the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyPowerUp(MV_U32 ethPortNum) +{ + mvEthPhyPower(ethPortNum, MV_TRUE); +} + +/******************************************************************************* +* mvEthPhyPower - +* +* DESCRIPTION: +* Do a basic power down/up to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* enable - MV_TRUE - power up +* MV_FALSE - power down +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable) +{ + MV_U16 reg; + if (enable == MV_FALSE) { + /* Power down command */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); /* select page 2 */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®); + reg |= BIT3; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); /* select to disable the SERDES */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); /* select page 0 */ + + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 3); /* Power off LED's */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, 0x88); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®); + reg |= ETH_PHY_CTRL_RESET_MASK; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* software reset */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®); + reg |= ETH_PHY_CTRL_POWER_DOWN_MASK; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* power down the PHY */ + } else { + /* Power up command */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); /* select page 2 */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®); + reg &= ~BIT3; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); /* select to enable the SERDES */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); /* select page 0 */ + + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 3); /* Power on LED's */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, 0x03); + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); + + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®); + reg |= ETH_PHY_CTRL_RESET_MASK; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* software reset */ + mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®); + reg &= ~ETH_PHY_CTRL_POWER_DOWN_MASK; + mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* power up the PHY */ + } +} + + +/******************************************************************************* +* mvEth1145PhyInit - Initialize MARVELL 1145 Phy +* +* DESCRIPTION: +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvEth1145PhyBasicInit(MV_U32 port) +{ + MV_U16 value; + + /* Set Link1000 output pin to be link indication, set Tx output pin to be activity */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x18, ETH_PHY_LED_ACT_LNK_DV); + mvOsDelay(10); + + /* Add delay to RGMII Tx and Rx */ + mvEthPhyRegRead(ethphyHalData.phyAddr[port], 0x14, &value); + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x14, (value | BIT1 | BIT7)); + mvOsDelay(10); +#if 0 /* Fix by yotam */ + if (boardId != RD_78XX0_AMC_ID && + boardId != RD_78XX0_H3C_ID) { + /* Set port 2 - Phy addr 9 to RGMII */ + if (port == 2) { + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x1b, 0x808b); + mvOsDelay(10); + } + + /* Set port 1 - Phy addr a to SGMII */ + if (port == 1) { + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x1b, 0x8084); + mvOsDelay(10); + + /* Reset Phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[port], 0x00, &value); + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x00, (value | BIT15)); + mvOsDelay(10); + #if defined(SGMII_OUTBAND_AN) + /* Set port 1 - Phy addr A Page 1 */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x16, 0x1); + mvOsDelay(10); + + /* Set port 1 - Phy addr A disable A.N. */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x0, 0x140); + mvOsDelay(10); + + /* Set port 1 - Phy addr A reset */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x0, 0x8140); + mvOsDelay(10); + + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x16, 0x0); + mvOsDelay(10); + #endif + } + } +#endif + + /* Set Phy TPVL to 0 */ + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x10, 0x60); + mvOsDelay(10); + + /* Reset Phy */ + mvEthPhyRegRead(ethphyHalData.phyAddr[port], 0x00, &value); + mvEthPhyRegWrite(ethphyHalData.phyAddr[port], 0x00, (value | BIT15)); + mvOsDelay(10); + + return; +} + + +/******************************************************************************* +* mvEthSgmiiToCopperPhyInit - Initialize Test board 1112 Phy +* +* DESCRIPTION: +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 port) +{ + MV_U16 value; + MV_U16 phyAddr = 0xC; + + /* Port 0 phyAdd c */ + /* Port 1 phyAdd d */ + mvEthPhyRegWrite(phyAddr + port, 22, 3); + mvEthPhyRegWrite(phyAddr + port, 16, 0x103); + mvEthPhyRegWrite(phyAddr + port, 22, 0); + + /* reset the phy */ + mvEthPhyRegRead(phyAddr + port, 0, &value); + value |= BIT15; + mvEthPhyRegWrite(phyAddr + port, 0, value); +} + + +MV_VOID mvEth1121PhyBasicInit(MV_U32 port) +{ + MV_U16 value; + MV_U16 phyAddr = ethphyHalData.phyAddr[port]; + + /* Change page select to 2 */ + value = 2; + mvEthPhyRegWrite(phyAddr, 22, value); + mvOsDelay(10); + + /* Set RGMII rx delay */ + mvEthPhyRegRead(phyAddr, 21, &value); + value |= BIT5; + mvEthPhyRegWrite(phyAddr, 21, value); + mvOsDelay(10); + + /* Change page select to 0 */ + value = 0; + mvEthPhyRegWrite(phyAddr, 22, value); + mvOsDelay(10); + + /* reset the phy */ + mvEthPhyRegRead(phyAddr, 0, &value); + value |= BIT15; + mvEthPhyRegWrite(phyAddr, 0, value); + mvOsDelay(10); +} +MV_VOID mvEthInternalGEPhyBasicInit(MV_U32 ethPortNum) +{ +} + +MV_VOID mvEth1540PhyBasicInit(MV_U32 ethPortNum, MV_BOOL eeeEnable) +{ + MV_U16 reg; + MV_U16 i = ethphyHalData.phyAddr[ethPortNum]; + + /* Set page to 0. */ + mvEthPhyRegWrite(i, 0x16, 0); + + /* Phy C_ANEG */ + mvEthPhyRegRead(i, 0x4, ®); + reg |= 0x1E0; + mvEthPhyRegWrite(i, 0x4, reg); + + /* Set page to 1. */ + mvEthPhyRegWrite(i, 0x16, 1); + +#if 0 + /* Phy C_ANEG */ + mvEthPhyRegRead(i, 0x4, ®); + reg &= ~(0x60); + reg |= 0x20; + mvEthPhyRegWrite(i, 0x4, reg); +#endif + + /* Enable SGMII AN */ + mvEthPhyRegWrite(i, 0x0, 0x1140); + + /* Set page to 3. */ + mvEthPhyRegWrite(i, 0x16, 3); + + /* LED setting */ + mvEthPhyRegWrite(i, 0x10, 0x8083); + + /* Set page to 0. */ + mvEthPhyRegWrite(i, 0x16, 0); + + if (eeeEnable) { + /* set ELU#0 default match */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x10); + /* RW U1 P0 R1 H0104 */ + mvEthPhyRegWrite(i, 0x1, 0x0104); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H4000 */ + mvEthPhyRegWrite(i, 0x3, 0x4000); + /* RW U1 P0 R1 H0904 */ + mvEthPhyRegWrite(i, 0x1, 0x0904); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H4000 */ + mvEthPhyRegWrite(i, 0x3, 0x4000); + /* RW U1 P0 R1 H1104 */ + mvEthPhyRegWrite(i, 0x1, 0x1104); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H4000 */ + mvEthPhyRegWrite(i, 0x3, 0x4000); + /* RW U1 P0 R1 H1904 */ + mvEthPhyRegWrite(i, 0x1, 0x1904); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H4000 */ + mvEthPhyRegWrite(i, 0x3, 0x4000); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* set ILU#0 default match */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H0207 */ + mvEthPhyRegWrite(i, 0x1, 0x0207); + /* RW U1 P0 R2 h4000 */ + mvEthPhyRegWrite(i, 0x2, 0x4000); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3, 0x0000); + /* RW U1 P0 R1 H0A07 */ + mvEthPhyRegWrite(i, 0x1, 0x0a07); + /* RW U1 P0 R2 h4000 */ + mvEthPhyRegWrite(i, 0x2, 0x4000); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3, 0x0000); + /* RW U1 P0 R1 H1207 */ + mvEthPhyRegWrite(i, 0x1, 0x1207); + /* RW U1 P0 R2 h4000 */ + mvEthPhyRegWrite(i, 0x2, 0x4000); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3, 0x0000); + /* RW U1 P0 R1 H1A07 */ + mvEthPhyRegWrite(i, 0x1, 0x1a07); + /* RW U1 P0 R2 h4000 */ + mvEthPhyRegWrite(i, 0x2, 0x4000); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3, 0x0000); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* change the wiremac ipg from 12 to 11 */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H0041 */ + mvEthPhyRegWrite(i, 0x1, 0x0041); + /* RW U1 P0 R2 h00b1 */ + mvEthPhyRegWrite(i, 0x2, 0x00b1); + /* RW U1 P0 R3 H0002 */ + mvEthPhyRegWrite(i, 0x3, 0x0002); + /* RW U1 P0 R1 H0841 */ + mvEthPhyRegWrite(i, 0x1, 0x0841); + /* RW U1 P0 R2 h00b1 */ + mvEthPhyRegWrite(i, 0x2, 0x00b1); + /* RW U1 P0 R3 H0002 */ + mvEthPhyRegWrite(i, 0x3, 0x0002); + /* RW U1 P0 R1 H1041 */ + mvEthPhyRegWrite(i, 0x1, 0x1041); + /* RW U1 P0 R2 h00b1 */ + mvEthPhyRegWrite(i, 0x2, 0x00b1); + /* RW U1 P0 R3 H0002 */ + mvEthPhyRegWrite(i, 0x3, 0x0002); + /* RW U1 P0 R1 H1841 */ + mvEthPhyRegWrite(i, 0x1, 0x1841); + /* RW U1 P0 R2 h00b1 */ + mvEthPhyRegWrite(i, 0x2, 0x00b1); + /* RW U1 P0 R3 H0002 */ + mvEthPhyRegWrite(i, 0x3, 0x0002); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + + /* change the setting to not drop badtag */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H000b */ + mvEthPhyRegWrite(i, 0x1, 0x000b); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H0fb4 */ + mvEthPhyRegWrite(i, 0x3, 0x0fb4); + /* RW U1 P0 R1 H080b */ + mvEthPhyRegWrite(i, 0x1, 0x080b); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H0fb4 */ + mvEthPhyRegWrite(i, 0x3, 0x0fb4); + /* RW U1 P0 R1 H100b */ + mvEthPhyRegWrite(i, 0x1, 0x100b); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H0fb4 */ + mvEthPhyRegWrite(i, 0x3, 0x0fb4); + /* RW U1 P0 R1 H180b */ + mvEthPhyRegWrite(i, 0x1, 0x180b); + /* RW U1 P0 R2 h0000 */ + mvEthPhyRegWrite(i, 0x2, 0x0000); + /* RW U1 P0 R3 H0fb4 */ + mvEthPhyRegWrite(i, 0x3, 0x0fb4); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* set MACSec EEE Entry/Exit Timer */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H03C0 */ + mvEthPhyRegWrite(i, 0x3, 0x03c0); + /* RW U1 P0 R2 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R3 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R1 H0BC0 */ + mvEthPhyRegWrite(i, 0x3, 0x0bc0); + /* RW U1 P0 R2 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R3 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R1 H13C0 */ + mvEthPhyRegWrite(i, 0x3, 0x13c0); + /* RW U1 P0 R2 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R3 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R1 H1BC0 */ + mvEthPhyRegWrite(i, 0x3, 0x1bc0); + /* RW U1 P0 R2 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R3 H111E */ + mvEthPhyRegWrite(i, 0x3, 0x111e); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* Start of EEE Workaround */ + /* RW U1 P0-3 R22 H00FB */ + mvEthPhyRegWrite(i, 0x16, 0x00FB); + /* RW U1 P0-3 R11 H1120 */ + mvEthPhyRegWrite(i, 0xB , 0x1120); + /* RW U1 P0-3 R8 H3666 */ + mvEthPhyRegWrite(i, 0x8 , 0x3666); + /* RW U1 P0-3 R22 H00FF */ + mvEthPhyRegWrite(i, 0x16, 0x00FF); + /* RW U1 P0-3 R17 H0F0C */ + mvEthPhyRegWrite(i, 0x11, 0x0F0C); + /* RW U1 P0-3 R16 H2146 */ + mvEthPhyRegWrite(i, 0x10, 0x2146); + /* RW U1 P0-3 R17 Hc090 */ + mvEthPhyRegWrite(i, 0x11, 0xC090); + /* RW U1 P0-3 R16 H2147 */ + mvEthPhyRegWrite(i, 0x10, 0x2147); + /* RW U1 P0-3 R17 H0000 */ + mvEthPhyRegWrite(i, 0x11, 0x0000); + /* RW U1 P0-3 R16 H2000 */ + mvEthPhyRegWrite(i, 0x10, 0x2000); + /* RW U1 P0-3 R17 H6000 */ + mvEthPhyRegWrite(i, 0x11, 0x6000); + /* RW U1 P0-3 R16 H2143 */ + mvEthPhyRegWrite(i, 0x10, 0x2143); + /* RW U1 P0-3 R17 HC004 */ + mvEthPhyRegWrite(i, 0x11, 0xC004); + /* RW U1 P0-3 R16 H2100 */ + mvEthPhyRegWrite(i, 0x10, 0x2100); + /* RW U1 P0-3 R17 H49E8 */ + mvEthPhyRegWrite(i, 0x11, 0x49E8); + /* RW U1 P0-3 R16 H2144 */ + mvEthPhyRegWrite(i, 0x10, 0x2144); + /* RW U1 P0-3 R17 H3180 */ + mvEthPhyRegWrite(i, 0x11, 0x3180); + /* RW U1 P0-3 R16 H2148 */ + mvEthPhyRegWrite(i, 0x10, 0x2148); + /* RW U1 P0-3 R17 HFC44 */ + mvEthPhyRegWrite(i, 0x11, 0xFC44); + /* RW U1 P0-3 R16 H214B */ + mvEthPhyRegWrite(i, 0x10, 0x214B); + /* RW U1 P0-3 R17 H7FD2 */ + mvEthPhyRegWrite(i, 0x11, 0x7FD2); + /* RW U1 P0-3 R16 H214C */ + mvEthPhyRegWrite(i, 0x10, 0x214C); + /* RW U1 P0-3 R17 H2240 */ + mvEthPhyRegWrite(i, 0x11, 0x2240); + /* RW U1 P0-3 R16 H214D */ + mvEthPhyRegWrite(i, 0x10, 0x214D); + /* RW U1 P0-3 R17 H3008 */ + mvEthPhyRegWrite(i, 0x11, 0x3008); + /* RW U1 P0-3 R16 H214E */ + mvEthPhyRegWrite(i, 0x10, 0x214E); + /* RW U1 P0-3 R17 H3DF0 */ + mvEthPhyRegWrite(i, 0x11, 0x3DF0); + /* RW U1 P0-3 R16 H214F */ + mvEthPhyRegWrite(i, 0x10, 0x214F); + /* RW U1 P0-3 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0); + + /* Enable EEE Auto-neg advertisement on P0-P7 ports */ + /* RW U1 P0-3 R13 H0007 */ + mvEthPhyRegWrite(i, 0xD , 0x0007); + /* RW U1 P0-3 R14 H003C */ + mvEthPhyRegWrite(i, 0xE , 0x003C); + /* RW U1 P0-3 R13 H4007 */ + mvEthPhyRegWrite(i, 0xD , 0x4007); + /* RW U1 P0-3 R14 H0006 */ + mvEthPhyRegWrite(i, 0xE , 0x0006); + + /* Soft-Reset on P0-P7 ports */ + /* RW U1 P0-3 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0); + /* RW U1 P0-3 R0 H9140 */ + mvEthPhyRegWrite(i, 0x0 , 0x9140); + + /* Enable MACsec EEE Master Mode on P0-3 ports */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H03C1 */ + mvEthPhyRegWrite(i, 0x1 , 0x03C1); + /* RW U1 P0 R2 H0001 */ + mvEthPhyRegWrite(i, 0x2 , 0x0001); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3 , 0x0000); + /* RW U1 P0 R1 H0BC1 */ + mvEthPhyRegWrite(i, 0x1 , 0x0BC1); + /* RW U1 P0 R2 H0001 */ + mvEthPhyRegWrite(i, 0x2 , 0x0001); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3 , 0x0000); + /* RW U1 P0 R1 H13C1 */ + mvEthPhyRegWrite(i, 0x1 , 0x13C1); + /* RW U1 P0 R2 H0001 */ + mvEthPhyRegWrite(i, 0x2 , 0x0001); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3 , 0x0000); + /* RW U1 P0 R1 H1BC1 */ + mvEthPhyRegWrite(i, 0x1 , 0x1BC1); + /* RW U1 P0 R2 H0001 */ + mvEthPhyRegWrite(i, 0x2 , 0x0001); + /* RW U1 P0 R3 H0000 */ + mvEthPhyRegWrite(i, 0x3 , 0x0000); + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + } + /* set ELU#0 default match */ + /* RW U1 P0 R22 H0010 */ + /* RW U1 P0 R1 H0104 */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H4000 */ + /* RW U1 P0 R1 H0904 */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H4000 */ + /* RW U1 P0 R1 H1104 */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H4000 */ + /* RW U1 P0 R1 H1904 */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H4000 */ + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* set ILU#0 default match */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H0207 */ + /* RW U1 P0 R2 h4000 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H0A07 */ + /* RW U1 P0 R2 h4000 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H1207 */ + /* RW U1 P0 R2 h4000 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H1A07 */ + /* RW U1 P0 R2 h4000 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* change the wiremac ipg from 12 to 11 */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H0041 */ + /* RW U1 P0 R2 h00b1 */ + /* RW U1 P0 R3 H0002 */ + /* RW U1 P0 R1 H0841 */ + /* RW U1 P0 R2 h00b1 */ + /* RW U1 P0 R3 H0002 */ + /* RW U1 P0 R1 H1041 */ + /* RW U1 P0 R2 h00b1 */ + /* RW U1 P0 R3 H0002 */ + /* RW U1 P0 R1 H1841 */ + /* RW U1 P0 R2 h00b1 */ + /* RW U1 P0 R3 H0002 */ + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + + /* change the setting to not drop badtag */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H000b */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H0fb4 */ + /* RW U1 P0 R1 H080b */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H0fb4 */ + /* RW U1 P0 R1 H100b */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H0fb4 */ + /* RW U1 P0 R1 H180b */ + /* RW U1 P0 R2 h0000 */ + /* RW U1 P0 R3 H0fb4 */ + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* set MACSec EEE Entry/Exit Timer */ + /* RW U1 P0 R22 H0010 */ + mvEthPhyRegWrite(i, 0x16, 0x0010); + /* RW U1 P0 R1 H03C0 */ + /* RW U1 P0 R2 H111E */ + /* RW U1 P0 R3 H111E */ + /* RW U1 P0 R1 H0BC0 */ + /* RW U1 P0 R2 H111E */ + /* RW U1 P0 R3 H111E */ + /* RW U1 P0 R1 H13C0 */ + /* RW U1 P0 R2 H111E */ + /* RW U1 P0 R3 H111E */ + /* RW U1 P0 R1 H1BC0 */ + /* RW U1 P0 R2 H111E */ + /* RW U1 P0 R3 H111E */ + /* RW U1 P0 R22 H0000 */ + /* RW U1 P0-3 R22 H00FB */ + /* RW U1 P0-3 R11 H1120 */ + /* RW U1 P0-3 R8 H3666 */ + /* RW U1 P0-3 R22 H00FF */ + /* RW U1 P0-3 R17 H0F0C */ + /* RW U1 P0-3 R16 H2146 */ + /* RW U1 P0-3 R17 Hc090 */ + /* RW U1 P0-3 R16 H2147 */ + /* RW U1 P0-3 R17 H0000 */ + /* RW U1 P0-3 R16 H2000 */ + /* RW U1 P0-3 R17 H6000 */ + /* RW U1 P0-3 R16 H2143 */ + /* RW U1 P0-3 R17 HC004 */ + /* RW U1 P0-3 R16 H2100 */ + /* RW U1 P0-3 R17 H49E8 */ + /* RW U1 P0-3 R16 H2144 */ + /* RW U1 P0-3 R17 H3180 */ + /* RW U1 P0-3 R16 H2148 */ + /* RW U1 P0-3 R17 HFC44 */ + /* RW U1 P0-3 R16 H214B */ + /* RW U1 P0-3 R17 H7FD2 */ + /* RW U1 P0-3 R16 H214C */ + /* RW U1 P0-3 R17 H2240 */ + /* RW U1 P0-3 R16 H214D */ + /* RW U1 P0-3 R17 H3008 */ + /* RW U1 P0-3 R16 H214E */ + /* RW U1 P0-3 R17 H3DF0 */ + /* RW U1 P0-3 R16 H214F */ + /* RW U1 P0-3 R22 H0000 */ + /* RW U1 P0-3 R13 H0007 */ + /* RW U1 P0-3 R14 H003C */ + /* RW U1 P0-3 R13 H4007 */ + /* RW U1 P0-3 R14 H0006 */ + /* RW U1 P0-3 R22 H0000 */ + /* RW U1 P0-3 R0 H9140 */ + /* RW U1 P0 R22 H0010 */ + /* RW U1 P0 R1 H03C1 */ + /* RW U1 P0 R2 H0001 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H0BC1 */ + /* RW U1 P0 R2 H0001 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H13C1 */ + /* RW U1 P0 R2 H0001 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R1 H1BC1 */ + /* RW U1 P0 R2 H0001 */ + /* RW U1 P0 R3 H0000 */ + /* RW U1 P0 R22 H0000 */ + mvEthPhyRegWrite(i, 0x16, 0x0000); + + /* Power up the phy */ + mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg); + /*mvOsDelay(100);*/ + /* Sleep 3000 */ + mvOsDelay(300); + +} + +MV_VOID mvEth1340PhyBasicInit(void) +{ + int i; + MV_U16 reg; + + + for (i = 0; i < 4; i++) { + mvEthPhyRegWrite(i, 0x16, 0); + mvEthPhyRegWrite(i, 0x1d, 3); + mvEthPhyRegWrite(i, 0x1e, 2); + mvEthPhyRegWrite(i, 0x1d, 0); + + /* Power up the phy */ + /* mvEthPhyRegRead(i,ETH_PHY_CTRL_REG, ®); */ + /* reg |= ETH_PHY_CTRL_RESET_MASK; */ + /* mvEthPhyRegWrite(i,ETH_PHY_CTRL_REG, reg); software reset */ + + /* Enable QSGMII AN */ + /* Set page to 4. */ + mvEthPhyRegWrite(i, 0x16, 4); + /* Enable AN */ + mvEthPhyRegWrite(i, 0x0, 0x1140); + /* Set page to 0. */ + mvEthPhyRegWrite(i, 0x16, 0); + + mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg); + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhy.h u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhy.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhy.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhy.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,145 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCETHPHYH +#define __INCETHPHYH + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysEthPhyConfig.h" + +#define MV_PHY_88E3061 0x1 /* E3061, E3081 */ +#define MV_PHY_88E104X 0x2 /* E1040, E1041, E1042 */ +#define MV_PHY_88E10X0 0x4 /* E1000, E1010, E1020 */ +#define MV_PHY_88E10X0S 0x5 /* E1000S, E1010S, E1020S */ +#define MV_PHY_88E1011 0x6 /* E1011, E1011S */ +#define MV_PHY_88E3082 0x8 +#define MV_PHY_88E1112 0x9 +#define MV_PHY_88E1149 0xA +#define MV_PHY_88E1121 0xB +#define MV_PHY_88E1111 0xC /* E1111, E1115 */ +#define MV_PHY_88E114X 0xD +#define MV_PHY_88E1181 0xE +#define MV_PHY_88E1340S 0x1C /* 88E1340S */ +#define MV_PHY_88E1340 0x1E /* 88E1340/x0a */ +#define MV_PHY_88E154X 0x2B /* 88E1545M */ +#define MV_PHY_88E1340M 0x1F /* 88E1340M/x0a */ +#define MV_PHY_88E1116R 0x24 +#define MV_PHY_88E1116 0x21 /* E1116, E1116R */ +#define MV_PHY_88E3016_88E3019 0x22 /* E3015, E3016, E3018, 88E3019 */ +#define MV_PHY_88E1240 0x23 +#define MV_PHY_88E1149R 0x25 +#define MV_PHY_88E1119R 0x28 /* 88E1119R */ +#define MV_PHY_88E1310 0x29 /* 88E1310 */ +#define MV_PHY_KW2_INTERNAL_GE 0x2b +#define MV_PHY_KW2_INTERNAL_3FE 0x26 + +#define MV_IS_MARVELL_OUI(_reg2, _reg3) \ + (((_reg2) == 0x0141) && (((_reg3)&0xFC00) == 0x0C00)) + +typedef struct { + MV_U32 phyAddr[MV_ETH_MAX_PORTS]; + MV_BOOL boardSpecInit; /* Special board phy init */ + MV_U32 specRegOff; /* Board specific register offset, + Valid if boardSpecInit == TRUE */ + MV_U32 specData; /* Board specific data to write, + Valid if boardSpecInit == TRUE */ +} MV_ETHPHY_HAL_DATA; + +MV_STATUS mvEthPhyHalInit(MV_ETHPHY_HAL_DATA *halData); +MV_STATUS mvEthPhyInit(MV_U32 ethPortNum, MV_BOOL eeeEnable); +MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); +MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout); +MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout); +MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex); +MV_STATUS mvEthPhyLoopback(MV_U32 phyAddr, MV_BOOL isEnable); +MV_BOOL mvEthPhyCheckLink(MV_U32 phyAddr); +MV_STATUS mvEthPhyPrintStatus(MV_U32 phyAddr); + +MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyPowerDown(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyPowerUp(MV_U32 ethPortNum); +MV_VOID mvEthE1116PhyPower(MV_U32 ethPortNum, MV_BOOL enable); +MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1310PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1011PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEth1145PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEth1121PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthInternalGEPhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEth1540PhyBasicInit(MV_U32 ethPortNum, MV_BOOL eeeEnable); +MV_VOID mvEth1340PhyBasicInit(void); +/* MV_VOID mvEthInternal3FEPhyBasicInit(MV_U32 port); */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef __INCETHPHYH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhyRegs.h u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhyRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/eth-phy/mvEthPhyRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/eth-phy/mvEthPhyRegs.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,174 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCethphyregsh +#define __INCethphyregsh + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvSysEthConfig.h" + +/* defines */ +#define ETH_PHY_TIMEOUT 10000 + +/* registers offsetes defines */ +/* FIXME: this change is not good for other SoCs, offset should be +in the sys part so we can prevent an issue here */ +#define ETH_PHY_SMI_REG (MV_ETH_REGS_BASE(0) + 0x004) /* PORT#0 SMI is used */ + +/* SMI register fields (ETH_PHY_SMI_REG) */ + +#define ETH_PHY_SMI_DATA_OFFS 0 /* Data */ +#define ETH_PHY_SMI_DATA_MASK (0xffff << ETH_PHY_SMI_DATA_OFFS) + +#define ETH_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define ETH_PHY_SMI_DEV_ADDR_MASK (0x1f << ETH_PHY_SMI_DEV_ADDR_OFFS) + +#define ETH_PHY_SMI_REG_ADDR_OFFS 21 /* PHY device register address */ +#define ETH_PHY_SMI_REG_ADDR_MASK (0x1f << ETH_PHY_SMI_REG_ADDR_OFFS) + +#define ETH_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define ETH_PHY_SMI_OPCODE_MASK (3 << ETH_PHY_SMI_OPCODE_OFFS) +#define ETH_PHY_SMI_OPCODE_WRITE (0 << ETH_PHY_SMI_OPCODE_OFFS) +#define ETH_PHY_SMI_OPCODE_READ (1 << ETH_PHY_SMI_OPCODE_OFFS) + +#define ETH_PHY_SMI_READ_VALID_BIT 27 /* Read Valid */ +#define ETH_PHY_SMI_READ_VALID_MASK (1 << ETH_PHY_SMI_READ_VALID_BIT) + +#define ETH_PHY_SMI_BUSY_BIT 28 /* Busy */ +#define ETH_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT) + +/* PHY registers and bits */ +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_STATUS_REG 1 +#define ETH_PHY_AUTONEGO_AD_REG 4 +#define ETH_PHY_1000BASE_T_CTRL_REG 9 +#define ETH_PHY_SPEC_CTRL_REG 16 +#define ETH_PHY_SPEC_STATUS_REG 17 + +/* ETH_PHY_CTRL_REG bits */ +#define ETH_PHY_CTRL_SPEED_MSB_BIT 6 +#define ETH_PHY_CTRL_SPEED_MSB_MASK (1 << ETH_PHY_CTRL_SPEED_MSB_BIT) + +#define ETH_PHY_CTRL_COLISION_TEST_BIT 7 +#define ETH_PHY_CTRL_COLISION_TEST_MASK (1 << ETH_PHY_CTRL_COLISION_TEST_BIT) + +#define ETH_PHY_CTRL_DUPLEX_BIT 8 +#define ETH_PHY_CTRL_DUPLEX_MASK (1 << ETH_PHY_CTRL_DUPLEX_BIT) + +#define ETH_PHY_CTRL_AN_RESTART_BIT 9 +#define ETH_PHY_CTRL_AN_RESTART_MASK (1 << ETH_PHY_CTRL_AN_RESTART_BIT) + +#define ETH_PHY_CTRL_ISOLATE_BIT 10 +#define ETH_PHY_CTRL_ISOLATE_MASK (1 << ETH_PHY_CTRL_ISOLATE_BIT) + +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +#define ETH_PHY_CTRL_AN_ENABLE_BIT 12 +#define ETH_PHY_CTRL_AN_ENABLE_MASK (1 << ETH_PHY_CTRL_AN_ENABLE_BIT) + +#define ETH_PHY_CTRL_SPEED_LSB_BIT 13 +#define ETH_PHY_CTRL_SPEED_LSB_MASK (1 << ETH_PHY_CTRL_SPEED_LSB_BIT) + +#define ETH_PHY_CTRL_LOOPBACK_BIT 14 +#define ETH_PHY_CTRL_LOOPBACK_MASK (1 << ETH_PHY_CTRL_LOOPBACK_BIT) + +#define ETH_PHY_CTRL_RESET_BIT 15 +#define ETH_PHY_CTRL_RESET_MASK (1 << ETH_PHY_CTRL_RESET_BIT) + +/* ETH_PHY_STATUS_REG bits */ +#define ETH_PHY_STATUS_AN_DONE_BIT 5 +#define ETH_PHY_STATUS_AN_DONE_MASK (1 << ETH_PHY_STATUS_AN_DONE_BIT) + +/* ETH_PHY_1000BASE_T_CTRL_REG bits */ +#define ETH_PHY_1000BASE_ADVERTISE_OFFSET 8 +#define ETH_PHY_1000BASE_ADVERTISE_MASK (0x3 << ETH_PHY_1000BASE_ADVERTISE_OFFSET) + +/* ETH_PHY_SPEC_STATUS_REG bits */ +#define ETH_PHY_SPEC_STATUS_SPEED_OFFS 14 +#define ETH_PHY_SPEC_STATUS_SPEED_MASK (0x3 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) + +#define ETH_PHY_SPEC_STATUS_SPEED_10MBPS (0x0 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) +#define ETH_PHY_SPEC_STATUS_SPEED_100MBPS (0x1 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) +#define ETH_PHY_SPEC_STATUS_SPEED_1000MBPS (0x2 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) + + +#define ETH_PHY_SPEC_STATUS_DUPLEX_BIT 13 +#define ETH_PHY_SPEC_STATUS_DUPLEX_MASK (0x1 << ETH_PHY_SPEC_STATUS_DUPLEX_BIT) + +#define ETH_PHY_SPEC_STATUS_LINK_BIT 10 +#define ETH_PHY_SPEC_STATUS_LINK_MASK (0x1 << ETH_PHY_SPEC_STATUS_LINK_BIT) + +/* ETH_PHY_SPEC_STATUS_REG bits */ +#define ETH_PHY_LED_ACT_LNK_DV 0x4109 + +#ifdef __cplusplus +} +#endif + + +#endif /* __INCethphyregsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/gpp/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/gpp/mvCompVer.txt 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGpp.c u-boot-2009.08/board/marvell/mv_hal/gpp/mvGpp.c --- u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGpp.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/gpp/mvGpp.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,381 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysGppConfig.h" +#include "mvGppRegs.h" +#include "mvGpp.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs, MV_U32 mask, MV_U32 value); + +static MV_GPP_HAL_DATA gppHalData; + +/******************************************************************************* +* mvGppInit - Init GPP HAL +* +* DESCRIPTION: +* +* INPUT: +* halData - GPP HAL data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS mvGppInit(MV_GPP_HAL_DATA *halData) +{ + mvOsMemcpy(&gppHalData, halData, sizeof(MV_GPP_HAL_DATA)); + return MV_OK; +} + +/******************************************************************************* +* mvGppTypeSet - Enable a GPP (OUT) pin +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP type per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to input and GPP15 to output. +* mvGppTypeSet(0, (GPP8 | GPP15), +* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) { + DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); + + /* Workaround for Erratum FE-MISC-70 */ + if (gppHalData.ctrlRev == MV_88F6XXX_A0_REV && (group == 1)) { + mask &= 0x2; + gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); + } + /*End of WA */ + return MV_OK; +} + +/******************************************************************************* +* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP blink per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to be static and GPP15 to be blinking. +* mvGppBlinkEn(0, (GPP8 | GPP15), +* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) { + DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); + + return MV_OK; + +} + +/******************************************************************************* +* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP polarity per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to the actual pin value and GPP15 to be inverted. +* mvGppPolaritySet(0, (GPP8 | GPP15), +* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) { + DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); + + return MV_OK; + +} + +/******************************************************************************* +* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppPolarityGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP polatity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 regVal; + + if (group >= MV_GPP_MAX_GROUP) { + DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); + return MV_ERROR; + } + regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); + + return (regVal & mask); +} + +/******************************************************************************* +* mvGppValueGet - Get a GPP Pin list value. +* +* DESCRIPTION: +* This function get GPP value. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppValueGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP activity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); + + gppData &= mask; + + return gppData; + +} + +/******************************************************************************* +* mvGppValueSet - Set a GPP Pin list value. +* +* DESCRIPTION: +* This function set value for given GPP pin list. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppValueSet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + MV_U32 outEnable, tmp; + MV_U32 i; + + if (group >= MV_GPP_MAX_GROUP) { + DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); + return MV_BAD_PARAM; + } + + /* verify that the gpp pin is configured as output */ + /* Note that in the register out enabled -> bit = '0'. */ + outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); + + /* Workaround for Erratum FE-MISC-70 */ + if (gppHalData.ctrlRev == MV_88F6XXX_A0_REV && (group == 1)) { + tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); + outEnable &= 0xfffffffd; + outEnable |= (tmp & 0x2); + } + /*End of WA */ + for (i = 0; i < 32; i++) { + if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) { + mvOsPrintf("mvGppValueSet: Err. An attempt to set output " + "value to GPP %d in input mode.\n", i); + return MV_ERROR; + } + } + + gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); + + return MV_OK; + +} + +/******************************************************************************* +* gppRegSet - Set a specific GPP pin on a specific GPP register +* +* DESCRIPTION: +* This function set a specific GPP pin on a specific GPP register +* +* INPUT: +* regOffs - GPP Register offset +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs, MV_U32 mask, MV_U32 value) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(regOffs); + + gppData &= ~mask; + + gppData |= (value & mask); + + MV_REG_WRITE(regOffs, gppData); +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGpp.h u-boot-2009.08/board/marvell/mv_hal/gpp/mvGpp.h --- u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGpp.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/gpp/mvGpp.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,126 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppH +#define __INCmvGppH + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysGppConfig.h" + + typedef struct { + MV_U8 ctrlRev; + } MV_GPP_HAL_DATA; + + /* These macros describes the GPP type. Each of the GPPs pins can */ + /* be assigned to act as a general purpose input or output pin. */ +#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ +#define MV_GPP_OUT 0 /* GPP output */ + + /* These macros describes the GPP Out Enable. */ +#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled */ +#define MV_GPP_OUT_EN 0 /* Out pin enabled */ + + /* These macros describes the GPP Out Blinking. */ + /* When set and the corresponding bit in GPIO Data Out Enable Control */ + /* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ + /* 2^24 TCLK clocks). */ +#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking */ +#define MV_GPP_OUT_STATIC 0 /* Out pin static */ + + /* These macros describes the GPP Polarity. */ + /* When set to 1 GPIO Data In Register reflects the inverted value of the */ + /* corresponding pin. */ + +#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got */ +#define MV_GPP_IN_ORIGIN 0 /* original value is got */ + + /* mvGppInit - Initialize GPP HAL */ + MV_STATUS mvGppInit(MV_GPP_HAL_DATA *halData); + + /* mvGppTypeSet - Set PP pin mode (IN or OUT) */ + MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); + + /* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ + MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); + + /* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ + MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); + + /* mvGppPolarityGet - Get the Polarity of a GPP Pin */ + MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); + + /* mvGppValueGet - Get a GPP Pin list value. */ + MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); + + /* mvGppValueSet - Set a GPP Pin list value. */ + MV_STATUS mvGppValueSet(MV_U32 group, MV_U32 mask, MV_U32 value); + +#ifdef __cplusplus +} +#endif +#endif /* #ifndef __INCmvGppH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGppRegs.h u-boot-2009.08/board/marvell/mv_hal/gpp/mvGppRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/gpp/mvGppRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/gpp/mvGppRegs.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,128 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppRegsH +#define __INCmvGppRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvSysGppConfig.h" + +#define MV_GPP0 BIT0 +#define MV_GPP1 BIT1 +#define MV_GPP2 BIT2 +#define MV_GPP3 BIT3 +#define MV_GPP4 BIT4 +#define MV_GPP5 BIT5 +#define MV_GPP6 BIT6 +#define MV_GPP7 BIT7 +#define MV_GPP8 BIT8 +#define MV_GPP9 BIT9 +#define MV_GPP10 BIT10 +#define MV_GPP11 BIT11 +#define MV_GPP12 BIT12 +#define MV_GPP13 BIT13 +#define MV_GPP14 BIT14 +#define MV_GPP15 BIT15 +#define MV_GPP16 BIT16 +#define MV_GPP17 BIT17 +#define MV_GPP18 BIT18 +#define MV_GPP19 BIT19 +#define MV_GPP20 BIT20 +#define MV_GPP21 BIT21 +#define MV_GPP22 BIT22 +#define MV_GPP23 BIT23 +#define MV_GPP24 BIT24 +#define MV_GPP25 BIT25 +#define MV_GPP26 BIT26 +#define MV_GPP27 BIT27 +#define MV_GPP28 BIT28 +#define MV_GPP29 BIT29 +#define MV_GPP30 BIT30 +#define MV_GPP31 BIT31 + + /* registers offsets */ + +#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) +#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */ +#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) +#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08) +#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C) +#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) +#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14) +#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18) +#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C) + +#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40) + + /* Relevant for MV78XX0 */ +#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20) +#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* #ifndef __INCmvGppRegsH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBm.c u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBm.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBm.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBm.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,309 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" /* Should be included before mvSysHwConfig */ +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "mvSysEthConfig.h" + +#include "mvBm.h" + +MV_U8 *mvBmVirtBase = 0; + +/* Initialize Hardware Buffer management unit */ +MV_STATUS mvBmInit(MV_U8 *virtBase) +{ + MV_U32 regVal; + + mvBmVirtBase = virtBase; + + /* Mask BM all interrupts */ + MV_REG_WRITE(MV_BM_INTR_MASK_REG, 0); + + /* Clear BM cause register */ + MV_REG_WRITE(MV_BM_INTR_CAUSE_REG, 0); + + /* Set BM configuration register */ + regVal = MV_REG_READ(MV_BM_CONFIG_REG); + + /* Reduce MaxInBurstSize from 32 BPs to 16 BPs */ + regVal &= ~MV_BM_MAX_IN_BURST_SIZE_MASK; + regVal |= MV_BM_MAX_IN_BURST_SIZE_16BP; + MV_REG_WRITE(MV_BM_CONFIG_REG, regVal); + + return MV_OK; +} + +MV_STATUS mvBmControl(MV_COMMAND cmd) +{ + MV_U32 regVal = 0; + + switch (cmd) { + case MV_START: + regVal = MV_BM_START_MASK; + break; + + case MV_STOP: + regVal = MV_BM_STOP_MASK; + break; + + case MV_PAUSE: + regVal = MV_BM_PAUSE_MASK; + break; + + default: + mvOsPrintf("bmControl: Unknown command %d\n", cmd); + return MV_FAIL; + } + MV_REG_WRITE(MV_BM_COMMAND_REG, regVal); + return MV_OK; +} + +MV_STATE mvBmStateGet(void) +{ + MV_U32 regVal; + MV_STATE state; + + regVal = MV_REG_READ(MV_BM_COMMAND_REG); + + switch ((regVal >> MV_BM_STATUS_OFFS) & MV_BM_STATUS_ALL_MASK) { + case MV_BM_STATUS_ACTIVE: + state = MV_ACTIVE; + break; + + case MV_BM_STATUS_NOT_ACTIVE: + state = MV_IDLE; + break; + + case MV_BM_STATUS_PAUSED: + state = MV_PAUSED; + break; + + default: + mvOsPrintf("bmStateGet: Unexpected state 0x%x\n", regVal); + state = MV_UNDEFINED_STATE; + } + return state; +} + +void mvBmPoolTargetSet(int pool, MV_U8 targetId, MV_U8 attr) +{ + MV_U32 regVal; + + /* validate poolId */ + if ((pool < 0) || (pool >= MV_BM_POOLS)) { + mvOsPrintf("bmPoolId = %d is invalid \n", pool); + return; + } + /* Read modify write */ + regVal = MV_REG_READ(MV_BM_XBAR_POOL_REG(pool)); + + regVal &= ~MV_BM_TARGET_ID_MASK(pool); + regVal &= ~MV_BM_XBAR_ATTR_MASK(pool); + regVal |= MV_BM_TARGET_ID_VAL(pool, targetId); + regVal |= MV_BM_XBAR_ATTR_VAL(pool, attr); + + MV_REG_WRITE(MV_BM_XBAR_POOL_REG(pool), regVal); +} + +void mvBmPoolEnable(int pool) +{ + MV_U32 regVal; + + /* validate poolId */ + if ((pool < 0) || (pool >= MV_BM_POOLS)) { + mvOsPrintf("bmPoolId = %d is invalid \n", pool); + return; + } + regVal = MV_REG_READ(MV_BM_POOL_BASE_REG(pool)); + regVal |= MV_BM_POOL_ENABLE_MASK; + MV_REG_WRITE(MV_BM_POOL_BASE_REG(pool), regVal); + + /* Clear BM cause register */ + MV_REG_WRITE(MV_BM_INTR_CAUSE_REG, 0); + +} + +void mvBmPoolDisable(int pool) +{ + MV_U32 regVal; + + /* validate poolId */ + if ((pool < 0) || (pool >= MV_BM_POOLS)) { + mvOsPrintf("bmPoolId = %d is invalid \n", pool); + return; + } + regVal = MV_REG_READ(MV_BM_POOL_BASE_REG(pool)); + regVal &= ~MV_BM_POOL_ENABLE_MASK; + MV_REG_WRITE(MV_BM_POOL_BASE_REG(pool), regVal); +} + +MV_BOOL mvBmPoolIsEnabled(int pool) +{ + MV_U32 regVal; + + /* validate poolId */ + if ((pool < 0) || (pool >= MV_BM_POOLS)) { + mvOsPrintf("bmPoolId = %d is invalid \n", pool); + return MV_FALSE; + } + regVal = MV_REG_READ(MV_BM_POOL_BASE_REG(pool)); + return (regVal & MV_BM_POOL_ENABLE_MASK); +} + +/* Configure BM specific pool of "capacity" size. */ +MV_STATUS mvBmPoolInit(int pool, MV_ULONG poolBase, int capacity) +{ + /* validate poolId */ + if ((pool < 0) || (pool >= MV_BM_POOLS)) { + mvOsPrintf("bmPoolId = %d is invalid \n", pool); + return MV_BAD_PARAM; + } + /* poolBase must be 4 byte aligned */ + if (MV_IS_NOT_ALIGN(poolBase, MV_BM_POOL_PTR_ALIGN)) { + mvOsPrintf("bmPoolBase = 0x%lx is not aligned 4 bytes\n", poolBase); + return MV_NOT_ALIGNED; + } + /* Minimum pool capacity is 128 entries */ + if (capacity < MV_BM_POOL_CAP_MIN) { + mvOsPrintf("bmPool capacity = %d is smaller than minimum (%d)\n", capacity, MV_BM_POOL_CAP_MIN); + return MV_BAD_SIZE; + } + + /* Maximum pool capacity is 4K entries (2^14) */ + if (capacity > MV_BM_POOL_CAP_MAX) { + mvOsPrintf("bmPool capacity = %d is larger than maximum (%d)\n", capacity, MV_BM_POOL_CAP_MAX); + return MV_BAD_SIZE; + } + + /* Set poolBase address */ + MV_REG_WRITE(MV_BM_POOL_BASE_REG(pool), poolBase); + + /* Set Read pointer to 0 */ + MV_REG_WRITE(MV_BM_POOL_READ_PTR_REG(pool), 0); + + /* Set Read pointer to 0 */ + MV_REG_WRITE(MV_BM_POOL_WRITE_PTR_REG(pool), 0); + + /* Set Pool size */ + MV_REG_WRITE(MV_BM_POOL_SIZE_REG(pool), MV_BM_POOL_SIZE_VAL(capacity)); + + return MV_OK; +} + +void mvBmRegs(void) +{ + int pool; + + mvOsPrintf("\n\t Hardware Buffer Management Registers:\n"); + + mvOsPrintf("MV_BM_CONFIG_REG : 0x%X = 0x%08x\n", + MV_BM_CONFIG_REG, MV_REG_READ(MV_BM_CONFIG_REG)); + + mvOsPrintf("MV_BM_COMMAND_REG : 0x%X = 0x%08x\n", + MV_BM_COMMAND_REG, MV_REG_READ(MV_BM_COMMAND_REG)); + + mvOsPrintf("MV_BM_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_BM_INTR_CAUSE_REG, MV_REG_READ(MV_BM_INTR_CAUSE_REG)); + + mvOsPrintf("MV_BM_INTR_MASK_REG : 0x%X = 0x%08x\n", + MV_BM_INTR_MASK_REG, MV_REG_READ(MV_BM_INTR_MASK_REG)); + + mvOsPrintf("MV_BM_XBAR_01_REG : 0x%X = 0x%08x\n", + MV_BM_XBAR_01_REG, MV_REG_READ(MV_BM_XBAR_01_REG)); + + mvOsPrintf("MV_BM_XBAR_23_REG : 0x%X = 0x%08x\n", + MV_BM_XBAR_23_REG, MV_REG_READ(MV_BM_XBAR_23_REG)); + + for (pool = 0; pool < MV_BM_POOLS; pool++) { + mvOsPrintf("\n\t BM Pool #%d registers:\n", pool); + + mvOsPrintf("MV_BM_POOL_BASE_REG : 0x%X = 0x%08x\n", + MV_BM_POOL_BASE_REG(pool), MV_REG_READ(MV_BM_POOL_BASE_REG(pool))); + + mvOsPrintf("MV_BM_POOL_READ_PTR_REG : 0x%X = 0x%08x\n", + MV_BM_POOL_READ_PTR_REG(pool), MV_REG_READ(MV_BM_POOL_READ_PTR_REG(pool))); + + mvOsPrintf("MV_BM_POOL_WRITE_PTR_REG : 0x%X = 0x%08x\n", + MV_BM_POOL_WRITE_PTR_REG(pool), MV_REG_READ(MV_BM_POOL_WRITE_PTR_REG(pool))); + + mvOsPrintf("MV_BM_POOL_SIZE_REG : 0x%X = 0x%08x\n", + MV_BM_POOL_SIZE_REG(pool), MV_REG_READ(MV_BM_POOL_SIZE_REG(pool))); + } + mvOsPrintf("\n"); + + mvOsPrintf("MV_BM_DEBUG_REG : 0x%X = 0x%08x\n", MV_BM_DEBUG_REG, MV_REG_READ(MV_BM_DEBUG_REG)); + + mvOsPrintf("MV_BM_READ_PTR_REG : 0x%X = 0x%08x\n", + MV_BM_READ_PTR_REG, MV_REG_READ(MV_BM_READ_PTR_REG)); + + mvOsPrintf("MV_BM_WRITE_PTR_REG : 0x%X = 0x%08x\n", + MV_BM_WRITE_PTR_REG, MV_REG_READ(MV_BM_WRITE_PTR_REG)); + + mvOsPrintf("\n"); + +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBm.h u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBm.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBm.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBm.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvBm_h__ +#define __mvBm_h__ + +/* includes */ +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvStack.h" +#include "mv802_3.h" + +#include "mvBmRegs.h" + +extern MV_U8 *mvBmVirtBase; +/* defines */ + +/* bits[8-9] of address define pool 0-3 */ +#define BM_POOL_ACCESS_OFFS 8 + +/* INLINE functions */ +static INLINE void mvBmPoolPut(int poolId, MV_ULONG bufPhysAddr) +{ + *((MV_ULONG *)((unsigned)mvBmVirtBase | (poolId << BM_POOL_ACCESS_OFFS))) = (MV_ULONG)(MV_32BIT_LE(bufPhysAddr)); +} + +static INLINE MV_ULONG mvBmPoolGet(int poolId) +{ + MV_U32 bufPhysAddr = *(MV_U32 *)((unsigned)mvBmVirtBase | (poolId << 8)); + + return (MV_ULONG)(MV_32BIT_LE(bufPhysAddr)); +} + +/* prototypes */ +MV_STATUS mvBmInit(MV_U8 *virtBase); +MV_STATUS mvBmControl(MV_COMMAND cmd); +MV_STATE mvBmStateGet(void); +void mvBmPoolTargetSet(int pool, MV_U8 targetId, MV_U8 attr); +void mvBmPoolEnable(int pool); +void mvBmPoolDisable(int pool); +MV_BOOL mvBmPoolIsEnabled(int pool); +MV_STATUS mvBmPoolInit(int pool, MV_ULONG poolBase, int capacity); +void mvBmRegs(void); + +#endif /* __mvBm_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBmRegs.h u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBmRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/bm/mvBmRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/bm/mvBmRegs.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,227 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __mvBmRegs_h__ +#define __mvBmRegs_h__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +#define MV_BM_POOLS 4 +#define MV_BM_POOL_CAP_MAX (16*1024 - MV_BM_POOL_PTR_ALIGN/4) +#define MV_BM_POOL_CAP_MIN 128 +#define MV_BM_POOL_PTR_ALIGN 128 + +/* BM Configuration Register */ +#define MV_BM_CONFIG_REG (MV_BM_REG_BASE + 0x0) + +#define MV_BM_SRC_BURST_SIZE_OFFS 0 +#define MV_BM_SRC_BURST_SIZE_MASK (3 << MV_BM_SRC_BURST_SIZE_OFFS) +#define MV_BM_SRC_BURST_SIZE_128B (0 << MV_BM_SRC_BURST_SIZE_OFFS) +#define MV_BM_SRC_BURST_SIZE_32B (1 << MV_BM_SRC_BURST_SIZE_OFFS) + +#define MV_BM_DST_BURST_SIZE_OFFS 2 +#define MV_BM_DST_BURST_SIZE_MASK (3 << MV_BM_DST_BURST_SIZE_OFFS) +#define MV_BM_DST_BURST_SIZE_128B (0 << MV_BM_DST_BURST_SIZE_OFFS) +#define MV_BM_DST_BURST_SIZE_32B (1 << MV_BM_DST_BURST_SIZE_OFFS) + +#define MV_BM_DST_SWAP_BIT 4 +#define MV_BM_DST_SWAP_MASK (1 << MV_BM_DST_SWAP_BIT) + +#define MV_BM_SRC_SWAP_BIT 5 +#define MV_BM_SRC_SWAP_MASK (1 << MV_BM_SRC_SWAP_BIT) + +#define MV_BM_LOW_THRESH_OFFS 8 +#define MV_BM_LOW_THRESH_MASK (0xF << MV_BM_LOW_THRESH_OFFS) +#define MV_BM_LOW_THRESH_VALUE(val) ((val) << MV_BM_LOW_THRESH_OFFS) + +#define MV_BM_HIGH_THRESH_OFFS 12 +#define MV_BM_HIGH_THRESH_MASK (0xF << MV_BM_HIGH_THRESH_OFFS) +#define MV_BM_HIGH_THRESH_VALUE(val) ((val) << MV_BM_HIGH_THRESH_OFFS) + +#define MV_BM_MAX_IN_BURST_SIZE_OFFS 17 +#define MV_BM_MAX_IN_BURST_SIZE_MASK (3 << MV_BM_MAX_IN_BURST_SIZE_OFFS) +#define MV_BM_MAX_IN_BURST_SIZE_32BP (0 << MV_BM_MAX_IN_BURST_SIZE_OFFS) +#define MV_BM_MAX_IN_BURST_SIZE_24BP (1 << MV_BM_MAX_IN_BURST_SIZE_OFFS) +#define MV_BM_MAX_IN_BURST_SIZE_16BP (2 << MV_BM_MAX_IN_BURST_SIZE_OFFS) +#define MV_BM_MAX_IN_BURST_SIZE_8BP (3 << MV_BM_MAX_IN_BURST_SIZE_OFFS) + +/* BM Activation Register */ +#define MV_BM_COMMAND_REG (MV_BM_REG_BASE + 0x4) + +#define MV_BM_START_BIT 0 +#define MV_BM_START_MASK (1 << MV_BM_START_BIT) + +#define MV_BM_STOP_BIT 1 +#define MV_BM_STOP_MASK (1 << MV_BM_STOP_BIT) + +#define MV_BM_PAUSE_BIT 2 +#define MV_BM_PAUSE_MASK (1 << MV_BM_PAUSE_BIT) + +#define MV_BM_STATUS_OFFS 4 +#define MV_BM_STATUS_ALL_MASK (0x3) +#define MV_BM_STATUS_NOT_ACTIVE (0x0) +#define MV_BM_STATUS_ACTIVE (0x1) +#define MV_BM_STATUS_PAUSED (0x2) +#define MV_BM_STATUS_MASK(status) ((status) << MV_BM_STATUS_OFFS) + +/* BM Xbar interface Register */ +#define MV_BM_XBAR_01_REG (MV_BM_REG_BASE + 0x8) +#define MV_BM_XBAR_23_REG (MV_BM_REG_BASE + 0xC) + +#define MV_BM_XBAR_POOL_REG(pool) (((pool) < 2) ? MV_BM_XBAR_01_REG : MV_BM_XBAR_23_REG) + +#define MV_BM_TARGET_ID_OFFS(pool) (((pool) & 1) ? 16 : 0) +#define MV_BM_TARGET_ID_MASK(pool) (0xF << MV_BM_TARGET_ID_OFFS(pool)) +#define MV_BM_TARGET_ID_VAL(pool, id) ((id) << MV_BM_TARGET_ID_OFFS(pool)) + +#define MV_BM_XBAR_ATTR_OFFS(pool) (((pool) & 1) ? 20 : 4) +#define MV_BM_XBAR_ATTR_MASK(pool) (0xFF << MV_BM_XBAR_ATTR_OFFS(pool)) +#define MV_BM_XBAR_ATTR_VAL(pool, attr) ((attr) << MV_BM_XBAR_ATTR_OFFS(pool)) + +/* Address of External Buffer Pointers Pool Register */ +#define MV_BM_POOL_BASE_REG(pool) (MV_BM_REG_BASE + 0x10 + ((pool) << 4)) + +#define MV_BM_POOL_ENABLE_BIT 0 +#define MV_BM_POOL_ENABLE_MASK (1 << MV_BM_POOL_ENABLE_BIT) + +#define MV_BM_POOL_BASE_ADDR_OFFS 2 +#define MV_BM_POOL_BASE_ADDR_MASK (0x3FFFFFFF << MV_BM_POOL_BASE_ADDR_OFFS) + +/* External Buffer Pointers Pool RD pointer Register */ +#define MV_BM_POOL_READ_PTR_REG(pool) (MV_BM_REG_BASE + 0x14 + ((pool) << 4)) + +#define MV_BM_POOL_SET_READ_PTR_OFFS 0 +#define MV_BM_POOL_SET_READ_PTR_MASK (0xFFFC << MV_BM_POOL_SET_READ_PTR_OFFS) +#define MV_BM_POOL_SET_READ_PTR(val) ((val) << MV_BM_POOL_SET_READ_PTR_OFFS) + +#define MV_BM_POOL_GET_READ_PTR_OFFS 16 +#define MV_BM_POOL_GET_READ_PTR_MASK (0xFFFC << MV_BM_POOL_GET_READ_PTR_OFFS) + + +/* External Buffer Pointers Pool WR pointer */ +#define MV_BM_POOL_WRITE_PTR_REG(pool) (MV_BM_REG_BASE + 0x18 + ((pool) << 4)) + +#define MV_BM_POOL_SET_WRITE_PTR_OFFS 0 +#define MV_BM_POOL_SET_WRITE_PTR_MASK (0xFFFC << MV_BM_POOL_SET_WRITE_PTR_OFFS) +#define MV_BM_POOL_SET_WRITE_PTR(val) ((val) << MV_BM_POOL_SET_WRITE_PTR_OFFS) + +#define MV_BM_POOL_GET_WRITE_PTR_OFFS 16 +#define MV_BM_POOL_GET_WRITE_PTR_MASK (0xFFFC << MV_BM_POOL_GET_WRITE_PTR_OFFS) + +/* External Buffer Pointers Pool Size Register */ +#define MV_BM_POOL_SIZE_REG(pool) (MV_BM_REG_BASE + 0x1C + ((pool) << 4)) + +#define MV_BM_POOL_SIZE_OFFS 0 +#define MV_BM_POOL_SIZE_MASK (0x3FFF << MV_BM_POOL_SIZE_OFFS) +#define MV_BM_POOL_SIZE_VAL(size) ((size) << MV_BM_POOL_SIZE_OFFS) + + +/* BM Interrupt Cause Register */ +#define MV_BM_INTR_CAUSE_REG (MV_BM_REG_BASE + 0x50) + +#define MV_BM_CAUSE_FREE_FAIL_BIT(p) (0 + ((p) * 6)) +#define MV_BM_CAUSE_FREE_FAIL_MASK(p) (1 << MV_BM_CAUSE_FREE_FAIL_BIT(p)) + +#define MV_BM_CAUSE_ALLOC_FAIL_BIT(p) (1 + ((p) * 6)) +#define MV_BM_CAUSE_ALLOC_FAIL_MASK(p) (1 << MV_BM_CAUSE_ALLOC_FAIL_BIT(p)) + +#define MV_BM_CAUSE_POOL_EMPTY_BIT(p) (2 + ((p) * 6)) +#define MV_BM_CAUSE_POOL_EMPTY_MASK(p) (1 << MV_BM_CAUSE_POOL_EMPTY_BIT(p)) + +#define MV_BM_CAUSE_POOL_FULL_BIT(p) (3 + ((p) * 6)) +#define MV_BM_CAUSE_POOL_FULL_MASK(p) (1 << MV_BM_CAUSE_POOL_FULL_BIT(p)) + +#define MV_BM_CAUSE_INT_PAR_ERR_BIT 27 +#define MV_BM_CAUSE_INT_PAR_ERR_MASK (1 << MV_BM_CAUSE_INT_PAR_ERR_MASK) + +#define MV_BM_CAUSE_XBAR_PAR_ERR_BIT 28 +#define MV_BM_CAUSE_XBAR_PAR_ERR_MASK (1 << MV_BM_CAUSE_XBAR_PAR_ERR_MASK) + +#define MV_BM_CAUSE_STOPPED_BIT 29 +#define MV_BM_CAUSE_STOPPED_MASK (1 << MV_BM_CAUSE_STOPPED_MASK) + +#define MV_BM_CAUSE_PAUSED_BIT 30 +#define MV_BM_CAUSE_PAUSED_MASK (1 << MV_BM_CAUSE_PAUSED_MASK) + +#define MV_BM_CAUSE_SUMMARY_BIT 31 +#define MV_BM_CAUSE_SUMMARY_MASK (1 << MV_BM_CAUSE_SUMMARY_MASK) + +/* BM interrupt Mask Register */ +#define MV_BM_INTR_MASK_REG (MV_BM_REG_BASE + 0x54) + +#define MV_BM_DEBUG_REG (MV_BM_REG_BASE + 0x60) +#define MV_BM_READ_PTR_REG (MV_BM_REG_BASE + 0x64) +#define MV_BM_WRITE_PTR_REG (MV_BM_REG_BASE + 0x68) + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __mvBmRegs_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvEthRegs.h u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvEthRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvEthRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvEthRegs.h 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,624 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvEthRegsh +#define __INCmvEthRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvNetaRegs.h" + +#define MV_ETH_MH_SIZE 2 +#define MV_ETH_CRC_SIZE 4 + +#define ETH_MAX_DECODE_WIN 6 +#define ETH_MAX_HIGH_ADDR_REMAP_WIN 4 + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ +#define ETH_REG_BASE(port) MV_ETH_REGS_BASE(port) + +#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x2000) +#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x2004) +#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x2008) +#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x200c) +#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x2014) +#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x2080) +#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x2084) + +#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x2094) +#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x2098) + +/* Ethernet Unit Control (EUC) register */ +#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x20B0) + +#define ETH_PHY_POLLING_ENABLE_BIT 1 +#define ETH_PHY_POLLING_ENABLE_MASK (1 << ETH_PHY_POLLING_ENABLE_BIT) + +#define ETH_UNIT_PORT_RESET_BIT 24 +#define ETH_UNIT_PORT_RESET_MASK (1 << ETH_UNIT_PORT_RESET_BIT) +/*-----------------------------------------------------------------------------------------------*/ + +/**** Address decode registers ****/ + +#define ETH_WIN_BASE_REG(port, win) (ETH_REG_BASE(port) + 0x2200 + ((win) << 3)) +#define ETH_WIN_SIZE_REG(port, win) (ETH_REG_BASE(port) + 0x2204 + ((win) << 3)) +#define ETH_WIN_REMAP_REG(port, win) (ETH_REG_BASE(port) + 0x2280 + ((win) << 2)) +#define ETH_BASE_ADDR_ENABLE_REG(port) (ETH_REG_BASE(port) + 0x2290) +#define ETH_ACCESS_PROTECT_REG(port) (ETH_REG_BASE(port) + 0x2294) + +/* The target associated with this window*/ +#define ETH_WIN_TARGET_OFFS 0 +#define ETH_WIN_TARGET_MASK (0xf << ETH_WIN_TARGET_OFFS) +/* The target attributes associated with window */ +#define ETH_WIN_ATTR_OFFS 8 +#define ETH_WIN_ATTR_MASK (0xff << ETH_WIN_ATTR_OFFS) + +/* The Base address associated with window */ +#define ETH_WIN_BASE_OFFS 16 +#define ETH_WIN_BASE_MASK (0xFFFF << ETH_WIN_BASE_OFFS) + +#define ETH_WIN_SIZE_OFFS 16 +#define ETH_WIN_SIZE_MASK (0xFFFF << ETH_WIN_SIZE_OFFS) + + /* Ethernet Port Access Protect Register (EPAPR) */ +#define ETH_PROT_NO_ACCESS 0 +#define ETH_PROT_READ_ONLY 1 +#define ETH_PROT_FULL_ACCESS 3 +#define ETH_PROT_WIN_OFFS(winNum) (2 * (winNum)) +#define ETH_PROT_WIN_MASK(winNum) (0x3 << ETH_PROT_WIN_OFFS(winNum)) +/*-----------------------------------------------------------------------------------------------*/ + + +/***** Port Configuration reg (PxCR) *****/ +#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x2400) + +#define ETH_UNICAST_PROMISCUOUS_MODE_BIT 0 +#define ETH_UNICAST_PROMISCUOUS_MODE_MASK (1 << ETH_UNICAST_PROMISCUOUS_MODE_BIT) + +#define ETH_DEF_RX_QUEUE_OFFSET 1 +#define ETH_DEF_RX_QUEUE_ALL_MASK (0x7 << ETH_DEF_RX_QUEUE_OFFSET) +#define ETH_DEF_RX_QUEUE_MASK(queue) ((queue) << ETH_DEF_RX_QUEUE_OFFSET) + +#define ETH_DEF_RX_ARP_QUEUE_OFFSET 4 +#define ETH_DEF_RX_ARP_QUEUE_ALL_MASK (0x7 << ETH_DEF_RX_ARP_QUEUE_OFFSET) +#define ETH_DEF_RX_ARP_QUEUE_MASK(queue) ((queue) << ETH_DEF_RX_ARP_QUEUE_OFFSET) + +#define ETH_REJECT_NOT_IP_ARP_BCAST_BIT 7 +#define ETH_REJECT_NOT_IP_ARP_BCAST_MASK (1 << ETH_REJECT_NOT_IP_ARP_BCAST_BIT) + +#define ETH_REJECT_IP_BCAST_BIT 8 +#define ETH_REJECT_IP_BCAST_MASK (1 << ETH_REJECT_IP_BCAST_BIT) + +#define ETH_REJECT_ARP_BCAST_BIT 9 +#define ETH_REJECT_ARP_BCAST_MASK (1 << ETH_REJECT_ARP_BCAST_BIT) + +#define ETH_TX_NO_SET_ERROR_SUMMARY_BIT 12 +#define ETH_TX_NO_SET_ERROR_SUMMARY_MASK (1 << ETH_TX_NO_SET_ERROR_SUMMARY_BIT) + +#define ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT 14 +#define ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK (1 << ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT) + +#define ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT 15 +#define ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK (1 << ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT) + +#define ETH_DEF_RX_TCP_QUEUE_OFFSET 16 +#define ETH_DEF_RX_TCP_QUEUE_ALL_MASK (0x7 << ETH_DEF_RX_TCP_QUEUE_OFFSET) +#define ETH_DEF_RX_TCP_QUEUE_MASK(queue) ((queue) << ETH_DEF_RX_TCP_QUEUE_OFFSET) + +#define ETH_DEF_RX_UDP_QUEUE_OFFSET 19 +#define ETH_DEF_RX_UDP_QUEUE_ALL_MASK (0x7 << ETH_DEF_RX_UDP_QUEUE_OFFSET) +#define ETH_DEF_RX_UDP_QUEUE_MASK(queue) ((queue) << ETH_DEF_RX_UDP_QUEUE_OFFSET) + +#define ETH_DEF_RX_BPDU_QUEUE_OFFSET 22 +#define ETH_DEF_RX_BPDU_QUEUE_ALL_MASK (0x7 << ETH_DEF_RX_BPDU_QUEUE_OFFSET) +#define ETH_DEF_RX_BPDU_QUEUE_MASK(queue) ((queue) << ETH_DEF_RX_BPDU_QUEUE_OFFSET) + +#define ETH_RX_CHECKSUM_MODE_OFFSET 25 +#define ETH_RX_CHECKSUM_NO_PSEUDO_HDR (0 << ETH_RX_CHECKSUM_MODE_OFFSET) +#define ETH_RX_CHECKSUM_WITH_PSEUDO_HDR (1 << ETH_RX_CHECKSUM_MODE_OFFSET) +/*-----------------------------------------------------------------------------------------------*/ + +/***** Port Configuration Extend reg (PxCXR) *****/ +#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x2404) + +#define ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT 1 +#define ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK (1 << ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT) + +#define ETH_TX_DISABLE_GEN_CRC_BIT 3 +#define ETH_TX_DISABLE_GEN_CRC_MASK (1 << ETH_TX_DISABLE_GEN_CRC_BIT) +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x2410) +#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x2414) +#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x2418) + + +/***** Port Sdma Configuration reg (SDCR) *****/ +#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x241c) + +#define ETH_RX_FRAME_INTERRUPT_BIT 0 +#define ETH_RX_FRAME_INTERRUPT_MASK (1 << ETH_RX_FRAME_INTERRUPT_BIT) + +#define ETH_BURST_SIZE_1_64BIT_VALUE 0 +#define ETH_BURST_SIZE_2_64BIT_VALUE 1 +#define ETH_BURST_SIZE_4_64BIT_VALUE 2 +#define ETH_BURST_SIZE_8_64BIT_VALUE 3 +#define ETH_BURST_SIZE_16_64BIT_VALUE 4 + +#define ETH_RX_BURST_SIZE_OFFSET 1 +#define ETH_RX_BURST_SIZE_ALL_MASK (0x7 << ETH_RX_BURST_SIZE_OFFSET) +#define ETH_RX_BURST_SIZE_MASK(burst) ((burst) << ETH_RX_BURST_SIZE_OFFSET) + +#define ETH_RX_NO_DATA_SWAP_BIT 4 +#define ETH_RX_NO_DATA_SWAP_MASK (1 << ETH_RX_NO_DATA_SWAP_BIT) +#define ETH_RX_DATA_SWAP_MASK (0 << ETH_RX_NO_DATA_SWAP_BIT) + +#define ETH_TX_NO_DATA_SWAP_BIT 5 +#define ETH_TX_NO_DATA_SWAP_MASK (1 << ETH_TX_NO_DATA_SWAP_BIT) +#define ETH_TX_DATA_SWAP_MASK (0 << ETH_TX_NO_DATA_SWAP_BIT) + +#define ETH_DESC_SWAP_BIT 6 +#define ETH_DESC_SWAP_MASK (1 << ETH_DESC_SWAP_BIT) +#define ETH_NO_DESC_SWAP_MASK (0 << ETH_DESC_SWAP_BIT) + +#define ETH_TX_BURST_SIZE_OFFSET 22 +#define ETH_TX_BURST_SIZE_ALL_MASK (0x7 << ETH_TX_BURST_SIZE_OFFSET) +#define ETH_TX_BURST_SIZE_MASK(burst) ((burst) << ETH_TX_BURST_SIZE_OFFSET) +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x2420 + ((code) << 2)) + +/* Port Serial Control0 register (PSC0) */ +#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x243c) + +#define ETH_TX_FC_MODE_OFFSET 5 +#define ETH_TX_FC_MODE_MASK (3 << ETH_TX_FC_MODE_OFFSET) +#define ETH_TX_FC_NO_PAUSE (0 << ETH_TX_FC_MODE_OFFSET) +#define ETH_TX_FC_SEND_PAUSE (1 << ETH_TX_FC_MODE_OFFSET) + +#define ETH_TX_BP_MODE_OFFSET 7 +#define ETH_TX_BP_MODE_MASK (3 << ETH_TX_BP_MODE_OFFSET) +#define ETH_TX_BP_NO_JAM (0 << ETH_TX_BP_MODE_OFFSET) +#define ETH_TX_BP_SEND_JAM (1 << ETH_TX_BP_MODE_OFFSET) + +#define ETH_RETRANSMIT_FOREVER_BIT 11 +#define ETH_RETRANSMIT_FOREVER_MASK (1 << ETH_RETRANSMIT_FOREVER_BIT) + +#define ETH_DTE_ADVERT_BIT 14 +#define ETH_DTE_ADVERT_MASK (1 << ETH_DTE_ADVERT_BIT) + +/* Other bits are different for new GMAC and old GMAC modules */ +#ifdef MV_ETH_GMAC_NEW + +#define ETH_IGNORE_RX_ERR_BIT 28 +#define ETH_IGNORE_RX_ERR_MASK (1 << ETH_IGNORE_RX_ERR_BIT) + +#define ETH_IGNORE_COL_BIT 29 +#define ETH_IGNORE_COL_MASK (1 << ETH_IGNORE_COL_BIT) + +#define ETH_IGNORE_CARRIER_SENSE_BIT 30 +#define ETH_IGNORE_CARRIER_SENSE_MASK (1 << ETH_IGNORE_CARRIER_SENSE_BIT) + +#else /* Old GMAC */ + +#define ETH_PORT_ENABLE_BIT 0 +#define ETH_PORT_ENABLE_MASK (1 << ETH_PORT_ENABLE_BIT) + +#define ETH_FORCE_LINK_PASS_BIT 1 +#define ETH_FORCE_LINK_PASS_MASK (1 << ETH_FORCE_LINK_PASS_BIT) + +#define ETH_DISABLE_DUPLEX_AUTO_NEG_BIT 2 +#define ETH_DISABLE_DUPLEX_AUTO_NEG_MASK (1 << ETH_DISABLE_DUPLEX_AUTO_NEG_BIT) + +#define ETH_DISABLE_FC_AUTO_NEG_BIT 3 +#define ETH_DISABLE_FC_AUTO_NEG_MASK (1 << ETH_DISABLE_FC_AUTO_NEG_BIT) + +#define ETH_ADVERTISE_SYM_FC_BIT 4 +#define ETH_ADVERTISE_SYM_FC_MASK (1 << ETH_ADVERTISE_SYM_FC_BIT) + +#define ETH_DO_NOT_FORCE_LINK_FAIL_BIT 10 +#define ETH_DO_NOT_FORCE_LINK_FAIL_MASK (1 << ETH_DO_NOT_FORCE_LINK_FAIL_BIT) + +#define ETH_DISABLE_SPEED_AUTO_NEG_BIT 13 +#define ETH_DISABLE_SPEED_AUTO_NEG_MASK (1 << ETH_DISABLE_SPEED_AUTO_NEG_BIT) + +#define ETH_MAX_RX_PACKET_SIZE_OFFSET 17 +#define ETH_MAX_RX_PACKET_SIZE_MASK (7 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_1518BYTE (0 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_1522BYTE (1 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_1552BYTE (2 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_9022BYTE (3 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_9192BYTE (4 << ETH_MAX_RX_PACKET_SIZE_OFFSET) +#define ETH_MAX_RX_PACKET_9700BYTE (5 << ETH_MAX_RX_PACKET_SIZE_OFFSET) + +#define ETH_SET_FULL_DUPLEX_BIT 21 +#define ETH_SET_FULL_DUPLEX_MASK (1 << ETH_SET_FULL_DUPLEX_BIT) + +#define ETH_SET_FLOW_CTRL_BIT 22 +#define ETH_SET_FLOW_CTRL_MASK (1 << ETH_SET_FLOW_CTRL_BIT) + +#define ETH_SET_GMII_SPEED_1000_BIT 23 +#define ETH_SET_GMII_SPEED_1000_MASK (1 << ETH_SET_GMII_SPEED_1000_BIT) + +#define ETH_SET_MII_SPEED_100_BIT 24 +#define ETH_SET_MII_SPEED_100_MASK (1 << ETH_SET_MII_SPEED_100_BIT) + +#endif /* MV_ETH_GMAC_NEW */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x2440) + +/***** Ethernet Port Status reg (PSR) *****/ +#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x2444) + +/* Other bits are different for new GMAC and old GMAC modules */ +#ifdef MV_ETH_GMAC_NEW + +#define ETH_TX_IN_PROGRESS_OFFS 0 +#define ETH_TX_IN_PROGRESS_MASK(txp) (1 << ((txp) + ETH_TX_IN_PROGRESS_OFFS)) +#define ETH_TX_IN_PROGRESS_ALL_MASK (0xFF << ETH_TX_IN_PROGRESS_OFFS) + +#define ETH_TX_FIFO_EMPTY_OFFS 8 +#define ETH_TX_FIFO_EMPTY_MASK(txp) (1 << ((txp) + ETH_TX_FIFO_EMPTY_OFFS)) +#define ETH_TX_FIFO_EMPTY_ALL_MASK (0xFF << ETH_TX_FIFO_EMPTY_OFFS) + +#define ETH_RX_FIFO_EMPTY_BIT 16 +#define ETH_RX_FIFO_EMPTY_MASK (1 << ETH_RX_FIFO_EMPTY_BIT) + +#else /* Old GMAC */ + +#define ETH_LINK_UP_BIT 1 +#define ETH_LINK_UP_MASK (1 << ETH_LINK_UP_BIT) + +#define ETH_FULL_DUPLEX_BIT 2 +#define ETH_FULL_DUPLEX_MASK (1 << ETH_FULL_DUPLEX_BIT) + +#define ETH_FLOW_CTRL_ENABLED_BIT 3 +#define ETH_FLOW_CTRL_ENABLED_MASK (1 << ETH_FLOW_CTRL_ENABLED_BIT) + +#define ETH_GMII_SPEED_1000_BIT 4 +#define ETH_GMII_SPEED_1000_MASK (1 << ETH_GMII_SPEED_1000_BIT) + +#define ETH_MII_SPEED_100_BIT 5 +#define ETH_MII_SPEED_100_MASK (1 << ETH_MII_SPEED_100_BIT) + +#define ETH_TX_IN_PROGRESS_BIT 7 +#define ETH_TX_IN_PROGRESS_MASK (1 << ETH_TX_IN_PROGRESS_BIT) + +#define ETH_TX_FIFO_EMPTY_BIT 10 +#define ETH_TX_FIFO_EMPTY_MASK (1 << ETH_TX_FIFO_EMPTY_BIT) + +#define ETH_RX_FIFO_EMPTY_BIT 12 +#define ETH_RX_FIFO_EMPTY_MASK (1 << ETH_RX_FIFO_EMPTY_BIT) + +#define PON_TX_IN_PROGRESS_OFFS 0 +#define PON_TX_IN_PROGRESS_MASK(txp) (1 << ((txp) + PON_TX_IN_PROGRESS_OFFS)) +#define PON_TX_IN_PROGRESS_ALL_MASK (0xFF << PON_TX_IN_PROGRESS_OFFS) + +#define PON_TX_FIFO_EMPTY_OFFS 8 +#define PON_TX_FIFO_EMPTY_MASK(txp) (1 << ((txp) + PON_TX_FIFO_EMPTY_OFFS)) +#define PON_TX_FIFO_EMPTY_ALL_MASK (0xFF << PON_TX_FIFO_EMPTY_OFFS) + +#endif /* MV_ETH_GMAC_NEW */ +/*-----------------------------------------------------------------------------------------------*/ + + +/***** Transmit Queue Command (TxQC) register *****/ +#define ETH_TX_QUEUE_COMMAND_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x0048) + +#define ETH_TXQ_ENABLE_OFFSET 0 +#define ETH_TXQ_ENABLE_MASK (0x000000FF << ETH_TXQ_ENABLE_OFFSET) + +#define ETH_TXQ_DISABLE_OFFSET 8 +#define ETH_TXQ_DISABLE_MASK (0x000000FF << ETH_TXQ_DISABLE_OFFSET) +/*-----------------------------------------------------------------------------------------------*/ + +/* Marvell Header Register */ +#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x2454) + +#define ETH_MH_EN_BIT 0 +#define ETH_MH_EN_MASK (1 << ETH_MH_EN_BIT) + +#define ETH_DSA_EN_OFFS 10 +#define ETH_DSA_EN_MASK (3 << ETH_DSA_EN_OFFS) +#define ETH_DSA_MASK (1 << ETH_DSA_EN_OFFS) +#define ETH_DSA_EXT_MASK (2 << ETH_DSA_EN_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Ethernet Cause Register */ +#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x2460) + +#define ETH_CAUSE_RX_READY_SUM_BIT 0 +#define ETH_CAUSE_EXTEND_BIT 1 + +#define ETH_CAUSE_RX_READY_OFFSET 2 +#define ETH_CAUSE_RX_READY_BIT(queue) (ETH_CAUSE_RX_READY_OFFSET + (queue)) +#define ETH_CAUSE_RX_READY_MASK(queue) (1 << (ETH_CAUSE_RX_READY_BIT(queue))) + +#define ETH_CAUSE_RX_ERROR_SUM_BIT 10 +#define ETH_CAUSE_RX_ERROR_OFFSET 11 +#define ETH_CAUSE_RX_ERROR_BIT(queue) (ETH_CAUSE_RX_ERROR_OFFSET + (queue)) +#define ETH_CAUSE_RX_ERROR_MASK(queue) (1 << (ETH_CAUSE_RX_ERROR_BIT(queue))) + +#define ETH_CAUSE_TX_END_BIT 19 +#define ETH_CAUSE_SUM_BIT 31 +/*-----------------------------------------------------------------------------------------------*/ + +/* Ethernet Cause Extended Register */ +#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x2464) + +#define ETH_CAUSE_TX_BUF_OFFSET 0 +#define ETH_CAUSE_TX_BUF_BIT(queue) (ETH_CAUSE_TX_BUF_OFFSET + (queue)) +#define ETH_CAUSE_TX_BUF_MASK(queue) (1 << (ETH_CAUSE_TX_BUF_BIT(queue))) + +#define ETH_CAUSE_TX_ERROR_OFFSET 8 +#define ETH_CAUSE_TX_ERROR_BIT(queue) (ETH_CAUSE_TX_ERROR_OFFSET + (queue)) +#define ETH_CAUSE_TX_ERROR_MASK(queue) (1 << (ETH_CAUSE_TX_ERROR_BIT(queue))) + +#define ETH_CAUSE_PHY_STATUS_CHANGE_BIT 16 +#define ETH_CAUSE_RX_OVERRUN_BIT 18 +#define ETH_CAUSE_TX_UNDERRUN_BIT 19 +#define ETH_CAUSE_LINK_STATE_CHANGE_BIT 20 +#define ETH_CAUSE_INTERNAL_ADDR_ERR_BIT 23 +#define ETH_CAUSE_EXTEND_SUM_BIT 31 +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x2468) +#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x246c) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x247c) +#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x2484) +#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x2488) +#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x2494) + +/***** Receive Queue Command (RxQC) register *****/ +#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x2680) + +#define ETH_RXQ_ENABLE_OFFSET 0 +#define ETH_RXQ_ENABLE_MASK (0x000000FF << ETH_RXQ_ENABLE_OFFSET) + +#define ETH_RXQ_DISABLE_OFFSET 8 +#define ETH_RXQ_DISABLE_MASK (0x000000FF << ETH_RXQ_DISABLE_OFFSET) +/*-----------------------------------------------------------------------------------------------*/ + +/******************************** WRR Legacy rigisters ********************************************/ + +#ifndef MV_ETH_WRR_NEW + +/* Transmit Queue Fixed Priority Configuration (TQFPC) */ +#define ETH_TX_FIXED_PRIO_CFG_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x00dc) + +#define ETH_TX_FIXED_PRIO_OFFS 0 +#define ETH_TX_FIXED_PRIO_MASK (0xFF << ETH_TX_FIXED_PRIO_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Transmit Token-Bucket Rate Configuration (PTTBRC) */ +#define ETH_TXP_TOKEN_RATE_CFG_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x00e0) + +#define ETH_TXP_TOKEN_RATE_OFFS 0 +#define ETH_TXP_TOKEN_RATE_MAX 0x3FF +#define ETH_TXP_TOKEN_RATE_ALL_MASK (ETH_TXP_TOKEN_RATE_MAX << ETH_TXP_TOKEN_RATE_OFFS) +#define ETH_TXP_TOKEN_RATE_MASK(rate) ((rate) << ETH_TXP_TOKEN_RATE_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmit Queue Command1 (TQC1) - reserved */ +#define ETH_TXQ_CMD_1_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x00e4) +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_MAX_TRANSMIT_UNIT_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x00e8) + +#define ETH_TX_MTU_OFFS 0 +#define ETH_TX_MTU_MASK (0x3F << ETH_TX_MTU_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Maximum Token Bucket Size (PMTBS) */ +#define ETH_TXP_TOKEN_SIZE_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x00ec) + +#define ETH_TXP_TOKEN_SIZE_OFFS 0 +#define ETH_TXP_TOKEN_SIZE_MAX 0xFFFF +#define ETH_TXP_TOKEN_SIZE_ALL_MASK (ETH_TXP_TOKEN_SIZE_MAX << ETH_TXP_TOKEN_SIZE_OFFS) +#define ETH_TXP_TOKEN_SIZE_MASK(size) ((size) << ETH_TXP_TOKEN_SIZE_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_TXQ_TOKEN_COUNT_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x0300 + ((q) << 4)) + +#define ETH_TXQ_TOKEN_COUNT_OFFS 0 +#define ETH_TXQ_TOKEN_COUNT_MASK (0x3FFFFFFF << ETH_TXQ_TOKEN_COUNT_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmit Queue Token Bucket Configuration (TQxTBC) */ +#define ETH_TXQ_TOKEN_CFG_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x0304 + ((q) << 4)) + +#define ETH_TXQ_TOKEN_RATE_OFFS 0 +#define ETH_TXQ_TOKEN_RATE_MAX 0x3FF +#define ETH_TXQ_TOKEN_RATE_ALL_MASK (ETH_TXQ_TOKEN_RATE_MAX << ETH_TXQ_TOKEN_RATE_OFFS) +#define ETH_TXQ_TOKEN_RATE_MASK(size) ((size) << ETH_TXQ_TOKEN_RATE_OFFS) + +#define ETH_TXQ_TOKEN_SIZE_OFFS 10 +#define ETH_TXQ_TOKEN_SIZE_MAX 0xFFFF +#define ETH_TXQ_TOKEN_SIZE_ALL_MASK (ETH_TXQ_TOKEN_SIZE_MAX << ETH_TXQ_TOKEN_SIZE_OFFS) +#define ETH_TXQ_TOKEN_SIZE_MASK(size) ((size) << ETH_TXQ_TOKEN_SIZE_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmit Queue Arbiter Configuration (TQxAC) register */ +#define ETH_TXQ_ARBITER_CFG_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x0308 + ((q) << 4)) + +#define ETH_TXQ_WRR_WEIGHT_OFFS 0 +#define ETH_TXQ_WRR_WEIGHT_MAX 0xFF +#define ETH_TXQ_WRR_WEIGHT_ALL_MASK (ETH_TXQ_WRR_WEIGHT_MAX << ETH_TXQ_WRR_WEIGHT_OFFS) +#define ETH_TXQ_WRR_WEIGHT_MASK(weigth) ((weigth) << ETH_TXQ_WRR_WEIGHT_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Transmit Token-Bucket Counter (PTTBC) */ +#define ETH_TXP_TOKEN_COUNT_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x0380) +#define ETH_TXP_TOKEN_COUNT_OFFS 0 +#define ETH_TXP_TOKEN_COUNT_MASK (0x3FFFFFFF << ETH_TXP_TOKEN_COUNT_OFFS) + +#endif /* MV_ETH_WRR_NEW */ +/**************************************************************************************************/ + + +#define ETH_MIB_COUNTERS_BASE(port, txp) (ETH_REG_BASE(port) + 0x3000 + ((txp) * 0x80)) +#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x3400) +#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x3500) +#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x3600) + +/* Phy address register definitions */ +#define ETH_PHY_ADDR_OFFS 0 +#define ETH_PHY_ADDR_MASK (0x1f << ETH_PHY_ADDR_OFFS) + +/* MIB Counters register definitions */ +#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 +#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 +#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 +#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc +#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 +#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 +#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 +#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c +#define ETH_MIB_FRAMES_64_OCTETS 0x20 +#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 +#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c +#define ETH_MIB_GOOD_FRAMES_SENT 0x40 +#define ETH_MIB_EXCESSIVE_COLLISION 0x44 +#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 +#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c +#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 +#define ETH_MIB_FC_SENT 0x54 +#define ETH_MIB_GOOD_FC_RECEIVED 0x58 +#define ETH_MIB_BAD_FC_RECEIVED 0x5c +#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 +#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 +#define ETH_MIB_OVERSIZE_RECEIVED 0x68 +#define ETH_MIB_JABBER_RECEIVED 0x6c +#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 +#define ETH_MIB_BAD_CRC_EVENT 0x74 +#define ETH_MIB_COLLISION 0x78 +#define ETH_MIB_LATE_COLLISION 0x7c + + +#ifndef MV_ETH_GMAC_NEW +/*****************************************************/ +/* Registers are not exist in new GMAC */ +/*****************************************************/ +#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x2408) +#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x240c) + +/* Port Serial Control1 (PSC1) */ +#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x244c) +#define ETH_PSC_ENABLE_BIT 2 +#define ETH_PSC_ENABLE_MASK (1 << ETH_PSC_ENABLE_BIT) + +#define ETH_RGMII_ENABLE_BIT 3 +#define ETH_RGMII_ENABLE_MASK (1 << ETH_RGMII_ENABLE_BIT) + +#define ETH_PORT_RESET_BIT 4 +#define ETH_PORT_RESET_MASK (1 << ETH_PORT_RESET_BIT) + +#define ETH_INBAND_AUTO_NEG_ENABLE_BIT 6 +#define ETH_INBAND_AUTO_NEG_ENABLE_MASK (1 << ETH_INBAND_AUTO_NEG_ENABLE_BIT) + +#define ETH_INBAND_AUTO_NEG_BYPASS_BIT 7 +#define ETH_INBAND_AUTO_NEG_BYPASS_MASK (1 << ETH_INBAND_AUTO_NEG_BYPASS_BIT) + +#define ETH_INBAND_AUTO_NEG_START_BIT 8 +#define ETH_INBAND_AUTO_NEG_START_MASK (1 << ETH_INBAND_AUTO_NEG_START_BIT) + +#define ETH_PORT_TYPE_BIT 11 +#define ETH_PORT_TYPE_1000BasedX_MASK (1 << ETH_PORT_TYPE_BIT) + +#define ETH_SGMII_MODE_BIT 12 +#define ETH_1000BaseX_MODE_MASK (0 << ETH_SGMII_MODE_BIT) +#define ETH_SGMII_MODE_MASK (1 << ETH_SGMII_MODE_BIT) + +#define ETH_MGMII_MODE_BIT 13 + +#define ETH_EN_MII_ODD_PRE_BIT 22 +#define ETH_EN_MII_ODD_PRE_MASK (1 << ETH_EN_MII_ODD_PRE_BIT) +/*-----------------------------------------------------------------------------------------------*/ + +/* Ethernet Port Status1 (PS1) */ +#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x2450) +#define ETH_AUTO_NEG_DONE_BIT 4 +#define ETH_AUTO_NEG_DONE_MASK (1 << ETH_AUTO_NEG_DONE_BIT) +/*-----------------------------------------------------------------------------------------------*/ + +#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x2458) + +#endif /* MV_ETH_GMAC_NEW */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvEthRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvHwf.c u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvHwf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvHwf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvHwf.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,244 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" /* Should be included before mvSysHwConfig */ +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvOs.h" +#include "mvNeta.h" +#include "bm/mvBm.h" + +/*#define HWF_DBG mvOsPrintf*/ +#define HWF_DBG(X...) + +/******************************************************************************* +* mvNetaHwfInit - Init HWF registers of the port +* DESCRIPTION: +* +* INPUT: +* int port - NETA port number +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* +* NOTE: +*******************************************************************************/ +MV_STATUS mvNetaHwfInit(int port) +{ + int p, txp, txq; + MV_U32 regVal; + MV_NETA_PORT_CTRL *pPortCtrl; + + if ((port < 0) || (port >= mvNetaHalData.maxPort)) { + mvOsPrintf("%s: port %d is out of range\n", __func__, port); + return MV_OUT_OF_RANGE; + } + + pPortCtrl = mvNetaPortHndlGet(port); + if (pPortCtrl == NULL) { + mvOsPrintf("%s: port %d is not initialized\n", __func__, port); + return MV_FAIL; + } + + /* Set TX Port base addresses and TXQ address and size */ + for (p = 0; p < mvNetaHalData.maxPort; p++) { + pPortCtrl = mvNetaPortHndlGet(p); + if (pPortCtrl == NULL) + continue; + + for (txp = 0; txp < pPortCtrl->txpNum; txp++) { + regVal = MV_REG_READ(NETA_HWF_TXP_CFG_REG(port, (p + txp))); + regVal &= ~NETA_TXP_BASE_ADDR_MASK(p + txp); + regVal |= ((NETA_TX_REG_BASE(p, txp) >> 10) << NETA_TXP_BASE_ADDR_OFFS(p + txp)); + MV_REG_WRITE(NETA_HWF_TXP_CFG_REG(port, (p + txp)), regVal); + + for (txq = 0; txq < CONFIG_MV_ETH_TXQ; txq++) { + int dropThresh; + + MV_NETA_QUEUE_CTRL *pQueueCtrl = + &pPortCtrl->pTxQueue[txp * CONFIG_MV_ETH_TXQ + txq].queueCtrl; + + if (pQueueCtrl->pFirst == NULL) + continue; + + regVal = NETA_HWF_TX_PORT_MASK(p + txp) | NETA_HWF_TXQ_MASK(txq); + MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal); + MV_REG_WRITE(NETA_HWF_TXQ_BASE_REG(port), pQueueCtrl->descBuf.bufPhysAddr); + MV_REG_WRITE(NETA_HWF_TXQ_SIZE_REG(port), pQueueCtrl->lastDesc + 1); + + dropThresh = (CONFIG_MV_ETH_HWF_TXQ_DROP * (pQueueCtrl->lastDesc + 1)) / 100; + regVal = (dropThresh << NETA_YELLOW_DROP_THRESH_OFFS) | + (CONFIG_MV_ETH_HWF_TXQ_DROP_RND << NETA_YELLOW_DROP_RND_GEN_OFFS); + + MV_REG_WRITE(NETA_HWF_DROP_TH_REG(port), regVal); + } + } + } + /* Init HWF RX Control register */ + regVal = NETA_GEM_PID_SRC_FLOW_ID | NETA_HWF_LONG_POOL_ID(port) | NETA_HWF_SHORT_POOL_ID(MV_BM_POOLS - 1); + + if (MV_PON_PORT(port)) + regVal |= NETA_MH_REPLACE_MH_REG(1); + else + regVal |= NETA_MH_REPLACE_GPON_HDR; + + MV_REG_WRITE(NETA_HWF_RX_CTRL_REG(port), regVal); + + return MV_OK; +} + +/******************************************************************************* + * mvNetaHwfEnable - Enable / Disable HWF of the port + * DESCRIPTION: + * + * INPUT: + * int port - port number + * int enable - 0 - disable, 1 - enable + * + * RETURN: MV_STATUS + * MV_OK - Success, Others - Failure + * + * NOTE: + *******************************************************************************/ +MV_STATUS mvNetaHwfEnable(int port, int enable) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_HWF_RX_CTRL_REG(port)); + if (enable) + regVal |= NETA_HWF_ENABLE_MASK; + else + regVal &= ~NETA_HWF_ENABLE_MASK; + + MV_REG_WRITE(NETA_HWF_RX_CTRL_REG(port), regVal); + + return MV_OK; +} + +/******************************************************************************* + * mvNetaHwfTxqEnable - Enable / Disable HWF of the port + * DESCRIPTION: + * + * INPUT: + * int rx_port: RX port number + * int tx_port, txp, txq: port, TCONT and TXQ numbers + * int enable: 0 - disable, 1 - enable + * + * RETURN: MV_STATUS + * MV_OK - Success, Others - Failure + * + * NOTE: + *******************************************************************************/ +MV_STATUS mvNetaHwfTxqEnable(int port, int tx_port, int txp, int txq, int enable) +{ + MV_U32 regVal; + + /* Enable HWF for each TXQ */ + regVal = NETA_HWF_TX_PORT_MASK(tx_port + txp) | NETA_HWF_TXQ_MASK(txq); + MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal); + + MV_REG_WRITE(NETA_HWF_TXQ_ENABLE_REG(port), enable << NETA_HWF_TXQ_ENABLE_BIT); + + return MV_OK; +} + +/******************************************************************************* + * mvNetaHwfTxqEnable - Enable / Disable HWF of the port + * DESCRIPTION: + * + * INPUT: + * int rx_port: RX port number + * int tx_port, txp, txq: port, TCONT and TXQ numbers + * int enable: 0 - disable, 1 - enable + * + * RETURN: MV_STATUS + * MV_OK - Success, Others - Failure + * + * NOTE: + *******************************************************************************/ +MV_STATUS mvNetaHwfTxqDropSet(int port, int tx_port, int txp, int txq, int thresh, int bits) +{ + MV_U32 regVal, dropThresh; + MV_NETA_PORT_CTRL *pPortCtrl; + MV_NETA_QUEUE_CTRL *pQueueCtrl; + + pPortCtrl = mvNetaPortHndlGet(tx_port); + if (pPortCtrl == NULL) + return MV_FAIL; + + pQueueCtrl = &pPortCtrl->pTxQueue[txp * CONFIG_MV_ETH_TXQ + txq].queueCtrl; + if (pQueueCtrl->pFirst == NULL) + return MV_FAIL; + + /* Set HWF Drop parameters for specific TXQ */ + regVal = NETA_HWF_TX_PORT_MASK(tx_port + txp) | NETA_HWF_TXQ_MASK(txq); + MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal); + + dropThresh = (thresh * (pQueueCtrl->lastDesc + 1)) / 100; + regVal = (dropThresh << NETA_YELLOW_DROP_THRESH_OFFS) | (bits << NETA_YELLOW_DROP_RND_GEN_OFFS); + + MV_REG_WRITE(NETA_HWF_DROP_TH_REG(port), regVal); + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaAddrDec.c u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaAddrDec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaAddrDec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaAddrDec.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,424 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvSysEthConfig.h" + +#include "mvNeta.h" + +MV_TARGET ethAddrDecPrioTab[] = { +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(CONFIG_MV_ETH_BM) + PNC_BM, +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(MV_U32 port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvNetaWinInit +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the default +* address decode windows of the unit. +* +* INPUT: +* port : The port number to initialize the address decoding for. +* addWinMap: An array holding the address decoding information for the +* system. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +MV_STATUS mvNetaWinInit(MV_U32 port, MV_UNIT_WIN_INFO *addrWinMap) +{ + MV_U32 winNum, winPrioIndex = 0, i, regVal = 0; + MV_UNIT_WIN_INFO *addrDecWin; + MV_U32 accessProtReg = 0; + + /* Initiate Ethernet address decode */ + /* First disable all address decode windows */ + for (winNum = 0; winNum < ETH_MAX_DECODE_WIN; winNum++) + regVal |= MV_BIT_MASK(winNum); + + MV_REG_WRITE(ETH_BASE_ADDR_ENABLE_REG(port), regVal); + + /* Go through all windows in user table until table terminator */ + for (winNum = 0; ((ethAddrDecPrioTab[winPrioIndex] != TBL_TERM) && (winNum < ETH_MAX_DECODE_WIN));) { + addrDecWin = &addrWinMap[ethAddrDecPrioTab[winPrioIndex]]; + + if (addrDecWin->enable == MV_TRUE) { + if (MV_OK != mvNetaWinWrite(port, winNum, addrDecWin)) { + mvOsPrintf("mvNetaWinInit failed: winNum=%d (%d, %d)\n", + winNum, winPrioIndex, ethAddrDecPrioTab[winPrioIndex]); + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + + /* set full access to all windows. */ + for (i = 0; i < winNum; i++) + accessProtReg |= (FULL_ACCESS << (i * 2)); + + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaWinWrite +* +* DESCRIPTION: +* This function writes the address decoding registers according to the +* given window configuration. +* +* INPUT: +* unit - The Ethernet unit number to configure. +* winNum - ETH target address decode window number. +* pAddrDecWin - ETH target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvNetaWinWrite(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin) +{ + MV_U32 size, alignment; + MV_U32 baseReg, sizeReg; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvNetaWinSet: ERR. Invalid win num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvNetaWinWrite: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvNetaWinSet: Error setting Ethernet window %d.\n" + "Address 0x%08x is unaligned to size 0x%x.\n", + winNum, pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + size = pAddrDecWin->addrWin.size; + if (!MV_IS_POWER_OF_2(size)) { + mvOsPrintf("mvNetaWinWrite: Error setting AUDIO window %d. " + "Window size is not a power to 2.", winNum); + return MV_BAD_PARAM; + } + + baseReg = (pAddrDecWin->addrWin.baseLow & ETH_WIN_BASE_MASK); + sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + /* set size */ + alignment = 1 << ETH_WIN_SIZE_OFFS; + sizeReg &= ~ETH_WIN_SIZE_MASK; + sizeReg |= (((size / alignment) - 1) << ETH_WIN_SIZE_OFFS); + + /* set attributes */ + baseReg &= ~ETH_WIN_ATTR_MASK; + baseReg |= pAddrDecWin->attrib << ETH_WIN_ATTR_OFFS; + + /* set target ID */ + baseReg &= ~ETH_WIN_TARGET_MASK; + baseReg |= pAddrDecWin->targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvNetaWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + mvNetaWinEnable(port, winNum, MV_TRUE); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(MV_U32 port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_UNIT_WIN_INFO addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex = 0; winNumIndex < ETH_MAX_DECODE_WIN; winNumIndex++) { + /* Do not check window itself */ + if (winNumIndex == winNum) + continue; + + /* Do not check disabled windows */ + if (baseAddrEnableReg & (1 << winNumIndex)) + continue; + + /* Get window parameters */ + if (MV_OK != mvNetaWinRead(port, winNumIndex, &addrDecWin)) { + mvOsPrintf("ethWinOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvNetaWinRead +* +* DESCRIPTION: +* Read Ethernet peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_BAD_PARAM if winNum is invalid. +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvNetaWinRead(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin) +{ + MV_U32 baseReg, sizeReg; + MV_U32 alignment, size; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvNetaWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + alignment = 1 << ETH_WIN_SIZE_OFFS; + size = (sizeReg & ETH_WIN_SIZE_MASK) >> ETH_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (size + 1) * alignment; + + /* Extract base address */ + pAddrDecWin->addrWin.baseLow = baseReg & ETH_WIN_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + /* attrib and targetId */ + pAddrDecWin->attrib = (baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + pAddrDecWin->targetId = (baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum)) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + return MV_OK; +} + +/******************************************************************************* +* mvNetaWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvNetaWinEnable(MV_U32 port, MV_U32 winNum, MV_BOOL enable) +{ + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvNetaTargetWinEnable:ERR. Invalid winNum%d\n", winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + else + /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaProtWinSet - Set access protection of Ethernet to target window. +* +* DESCRIPTION: +* Each Ethernet port can be configured with access attributes for each +* of the Ethenret to target windows (address decode windows). This +* function sets access attributes to a given window for the given channel. +* +* INPUTS: +* ethPort - ETH channel number. See MV_ETH_CHANNEL enumerator. +* winNum - IETH to target address decode window number. +* access - IETH access rights. See MV_ACCESS_RIGHTS enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case window number is invalid or access right reserved. +* +*******************************************************************************/ +MV_STATUS mvNetaProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS access) +{ + MV_U32 protReg; + + /* Parameter checking */ + if (portNo >= MV_ETH_MAX_PORTS) { + mvOsPrintf("mvNetaProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) { + mvOsPrintf("mvNetaProtWinSet:ERR. Invalid winNum%d\n", winNum); + return MV_ERROR; + } + + if ((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) { + mvOsPrintf("mvNetaProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNeta.c u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNeta.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNeta.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNeta.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,2494 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" /* Should be included before mvSysHwConfig */ +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "mvOs.h" + +#include "mvNeta.h" +#include "pnc/mvPnc.h" +#include "bm/mvBm.h" + +/* This array holds the control structure of each port */ +MV_NETA_PORT_CTRL **mvNetaPortCtrl = NULL; +MV_NETA_HAL_DATA mvNetaHalData; + +/* Function prototypes */ +#ifndef CONFIG_MV_ETH_PNC +static MV_BOOL netaSetUcastAddr(int port, MV_U8 lastNibble, int queue); +static MV_BOOL netaSetSpecialMcastAddr(int port, MV_U8 lastByte, int queue); +static MV_BOOL netaSetOtherMcastAddr(int port, MV_U8 crc8, int queue); +#endif /* CONFIG_MV_ETH_PNC */ + +static MV_U8 *netaDescrMemoryAlloc(MV_NETA_PORT_CTRL * pPortCtrl, int descSize, + MV_ULONG *pPhysAddr, MV_U32 *memHandle); +static void mvNetaDescRingReset(MV_NETA_QUEUE_CTRL *pQueueHndl); + +#define TX_DISABLE_TIMEOUT_MSEC 1000 +#define RX_DISABLE_TIMEOUT_MSEC 1000 +#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 +#define PORT_DISABLE_WAIT_TCLOCKS 5000 + +int mvNetaPortCheck(int port) +{ + if ((port < 0) || (port >= mvNetaHalData.maxPort)) { + mvOsPrintf("port %d is out of range\n", port); + return 1; + } + + return 0; +} + +int mvNetaTxpCheck(int port, int txp) +{ + int txpNum; + + if (mvNetaPortCheck(port)) + return 1; + + txpNum = 1; + +#ifdef CONFIG_MV_PON + if (MV_PON_PORT(port)) + txpNum = MV_ETH_MAX_TCONT(); +#endif /* CONFIG_MV_PON */ + + if ((txp < 0) || (txp >= txpNum)) { + mvOsPrintf("txp %d is out of range\n", txp); + return 1; + } + return 0; +} + +int mvNetaMaxCheck(int num, int limit) +{ + if ((num < 0) || (num >= limit)) { + mvOsPrintf("%d is out of range %d\n", num, limit); + return 1; + } + + return 0; +} + +/******************************************************************************/ +/* Port Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvNetaPortInit - Initialize the NETA port +* +* DESCRIPTION: +* This function initializes the NETA port. +* 1) Allocates and initializes internal port control structure. +* 2) Creates RX and TX descriptor rings. +* 3) Disables RX and TX operations, clears cause registers and +* masks all interrupts. +* 4) Sets all registers to default values and cleans all MAC tables. +* +* INPUT: +* int portNo - NETA port number +* +* RETURN: +* void* - NETA port handler that should be passed to most other +* functions dealing with this port. +* +* NOTE: This function is called once per port when loading the NETA module. +*******************************************************************************/ +void *mvNetaPortInit(int portNo, void *osHandle) +{ + MV_NETA_PORT_CTRL *pPortCtrl; + + /* Check validity of parameters */ + if ((portNo < 0) || (portNo >= mvNetaHalData.maxPort)) { + mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); + return NULL; + } + + pPortCtrl = (MV_NETA_PORT_CTRL *) mvOsMalloc(sizeof(MV_NETA_PORT_CTRL)); + if (pPortCtrl == NULL) { + mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", + (int)sizeof(MV_NETA_PORT_CTRL), portNo); + return NULL; + } + + memset(pPortCtrl, 0, sizeof(MV_NETA_PORT_CTRL)); + mvNetaPortCtrl[portNo] = pPortCtrl; + + pPortCtrl->portNo = portNo; + pPortCtrl->osHandle = osHandle; + + pPortCtrl->txpNum = 1; + +#ifdef CONFIG_MV_PON + if (MV_PON_PORT(portNo)) + pPortCtrl->txpNum = MV_ETH_MAX_TCONT(); +#endif /* CONFIG_MV_PON */ + + pPortCtrl->rxqNum = CONFIG_MV_ETH_RXQ; + pPortCtrl->txqNum = CONFIG_MV_ETH_TXQ; + + /* Allocate RXQ and TXQ structures */ + pPortCtrl->pRxQueue = mvOsMalloc(pPortCtrl->rxqNum * sizeof(MV_NETA_RXQ_CTRL)); + if (pPortCtrl->pRxQueue == NULL) { + mvOsPrintf("mvNeta port%d: Can't allocate %d Bytes for %d RXQs controls\n", + portNo, (int)pPortCtrl->rxqNum * sizeof(MV_NETA_RXQ_CTRL), pPortCtrl->rxqNum); + return NULL; + } + + pPortCtrl->pTxQueue = mvOsMalloc(pPortCtrl->txpNum * pPortCtrl->txqNum * sizeof(MV_NETA_TXQ_CTRL)); + if (pPortCtrl->pTxQueue == NULL) { + mvOsPrintf("mvNeta port%d: Can't allocate %d Bytes for %d TXQs controls\n", + portNo, (int)pPortCtrl->txqNum * pPortCtrl->txpNum * sizeof(MV_NETA_TXQ_CTRL), + pPortCtrl->txqNum * pPortCtrl->txpNum); + return NULL; + } + + /* Disable port */ + mvNetaPortDisable(portNo); + mvNetaDefaultsSet(portNo); + + return pPortCtrl; +} + +/******************************************************************************* +* mvNetaAccMode - Get NETA Acceleration mode +* +* DESCRIPTION: +* +* INPUT: +* +* RETURN: +* int - NETA Acceleration mode +* +* NOTE: This function is called once on loading the NETA module. +*******************************************************************************/ +int mvNetaAccMode(void) +{ + int mode; + +#if defined(CONFIG_MV_ETH_BM) && defined(CONFIG_MV_ETH_PNC) + mode = NETA_ACC_MODE_MASK(NETA_ACC_MODE_EXT_PNC_BMU); +#elif defined(CONFIG_MV_ETH_BM) + mode = NETA_ACC_MODE_MASK(NETA_ACC_MODE_EXT_BMU); +#elif defined(CONFIG_MV_ETH_PNC) + mode = NETA_ACC_MODE_MASK(NETA_ACC_MODE_EXT_PNC); +#else + mode = NETA_ACC_MODE_MASK(NETA_ACC_MODE_EXT); +#endif + + return mode; +} + +/******************************************************************************* +* mvNetaDefaultsSet - Set defaults to the NETA port +* +* DESCRIPTION: +* This function sets default values to the NETA port. +* 1) Clears interrupt Cause and Mask registers. +* 2) Clears all MAC tables. +* 3) Sets defaults to all registers. +* 4) Resets RX and TX descriptor rings. +* 5) Resets PHY. +* +* INPUT: +* void* pNetaPortHndl - NETA port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* NOTE: +* This function updates all the port configurations except those set +* initialy by the OsGlue by MV_NETA_PORT_INIT. +* This function can be called after portDown to return the port settings +* to defaults. +*******************************************************************************/ +MV_STATUS mvNetaDefaultsSet(int port) +{ + int i; + int queue, txp; + MV_U32 regVal; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortHndlGet(port); + + /* Clear all Cause registers */ + MV_REG_WRITE(NETA_INTR_NEW_CAUSE_REG(port), 0); + MV_REG_WRITE(NETA_INTR_OLD_CAUSE_REG(port), 0); + MV_REG_WRITE(NETA_INTR_MISC_CAUSE_REG(port), 0); + + /* Mask all interrupts */ + MV_REG_WRITE(NETA_INTR_NEW_MASK_REG(port), 0); + MV_REG_WRITE(NETA_INTR_OLD_MASK_REG(port), 0); + MV_REG_WRITE(NETA_INTR_MISC_MASK_REG(port), 0); + + MV_REG_WRITE(NETA_INTR_ENABLE_REG(port), 0); + + /* Enable MBUS Retry bit16 */ + MV_REG_WRITE(NETA_MBUS_RETRY_REG(port), NETA_MBUS_RETRY_CYCLES(0x20)); + + /* Set CPU queue access map - default CPU_0 can access all RX and TX queues */ + for (i = 0; i < mvNetaHalData.maxCPUs; i++) + MV_REG_WRITE(NETA_CPU_MAP_REG(port, i), (NETA_CPU_RXQ_ACCESS_ALL_MASK | NETA_CPU_TXQ_ACCESS_ALL_MASK)); + + /* Reset RX and TX DMAs */ + MV_REG_WRITE(NETA_PORT_RX_RESET_REG(port), NETA_PORT_RX_DMA_RESET_MASK); + + for (txp = 0; txp < pPortCtrl->txpNum; txp++) { + MV_REG_WRITE(NETA_PORT_TX_RESET_REG(port, txp), NETA_PORT_TX_DMA_RESET_MASK); + +#ifdef CONFIG_MV_PON + if ((txp * MV_ETH_MAX_TXQ % 32) == 0) { + MV_REG_WRITE(GPON_TXQ_INTR_NEW_CAUSE_REG(txp * MV_ETH_MAX_TXQ), 0); + MV_REG_WRITE(GPON_TXQ_INTR_NEW_MASK_REG(txp * MV_ETH_MAX_TXQ), 0); + MV_REG_WRITE(GPON_TXQ_INTR_OLD_CAUSE_REG(txp * MV_ETH_MAX_TXQ), 0); + MV_REG_WRITE(GPON_TXQ_INTR_OLD_MASK_REG(txp * MV_ETH_MAX_TXQ), 0); + MV_REG_WRITE(GPON_TXQ_INTR_ERR_CAUSE_REG(txp * MV_ETH_MAX_TXQ), 0); + MV_REG_WRITE(GPON_TXQ_INTR_ERR_MASK_REG(txp * MV_ETH_MAX_TXQ), 0); + + MV_REG_WRITE(GPON_TXQ_INTR_ENABLE_REG(txp * MV_ETH_MAX_TXQ), 0xFFFFFFFF); + } +#endif /* CONFIG_MV_PON */ + + /* Disable Legacy WRR, Disable EJP, Release from reset */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port, txp), 0); + for (queue = 0; queue < MV_ETH_MAX_TXQ; queue++) { + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(port, txp, queue), 0); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(port, txp, queue), 0); + } + MV_REG_WRITE(NETA_PORT_TX_RESET_REG(port, txp), 0); + } + + MV_REG_WRITE(NETA_PORT_RX_RESET_REG(port), 0); + + MV_REG_WRITE(NETA_RX_INTR_TIME_COAL_REG(port), 0); + + /* Set Port Acceleration Mode */ + regVal = mvNetaAccMode(); + MV_REG_WRITE(NETA_ACC_MODE_REG(port), regVal); + +#ifdef CONFIG_MV_ETH_BM + /* Set address of Buffer Management Unit */ + MV_REG_WRITE(NETA_BM_ADDR_REG(port), mvNetaHalData.bmPhysBase); +#endif /* CONFIG_MV_ETH_BM */ + + /* Update value of portCfg register accordingly with all RxQueue types */ + regVal = PORT_CONFIG_VALUE(CONFIG_MV_ETH_RXQ_DEF); + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), regVal); + + regVal = PORT_CONFIG_EXTEND_VALUE; + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(port), regVal); + + if (MV_PON_PORT(port)) { + MV_REG_WRITE(ETH_RX_MINIMAL_FRAME_SIZE_REG(port), 40); + } else { + MV_REG_WRITE(ETH_RX_MINIMAL_FRAME_SIZE_REG(port), 64); + + regVal = PORT_SERIAL_CONTROL_VALUE; + + regVal &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + regVal |= ETH_MAX_RX_PACKET_1522BYTE; + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), regVal); + + /* Allow receiving packes with odd number of preamble nibbles */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal |= ETH_EN_MII_ODD_PRE_MASK; + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + } + + /* build PORT_SDMA_CONFIG_REG */ + regVal = 0; + regVal |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); + +#ifdef CONFIG_HW_CACHE_COHERENCY + /* some devices have restricted RX burst size when using HW coherency */ + regVal |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); +#else + regVal |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); +#endif /* CONFIG_HW_CACHE_COHERENCY */ + + regVal |= (ETH_RX_NO_DATA_SWAP_MASK | ETH_TX_NO_DATA_SWAP_MASK | ETH_NO_DESC_SWAP_MASK); + + /* Assign port SDMA configuration */ + MV_REG_WRITE(ETH_SDMA_CONFIG_REG(port), regVal); + + mvNetaSetUcastTable(port, -1); + mvNetaSetSpecialMcastTable(port, -1); + mvNetaSetOtherMcastTable(port, -1); + + + /* Set port interrupt enable register - default enable all */ + MV_REG_WRITE(NETA_INTR_ENABLE_REG(port), + (NETA_RXQ_PKT_INTR_ENABLE_ALL_MASK | NETA_TXQ_PKT_INTR_ENABLE_ALL_MASK)); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaHalInit - Initialize the HAL and the NETA unit +* +* DESCRIPTION: +* This function: +* 1) Initializes HAL global data structures. +* 2) Clears and disables NETA unit interrupts. +* +* INPUT: NONE +* +* RETURN: NONE +* +* NOTE: this function is called once in the boot process. +*******************************************************************************/ +MV_STATUS mvNetaHalInit(MV_NETA_HAL_DATA *halData) +{ + int port; + + mvNetaHalData = *halData; + + /* Allocate port data structures */ + mvNetaPortCtrl = mvOsMalloc(mvNetaHalData.maxPort * sizeof(MV_NETA_PORT_CTRL *)); + if (mvNetaPortCtrl == NULL) { + mvOsPrintf("%s: Can't allocate %d bytes for %d ports\n", __func__, + mvNetaHalData.maxPort * sizeof(MV_NETA_PORT_CTRL), mvNetaHalData.maxPort); + return MV_FAIL; + } + for (port = 0; port < mvNetaHalData.maxPort; port++) + mvNetaPortCtrl[port] = NULL; + +#ifdef CONFIG_MV_ETH_BM + mvBmInit(mvNetaHalData.bmVirtBase); +#endif /* CONFIG_MV_ETH_BM */ + +#ifdef CONFIG_MV_ETH_PNC + mvPncInit(mvNetaHalData.pncVirtBase); +#endif /* CONFIG_MV_ETH_PNC */ + + return MV_OK; +} + +/* Functions below are different for old and new version of GMAC */ +#ifdef MV_ETH_GMAC_NEW +MV_STATUS mvEthGmacRgmiiSet(int port, int enable) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_GMAC_CTRL_2_REG(port)); + if(enable) + regVal |= NETA_GMAC_PORT_RGMII_MASK; + else + regVal &= ~NETA_GMAC_PORT_RGMII_MASK; + + MV_REG_WRITE(NETA_GMAC_CTRL_2_REG(port), regVal); + + return MV_OK; +} + +void mvNetaPortPowerUp(int port) +{ + MV_U32 regVal; + + /* MAC Cause register should be cleared */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + +/* + if (mvBoardIsPortInSgmii(port)) + mvEthPortSgmiiConfig(port); +*/ + /* Cancel Port Reset */ + regVal = MV_REG_READ(NETA_GMAC_CTRL_2_REG(port)); + regVal &= (~NETA_GMAC_PORT_RESET_MASK); + MV_REG_WRITE(NETA_GMAC_CTRL_2_REG(port), regVal); + while( (MV_REG_READ(NETA_GMAC_CTRL_2_REG(port)) & NETA_GMAC_PORT_RESET_MASK) != 0) + continue; +} + +void mvNetaPortPowerDown(int port) +{ +} + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvNetaMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* imidiately. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaMaxRxSizeSet(int portNo, int maxRxSize) +{ + MV_U32 regVal; + + if (!MV_PON_PORT(portNo)) { + + regVal = MV_REG_READ(NETA_GMAC_CTRL_0_REG(portNo)); + regVal &= ~NETA_GMAC_MAX_RX_SIZE_MASK; + regVal |= ((maxRxSize / 2) << NETA_GMAC_MAX_RX_SIZE_OFFS); + MV_REG_WRITE(NETA_GMAC_CTRL_0_REG(portNo), regVal); +/* + mvOsPrintf("%s: port=%d, maxRxSize=%d, regAddr=0x%x, regVal=0x%x\n", + __FUNCTION__, portNo, maxRxSize, NETA_GMAC_CTRL_0_REG(portNo), regVal); +*/ + } + return MV_OK; +} + +/******************************************************************************* +* mvNetaForceLinkModeSet - +* +* DESCRIPTION: +* Sets "Force Link Pass" and "Do Not Force Link Fail" bits. +* Note: This function should only be called when the port is disabled. +* +* INPUT: +* int portNo - port number +* MV_BOOL force_link_pass - Force Link Pass +* MV_BOOL force_link_fail - Force Link Failure +* 0, 0 - normal state: detect link via PHY and connector +* 1, 1 - prohibited state. +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaForceLinkModeSet(int portNo, MV_BOOL force_link_up, MV_BOOL force_link_down) +{ + MV_U32 regVal; + + if ((portNo < 0) || (portNo >= mvNetaHalData.maxPort)) + return MV_BAD_PARAM; + + /* Can't force link pass and link fail at the same time */ + if ((force_link_up) && (force_link_down)) + return MV_BAD_PARAM; + + regVal = MV_REG_READ(NETA_GMAC_AN_CTRL_REG(portNo)); + if(force_link_up) + regVal |= NETA_FORCE_LINK_PASS_MASK; + else if(force_link_down) + regVal |= NETA_FORCE_LINK_FAIL_MASK; + + MV_REG_WRITE(NETA_GMAC_AN_CTRL_REG(portNo), regVal); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaSpeedDuplexSet - +* +* DESCRIPTION: +* Sets port speed to Auto Negotiation / 1000 / 100 / 10 Mbps. +* Sets port duplex to Auto Negotiation / Full / Half Duplex. +* +* INPUT: +* int portNo - port number +* MV_ETH_PORT_SPEED speed - port speed +* MV_ETH_PORT_DUPLEX duplex - port duplex mode +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaSpeedDuplexSet(int portNo, MV_ETH_PORT_SPEED speed, MV_ETH_PORT_DUPLEX duplex) +{ + MV_U32 regVal; + + if ((portNo < 0) || (portNo >= mvNetaHalData.maxPort)) + return MV_BAD_PARAM; + + /* Check validity */ + if ((speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF)) + return MV_BAD_PARAM; + + regVal = MV_REG_READ(NETA_GMAC_AN_CTRL_REG(portNo)); + + switch (speed) { + case MV_ETH_SPEED_AN: + regVal |= NETA_ENABLE_SPEED_AUTO_NEG_MASK; + /* the other bits don't matter in this case */ + break; + case MV_ETH_SPEED_1000: + regVal &= ~NETA_ENABLE_SPEED_AUTO_NEG_MASK; + regVal |= NETA_SET_GMII_SPEED_1000_MASK; + regVal &= ~NETA_SET_MII_SPEED_100_MASK; + /* the 100/10 bit doesn't matter in this case */ + break; + case MV_ETH_SPEED_100: + regVal &= ~NETA_ENABLE_SPEED_AUTO_NEG_MASK; + regVal &= ~NETA_SET_GMII_SPEED_1000_MASK; + regVal |= NETA_SET_MII_SPEED_100_MASK; + break; + case MV_ETH_SPEED_10: + regVal &= ~NETA_ENABLE_SPEED_AUTO_NEG_MASK; + regVal &= ~NETA_SET_GMII_SPEED_1000_MASK; + regVal &= ~NETA_SET_MII_SPEED_100_MASK; + break; + default: + mvOsPrintf("Unexpected Speed value %d\n", speed); + return MV_BAD_PARAM; + } + + switch (duplex) { + case MV_ETH_DUPLEX_AN: + regVal |= NETA_ENABLE_DUPLEX_AUTO_NEG_MASK; + /* the other bits don't matter in this case */ + break; + case MV_ETH_DUPLEX_HALF: + regVal &= ~NETA_ENABLE_DUPLEX_AUTO_NEG_MASK; + regVal &= ~NETA_SET_FULL_DUPLEX_MASK; + break; + case MV_ETH_DUPLEX_FULL: + regVal &= ~NETA_ENABLE_DUPLEX_AUTO_NEG_MASK; + regVal |= NETA_SET_FULL_DUPLEX_MASK; + break; + default: + mvOsPrintf("Unexpected Duplex value %d\n", duplex); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(NETA_GMAC_AN_CTRL_REG(portNo), regVal); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configures the port's Flow Control properties. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvNetaFlowCtrlSet(int port, MV_ETH_PORT_FC flowControl) +{ + MV_U32 regVal; + + if ((port < 0) || (port >= mvNetaHalData.maxPort)) + return MV_OUT_OF_RANGE; + + regVal = MV_REG_READ(NETA_GMAC_AN_CTRL_REG(port)); + + switch (flowControl) { + case MV_ETH_FC_AN_NO: + regVal |= NETA_ENABLE_FLOW_CONTROL_AUTO_NEG_MASK; + regVal &= ~NETA_FLOW_CONTROL_ADVERTISE_MASK; + regVal &= ~NETA_FLOW_CONTROL_ASYMETRIC_MASK; + break; + + case MV_ETH_FC_AN_SYM: + regVal |= NETA_ENABLE_FLOW_CONTROL_AUTO_NEG_MASK; + regVal |= NETA_FLOW_CONTROL_ADVERTISE_MASK; + regVal &= ~NETA_FLOW_CONTROL_ASYMETRIC_MASK; + break; + + case MV_ETH_FC_AN_ASYM: + regVal |= NETA_ENABLE_FLOW_CONTROL_AUTO_NEG_MASK; + regVal |= NETA_FLOW_CONTROL_ADVERTISE_MASK; + regVal |= NETA_FLOW_CONTROL_ASYMETRIC_MASK; + break; + + case MV_ETH_FC_DISABLE: + regVal &= ~NETA_ENABLE_FLOW_CONTROL_AUTO_NEG_MASK; + regVal &= ~NETA_SET_FLOW_CONTROL_MASK; + break; + + case MV_ETH_FC_ENABLE: + regVal &= ~NETA_ENABLE_FLOW_CONTROL_AUTO_NEG_MASK; + regVal |= NETA_SET_FLOW_CONTROL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + + + MV_REG_WRITE(NETA_GMAC_AN_CTRL_REG(port), regVal); + + return MV_OK; +} + +#else + +void mvNetaPortPowerUp(int port) +{ + MV_U32 regVal; + + /* MAC Cause register should be cleared */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + +/* + if (mvBoardIsPortInSgmii(port)) + mvEthPortSgmiiConfig(port); +*/ + /* Cancel Port Reset */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal &= (~ETH_PORT_RESET_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + while ((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0) + continue; +} + +void mvNetaPortPowerDown(int port) +{ +} + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ + +/******************************************************************************* +* netaMruGet - Get MRU configuration for Max Rx packet size. +* +* INPUT: +* MV_U32 maxRxPktSize - max packet size. +* +* RETURN: MV_U32 - MRU configuration. +* +*******************************************************************************/ +static MV_U32 netaMruGet(MV_U32 maxRxPktSize) +{ + MV_U32 portSerialCtrlReg = 0; + + if (maxRxPktSize > 9192) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; + else if (maxRxPktSize > 9022) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; + else if (maxRxPktSize > 1552) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; + else if (maxRxPktSize > 1522) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; + else if (maxRxPktSize > 1518) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; + else + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; + + return portSerialCtrlReg; +} + +/******************************************************************************* +* mvNetaMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* imidiately. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaMaxRxSizeSet(int portNo, int maxRxSize) +{ + MV_U32 portSerialCtrlReg; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(portNo)); + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + portSerialCtrlReg |= netaMruGet(maxRxSize); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(portNo), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaForceLinkModeSet - +* +* DESCRIPTION: +* Sets "Force Link Pass" and "Do Not Force Link Fail" bits. +* Note: This function should only be called when the port is disabled. +* +* INPUT: +* int portNo - port number +* MV_BOOL force_link_pass - value for Force Link Pass bit (bit 1): 0 or 1 +* MV_BOOL do_not_force_link_fail - value for Do Not Force Link Fail bit (bit 10): 0 or 1 +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaForceLinkModeSet(int portNo, MV_BOOL force_link_up, MV_BOOL force_link_down) +{ + MV_U32 portSerialCtrlReg; + + if ((portNo < 0) || (portNo >= mvNetaHalData.maxPort)) + return MV_BAD_PARAM; + + /* Can't force link pass and link fail at the same time */ + if ((force_link_up) && (force_link_down)) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(portNo)); + + if(force_link_up) + portSerialCtrlReg |= ETH_FORCE_LINK_PASS_MASK | ETH_DO_NOT_FORCE_LINK_FAIL_MASK; + else if(force_link_down) + portSerialCtrlReg &= ~(ETH_FORCE_LINK_PASS_MASK | ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(portNo), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaSpeedDuplexSet - +* +* DESCRIPTION: +* Sets port speed to Auto Negotiation / 1000 / 100 / 10 Mbps. +* Sets port duplex to Auto Negotiation / Full / Half Duplex. +* +* INPUT: +* int portNo - port number +* MV_ETH_PORT_SPEED speed - port speed +* MV_ETH_PORT_DUPLEX duplex - port duplex mode +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvNetaSpeedDuplexSet(int portNo, MV_ETH_PORT_SPEED speed, MV_ETH_PORT_DUPLEX duplex) +{ + MV_U32 portSerialCtrlReg; + + if ((portNo < 0) || (portNo >= mvNetaHalData.maxPort)) + return MV_BAD_PARAM; + + /* Check validity */ + if ((speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF)) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(portNo)); + + switch (speed) { + case MV_ETH_SPEED_AN: + portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; + /* the other bits don't matter in this case */ + break; + case MV_ETH_SPEED_1000: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; + /* the 100/10 bit doesn't matter in this case */ + break; + case MV_ETH_SPEED_100: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; + break; + case MV_ETH_SPEED_10: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; + break; + default: + mvOsPrintf("Unexpected Speed value %d\n", speed); + return MV_BAD_PARAM; + } + + switch (duplex) { + case MV_ETH_DUPLEX_AN: + portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + /* the other bits don't matter in this case */ + break; + case MV_ETH_DUPLEX_HALF: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; + break; + case MV_ETH_DUPLEX_FULL: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; + break; + default: + mvOsPrintf("Unexpected Duplex value %d\n", duplex); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(portNo), portSerialCtrlReg); + + return MV_OK; + +} +#endif /* MV_ETH_GMAC_NEW */ + +/******************************************************************************/ +/* MAC Filtering functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvNetaRxFilterModeSet - Configure Fitering mode of Ethernet port +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* MV_BOOL isPromisc - Promiscous mode +* MV_TRUE - accept all Broadcast, Multicast +* and Unicast packets +* MV_FALSE - accept all Broadcast, +* specially added Multicast and +* single Unicast packets +* +* RETURN: MV_STATUS MV_OK - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvNetaRxUnicastPromiscSet(int port, MV_BOOL isPromisc) +{ + MV_U32 portCfgReg; + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(port)); + /* Set / Clear UPM bit in port configuration register */ + if (isPromisc == MV_TRUE) { + /* Accept all Unicast addresses */ + portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(port), 0xFFFF); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(port), 0xFFFFFFFF); + } else { + /* Reject all Unicast addresses */ + portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; + } + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), portCfgReg); + + return MV_OK; +} + +#ifndef CONFIG_MV_ETH_PNC +/******************************************************************************* +* mvNetaMacAddrSet - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. This address +* will be used to send Pause frames if enabled. Packets with this +* address will be accepted and dispatched to default RX queue +* +* INPUT: +* int* port - Ethernet port. +* char* pAddr - Address to be set +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvNetaMacAddrSet(int portNo, unsigned char *pAddr, int queue) +{ + unsigned int macH; + unsigned int macL; + + if (queue >= CONFIG_MV_ETH_RXQ) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); + return MV_BAD_PARAM; + } + + if (queue != -1) { + macL = (pAddr[4] << 8) | (pAddr[5]); + macH = (pAddr[0] << 24) | (pAddr[1] << 16) | (pAddr[2] << 8) | (pAddr[3] << 0); + + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(portNo), macL); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(portNo), macH); + } + + /* Accept frames of this address */ + netaSetUcastAddr(portNo, pAddr[5], queue); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaMacAddrGet - This function returns the port Unicast address. +* +* DESCRIPTION: +* This function returns the port Ethernet MAC address. +* +* INPUT: +* int portNo - Ethernet port number. +* char* pAddr - Pointer where address will be written to +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvNetaMacAddrGet(int portNo, unsigned char *pAddr) +{ + unsigned int macH; + unsigned int macL; + + if (pAddr == NULL) { + mvOsPrintf("mvNetaMacAddrGet: NULL pointer.\n"); + return MV_BAD_PARAM; + } + + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); + pAddr[0] = (macH >> 24) & 0xff; + pAddr[1] = (macH >> 16) & 0xff; + pAddr[2] = (macH >> 8) & 0xff; + pAddr[3] = macH & 0xff; + pAddr[4] = (macL >> 8) & 0xff; + pAddr[5] = macL & 0xff; + + return MV_OK; +} + +/******************************************************************************* +* mvNetaMcastCrc8Get - Calculate CRC8 of MAC address. +* +* DESCRIPTION: +* +* INPUT: +* MV_U8* pAddr - Address to calculate CRC-8 +* +* RETURN: MV_U8 - CRC-8 of this MAC address +* +*******************************************************************************/ +MV_U8 mvNetaMcastCrc8Get(MV_U8 *pAddr) +{ + unsigned int macH; + unsigned int macL; + int macArray[48]; + int crc[8]; + int i; + unsigned char crcResult = 0; + + /* Calculate CRC-8 out of the given address */ + macH = (pAddr[0] << 8) | (pAddr[1]); + macL = (pAddr[2] << 24) | (pAddr[3] << 16) | (pAddr[4] << 8) | (pAddr[5] << 0); + + for (i = 0; i < 32; i++) + macArray[i] = (macL >> i) & 0x1; + + for (i = 32; i < 48; i++) + macArray[i] = (macH >> (i - 32)) & 0x1; + + crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ + macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ + macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ + macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ + macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; + + crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ + macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ + macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ + macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ + macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ + macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; + + crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ + macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ + macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ + macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ + macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ + macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; + + crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ + macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ + macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ macArray[3] ^ macArray[2] ^ macArray[1]; + + crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ + macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ + macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ + macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ macArray[3] ^ macArray[2]; + + crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ + macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ + macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ + macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ macArray[4] ^ macArray[3]; + + crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ + macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ + macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ + macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ macArray[4]; + + crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ + macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ + macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ + macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ + macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; + + for (i = 0; i < 8; i++) + crcResult = crcResult | (crc[i] << i); + + return crcResult; +} + +/******************************************************************************* +* mvNetaMcastAddrSet - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls netaPortSmcAddr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* netaPortOmcAddr() routine to set the Other Multicast Table. +* +* INPUT: +* void* port - Ethernet port. +* MV_U8* pAddr - Address to be set +* int queue - RX queue to capture all packets with this +* Multicast MAC address. +* -1 means delete this Multicast address. +* +* RETURN: MV_STATUS +* MV_TRUE - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvNetaMcastAddrSet(int port, MV_U8 *pAddr, int queue) +{ + if (queue >= CONFIG_MV_ETH_RXQ) { + mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", port, queue); + return MV_BAD_PARAM; + } + + if ((pAddr[0] == 0x01) && (pAddr[1] == 0x00) && (pAddr[2] == 0x5E) && (pAddr[3] == 0x00) && (pAddr[4] == 0x00)) { + netaSetSpecialMcastAddr(port, pAddr[5], queue); + } else { + unsigned char crcResult = 0; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortHndlGet(port); + + crcResult = mvNetaMcastCrc8Get(pAddr); + + /* Check Add counter for this CRC value */ + if (queue == -1) { + if (pPortCtrl->mcastCount[crcResult] == 0) { + mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", port, (unsigned)crcResult); + return MV_NO_SUCH; + } + + pPortCtrl->mcastCount[crcResult]--; + if (pPortCtrl->mcastCount[crcResult] != 0) { + mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], (unsigned)crcResult); + return MV_NO_CHANGE; + } + } else { + pPortCtrl->mcastCount[crcResult]++; + if (pPortCtrl->mcastCount[crcResult] > 1) { + mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", + port, (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + netaSetOtherMcastAddr(port, crcResult, queue); + } + return MV_OK; +} +#endif /* CONFIG_MV_ETH_PNC */ + +/******************************************************************************* +* mvNetaSetUcastTable - Unicast address settings. +* +* DESCRIPTION: +* Set all entries in the Unicast MAC Table queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +void mvNetaSetUcastTable(int port, int queue) +{ + int offset; + MV_U32 regValue; + + if (queue == -1) { + regValue = 0; + } else { + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(port) + offset), regValue); +} + +/******************************************************************************* +* mvNetaSetSpecialMcastTable - Special Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvNetaSetSpecialMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if (queue == -1) { + regValue = 0; + } else { + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xFC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* mvNetaSetOtherMcastTable - Other Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvNetaSetOtherMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortHndlGet(portNo); + + if (queue == -1) { + memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); + regValue = 0; + } else { + memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); + regValue = (((0x01 | (queue << 1)) << 0) | + ((0x01 | (queue << 1)) << 8) | + ((0x01 | (queue << 1)) << 16) | ((0x01 | (queue << 1)) << 24)); + } + + for (offset = 0; offset <= 0xFC; offset += 4) + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + offset), regValue); +} + +#ifndef CONFIG_MV_ETH_PNC +/******************************************************************************* +* netaSetUcastAddr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* int portNo - Port number. +* MV_U8 lastNibble - Unicast MAC Address last nibble. +* int queue - Rx queue number for this MAC address. +* value "-1" means remove address. +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL netaSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) +{ + unsigned int unicastReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the Unicast table entry */ + lastNibble = (0xf & lastNibble); + tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base */ + regOffset = lastNibble % 4; /* Entry offset within the above register */ + + unicastReg = MV_REG_READ((ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified unicast DA table entry */ + unicastReg &= ~(0xFF << (8 * regOffset)); + } else { + unicastReg &= ~(0xFF << (8 * regOffset)); + unicastReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), unicastReg); + + return MV_TRUE; +} + +/******************************************************************************* +* netaSetSpecialMcastAddr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* int port Port number. +* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). +* int queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL netaSetSpecialMcastAddr(int port, MV_U8 lastByte, int queue) +{ + unsigned int smcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the SMC table entry */ + tblOffset = (lastByte / 4); /* Register offset from SMC table base */ + regOffset = lastByte % 4; /* Entry offset within the above register */ + + smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblOffset * 4)); + + if (queue == -1) { + /* Clear accepts frame bit at specified Special DA table entry */ + smcTableReg &= ~(0xFF << (8 * regOffset)); + } else { + smcTableReg &= ~(0xFF << (8 * regOffset)); + smcTableReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblOffset * 4), smcTableReg); + + return MV_TRUE; +} + +/******************************************************************************* +* netaSetOtherMcastAddr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* int port Port number. +* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* int queue Rx queue number for this MAC address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL netaSetOtherMcastAddr(int port, MV_U8 crc8, int queue) +{ + unsigned int omcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the OMC table entry */ + tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + regOffset = crc8 % 4; /* Entry offset within the above register */ + + omcTableReg = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblOffset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified Other DA table entry */ + omcTableReg &= ~(0xFF << (8 * regOffset)); + } else { + omcTableReg &= ~(0xFF << (8 * regOffset)); + omcTableReg |= ((0x01 | (queue << 1)) << (8 * regOffset)); + } + + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblOffset), omcTableReg); + + return MV_TRUE; +} +#endif /* CONFIG_MV_ETH_PNC */ + +/******************************************************************************/ +/* PHY Control Functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvNetaPhyAddrSet - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int phyAddr - PHY address +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvNetaPhyAddrSet(int port, int phyAddr) +{ + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + regData &= ~ETH_PHY_ADDR_MASK; + regData |= phyAddr; + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); + + /* Enable PHY polling */ + regData = MV_REG_READ(ETH_UNIT_CONTROL_REG(port)); + regData |= ETH_PHY_POLLING_ENABLE_MASK; + MV_REG_WRITE(ETH_UNIT_CONTROL_REG(port), regData); + + return; +} + +/******************************************************************************* +* mvNetaPhyAddrGet - Get the ethernet port PHY address. +* +* DESCRIPTION: +* This routine returns the given ethernet port PHY address. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* +* RETURN: int - PHY address. +* +*******************************************************************************/ +int mvNetaPhyAddrGet(int port) +{ + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + return ((regData >> (5 * port)) & 0x1f); +} + +/******************************************************************************/ +/* Descriptor handling Functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvNetaDescRingReset - +* +* DESCRIPTION: +* +* INPUT: +* MV_NETA_PORT_CTRL *pPortCtrl NETA Port Control srtucture. +* int queue Number of Rx queue. +* +* OUTPUT: +* +* RETURN: None +* +*******************************************************************************/ +static void mvNetaDescRingReset(MV_NETA_QUEUE_CTRL *pQueueCtrl) +{ + int descrNum = (pQueueCtrl->lastDesc + 1); + char *pDesc = pQueueCtrl->pFirst; + + if (pDesc == NULL) + return; + + /* reset ring of descriptors */ + memset(pDesc, 0, (descrNum * NETA_DESC_ALIGNED_SIZE)); + mvOsCacheFlush(NULL, pDesc, (descrNum * NETA_DESC_ALIGNED_SIZE)); + pQueueCtrl->nextToProc = 0; +} + +/* Reset all RXQs */ +void mvNetaRxReset(int port) +{ + int rxq; + MV_NETA_RXQ_CTRL *pRxqCtrl; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortCtrl[port]; + + MV_REG_WRITE(NETA_PORT_RX_RESET_REG(port), NETA_PORT_RX_DMA_RESET_MASK); + for (rxq = 0; rxq < pPortCtrl->rxqNum ; rxq++) { + pRxqCtrl = mvNetaRxqHndlGet(port, rxq); + mvNetaDescRingReset(&pRxqCtrl->queueCtrl); + } + MV_REG_WRITE(NETA_PORT_RX_RESET_REG(port), 0); +} + +/* Reset all TXQs */ +void mvNetaTxpReset(int port, int txp) +{ + int txq; + MV_NETA_TXQ_CTRL *pTxqCtrl; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortCtrl[port]; + + MV_REG_WRITE(NETA_PORT_TX_RESET_REG(port, txp), NETA_PORT_TX_DMA_RESET_MASK); + for (txq = 0; txq < pPortCtrl->txqNum; txq++) { + pTxqCtrl = mvNetaTxqHndlGet(port, txp, txq); + mvNetaDescRingReset(&pTxqCtrl->queueCtrl); + } + MV_REG_WRITE(NETA_PORT_TX_RESET_REG(port, txp), 0); +} + +/******************************************************************************* +* mvNetaRxqInit - +* +* DESCRIPTION: +* +* INPUT: +* MV_NETA_PORT_CTRL *pPortCtrl NETA Port Control srtucture. +* int queue Number of Rx queue. +* int descrNum Number of descriptors +* +* OUTPUT: +* +* RETURN: None +* +*******************************************************************************/ +MV_NETA_RXQ_CTRL *mvNetaRxqInit(int port, int queue, int descrNum) +{ + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortCtrl[port]; + MV_NETA_RXQ_CTRL *pRxqCtrl = &pPortCtrl->pRxQueue[queue]; + MV_NETA_QUEUE_CTRL *pQueueCtrl = &pRxqCtrl->queueCtrl; + int descSize; + + /* Allocate memory for RX descriptors */ + descSize = ((descrNum * NETA_DESC_ALIGNED_SIZE) + CPU_D_CACHE_LINE_SIZE); + pQueueCtrl->descBuf.bufVirtPtr = + netaDescrMemoryAlloc(pPortCtrl, descSize, &pQueueCtrl->descBuf.bufPhysAddr, &pQueueCtrl->descBuf.memHandle); + + pQueueCtrl->descBuf.bufSize = descSize; + + if (pQueueCtrl->descBuf.bufVirtPtr == NULL) { + mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes for %d RX descr\n", + pPortCtrl->portNo, queue, descSize, descrNum); + return NULL; + } + + /* Make sure descriptor address is cache line size aligned */ + pQueueCtrl->pFirst = (char *)MV_ALIGN_UP((MV_ULONG) pQueueCtrl->descBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + pQueueCtrl->lastDesc = (descrNum - 1); + + mvNetaDescRingReset(pQueueCtrl); + + /* Set Rx descriptors queue starting address */ + MV_REG_WRITE(NETA_RXQ_BASE_ADDR_REG(pPortCtrl->portNo, queue), + netaDescVirtToPhys(pQueueCtrl, pQueueCtrl->pFirst)); + MV_REG_WRITE(NETA_RXQ_SIZE_REG(pPortCtrl->portNo, queue), descrNum); + + /* Set Rx interrupt coalescing - default NO coalescing */ + MV_REG_WRITE(NETA_RXQ_THRESHOLD_REG(pPortCtrl->portNo, queue), 0); + + return pRxqCtrl; +} + +/******************************************************************************* +* mvNetaTxqInit - +* +* DESCRIPTION: +* +* INPUT: +* MV_NETA_PORT_CTRL *pPortCtrl NETA Port Control srtucture. +* int queue Number of Tx queue. +* int descrNum Number of descriptors +* +* OUTPUT: +* +* RETURN: None +* +*******************************************************************************/ +MV_NETA_TXQ_CTRL *mvNetaTxqInit(int port, int txp, int queue, int descrNum) +{ + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortCtrl[port]; + MV_NETA_TXQ_CTRL *pTxqCtrl; + MV_NETA_QUEUE_CTRL *pQueueCtrl; + int descSize; + + pTxqCtrl = mvNetaTxqHndlGet(port, txp, queue); + pQueueCtrl = &pTxqCtrl->queueCtrl; + + /* Allocate memory for TX descriptors */ + descSize = ((descrNum * NETA_DESC_ALIGNED_SIZE) + CPU_D_CACHE_LINE_SIZE); + pQueueCtrl->descBuf.bufVirtPtr = + netaDescrMemoryAlloc(pPortCtrl, descSize, &pQueueCtrl->descBuf.bufPhysAddr, &pQueueCtrl->descBuf.memHandle); + + pQueueCtrl->descBuf.bufSize = descSize; + + if (pQueueCtrl->descBuf.bufVirtPtr == NULL) { + mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes for %d TX descr\n", + pPortCtrl->portNo, queue, descSize, descrNum); + return NULL; + } + + /* Make sure descriptor address is cache line size aligned */ + pQueueCtrl->pFirst = (char *)MV_ALIGN_UP((MV_ULONG) pQueueCtrl->descBuf.bufVirtPtr, CPU_D_CACHE_LINE_SIZE); + + pQueueCtrl->lastDesc = (descrNum - 1); + + mvNetaDescRingReset(pQueueCtrl); + + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(port, txp, queue), 0x03ffffff); + + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(port, txp, queue), 0x3fffffff); + + /* Set Tx descriptors queue starting address */ + MV_REG_WRITE(NETA_TXQ_BASE_ADDR_REG(port, txp, queue), netaDescVirtToPhys(pQueueCtrl, pQueueCtrl->pFirst)); + + MV_REG_WRITE(NETA_TXQ_SIZE_REG(port, txp, queue), NETA_TXQ_DESC_NUM_MASK(descrNum)); + + return pTxqCtrl; +} + +#if 0 +/******************************************************************************* +* netaDescrMemoryFree - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function frees memory allocated for RX and TX descriptors. +* +* INPUT: +* +* RETURN: None +* +*******************************************************************************/ +static void netaDescrMemoryFree(MV_NETA_PORT_CTRL *pPortCtrl, MV_BUF_INFO *pDescBuf) +{ + if ((pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL)) + return; + +#ifdef ETH_DESCR_UNCACHED + mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr, pDescBuf->memHandle); +#else + mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr, pDescBuf->memHandle); +#endif /* ETH_DESCR_UNCACHED */ +} + +static void netaRxDescRingDestroy(MV_NETA_PORT_CTRL *pPortCtrl, int queue) +{ + netaDescrMemoryFree(pPortCtrl, &pPortCtrl->rxQueue[queue].queueCtrl.descBuf); + pPortCtrl->rxQueue[queue].queueCtrl.pFirst = NULL; + /* Set Rx descriptors queue starting address */ + MV_REG_WRITE(NETA_RXQ_BASE_ADDR_REG(pPortCtrl->portNo, queue), 0); + /* Update RX Command register */ +} + +static void netaTxDescRingDestroy(MV_NETA_PORT_CTRL *pPortCtrl, int queue) +{ + netaDescrMemoryFree(pPortCtrl, &pPortCtrl->pTxQueue[queue].queueCtrl.descBuf); + pPortCtrl->pTxQueue[queue].queueCtrl.pFirst = NULL; + /* Set Tx descriptors queue starting address */ + MV_REG_WRITE(NETA_TXQ_BASE_ADDR_REG(pPortCtrl->portNo, queue), 0); +} +#endif + +/******************************************************************************* +* netaDescrMemoryAlloc - Allocate memory for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* +* INPUT: +* +* RETURN: None +* +*******************************************************************************/ +static MV_U8 *netaDescrMemoryAlloc(MV_NETA_PORT_CTRL *pPortCtrl, int descSize, + MV_ULONG *pPhysAddr, MV_U32 *memHandle) +{ + MV_U8 *pVirt; + +#ifdef ETH_DESCR_UNCACHED + pVirt = (MV_U8 *) mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, pPhysAddr, memHandle); +#else + pVirt = (MV_U8 *) mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, pPhysAddr, memHandle); +#endif /* ETH_DESCR_UNCACHED */ + memset(pVirt, 0, descSize); + + return pVirt; +} + +/***************** Configuration functions ************************/ + +MV_STATUS mvNetaMhSet(int port, MV_NETA_MH_MODE mh) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); + /* Clear relevant fields */ + regVal &= ~(ETH_DSA_EN_MASK | ETH_MH_EN_MASK); + switch (mh) { + case MV_NETA_MH_NONE: + break; + + case MV_NETA_MH: + regVal |= ETH_MH_EN_MASK; + break; + + case MV_NETA_DSA: + regVal |= ETH_DSA_MASK; + break; + + case MV_NETA_DSA_EXT: + regVal |= ETH_DSA_EXT_MASK; + + default: + mvOsPrintf("port=%d: Unexpected MH = %d value\n", port, mh); + return MV_BAD_PARAM; + } + MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), regVal); + return MV_OK; +} + +MV_STATUS mvNetaRxqBufSizeSet(int port, int rxq, int bufSize) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_SIZE_REG(port, rxq)); + + regVal &= ~NETA_RXQ_BUF_SIZE_MASK; + regVal |= ((bufSize >> 3) << NETA_RXQ_BUF_SIZE_OFFS); + + MV_REG_WRITE(NETA_RXQ_SIZE_REG(port, rxq), regVal); + + return MV_OK; +} + +MV_STATUS mvNetaRxTimeCoalSet(int port, MV_U32 uSec) +{ + MV_U32 regVal; + + regVal = (mvNetaHalData.tClk / 1000000) * uSec; + + MV_REG_WRITE(NETA_RX_INTR_TIME_COAL_REG(port), regVal); + + return MV_OK; +} + +MV_STATUS mvNetaRxPktsCoalSet(int port, int rxq, MV_U32 pkts) +{ + MV_REG_WRITE(NETA_RXQ_THRESHOLD_REG(port, rxq), + (NETA_RXQ_OCCUPIED_DESC_MASK(pkts) | NETA_RXQ_NON_OCCUPIED_DESC_MASK(0))); + + return MV_OK; +} + +MV_STATUS mvNetaTxDonePktsCoalSet(int port, int txp, int txq, MV_U32 pkts) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_TXQ_SIZE_REG(port, txp, txq)); + + regVal &= ~NETA_TXQ_SENT_DESC_TRESH_ALL_MASK; + regVal |= NETA_TXQ_SENT_DESC_TRESH_MASK(pkts); + + MV_REG_WRITE(NETA_TXQ_SIZE_REG(port, txp, txq), regVal); + + return MV_OK; +} + +MV_U32 mvNetaRxTimeCoalGet(int port) +{ + MV_U32 regVal, uSec; + + regVal = MV_REG_READ(NETA_RX_INTR_TIME_COAL_REG(port)); + + uSec = regVal / (mvNetaHalData.tClk / 1000000); + + return uSec; +} + +MV_U32 mvNetaRxPktsCoalGet(int port, int rxq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_THRESHOLD_REG(port, rxq)); + + return ((regVal & NETA_RXQ_OCCUPIED_DESC_ALL_MASK) >> NETA_RXQ_OCCUPIED_DESC_OFFS); +} + +MV_U32 mvNetaTxDonePktsCoalGet(int port, int txp, int txq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_TXQ_SIZE_REG(port, txp, txq)); + + return ((regVal & NETA_TXQ_SENT_DESC_TRESH_ALL_MASK) >> NETA_TXQ_SENT_DESC_TRESH_OFFS); +} + +/******************************************************************************* +* mvNetaPortUp - Start the Ethernet port RX and TX activity. +* +* DESCRIPTION: +* This routine start Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pPortCtrl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +*******************************************************************************/ +MV_STATUS mvNetaPortUp(int port) +{ + int queue, txp; + MV_U32 qMap; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortHndlGet(port); + MV_NETA_QUEUE_CTRL *pQueueCtrl; + + /* Enable all initialized TXs. */ + for (txp = 0; txp < pPortCtrl->txpNum; txp++) { + mvNetaMibCountersClear(port, txp); + + qMap = 0; + for (queue = 0; queue < CONFIG_MV_ETH_TXQ; queue++) { + pQueueCtrl = &pPortCtrl->pTxQueue[txp * CONFIG_MV_ETH_TXQ + queue].queueCtrl; + + if (pQueueCtrl->pFirst != NULL) + qMap |= (1 << queue); + } + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo, txp), qMap); + } + /* Enable all initialized RXQs. */ + qMap = 0; + for (queue = 0; queue < CONFIG_MV_ETH_RXQ; queue++) { + pQueueCtrl = &pPortCtrl->pRxQueue[queue].queueCtrl; + + if (pQueueCtrl->pFirst != NULL) + qMap |= (1 << queue); + } + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(pPortCtrl->portNo), qMap); + +/* + mvOsPrintf("Start TX port activity: regData=0x%x (0x%x)\n", + pPortCtrl->txqMap, MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo))); +*/ + return MV_OK; +} + +/******************************************************************************* +* mvNetaPortDown - Stop the Ethernet port activity. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link down. +*******************************************************************************/ +MV_STATUS mvNetaPortDown(int port) +{ + int txp; + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortHndlGet(port); + MV_U32 regData, txFifoEmptyMask = 0, txInProgMask = 0; + int mDelay; + + /* Stop Rx port activity. Check port Rx activity. */ + regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(port))) & ETH_RXQ_ENABLE_MASK; + if (regData != 0) { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(port), (regData << ETH_RXQ_DISABLE_OFFSET)); + } + /* Wait for all Rx activity to terminate. */ + mDelay = 0; + do { + if (mDelay >= RX_DISABLE_TIMEOUT_MSEC) { + mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", port, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port RX Command register that all Rx queues are stopped */ + regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(port)); + } while (regData & 0xFF); + + /* Stop Tx port activity. Check port Tx activity. */ + for (txp = 0; txp < pPortCtrl->txpNum; txp++) { + /* Issue stop command for active channels only */ + regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(port, txp))) & ETH_TXQ_ENABLE_MASK; + if (regData != 0) + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(port, txp), (regData << ETH_TXQ_DISABLE_OFFSET)); + + /* Wait for all Tx activity to terminate. */ + mDelay = 0; + do { + if (mDelay >= TX_DISABLE_TIMEOUT_MSEC) { + mvOsPrintf("port=%d, txp=%d: TIMEOUT for TX stopped !!! txQueueCmd - 0x%08x\n", + port, txp, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port TX Command register that all Tx queues are stopped */ + regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(port, txp)); + } while (regData & 0xFF); + + if (MV_PON_PORT(port)) { + txFifoEmptyMask |= PON_TX_FIFO_EMPTY_MASK(txp); + txInProgMask |= PON_TX_IN_PROGRESS_MASK(txp); + } else { + txFifoEmptyMask = ETH_TX_FIFO_EMPTY_MASK; + txInProgMask = ETH_TX_IN_PROGRESS_MASK; + } + + } + + /* Double check to Verify that TX FIFO is Empty */ + mDelay = 0; + while (MV_TRUE) { + do { + if (mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) { + mvOsPrintf("\n port=%d, TX FIFO empty timeout. status=0x08%x, empty=0x%x, inProg=0x%x\n", + port, regData, txFifoEmptyMask, txInProgMask); + break; + } + mvOsDelay(1); + mDelay++; + + regData = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + } while (((regData & txFifoEmptyMask) != txFifoEmptyMask) || ((regData & txInProgMask) != 0)); + + if (mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + break; + + /* Double check */ + regData = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + if (((regData & txFifoEmptyMask) == txFifoEmptyMask) && ((regData & txInProgMask) == 0)) { + break; + } else + mvOsPrintf("port=%d: TX FIFO Empty double check failed. %d msec, status=0x%x, empty=0x%x, inProg=0x%x\n", + port, mDelay, regData, txFifoEmptyMask, txInProgMask); + } + + /* Wait about 200 usec */ + mvOsUDelay(200); + + return MV_OK; +} + +MV_STATUS mvNetaPortEnable(int port) +{ + if (!MV_PON_PORT(port)) { + MV_U32 regVal; + + /* Enable port */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + regVal |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), regVal); + + /* If Link is UP, Start RX and TX traffic */ + if (MV_REG_READ(ETH_PORT_STATUS_REG(port)) & ETH_LINK_UP_MASK) + return mvNetaPortUp(port); + } + return MV_NOT_READY; +} + +MV_STATUS mvNetaPortDisable(int port) +{ + MV_U32 regData; + + mvNetaPortDown(port); + + if (!MV_PON_PORT(port)) { + /* Reset the Enable bit in the Serial Control Register */ + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + regData &= ~(ETH_PORT_ENABLE_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), regData); + } + /* Wait about 200 usec */ + mvOsUDelay(200); + + return MV_OK; +} + +MV_BOOL mvNetaLinkIsUp(port) +{ + MV_U32 regVal; + + if (MV_PON_PORT(port)) + return MV_TRUE; + + regVal = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + if(regVal & ETH_LINK_UP_MASK) + return MV_TRUE; + + return MV_FALSE; +} + +MV_STATUS mvNetaLinkStatus(int port, MV_ETH_PORT_STATUS *pStatus) +{ + MV_U32 regVal; + + if (MV_PON_PORT(port)) { + /* FIXME: --BK */ + pStatus->linkup = MV_TRUE; + pStatus->speed = MV_ETH_SPEED_1000; + pStatus->duplex = MV_ETH_DUPLEX_FULL; + pStatus->rxFc = MV_ETH_FC_DISABLE; + pStatus->txFc = MV_ETH_FC_DISABLE; + return MV_OK; + } + + regVal = MV_REG_READ(ETH_PORT_STATUS_REG(port)); + + if (regVal & ETH_GMII_SPEED_1000_MASK) + pStatus->speed = MV_ETH_SPEED_1000; + else if (regVal & ETH_MII_SPEED_100_MASK) + pStatus->speed = MV_ETH_SPEED_100; + else + pStatus->speed = MV_ETH_SPEED_10; + + if (regVal & ETH_LINK_UP_MASK) + pStatus->linkup = MV_TRUE; + else + pStatus->linkup = MV_FALSE; + + if (regVal & ETH_FULL_DUPLEX_MASK) + pStatus->duplex = MV_ETH_DUPLEX_FULL; + else + pStatus->duplex = MV_ETH_DUPLEX_HALF; + + pStatus->txFc = MV_ETH_FC_DISABLE; + if (regVal & ETH_FLOW_CTRL_ENABLED_MASK) + pStatus->rxFc = MV_ETH_FC_ENABLE; + else + pStatus->rxFc = MV_ETH_FC_DISABLE; + + return MV_OK; +} + +MV_STATUS mvNetaRxqOffsetSet(int port, int rxq, int offset) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_CONFIG_REG(port, rxq)); + regVal &= ~NETA_RXQ_PACKET_OFFSET_ALL_MASK; + + /* Offset is in */ + regVal |= NETA_RXQ_PACKET_OFFSET_MASK(offset >> 3); + + MV_REG_WRITE(NETA_RXQ_CONFIG_REG(port, rxq), regVal); + + return MV_OK; +} + +MV_STATUS mvNetaBmPoolBufSizeSet(int port, int pool, int bufsize) +{ + MV_U32 regVal; + + regVal = MV_ALIGN_UP(bufsize, NETA_POOL_BUF_SIZE_ALIGN); + MV_REG_WRITE(NETA_POOL_BUF_SIZE_REG(port, pool), regVal); + + return MV_OK; +} + +MV_STATUS mvNetaRxqBmEnable(int port, int rxq, int shortPool, int longPool) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_CONFIG_REG(port, rxq)); + + regVal &= ~(NETA_RXQ_SHORT_POOL_ID_MASK | NETA_RXQ_LONG_POOL_ID_MASK); + regVal |= (shortPool << NETA_RXQ_SHORT_POOL_ID_OFFS); + regVal |= (longPool << NETA_RXQ_LONG_POOL_ID_OFFS); + regVal |= NETA_RXQ_HW_BUF_ALLOC_MASK; + + MV_REG_WRITE(NETA_RXQ_CONFIG_REG(port, rxq), regVal); + + return MV_OK; +} + +MV_STATUS mvNetaRxqBmDisable(int port, int rxq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_CONFIG_REG(port, rxq)); + + regVal &= ~NETA_RXQ_HW_BUF_ALLOC_MASK; + + MV_REG_WRITE(NETA_RXQ_CONFIG_REG(port, rxq), regVal); + + return MV_OK; +} + +/******************************************************************************/ +/* WRR / EJP configuration routines */ +/******************************************************************************/ + +/* Enable / Disable EJP mode */ +MV_STATUS mvNetaTxpEjpSet(int port, int txp, int enable) +{ + if (mvNetaTxpCheck(port, txp)) + return MV_BAD_PARAM; + + mvOsPrintf("Not supported\n"); + + return MV_OK; +} + +/* Set maximum burst rate (using IPG configuration) */ +MV_STATUS mvNetaTxpEjpBurstRateSet(int port, int txp, int txq, int rate) +{ + MV_U32 regVal; + + if (mvNetaTxpCheck(port, txp)) + return MV_BAD_PARAM; + + /* Only TXQs 2 and 3 are valid */ + if ((txq != 2) && (txq != 3)) { + mvOsPrintf("%s: txq=%d is INVALID. Only TXQs 2 and 3 are supported\n", __func__, txq); + return MV_BAD_PARAM; + } + + /* TBD - calculate */ + regVal = rate; + + /* MV_REG_WRITE( NETA_TXQ_EJP_IPG_REG(port, txp, txq), regVal); */ + mvOsPrintf("Not supported\n"); + + return MV_OK; +} + +/* Set maximum packet size for each one of EJP priorities (IsoLo, Async) */ +MV_STATUS mvNetaTxpEjpMaxPktSizeSet(int port, int txp, int type, int size) +{ + if (mvNetaTxpCheck(port, txp)) + return MV_BAD_PARAM; + + mvOsPrintf("Not supported\n"); + + /* TBD */ + return MV_OK; +} + +/* TBD - Set Transmit speed for EJP calculations */ +MV_STATUS mvNetaTxpEjpTxSpeedSet(int port, int txp, int type, int speed) +{ + MV_U32 regVal; + + if (mvNetaTxpCheck(port, txp)) + return MV_BAD_PARAM; + + /* TBD - add calc */ + regVal = speed; + + /* MV_REG_WRITE(NETA_TXP_EJP_SPEED_REG(port, txp), regVal); */ + mvOsPrintf("Not supported\n"); + + return MV_OK; +} + +/* Set TXQ to work in FIX priority mode */ +MV_STATUS mvNetaTxqFixPrioSet(int port, int txp, int txq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TX_FIXED_PRIO_CFG_REG(port, txp)); + regVal |= (1 << txq); + MV_REG_WRITE(ETH_TX_FIXED_PRIO_CFG_REG(port, txp), regVal); + + return MV_OK; +} + +/* Set TXQ to work in WRR mode and set relative weight. */ +/* Weight range [1..N] */ +MV_STATUS mvNetaTxqWrrPrioSet(int port, int txp, int txq, int weight) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TXQ_ARBITER_CFG_REG(port, txp, txq)); +/* + mtu = (regVal & ETH_TXQ_WRR_MTU_ALL_MASK) >> ETH_TXQ_WRR_MTU_OFFS; + weight = mtu*weight & ETH_TXQ_WRR_WEIGHT_MAX; +*/ + regVal &= ~ETH_TXQ_WRR_WEIGHT_ALL_MASK; + regVal |= ETH_TXQ_WRR_WEIGHT_MASK(weight); + MV_REG_WRITE(ETH_TXQ_ARBITER_CFG_REG(port, txp, txq), regVal); + + regVal = MV_REG_READ(ETH_TX_FIXED_PRIO_CFG_REG(port, txp)); + regVal &= ~(1 << txq); + MV_REG_WRITE(ETH_TX_FIXED_PRIO_CFG_REG(port, txp), regVal); + + return MV_OK; +} + +/* Set bandwidth limitation for TX port + * bw [Mbps] - steady state TX bandwidth limitation + */ +MV_STATUS mvNetaTxpRateSet(int port, int txp, int bw) +{ + MV_U32 regVal, rate; + + /* TokenRate[1/64 bit/cycle] = BW[Mb/sec]*64/TCLK[MHz]. */ + rate = ((bw * 64) / (mvNetaHalData.tClk / 1000000)) & ETH_TXP_TOKEN_RATE_MAX; + + regVal = MV_REG_READ(ETH_TXP_TOKEN_RATE_CFG_REG(port, txp)); + regVal &= ~ETH_TXP_TOKEN_RATE_ALL_MASK; + regVal |= ETH_TXP_TOKEN_RATE_MASK(rate); + + MV_REG_WRITE(ETH_TXP_TOKEN_RATE_CFG_REG(port, txp), regVal); + + return MV_OK; +} + +/* Set maximum burst size for TX port + * burst [bits] - number of bits to be sent with maximum possible TX rate, + * before TX rate limitation will take place. + */ +MV_STATUS mvNetaTxpBurstSet(int port, int txp, int burst) +{ + MV_U32 regVal, size; + + /* Tocket Bucket Size */ + size = (256 * 8 * burst) & ETH_TXP_TOKEN_SIZE_MAX; + + regVal = MV_REG_READ(ETH_TXP_TOKEN_SIZE_REG(port, txp)); + regVal &= ~ETH_TXP_TOKEN_SIZE_ALL_MASK; + regVal |= ETH_TXP_TOKEN_SIZE_MASK(size); + + MV_REG_WRITE(ETH_TXP_TOKEN_SIZE_REG(port, txp), regVal); + + return MV_OK; +} + +/* Set bandwidth limitation for TXQ + * rate [Mbps] - steady state TX rate limitation + */ +MV_STATUS mvNetaTxqRateSet(int port, int txp, int txq, int bw) +{ + MV_U32 regVal; + MV_U32 rate; + + regVal = MV_REG_READ(ETH_TXQ_TOKEN_CFG_REG(port, txp, txq)); + + /* TokenRate[1/64 bit/cycle] = BW[Mb/sec]*64/TCLK[MHz]. */ + rate = ((bw * 64) / (mvNetaHalData.tClk / 1000000)) & ETH_TXQ_TOKEN_RATE_MAX; + + regVal &= ~ETH_TXQ_TOKEN_RATE_ALL_MASK; + regVal |= ETH_TXQ_TOKEN_RATE_MASK(rate); + + return MV_OK; +} + +/* Set maximum burst size for TX port + * burst [bits] - number of bits to be sent with maximum possible TX rate, + * before TX bandwidth limitation will take place. + */ +MV_STATUS mvNetaTxqBurstSet(int port, int txp, int txq, int burst) +{ + MV_U32 regVal, size; + + /* Tocket Bucket Size */ + size = (256 * 8 * burst) & ETH_TXQ_TOKEN_SIZE_MAX; + + regVal = MV_REG_READ(ETH_TXQ_TOKEN_CFG_REG(port, txp, txq)); + regVal &= ~ETH_TXQ_TOKEN_SIZE_ALL_MASK; + regVal |= ETH_TXQ_TOKEN_SIZE_MASK(size); + + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(port, txp, txq), regVal); + + return MV_OK; +} + +#ifndef CONFIG_MV_ETH_PNC +/******************************************************************************/ +/* RX Dispatching configuration routines */ +/******************************************************************************/ + +MV_STATUS mvNetaTcpRxq(int port, int rxq) +{ + MV_U32 portCfgReg; + + if ((rxq < 0) || (rxq >= MV_ETH_MAX_RXQ)) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", rxq); + return MV_BAD_PARAM; + } + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(port)); + + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(rxq); + portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), portCfgReg); + + return MV_OK; +} + +MV_STATUS mvNetaUdpRxq(int port, int rxq) +{ + MV_U32 portCfgReg; + + if ((rxq < 0) || (rxq >= MV_ETH_MAX_RXQ)) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", rxq); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(port)); + + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(rxq); + portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), portCfgReg); + + return MV_OK; +} + +MV_STATUS mvNetaArpRxq(int port, int rxq) +{ + MV_U32 portCfgReg; + + if ((rxq < 0) || (rxq >= MV_ETH_MAX_RXQ)) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", rxq); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(port)); + + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(rxq); + portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), portCfgReg); + + return MV_OK; +} + +MV_STATUS mvNetaBpduRxq(int port, int rxq) +{ + MV_U32 portCfgReg; + MV_U32 portCfgExtReg; + + if ((rxq < 0) || (rxq >= MV_ETH_MAX_RXQ)) { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", rxq); + return MV_BAD_PARAM; + } + + portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(port)); + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(port)); + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(rxq); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(port), portCfgReg); + + portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(port), portCfgExtReg); + + return MV_OK; +} +#endif /* CONFIG_MV_ETH_PNC */ + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvNetaMibCounterRead - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or +* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, +* so pHigh32 pointer should not be NULL in this case. +* +* INPUT: +* port - Ethernet Port number. +* mib - MIB number +* mibOffset - MIB counter offset. +* +* OUTPUT: +* MV_U32* pHigh32 - pointer to place where 32 most significant bits +* of the counter will be stored. +* +* RETURN: +* 32 low sgnificant bits of MIB counter value. +* +*******************************************************************************/ +MV_U32 mvNetaMibCounterRead(int port, int mib, unsigned int mibOffset, MV_U32 *pHigh32) +{ + MV_U32 valLow32, valHigh32; + + valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(port, mib) + mibOffset); + + /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ + /* of a 64-bit MIB Counter. */ + if ((mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW)) { + valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(port, mib) + mibOffset + 4); + if (pHigh32 != NULL) + *pHigh32 = valHigh32; + } + return valLow32; +} + +/******************************************************************************* +* mvNetaMibCountersClear - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters +* +* INPUT: +* port - Ethernet Port number. +* txp - TX port number +* +* +* RETURN: void +* +*******************************************************************************/ +void mvNetaMibCountersClear(int port, int mib) +{ + int i; + MV_U32 dummy; + + if (MV_PON_PORT(port)) + return; + + /* Perform dummy reads from MIB counters */ + for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) + dummy = MV_REG_READ((ETH_MIB_COUNTERS_BASE(port, mib) + i)); +} + +/******************************************************************************* +* mvNetaFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configures the port's Flow Control properties. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvNetaFlowCtrlSet(int port, MV_ETH_PORT_FC flowControl) +{ + MV_U32 regVal; + + if ((port < 0) || (port >= mvNetaHalData.maxPort)) + return MV_OUT_OF_RANGE; + + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + + switch (flowControl) { + case MV_ETH_FC_AN_NO: + regVal &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + regVal &= ~ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_AN_SYM: + regVal &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + regVal |= ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_DISABLE: + regVal |= ETH_DISABLE_FC_AUTO_NEG_MASK; + regVal &= ~ETH_SET_FLOW_CTRL_MASK; + break; + + case MV_ETH_FC_ENABLE: + regVal |= ETH_DISABLE_FC_AUTO_NEG_MASK; + regVal |= ETH_SET_FLOW_CTRL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), regVal); + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaDebug.c u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaDebug.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaDebug.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaDebug.c 2011-04-04 13:57:34.985596949 -0400 @@ -0,0 +1,722 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNetaDebug.c - Source file for user friendly debug functions +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" + +#include "mvNeta.h" +#include "bm/mvBm.h" +#include "pnc/mvTcam.h" + +static void mvEthRegPrint(MV_U32 reg_addr, MV_U8 *reg_name) +{ + mvOsPrintf(" %-32s: 0x%x = 0x%08x\n", reg_name, reg_addr, MV_REG_READ(reg_addr)); +} + +static void mvEthRegPrint0(MV_U32 reg_addr, MV_U8 *reg_name) +{ + mvOsPrintf(" %-32s: %u\n", reg_name, MV_REG_READ(reg_addr)); +} + +static void mvEthRegPrint2(MV_U32 reg_addr, MV_U8 *reg_name, MV_U32 index) +{ + char buf[64]; + + mvOsSPrintf(buf, "%s[%d]", reg_name, index); + mvOsPrintf(" %-32s: 0x%x = 0x%08x\n", buf, reg_addr, MV_REG_READ(reg_addr)); +} + +static void mvEthMibPrint(int port, int mib, MV_U32 offset, MV_U8 *mib_name) +{ + MV_U32 regVaLo, regValHi = 0; + + regVaLo = mvNetaMibCounterRead(port, mib, offset, ®ValHi); + + if (!regValHi) + mvOsPrintf(" %-32s: %u\n", mib_name, regVaLo); + else + mvOsPrintf(" t%-32s: 0x%08x%08x\n", mib_name, regValHi, regVaLo); +} + +void mvEthTxpWrrRegs(int port, int txp) +{ + int queue; + + if (mvNetaTxpCheck(port, txp)) + return; + + mvOsPrintf("\n[TXP WRR/EJP registers: port=%d, txp=%d]\n", port, txp); + mvEthRegPrint(ETH_TX_QUEUE_COMMAND_REG(port, txp), "ETH_TX_QUEUE_COMMAND_REG"); + +#ifdef MV_ETH_WRR_NEW + mvEthRegPrint(NETA_TX_CMD_1_REG(port,txp), "NETA_TX_CMD_1_REG"); + mvEthRegPrint(NETA_TX_FIXED_PRIO_CFG_REG(port,txp), "NETA_TX_FIXED_PRIO_CFG_REG"); + mvEthRegPrint(NETA_TX_REFILL_PERIOD_REG(port,txp), "NETA_TX_REFILL_PERIOD_REG"); + mvEthRegPrint(NETA_TXP_MTU_REG(port,txp), "NETA_TXP_MTU_REG"); + mvEthRegPrint(NETA_TXP_REFILL_REG(port,txp), "NETA_TXP_REFILL_REG"); + mvEthRegPrint(NETA_TXP_TOKEN_SIZE_REG(port,txp), "NETA_TXP_TOKEN_SIZE_REG"); + mvEthRegPrint(NETA_TXP_TOKEN_CNTR_REG(port,txp), "NETA_TXP_TOKEN_CNTR_REG"); + mvEthRegPrint(NETA_TXP_EJP_HI_LO_REG(port,txp), "NETA_TXP_EJP_HI_LO_REG"); + mvEthRegPrint(NETA_TXP_EJP_HI_ASYNC_REG(port,txp), "NETA_TXP_EJP_HI_ASYNC_REG"); + mvEthRegPrint(NETA_TXP_EJP_LO_ASYNC_REG(port,txp), "NETA_TXP_EJP_LO_ASYNC_REG"); + mvEthRegPrint(NETA_TXP_EJP_SPEED_REG(port,txp), "NETA_TXP_EJP_SPEED_REG"); + + for(queue=0; queue> ETH_DEF_RX_QUEUE_OFFSET, + (regValue & ETH_DEF_RX_ARP_QUEUE_ALL_MASK) >> ETH_DEF_RX_ARP_QUEUE_OFFSET, + (regValue & ETH_DEF_RX_BPDU_QUEUE_ALL_MASK) >> ETH_DEF_RX_BPDU_QUEUE_OFFSET, + (regValue & ETH_DEF_RX_TCP_QUEUE_ALL_MASK) >> ETH_DEF_RX_TCP_QUEUE_OFFSET, + (regValue & ETH_DEF_RX_UDP_QUEUE_ALL_MASK) >> ETH_DEF_RX_UDP_QUEUE_OFFSET); + } +#endif /* CONFIG_MV_ETH_PNC */ +} + +void mvNetaRxqShow(int port, int rxq, int mode) +{ + MV_NETA_PORT_CTRL *pPortCtrl; + MV_NETA_QUEUE_CTRL *pQueueCtrl; + + if (mvNetaPortCheck(port)) + return; + + if (mvNetaMaxCheck(rxq, MV_ETH_MAX_RXQ)) + return; + + pPortCtrl = mvNetaPortHndlGet(port); + if (!pPortCtrl) + return; + + pQueueCtrl = &pPortCtrl->pRxQueue[rxq].queueCtrl; + mvOsPrintf("\n[NetA RxQ: port=%d, rxq=%d]\n", port, rxq); + + if (!pQueueCtrl->pFirst) { + mvOsPrintf("rx queue %d wasn't created\n", rxq); + return; + } + + mvOsPrintf("pFirst=%p (0x%x), numOfDescr=%d\n", + pQueueCtrl->pFirst, + (MV_U32) netaDescVirtToPhys(pQueueCtrl, (MV_U8 *) pQueueCtrl->pFirst), pQueueCtrl->lastDesc + 1); + + mvOsPrintf("nextToProc=%d (%p), rxqOccupied=%d, rxqNonOccupied=%d\n", + pQueueCtrl->nextToProc, + MV_NETA_QUEUE_DESC_PTR(pQueueCtrl, pQueueCtrl->nextToProc), + mvNetaRxqBusyDescNumGet(port, rxq), mvNetaRxqFreeDescNumGet(port, rxq)); + + if (mode > 0) { + int i; + NETA_RX_DESC *pRxDesc; + + for (i = 0; i <= pQueueCtrl->lastDesc; i++) { + pRxDesc = (NETA_RX_DESC *) MV_NETA_QUEUE_DESC_PTR(pQueueCtrl, i); + + mvOsPrintf("%3d. desc=%p, status=%08x, data=%4d, bufAddr=%08x, bufCookie=%08x\n", + i, pRxDesc, pRxDesc->status, + pRxDesc->dataSize, (MV_U32) pRxDesc->bufPhysAddr, (MV_U32) pRxDesc->bufCookie); + + mvOsCacheLineInv(NULL, pRxDesc); + } + } +} + +void mvNetaTxqShow(int port, int txp, int txq, int mode) +{ + MV_NETA_PORT_CTRL *pPortCtrl; + MV_NETA_TXQ_CTRL *pTxqCtrl; + MV_NETA_QUEUE_CTRL *pQueueCtrl; + + if (mvNetaTxpCheck(port, txp)) + return; + + pPortCtrl = mvNetaPortHndlGet(port); + if (!pPortCtrl) + return; + + if (mvNetaMaxCheck(txq, MV_ETH_MAX_TXQ)) + return; + + mvOsPrintf("\n[NetA TxQ: port=%d, txp=%d, txq=%d]\n", port, txp, txq); + + pTxqCtrl = mvNetaTxqHndlGet(port, txp, txq); + pQueueCtrl = &pTxqCtrl->queueCtrl; + + if (!pQueueCtrl->pFirst) { + mvOsPrintf("tx queue %d wasn't created\n", txq); + return; + } + + mvOsPrintf("pFirst=%p (0x%x), numOfDescr=%d\n", + pQueueCtrl->pFirst, + (MV_U32) netaDescVirtToPhys(pQueueCtrl, (MV_U8 *) pQueueCtrl->pFirst), pQueueCtrl->lastDesc + 1); + + mvOsPrintf("nextToProc=%d (%p), txqSent=%d, txqPending=%d\n", + pQueueCtrl->nextToProc, + MV_NETA_QUEUE_DESC_PTR(pQueueCtrl, pQueueCtrl->nextToProc), + mvNetaTxqSentDescNumGet(port, txp, txq), mvNetaTxqPendDescNumGet(port, txp, txq)); + + if (mode > 0) { + int i; + NETA_TX_DESC *pTxDesc; + + for (i = 0; i <= pQueueCtrl->lastDesc; i++) { + pTxDesc = (NETA_TX_DESC *) MV_NETA_QUEUE_DESC_PTR(pQueueCtrl, i); + + mvOsPrintf("%3d. pTxDesc=%p, cmd=%08x, data=%4d, bufAddr=%08x, gponinfo=%x\n", + i, pTxDesc, pTxDesc->command, pTxDesc->dataSize, + (MV_U32) pTxDesc->bufPhysAddr, pTxDesc->hw_cmd); + + mvOsCacheLineInv(NULL, pTxDesc); + } + } +} + +/* Print counters of the Ethernet port */ +void mvEthPortCounters(int port, int mib) +{ + if (MV_PON_PORT(port)) { + mvOsPrintf("%s: not supported for PON port\n", __func__); + return; + } + + if (mvNetaTxpCheck(port, mib)) + return; + + if (!mvNetaPortHndlGet(port)) + return; + + mvOsPrintf("\nMIBs: port=%d, mib=%d\n", port, mib); + +#ifdef CONFIG_MV_PON + if (MV_PON_PORT(port)) { + int i; + + for(i=0; i> 24) & 0xff), ((macH >> 16) & 0xff), + ((macH >> 8) & 0xff), (macH & 0xff), ((macL >> 8) & 0xff), (macL & 0xff)); + + for (i = 0; i < 4; i++) { + unicastReg = MV_REG_READ((ETH_DA_FILTER_UCAST_BASE(port) + i * 4)); + for (j = 0; j < 4; j++) { + MV_U8 macEntry = (unicastReg >> (8 * j)) & 0xFF; + mvOsPrintf("%X: %8s, Q = %d\n", i * 4 + j, + (macEntry & BIT0) ? "accept" : "reject", (macEntry >> 1) & 0x7); + } + } +} + +void mvEthPortMcastShow(int port) +{ + int tblIdx, regIdx; + MV_U32 regVal; + + mvOsPrintf("Special (IP) Multicast Table port=%d: 01:00:5E:00:00:XX\n", port); + + for (tblIdx = 0; tblIdx < (256 / 4); tblIdx++) { + regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx * 4)); + for (regIdx = 0; regIdx < 4; regIdx++) { + if ((regVal & (0x01 << (regIdx * 8))) != 0) { + mvOsPrintf("0x%02X: accepted, rxQ = %d\n", + tblIdx * 4 + regIdx, ((regVal >> (regIdx * 8 + 1)) & 0x07)); + } + } + } + + mvOsPrintf("Other Multicast Table: port=%d\n", port); + for (tblIdx = 0; tblIdx < (256 / 4); tblIdx++) { + regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx * 4)); + for (regIdx = 0; regIdx < 4; regIdx++) { + if ((regVal & (0x01 << (regIdx * 8))) != 0) { + mvOsPrintf("crc8=0x%02X: accepted, rxq = %d\n", + tblIdx * 4 + regIdx, ((regVal >> (regIdx * 8 + 1)) & 0x07)); + } + } + } +} + +#ifdef CONFIG_MV_ETH_HWF +void mvNetaHwfTxpCntrs(int port, int p, int txp) +{ + int txq; + MV_U32 regVal; + + if (mvNetaPortCheck(port) || mvNetaPortCheck(p)) + return; + + if (mvNetaTxpCheck(p, txp)) + return; + + mvOsPrintf("\n[HWF Counters: port=%d]\n", port); + + for (txq = 0; txq < CONFIG_MV_ETH_TXQ; txq++) { + mvOsPrintf("\n[HWF: hwf_txp=%d, txq=%d]\n", p + txp, txq); + + regVal = NETA_HWF_TX_PORT_MASK(p + txp) | NETA_HWF_TXQ_MASK(txq); + MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal); + + mvEthRegPrint(NETA_HWF_ACCEPTED_CNTR(port), "NETA_HWF_ACCEPTED_CNTR"); + mvEthRegPrint(NETA_HWF_YELLOW_DROP_CNTR(port), "NETA_HWF_YELLOW_DROP_CNTR"); + mvEthRegPrint(NETA_HWF_GREEN_DROP_CNTR(port), "NETA_HWF_GREEN_DROP_CNTR"); + mvEthRegPrint(NETA_HWF_THRESH_DROP_CNTR(port), "NETA_HWF_THRESH_DROP_CNTR"); + } +} + +void mvNetaHwfRxpRegs(int port) +{ + int txpNum, txp; + + if (mvNetaPortCheck(port)) + return; + + mvOsPrintf("\n[HWF Config: port=%d]\n", port); + mvEthRegPrint(NETA_HWF_RX_CTRL_REG(port), "NETA_HWF_RX_CTRL_REG"); + mvEthRegPrint(NETA_HWF_RX_THRESH_REG(port), "NETA_HWF_RX_THRESH_REG"); + + /* Calculate total number of txp */ + txpNum = 2; + +#ifdef CONFIG_MV_PON + txpNum += MV_ETH_MAX_TCONT(); +#endif /* CONFIG_MV_PON */ + + for (txp = 0; txp < txpNum; txp += 2) + mvEthRegPrint2(NETA_HWF_TXP_CFG_REG(port, txp), "NETA_HWF_TXP_CFG_REG", txp); +} + +void mvNetaHwfTxpRegs(int port, int p, int txp) +{ + int txq; + MV_U32 regVal; + + if (mvNetaPortCheck(port) || mvNetaPortCheck(p)) + return; + + if (mvNetaTxpCheck(p, txp)) + return; + + for (txq = 0; txq < CONFIG_MV_ETH_TXQ; txq++) { + mvOsPrintf("\n[HWF: hwf_txp=%d, txq=%d]\n", p + txp, txq); + regVal = NETA_HWF_TX_PORT_MASK(p + txp) | NETA_HWF_TXQ_MASK(txq); + MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal); + + mvEthRegPrint(NETA_HWF_DROP_TH_REG(port), "NETA_HWF_DROP_TH_REG"); + mvEthRegPrint(NETA_HWF_TXQ_BASE_REG(port), "NETA_HWF_TXQ_BASE_REG"); + mvEthRegPrint(NETA_HWF_TXQ_SIZE_REG(port), "NETA_HWF_TXQ_SIZE_REG"); + mvEthRegPrint(NETA_HWF_TXQ_ENABLE_REG(port), "NETA_HWF_TXQ_ENABLE_REG"); + } +} +#endif /* CONFIG_MV_ETH_HWF */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNeta.h u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNeta.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNeta.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNeta.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,568 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvNeta_h__ +#define __mvNeta_h__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysEthConfig.h" +#include "mvNetaRegs.h" +#include "mvEthRegs.h" + + +#define NETA_RX_IP_IS_FRAG(status) ((status) & NETA_RX_IP4_FRAG_MASK) +#define NETA_RX_L4_CSUM_IS_OK(status) ((status) & NETA_RX_L4_CSUM_OK_MASK) + +#ifdef CONFIG_MV_ETH_PNC +#define NETA_RX_L3_IS_IP4(status) (((status) & NETA_RX_L3_MASK) == NETA_RX_L3_IP4) +#define NETA_RX_L3_IS_IP4_ERR(status) (((status) & NETA_RX_L3_MASK) == NETA_RX_L3_IP4_ERR) +#define NETA_RX_L3_IS_IP6(status) (((status) & NETA_RX_L3_MASK) == NETA_RX_L3_IP6) +#define NETA_RX_L4_IS_TCP(status) (((status) & NETA_RX_L4_MASK) == NETA_RX_L4_TCP) +#define NETA_RX_L4_IS_UDP(status) (((status) & NETA_RX_L4_MASK) == NETA_RX_L4_UDP) +#else +#define NETA_RX_L3_IS_IP4(status) ((status) & ETH_RX_IP_HEADER_OK_MASK) +#define NETA_RX_L3_IS_IP4_ERR(status) (((status) & ETH_RX_IP_FRAME_TYPE_MASK) && \ + !((status) & ETH_RX_IP_HEADER_OK_MASK)) +#define NETA_RX_L3_IS_IP6(status) (MV_FALSE) +#define NETA_RX_L4_IS_TCP(status) (((status) & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_TCP_TYPE) +#define NETA_RX_L4_IS_UDP(status) (((status) & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_UDP_TYPE) +#endif /* CONFIG_MV_ETH_PNC */ + + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE(rxQ) \ + ( \ + ETH_DEF_RX_QUEUE_MASK(rxQ) | \ + ETH_DEF_RX_ARP_QUEUE_MASK(rxQ) | \ + ETH_DEF_RX_TCP_QUEUE_MASK(rxQ) | \ + ETH_DEF_RX_UDP_QUEUE_MASK(rxQ) | \ + ETH_DEF_RX_BPDU_QUEUE_MASK(rxQ) | \ + ETH_RX_CHECKSUM_WITH_PSEUDO_HDR \ + ) + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE 0 +#define PORT_SERIAL_CONTROL_VALUE \ + ( \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_SET_FULL_DUPLEX_MASK \ + ) + +typedef enum { + MV_ETH_SPEED_AN, + MV_ETH_SPEED_10, + MV_ETH_SPEED_100, + MV_ETH_SPEED_1000 +} MV_ETH_PORT_SPEED; + +typedef enum { + MV_ETH_DUPLEX_AN, + MV_ETH_DUPLEX_HALF, + MV_ETH_DUPLEX_FULL +} MV_ETH_PORT_DUPLEX; + +typedef enum { + MV_ETH_FC_AN_NO, + MV_ETH_FC_AN_SYM, + MV_ETH_FC_AN_ASYM, + MV_ETH_FC_DISABLE, + MV_ETH_FC_ENABLE, + MV_ETH_FC_ACTIVE, + +} MV_ETH_PORT_FC; + + +typedef enum { + MV_ETH_PRIO_FIXED = 0, /* Fixed priority mode */ + MV_ETH_PRIO_WRR = 1 /* Weighted round robin priority mode */ +} MV_ETH_PRIO_MODE; + +/* Ethernet port specific infomation */ +typedef struct eth_link_status { + MV_BOOL linkup; + MV_ETH_PORT_SPEED speed; + MV_ETH_PORT_DUPLEX duplex; + MV_ETH_PORT_FC rxFc; + MV_ETH_PORT_FC txFc; + +} MV_ETH_PORT_STATUS; + +typedef enum { + MV_NETA_MH_NONE = 0, + MV_NETA_MH = 1, + MV_NETA_DSA = 2, + MV_NETA_DSA_EXT = 3 +} MV_NETA_MH_MODE; + +typedef struct { + MV_U32 maxPort; + MV_U32 pClk; + MV_U32 tClk; + +#ifdef CONFIG_MV_ETH_BM + MV_ULONG bmPhysBase; + MV_U8 *bmVirtBase; +#endif /* CONFIG_MV_ETH_BM */ + +#ifdef CONFIG_MV_ETH_PNC + MV_ULONG pncPhysBase; + MV_U8 *pncVirtBase; +#endif /* CONFIG_MV_ETH_PNC */ + MV_U8 maxCPUs; +} MV_NETA_HAL_DATA; + +typedef struct eth_pbuf { + void *osInfo; + MV_ULONG physAddr; + MV_U8 *pBuf; + MV_U16 bytes; + MV_U16 offset; + MV_U32 tx_cmd; + void *dev; + MV_U8 pool; + MV_U8 tos; + MV_U16 reserved; + MV_U32 hw_cmd; +} MV_ETH_PKT; + +typedef struct { + char *pFirst; + int lastDesc; + int nextToProc; + int descSize; + MV_BUF_INFO descBuf; + +} MV_NETA_QUEUE_CTRL; + +#define MV_NETA_QUEUE_DESC_PTR(pQueueCtrl, descIdx) \ + ((pQueueCtrl)->pFirst + ((descIdx) * NETA_DESC_ALIGNED_SIZE)) + +#define MV_NETA_QUEUE_NEXT_DESC(pQueueCtrl, descIdx) \ + (((descIdx) < (pQueueCtrl)->lastDesc) ? ((descIdx) + 1) : 0) + +#define MV_NETA_QUEUE_PREV_DESC(pQueueCtrl, descIdx) \ + (((descIdx) > 0) ? ((descIdx) - 1) : (pQueueCtrl)->lastDesc) + +typedef struct { + MV_NETA_QUEUE_CTRL queueCtrl; + +} MV_NETA_RXQ_CTRL; + +typedef struct { + MV_NETA_QUEUE_CTRL queueCtrl; + +} MV_NETA_TXQ_CTRL; + +typedef struct { + int portNo; + MV_NETA_RXQ_CTRL *pRxQueue; + MV_NETA_TXQ_CTRL *pTxQueue; + int rxqNum; + int txpNum; + int txqNum; + MV_U8 mcastCount[256]; + void *osHandle; +} MV_NETA_PORT_CTRL; + +extern MV_NETA_PORT_CTRL **mvNetaPortCtrl; +extern MV_NETA_HAL_DATA mvNetaHalData; + +#ifdef CONFIG_MV_PON +#define MV_ETH_MAX_TCONT() CONFIG_MV_PON_TCONTS +#endif /* CONFIG_MV_PON */ + +/* Get Giga port handler */ +static INLINE MV_NETA_PORT_CTRL *mvNetaPortHndlGet(int port) +{ + return mvNetaPortCtrl[port]; +} + +/* Get RX queue handler */ +static INLINE MV_NETA_RXQ_CTRL *mvNetaRxqHndlGet(int port, int rxq) +{ + return &mvNetaPortCtrl[port]->pRxQueue[rxq]; +} + +/* Get TX queue handler */ +static INLINE MV_NETA_TXQ_CTRL *mvNetaTxqHndlGet(int port, int txp, int txq) +{ + MV_NETA_PORT_CTRL *pPortCtrl = mvNetaPortCtrl[port]; + + return &pPortCtrl->pTxQueue[txp * pPortCtrl->txqNum + txq]; +} + +#if defined(MV_CPU_BE) +/* Swap RX descriptor to be BE */ +static INLINE void mvNetaRxqDescSwap(NETA_RX_DESC *pRxDesc) +{ + pRxDesc->status = MV_BYTE_SWAP_32BIT(pRxDesc->status); + pRxDesc->pncInfo = MV_BYTE_SWAP_16BIT(pRxDesc->pncInfo); + pRxDesc->dataSize = MV_BYTE_SWAP_16BIT(pRxDesc->dataSize); + pRxDesc->bufPhysAddr = MV_BYTE_SWAP_32BIT(pRxDesc->bufPhysAddr); + pRxDesc->pncFlowId = MV_BYTE_SWAP_32BIT(pRxDesc->pncFlowId); + /* pRxDesc->bufCookie = MV_BYTE_SWAP_32BIT(pRxDesc->bufCookie); */ + pRxDesc->prefetchCmd = MV_BYTE_SWAP_16BIT(pRxDesc->prefetchCmd); + pRxDesc->csumL4 = MV_BYTE_SWAP_16BIT(pRxDesc->csumL4); + pRxDesc->pncExtra = MV_BYTE_SWAP_32BIT(pRxDesc->pncExtra); + pRxDesc->hw_cmd = MV_BYTE_SWAP_32BIT(pRxDesc->hw_cmd); +} + +/* Swap TX descriptor to be BE */ +static INLINE void mvNetaTxqDescSwap(NETA_TX_DESC *pTxDesc) +{ + pTxDesc->command = MV_BYTE_SWAP_32BIT(pTxDesc->command); + pTxDesc->csumL4 = MV_BYTE_SWAP_16BIT(pTxDesc->csumL4); + pTxDesc->dataSize = MV_BYTE_SWAP_16BIT(pTxDesc->dataSize); + pTxDesc->bufPhysAddr = MV_BYTE_SWAP_32BIT(pTxDesc->bufPhysAddr); + pTxDesc->hw_cmd = MV_BYTE_SWAP_32BIT(pTxDesc->hw_cmd); +} +#endif /* MV_CPU_BE */ + +/* Get number of RX descriptors occupied by received packets */ +static INLINE int mvNetaRxqBusyDescNumGet(int port, int rxq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_STATUS_REG(port, rxq)); + + return (regVal & NETA_RXQ_OCCUPIED_DESC_ALL_MASK) >> NETA_RXQ_OCCUPIED_DESC_OFFS; +} + +/* Get number of free RX descriptors ready to received new packets */ +static INLINE int mvNetaRxqFreeDescNumGet(int port, int rxq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_RXQ_STATUS_REG(port, rxq)); + + return (regVal & NETA_RXQ_NON_OCCUPIED_DESC_ALL_MASK) >> NETA_RXQ_NON_OCCUPIED_DESC_OFFS; +} + +/* Update HW with number of RX descriptors processed by SW: + * - decrement number of occupied descriptors + * - increment number of Non-occupied descriptors + */ +static INLINE void mvNetaRxqDescNumUpdate(int port, int rxq, int rx_done, int rx_filled) +{ + MV_U32 regVal; + + /* Only 255 descriptors can be added at once - we don't check it for performance */ + /* Assume caller process RX desriptors in quanta less than 256 */ + regVal = (rx_done << NETA_RXQ_DEC_OCCUPIED_OFFS) | (rx_filled << NETA_RXQ_ADD_NON_OCCUPIED_OFFS); + MV_REG_WRITE(NETA_RXQ_STATUS_UPDATE_REG(port, rxq), regVal); +} + +/* Add number of descriptors are ready to receive new packets */ +static INLINE void mvNetaRxqNonOccupDescAdd(int port, int rxq, int rx_desc) +{ + MV_U32 regVal; + + /* Only 255 descriptors can be added at once */ + while (rx_desc > 0xFF) { + regVal = (0xFF << NETA_RXQ_ADD_NON_OCCUPIED_OFFS); + MV_REG_WRITE(NETA_RXQ_STATUS_UPDATE_REG(port, rxq), regVal); + rx_desc = rx_desc - 0xFF; + } + regVal = (rx_desc << NETA_RXQ_ADD_NON_OCCUPIED_OFFS); + MV_REG_WRITE(NETA_RXQ_STATUS_UPDATE_REG(port, rxq), regVal); +} + +/* Get number of TX descriptors already sent by HW */ +static INLINE int mvNetaTxqSentDescNumGet(int port, int txp, int txq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_TXQ_STATUS_REG(port, txp, txq)); + + return (regVal & NETA_TXQ_SENT_DESC_MASK) >> NETA_TXQ_SENT_DESC_OFFS; +} + +/* Get number of TX descriptors didn't send by HW yet and waiting for TX */ +static INLINE int mvNetaTxqPendDescNumGet(int port, int txp, int txq) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(NETA_TXQ_STATUS_REG(port, txp, txq)); + + return (regVal & NETA_TXQ_PENDING_DESC_MASK) >> NETA_TXQ_PENDING_DESC_OFFS; +} + +/* Update HW with number of TX descriptors to be sent */ +static INLINE void mvNetaTxqPendDescAdd(int port, int txp, int txq, int pend_desc) +{ + MV_U32 regVal; + + /* Only 255 descriptors can be added at once - we don't check it for performance */ + /* Assume caller process TX desriptors in quanta less than 256 */ + regVal = (pend_desc << NETA_TXQ_ADD_PENDING_OFFS); + MV_REG_WRITE(NETA_TXQ_UPDATE_REG(port, txp, txq), regVal); +} + +/* Decrement sent descriptors counter */ +static INLINE void mvNetaTxqSentDescDec(int port, int txp, int txq, int sent_desc) +{ + MV_U32 regVal; + + /* Only 255 TX descriptors can be updated at once */ + while (sent_desc > 0xFF) { + regVal = (0xFF << NETA_TXQ_DEC_SENT_OFFS); + MV_REG_WRITE(NETA_TXQ_UPDATE_REG(port, txp, txq), regVal); + sent_desc = sent_desc - 0xFF; + } + regVal = (sent_desc << NETA_TXQ_DEC_SENT_OFFS); + MV_REG_WRITE(NETA_TXQ_UPDATE_REG(port, txp, txq), regVal); +} + +/* Get pointer to next RX descriptor to be processed by SW */ +static INLINE NETA_RX_DESC *mvNetaRxqNextDescGet(MV_NETA_RXQ_CTRL *pRxq) +{ + NETA_RX_DESC *pRxDesc; + int rxDesc = pRxq->queueCtrl.nextToProc; + + pRxq->queueCtrl.nextToProc = MV_NETA_QUEUE_NEXT_DESC(&(pRxq->queueCtrl), rxDesc); + + pRxDesc = ((NETA_RX_DESC *)pRxq->queueCtrl.pFirst) + rxDesc; + + mvOsCacheLineInv(NULL, pRxDesc); + +#if defined(MV_CPU_BE) + mvNetaRxqDescSwap(pRxDesc); +#endif /* MV_CPU_BE */ + + return pRxDesc; +} + +/* Refill RX descriptor (when BM is not supported) */ +static INLINE void mvNetaRxDescFill(NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt) +{ + pRxDesc->bufCookie = (MV_U32) pPkt; + + pRxDesc->bufPhysAddr = MV_32BIT_LE(pPkt->physAddr); + + mvOsCacheLineFlush(NULL, pRxDesc); +} + +/* Get pointer to next TX descriptor to be processed (send) by HW */ +static INLINE NETA_TX_DESC *mvNetaTxqNextDescGet(MV_NETA_TXQ_CTRL *pTxq) +{ + int txDesc = pTxq->queueCtrl.nextToProc; + + pTxq->queueCtrl.nextToProc = MV_NETA_QUEUE_NEXT_DESC(&(pTxq->queueCtrl), txDesc); + + return ((NETA_TX_DESC *) pTxq->queueCtrl.pFirst) + txDesc; +} + +/* Get pointer to previous TX descriptor in the ring for rollback when needed */ +static INLINE NETA_TX_DESC *mvNetaTxqPrevDescGet(MV_NETA_TXQ_CTRL *pTxq) +{ + int txDesc = pTxq->queueCtrl.nextToProc; + + pTxq->queueCtrl.nextToProc = MV_NETA_QUEUE_PREV_DESC(&(pTxq->queueCtrl), txDesc); + + return ((NETA_TX_DESC *) pTxq->queueCtrl.pFirst) + txDesc; +} +static INLINE MV_ULONG netaDescVirtToPhys(MV_NETA_QUEUE_CTRL *pQueueCtrl, MV_U8 *pDesc) +{ + return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); +} + +/* Function prototypes */ +MV_STATUS mvNetaHalInit(MV_NETA_HAL_DATA *halData); + +MV_STATUS mvNetaWinInit(MV_U32 port, MV_UNIT_WIN_INFO *addrWinMap); +MV_STATUS mvNetaWinWrite(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin); +MV_STATUS mvNetaWinRead(MV_U32 port, MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin); +MV_STATUS mvNetaWinEnable(MV_U32 port, MV_U32 winNum, MV_BOOL enable); + +int mvNetaAccMode(void); +MV_STATUS mvNetaMemMapGet(MV_ULONG physAddr, MV_U8 *pTarget, MV_U8 *pAttr); + +void *mvNetaPortInit(int port, void *osHandle); +MV_NETA_TXQ_CTRL *mvNetaTxqInit(int port, int txp, int queue, int descrNum); +MV_NETA_RXQ_CTRL *mvNetaRxqInit(int port, int queue, int descrNum); + +void mvNetaRxReset(int port); +void mvNetaTxpReset(int port, int txp); + +MV_STATUS mvNetaPortDisable(int port); +MV_STATUS mvNetaPortEnable(int port); +MV_STATUS mvNetaPortUp(int port); +MV_STATUS mvNetaPortDown(int port); + +MV_BOOL mvNetaLinkIsUp(int port); +MV_STATUS mvNetaLinkStatus(int port, MV_ETH_PORT_STATUS *pStatus); +MV_STATUS mvNetaDefaultsSet(int port); +MV_STATUS mvNetaRxUnicastPromiscSet(int port, MV_BOOL isPromisc); +MV_STATUS mvNetaForceLinkModeSet(int portNo, MV_BOOL force_link_pass, MV_BOOL force_link_fail); +MV_STATUS mvNetaSpeedDuplexSet(int portNo, MV_ETH_PORT_SPEED speed, MV_ETH_PORT_DUPLEX duplex); + +void mvNetaSetOtherMcastTable(int portNo, int queue); +void mvNetaSetUcastTable(int port, int queue); +void mvNetaSetSpecialMcastTable(int portNo, int queue); + +MV_STATUS mvNetaMcastAddrSet(int port, MV_U8 *pAddr, int queue); +MV_STATUS mvNetaMacAddrGet(int portNo, unsigned char *pAddr); + +void mvNetaPhyAddrSet(int port, int phyAddr); +int mvNetaPhyAddrGet(int port); + +void mvNetaPortPowerDown(int port); +void mvNetaPortPowerUp(int port); + +/* Interrupt Coalesting functions */ +MV_STATUS mvNetaRxTimeCoalSet(int port, MV_U32 uSec); +MV_STATUS mvNetaRxPktsCoalSet(int port, int rxq, MV_U32 pkts); +MV_STATUS mvNetaTxDonePktsCoalSet(int port, int txp, int txq, MV_U32 pkts); +MV_U32 mvNetaRxTimeCoalGet(int port); +MV_U32 mvNetaRxPktsCoalGet(int port, int rxq); +MV_U32 mvNetaTxDonePktsCoalGet(int port, int txp, int txq); + +MV_STATUS mvNetaRxqBufSizeSet(int port, int rxq, int bufSize); +MV_STATUS mvNetaMhSet(int port, MV_NETA_MH_MODE mh); +MV_STATUS mvNetaMaxRxSizeSet(int port, int maxRxSize); +MV_STATUS mvNetaMacAddrSet(int port, unsigned char *pAddr, int queue); + +MV_STATUS mvNetaRxqOffsetSet(int port, int rxq, int offset); +MV_STATUS mvNetaBmPoolBufSizeSet(int port, int pool, int bufsize); +MV_STATUS mvNetaRxqBmEnable(int port, int rxq, int smallPool, int largePool); +MV_STATUS mvNetaRxqBmDisable(int port, int rxq); + +MV_STATUS mvNetaTcpRxq(int port, int rxq); +MV_STATUS mvNetaUdpRxq(int port, int rxq); +MV_STATUS mvNetaArpRxq(int port, int rxq); +MV_STATUS mvNetaBpduRxq(int port, int rxq); + +MV_STATUS mvNetaTxpEjpSet(int port, int txp, int enable); +MV_STATUS mvNetaTxqFixPrioSet(int port, int txp, int txq); +MV_STATUS mvNetaTxqWrrPrioSet(int port, int txp, int txq, int weight); +MV_STATUS mvNetaTxpMaxTxSizeSet(int port, int txp, int maxTxSize); +MV_STATUS mvNetaTxpRateSet(int port, int txp, int bw); +MV_STATUS mvNetaTxqRateSet(int port, int txp, int txq, int bw); +MV_STATUS mvNetaTxpBurstSet(int port, int txp, int burst); +MV_STATUS mvNetaTxqBurstSet(int port, int txp, int txq, int burst); +MV_STATUS mvNetaTxpEjpBurstRateSet(int port, int txp, int txq, int rate); +MV_STATUS mvNetaTxpEjpMaxPktSizeSet(int port, int txp, int type, int size); +MV_STATUS mvNetaTxpEjpTxSpeedSet(int port, int txp, int type, int speed); + +int mvNetaPortCheck(int port); +int mvNetaTxpCheck(int port, int txp); +int mvNetaMaxCheck(int num, int limit); + +void mvNetaMibCountersClear(int port, int txp); +MV_U32 mvNetaMibCounterRead(int port, int txp, unsigned int mibOffset, MV_U32 *pHigh32); + +void mvEthPortRegs(int port); +void mvEthPortUcastShow(int port); +void mvEthPortMcastShow(int port); +void mvNetaPortRegs(int port); +void mvNetaPncRegs(void); +void mvNetaTxpRegs(int port, int txp); +void mvNetaRxqRegs(int port, int rxq); +void mvNetaTxqRegs(int port, int txp, int txq); +void mvNetaPortStatus(int port); +void mvNetaRxqShow(int port, int rxq, int mode); +void mvNetaTxqShow(int port, int txp, int txq, int mode); + +void mvEthTxpWrrRegs(int port, int txp); +void mvEthRegs(int port); +void mvEthPortCounters(int port, int mib); +void mvEthPortRmonCounters(int port, int mib); + +MV_STATUS mvNetaFlowCtrlSet(int port, MV_ETH_PORT_FC flowControl); + +#ifdef MV_ETH_GMAC_NEW +MV_STATUS mvEthGmacRgmiiSet(int port, int enable); +MV_STATUS mvNetaGmacLpiSet(int port, int mode); +void mvNetaGmacRegs(int port); +#endif /* MV_ETH_GMAC_NEW */ + +#ifdef CONFIG_MV_PON +MV_STATUS mvNetaPonRxMibDefault(int mib); +MV_STATUS mvNetaPonRxMibGemPid(int mib, MV_U16 gemPid); +#endif /* CONFIG_MV_PON */ + +#ifdef CONFIG_MV_ETH_HWF +MV_STATUS mvNetaHwfInit(int port); +MV_STATUS mvNetaHwfEnable(int port, int enable); +MV_STATUS mvNetaHwfTxqInit(int p, int txp, int txq); +MV_STATUS mvNetaHwfTxqEnable(int port, int p, int txp, int txq, int enable); +MV_STATUS mvNetaHwfTxqDropSet(int port, int p, int txp, int txq, int thresh, int bits); +void mvNetaHwfRxpRegs(int port); +void mvNetaHwfTxpRegs(int port, int p, int txp); +void mvNetaHwfTxpCntrs(int port, int p, int txp); +#endif /* CONFIG_MV_ETH_HWF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __mvNeta_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaRegs.h u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/gbe/mvNetaRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/gbe/mvNetaRegs.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,977 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __mvNetaRegs_h__ +#define __mvNetaRegs_h__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvSysEthConfig.h" + +#define NETA_REG_BASE(port) MV_ETH_REGS_BASE(port) + +/************************** NETA PNC Registers ******************************/ + +#define MV_PNC_LOOP_CTRL_REG (MV_PNC_REG_BASE + 0x00) +#define MV_PNC_TCAM_CTRL_REG (MV_PNC_REG_BASE + 0x04) +#define MV_PNC_INIT_OFFS_REG (MV_PNC_REG_BASE + 0x08) +#define MV_PNC_INIT_LOOKUP_REG (MV_PNC_REG_BASE + 0x0C) +#define MV_PNC_CAUSE_REG (MV_PNC_REG_BASE + 0x10) +#define MV_PNC_MASK_REG (MV_PNC_REG_BASE + 0x14) +#define MV_PNC_HIT_SEQ0_REG (MV_PNC_REG_BASE + 0x18) +#define MV_PNC_HIT_SEQ1_REG (MV_PNC_REG_BASE + 0x1C) +#define MV_PNC_HIT_SEQ2_REG (MV_PNC_REG_BASE + 0x20) +#define MV_PNC_XBAR_RET_REG (MV_PNC_REG_BASE + 0x24) + +/************************** NETA TX Registers ******************************/ + +#ifdef CONFIG_MV_PON +#define NETA_TX_REG_BASE(p, txp) (MV_PON_PORT(p) ? \ + (MV_PON_REG_BASE + 0x4000 + ((txp) >> 1) * 0x2000 + ((txp) & 0x1) * 0x400) : \ + (NETA_REG_BASE(p) + 0x2400)) +#else +#define NETA_TX_REG_BASE(p, txp) (NETA_REG_BASE(p) + 0x2400) +#endif /* CONFIG_MV_PON */ + +/************************** NETA RX Registers ******************************/ + +/* PxRXyC: Port RX queues Configuration Register */ +#define NETA_RXQ_CONFIG_REG(p, q) (NETA_REG_BASE(p) + 0x1400 + ((q) << 2)) + +#define NETA_RXQ_HW_BUF_ALLOC_BIT 0 +#define NETA_RXQ_HW_BUF_ALLOC_MASK (1 << NETA_RXQ_HW_BUF_ALLOC_BIT) + +#define NETA_RXQ_SHORT_POOL_ID_OFFS 4 +#define NETA_RXQ_SHORT_POOL_ID_MASK (0x3 << NETA_RXQ_SHORT_POOL_ID_OFFS) + +#define NETA_RXQ_LONG_POOL_ID_OFFS 6 +#define NETA_RXQ_LONG_POOL_ID_MASK (0x3 << NETA_RXQ_LONG_POOL_ID_OFFS) + +#define NETA_RXQ_PACKET_OFFSET_OFFS 8 +#define NETA_RXQ_PACKET_OFFSET_ALL_MASK (0xF << NETA_RXQ_PACKET_OFFSET_OFFS) +#define NETA_RXQ_PACKET_OFFSET_MASK(offs) ((offs) << NETA_RXQ_PACKET_OFFSET_OFFS) + + +#define NETA_RXQ_INTR_ENABLE_BIT 15 +#define NETA_RXQ_INTR_ENABLE_MASK (0x1 << NETA_RXQ_INTR_ENABLE_BIT) + +/* ????? What about PREFETCH commands 1, 2, 3 */ +#define NETA_RXQ_PREFETCH_MODE_BIT 16 +#define NETA_RXQ_PREFETCH_PNC (0 << NETA_RXQ_PREFETCH_MODE_BIT) +#define NETA_RXQ_PREFETCH_CMD_0 (1 << NETA_RXQ_PREFETCH_MODE_BIT) +/*-------------------------------------------------------------------------------*/ + +#define NETA_RXQ_SNOOP_REG(p, q) (NETA_REG_BASE(p) + 0x1420 + ((q) << 2)) + +#define NETA_RXQ_SNOOP_BYTES_OFFS 0 +#define NETA_RXQ_SNOOP_BYTES_MASK (0x3FFF << NETA_RXQ_SNOOP_BYTES_OFFS) + +#define NETA_RXQ_L2_DEPOSIT_BYTES_OFFS 16 +#define NETA_RXQ_L2_DEPOSIT_BYTES_MASK (0x3FFF << NETA_RXQ_L2_DEPOSIT_BYTES_OFFS) + + +#define NETA_RXQ_PREFETCH_01_REG(p, q) (NETA_REG_BASE(p) + 0x1440 + ((q) << 2)) +#define NETA_RXQ_PREFETCH_23_REG(p, q) (NETA_REG_BASE(p) + 0x1460 + ((q) << 2)) + +#define NETA_RXQ_PREFETCH_CMD_OFFS(cmd) (((cmd) & 1) ? 16 : 0) +#define NETA_RXQ_PREFETCH_CMD_MASK(cmd) (0xFFFF << NETA_RXQ_PREFETCH_CMD_OFFS(cmd)) +/*-------------------------------------------------------------------------------*/ + +#define NETA_RXQ_BASE_ADDR_REG(p, q) (NETA_REG_BASE(p) + 0x1480 + ((q) << 2)) +#define NETA_RXQ_SIZE_REG(p, q) (NETA_REG_BASE(p) + 0x14A0 + ((q) << 2)) + +#define NETA_RXQ_DESC_NUM_OFFS 0 +#define NETA_RXQ_DESC_NUM_MASK (0x3FFF << NETA_RXQ_DESC_NUM_OFFS) + +#define NETA_RXQ_BUF_SIZE_OFFS 19 +#define NETA_RXQ_BUF_SIZE_MASK (0x1FFF << NETA_RXQ_BUF_SIZE_OFFS) +/*-------------------------------------------------------------------------------*/ + +#define NETA_RXQ_THRESHOLD_REG(p, q) (NETA_REG_BASE(p) + 0x14C0 + ((q) << 2)) +#define NETA_RXQ_STATUS_REG(p, q) (NETA_REG_BASE(p) + 0x14E0 + ((q) << 2)) + +#define NETA_RXQ_OCCUPIED_DESC_OFFS 0 +#define NETA_RXQ_OCCUPIED_DESC_ALL_MASK (0x3FFF << NETA_RXQ_OCCUPIED_DESC_OFFS) +#define NETA_RXQ_OCCUPIED_DESC_MASK(val) ((val) << NETA_RXQ_OCCUPIED_DESC_OFFS) + +#define NETA_RXQ_NON_OCCUPIED_DESC_OFFS 16 +#define NETA_RXQ_NON_OCCUPIED_DESC_ALL_MASK (0x3FFF << NETA_RXQ_NON_OCCUPIED_DESC_OFFS) +#define NETA_RXQ_NON_OCCUPIED_DESC_MASK(v) ((v) << NETA_RXQ_NON_OCCUPIED_DESC_OFFS) +/*-------------------------------------------------------------------------------*/ + +#define NETA_RXQ_STATUS_UPDATE_REG(p, q) (NETA_REG_BASE(p) + 0x1500 + ((q) << 2)) + +/* Decrement OCCUPIED Descriptors counter */ +#define NETA_RXQ_DEC_OCCUPIED_OFFS 0 +#define NETA_RXQ_DEC_OCCUPIED_MASK (0xFF << NETA_RXQ_DEC_OCCUPIED_OFFS) + +/* Increment NON_OCCUPIED Descriptors counter */ +#define NETA_RXQ_ADD_NON_OCCUPIED_OFFS 16 +#define NETA_RXQ_ADD_NON_OCCUPIED_MASK (0xFF << NETA_RXQ_ADD_NON_OCCUPIED_OFFS) +/*-------------------------------------------------------------------------------*/ + +/* Port RX queues Descriptors Index Register (a register per RX Queue) */ +#define NETA_RXQ_INDEX_REG(p, q) (NETA_REG_BASE(p) + 0x1520 + ((q) << 2)) + +#define NETA_RXQ_NEXT_DESC_INDEX_OFFS 0 +#define NETA_RXQ_NEXT_DESC_INDEX_MASK (0x3FFF << NETA_RXQ_NEXT_DESC_INDEX_OFFS) +/*-------------------------------------------------------------------------------*/ + +/* Port Pool-N Buffer Size Register - 8 bytes alignment */ +#define NETA_POOL_BUF_SIZE_REG(p, pool) (NETA_REG_BASE(p) + 0x1700 + ((pool) << 2)) +#define NETA_POOL_BUF_SIZE_ALIGN 8 +#define NETA_POOL_BUF_SIZE_OFFS 3 +#define NETA_POOL_BUF_SIZE_MASK (0x1FFF << NETA_POOL_BUF_SIZE_OFFS) +/*-------------------------------------------------------------------------------*/ + +/* Port RX Flow Control register */ +#define NETA_FLOW_CONTROL_REG(p) (NETA_REG_BASE(p) + 0x1710) + +#define NETA_PRIO_PAUSE_PKT_GEN_BIT 0 +#define NETA_PRIO_PAUSE_PKT_GEN_GIGA (0 << NETA_PRIO_PAUSE_PKT_GEN_BIT) +#define NETA_PRIO_PAUSE_PKT_GEN_CPU (1 << NETA_PRIO_PAUSE_PKT_GEN_BIT) + +#define NETA_PRIO_TX_PAUSE_BIT 1 +#define NETA_PRIO_TX_PAUSE_GIGA (0 << NETA_PRIO_TX_PAUSE_BIT) +#define NETA_PRIO_TX_PAUSE_CPU (1 << NETA_PRIO_TX_PAUSE_BIT) +/*-------------------------------------------------------------------------------*/ + +/* Port TX pause control register */ +#define NETA_TX_PAUSE_REG(p) (NETA_REG_BASE(p) + 0x1714) + +/* ????? One register for all TXQs - problem for multi-core */ +#define NETA_TXQ_PAUSE_ENABLE_OFFS 0 +#define NETA_TXQ_PAUSE_ENABLE_ALL_MASK (0xFF << NETA_TXQ_PAUSE_ENABLE_OFFS) +#define NETA_TXQ_PAUSE_ENABLE_MASK(q) ((1 << q) << NETA_TXQ_PAUSE_ENABLE_OFFS) +/*-------------------------------------------------------------------------------*/ + +/* Port Flow Control generation control register */ +#define NETA_FC_GEN_REG(p) (NETA_REG_BASE(p) + 0x1718) + +#define NETA_PAUSE_PKT_GEN_DATA_BIT 0 +#define NETA_PAUSE_PKT_GEN_DATA_OFF (0 << NETA_PAUSE_PKT_GEN_DATA_BIT) +#define NETA_PAUSE_PKT_GEN_DATA_ON (1 << NETA_PAUSE_PKT_GEN_DATA_BIT) + +#define NETA_TXQ_PAUSE_PKT_GEN_OFFS 4 +#define NETA_TXQ_PAUSE_PKT_GEN_ALL_MASK (0x7 << NETA_TXQ_PAUSE_PKT_GEN_OFFS) +#define NETA_TXQ_PAUSE_PKT_GEN_MASK(q) ((1 << q) << NETA_TXQ_PAUSE_PKT_GEN_OFFS) + +#define NETA_RX_DEBUG_REG(p) (NETA_REG_BASE(p) + 0x17f0) +/* RXQ memory dump: offset = 1c00 - 1cbc */ + +/* PxRXINIT: Port RX Initialization Register */ +#define NETA_PORT_RX_RESET_REG(p) (NETA_REG_BASE(p) + 0x1cc0) + +#define NETA_PORT_RX_DMA_RESET_BIT 0 +#define NETA_PORT_RX_DMA_RESET_MASK (1 << NETA_PORT_RX_DMA_RESET_BIT) +/*-------------------------------------------------------------------------------*/ + + +#define NETA_HWF_RX_CTRL_REG(p) (NETA_REG_BASE(p) + 0x1d00) + +#define NETA_COLOR_SRC_SEL_BIT 0 +#define NETA_COLOR_SRC_SEL_MASK (1 << NETA_COLOR_SRC_SEL_BIT) + +#define NETA_GEM_PID_SRC_SEL_OFFS 4 +#define NETA_GEM_PID_SRC_SEL_MASK (7 << NETA_GEM_PID_SRC_SEL_OFFS) +#define NETA_GEM_PID_SRC_GPON_HDR (0 << NETA_GEM_PID_SRC_SEL_OFFS) +#define NETA_GEM_PID_SRC_EXT_DSA_TAG (1 << NETA_GEM_PID_SRC_SEL_OFFS) +#define NETA_GEM_PID_SRC_FLOW_ID (2 << NETA_GEM_PID_SRC_SEL_OFFS) +#define NETA_GEM_PID_SRC_DSA_TAG (3 << NETA_GEM_PID_SRC_SEL_OFFS) +#define NETA_GEM_PID_SRC_ZERO (4 << NETA_GEM_PID_SRC_SEL_OFFS) + +#define NETA_TXQ_SRC_SEL_BIT 8 +#define NETA_TXQ_SRC_SEL_MASK (1 << NETA_TXQ_SRC_SEL_BIT) +#define NETA_TXQ_SRC_FLOW_ID (0 << NETA_TXQ_SRC_SEL_BIT) +#define NETA_TXQ_SRC_RES_INFO (1 << NETA_TXQ_SRC_SEL_BIT) + +#ifdef MV_ETH_PMT_NEW + +#define NETA_MH_SEL_OFFS 12 +#define NETA_MH_SEL_MASK (0xF << NETA_MH_SEL_OFFS) +#define NETA_MH_DONT_CHANGE (0 << NETA_MH_SEL_OFFS) + +#define NETA_MH_SRC_SEL_BIT 16 +#define NETA_MH_SRC_SEL_MASK (1 << NETA_MH_SRC_SEL_BIT) + +#define NETA_HWF_ENABLE_BIT 17 +#define NETA_HWF_ENABLE_MASK (1 << NETA_HWF_ENABLE_BIT) + +#else + +#define NETA_MH_SEL_OFFS 12 +#define NETA_MH_SEL_MASK (0x7 << NETA_MH_SEL_OFFS) +#define NETA_MH_DONT_CHANGE (0 << NETA_MH_SEL_OFFS) +#define NETA_MH_REPLACE_GPON_HDR (1 << NETA_MH_SEL_OFFS) +#define NETA_MH_REPLACE_MH_REG(r) (((r) + 1) << NETA_MH_SEL_OFFS) + +#define NETA_HWF_ENABLE_BIT 16 +#define NETA_HWF_ENABLE_MASK (1 << NETA_HWF_ENABLE_BIT) + +#endif /* MV_ETH_PMT_NEW */ + +#define NETA_HWF_SHORT_POOL_OFFS 20 +#define NETA_HWF_SHORT_POOL_MASK (3 << NETA_HWF_SHORT_POOL_OFFS) +#define NETA_HWF_SHORT_POOL_ID(pool) ((pool) << NETA_HWF_SHORT_POOL_OFFS) + +#define NETA_HWF_LONG_POOL_OFFS 22 +#define NETA_HWF_LONG_POOL_MASK (3 << NETA_HWF_LONG_POOL_OFFS) +#define NETA_HWF_LONG_POOL_ID(pool) ((pool) << NETA_HWF_LONG_POOL_OFFS) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_RX_THRESH_REG(p) (NETA_REG_BASE(p) + 0x1d04) + +#ifdef MV_ETH_PMT_NEW + +#define NETA_HWF_RX_FIFO_WORDS_OFFS 0 +#define NETA_HWF_RX_FIFO_WORDS_MASK (0x3FF << NETA_HWF_RX_FIFO_WORDS_OFFS) + +#define NETA_HWF_RX_FIFO_PKTS_OFFS 16 +#define NETA_HWF_RX_FIFO_PKTS_MASK (0x7F << NETA_HWF_RX_FIFO_PKTS_OFFS) + +#else + +#define NETA_HWF_RX_FIFO_WORDS_OFFS 0 +#define NETA_HWF_RX_FIFO_WORDS_MASK (0xFF << NETA_HWF_RX_FIFO_WORDS_OFFS) + +#define NETA_HWF_RX_FIFO_PKTS_OFFS 8 +#define NETA_HWF_RX_FIFO_PKTS_MASK (0x1F << NETA_HWF_RX_FIFO_PKTS_OFFS) + +#endif /* MV_ETH_PMT_NEW */ +/*-----------------------------------------------------------------------------------*/ + + +#define NETA_HWF_TXP_CFG_REG(p, txp) (NETA_REG_BASE(p) + 0x1d10 + ((txp) >> 1) * 4) + +#define NETA_TXP_BASE_ADDR_OFFS(txp) (((txp) & 0x1) ? 18 : 2) +#define NETA_TXP_BASE_ADDR_MASK(txp) (0xFFFF << NETA_TXP_BASE_ADDR_OFFS(txp)) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_TX_PTR_REG(p) (NETA_REG_BASE(p) + 0x1d30) + +#define NETA_HWF_TX_PORT_OFFS 11 +#define NETA_HWF_TX_PORT_ALL_MASK (0xF << NETA_HWF_TX_PORT_OFFS) +#define NETA_HWF_TX_PORT_MASK(txp) ((txp) << NETA_HWF_TX_PORT_OFFS) + +#define NETA_HWF_TXQ_OFFS 8 +#define NETA_HWF_TXQ_ALL_MASK (0x7 << NETA_HWF_TXQ_OFFS) +#define NETA_HWF_TXQ_MASK(txq) ((txq) << NETA_HWF_TXQ_OFFS) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_DROP_TH_REG(p) (NETA_REG_BASE(p) + 0x1d40) + +#define NETA_YELLOW_DROP_THRESH_OFFS 0 +#define NETA_YELLOW_DROP_THRESH_MASK (0x3fff << NETA_YELLOW_DROP_THRESH_OFFS) + +#define NETA_YELLOW_DROP_RND_GEN_OFFS 16 +#define NETA_YELLOW_DROP_RND_GEN_MASK (0xf << NETA_YELLOW_DROP_RND_GEN_OFFS) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_TXQ_BASE_REG(p) (NETA_REG_BASE(p) + 0x1d44) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_TXQ_SIZE_REG(p) (NETA_REG_BASE(p) + 0x1d48) + +#define NETA_HWF_TXQ_SIZE_OFFS 0 +#define NETA_HWF_TXQ_SIZE_MASK (0x3fff << NETA_HWF_TXQ_SIZE_OFFS) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_TXQ_ENABLE_REG(p) (NETA_REG_BASE(p) + 0x1d4c) + +#define NETA_HWF_TXQ_ENABLE_BIT 0 +#define NETA_HWF_TXQ_ENABLE_MASK (1 << NETA_HWF_TXQ_ENABLE_BIT) +/*-----------------------------------------------------------------------------------*/ + +#define NETA_HWF_ACCEPTED_CNTR(p) (NETA_REG_BASE(p) + 0x1d50) +#define NETA_HWF_YELLOW_DROP_CNTR(p) (NETA_REG_BASE(p) + 0x1d54) +#define NETA_HWF_GREEN_DROP_CNTR(p) (NETA_REG_BASE(p) + 0x1d58) +#define NETA_HWF_THRESH_DROP_CNTR(p) (NETA_REG_BASE(p) + 0x1d5c) + + +/**************************** NETA General Registers ***********************/ + +/* Cross Bar registers per Giga Unit */ +#define NETA_MBUS_RETRY_REG(p) (NETA_REG_BASE((p) & ~0x1) + 0x2010) + +#define NETA_MBUS_RETRY_DISABLE_BIT 16 +#define NETA_MBUS_RETRY_DISABLE_MASK (1 << NETA_MBUS_RETRY_DISABLE_BIT) + +#define NETA_MBUS_RETRY_CYCLES_OFFS 0 +#define NETA_MBUS_RETRY_CYCLES_MASK (0xFF << NETA_MBUS_RETRY_CYCLES_OFFS) +#define NETA_MBUS_RETRY_CYCLES(val) ((val) << NETA_MBUS_RETRY_CYCLES_OFFS) +/*-------------------------------------------------------------------------------*/ + +#define NETA_MBUS_ARBITER_REG(p) (NETA_REG_BASE((p) & ~0x1) + 0x20C0) +/*-------------------------------------------------------------------------------*/ + +/* PACC - Port Acceleration Register */ +#define NETA_ACC_MODE_REG(p) (NETA_REG_BASE(p) + 0x2500) + +#define NETA_ACC_MODE_OFFS 0 +#define NETA_ACC_MODE_ALL_MASK (7 << NETA_ACC_MODE_OFFS) +#define NETA_ACC_MODE_MASK(mode) ((mode) << NETA_ACC_MODE_OFFS) +#define NETA_ACC_MODE_LEGACY 0 +#define NETA_ACC_MODE_EXT 1 +#define NETA_ACC_MODE_EXT_BMU 2 +#define NETA_ACC_MODE_EXT_PNC 3 +#define NETA_ACC_MODE_EXT_PNC_BMU 4 +/*-------------------------------------------------------------------------------*/ + +#define NETA_BM_ADDR_REG(p) (NETA_REG_BASE(p) + 0x2504) + +#define NETA_CPU_MAP_REG(p, cpu) (NETA_REG_BASE(p) + 0x2540 + ((cpu) << 2)) + +#define NETA_CPU_RXQ_ACCESS_OFFS 0 +#define NETA_CPU_RXQ_ACCESS_ALL_MASK (0xFF << NETA_CPU_RXQ_ACCESS_OFFS) +#define NETA_CPU_RXQ_ACCESS_MASK(q) ((1 << NETA_CPU_RXQ_ACCESS_OFFS + (q)) + +#define NETA_CPU_TXQ_ACCESS_OFFS 8 +#define NETA_CPU_TXQ_ACCESS_ALL_MASK (0xFF << NETA_CPU_TXQ_ACCESS_OFFS) +#define NETA_CPU_TXQ_ACCESS_MASK(q) ((1 << NETA_CPU_TXQ_ACCESS_OFFS + (q)) + +/* Interrupt coalescing mechanism */ +#define NETA_RX_INTR_TIME_COAL_REG(p) (NETA_REG_BASE(p) + 0x2580) + +/* Exception Interrupt Port/Queue Cause register */ +#define NETA_INTR_NEW_CAUSE_REG(p) (NETA_REG_BASE(p) + 0x25A0) +#define NETA_INTR_NEW_MASK_REG(p) (NETA_REG_BASE(p) + 0x25A4) + +#ifdef CONFIG_MV_PON +# define GPON_CAUSE_TXQ_SENT_SUM_OFFS 0 +# define GPON_CAUSE_TXQ_SENT_SUM_MASK (3 << GPON_CAUSE_TXQ_SENT_SUM_OFFS) +#endif /* CONFIG_MV_PON */ + +#define NETA_CAUSE_TXQ_SENT_DESC_OFFS 0 +#define NETA_CAUSE_TXQ_SENT_DESC_BIT(q) (NETA_CAUSE_TXQ_SENT_DESC_OFFS + (q)) +#define NETA_CAUSE_TXQ_SENT_DESC_ALL_MASK (0xFF << NETA_CAUSE_TXQ_SENT_DESC_OFFS) +#define NETA_CAUSE_TXQ_SENT_DESC_MASK(q) (1 << (NETA_CAUSE_TXQ_SENT_DESC_BIT(q))) + +#define NETA_CAUSE_RXQ_OCCUP_DESC_OFFS 8 +#define NETA_CAUSE_RXQ_OCCUP_DESC_BIT(q) (NETA_CAUSE_RXQ_OCCUP_DESC_OFFS + (q)) +#define NETA_CAUSE_RXQ_OCCUP_DESC_ALL_MASK (0xFF << NETA_CAUSE_RXQ_OCCUP_DESC_OFFS) +#define NETA_CAUSE_RXQ_OCCUP_DESC_MASK(q) (1 << (NETA_CAUSE_RXQ_OCCUP_DESC_BIT(q))) + +#define NETA_CAUSE_RXQ_FREE_DESC_OFFS 16 +#define NETA_CAUSE_RXQ_FREE_DESC_BIT(q) (NETA_CAUSE_RXQ_FREE_DESC_OFFS + (q)) +#define NETA_CAUSE_RXQ_FREE_DESC_MASK(q) (1 << (NETA_CAUSE_RXQ_FREE_DESC_BIT(q))) + +#define NETA_CAUSE_OLD_REG_SUM_BIT 29 +#define NETA_CAUSE_OLD_REG_SUM_MASK (1 << NETA_CAUSE_OLD_REG_SUM_BIT) + +#define NETA_CAUSE_TX_ERR_SUM_BIT 30 +#define NETA_CAUSE_TX_ERR_SUM_MASK (1 << NETA_CAUSE_TX_ERR_SUM_BIT) + +#define NETA_CAUSE_MISC_SUM_BIT 31 +#define NETA_CAUSE_MISC_SUM_MASK (1 << NETA_CAUSE_MISC_SUM_BIT) +/*-------------------------------------------------------------------------------*/ + +/* Data Path Port/Queue Cause Register */ +#define NETA_INTR_OLD_CAUSE_REG(p) (NETA_REG_BASE(p) + 0x25A8) +#define NETA_INTR_OLD_MASK_REG(p) (NETA_REG_BASE(p) + 0x25AC) + +#ifdef CONFIG_MV_PON +# define GPON_CAUSE_TXQ_BUF_OFFS 0 +# define GPON_CAUSE_TXQ_BUF_MASK (3 << GPON_CAUSE_TXQ_BUF_OFFS) +#endif /* CONFIG_MV_PON */ + +#define NETA_CAUSE_TXQ_BUF_OFFS 0 +#define NETA_CAUSE_TXQ_BUF_BIT(q) (NETA_CAUSE_TXQ_BUF_OFFS + (q)) +#define NETA_CAUSE_TXQ_BUF_ALL_MASK (0xFF << NETA_CAUSE_TXQ_BUF_OFFS) +#define NETA_CAUSE_TXQ_BUF_MASK(q) (1 << (NETA_CAUSE_TXQ_BUF_BIT(q))) + +#define NETA_CAUSE_RXQ_PKT_OFFS 8 +#define NETA_CAUSE_RXQ_PKT_BIT(q) (NETA_CAUSE_RXQ_PKT_OFFS + (q)) +#define NETA_CAUSE_RXQ_PKT_ALL_MASK (0xFF << NETA_CAUSE_RXQ_PKT_OFFS) +#define NETA_CAUSE_RXQ_PKT_MASK(q) (1 << (NETA_CAUSE_RXQ_PKT_BIT(q))) + +#define NETA_CAUSE_RXQ_ERROR_OFFS 16 +#define NETA_CAUSE_RXQ_ERROR_BIT(q) (NETA_CAUSE_RXQ_ERROR_OFFS + (q)) +#define NETA_CAUSE_RXQ_ERROR_ALL_MASK (0xFF << NETA_CAUSE_RXQ_ERROR_OFFS) +#define NETA_CAUSE_RXQ_ERROR_MASK(q) (1 << (NETA_CAUSE_RXQ_ERROR_BIT(q))) + +#define NETA_CAUSE_NEW_REG_SUM_BIT 29 +#define NETA_CAUSE_NEW_REG_SUM_MASK (1 << NETA_CAUSE_NEW_REG_SUM_BIT) +/*-------------------------------------------------------------------------------*/ + +/* Misc Port Cause Register */ +#define NETA_INTR_MISC_CAUSE_REG(p) (NETA_REG_BASE(p) + 0x25B0) +#define NETA_INTR_MISC_MASK_REG(p) (NETA_REG_BASE(p) + 0x25B4) + +#define NETA_CAUSE_PHY_STATUS_CHANGE_BIT 0 +#define NETA_CAUSE_PHY_STATUS_CHANGE_MASK (1 << NETA_CAUSE_PHY_STATUS_CHANGE_BIT) + +#define NETA_CAUSE_LINK_CHANGE_BIT 1 +#define NETA_CAUSE_LINK_CHANGE_MASK (1 << NETA_CAUSE_LINK_CHANGE_BIT) + +#define NETA_CAUSE_PTP_BIT 4 + +#define NETA_CAUSE_INTERNAL_ADDR_ERR_BIT 7 +#define NETA_CAUSE_RX_OVERRUN_BIT 8 +#define NETA_CAUSE_RX_CRC_ERROR_BIT 9 +#define NETA_CAUSE_RX_LARGE_PKT_BIT 10 +#define NETA_CAUSE_TX_UNDERUN_BIT 11 +#define NETA_CAUSE_PRBS_ERR_BIT 12 +#define NETA_CAUSE_PSC_SYNC_CHANGE_BIT 13 +#define NETA_CAUSE_SERDES_SYNC_ERR_BIT 14 + +#define NETA_CAUSE_BMU_ALLOC_ERR_OFFS 16 +#define NETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << NETA_CAUSE_BMU_ALLOC_ERR_OFFS) +#define NETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (NETA_CAUSE_BMU_ALLOC_ERR_OFFS + (pool))) + +#define NETA_CAUSE_TXQ_ERROR_OFFS 24 +#define NETA_CAUSE_TXQ_ERROR_BIT(q) (NETA_CAUSE_TXQ_ERROR_OFFS + (q)) +#define NETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << NETA_CAUSE_TXQ_ERROR_OFFS) +#define NETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (NETA_CAUSE_TXQ_ERROR_BIT(q))) + +#ifdef CONFIG_MV_PON +# define GPON_CAUSE_TXQ_ERROR_OFFS 24 +# define GPON_CAUSE_TXQ_ERROR_MASK (0x3 << GPON_CAUSE_TXQ_ERROR_OFFS) +#endif /* CONFIG_MV_PON */ +/*-------------------------------------------------------------------------------*/ + +/* one register for all queues - problem for Multi-Core */ +#define NETA_INTR_ENABLE_REG(p) (NETA_REG_BASE(p) + 0x25B8) + +#define NETA_RXQ_PKT_INTR_ENABLE_OFFS 0 +#define NETA_RXQ_PKT_INTR_ENABLE_ALL_MASK (0xFF << NETA_RXQ_PKT_INTR_ENABLE_OFFS) +#define NETA_RXQ_PKT_INTR_ENABLE_MASK(q) ((1 << NETA_RXQ_PKT_INTR_ENABLE_OFFS + (q)) + +#define NETA_TXQ_PKT_INTR_ENABLE_OFFS 8 +#define NETA_TXQ_PKT_INTR_ENABLE_ALL_MASK (0xFF << NETA_TXQ_PKT_INTR_ENABLE_OFFS) +#define NETA_TXQ_PKT_INTR_ENABLE_MASK(q) ((1 << NETA_TXQ_PKT_INTR_ENABLE_OFFS + (q)) +/*-------------------------------------------------------------------------------*/ + +#define NETA_VERSION_REG(p) (NETA_REG_BASE(p) + 0x25BC) + +#define NETA_VERSION_OFFS 0 +#define NETA_VERSION_MASK (0xFF << NETA_VERSION_OFFS) + +/* Serdes registres: 0x72E00-0x72FFC */ + +#ifdef CONFIG_MV_PON +/* Extra registers for GPON port only */ +# define GPON_TXQ_INTR_ENABLE_REG(txq) (MV_PON_REG_BASE + 0x0480 + (txq / 32) * 4) +# define GPON_TXQ_INTR_NEW_CAUSE_REG(txq) (MV_PON_REG_BASE + 0x0500 + (txq / 32) * 8) +# define GPON_TXQ_INTR_NEW_MASK_REG(txq) (MV_PON_REG_BASE + 0x0504 + (txq / 32) * 8) +# define GPON_TXQ_INTR_OLD_CAUSE_REG(txq) (MV_PON_REG_BASE + 0x0540 + (txq / 32) * 8) +# define GPON_TXQ_INTR_OLD_MASK_REG(txq) (MV_PON_REG_BASE + 0x0544 + (txq / 32) * 8) +# define GPON_TXQ_INTR_ERR_CAUSE_REG(txq) (MV_PON_REG_BASE + 0x0580 + (txq / 32) * 8) +# define GPON_TXQ_INTR_ERR_MASK_REG(txq) (MV_PON_REG_BASE + 0x0584 + (txq / 32) * 8) +#endif /* CONFIG_MV_PON */ +/*-------------------------------------------------------------------------------*/ + +/******************************** NETA TX Registers *****************************/ + +#define NETA_TXQ_BASE_ADDR_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1800 + ((q) << 2)) + +#define NETA_TXQ_SIZE_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1820 + ((q) << 2)) + +#define NETA_TXQ_DESC_NUM_OFFS 0 +#define NETA_TXQ_DESC_NUM_ALL_MASK (0x3FFF << NETA_TXQ_DESC_NUM_OFFS) +#define NETA_TXQ_DESC_NUM_MASK(size) ((size) << NETA_TXQ_DESC_NUM_OFFS) + +#define NETA_TXQ_SENT_DESC_TRESH_OFFS 16 +#define NETA_TXQ_SENT_DESC_TRESH_ALL_MASK (0x3FFF << NETA_TXQ_SENT_DESC_TRESH_OFFS) +#define NETA_TXQ_SENT_DESC_TRESH_MASK(coal) ((coal) << NETA_TXQ_SENT_DESC_TRESH_OFFS) + +#define NETA_TXQ_STATUS_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1840 + ((q) << 2)) + +#define NETA_TXQ_PENDING_DESC_OFFS 0 +#define NETA_TXQ_PENDING_DESC_MASK (0x3FFF << NETA_TXQ_PENDING_DESC_OFFS) + +#define NETA_TXQ_SENT_DESC_OFFS 16 +#define NETA_TXQ_SENT_DESC_MASK (0x3FFF << NETA_TXQ_SENT_DESC_OFFS) + +#define NETA_TXQ_UPDATE_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1860 + ((q) << 2)) + +#define NETA_TXQ_ADD_PENDING_OFFS 0 +#define NETA_TXQ_ADD_PENDING_MASK (0xFF << NETA_TXQ_ADD_PENDING_OFFS) + +#define NETA_TXQ_DEC_SENT_OFFS 16 +#define NETA_TXQ_DEC_SENT_MASK (0xFF << NETA_TXQ_DEC_SENT_OFFS) + +#define NETA_TXQ_INDEX_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1880 + ((q) << 2)) + +#define NETA_TXQ_NEXT_DESC_INDEX_OFFS 0 +#define NETA_TXQ_NEXT_DESC_INDEX_MASK (0x3FFF << NETA_TXQ_NEXT_DESC_INDEX_OFFS) + +#define NETA_TXQ_SENT_DESC_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x18A0 + ((q) << 2)) +/* Use NETA_TXQ_SENT_DESC_OFFS and NETA_TXQ_SENT_DESC_MASK */ + +#ifdef MV_ETH_PMT_NEW +#define NETA_TX_BAD_FCS_CNTR_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x18C0) +#define NETA_TX_DROP_CNTR_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x18C4) +#endif /* MV_ETH_PMT_NEW */ + +#define NETA_PORT_TX_RESET_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x18F0) + +#define NETA_PORT_TX_DMA_RESET_BIT 0 +#define NETA_PORT_TX_DMA_RESET_MASK (1 << NETA_PORT_TX_DMA_RESET_BIT) + +#ifdef MV_ETH_PMT_NEW + +#define NETA_TX_ADD_BYTES_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x18FC) +#define NETA_TXQ_BYTES_REG(p, txp, txq) (NETA_TX_REG_BASE((p), (txp)) + 0x1900 + ((txq) << 2)) + +#define NETA_TX_MAX_MH_REGS 15 +#define NETA_TX_MH_REG(p, txp, idx) (NETA_TX_REG_BASE((p), (txp)) + 0x1944 + ((idx) << 2)) + +/*************** Packet Modification Registers *******************/ +#define NETA_TX_PMT_ACCESS_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x1980) +#define NETA_TX_PMT_FIFO_THRESH_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x1984) +#define NETA_TX_PMT_MTU_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x1988) + +#define NETA_TX_PMT_MAX_ETHER_TYPES 4 +#define NETA_TX_PMT_ETHER_TYPE_REG(p, i) (NETA_TX_REG_BASE((p), 0) + 0x1990 + ((i) << 2)) + +#define NETA_TX_PMT_DEF_VLAN_CFG_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19a0) +#define NETA_TX_PMT_DEF_DSA_1_CFG_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19a4) +#define NETA_TX_PMT_DEF_DSA_2_CFG_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19a8) +#define NETA_TX_PMT_DEF_DSA_SRC_DEV_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19ac) + +#define NETA_TX_PMT_TTL_ZERO_FRWD_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19b0) +#define NETA_TX_PMT_TTL_ZERO_CNTR_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19b4) + +#define NETA_TX_PMT_PPPOE_TYPE_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19c0) +#define NETA_TX_PMT_PPPOE_DATA_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19c4) +#define NETA_TX_PMT_PPPOE_LEN_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19c8) +#define NETA_TX_PMT_PPPOE_PROTO_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19cc) + +#define NETA_TX_PMT_CONFIG_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19d0) +#define NETA_TX_PMT_STATUS_1_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19d4) +#define NETA_TX_PMT_STATUS_2_REG(p) (NETA_TX_REG_BASE((p), 0) + 0x19d8) + +#else + +#define NETA_TX_COLOR_ADD_BYTES_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1900) +#define NETA_TX_GREEN_BYTES_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1908) +#define NETA_TX_YELLOW_BYTES_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x190c) + +#define NETA_TX_MAX_MH_REGS 6 +#define NETA_TX_MH_REG(p, txp, idx) (NETA_TX_REG_BASE((p), (txp)) + 0x1910 + ((idx) << 2)) + +#define NETA_TX_DSA_SRC_DEV_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x192C) + +#define NETA_TX_MAX_ETH_TYPE_REGS 4 +#define NETA_TX_ETH_TYPE_REG(p, txp, idx) (NETA_TX_REG_BASE((p), (txp)) + 0x1930 + ((idx) << 2)) + +#define NETA_TX_PMT_SIZE 256 +#define NETA_TX_PMT_W0_MASK 0xFFFF +#define NETA_TX_PMT_W1_MASK 0xFFFFFFFF +#define NETA_TX_PMT_W2_MASK 0x7FFFFFF +#define NETA_TX_PMT_REG(p) (NETA_TX_REG_BASE(p, 0) + 0x1940) +#define NETA_TX_PMT_W0_REG(p) (NETA_TX_REG_BASE(p, 0) + 0x1944) +#define NETA_TX_PMT_W1_REG(p) (NETA_TX_REG_BASE(p, 0) + 0x1948) +#define NETA_TX_PMT_W2_REG(p) (NETA_TX_REG_BASE(p, 0) + 0x194c) + +#endif /* MV_ETH_PMT_NEW */ + +#ifdef MV_ETH_WRR_NEW +/*********************** New TX WRR EJP Registers ********************************/ + +#define NETA_TX_CMD_1_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a00) + +#define NETA_TX_EJP_RESET_BIT 0 +#define NETA_TX_EJP_RESET_MASK (1 << NETA_TX_EJP_RESET_BIT) + +#define NETA_TX_PTP_SYNC_BIT 1 +#define NETA_TX_PTP_SYNC_MASK (1 << NETA_TX_EJP_RESET_BIT) + +#define NETA_TX_EJP_ENABLE_BIT 2 +#define NETA_TX_EJP_ENABLE_MASK (1 << NETA_TX_EJP_ENABLE_BIT) + +#define NETA_TX_LEGACY_WRR_BIT 3 +#define NETA_TX_LEGACY_WRR_MASK (1 << NETA_TX_LEGACY_WRR_BIT) +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmit Queue Fixed Priority Configuration (TQFPC) */ +#define NETA_TX_FIXED_PRIO_CFG_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a04) + +#define NETA_TX_FIXED_PRIO_OFFS 0 +#define NETA_TX_FIXED_PRIO_MASK (0xFF << NETA_TX_FIXED_PRIO_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Basic Refill No of Clocks (BRC) */ +#define NETA_TX_REFILL_PERIOD_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a08) + +#define NETA_TX_REFILL_CLOCKS_OFFS 0 +#define NETA_TX_REFILL_CLOCKS_MIN 16 +#define NETA_TX_REFILL_CLOCKS_MASK (0xFFFF << NETA_TX_REFILL_RATE_CLOCKS_MASK) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Maximum Transmit Unit (PMTU) */ +#define NETA_TXP_MTU_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a0c) + +#define NETA_TXP_MTU_OFFS 0 +#define NETA_TXP_MTU_ALL_MASK (0x3FFFF << NETA_TXP_MTU_OFFS) +#define NETA_TXP_MTU_MASK(mtu) ((mtu) << NETA_TXP_MTU_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Bucket Refill (PRefill) */ +#define NETA_TXP_REFILL_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a10) + +#define NETA_TXP_REFILL_TOKENS_OFFS 0 +#define NETA_TXP_REFILL_TOKENS_MAX 0x7FFFF +#define NETA_TXP_REFILL_TOKENS_ALL_MASK (NETA_TXP_REFILL_TOKENS_MAX << NETA_TXP_REFILL_TOKENS_OFFS) +#define NETA_TXP_REFILL_TOKENS_MASK(val) ((val) << NETA_TXP_REFILL_TOKENS_OFFS) + +#define NETA_TXP_REFILL_PERIOD_OFFS 20 +#define NETA_TXP_REFILL_PERIOD_MAX 0x3FF +#define NETA_TXP_REFILL_PERIOD_ALL_MASK (NETA_TXP_REFILL_PERIOD_MAX << NETA_TXP_REFILL_PERIOD_OFFS) +#define NETA_TXP_REFILL_PERIOD_MASK(val) ((val) << NETA_TXP_REFILL_PERIOD_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Maximum Token Bucket Size (PMTBS) */ +#define NETA_TXP_TOKEN_SIZE_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a14) +#define NETA_TXP_TOKEN_SIZE_MAX 0xFFFFFFFF +/*-----------------------------------------------------------------------------------------------*/ + +/* Port Token Bucket Counter (PMTBS) */ +#define NETA_TXP_TOKEN_CNTR_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1a18) +#define NETA_TXP_TOKEN_CNTR_MAX 0xFFFFFFFF +/*-----------------------------------------------------------------------------------------------*/ + +/* Queue Bucket Refill (QRefill) */ +#define NETA_TXQ_REFILL_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1a20 + ((q) << 2)) + +#define NETA_TXQ_REFILL_TOKENS_OFFS 0 +#define NETA_TXQ_REFILL_TOKENS_MAX 0x7FFFF +#define NETA_TXQ_REFILL_TOKENS_ALL_MASK (NETA_TXQ_REFILL_TOKENS_MAX << NETA_TXQ_REFILL_TOKENS_OFFS) +#define NETA_TXQ_REFILL_TOKENS_MASK(val) ((val) << NETA_TXQ_REFILL_TOKENS_OFFS) + +#define NETA_TXQ_REFILL_PERIOD_OFFS 20 +#define NETA_TXQ_REFILL_PERIOD_MAX 0x3FF +#define NETA_TXQ_REFILL_PERIOD_ALL_MASK (NETA_TXQ_REFILL_PERIOD_MAX << NETA_TXQ_REFILL_PERIOD_OFFS) +#define NETA_TXQ_REFILL_PERIOD_MASK(val) ((val) << NETA_TXQ_REFILL_PERIOD_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Queue Maximum Token Bucket Size (QMTBS) */ +#define NETA_TXQ_TOKEN_SIZE_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1a40 + ((q) << 2)) +#define NETA_TXQ_TOKEN_SIZE_MAX 0x7FFFFFFF +/*-----------------------------------------------------------------------------------------------*/ + +/* Queue Token Bucket Counter (PMTBS) */ +#define NETA_TXQ_TOKEN_CNTR_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1a60 + ((q) << 2)) +#define NETA_TXQ_TOKEN_CNTR_MAX 0xFFFFFFFF +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmit Queue Arbiter Configuration (TQxAC) */ +#define NETA_TXQ_WRR_ARBITER_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1a80 + ((q) << 2)) + +#define NETA_TXQ_WRR_WEIGHT_OFFS 0 +#define NETA_TXQ_WRR_WEIGHT_MAX 0xFF +#define NETA_TXQ_WRR_WEIGHT_ALL_MASK (NETA_TXQ_WRR_WEIGHT_MAX << NETA_TXQ_WRR_WEIGHT_OFFS) +#define NETA_TXQ_WRR_WEIGHT_MASK(weigth) ((weigth) << NETA_TXQ_WRR_WEIGHT_OFFS) + +#define NETA_TXQ_WRR_BYTE_COUNT_OFFS 8 +#define NETA_TXQ_WRR_BYTE_COUNT_MASK (0x3FFFF << NETA_TXQ_WRR_BYTE_COUNT_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +/* Transmission Queue IPG (TQxIPG) */ +#define NETA_TXQ_EJP_IPG_REG(p, txp, q) (NETA_TX_REG_BASE((p), (txp)) + 0x1aa0 + ((q) << 2)) + +#define NETA_TXQ_EJP_IPG_OFFS 0 +#define NETA_TXQ_EJP_IPG_MASK (0x3FFF << NETA_TXQ_EJP_IPG_OFFS) +/*-----------------------------------------------------------------------------------------------*/ + +#define NETA_TXP_EJP_HI_LO_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1ab0) +#define NETA_TXP_EJP_HI_ASYNC_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1ab4) +#define NETA_TXP_EJP_LO_ASYNC_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1ab8) +#define NETA_TXP_EJP_SPEED_REG(p, txp) (NETA_TX_REG_BASE((p), (txp)) + 0x1abc) +/*-----------------------------------------------------------------------------------------------*/ +#endif /* MV_ETH_WRR_NEW */ + +/******************** NETA RX EXTENDED DESCRIPTOR ********************************/ + +#define NETA_DESC_ALIGNED_SIZE 32 + +typedef struct neta_rx_desc { + MV_U32 status; + MV_U16 pncInfo; + MV_U16 dataSize; + MV_U32 bufPhysAddr; + MV_U32 pncFlowId; + MV_U32 bufCookie; + MV_U16 prefetchCmd; + MV_U16 csumL4; + MV_U32 pncExtra; + MV_U32 hw_cmd; + +} NETA_RX_DESC; + +/* "status" word fileds definition */ +#define NETA_RX_L3_OFFSET_OFFS 0 +#define NETA_RX_L3_OFFSET_MASK (0x7F << NETA_RX_L3_OFFSET_OFFS) + +#define NETA_RX_IP_HLEN_OFFS 8 +#define NETA_RX_IP_HLEN_MASK (0x1F << NETA_RX_IP_HLEN_OFFS) + +#define NETA_RX_BM_POOL_ID_OFFS 13 +#define NETA_RX_BM_POOL_ALL_MASK (0x3 << NETA_RX_BM_POOL_ID_OFFS) +#define NETA_RX_BM_POOL_ID_MASK(pool) ((pool) << NETA_RX_BM_POOL_ID_OFFS) + +#define NETA_RX_ES_BIT 16 +#define NETA_RX_ES_MASK (1 << NETA_RX_ES_BIT) + +#define NETA_RX_ERR_CODE_OFFS 17 +#define NETA_RX_ERR_CODE_MASK (3 << NETA_RX_ERR_CODE_OFFS) +#define NETA_RX_ERR_CRC (0 << NETA_RX_ERR_CODE_OFFS) +#define NETA_RX_ERR_OVERRUN (1 << NETA_RX_ERR_CODE_OFFS) +#define NETA_RX_ERR_LEN (2 << NETA_RX_ERR_CODE_OFFS) +#define NETA_RX_ERR_RESOURCE (3 << NETA_RX_ERR_CODE_OFFS) + +#define NETA_RX_F_DESC_BIT 26 +#define NETA_RX_F_DESC_MASK (1 << NETA_RX_F_DESC_BIT) + +#define NETA_RX_L_DESC_BIT 27 +#define NETA_RX_L_DESC_MASK (1 << NETA_RX_L_DESC_BIT) + +#define NETA_RX_L4_CSUM_OK_BIT 30 +#define NETA_RX_L4_CSUM_OK_MASK (1 << NETA_RX_L4_CSUM_OK_BIT) + +#define NETA_RX_IP4_FRAG_BIT 31 +#define NETA_RX_IP4_FRAG_MASK (1 << NETA_RX_IP4_FRAG_BIT) + +#ifdef CONFIG_MV_ETH_PNC + +#define NETA_RX_L3_OFFS 24 +#define NETA_RX_L3_MASK (3 << NETA_RX_L3_OFFS) +#define NETA_RX_L3_UN (0 << NETA_RX_L3_OFFS) +#define NETA_RX_L3_IP6 (1 << NETA_RX_L3_OFFS) +#define NETA_RX_L3_IP4 (2 << NETA_RX_L3_OFFS) +#define NETA_RX_L3_IP4_ERR (3 << NETA_RX_L3_OFFS) + +#define NETA_RX_L4_OFFS 28 +#define NETA_RX_L4_MASK (3 << NETA_RX_L4_OFFS) +#define NETA_RX_L4_TCP (0 << NETA_RX_L4_OFFS) +#define NETA_RX_L4_UDP (1 << NETA_RX_L4_OFFS) +#define NETA_RX_L4_OTHER (2 << NETA_RX_L4_OFFS) + +/* Bits of "pncExtra" field */ +#define NETA_RX_PNC_ENABLED_BIT 0 +#define NETA_RX_PNC_ENABLED_MASK (1 << NETA_RX_PNC_ENABLED_BIT) + +#define NETA_RX_PNC_LOOPS_OFFS 1 +#define NETA_RX_PNC_LOOPS_MASK (0xF << NETA_RX_PNC_LOOPS_OFFS) + +#define NETA_PNC_STATUS_OFFS 5 +#define NETA_PNC_STATUS_MASK (3 << NETA_PNC_STATUS_OFFS) + +#define NETA_PNC_RI_EXTRA_OFFS 16 +#define NETA_PNC_RI_EXTRA_MASK (0xFFF << NETA_PNC_RI_EXTRA_OFFS) +/*---------------------------------------------------------------------------*/ + +#else + +#define ETH_RX_VLAN_TAGGED_FRAME_BIT 19 +#define ETH_RX_VLAN_TAGGED_FRAME_MASK (1 << ETH_RX_VLAN_TAGGED_FRAME_BIT) + +#define ETH_RX_BPDU_FRAME_BIT 20 +#define ETH_RX_BPDU_FRAME_MASK (1 << ETH_RX_BPDU_FRAME_BIT) + +#define ETH_RX_L4_TYPE_OFFSET 21 +#define ETH_RX_L4_TYPE_MASK (3 << ETH_RX_L4_TYPE_OFFSET) +#define ETH_RX_L4_TCP_TYPE (0 << ETH_RX_L4_TYPE_OFFSET) +#define ETH_RX_L4_UDP_TYPE (1 << ETH_RX_L4_TYPE_OFFSET) +#define ETH_RX_L4_OTHER_TYPE (2 << ETH_RX_L4_TYPE_OFFSET) + +#define ETH_RX_NOT_LLC_SNAP_FORMAT_BIT 23 +#define ETH_RX_NOT_LLC_SNAP_FORMAT_MASK (1 << ETH_RX_NOT_LLC_SNAP_FORMAT_BIT) + +#define ETH_RX_IP_FRAME_TYPE_BIT 24 +#define ETH_RX_IP_FRAME_TYPE_MASK (1 << ETH_RX_IP_FRAME_TYPE_BIT) + +#define ETH_RX_IP_HEADER_OK_BIT 25 +#define ETH_RX_IP_HEADER_OK_MASK (1 << ETH_RX_IP_HEADER_OK_BIT) + +#define ETH_RX_UNKNOWN_DA_BIT 28 +#define ETH_RX_UNKNOWN_DA_MASK (1 << ETH_RX_UNKNOWN_DA_BIT) + +#endif /* CONFIG_MV_ETH_PNC */ +/*---------------------------------------------------------------------------*/ + + +/* Bit map of "hw_cmd" field */ +#define NETA_RX_COLOR_BIT 3 +#define NETA_RX_COLOR_MASK (1 << NETA_RX_COLOR_BIT) +#define NETA_RX_COLOR_GREEN (0 << NETA_RX_COLOR_BIT) +#define NETA_RX_COLOR_YELLOW (1 << NETA_RX_COLOR_BIT) + +#define NETA_RX_DSA_OFFS 4 +#define NETA_RX_DSA_MASK (3 << NETA_RX_DSA_OFFS) +#define NETA_RX_DSA_NONE (0 << NETA_RX_DSA_OFFS) +#define NETA_RX_DSA (1 << NETA_RX_DSA_OFFS) +#define NETA_RX_DSA_E (2 << NETA_RX_DSA_OFFS) + +#define NETA_RX_GEM_PID_OFFS 8 +#define NETA_RX_GEM_PID_MASK (0xFFF << NETA_RX_GEM_PID_OFFS) +/*---------------------------------------------------------------------------*/ + + +/******************** NETA TX EXTENDED DESCRIPTOR ********************************/ + +typedef struct neta_tx_desc { + MV_U32 command; + MV_U16 csumL4; + MV_U16 dataSize; + MV_U32 bufPhysAddr; + MV_U32 hw_cmd; + MV_U32 reserved[4]; + +} NETA_TX_DESC; + +/* "command" word fileds definition */ +#define NETA_TX_L3_OFFSET_OFFS 0 +#define NETA_TX_L3_OFFSET_MASK (0x7F << NETA_TX_L3_OFFSET_OFFS) + +#define NETA_TX_GEM_OEM_BIT 7 +#define NETA_TX_GEM_OEM_MASK (1 << NETA_TX_GEM_OEM_BIT) + +#define NETA_TX_IP_HLEN_OFFS 8 +#define NETA_TX_IP_HLEN_MASK (0x1F << NETA_TX_IP_HLEN_OFFS) + +#define NETA_TX_BM_POOL_ID_OFFS 13 +#define NETA_TX_BM_POOL_ID_ALL_MASK (0x3 << NETA_TX_BM_POOL_ID_OFFS) +#define NETA_TX_BM_POOL_ID_MASK(pool) ((pool) << NETA_TX_BM_POOL_ID_OFFS) + +#define NETA_TX_HWF_BIT 15 +#define NETA_TX_HWF_MASK (1 << NETA_TX_HWF_BIT) + +#define NETA_TX_L4_BIT 16 +#define NETA_TX_L4_TCP (0 << NETA_TX_L4_BIT) +#define NETA_TX_L4_UDP (1 << NETA_TX_L4_BIT) + +#define NETA_TX_L3_BIT 17 +#define NETA_TX_L3_IP4 (0 << NETA_TX_L3_BIT) +#define NETA_TX_L3_IP6 (1 << NETA_TX_L3_BIT) + +#define NETA_TX_IP_CSUM_BIT 18 +#define NETA_TX_IP_CSUM_MASK (1 << NETA_TX_IP_CSUM_BIT) + +#define NETA_TX_Z_PAD_BIT 19 +#define NETA_TX_Z_PAD_MASK (1 << NETA_TX_Z_PAD_BIT) + +#define NETA_TX_L_DESC_BIT 20 +#define NETA_TX_L_DESC_MASK (1 << NETA_TX_L_DESC_BIT) + +#define NETA_TX_F_DESC_BIT 21 +#define NETA_TX_F_DESC_MASK (1 << NETA_TX_F_DESC_BIT) + +#define NETA_TX_BM_ENABLE_BIT 22 +#define NETA_TX_BM_ENABLE_MASK (1 << NETA_TX_BM_ENABLE_BIT) + + +#define NETA_TX_PKT_OFFSET_OFFS 23 +#define NETA_TX_PKT_OFFSET_ALL_MASK (0x7F << NETA_TX_PKT_OFFSET_OFFS) +#define NETA_TX_PKT_OFFSET_MASK(offset) ((offset) << NETA_TX_PKT_OFFSET_OFFS) + +#define NETA_TX_L4_CSUM_BIT 30 +#define NETA_TX_L4_CSUM_MASK (3 << NETA_TX_L4_CSUM_BIT) +#define NETA_TX_L4_CSUM_PART (0 << NETA_TX_L4_CSUM_BIT) +#define NETA_TX_L4_CSUM_FULL (1 << NETA_TX_L4_CSUM_BIT) +#define NETA_TX_L4_CSUM_NOT (2 << NETA_TX_L4_CSUM_BIT) + +#define NETA_TX_FLZ_DESC_MASK (NETA_TX_F_DESC_MASK | NETA_TX_L_DESC_MASK | NETA_TX_Z_PAD_MASK) +/*-------------------------------------------------------------------------------*/ + +/* "hw_cmd" field definition */ +#define NETA_TX_ES_BIT 0 +#define NETA_TX_ES_MASK (1 << NETA_TX_ES_BIT) + +#define NETA_TX_ERR_CODE_OFFS 1 +#define NETA_TX_ERR_CODE_MASK (3 << NETA_TX_ERR_CODE_OFFS) +#define NETA_TX_ERR_LATE_COLLISION (0 << NETA_TX_ERR_CODE_OFFS) +#define NETA_TX_ERR_UNDERRUN (1 << NETA_TX_ERR_CODE_OFFS) +#define NETA_TX_ERR_EXCE_COLLISION (2 << NETA_RX_ERR_CODE_OFFS) + +#define NETA_TX_COLOR_BIT 3 +#define NETA_TX_COLOR_GREEN (0 << NETA_TX_COLOR_BIT) +#define NETA_TX_COLOR_YELLOW (1 << NETA_TX_COLOR_BIT) + +#define NETA_TX_MH_SEL_OFFS 4 +#define NETA_TX_MH_SEL_MASK (7 << NETA_TX_MH_SEL_OFFS) +#define NETA_TX_MH_UNCHANGE (0 << NETA_TX_MH_SEL_OFFS) + +#define NETA_TX_GEM_PID_OFFS 8 +#define NETA_TX_GEM_PID_MASK (0xFFF << NETA_TX_GEM_PID_OFFS) + +#define NETA_TX_MOD_CMD_OFFS 20 +#define NETA_TX_MOD_CMD_MASK (0x3FF << NETA_TX_MOD_CMD_OFFS) + +#define NETA_TX_DSA_OFFS 30 +#define NETA_TX_DSA_MASK (3 << NETA_TX_DSA_OFFS) +#define NETA_TX_DSA_NONE (0 << NETA_TX_DSA_OFFS) +#define NETA_TX_DSA (1 << NETA_TX_DSA_OFFS) /* normal dsa */ +#define NETA_TX_DSA_E (2 << NETA_TX_DSA_OFFS) /* extended dsa */ +/*-------------------------------------------------------------------------------*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __mvNetaRegs_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfp.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfp.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfp.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfp.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,749 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.c - Marvell Network Fast Processing (Routing and NAT) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "gbe/mvEthRegs.h" +#include "gbe/mvNetaRegs.h" +#include "gbe/mvNeta.h" +#include "mvNfp.h" + +static MV_U32 nfp_ports[MV_ETH_MAX_PORTS]; +static NFP_STATS nfp_stats[MV_ETH_MAX_PORTS]; + +unsigned int mgr_rule_jhash_iv; + +#if 0 +#define NFP_DBG mvOsPrintf +#else +#define NFP_DBG(X...) +#endif + +#ifdef NFP_STAT +#define NFP_INC(p, s) nfp_stats[p].s++; +#else +#define NFP_INC(p, s) +#endif + +/* + * Init + */ +MV_VOID _INIT mvNfpInit(MV_VOID) +{ + mvOsMemset(nfp_ports, 0, sizeof(MV_U32) * MV_ETH_MAX_PORTS); + mvOsMemset(nfp_stats, 0, sizeof(NFP_STATS) * MV_ETH_MAX_PORTS); +} + +/* + * Port capability, e.g. NAT/PPP/IPSEC + */ +MV_VOID mvNfpPortCapSet(MV_U32 port, MV_U32 cap, MV_U32 on) +{ + if (on) + nfp_ports[port] |= cap; + else + nfp_ports[port] &= ~cap; +} + +MV_U32 mvNfpPortCapGet(MV_U32 port) +{ + return nfp_ports[port]; +} + +static INLINE MV_U32 mvNfpPortCapNat(MV_U32 port) +{ + return nfp_ports[port] & NFP_P_NAT; +} + +static INLINE void mvNfpFibMacUpdate(MV_U8 *pData, NFP_RULE_FIB *pFib) +{ + *(MV_U32 *) (pData + 0) = *(MV_U32 *) (&pFib->mh); + *(MV_U32 *) (pData + 4) = *(MV_U32 *) (&pFib->da[2]); + *(MV_U32 *) (pData + 8) = *(MV_U32 *) (&pFib->sa[0]); + *(MV_U16 *) (pData + 12) = *(MV_U16 *) (&pFib->sa[4]); +} + +static INLINE void mvNfpFibIPUpdate(MV_IP_HEADER *pIph) +{ + pIph->ttl--; +} + +static INLINE void mvNfpFibIP6Update(MV_IP6_HEADER *pIp6Hdr) +{ + pIp6Hdr->hoplimit--; +} + +#ifdef NFP_NAT +static INLINE NFP_RULE_NAT *mvNfpNatLookup(MV_U32 sip, MV_U32 dip, MV_U32 proto, MV_U32 ports) +{ + MV_U32 hash; + NFP_RULE_NAT *rule; + int family = MV_INET; + + if ((proto != MV_IP_PROTO_TCP) && (proto != MV_IP_PROTO_UDP)) + return NULL; + hash = mv_jhash_2addr(family, (const MV_U8 *)&sip, (const MV_U8 *)&dip, ports | proto, mgr_rule_jhash_iv); + hash &= NFP_NAT_HASH_MASK; + + rule = nat_hash[hash]; + + while (rule) { + if ((rule->sip == sip) && (rule->dip == dip) && (rule->ports == ports) && (rule->proto == proto)) { + rule->age++; + return rule; + } + rule = rule->next; + } + + return NULL; +} + +static INLINE void mvNfpNatUpdate(MV_IP_HEADER *pIpHdr, int ipHdrLen, NFP_RULE_NAT *pDnat, NFP_RULE_NAT *pSnat) +{ + MV_U16 *pPort = (MV_U16 *) ((char *)pIpHdr + ipHdrLen); + + if (pSnat) { + pIpHdr->srcIP = pSnat->nip; + *pPort = pSnat->nport; + } + + if (pDnat) { + pIpHdr->dstIP = pDnat->nip; + pPort++; + *pPort = pDnat->nport; + } +} +#endif /* NFP_NAT */ + +#ifdef CONFIG_MV_ETH_NFP_PPP +static INLINE int removePppoeHeader(MV_U8 *pData) +{ + /* writing IP ethertype to the new location of ether header */ + pData[MV_ETH_ALEN + MV_PPPOE_HDR_SIZE] = 0x08; + pData[MV_ETH_ALEN + MV_PPPOE_HDR_SIZE + 1] = 0x00; + + return MV_PPPOE_HDR_SIZE; +} + +static INLINE int addPppoeHeader(MV_U8 *pData, NFP_RULE_FIB *pFib, MV_U16 ipLen) +{ + PPPoE_HEADER *pPPPNew; + + pData = pData - MV_PPPOE_HDR_SIZE; + + pData[MV_ETH_ALEN] = 0x88; + pData[MV_ETH_ALEN + 1] = 0x64; + + pPPPNew = (PPPoE_HEADER *) (pData + MV_ETH_ALEN + MV_ETH_MH_SIZE); + pPPPNew->version = 0x11; + pPPPNew->code = 0x0; + pPPPNew->proto = 0x2100; + pPPPNew->session = pFib->sid; + + /* calculate PPPoE payload len considering padding for short packets */ + pPPPNew->len = MV_16BIT_BE(ipLen + MV_PPP_HDR_SIZE); + return -MV_PPPOE_HDR_SIZE; +} +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef NFP_PNC +/* + * NFP Process with PnC + */ +MV_STATUS mvNfpPnC(MV_U32 port, NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt) +{ + NFP_RULE_PNC *pPnc; + NFP_RULE_FIB *pFib; + MV_U8 *pData; + MV_U8 *pWrite = NULL; + MV_IP_HEADER *pIph = NULL; + MV_IP6_HEADER *pIp6Hdr = NULL; + int ipHdrLen, ipOffset, flowId, shift = 0; + MV_U16 ipLen = 0; + MV_U8 tos = 0; + MV_U8 *srcL3; + MV_U8 *dstL3; + int family = 0; +#ifdef NFP_NAT + NFP_RULE_NAT *pSnat, *pDnat; +#endif + NFP_INC(port, pnc_in); + + if ((pRxDesc->status & NETA_RX_L3_MASK) == NETA_RX_L3_IP4_ERR) { + NFP_INC(port, ipv4_csum_err); + return MV_TERMINATE; + } else + if ((pRxDesc->status & NETA_RX_L3_MASK) == NETA_RX_L3_UN) { + NFP_INC(port, non_ip); + return MV_TERMINATE; + } + + if ((((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_TCP) || + ((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_UDP)) && + ((pRxDesc->status & NETA_RX_L4_CSUM_OK_MASK) == 0)) { + NFP_INC(port, l4_csum_err); + return MV_TERMINATE; + } + + flowId = pRxDesc->pncFlowId; + +#ifdef CONFIG_MV_ETH_NFP_DEBUG + /* sanity */ + if (flowId >= NFP_PNC_ARRAY_SIZE) { + NFP_INC(port, pnc_flow_oor); + return MV_TERMINATE; + } +#endif /* CONFIG_MV_ETH_NFP_DEBUG */ + + pPnc = pnc_hash + flowId; + pPnc->age++; +#ifdef CONFIG_MV_ETH_NFP_DEBUG + /* sanity */ + if (pPnc->flowid != flowId) { + NFP_INC(port, pnc_flow_err); + return MV_TERMINATE; + } +#endif /* CONFIG_MV_ETH_NFP_DEBUG */ + + pFib = pPnc->fib; + +#ifdef CONFIG_MV_ETH_NFP_DEBUG + /* sanity: Routing must be valid */ + if (!pFib || (pFib->flags & NFP_F_INV)) { + NFP_INC(port, pnc_fib_err); + return MV_TERMINATE; + } +#endif /* CONFIG_MV_ETH_NFP_DEBUG */ + + pFib->age++; + NFP_INC(port, pnc_fib_hit); +#ifdef NFP_NAT + /* DNAT */ + pDnat = NULL; + if (mvNfpPortCapNat(port)) { + if (!pPnc->nat) { + NFP_INC(port, pnc_dnat_err); + return MV_TERMINATE; + } + if (pPnc->nat->flags & NFP_F_DNAT) { + pDnat = pPnc->nat; + NFP_INC(port, pnc_dnat_hit); + pDnat->age++; + } + } + + /* SNAT */ + pSnat = NULL; + if (mvNfpPortCapNat(pFib->outport)) { + if (!pPnc->nat) { + NFP_INC(port, pnc_snat_err); + return MV_TERMINATE; + } + if (pPnc->nat->flags & NFP_F_SNAT) { + pSnat = pPnc->nat; + NFP_INC(port, pnc_snat_hit); + pSnat->age++; + } + } +#endif /* NFP_NAT */ + + /* Calculate pointers to L2, L3 and L4 headers */ + pData = pPkt->pBuf + pPkt->offset; + ipOffset = (pRxDesc->status & NETA_RX_L3_OFFSET_MASK) >> NETA_RX_L3_OFFSET_OFFS; + ipHdrLen = ((pRxDesc->status & NETA_RX_IP_HLEN_MASK) >> NETA_RX_IP_HLEN_OFFS) << 2; + if ((pRxDesc->status & NETA_RX_L3_MASK) == NETA_RX_L3_IP6) { + family = MV_INET6; + pIp6Hdr = (MV_IP6_HEADER *)(pData + ipOffset); + if (pIp6Hdr->hoplimit <= 1) { + NFP_INC(port, ttl_exp); + return MV_TERMINATE; + } + NFP_INC(port, process6); + srcL3 = pIp6Hdr->srcAddr; + dstL3 = pIp6Hdr->dstAddr; + /* tos = pIp6Hdr->priority; */ + } else { + family = MV_INET; + pIph = (MV_IP_HEADER *)(pData + ipOffset); + + /* Check TTL validity - add to PNC - TBD */ + if (pIph->ttl <= 1) { + NFP_INC(port, ttl_exp); + return MV_TERMINATE; + } + tos = pIph->tos; + + /* Remove padding */ + ipLen = MV_16BIT_BE(pIph->totalLength); + pPkt->bytes = (ipLen + ipOffset); + } + + /* Update packet */ + if (pFib) { +#ifdef CONFIG_MV_ETH_NFP_PPP + /* remove pppoe header */ + if (pFib->flags & NFP_F_PPPOE_REMOVE) { + int pppShift = removePppoeHeader(pData); + shift += pppShift; + pPkt->bytes -= pppShift; + NFP_INC(port, pppoe_remove); + } + /* add pppoe header */ + if (pFib->flags & NFP_F_PPPOE_ADD) { + int pppShift = addPppoeHeader(pData, pFib, ipLen); + shift += pppShift; + pPkt->bytes -= pppShift; + NFP_INC(port, pppoe_add); + } +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + mvNfpFibMacUpdate(pData + shift, pFib); + if (family == MV_INET) + mvNfpFibIPUpdate(pIph); + else + mvNfpFibIP6Update(pIp6Hdr); + + + /* Process 2B of MH */ + if (!(nfp_ports[pFib->outport] & NFP_P_MH)) { + shift += MV_ETH_MH_SIZE; + pPkt->bytes -= MV_ETH_MH_SIZE; + } + if (family == MV_INET) { + + pPkt->tx_cmd |= NETA_TX_L3_IP4 | NETA_TX_IP_CSUM_MASK | + NETA_TX_PKT_OFFSET_MASK(pPkt->offset + shift) | + ((ipOffset - shift) << NETA_TX_L3_OFFSET_OFFS) | + ((ipHdrLen >> 2) << NETA_TX_IP_HLEN_OFFS); + pWrite = (MV_U8 *)pIph + ipHdrLen; + } else { + pPkt->tx_cmd |= NETA_TX_L3_IP6 | + NETA_TX_PKT_OFFSET_MASK(pPkt->offset + shift) | + ((ipOffset - shift) << NETA_TX_L3_OFFSET_OFFS) | + ((ipHdrLen >> 2) << NETA_TX_IP_HLEN_OFFS); + pWrite = (MV_U8 *)pIp6Hdr + ipHdrLen; + } + + +#ifdef NFP_NAT + if (pDnat || pSnat) { + mvNfpNatUpdate(pIph, ipHdrLen, pDnat, pSnat); + pPkt->tx_cmd &= ~NETA_TX_L4_CSUM_MASK; + if ((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_TCP) + pPkt->tx_cmd |= NETA_TX_L4_TCP | NETA_TX_L4_CSUM_FULL; + else if ((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_UDP) + pPkt->tx_cmd |= NETA_TX_L4_UDP | NETA_TX_L4_CSUM_FULL; + pWrite += 4; + } +#endif /* NFP_NAT */ + } + if (pWrite != NULL) { + if (shift < 0) + pData += shift; + /*mvOsPrintf("cacheFlashInv: pData=%p, size=%d\n", pData, (pWrite - pData));*/ + mvOsCacheFlushInv(NULL, pData, (pWrite - pData)); + } + pPkt->dev = pFib->outdev; + pPkt->tos = tos; + + NFP_INC(port, pnc_out); + + return MV_OK; +} +#endif /* PNC */ + + +/* + * NFP Process without PnC + */ +MV_STATUS mvNfpRx(MV_U32 port, NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt) +{ + NFP_RULE_FIB *pFib; + MV_U32 ports = 0, proto = 0; + MV_U8 *pData, *pEth, *pWrite = NULL; + MV_IP_HEADER *pIph = NULL; + MV_IP6_HEADER *pIp6Hdr = NULL; + int ipHdrLen, ipOffset, shift = 0; + MV_U16 ipLen = 0; + MV_U8 tos = 0; +#ifdef NFP_NAT + NFP_RULE_NAT *pDnat = NULL; + NFP_RULE_NAT *pSnat = NULL; +#endif + int family = 0; + MV_U8 *srcL3; + MV_U8 *dstL3; + + NFP_INC(port, parse); + + pData = pPkt->pBuf + pPkt->offset; + +#ifdef CONFIG_MV_ETH_PNC + if ((pRxDesc->status & NETA_RX_L3_MASK) == NETA_RX_L3_IP4_ERR) { + NFP_INC(port, ipv4_csum_err); + return MV_TERMINATE; + } else if ((pRxDesc->status & NETA_RX_L3_MASK) == NETA_RX_L3_UN) { + NFP_INC(port, non_ip); + return MV_TERMINATE; + } + if ((((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_TCP) || + ((pRxDesc->status & NETA_RX_L4_MASK) == NETA_RX_L4_UDP)) && + ((pRxDesc->status & NETA_RX_L4_CSUM_OK_MASK) == 0)) { + NFP_INC(port, l4_csum_err); + return MV_TERMINATE; + } + + ipOffset = (pRxDesc->status & NETA_RX_L3_OFFSET_MASK) >> NETA_RX_L3_OFFSET_OFFS; + ipHdrLen = ((pRxDesc->status & NETA_RX_IP_HLEN_MASK) >> NETA_RX_IP_HLEN_OFFS) << 2; +#else + if (((pRxDesc->status & ETH_RX_NOT_LLC_SNAP_FORMAT_MASK) == 0) || + ((pRxDesc->status & ETH_RX_IP_HEADER_OK_MASK) == 0)) { + NFP_INC(port, non_ip); + return MV_TERMINATE; + } + + if ((((pRxDesc->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_TCP_TYPE) || + ((pRxDesc->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_UDP_TYPE)) && + ((pRxDesc->status & NETA_RX_L4_CSUM_OK_MASK) == 0)) { + NFP_INC(port, l4_csum_err); + return MV_TERMINATE; + } + + if ((pRxDesc->status & ETH_RX_VLAN_TAGGED_FRAME_MASK)) + ipOffset = MV_ETH_MH_SIZE + sizeof(MV_802_3_HEADER) + MV_VLAN_HLEN; + else + ipOffset = MV_ETH_MH_SIZE + sizeof(MV_802_3_HEADER); + + ipHdrLen = sizeof(MV_IP_HEADER); +#endif /* CONFIG_MV_ETH_PNC */ + + pEth = pData + MV_ETH_MH_SIZE; + if (pEth[0] & 0x01) { /* Check multicast and broadcast */ + NFP_INC(port, mac_mcast); + return MV_TERMINATE; + } + if(NETA_RX_L3_IS_IP6(pRxDesc->status) ) { + family = MV_INET6; + pIp6Hdr = (MV_IP6_HEADER *) (pData + ipOffset); + if (pIp6Hdr->hoplimit <= 1) { + NFP_INC(port, ttl_exp); + return MV_TERMINATE; + } + + NFP_INC(port, process6); + + srcL3 = pIp6Hdr->srcAddr; + dstL3 = pIp6Hdr->dstAddr; + } else { + family = MV_INET; + pIph = (MV_IP_HEADER *) (pData + ipOffset); + if (NETA_RX_IP_IS_FRAG(pRxDesc->status)) { + NFP_INC(port, ipv4_frag); + return MV_TERMINATE; + } + + if (pIph->ttl <= 1) { + NFP_INC(port, ttl_exp); + return MV_TERMINATE; + } + + /* Remove padding */ + ipLen = MV_16BIT_BE(pIph->totalLength); + pPkt->bytes = (ipLen + ipOffset); + + NFP_INC(port, process); + + /* save 5-tuple information from received packet */ + dstL3 = (MV_U8 *) &(pIph->dstIP); + srcL3 = (MV_U8 *) &(pIph->srcIP); + + proto = pIph->protocol; + ports = *(MV_U32 *) ((char *)pIph + ipHdrLen); + tos = pIph->tos; + +#ifdef NFP_NAT + /* DNAT */ + if (mvNfpPortCapNat(port)) { + if (!NETA_RX_L4_CSUM_IS_OK(pRxDesc->status)) { + NFP_INC(port, l4_unknown); + return MV_TERMINATE; + } + pDnat = mvNfpNatLookup(pIph->srcIP, pIph->dstIP, proto, ports); + + if (!pDnat) { + NFP_INC(port, dnat_miss); + return MV_TERMINATE; + } + + if ((pDnat->flags & NFP_F_DNAT) == 0) { + NFP_INC(port, dnat_inv); + return MV_TERMINATE; + } + + NFP_INC(port, dnat_hit); + + /* In case we found a DNAT rule, + we need to update the dip and destination port for future FIB and SNAT lookups */ + dstL3 = (MV_U8 *) &(pDnat->nip); + ports = (pDnat->nport << 16) | (ports & 0x0000FFFF); + } else + pDnat = NULL; +#endif /* NFP_NAT */ + } + + pFib = mvNfpFibLookup(family, srcL3, dstL3); + + if (!pFib) { + if (family == MV_INET) + NFP_DBG("%s failed: " MV_IPQUAD_FMT "->" MV_IPQUAD_FMT "\n", + __func__, MV_IPQUAD(*((u32 *) srcL3)), MV_IPQUAD(*((u32 *) dstL3))); + else + NFP_DBG("%s failed: " MV_IP6_FMT "->" MV_IP6_FMT "\n", + __func__, MV_IP6_ARG(srcL3), MV_IP6_ARG(dstL3)); + + NFP_INC(port, fib_miss); + return MV_TERMINATE; + } + pFib->age++; + + if (pFib->flags & NFP_F_INV) { + NFP_INC(port, fib_inv); + return MV_TERMINATE; + } + NFP_INC(port, fib_hit); + +#ifdef NFP_NAT + if (pIph != NULL) { + /* SNAT */ + if (mvNfpPortCapNat(pFib->outport)) { + if (!NETA_RX_L4_CSUM_IS_OK(pRxDesc->status)) { + NFP_INC(port, l4_unknown); + return MV_TERMINATE; + } + /* We must not use here pIph->srcIP + since it might not reflect an update */ + pSnat = mvNfpNatLookup(*((u32 *) srcL3), *((u32 *) dstL3), proto, ports); + + if (!pSnat) { + NFP_INC(port, snat_miss); + return MV_TERMINATE; + } + + if ((pSnat->flags & NFP_F_SNAT) == 0) { + NFP_INC(port, snat_inv); + return MV_TERMINATE; + } + + NFP_INC(port, snat_hit); + } else + pSnat = NULL; + } +#endif /* NFP_NAT */ + + /* if (pIph != NULL) */ + /* Modify packet */ + if (pFib) { +#ifdef CONFIG_MV_ETH_NFP_PPP + /* remove pppoe header */ + if (pFib->flags & NFP_F_PPPOE_REMOVE) { + int pppShift = removePppoeHeader(pData); + + shift += pppShift; + pPkt->bytes -= pppShift; + NFP_INC(port, pppoe_remove); + } + /* add pppoe header */ + if (pFib->flags & NFP_F_PPPOE_ADD) { + int pppShift = addPppoeHeader(pData, pFib, ipLen); + + shift += pppShift; + pPkt->bytes -= pppShift; + NFP_INC(port, pppoe_add); + + } +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + mvNfpFibMacUpdate(pData + shift, pFib); + if (family == MV_INET) + mvNfpFibIPUpdate(pIph); + else + mvNfpFibIP6Update(pIp6Hdr); + + /* Process 2B of MH */ + if (!(nfp_ports[pFib->outport] & NFP_P_MH)) { + shift += MV_ETH_MH_SIZE; + pPkt->bytes -= MV_ETH_MH_SIZE; + } + if (family == MV_INET) { + + pPkt->tx_cmd |= NETA_TX_L3_IP4 | NETA_TX_IP_CSUM_MASK | + NETA_TX_PKT_OFFSET_MASK(pPkt->offset + shift) | + ((ipOffset - shift) << NETA_TX_L3_OFFSET_OFFS) | ((ipHdrLen >> 2) << NETA_TX_IP_HLEN_OFFS); + pWrite = (MV_U8 *) pIph + ipHdrLen; + } else { + pPkt->tx_cmd |= NETA_TX_L3_IP6 | + NETA_TX_PKT_OFFSET_MASK(pPkt->offset + shift) | + ((ipOffset - shift) << NETA_TX_L3_OFFSET_OFFS) | ((ipHdrLen >> 2) << NETA_TX_IP_HLEN_OFFS); + pWrite = (MV_U8 *) pIp6Hdr + ipHdrLen; + } + +#ifdef NFP_NAT + if (pDnat || pSnat) { + mvNfpNatUpdate(pIph, ipHdrLen, pDnat, pSnat); + + pPkt->tx_cmd &= ~NETA_TX_L4_CSUM_MASK; + if (NETA_RX_L4_IS_TCP(pRxDesc->status)) + pPkt->tx_cmd |= NETA_TX_L4_TCP | NETA_TX_L4_CSUM_FULL; + else if (NETA_RX_L4_IS_UDP(pRxDesc->status)) + pPkt->tx_cmd |= NETA_TX_L4_UDP | NETA_TX_L4_CSUM_FULL; + + pWrite += 4; + } +#endif /* NFP_NAT */ + } + /* Flash maximum accessed data before TX */ + if (pWrite != NULL) { + if (shift < 0) + pData += shift; + + /*mvOsPrintf("cacheFlashInv: pData=%p, size=%d\n", pData, (pWrite - pData)); */ + mvOsCacheFlushInv(NULL, pData, (pWrite - pData)); + } + pPkt->dev = pFib->outdev; + pPkt->tos = tos; + + return MV_OK; +} + +MV_VOID mvNfpStats(MV_U32 port) +{ + mvOsPrintf("\n====================================================\n"); + mvOsPrintf(" NFP statistics"); + mvOsPrintf("\n-------------------------------\n"); + +#ifdef NFP_STAT + mvOsPrintf("nfp_parsed....................%10u\n", nfp_stats[port].parse); + mvOsPrintf("nfp_non_ip....................%10u\n", nfp_stats[port].non_ip); + mvOsPrintf("nfp_ipv4_csum_err.............%10u\n", nfp_stats[port].ipv4_csum_err); + mvOsPrintf("nfp_ipv4_frag.................%10u\n", nfp_stats[port].ipv4_frag); + mvOsPrintf("nfp_mac_mcast.................%10u\n", nfp_stats[port].mac_mcast); + mvOsPrintf("nfp_ttl_exp...................%10u\n", nfp_stats[port].ttl_exp); + mvOsPrintf("nfp_l4_unknown................%10u\n", nfp_stats[port].l4_unknown); + mvOsPrintf("nfp_l4_csum_err...............%10u\n", nfp_stats[port].l4_csum_err); + mvOsPrintf("nfp_process...................%10u\n", nfp_stats[port].process); + mvOsPrintf("nfp_process_ipv6..............%10u\n", nfp_stats[port].process6); +#ifdef NFP_FIB + mvOsPrintf("nfp_fib_hit...................%10u\n", nfp_stats[port].fib_hit); + mvOsPrintf("nfp_fib_miss..................%10u\n", nfp_stats[port].fib_miss); + mvOsPrintf("nfp_fib_inv...................%10u\n", nfp_stats[port].fib_inv); +#endif /* NFP_FIB */ + +#ifdef NFP_NAT + mvOsPrintf("nfp_dnat_hit..................%10u\n", nfp_stats[port].dnat_hit); + mvOsPrintf("nfp_dnat_miss.................%10u\n", nfp_stats[port].dnat_miss); + mvOsPrintf("nfp_dnat_inv..................%10u\n", nfp_stats[port].dnat_inv); + + mvOsPrintf("nfp_snat_hit..................%10u\n", nfp_stats[port].snat_hit); + mvOsPrintf("nfp_snat_miss.................%10u\n", nfp_stats[port].snat_miss); + mvOsPrintf("nfp_snat_inv..................%10u\n", nfp_stats[port].snat_inv); +#endif /* NFP_NAT */ + +#ifdef NFP_SWF + mvOsPrintf("nfp_swf_hit...................%10u\n", nfp_stats[port].swf_hit); + mvOsPrintf("nfp_swf_miss..................%10u\n", nfp_stats[port].swf_miss); +#endif /* NFP_SWF */ + +#ifdef NFP_PNC + mvOsPrintf("pnc_in........................%10u\n", nfp_stats[port].pnc_in); + mvOsPrintf("pnc_dnat_hit..................%10u\n", nfp_stats[port].pnc_dnat_hit); + mvOsPrintf("pnc_fib_hit...................%10u\n", nfp_stats[port].pnc_fib_hit); + mvOsPrintf("pnc_snat_hit..................%10u\n", nfp_stats[port].pnc_snat_hit); + mvOsPrintf("pnc_out.......................%10u\n", nfp_stats[port].pnc_out); + mvOsPrintf("pnc_flow_oor..................%10u\n", nfp_stats[port].pnc_flow_oor); + mvOsPrintf("pnc_flow_err..................%10u\n", nfp_stats[port].pnc_flow_err); + mvOsPrintf("pnc_dnat_err..................%10u\n", nfp_stats[port].pnc_dnat_err); + mvOsPrintf("pnc_fib_err...................%10u\n", nfp_stats[port].pnc_fib_err); + mvOsPrintf("pnc_snat_err..................%10u\n", nfp_stats[port].pnc_snat_err); +#endif /* NFP_PNC */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + mvOsPrintf("pppoe_add.....................%10u\n", nfp_stats[port].pppoe_add); + mvOsPrintf("pppoe_remove..................%10u\n", nfp_stats[port].pppoe_remove); +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + mvOsMemset(&nfp_stats[port], 0, sizeof(NFP_STATS)); +#endif /* NFP_STAT */ +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpDefs.h u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpDefs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpDefs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpDefs.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,105 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.h - Header File for Marvell NFP (Routing and NAT) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing (Routing and NAT). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfpDefs_h__ +#define __mvNfpDefs_h__ + +#ifdef CONFIG_MV_ETH_NFP +#define ETH_NFP + +#ifdef CONFIG_MV_ETH_NFP_PNC +#define NFP_PNC +#endif + +#ifdef CONFIG_MV_ETH_NFP_FIB +#define NFP_FIB +#endif + +#ifdef CONFIG_MV_ETH_NFP_NAT +#define NFP_NAT +#endif + +#ifdef CONFIG_MV_ETH_NFP_SWF +#define NFP_SWF +#endif + +#ifdef CONFIG_MV_ETH_NFP_STATS +#define NFP_STAT +#endif + +#endif /* CONFIG_MV_ETH_NFP */ + +#endif /* __mvNfp_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpFib.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpFib.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpFib.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpFib.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,356 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpFib.c - Marvell Fast Network Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvDebug.h" +#include "gbe/mvNeta.h" +#include "mvNfpDefs.h" +#include "mvNfp.h" + +/*#define NFP_DBG(x...) mvOsPrintf(x)*/ +#define NFP_DBG(x...) + +NFP_RULE_FIB **fib_hash = NULL; + +MV_STATUS _INIT mvNfpFibInit(void) +{ + MV_U32 bytes = sizeof(NFP_RULE_FIB *) * NFP_FIB_HASH_SIZE; + + fib_hash = (NFP_RULE_FIB **) mvOsMalloc(bytes); + if (fib_hash == NULL) { + mvOsPrintf("NFP (fib): not enough memory\n"); + return MV_NO_RESOURCE; + } + + mvOsMemset(fib_hash, 0, bytes); + + mvOsPrintf("NFP (fib) init %d entries, %d bytes\n", NFP_FIB_HASH_SIZE, bytes); + + return MV_OK; +} + +static void mvNfpFibRulePrint(NFP_RULE_FIB *fib) +{ + if (fib->family == MV_INET) { + + mvOsPrintf("IPv4: " MV_IPQUAD_FMT "->" MV_IPQUAD_FMT"\n", + MV_IPQUAD(*((u32 *) fib->srcL3)), MV_IPQUAD(*((u32 *) fib->dstL3))); + } else { + mvOsPrintf("IPv6: " MV_IP6_FMT "->" MV_IP6_FMT"\n", + MV_IP6_ARG(fib->srcL3), MV_IP6_ARG(fib->dstL3)); + + } + mvOsPrintf(" mh=%2.2x:%2.2x da=" MV_MACQUAD_FMT " sa=" MV_MACQUAD_FMT "\n", + ((MV_U8 *) &fib->mh)[0], ((MV_U8 *) &fib->mh)[1], MV_MACQUAD(fib->da), MV_MACQUAD(fib->sa)); + mvOsPrintf(" port=%d flags=0x%x ref=%d age=%x fib=%p pnc=%p\n", + fib->outport, fib->flags, fib->ref, fib->age, fib, fib->pnc); + + mvOsPrintf("Flags: "); + if (fib->flags & NFP_F_DYNAMIC) + mvOsPrintf("NFP_F_DYNAMIC "); + if (fib->flags & NFP_F_STATIC) + mvOsPrintf("NFP_F_STATIC "); + if (fib->flags & NFP_F_INV) + mvOsPrintf("NFP_F_INV "); + if (fib->flags & NFP_F_SNAT) + mvOsPrintf("NFP_F_SNAT "); + if (fib->flags & NFP_F_DNAT) + mvOsPrintf("NFP_F_DNAT "); + if (fib->flags & NFP_F_BUSY) + mvOsPrintf("NFP_F_BUSY "); + if (fib->flags & NFP_F_PPPOE_ADD) + mvOsPrintf("NFP_F_PPPOE_ADD "); + if (fib->flags & NFP_F_PPPOE_REMOVE) + mvOsPrintf("NFP_F_PPPOE_REMOVE "); + if (fib->flags & NFP_F_HWF) + mvOsPrintf("NFP_F_HWF "); + + mvOsPrintf("\n"); +} + +MV_STATUS mvNfpFibRuleArpAdd(int family, NFP_RULE_FIB *fib2) +{ + MV_U32 i = NFP_FIB_HASH_SIZE; + NFP_RULE_FIB *fib; + MV_STATUS status = MV_NOT_FOUND; + + if (!fib_hash) + return MV_FAIL; + + while (i--) { + fib = fib_hash[i]; + while (fib) { + if ((l3_addr_eq(family, fib->defGtwL3, fib2->defGtwL3))) { + + /* Found routing entry */ + if (fib->flags & NFP_F_INV) { + /* Validate new route */ + fib->flags &= ~NFP_F_INV; + mvOsMemcpy(fib->da, fib2->da, 6); + } else if (memcmp(fib->da, fib2->da, 6)) { + /* Update already valid route with new MAC address. FIXME - update HWF rule */ + mvOsMemcpy(fib->da, fib2->da, 6); + } else { + /* Do nothing - MAC address don't changed */ + } + status = MV_OK; + } + fib = fib->next; + } + } + return status; +} + +/* Invalidate all routes with rule2->defGtwL3 */ +MV_STATUS mvNfpFibRuleArpDel(int family, NFP_RULE_FIB *fib2) +{ + MV_U32 i = NFP_FIB_HASH_SIZE; + NFP_RULE_FIB *fib; + MV_STATUS status = MV_NOT_FOUND; + + if (!fib_hash) + return MV_FAIL; + + while (i--) { + fib = fib_hash[i]; + while (fib) { + if ((l3_addr_eq(family, fib->defGtwL3, fib2->defGtwL3))) { + + /* Invalidate existing route. FIXME - update HWF rule */ + fib->flags &= ~NFP_F_INV; + status = MV_OK; + } + fib = fib->next; + } + } + return status; +} + +/* If exist routing entires with the rule2->defGtwL3 - prevent aging */ +MV_STATUS mvNfpFibRuleArpAge(int family, NFP_RULE_FIB *fib2) +{ + MV_U32 i = NFP_FIB_HASH_SIZE; + NFP_RULE_FIB *fib; + + fib2->age = 0; + if (!fib_hash) + return MV_FAIL; + + while (i--) { + fib = fib_hash[i]; + while (fib) { + if ((l3_addr_eq(family, fib->defGtwL3, fib2->defGtwL3))) { + + /* Prevent neigbour aging */ + fib2->age = 1; + return MV_OK; + } + fib = fib->next; + } + } + return MV_NOT_FOUND; +} + +MV_STATUS mvNfpFibRuleAge(int family, NFP_RULE_FIB *fib2) +{ + NFP_RULE_FIB *fib; + + fib = mvNfpFibLookup(family, fib2->srcL3, fib2->dstL3); + if (fib) { + fib2->age = fib->age; + fib->age = 0; + return MV_OK; + } + fib2->age = 0; + return MV_NOT_FOUND; +} + +MV_STATUS mvNfpFibRuleAdd(int family, NFP_RULE_FIB *fib2) +{ + MV_U32 hash; + NFP_RULE_FIB *fib; + + fib = mvNfpFibLookup(family, fib2->srcL3, fib2->dstL3); + if (fib) { + MV_U32 ref = fib->ref; + mvOsMemcpy(fib, fib2, sizeof(NFP_RULE_FIB)); + fib->ref = ref; + goto out; + } + + hash = mv_jhash_2addr(family, fib2->srcL3, fib2->dstL3, (u32) 0, mgr_rule_jhash_iv); + hash &= NFP_FIB_HASH_MASK; + + fib = (NFP_RULE_FIB *) mvOsMalloc(sizeof(NFP_RULE_FIB)); + if (!fib) { + mvOsPrintf("NFP (fib) %s OOM\n", __func__); + return MV_FAIL; + } + + mvOsMemcpy(fib, fib2, sizeof(NFP_RULE_FIB)); + + fib->next = fib_hash[hash]; + fib_hash[hash] = fib; +out: + NFP_DBG("NFP (fib) add %p\n", fib); + +#ifdef NFP_PNC + mvNfpPncFibAdd(fib); +#endif + + return MV_OK; +} + +MV_STATUS mvNfpFibRuleDel(int family, NFP_RULE_FIB *fib2) +{ + MV_U32 hash; + NFP_RULE_FIB *fib, *prev; + + hash = mv_jhash_2addr(family, (const MV_U8 *)&fib2->srcL3, (const MV_U8 *)&fib2->dstL3, 0, mgr_rule_jhash_iv); + hash &= NFP_FIB_HASH_MASK; + + fib = fib_hash[hash]; + prev = NULL; + + while (fib) { + if ((l3_addr_eq(family, fib->srcL3, fib2->srcL3)) && (l3_addr_eq(family, fib->dstL3, fib2->dstL3))) { + +#ifdef NFP_PNC + mvNfpPncFibDel(fib); +#endif + if (fib->ref) { + fib->flags = NFP_F_INV; + NFP_DBG("NFP (fib) del %p, retain ref=%d \n", fib, fib->ref); + return MV_OK; + } + + if (prev) + prev->next = fib->next; + else + fib_hash[hash] = fib->next; + + NFP_DBG("NFP (fib) del %p\n", fib); + mvOsFree(fib); + + return MV_OK; + } + + prev = fib; + fib = fib->next; + } + + return MV_NOT_FOUND; +} + +void mvNfpFibClean(void) +{ + int i; + NFP_RULE_FIB *fib, *next; + + for (i = 0; i < NFP_FIB_HASH_SIZE; i++) { + fib = fib_hash[i]; + while (fib) { +#ifdef NFP_PNC + mvNfpPncFibDel(fib); +#endif + next = fib->next; + mvOsFree(fib); + fib = next; + } + fib_hash[i] = NULL; + } +} + +void mvNfpFibDestroy(void) +{ + if (fib_hash != NULL) + mvOsFree(fib_hash); +} + +void mvNfpFibDump(void) +{ + MV_U32 i; + NFP_RULE_FIB *fib; + + mvOsPrintf("(fib)\n"); + for (i = 0; i < NFP_FIB_HASH_SIZE; i++) { + fib = fib_hash[i]; + + while (fib) { + mvOsPrintf(" [%4d] ", i); + mvNfpFibRulePrint(fib); + fib = fib->next; + } + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfp.h u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfp.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfp.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfp.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,450 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.h - Header File for Marvell NFP (Routing and NAT) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing (Routing and NAT). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfp_h__ +#define __mvNfp_h__ + +#include "mvSysHwConfig.h" +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvStack.h" +#include "mv802_3.h" +#include "gbe/mvEthRegs.h" +#include "pnc/mvPnc.h" + +#include "mvNfpDefs.h" + + +/* + * Port capabilities + */ +#define NFP_P_NAT 0x1 +#define NFP_P_MH 0x2 + +extern unsigned int mgr_rule_jhash_iv; + +/* The golden ration: an arbitrary value */ +#define MV_JHASH_GOLDEN_RATIO 0x9e3779b9 + +#define MV_JHASH 0x9e3779b9 +#define MV_JHASH_MIX(a, b, c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + +static INLINE MV_U32 mv_jhash_array(const MV_U8 * k, MV_U32 length, MV_U32 initval) +{ + MV_U32 a, b, c, l; + + l = length; + a = b = MV_JHASH_GOLDEN_RATIO; + c = initval; + + while (l >= 12) { + a += (k[0] + ((MV_U32) k[1] << 8) + ((MV_U32) k[2] << 16) + ((MV_U32) k[3] << 24)); + b += (k[4] + ((MV_U32) k[5] << 8) + ((MV_U32) k[6] << 16) + ((MV_U32) k[7] << 24)); + c += (k[8] + ((MV_U32) k[9] << 8) + ((MV_U32) k[10] << 16) + ((MV_U32) k[11] << 24)); + MV_JHASH_MIX(a, b, c); + k += 12; + l -= 12; + } + + c += length; + switch (l) { + case 11: + c += ((MV_U32) k[10] << 24); + case 10: + c += ((MV_U32) k[9] << 16); + case 9: + c += ((MV_U32) k[8] << 8); + case 8: + b += ((MV_U32) k[7] << 24); + case 7: + b += ((MV_U32) k[6] << 16); + case 6: + b += ((MV_U32) k[5] << 8); + case 5: + b += k[4]; + case 4: + a += ((MV_U32) k[3] << 24); + case 3: + a += ((MV_U32) k[2] << 16); + case 2: + a += ((MV_U32) k[1] << 8); + case 1: + a += k[0]; + default: + /* do nothing */; + } + + MV_JHASH_MIX(a, b, c); + return c; +} + +static INLINE MV_U32 mv_jhash_3words(MV_U32 a, MV_U32 b, MV_U32 c, MV_U32 initval) +{ + a += MV_JHASH_GOLDEN_RATIO; + b += MV_JHASH_GOLDEN_RATIO; + c += initval; + MV_JHASH_MIX(a, b, c); + + return c; +} + +static INLINE MV_U32 mv_jhash_2addr(int family, const MV_U8 * aa, const MV_U8 * ab, MV_U32 c, MV_U32 initval) +{ + MV_U32 a, b; + + if (family == MV_INET6) { + a = mv_jhash_array(aa, 16, initval); + b = mv_jhash_array(ab, 16, initval); + } else { + a = *((const MV_U32 *)(aa)); + b = *((const MV_U32 *)(ab)); + } + + return mv_jhash_3words(a, b, c, initval); +} + +/* L3 address copy. Supports AF_INET and AF_INET6 */ +static inline void l3_addr_copy(int family, u8 *dst, const u8 *src) +{ + const u32 *s = (const u32 *)src; + u32 *d = (u32 *) dst; + + *d++ = *s++; /* 4 */ + if (family == MV_INET) + return; + + *d++ = *s++; /* 8 */ + *d++ = *s++; /* 12 */ + *d++ = *s++; /* 16 */ +} + +static INLINE MV_U32 l3_addr_eq(int family, const MV_U8 * a, const MV_U8 * b) +{ + const MV_U32 *aa = (const MV_U32 *)a; + const MV_U32 *bb = (const MV_U32 *)b; + MV_U32 r; + + r = *aa++ ^ *bb++; /* 4 */ + if (family == MV_INET) + return !r; + + r |= *aa++ ^ *bb++; /* 8 */ + r |= *aa++ ^ *bb++; /* 12 */ + r |= *aa++ ^ *bb++; /* 16 */ + + return !r; +} + +#define NFP_FIB_HASH_BITS 14 +#define NFP_FIB_HASH_SIZE (1 << NFP_FIB_HASH_BITS) +#define NFP_FIB_HASH_MASK (NFP_FIB_HASH_SIZE - 1) + +#define NFP_NAT_HASH_BITS 14 +#define NFP_NAT_HASH_SIZE (1 << NFP_NAT_HASH_BITS) +#define NFP_NAT_HASH_MASK (NFP_NAT_HASH_SIZE - 1) + +#define NFP_PNC_ARRAY_SIZE ((TE_FLOW_NFP_END - TE_FLOW_NFP) + 1) + +/* + * Flags + */ +#define NFP_F_DYNAMIC 0x1 +#define NFP_F_STATIC 0x2 +#define NFP_F_INV 0x4 +#define NFP_F_SNAT 0x8 +#define NFP_F_DNAT 0x10 +#define NFP_F_BUSY 0x20 +#define NFP_F_PPPOE_ADD 0x40 +#define NFP_F_PPPOE_REMOVE 0x80 +#define NFP_F_HWF 0x100 +#define NFP_F_PARTIAL 0x200 + +struct nfp_rule_pnc; + +typedef struct nfp_rule_fib { +#ifdef NFP_FIB + struct nfp_rule_fib *next; + MV_U8 srcL3[MV_MAX_L3_ADDR_SIZE]; + MV_U8 dstL3[MV_MAX_L3_ADDR_SIZE]; + MV_U16 mh; + MV_U8 da[MV_MAC_ADDR_SIZE]; + MV_U8 sa[MV_MAC_ADDR_SIZE]; + MV_U32 age; + MV_U8 defGtwL3[MV_MAX_L3_ADDR_SIZE]; + MV_U32 flags; + void *outdev; + MV_U8 outport; +#ifdef CONFIG_MV_ETH_NFP_HWF + MV_U8 hwf_txp; + MV_U8 hwf_txq; + MV_U8 reserved; +#else + MV_U8 reserved[3]; +#endif /* CONFIG_MV_ETH_NFP_HWF */ + MV_U32 ref; + struct nfp_rule_pnc *pnc; + int family; +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_U16 sid; /* PPPoE session id */ +#endif + +#endif +} NFP_RULE_FIB; + +typedef struct nfp_rule_nat { +#ifdef NFP_NAT + struct nfp_rule_nat *next; + MV_U32 sip; + MV_U32 dip; + MV_U32 ports; + MV_U16 proto; + MV_U16 nport; + MV_U32 nip; + MV_U32 flags; + MV_U32 age; + struct nfp_rule_pnc *pnc; +#endif +} NFP_RULE_NAT; + +typedef struct nfp_rule_swf { +#ifdef NFP_SWF + struct nfp_rule_swf *next; + MV_U32 flowid; + MV_U8 port; + MV_U8 txp; + MV_U8 txq; + MV_U8 mh_sel; +#endif /* NFP_SWF */ +} NFP_RULE_SWF; + +typedef struct nfp_rule_pnc { +#ifdef NFP_PNC + NFP_RULE_FIB *fib; + NFP_RULE_NAT *nat; + MV_U32 age; + MV_U32 flowid; + MV_U16 tid; /* TCAM entry ID */ + MV_U8 ainfo; + MV_U8 pmtno; /* Number of used PMT entires */ + MV_U32 flags; + struct nfp_rule_pnc *next; +#endif /* PNC */ +} NFP_RULE_PNC; + +typedef struct { +#ifdef NFP_STAT + MV_U32 parse; + MV_U32 process; + MV_U32 process6; + MV_U32 non_ip; + MV_U32 ipv4_csum_err; + MV_U32 ipv4_frag; + MV_U32 mac_mcast; + MV_U32 ttl_exp; + MV_U32 l4_unknown; + MV_U32 l4_csum_err; + +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_U32 pppoe_add; + MV_U32 pppoe_remove; +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef NFP_FIB + MV_U32 fib_hit; + MV_U32 fib_miss; + MV_U32 fib_inv; +#endif /* NFP_FIB */ + +#ifdef NFP_NAT + MV_U32 dnat_hit; + MV_U32 dnat_miss; + MV_U32 dnat_inv; + MV_U32 snat_hit; + MV_U32 snat_miss; + MV_U32 snat_inv; +#endif /* NFP_NAT */ + +#ifdef NFP_SWF + MV_U32 swf_hit; + MV_U32 swf_miss; +#endif + +#ifdef NFP_PNC + MV_U32 pnc_in; + MV_U32 pnc_out; + MV_U32 pnc_fib_hit; + MV_U32 pnc_snat_hit; + MV_U32 pnc_dnat_hit; + MV_U32 pnc_flow_oor; + MV_U32 pnc_flow_err; + MV_U32 pnc_dnat_err; + MV_U32 pnc_fib_err; + MV_U32 pnc_snat_err; +#endif /* NFP_PNC */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_U32 pnc_pppoe_add; + MV_U32 pnc_pppoe_remove; +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#endif /* NFP_STAT */ +} NFP_STATS; + +MV_VOID mvNfpInit(MV_VOID); +MV_STATUS mvNfpRx(MV_U32 inPort, NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt); +MV_VOID mvNfpPortCapSet(MV_U32 port, MV_U32 cap, MV_U32 on); +MV_U32 mvNfpPortCapGet(MV_U32 port); + +MV_VOID mvNfpStats(MV_U32); +MV_VOID mvNfpStats(MV_U32 port); + +#ifdef NFP_FIB +extern NFP_RULE_FIB **fib_hash; + +static INLINE NFP_RULE_FIB *mvNfpFibLookup(int family, const MV_U8 *src_l3, const MV_U8 *dst_l3) +{ + MV_U32 hash; + NFP_RULE_FIB *rule; + hash = mv_jhash_2addr(family, src_l3, dst_l3, (u32) 0, mgr_rule_jhash_iv); + hash &= NFP_FIB_HASH_MASK; + rule = fib_hash[hash]; + while (rule) { + if (!(rule->family == family)) + continue; + if (l3_addr_eq(family, rule->srcL3, src_l3) && (l3_addr_eq(family, rule->dstL3, dst_l3))) + return rule; + rule = rule->next; + } + return NULL; +} + +MV_STATUS mvNfpFibInit(void); +MV_STATUS mvNfpFibRuleAdd(int family, NFP_RULE_FIB *fib2); +MV_STATUS mvNfpFibRuleDel(int family, NFP_RULE_FIB *fib2); +MV_STATUS mvNfpFibRuleAge(int family, NFP_RULE_FIB *fib2); + +MV_STATUS mvNfpFibRuleArpAdd(int family, NFP_RULE_FIB *fib2); +MV_STATUS mvNfpFibRuleArpDel(int family, NFP_RULE_FIB *fib2); +MV_STATUS mvNfpFibRuleArpAge(int family, NFP_RULE_FIB *fib2); + +void mvNfpFibDump(void); +void mvNfpFibClean(void); +void mvNfpFibDestroy(void); +#endif /* NFP_FIB */ + +#ifdef NFP_NAT +extern NFP_RULE_NAT **nat_hash; +MV_STATUS mvNfpNatInit(MV_VOID); +MV_STATUS mvNfpNatRuleAdd(NFP_RULE_NAT *rule); +MV_STATUS mvNfpNatRuleDel(NFP_RULE_NAT *rule); +MV_STATUS mvNfpNatRuleAge(NFP_RULE_NAT *rule); +void mvNfpNatDump(void); +void mvNfpNatClean(void); +void mvNfpNatDestroy(void); +#endif /* NFP_NAT */ + +#ifdef NFP_SWF +MV_STATUS mvNfpSwfInit(void); +MV_STATUS mvNfpSwfRuleAdd(NFP_RULE_SWF *rule); +MV_STATUS mvNfpSwfRuleDel(NFP_RULE_SWF *rule); +void mvNfpSwfDump(void); +MV_U32 mvNfpSwfStats(MV_U8 *buf); +MV_STATUS mvNfpSwf(MV_U32 port, NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt); +#endif /* NFP_SWF */ + +#ifdef NFP_PNC +extern NFP_RULE_PNC *pnc_hash; +MV_STATUS mvNfpPncInit(void); +MV_STATUS mvNfpPncFibAdd(NFP_RULE_FIB *rule); +MV_STATUS mvNfpPncFibDel(NFP_RULE_FIB *rule); +MV_STATUS mvNfpPncNatAdd(NFP_RULE_NAT *rule); +MV_STATUS mvNfpPncNatDel(NFP_RULE_NAT *rule); +void mvNfpPncDump(void); +MV_STATUS mvNfpPnC(MV_U32 port, NETA_RX_DESC *pRxDesc, MV_ETH_PKT *pPkt); +#endif /* NFP_PNC */ + +#endif /* __mvNfp_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpNat.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpNat.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpNat.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpNat.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,269 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpNat.c - Marvell Fast Network Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "gbe/mvNeta.h" +#include "mvNfpDefs.h" +#include "mvNfp.h" + +#define NFP_DBG(x...) mvOsPrintf(x) +/* #define NFP_DBG(x...) */ + +NFP_RULE_NAT **nat_hash = NULL; + +MV_STATUS _INIT mvNfpNatInit(MV_VOID) +{ + MV_U32 bytes = sizeof(NFP_RULE_NAT *) * NFP_NAT_HASH_SIZE; + + nat_hash = (NFP_RULE_NAT **)mvOsMalloc(bytes); + if (nat_hash == NULL) { + mvOsPrintf("NFP (nat): not enough memory\n"); + return MV_NO_RESOURCE; + } + + mvOsMemset(nat_hash, 0, bytes); + + mvOsPrintf("NFP (nat) init %d entries, %d bytes\n", NFP_NAT_HASH_SIZE, bytes); + + return MV_OK; +} + +static MV_VOID mvNfpNatRulePrint(NFP_RULE_NAT *nat) +{ + mvOsPrintf(MV_IPQUAD_FMT":%d" + "->"MV_IPQUAD_FMT":%d" + " %-2d " + "%s:"MV_IPQUAD_FMT" " + "age=%x (%p)\n", + MV_IPQUAD(nat->sip), MV_16BIT_BE(nat->ports & 0xFFFF), + MV_IPQUAD(nat->dip), MV_16BIT_BE(nat->ports >> 16), + nat->proto, nat->flags & NFP_F_DNAT ? "DNAT" : "SNAT", + MV_IPQUAD(nat->nip), nat->age, nat); +} + +static INLINE MV_U32 mvNfpNatHash(NFP_RULE_NAT *nat) +{ + int family = MV_INET; + return mv_jhash_2addr(family, (const MV_U8*) &nat->sip, (const MV_U8*) &nat->dip, nat->ports | nat->proto, + mgr_rule_jhash_iv); + +} + +static INLINE NFP_RULE_NAT *mvNfpNatLookup(NFP_RULE_NAT *nat2) +{ + MV_U32 hash; + NFP_RULE_NAT *nat; + + hash = mvNfpNatHash(nat2); + hash &= NFP_NAT_HASH_MASK; + + nat = nat_hash[hash]; + + while (nat) { + if ((nat->sip == nat2->sip) && (nat->dip == nat2->dip) && + (nat->ports == nat2->ports) && (nat->proto == nat2->proto)) + return nat; + nat = nat->next; + } + + return NULL; +} + +MV_STATUS mvNfpNatRuleAge(NFP_RULE_NAT *nat2) +{ + NFP_RULE_NAT *nat; + + nat = mvNfpNatLookup(nat2); + if (nat) { + nat2->age = nat->age; + nat->age = 0; + return MV_OK; + } + nat2->age = 0; + return MV_NOT_FOUND; +} + +MV_STATUS mvNfpNatRuleAdd(NFP_RULE_NAT *nat2) +{ + MV_U32 hash; + NFP_RULE_NAT *nat; + nat = mvNfpNatLookup(nat2); + if (nat) + return MV_OK; + hash = mvNfpNatHash(nat2); + hash &= NFP_NAT_HASH_MASK; + + nat = (NFP_RULE_NAT *)mvOsMalloc(sizeof(NFP_RULE_NAT)); + if (!nat) { + mvOsPrintf("%s: OOM\n", __func__); + return MV_FAIL; + } + + mvOsMemcpy(nat, nat2, sizeof(NFP_RULE_NAT)); + + nat->next = nat_hash[hash]; + nat_hash[hash] = nat; + + NFP_DBG("NFP (nat) add %p\n", nat); + +#ifdef NFP_PNC + mvNfpPncNatAdd(nat); +#endif + + return MV_OK; +} + +MV_STATUS mvNfpNatRuleDel(NFP_RULE_NAT *nat2) +{ + MV_U32 hash; + NFP_RULE_NAT *nat, *prev; + + hash = mvNfpNatHash(nat2); + hash &= NFP_NAT_HASH_MASK; + + nat = nat_hash[hash]; + prev = NULL; + + while (nat) { + if ((nat->sip == nat2->sip) && + (nat->dip == nat2->dip) && + (nat->ports == nat2->ports) && + (nat->proto == nat2->proto)) { + + if (prev) + prev->next = nat->next; + else + nat_hash[hash] = nat->next; +#ifdef NFP_PNC + mvNfpPncNatDel(nat); +#endif + NFP_DBG("NFP (nat) del %p\n", nat); + + mvOsFree(nat); + return MV_OK; + } + + prev = nat; + nat = nat->next; + } + + return MV_NOT_FOUND; +} + +void mvNfpNatClean(void) +{ + int i; + NFP_RULE_NAT *nat, *next; + + for (i = 0; i < NFP_NAT_HASH_SIZE; i++) { + nat = nat_hash[i]; + + while (nat) { +#ifdef NFP_PNC + mvNfpPncNatDel(nat); +#endif + next = nat->next; + mvOsFree(nat); + nat = next; + } + nat_hash[i] = NULL; + } +} + +void mvNfpNatDestroy(void) +{ + if (nat_hash) + mvOsFree(nat_hash); +} + +void mvNfpNatDump(void) +{ + MV_U32 i; + NFP_RULE_NAT *nat; + + mvOsPrintf("(nat)\n"); + for (i = 0; i < NFP_NAT_HASH_SIZE; i++) { + nat = nat_hash[i]; + + while (nat) { + mvOsPrintf(" [%2d] ", i); + mvNfpNatRulePrint(nat); + + nat = nat->next; + } + } +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpPnc.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpPnc.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpPnc.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpPnc.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,374 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpPnc.c - Marvell Fast Network Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvDebug.h" +#include "mvList.h" +#include "gbe/mvNeta.h" +#include "pnc/mvPnc.h" +#include "mvNfp.h" + +#ifdef NFP_NAT +static MV_LIST *nat_pnc_inv_list = NULL; +static MV_STATUS mvNfpPncNatFibAdd(NFP_RULE_NAT *nat, NFP_RULE_FIB *fib); +#endif /* NFP_NAT */ + +NFP_RULE_PNC *pnc_hash = NULL; + +MV_STATUS _INIT mvNfpPncInit(MV_VOID) +{ + MV_U32 bytes = sizeof(NFP_RULE_PNC) * NFP_PNC_ARRAY_SIZE; + + pnc_hash = (NFP_RULE_PNC *) mvOsMalloc(bytes); + if (pnc_hash == NULL) { + mvOsPrintf("NFP (pnc): not enough memory\n"); + return MV_NO_RESOURCE; + } + + mvOsMemset(pnc_hash, 0, bytes); + mvOsPrintf("NFP (pnc) init %d entries, %d bytes\n", NFP_PNC_ARRAY_SIZE, bytes); + + return MV_OK; +} + +static MV_VOID mvNfpPncRulePrint(NFP_RULE_PNC *rule) +{ + if (!rule->fib) + mvOsPrintf("flow=%x fib=%p nat=%p flags=0x%x age=%x\n", + rule->flowid, rule->fib, rule->nat, rule->flags, rule->age); + else + { + if (rule->fib->family==MV_INET) + mvOsPrintf("flow=%x fib=%p nat=%p flags=0x%x age=%x (IPv4)\n", + rule->flowid, rule->fib, rule->nat, rule->flags, rule->age); + else + mvOsPrintf("flow=%x fib=%p nat=%p flags=0x%x age=%x (IPv6)\n", + rule->flowid, rule->fib, rule->nat, rule->flags, rule->age); + } + mvOsPrintf("Flags: "); + if (rule->flags & NFP_F_DYNAMIC) + mvOsPrintf("NFP_F_DYNAMIC "); + if (rule->flags & NFP_F_STATIC) + mvOsPrintf("NFP_F_STATIC "); + if (rule->flags & NFP_F_INV) + mvOsPrintf("NFP_F_INV "); + if (rule->flags & NFP_F_SNAT) + mvOsPrintf("NFP_F_SNAT "); + if (rule->flags & NFP_F_DNAT) + mvOsPrintf("NFP_F_DNAT "); + if (rule->flags & NFP_F_BUSY) + mvOsPrintf("NFP_F_BUSY "); + if (rule->flags & NFP_F_PPPOE_ADD) + mvOsPrintf("NFP_F_PPPOE_ADD "); + if (rule->flags & NFP_F_PPPOE_REMOVE) + mvOsPrintf("NFP_F_PPPOE_REMOVE "); + mvOsPrintf("\n"); +} + +MV_VOID mvNfpPncDump(MV_VOID) +{ + MV_U32 i; + NFP_RULE_PNC *rule; + + mvOsPrintf("(pnc)\n"); + + for (i = 0; i < NFP_PNC_ARRAY_SIZE; i++) { + rule = pnc_hash + i; + + if (rule->flags) { + mvOsPrintf(" [%3d] ", i); + mvNfpPncRulePrint(rule); + } + } +} + +/* Returns the first available entry in the PnC array */ +/* Returns NFP_PNC_ARRAY_SIZE if no entry was found */ +static MV_U32 mvNfpPncGetFirstFree(MV_VOID) +{ + MV_U32 i; + + for (i = 0; i < NFP_PNC_ARRAY_SIZE; i++) { + if (!pnc_hash[i].flags) + break; + } + + return i; +} + +/* Returns the last available entry in the PnC array */ +/* Returns NFP_PNC_ARRAY_SIZE if no entry was found */ +static MV_U32 mvNfpPncGetLastFree(MV_VOID) +{ + MV_U32 i; + + i = NFP_PNC_ARRAY_SIZE; + do { + i--; + if (!pnc_hash[i].flags) + break; + } while (i > 0); + + if ((i == 0) && (pnc_hash[i].flags)) + return NFP_PNC_ARRAY_SIZE; + + return i; +} + +MV_STATUS mvNfpPncFibAdd(NFP_RULE_FIB *fib) +{ + MV_U32 i, rxq; + NFP_RULE_PNC *pnc = NULL; + NFP_RULE_PNC* pnc2 = NULL; + int tid1 = 0; + int tid2 = 0; + const MV_U8 *natDip; + const MV_U8 *natSip; + + int family = fib->family; + if (family == MV_INET) { + MV_U32 fibSip32 = *((u32 *) fib->srcL3); + MV_U32 fibDip32 = *((u32 *) fib->dstL3); + i = mvNfpPncGetLastFree(); + if (i < NFP_PNC_ARRAY_SIZE) { + pnc = pnc_hash + i; + pnc->flags = NFP_F_BUSY; + pnc->fib = fib; + pnc->flowid = i; + pnc->age = 0; + fib->pnc = pnc; + fib->ref++; + rxq = 0; + /* Set 2 tuples rule */ + pnc->tid = TE_FLOW_NFP + i; + pnc_ipv4_2_tuples_add(pnc->tid, pnc->flowid, fibSip32, fibDip32, rxq); + } + } else { + i = mvNfpPncGetLastFree(); + if (i < NFP_PNC_ARRAY_SIZE) { + pnc = pnc_hash + i; + pnc->flags = NFP_F_BUSY; + pnc->fib = fib; + pnc->flowid = i; + pnc->age = 0; + fib->pnc = pnc; + fib->ref++; + rxq = 0; + /* Set 2 tuples rule */ + pnc->tid = TE_FLOW_NFP + i; + tid1 = pnc->tid; + } + i = mvNfpPncGetLastFree(); + if (i < NFP_PNC_ARRAY_SIZE) { + tid2 = TE_FLOW_NFP + i; + pnc2 = pnc_hash + i; + pnc2->flags = NFP_F_BUSY; + pnc2->fib = fib; + pnc2->flowid = i; + } + pnc_ipv6_2_tuples_add(tid1, tid2, pnc->flowid, fib->srcL3, fib->dstL3, rxq); + } + +#ifdef NFP_NAT + /* Try to complete incomplete NAT rule */ + { + MV_LIST *list = nat_pnc_inv_list; + NFP_RULE_NAT *nat; + while (list) { + nat = (NFP_RULE_NAT *) list->data; + natSip = (const MV_U8 *)&nat->sip; + if (nat->flags & NFP_F_DNAT) + natDip = (const MV_U8 *)&nat->nip; + else + natDip = (const MV_U8 *)&nat->dip; + + if ((l3_addr_eq(family, fib->srcL3, natSip)) && (l3_addr_eq(family, fib->dstL3, natDip))) { + /* complete PNC entry */ + mvNfpPncNatFibAdd(nat, fib); + list = mvListDel(&list); + } else + list = list->next; + } + } +#endif /* NFP_NAT */ + + return MV_OK; +} + + +MV_STATUS mvNfpPncFibDel(NFP_RULE_FIB *fib) +{ + NFP_RULE_PNC *pnc = fib->pnc; + + if (pnc) { + if (pnc->fib != fib) { + mvOsPrintf("NFP (pnc) bug pnc=%p pnc->fib=%p fib=%p\n", pnc, pnc->fib, fib); + goto out; + } + pnc_te_del(pnc->tid); + + pnc->fib = NULL; + pnc->nat = NULL; + pnc->flowid = 0; + pnc->flags = 0; + pnc->tid = 0; + fib->pnc = NULL; + fib->ref--; + } + +out: + return MV_OK; +} + +#ifdef NFP_NAT + +static MV_STATUS mvNfpPncNatFibAdd(NFP_RULE_NAT *nat, NFP_RULE_FIB *fib) +{ + NFP_RULE_PNC *pnc; + MV_U32 i, rxq; + + i = mvNfpPncGetFirstFree(); + if (i < NFP_PNC_ARRAY_SIZE) { + pnc = pnc_hash + i; + + pnc->nat = nat; + pnc->fib = fib; + pnc->fib->ref++; + + pnc->flags = NFP_F_BUSY; + pnc->flowid = i; + nat->pnc = pnc; + rxq = 0; + + /* Add TCAM entry */ + pnc->tid = TE_FLOW_NFP + i; + pnc_ipv4_5_tuples_add(pnc->tid, pnc->flowid, nat->sip, nat->dip, nat->proto, nat->ports, rxq); + } + + return MV_OK; + +} + +MV_STATUS mvNfpPncNatAdd(NFP_RULE_NAT *nat) +{ + NFP_RULE_FIB *fib; + + int family = MV_INET; + const MV_U8 *natSip = (const MV_U8 *)&nat->sip; + const MV_U8 *natDip = (const MV_U8 *)&nat->dip; + const MV_U8 *natNip = (const MV_U8 *)&nat->nip; + + if (nat->flags & NFP_F_DNAT) + fib = mvNfpFibLookup(family, natSip, natNip); + else + fib = mvNfpFibLookup(family, natSip, natDip); + + if (fib) + return mvNfpPncNatFibAdd(nat, fib); + + mvOsPrintf("NFP (pnc) no route for %s: " MV_IPQUAD_FMT "->" MV_IPQUAD_FMT " nip=" MV_IPQUAD_FMT "\n", + (nat->flags & NFP_F_DNAT) ? "DNAT" : "SNAT", MV_IPQUAD(nat->sip), + MV_IPQUAD(nat->dip), MV_IPQUAD(nat->nip)); + + /* remember incomplete NAT entry */ + mvListAddHead(&nat_pnc_inv_list, (MV_ULONG) nat); + + return MV_NOT_READY; +} + +MV_STATUS mvNfpPncNatDel(NFP_RULE_NAT *nat) +{ + NFP_RULE_PNC *pnc = nat->pnc; + + if (pnc) { + if (pnc->nat != nat) { + mvOsPrintf("NFP (pnc) bug pnc=%p pnc->nat=%p nat=%p\n", pnc, pnc->nat, nat); + goto out; + } + + if (pnc->fib) + pnc->fib->ref--; + + pnc_te_del(pnc->tid); + + pnc->fib = NULL; + pnc->nat = NULL; + pnc->flowid = 0; + pnc->flags = 0; + nat->pnc = NULL; + } +out: + return MV_OK; +} +#endif /* NFP_NAT */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSec.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSec.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSec.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSec.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,213 @@ +// mvNfpSec.c + +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "mvNfpSec.h" + + +static MV_NFP_SEC_STATE nfpSecStates[NFP_SEC_MAX_STATES]; +static MV_NFP_SEC_RULE **nfpSecRuleDb; +static MV_U32 nfpSecRuleDbSize; +static MV_U32 nfp_sec_jhash_iv; + +#define NFP_MAGIC 0x4E465021 /* "NFP!" */ + +//extern void nfp_cesa_lock(void); +//extern void nfp_cesa_unlock(void); + +//tmp +void nfp_cesa_lock(void) +{ +} +void nfp_cesa_unlock(void) +{ +} + + +static MV_STATUS mvNfpSecAhIn(MV_NFP_SEC_INFO *info) +{ + MV_STATUS status; + // tmp + return status; +} + +static MV_STATUS mvNfpSecPacketInject(MV_NFP_SEC_INFO *info) +{ + // MV_NFP_STATS *pNfpStats; + MV_U32 headerLength; + +} + +static MV_STATUS mvNfpSecEspIn(MV_NFP_SEC_INFO *info) +{ + MV_CESA_CRYPTO_ALG enc; + MV_CESA_MAC_MODE mac; + MV_CESA_COMMAND *cmd; + MV_STATUS status; + MV_U8 *byte; + info->hLen += sizeof(MV_ESP_HEADER); + enc = info->pEspRule->state->cesaSessionIn.cryptoAlgorithm; + mac = info->pEspRule->state->cesaSessionIn.macMode; + if (enc == MV_CESA_CRYPTO_NULL && mac == MV_CESA_MAC_NULL) + { + byte = info->pPkt->pFrags->bufVirtPtr + + info->pPkt->pFrags->dataSize - info->tLen - 1; + info->proto = *byte--; + info->tLen = *byte+2; + return mvNfpSecPacketInject(info); + } +// info->receiver = mvNfpSecEspPostIn; + cmd = &info->cesaCommand; + memset(cmd, 0, sizeof(MV_CESA_COMMAND)); + cmd->pReqPrv = info; + cmd->pSrc = &info->cesaMbuf; + cmd->pDst = &info->cesaMbuf; + cmd->sessionId = info->pEspRule->state->cesaSidIn; + + if (enc != MV_CESA_CRYPTO_NULL) + { +// cmd->ivOffset = (MV_U8*)info->pEspHdr - (MV_U8*) + } + +} + + + +MV_VOID mvNfpSecStateDestroy(MV_NFP_SEC_STATE *state) +{ + state->refCnt -= 1; + if (!state->refCnt) { + nfp_cesa_lock(); + mvCesaSessionClose(state->cesaSidIn); + mvCesaSessionClose(state->cesaSidOut); + nfp_cesa_unlock(); + } +} + + +MV_VOID mvNfpSecRuleDelete(MV_NFP_SEC_RULE *pRule) + { + + MV_NFP_SEC_STATE *state = pRule->state; + mvOsFree(pRule); + mvNfpSecStateDestroy(state); + } + +MV_STATUS mvNfpSecInit(MV_U32 dbSize) + { + if(dbSize == 0) + return MV_BAD_PARAM; + + nfpSecRuleDbSize = dbSize; + nfpSecRuleDb = mvOsMalloc(dbSize * sizeof(MV_NFP_SEC_RULE *)); + if (!nfpSecRuleDb) + return MV_NO_RESOURCE; + + memset(nfpSecStates, 0, sizeof(nfpSecStates)); + memset(nfpSecRuleDb, 0, dbSize * sizeof(MV_NFP_SEC_RULE *)); + + nfp_sec_jhash_iv = mvOsRand(); + + return MV_OK; + +} + + + +MV_NFP_SEC_RULE *mvNfpSecRuleFind(int family, const MV_U8 *dstL3, + const MV_U8 *srcL3, MV_U32 proto, MV_U32 spi) + { + + MV_NFP_SEC_RULE *pPrevRule, *pRule, *tmp; + MV_U32 hash; + + hash = mv_jhash_2addr(family, dstL3, srcL3, 0, nfp_sec_jhash_iv); + hash &= (nfpSecRuleDbSize - 1); + + pPrevRule = NULL; + pRule = nfpSecRuleDb[hash]; + + while (pRule) { + if (!pRule->state->osState) { + tmp = pRule; + + if (pPrevRule) + pRule = pPrevRule->next = pRule->next; + else + pRule = nfpSecRuleDb[hash] = pRule->next; + + mvNfpSecRuleDelete(tmp); + continue; + } + + if (pRule->family == family && + l3_addr_eq(family, pRule->dstL3, dstL3) && + l3_addr_eq(family, pRule->srcL3, srcL3) && + pRule->state->proto == proto && + (pRule->state->spi == spi || spi == 0)) + break; + + pPrevRule = pRule; + pRule = pRule->next; + } + + return pRule; + } + +MV_STATUS mvNfpSecRuleInsert(int family, const MV_U8 *dstL3, const MV_U8 *srcL3, + MV_NFP_SEC_STATE *state) + { + MV_NFP_SEC_RULE *pRule; + MV_U32 hash; + if (mvNfpSecRuleFind(family, dstL3, srcL3, state->proto, state->spi)) + return MV_ALREADY_EXIST; + pRule = mvOsMalloc(sizeof(MV_NFP_SEC_RULE)); + if (!pRule) + return MV_NO_RESOURCE; + pRule->family = family; + pRule->state = state; + l3_addr_copy(family, pRule->dstL3, dstL3); + + l3_addr_copy(family, pRule->srcL3, srcL3); + + state->refCnt += 1; + hash = mv_jhash_2addr(family, dstL3, srcL3, 0, nfp_sec_jhash_iv); + hash &= (nfpSecRuleDbSize-1); + pRule->next = nfpSecRuleDb[hash]; + nfpSecRuleDb[hash] = pRule; + return MV_OK; + } + +MV_STATUS mvNfpProcessIn(MV_U32 ifIndex, MV_NFP_SEC_RULE *pAhRule, + MV_NFP_SEC_RULE *pEspRule, MV_IP_HEADER *pIpHdr, + MV_AH_HEADER *pAhHdr, MV_ESP_HEADER *pEspHdr) +{ + MV_NFP_SEC_INFO *info; + MV_STATUS status; + info = mvOsMalloc(sizeof(MV_NFP_SEC_INFO)); + if (!info) + return MV_NO_RESOURCE; + info->magic = NFP_MAGIC; + info->ifIndex = ifIndex; + // info->pFpStats = pFpStats; + info->pAhRule = pAhRule; + info->pEspRule = pEspRule; + info->pIpHdr = pIpHdr; + info->pAhHdr = pAhHdr; + info->pEspHdr = pEspHdr; + if (pAhRule) + status = mvNfpSecAhIn(info); + else if (pEspRule) + status = mvNfpSecEspIn(info); + else + status = MV_BAD_PARAM; + if (status == MV_OK) { + mvOsPrintf("%s\n",__FUNCTION__); + mvOsFree(info); + } + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSec.h u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSec.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSec.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSec.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,105 @@ +// nfp/mvNfpSec.h + +#ifndef NFP_MVNFPSEC_H +#define NFP_MVNFPSEC_H + +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" + +#include "cesa/mvCesa.h" +#include "gbe/mvNeta.h" +#include "nfp/mvNfp.h" + +#ifdef CONFIG_MV_ETH_NFP_SEC + + +typedef struct { + /* Cesa sessions */ + MV_U16 cesaSidIn; + + MV_CESA_OPEN_SESSION cesaSessionIn; + MV_U16 cesaSidOut; + MV_CESA_OPEN_SESSION cesaSessionOut; + + MV_U8 proto; + MV_U32 spi; + MV_U32 outSeqNum; + MV_VOID *osState; + + /* Reference count */ + unsigned int refCnt; +} MV_NFP_SEC_STATE; + +typedef struct __MV_NFP_SEC_RULE { + MV_U32 family; + MV_U8 dstL3[MV_MAX_L3_ADDR_SIZE]; + MV_U8 srcL3[MV_MAX_L3_ADDR_SIZE]; + MV_NFP_SEC_STATE *state; + struct __MV_NFP_SEC_RULE *next; +} MV_NFP_SEC_RULE; + +// TBD: should this define be here ? or in mv_hal/cesa/mvCesa.h +#define MV_CESA_NFP_RESERVED_SESSIONS 64 + +#define NFP_HMAC_LENGTH 12 +#define NFP_SEC_MAX_STATES (MV_CESA_NFP_RESERVED_SESSIONS / 2) + +typedef struct __MV_NFP_SEC_INFO { + MV_U32 magic; + MV_CESA_COMMAND cesaCommand; + MV_CESA_MBUF cesaMbuf; + + MV_U32 ifIndex; + MV_PKT_INFO *pPkt; +// MV_FP_STATS *pFpStats; + MV_NFP_SEC_RULE *pAhRule; + MV_NFP_SEC_RULE *pEspRule; + MV_IP_HEADER *pIpHdr; + MV_AH_HEADER *pAhHdr; + MV_ESP_HEADER *pEspHdr; + + MV_STATUS (*receiver)(struct __MV_NFP_SEC_INFO *); + MV_IP_HEADER ipHdr; + MV_U8 digest[NFP_HMAC_LENGTH]; + + MV_U16 hLen; + MV_U16 tLen; + MV_U8 proto; +} MV_NFP_SEC_INFO; + +extern MV_STATUS mvNfpSecInit(MV_U32 dbSize); +/* +extern MV_VOID *mvFpSecStateCreate(MV_CESA_CRYPTO_ALG enc, const MV_U8 *encKey, + MV_U8 encKeyLen, MV_CESA_MAC_MODE mac, const MV_U8 *macKey, + MV_U8 macKeyLen, MV_U8 proto, MV_U32 spi, MV_U32 outSeqNum, + MV_VOID *osState); +extern MV_VOID mvFpSecStateMarkDead(MV_FP_SEC_STATE *state); +extern MV_VOID mvFpSecStateDestroy(MV_FP_SEC_STATE *state); +*/ +extern MV_NFP_SEC_RULE *mvNfpSecRuleFind(int family, const MV_U8 *dstL3, + const MV_U8 *srcL3, MV_U32 proto, MV_U32 spi); + +extern MV_STATUS mvNfpSecRuleInsert(int family, const MV_U8 *dstL3, const MV_U8 *srcL3, + MV_NFP_SEC_STATE *state); +/* + +extern MV_VOID mvFpSecRuleDelete(MV_FP_SEC_RULE *pRule); +extern MV_U32 mvFpSecGetOutSeqNum(MV_FP_SEC_STATE *state); +extern MV_VOID mvFpSecSetOutSeqNum(MV_FP_SEC_STATE *state, MV_U32 seqNum); + +extern MV_STATUS mvFpSecProcessDone(MV_FP_SEC_INFO *info); +extern MV_STATUS mvFpSecProcessIn(MV_U32 ifIndex, MV_PKT_INFO *pPkt, + MV_FP_STATS *pFpStats, MV_FP_SEC_RULE *pAhRule, + MV_FP_SEC_RULE *pEspRule, MV_IP_HEADER *pIpHdr, + MV_AH_HEADER *pAhHdr, MV_ESP_HEADER *pEspHdr); +extern MV_STATUS mvFpSecProcessOut(MV_U32 ifIndex, MV_PKT_INFO *pPkt, + MV_FP_STATS *pFpStats, MV_FP_SEC_RULE *pAhRule, + MV_FP_SEC_RULE *pEspRule, MV_IP_HEADER *pIpHdr); + +extern MV_VOID mvFpSecDbPrint(MV_VOID); +*/ + +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSwf.c u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSwf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/nfp/mvNfpSwf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/nfp/mvNfpSwf.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,296 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpSwf.c - Marvell Fast Network Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "gbe/mvNeta.h" +#include "mvNfp.h" + +#if 1 +#define NFP_DBG mvOsPrintf +#else +#define NFP_DBG +#endif + +#ifdef NFP_STAT +#define NFP_INC(p, s) nfp_stats[p].s++; +#else +#define NFP_INC(p, s) +#endif + +#define NFP_SWF_HASH_BITS 5 +#define NFP_SWF_HASH_SIZE (1<flowid == flowid) + return rule; + rule = rule->next; + } + + return NULL; +} + +MV_STATUS mvNfpSwfRuleAdd(NFP_RULE_SWF *rule2) +{ + MV_U32 hash; + NFP_RULE_SWF *rule; + + hash = mvNfpSwfRuleHash(rule2->flowid); + hash &= NFP_SWF_HASH_MASK; + + rule = nfp_swf_hash[hash]; + + while (rule) { + if (rule->flowid == rule2->flowid) + goto out; + + rule = rule->next; + } + + rule = (NFP_RULE_SWF *) mvOsMalloc(sizeof(NFP_RULE_SWF)); + + if (!rule) { + mvOsPrintf("%s: OOM\n", __func__); + return MV_FAIL; + } + + rule->next = nfp_swf_hash[hash]; + nfp_swf_hash[hash] = rule; +out: + /* + * Port mapping: + * 0 - cpu, 1 - gbe0, 2 - gbe1 + * 3..10 - tcont 0..7 + */ + if (rule2->txp <= 2) { + rule->port = rule2->txp - 1; + rule->txp = 0; + } else { + rule->port = 2; + rule->txp = rule2->txp - 3; + } + rule->flowid = rule2->flowid; + rule->txq = rule2->txq; + rule->mh_sel = rule2->mh_sel; + +#ifdef NFP_DBG + mvOsPrintf("NFP (swf) set flowid=%x port=%d txp=%x txq=%x mh=%x\n", + rule->flowid, rule->port, rule->txp, rule->txq, rule->mh_sel); +#endif + return MV_OK; +} + +MV_STATUS mvNfpSwfRuleDel(NFP_RULE_SWF *rule2) +{ + MV_U32 hash; + NFP_RULE_SWF *rule, *prev; + + hash = mvNfpSwfRuleHash(rule2->flowid); + hash &= NFP_SWF_HASH_MASK; + + rule = nfp_swf_hash[hash]; + prev = NULL; + + while (rule) { + if (rule->flowid == rule2->flowid) { + + if (prev) + prev->next = rule->next; + else + nfp_swf_hash[hash] = rule->next; +#ifdef NFP_DBG + mvOsPrintf("NFP (swf) del flowid=%x\n", rule->flowid); +#endif + mvOsFree(rule); + + return MV_OK; + } + + prev = rule; + rule = rule->next; + } + + return MV_NOT_FOUND; +} + +MV_VOID mvNfpSwfDump(MV_VOID) +{ + MV_U32 i; + NFP_RULE_SWF *rule; + + mvOsPrintf("(swf)\n"); + for (i = 0; i < NFP_SWF_HASH_SIZE; i++) { + rule = nfp_swf_hash[i]; + + while (rule) { + mvOsPrintf("NFP (swf) [%2d] flowid=0x%x port=%d txp=%d txq=%d mh=%x\n", + i, rule->flowid, rule->port, rule->txp, rule->txq, rule->mh_sel); + rule = rule->next; + } + } +} + +MV_STATUS mvNfpSwf(MV_U32 rxPort, NETA_RX_DESC * rxDesc, MV_ETH_PKT * pPkt) +{ + NFP_RULE_SWF *rule; + + rule = mvNfpSwfLookup(rxDesc->pncFlowId); + + if (!rule) { + NFP_INC(rxPort, swf_miss); + return MV_NOT_FOUND; + } + + NFP_INC(rxPort, swf); + + pPkt->hw_cmd = rxDesc->hw_cmd & (NETA_RX_GEM_PID_MASK | NETA_RX_COLOR_MASK); + pPkt->hw_cmd |= ((rxDesc->hw_cmd & NETA_RX_DSA_MASK) >> NETA_RX_DSA_OFFS) << NETA_TX_DSA_OFFS; + pPkt->hw_cmd |= rxDesc->pncFlowId << NETA_TX_MOD_CMD_OFFS; + pPkt->hw_cmd |= rule->mh_sel << NETA_TX_MH_SEL_OFFS; + + pPkt->tx_cmd = NETA_TX_L4_CSUM_NOT | NETA_TX_PKT_OFFSET_MASK(pPkt->offset); + + /* Process 2B of MH */ + if (rule->mh_sel == (NETA_TX_MH_UNCHANGE >> NETA_TX_MH_SEL_OFFS)) { + MV_U16 *pMh = (MV_U16 *) (pPkt->pBuf + pPkt->offset); + +/* *pMh = mvNfpPortTxMhGet(rule->port); - To be FIXED */ + mvOsCacheLineFlushInv(NULL, pMh); + } + pPkt->port = rule->port; + pPkt->txp = rule->txp; + pPkt->txq = rule->txq; + + return MV_OK; +} + +MV_U32 mvNfpSwfStats(MV_U8 *buf) +{ + MV_U32 port, off = 0; + + off += mvOsSPrintf(buf + off, "swf_hits...."); + for (port = 0; port < NFP_PORT_MAX; port++) + off += mvOsSPrintf(buf + off, "%4u ", nfp_stats[port].swf); + off += mvOsSPrintf(buf + off, "\n"); + + off += mvOsSPrintf(buf + off, "swf_miss...."); + for (port = 0; port < NFP_PORT_MAX; port++) + off += mvOsSPrintf(buf + off, "%4u ", nfp_stats[port].swf_miss); + off += mvOsSPrintf(buf + off, "\n"); + + mvOsMemset(&nfp_stats[port], 0, sizeof(NFP_SWF_STATS)); + + return off; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pmt/mvPmt.c u-boot-2009.08/board/marvell/mv_hal/neta/pmt/mvPmt.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pmt/mvPmt.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pmt/mvPmt.c 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,226 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" /* Should be included before mvSysHwConfig */ +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvOs.h" + +#include "gbe/mvNeta.h" + +#include "mvPmt.h" + +/*#define PMT_DBG mvOsPrintf*/ +#define PMT_DBG(X...) + +/******************************************************************************* +* mvNetaPmtWrite - Add entry to Packet Modification Table +* DESCRIPTION: +* +* INPUT: +* int port - NETA port number +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* +* NOTE: +*******************************************************************************/ +MV_STATUS mvNetaPmtWrite(int port, int idx, MV_NETA_PMT *pEntry) +{ + if (mvNetaPortCheck(port)) + return MV_OUT_OF_RANGE; + + if (mvNetaMaxCheck(idx, NETA_TX_PMT_SIZE)) + return MV_OUT_OF_RANGE; + + PMT_DBG("%s: 0x%08x <-- 0x%x\n", __func__, NETA_TX_PMT_REG(port), idx); + MV_REG_WRITE(NETA_TX_PMT_REG(port), (MV_U32) idx); + MV_REG_WRITE(NETA_TX_PMT_W0_REG(port), pEntry->mt_w0 & NETA_TX_PMT_W0_MASK); + MV_REG_WRITE(NETA_TX_PMT_W1_REG(port), pEntry->mt_w1 & NETA_TX_PMT_W1_MASK); + MV_REG_WRITE(NETA_TX_PMT_W2_REG(port), pEntry->mt_w2 & NETA_TX_PMT_W2_MASK); + + return MV_OK; +} +/******************************************************************************* +* mvNetaPmtRead - Read entry from Packet Modification Table +* DESCRIPTION: +* +* INPUT: +* int port - NETA port number +* int inx - PMT entry index to read from +* OUTPUT: +* MV_NETA_PMT pEntry - PMT entry +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* +* NOTE: +*******************************************************************************/ +MV_STATUS mvNetaPmtRead(int port, int idx, MV_NETA_PMT *pEntry) +{ + if (mvNetaPortCheck(port)) + return MV_OUT_OF_RANGE; + + if (mvNetaMaxCheck(idx, NETA_TX_PMT_SIZE)) + return MV_OUT_OF_RANGE; + + PMT_DBG("%s: 0x%08x <-- 0x%x\n", __func__, NETA_TX_PMT_REG(port), idx); + + MV_REG_WRITE(NETA_TX_PMT_REG(port), (MV_U32) idx); + pEntry->mt_w0 = MV_REG_READ(NETA_TX_PMT_W0_REG(port)); + pEntry->mt_w1 = MV_REG_READ(NETA_TX_PMT_W1_REG(port)); + pEntry->mt_w2 = MV_REG_READ(NETA_TX_PMT_W2_REG(port)); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaPmtInit - Clear Packet Modification Table +* DESCRIPTION: +* +* INPUT: +* int port - NETA port number +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* +* NOTE: +*******************************************************************************/ +MV_STATUS mvNetaPmtInit(int port) +{ + int idx; + MV_NETA_PMT entry; + + if (mvNetaPortCheck(port)) + return MV_OUT_OF_RANGE; + + memset(&entry, 0, sizeof(MV_NETA_PMT)); + + for (idx = 0; idx < NETA_TX_PMT_SIZE; idx++) + mvNetaPmtWrite(port, idx, &entry); + + return MV_OK; +} + +/******************************************************************************* +* mvNetaPmtDump - Dump Packet Modification Table +* DESCRIPTION: +* +* INPUT: +* int port - NETA port number +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* +* NOTE: +*******************************************************************************/ +MV_STATUS mvNetaPmtDump(int port) +{ + int idx, count = 0; + MV_NETA_PMT entry; + + if (mvNetaPortCheck(port)) + return MV_OUT_OF_RANGE; + + for (idx = 0; idx < NETA_TX_PMT_SIZE; idx++) { + mvNetaPmtRead(port, idx, &entry); + if (entry.mt_w0 || entry.mt_w1 || entry.mt_w2) { + count++; + mvOsPrintf("[%2x] 0x%08x 0x%08x 0x%08x\n", idx, entry.mt_w0, entry.mt_w1, entry.mt_w2); + } + } + + if (!count) + mvOsPrintf("PMT is empty, %d entries\n", NETA_TX_PMT_SIZE); + + return MV_OK; +} + +/* Set MH register */ +MV_STATUS mvNetaPmtMhRegSet(int port, int txp, int reg, MV_U16 val) +{ + if (mvNetaTxpCheck(port, txp)) + return MV_OUT_OF_RANGE; + + if (mvNetaMaxCheck(reg, NETA_TX_MAX_MH_REGS)) + return MV_OUT_OF_RANGE; + + MV_REG_WRITE(NETA_TX_MH_REG(port, txp, reg), val); + + return MV_OK; +} + +/* Set ETH_TYPE register */ +MV_STATUS mvNetaPmtEthTypeRegSet(int port, int txp, int reg, MV_U16 val) +{ + if (mvNetaTxpCheck(port, txp)) + return MV_OUT_OF_RANGE; + + if (mvNetaMaxCheck(reg, NETA_TX_MAX_ETH_TYPE_REGS)) + return MV_OUT_OF_RANGE; + + MV_REG_WRITE(NETA_TX_ETH_TYPE_REG(port, txp, reg), val); + + return MV_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pmt/mvPmt.h u-boot-2009.08/board/marvell/mv_hal/neta/pmt/mvPmt.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pmt/mvPmt.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pmt/mvPmt.h 2011-04-04 13:57:34.995595820 -0400 @@ -0,0 +1,95 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __mvPmt_h__ +#define __mvPmt_h__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" + +typedef struct mv_neta_pmt_t{ + MV_U16 mt_w0; /* W0 - bits[15-0] */ + MV_U32 mt_w1; /* W1 - bits[31-0] */ + MV_U32 mt_w2; /* W2 - bits[26-0] */ +} MV_NETA_PMT; + +MV_STATUS mvNetaPmtWrite(int port, int idx, MV_NETA_PMT *pEntry); +MV_STATUS mvNetaPmtRead(int port, int idx, MV_NETA_PMT *pEntry); +MV_STATUS mvNetaPmtInit(int port); +MV_STATUS mvNetaPmtDump(int port); +void mvNetaPmtRegs(int port, int txp); +MV_STATUS mvNetaPmtMhRegSet(int port, int txp, int reg, MV_U16 val); +MV_STATUS mvNetaPmtEthTypeRegSet(int port, int txp, int reg, MV_U16 val); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __mvPmt_h__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvPnc.c u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvPnc.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvPnc.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvPnc.c 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,1354 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mv802_3.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +#include "mvPnc.h" +#include "mvTcam.h" + +#include "gbe/mvNetaRegs.h" +#include "gbe/mvEthRegs.h" + +/* + * PNC debug + */ +/*#define PNC_DBG mvOsPrintf*/ +#define PNC_DBG(X...) + +/* + * PNC errors + */ +#define PNC_ERR mvOsPrintf +/*#define PNC_ERR(X...)*/ + +MV_U8 *mvPncVirtBase = NULL; +/* + * Local variables + */ +static int pnc_inited; +static int rxq_mac_bc = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_mac_mc = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_vlan = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_ip6 = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_ip4 = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_ip4_tcp = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_ip4_udp = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_ip4_igmp = CONFIG_MV_ETH_RXQ_DEF; +static int rxq_arp = CONFIG_MV_ETH_RXQ_DEF; + +static int pnc_port_map(int pnc_port) +{ + switch (pnc_port) { + case 2: + return 0; + + case 4: + return 1; + + case 0: + return 2; + + default: + mvOsPrintf("%s: pnc_port=%d is out of range\n", __func__, pnc_port); + return -1; + } +} + +static int pnc_eth_port_map(int eth_port) +{ + switch (eth_port) { + case 0: + return 2; + + case 1: + return 4; + + case 2: + return 0; + + default: + mvOsPrintf("%s: eth_port=%d is out of range\n", __func__, eth_port); + return -1; + } +} + +/* pnc port setting: data: 0 for all bits, mask: 0 - for accepted ports, 1 - for rejected ports */ +static unsigned int pnc_port_mask_update(unsigned int mask, int eth_port, int add) +{ + int pnc_port = pnc_eth_port_map(eth_port); + + if (pnc_port < 0) + return mask; + + if (add) + mask &= ~(1 << pnc_port); + else + mask |= (1 << pnc_port); + + return mask; +} + +static unsigned int pnc_port_mask(int eth_port) +{ + unsigned int mask; + int pnc_port = pnc_eth_port_map(eth_port); + + if (pnc_port < 0) + return 0; + + mask = (~(1 << pnc_port)) & PORT_MASK; + return mask; +} + +/****************************************************************************** + * + * Marvell/GPON Header Section + * + ****************************************************************************** + */ +int pnc_mh_omci(unsigned int port, unsigned short data, unsigned short mask) +{ + struct tcam_entry *te = NULL; + + PNC_DBG("%s\n", __func__); + + te = tcam_sw_alloc(TCAM_LU_MAC); + + sram_sw_set_rinfo(te, RI_OMCI); + sram_sw_set_lookup_done(te, 1); + tcam_sw_set_port(te, 0, pnc_port_mask(port)); + + tcam_sw_set_byte(te, 0, data >> 8); + tcam_sw_set_mask(te, 0, mask >> 8); + + tcam_sw_set_byte(te, 1, data & 0xFF); + tcam_sw_set_mask(te, 1, mask & 0xFF); + + tcam_sw_text(te, "mh_omci"); + + tcam_hw_write(te, TE_MH_OMCI); + + tcam_sw_free(te); + + return 0; +} + +/****************************************************************************** + * + * MAC Address Section + * + ****************************************************************************** + */ + +/* Get TCAM entry if valid, NULL if invalid */ +static struct tcam_entry *pnc_tcam_entry_get(int tid) +{ + struct tcam_entry *te; + + te = tcam_sw_alloc(0); + + tcam_hw_read(te, tid); + + if (te->ctrl.flags & TCAM_F_INV) { + tcam_sw_free(te); + return NULL; + } + return te; +} + +/* + * pnc_mac_fc_drop - Add Flow Control MAC address match rule to the MAC section + * to drop PAUSE frames arriving without Marvell Header on all ports + */ +static void pnc_mac_fc_drop(void) +{ + struct tcam_entry *te = NULL; + unsigned char da[6] = { 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 }; + unsigned int len = MV_MAC_ADDR_SIZE; + + te = tcam_sw_alloc(TCAM_LU_MAC); + + /* set match on DA */ + while (len--) + tcam_sw_set_byte(te, len, da[len]); + + /* port id match */ + tcam_sw_set_port(te, 0, 0); /* all ports */ + + /* result info bit */ + sram_sw_set_rinfo(te, RI_DROP); + + tcam_sw_text(te, "flow control"); + sram_sw_set_lookup_done(te, 1); + + tcam_hw_write(te, TE_MAC_FLOW_CTRL); + tcam_sw_free(te); +} + +/* + * pnc_mac_da - Add DA MAC address match rule to the MAC section + * @da: destination MAC address + * @len: destination MAC address length to match on: 0..6 + * @port_mask: source port id: 0..1F or ANY + * @rxq: rx queue + * @rinfo: result info bits to set + */ +static struct tcam_entry *pnc_mac_da(unsigned char *da, unsigned int len, + unsigned int port_mask, int rxq, unsigned int rinfo) +{ + struct tcam_entry *te = NULL; + + if (len > MV_MAC_ADDR_SIZE) + goto out; + + if (rinfo >= BIT24) + goto out; + + te = tcam_sw_alloc(TCAM_LU_MAC); + + /* set match on DA */ + while (len--) + tcam_sw_set_byte(te, MV_ETH_MH_SIZE + len, da[len]); + + /* port id match */ + tcam_sw_set_port(te, 0, port_mask); + + /* result info bit */ + sram_sw_set_rinfo(te, rinfo); + + /* set rx queue */ + sram_sw_set_rxq(te, rxq); + + /* shift to ethertype */ + sram_sw_set_shift_update(te, 0, MV_ETH_MH_SIZE + 2 * MV_MAC_ADDR_SIZE); + sram_sw_set_next_lookup(te, TCAM_LU_L2); +out: + return te; +} + +/* + * pnc_mac_me - Add DA MAC address of port + * @mac: destination MAC address or NULL for promiscuous + * @port: ingress giga port number + */ +int pnc_mac_me(unsigned int port, unsigned char *mac, int rxq) +{ + struct tcam_entry *te; + int len = MV_MAC_ADDR_SIZE; + char text[TCAM_TEXT]; + unsigned int port_mask = pnc_port_mask(port); + + if (port_mask < 0) + return 1; + + if (!mac) + len = 0; + + te = pnc_mac_da(mac, len, port_mask, rxq, RI_DA_ME); + sprintf(text, "%s%d", "ucast_me", port); + tcam_sw_text(te, text); + + tcam_hw_write(te, TE_MAC_ME + port); + tcam_sw_free(te); + + return 0; +} + +/* + * pnc_mcast_all - Accept all MAC multicast of port + * @port: ingress giga port number. + * @en: 1 - Accept ALL MCAST, 0 - Discard ALL MCAST + */ +int pnc_mcast_all(unsigned int port, int en) +{ + struct tcam_entry *te; + unsigned int data, mask; + + te = pnc_tcam_entry_get(TE_MAC_MC_ALL); + if (te == NULL) { + mvOsPrintf("%s: MC_ALL entry (tid=%d) is invalid\n", __func__, TE_MAC_MC_ALL); + return 1; + } + + /* Update port mask */ + tcam_sw_get_port(te, &data, &mask); + mask = pnc_port_mask_update(mask, port, en); + + tcam_sw_set_port(te, data, mask); + tcam_sw_text(te, "mcast_all"); + + tcam_hw_write(te, TE_MAC_MC_ALL); + tcam_sw_free(te); + + return 0; +} + +/* + * pnc_mcast_me - Add DA MAC address of port + * @mac: Multicast MAC DA or NULL to delete all Multicast DAs for this port + * @port: ingress giga port number + */ +int pnc_mcast_me(unsigned int port, unsigned char *mac) +{ + struct tcam_entry *te; + int tid, empty = -1; + unsigned int data, mask; + + if (mac == NULL) { + /* Delete all Multicast addresses for this port */ + for (tid = (TE_MAC_MC_ALL + 1); tid <= TE_MAC_MC_L; tid++) { + /* Check TCAM entry */ + te = pnc_tcam_entry_get(tid); + if (te != NULL) { + /* delete entry if belong specific port */ + tcam_sw_get_port(te, &data, &mask); + mask = pnc_port_mask_update(mask, port, 0); + if (mask == PORT_MASK) { /* No valid ports */ + tcam_hw_inv(tid); + } else { + tcam_sw_set_port(te, data, mask); + tcam_hw_write(te, tid); + } + tcam_sw_free(te); + } + } + return 0; + } + + /* Add new Multicast DA for this port */ + for (tid = (TE_MAC_MC_ALL + 1); tid <= TE_MAC_MC_L; tid++) { + te = pnc_tcam_entry_get(tid); + + /* Remember first Empty entry */ + if (te == NULL) { + if (empty == -1) + empty = tid; + + continue; + } + + /* Find existing TCAM entry with this DA */ + if (tcam_sw_cmp_bytes(te, MV_ETH_MH_SIZE, MV_MAC_ADDR_SIZE, mac) == 0) { + /* check and update port mask */ + tcam_sw_get_port(te, &data, &mask); + mask = pnc_port_mask_update(mask, port, 1); + tcam_sw_set_port(te, data, mask); + + tcam_hw_write(te, tid); + tcam_sw_free(te); + return 0; + } + tcam_sw_free(te); + } + + /* Not found existing entry and no free TCAM entry - Failed */ + if (empty == -1) + return 1; + + /* Not found existing entry - add to free TCAM entry */ + te = pnc_mac_da(mac, MV_MAC_ADDR_SIZE, pnc_port_mask(port), rxq_mac_mc, RI_DA_MC); + tcam_sw_text(te, "mcast_me"); + + tcam_hw_write(te, empty); + tcam_sw_free(te); + return 0; +} + +/* + * pnc_mac_init - GE init phase configuration + */ +static int pnc_mac_init(void) +{ + struct tcam_entry *te; + unsigned char da_mc[6] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; + unsigned char da_bc[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + + PNC_DBG("%s\n", __func__); + + /* broadcast - for all ports */ + te = pnc_mac_da(da_bc, 6, 0, rxq_mac_bc, RI_DA_BC); + tcam_sw_text(te, "bcast"); + + tcam_hw_write(te, TE_MAC_BC); + tcam_sw_free(te); + + /* flow control PAUSE frames - discard for all ports by default */ + pnc_mac_fc_drop(); + + /* All Multicast - no ports by default */ + te = pnc_mac_da(da_mc, 1, PORT_MASK, rxq_mac_mc, RI_DA_MC); + tcam_sw_text(te, "mcast_all"); + + tcam_hw_write(te, TE_MAC_MC_ALL); + tcam_sw_free(te); + + /* end of section */ + te = tcam_sw_alloc(TCAM_LU_MAC); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_MAC); + + /* Non-promiscous mode - DROP unknown packets */ + sram_sw_set_rinfo(te, RI_DROP); + sram_sw_set_lookup_done(te, 1); + tcam_sw_text(te, "mac_eof"); + + tcam_hw_write(te, TE_MAC_EOF); + tcam_sw_free(te); + + return 0; +} + +/****************************************************************************** + * + * L2 Section + * + ****************************************************************************** + */ + +/* + * Helper: match ethertype + */ +static void pnc_match_etype(struct tcam_entry *te, unsigned short ethertype) +{ + tcam_sw_set_byte(te, 0, ethertype >> 8); + tcam_sw_set_byte(te, 1, ethertype & 0xFF); +} + +/* + * VLAN section: Add non-Ethertype II match rules + */ +#ifdef CONFIG_MV_ETH_PNC_SNAP +static int pnc_snap_llc(void) +{ + struct tcam_entry *te; + int tid = TE_SNAP; + + PNC_DBG("%s\n", __func__); + + /* 0x8870 SNAP */ + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, 0x8870); + sram_sw_set_rinfo(te, RI_ETYPE_8023); + sram_sw_set_lookup_done(te, 1); + tcam_sw_text(te, "snap"); + + tcam_hw_write(te, tid++); + tcam_sw_free(te); + + /* 1536 */ + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, 0x0600); + sram_sw_set_rinfo(te, RI_ETYPE_8023); + sram_sw_set_lookup_done(te, 1); + tcam_sw_text(te, "802.3"); + + tcam_hw_write(te, tid++); + tcam_sw_free(te); + + /* 1024-1535 with LLC/SNAP */ + te = tcam_sw_alloc(TCAM_LU_L2); + tcam_sw_set_byte(te, 0, 0x04); + tcam_sw_set_mask(te, 0, 0xFE); + tcam_sw_set_byte(te, 2, 0xAA); + tcam_sw_set_byte(te, 3, 0xAA); + sram_sw_set_rinfo(te, RI_ETYPE_8023); + sram_sw_set_next_lookup(te, TCAM_LU_L2); + sram_sw_set_shift_update(te, 0, 2 + MV_LLC_HLEN); + tcam_sw_text(te, "llc"); + + tcam_hw_write(te, tid++); + tcam_sw_free(te); + + /* 0-1023 with LLC/SNAP */ + te = tcam_sw_alloc(TCAM_LU_L2); + tcam_sw_set_byte(te, 0, 0x00); + tcam_sw_set_mask(te, 0, 0xFC); + tcam_sw_set_byte(te, 2, 0xAA); + tcam_sw_set_byte(te, 3, 0xAA); + sram_sw_set_rinfo(te, RI_ETYPE_8023); + sram_sw_set_next_lookup(te, TCAM_LU_L2); + sram_sw_set_shift_update(te, 0, 2 + MV_LLC_HLEN); + tcam_sw_text(te, "llc"); + + tcam_hw_write(te, tid++); + tcam_sw_free(te); + + ERR_ON_OOR(--tid > TE_SNAP_END); + + return 0; +} +#endif /* CONFIG_MV_ETH_PNC_SNAP */ + +/* + * VLAN section - Add 802.1p priority rules + */ +int pnc_vlan_prio(unsigned char prio, int rxq) +{ + + return 0; +} + +/* VLAN default entry */ +static int pnc_vlan_def(void) +{ + struct tcam_entry *te; + int tid = TE_VLAN_DEF; + + PNC_DBG("%s\n", __func__); + + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_VLAN_TYPE); + + sram_sw_set_rxq(te, rxq_vlan); + + sram_sw_set_rinfo(te, RI_VLAN); + sram_sw_set_next_lookup(te, TCAM_LU_L2); + sram_sw_set_shift_update(te, 0, MV_VLAN_HLEN); + tcam_sw_text(te, "vlan"); + + tcam_hw_write(te, tid); + tcam_sw_free(te); + + return 0; +} + +int pnc_vlan_init(void) +{ + PNC_DBG("%s\n", __func__); + +#ifdef CONFIG_MV_ETH_PNC_SNAP + pnc_snap_llc(); +#endif /* CONFIG_MV_ETH_PNC_SNAP */ + + pnc_vlan_def(); + + return 0; +} + +/****************************************************************************** + * + * Ethertype Section + * + ****************************************************************************** + */ +static void pnc_etype_arp(void) +{ + /* match arp */ + struct tcam_entry *te; + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_IP_ARP_TYPE); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_rxq(te, rxq_arp); + tcam_sw_text(te, "etype_arp"); + + tcam_hw_write(te, TE_ETYPE_ARP); + tcam_sw_free(te); +} + +static void pnc_etype_ip4(void) +{ + /* match ip4 */ + struct tcam_entry *te; + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_IP_TYPE); + sram_sw_set_shift_update(te, 0, MV_ETH_TYPE_LEN); + sram_sw_set_next_lookup(te, TCAM_LU_IP4); + tcam_sw_text(te, "etype_ipv4"); + + tcam_hw_write(te, TE_ETYPE_IP4); + tcam_sw_free(te); +} + +static void pnc_etype_ip6(void) +{ + /* match ip6 */ + struct tcam_entry *te; + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_IP6_TYPE); + sram_sw_set_shift_update(te, 0, MV_ETH_TYPE_LEN); + sram_sw_set_next_lookup(te, TCAM_LU_IP6); + tcam_sw_text(te, "etype_ipv6"); + + tcam_hw_write(te, TE_ETYPE_IP6); + tcam_sw_free(te); +} + +static void pnc_etype_pppoe(void) +{ + /* match pppoe */ + struct tcam_entry *te; + + /* IPv4 over PPPoE */ + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_PPPOE_TYPE); + tcam_sw_set_byte(te, MV_PPPOE_HDR_SIZE, 0x21); + tcam_sw_set_byte(te, MV_PPPOE_HDR_SIZE + 1, 0x00); + + sram_sw_set_shift_update(te, 0, MV_ETH_TYPE_LEN + MV_PPPOE_HDR_SIZE); + sram_sw_set_next_lookup(te, TCAM_LU_IP4); + sram_sw_set_rinfo(te, RI_PPPOE); + tcam_sw_text(te, "pppoe_ip4"); + + tcam_hw_write(te, TE_PPPOE_IP4); + tcam_sw_free(te); + + /* IPv6 over PPPoE */ + te = tcam_sw_alloc(TCAM_LU_L2); + pnc_match_etype(te, MV_PPPOE_TYPE); + + tcam_sw_set_byte(te, MV_PPPOE_HDR_SIZE, 0x57); + tcam_sw_set_byte(te, MV_PPPOE_HDR_SIZE + 1, 0x00); + + sram_sw_set_shift_update(te, 0, MV_ETH_TYPE_LEN + MV_PPPOE_HDR_SIZE); + sram_sw_set_next_lookup(te, TCAM_LU_IP6); + sram_sw_set_rinfo(te, RI_PPPOE); + tcam_sw_text(te, "pppoe_ip6"); + + tcam_hw_write(te, TE_PPPOE_IP6); + tcam_sw_free(te); +} + +/* + * pnc_etype_init - match basic ethertypes + */ +static int pnc_etype_init(void) +{ + struct tcam_entry *te; + int tid; + + PNC_DBG("%s\n", __func__); + + pnc_etype_arp(); + pnc_etype_ip4(); + pnc_etype_ip6(); + pnc_etype_pppoe(); + + /* add custom ethertypes here */ + tid = TE_ETYPE; + + ERR_ON_OOR(--tid >= TE_ETYPE_EOF); + + /* end of section */ + te = tcam_sw_alloc(TCAM_LU_L2); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_L2); + sram_sw_set_rxq(te, CONFIG_MV_ETH_RXQ_DEF); + sram_sw_set_lookup_done(te, 1); + tcam_sw_text(te, "etype_eof"); + + tcam_hw_write(te, TE_ETYPE_EOF); + tcam_sw_free(te); + + return 0; +} + +/****************************************************************************** + * + * IPv4 Section + * + ****************************************************************************** + */ + +/* + * pnc_ip4_tos - Add TOS prioroty rules + */ +int pnc_ip4_dscp(unsigned char dscp, unsigned char mask, int rxq) +{ +#if (CONFIG_MV_ETH_PNC_DSCP_PRIO > 0) + struct tcam_entry *te; + int tid, empty = -1; + + for (tid = TE_IP4_DSCP; tid <= TE_IP4_DSCP_END; tid++) { + PNC_DBG("%s: tid=%d, dscp=0x%02x, mask=0x%02x, rxq=%d\n", __func__, tid, dscp, mask, rxq); + + te = pnc_tcam_entry_get(tid); + /* Remember first Empty entry */ + if (te == NULL) { + if (empty == -1) + empty = tid; + + continue; + } + /* Find existing entry for this TOS */ + if (tcam_sw_cmp_bytes(te, 1, 1, &dscp) == 0) { + if (rxq == -1) + tcam_hw_inv(tid); + else { + /* Update RXQ */ + sram_sw_set_rxq(te, rxq); + tcam_hw_write(te, tid); + tcam_sw_free(te); + } + return 0; + } + tcam_sw_free(te); + } + + /* Not found existing entry and no free TCAM entry - Failed */ + if (empty == -1) + return 1; + + /* Not found existing entry - add to free TCAM entry */ + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 1, (MV_U8) dscp); + tcam_sw_set_mask(te, 1, (MV_U8) mask); + sram_sw_set_rxq(te, rxq); + sram_sw_set_next_lookup(te, TCAM_LU_IP4); + tcam_sw_set_ainfo(te, 0, AI_DONE_MASK); + sram_sw_set_ainfo(te, AI_DONE_MASK, AI_DONE_MASK); + + tcam_sw_text(te, "ipv4_tos"); + + tcam_hw_write(te, empty); + tcam_sw_free(te); + return 0; +#else + return 1; +#endif /* (CONFIG_MV_ETH_PNC_DSCP_PRIO > 0) */ +} + +/* + * pnc_ip4_tcp - TCP/IP header parsing for fragmentation + * and L4 offset. + */ +static void pnc_ip4_tcp(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + /* TCP, FRAG=0 normal */ + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 9, MV_IP_PROTO_TCP); + tcam_sw_set_byte(te, 6, 0x00); + tcam_sw_set_mask(te, 6, 0x3F); + tcam_sw_set_byte(te, 7, 0x00); + tcam_sw_set_mask(te, 7, 0xFF); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP4); + sram_sw_set_shift_update(te, 1, SHIFT_IP4_HLEN); + sram_sw_set_rinfo(te, RI_L3_IP4 | RI_L4_TCP); + sram_sw_set_rxq(te, rxq_ip4_tcp); + sram_sw_set_ainfo(te, 0, AI_DONE_MASK); + + tcam_sw_text(te, "ipv4_tcp"); + + tcam_hw_write(te, TE_IP4_TCP); + tcam_sw_free(te); + + /* TCP, FRAG=1 any */ + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 9, MV_IP_PROTO_TCP); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP4); + sram_sw_set_shift_update(te, 1, SHIFT_IP4_HLEN); + sram_sw_set_rinfo(te, RI_L3_IP4_FRAG | RI_L4_TCP); + sram_sw_set_rxq(te, rxq_ip4_tcp); + sram_sw_set_ainfo(te, 0, AI_DONE_MASK); + tcam_sw_text(te, "ipv4_tcp_fr"); + + tcam_hw_write(te, TE_IP4_TCP_FRAG); + tcam_sw_free(te); +} + +/* + * pnc_ip4_udp - UDP/UDP header parsing for fragmentation + * and L4 offset. + */ +static void pnc_ip4_udp(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + /* UDP, FRAG=0 normal */ + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 9, MV_IP_PROTO_UDP); + tcam_sw_set_byte(te, 6, 0x00); + tcam_sw_set_mask(te, 6, 0x3F); + tcam_sw_set_byte(te, 7, 0x00); + tcam_sw_set_mask(te, 7, 0xFF); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP4); + sram_sw_set_shift_update(te, 1, SHIFT_IP4_HLEN); + sram_sw_set_rinfo(te, RI_L3_IP4 | RI_L4_UDP); + sram_sw_set_rxq(te, rxq_ip4_udp); + sram_sw_set_ainfo(te, 0, AI_DONE_MASK); + tcam_sw_text(te, "ipv4_udp"); + + tcam_hw_write(te, TE_IP4_UDP); + tcam_sw_free(te); + + /* UDP, FRAG=1 any */ + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 9, MV_IP_PROTO_UDP); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP4); + sram_sw_set_shift_update(te, 1, SHIFT_IP4_HLEN); + sram_sw_set_rinfo(te, RI_L3_IP4_FRAG | RI_L4_UDP); + sram_sw_set_rxq(te, rxq_ip4_udp); + sram_sw_set_ainfo(te, 0, AI_DONE_MASK); + tcam_sw_text(te, "ipv4_udp_fr"); + + tcam_hw_write(te, TE_IP4_UDP_FRAG); + tcam_sw_free(te); +} + +/* + * IGMP + */ +static void pnc_ip4_igmp(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + te = tcam_sw_alloc(TCAM_LU_IP4); + tcam_sw_set_byte(te, 9, MV_IP_PROTO_IGMP); + sram_sw_set_lookup_done(te, 1); + + sram_sw_set_rinfo(te, RI_L3_IP4 | RI_L4_UN | RI_IGMP); + sram_sw_set_rxq(te, rxq_ip4_igmp); + tcam_sw_text(te, "ipv4_igmp"); + + tcam_hw_write(te, TE_IP4_IGMP); + tcam_sw_free(te); +} + +/* IPv4 - end of section */ +static void pnc_ip4_end(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + te = tcam_sw_alloc(TCAM_LU_IP4); + sram_sw_set_rinfo(te, RI_L3_IP4 | RI_L4_UN); + sram_sw_set_rxq(te, rxq_ip4); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_IP4); + tcam_sw_text(te, "ipv4_eof"); + + tcam_hw_write(te, TE_IP4_EOF); + tcam_sw_free(te); +} + +int pnc_ip4_init(void) +{ + PNC_DBG("%s\n", __func__); + + pnc_ip4_tcp(); + pnc_ip4_udp(); + pnc_ip4_igmp(); + /*pnc_ip4_esp();*/ + pnc_ip4_end(); + + return 0; +} + +/* IPv6 - detect TCP */ +static void pnc_ip6_tcp(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + /* TCP without extension headers */ + te = tcam_sw_alloc(TCAM_LU_IP6); + tcam_sw_set_byte(te, 6, MV_IP_PROTO_TCP); + sram_sw_set_shift_update(te, 1, sizeof(MV_IP6_HEADER)); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP6_A); + + sram_sw_set_rinfo(te, RI_L3_IP6 | RI_L4_TCP); + sram_sw_set_rxq(te, rxq_ip6); + tcam_sw_text(te, "ipv6_tcp"); + + tcam_hw_write(te, TE_IP6_TCP); + tcam_sw_free(te); +} + +/* IPv6 - detect UDP */ +static void pnc_ip6_udp(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + /* UDP without extension headers */ + te = tcam_sw_alloc(TCAM_LU_IP6); + tcam_sw_set_byte(te, 6, MV_IP_PROTO_UDP); + sram_sw_set_shift_update(te, 1, sizeof(MV_IP6_HEADER)); + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP6_A); + + sram_sw_set_rinfo(te, RI_L3_IP6 | RI_L4_UDP); + sram_sw_set_rxq(te, rxq_ip6); + tcam_sw_text(te, "ipv6_udp"); + + tcam_hw_write(te, TE_IP6_UDP); + tcam_sw_free(te); +} + +/* IPv6 - end of section */ +static void pnc_ip6_end(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + te = tcam_sw_alloc(TCAM_LU_IP6); + sram_sw_set_shift_update(te, 1, sizeof(MV_IP6_HEADER)); + sram_sw_set_rinfo(te, RI_L3_IP6 | RI_L4_UN); + sram_sw_set_rxq(te, rxq_ip6); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_IP6); + tcam_sw_text(te, "ipv6_eof"); + + tcam_hw_write(te, TE_IP6_EOF); + tcam_sw_free(te); +} + +int pnc_ip6_init(void) +{ + PNC_DBG("%s\n", __func__); + + pnc_ip6_tcp(); + pnc_ip6_udp(); + + pnc_ip6_end(); + + return 0; +} + +/****************************************************************************** + * + * IPv4 Section + * + ****************************************************************************** + */ + +static int pnc_flow_init(void) +{ + struct tcam_entry *te; + + PNC_DBG("%s\n", __func__); + + /* end of section for IPv4 */ + te = tcam_sw_alloc(TCAM_LU_FLOW_IP4); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_FLOW_IP4); + tcam_sw_text(te, "flow_ip4_eof"); + + tcam_hw_write(te, TE_FLOW_IP4_EOF); + tcam_sw_free(te); + + /* end of section for IPv6_A */ + te = tcam_sw_alloc(TCAM_LU_FLOW_IP6_A); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_FLOW_IP6_A); + tcam_sw_text(te, "flow_ip6_A_eof"); + + tcam_hw_write(te, TE_FLOW_IP6_A_EOF); + tcam_sw_free(te); + + /* end of section for IPv6_B */ + te = tcam_sw_alloc(TCAM_LU_FLOW_IP6_B); + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, FLOWID_EOF_LU_FLOW_IP6_B); + tcam_sw_text(te, "flow_ip6_B_eof"); + + tcam_hw_write(te, TE_FLOW_IP6_B_EOF); + tcam_sw_free(te); + + return 0; +} + +int pnc_te_del(unsigned int tid) +{ + PNC_DBG("%s [%d]\n", __func__, tid); + + tcam_hw_inv(tid); + + return 0; +} + +/* require 2 TCAM entries for macth */ +int pnc_ipv6_2_tuples_add(unsigned int tid1, unsigned int tid2, unsigned int flow_id, + MV_U8* sip, MV_U8* dip, unsigned int rxq) +{ + struct tcam_entry* te; + int i; + static int unique=0; + unique++; + if (unique>=64) { + mvOsPrintf("unique>=64 in %s\n",__FUNCTION__); + return 1; + } + + + if( (tid1 < TE_FLOW_NFP) || (tid1 > TE_FLOW_NFP_END) ) + ERR_ON_OOR(1); + + if( (tid2 < TE_FLOW_NFP) || (tid2 > TE_FLOW_NFP_END) ) + ERR_ON_OOR(2); + + te = tcam_sw_alloc(TCAM_LU_FLOW_IP6_A); + for(i=0; i<16; i++) + { + tcam_sw_set_byte(te, 8+i, sip[i]); + } + sram_sw_set_shift_update(te, 2, 24); + + sram_sw_set_next_lookup_shift(te, 2); + + sram_sw_set_next_lookup(te, TCAM_LU_FLOW_IP6_B); + + + sram_sw_set_ainfo(te, unique, AI_DONE_MASK); + tcam_sw_text(te, "ipv6_2t_A"); + + tcam_hw_write(te, tid1); + tcam_sw_free(te); + + te = tcam_sw_alloc(TCAM_LU_FLOW_IP6_B); + for(i=0; i<16; i++) + { + tcam_sw_set_byte(te, i, dip[i]); + } + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, flow_id); + + sram_sw_set_rxq(te, rxq); + sram_sw_set_rinfo(te, RI_NFP_FLOW); + + tcam_sw_set_ainfo(te, unique, AI_MASK); + tcam_sw_text(te, "ipv6_2t_B"); + + tcam_hw_write(te, tid2); + tcam_sw_free(te); + + return 0; +} + + + +int pnc_ipv4_2_tuples_add(unsigned int tid, unsigned int flow_id, unsigned int sip, unsigned int dip, unsigned int rxq) +{ + struct tcam_entry *te; + + PNC_DBG("%s [%d] flow=%d " MV_IPQUAD_FMT "->" MV_IPQUAD_FMT "\n", + __func__, tid, flow_id, MV_IPQUAD(sip), MV_IPQUAD(dip)); + + if (tid < TE_FLOW_NFP) + ERR_ON_OOR(1); + + if (tid > TE_FLOW_NFP_END) + ERR_ON_OOR(1); + + te = tcam_sw_alloc(TCAM_LU_FLOW_IP4); + + tcam_sw_set_byte(te, 12, (sip >> 0) & 0xFF); + tcam_sw_set_byte(te, 13, (sip >> 8) & 0xFF); + tcam_sw_set_byte(te, 14, (sip >> 16) & 0xFF); + tcam_sw_set_byte(te, 15, (sip >> 24) & 0xFF); + + tcam_sw_set_byte(te, 16, (dip >> 0) & 0xFF); + tcam_sw_set_byte(te, 17, (dip >> 8) & 0xFF); + tcam_sw_set_byte(te, 18, (dip >> 16) & 0xFF); + tcam_sw_set_byte(te, 19, (dip >> 24) & 0xFF); + + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, flow_id); + sram_sw_set_rxq(te, rxq); + sram_sw_set_rinfo(te, RI_NFP_FLOW); + tcam_sw_text(te, "ipv4_2t"); + + tcam_hw_write(te, tid); + tcam_sw_free(te); + + return 0; +} + +int pnc_ipv4_5_tuples_add(unsigned int tid, unsigned int flow_id, + unsigned int sip, unsigned int dip, unsigned int proto, unsigned int ports, unsigned int rxq) +{ + struct tcam_entry *te; + + PNC_DBG("%s [%d] flow=%d " MV_IPQUAD_FMT "->" MV_IPQUAD_FMT ", ports=0x%x, proto=%d\n", + __func__, tid, flow_id, MV_IPQUAD(sip), MV_IPQUAD(dip), ports, proto); + + if (tid < TE_FLOW_NFP) + ERR_ON_OOR(1); + + if (tid > TE_FLOW_NFP_END) + ERR_ON_OOR(1); + + /* sanity check */ + + te = tcam_sw_alloc(TCAM_LU_FLOW_IP4); + + tcam_sw_set_byte(te, 9, proto); + + tcam_sw_set_byte(te, 12, (sip >> 0) & 0xFF); + tcam_sw_set_byte(te, 13, (sip >> 8) & 0xFF); + tcam_sw_set_byte(te, 14, (sip >> 16) & 0xFF); + tcam_sw_set_byte(te, 15, (sip >> 24) & 0xFF); + + tcam_sw_set_byte(te, 16, (dip >> 0) & 0xFF); + tcam_sw_set_byte(te, 17, (dip >> 8) & 0xFF); + tcam_sw_set_byte(te, 18, (dip >> 16) & 0xFF); + tcam_sw_set_byte(te, 19, (dip >> 24) & 0xFF); + + tcam_sw_set_byte(te, 20, (ports >> 0) & 0xFF); + tcam_sw_set_byte(te, 21, (ports >> 8) & 0xFF); + tcam_sw_set_byte(te, 22, (ports >> 16) & 0xFF); + tcam_sw_set_byte(te, 23, (ports >> 24) & 0xFF); + + sram_sw_set_lookup_done(te, 1); + sram_sw_set_flowid_lo(te, flow_id); + sram_sw_set_rxq(te, rxq); + sram_sw_set_rinfo(te, RI_NFP_FLOW); + tcam_sw_text(te, "ipv4_5t"); + + tcam_hw_write(te, tid); + tcam_sw_free(te); + + return 0; +} + +/****************************************************************************** + * + * GPON API + * + ****************************************************************************** + */ + +MV_STATUS mvPncInit(MV_U8 *pncVirtBase) +{ + pnc_inited = 0; + mvPncVirtBase = pncVirtBase; + + mvOsPrintf("mvPncVirtBase = 0x%p\n", pncVirtBase); + return MV_OK; +} + +/****************************************************************************** + * + * PnC Init + * + ****************************************************************************** + */ +int pnc_default_init(void) +{ + int rc; + + PNC_DBG("%s\n", __func__); + + rc = tcam_hw_init(); + if (rc) + goto out; + + /* Mask all interrupts */ + MV_REG_WRITE(MV_PNC_MASK_REG, 0xffffffff); + + /* Clear all interrupts */ + MV_REG_WRITE(MV_PNC_CAUSE_REG, 0x0); + + /* Always start from lookup = 0 */ + MV_REG_WRITE(MV_PNC_INIT_LOOKUP_REG, 0x0); + + rc = pnc_mac_init(); + if (rc) + goto out; + + rc = pnc_vlan_init(); + if (rc) + goto out; + + rc = pnc_etype_init(); + if (rc) + goto out; + + rc = pnc_ip4_init(); + if (rc) + goto out; + + rc = pnc_ip6_init(); + if (rc) + goto out; + + rc = pnc_flow_init(); + if (rc) + goto out; + + pnc_inited = 1; +out: + return rc; +} + +static void pnc_port_sprintf(struct tcam_entry *te, char *buf) +{ + int p, offs; + unsigned int data, mask; + + tcam_sw_get_port(te, &data, &mask); + if (mask == PORT_MASK) + mvOsSPrintf(buf, "None"); + else if (mask == 0) + mvOsSPrintf(buf, "All"); + else { + offs = 0; + for (p = 0; p < PORT_BITS; p++) { + if ((mask & (1 << p)) == 0) + offs += mvOsSPrintf(buf + offs, " %d,", pnc_port_map(p)); + } + } +} + +void pnc_ipv4_dscp_show(void) +{ +#if (CONFIG_MV_ETH_PNC_DSCP_PRIO > 0) + struct tcam_entry *te; + int tid; + unsigned char tos; + char buf[16]; + + mvOsPrintf("TOS Mask Ports RXQ Name\n"); + for (tid = TE_IP4_DSCP; tid <= TE_IP4_DSCP_END; tid++) { + te = pnc_tcam_entry_get(tid); + if (te) { + tos = *(te->data.u.byte + 1); + mvOsPrintf("0x%02x", tos); + tos = *(te->mask.u.byte + 1); + mvOsPrintf(" 0x%02x", tos); + pnc_port_sprintf(te, buf); + mvOsPrintf(" %10s", buf); + mvOsPrintf(" %d", sram_sw_get_rxq(te)); + mvOsPrintf(" %s\n", te->ctrl.text); + tcam_sw_free(te); + } + } +#endif /* CONFIG_MV_ETH_PNC_DSCP_PRIO > 0 */ + return; +} + +void pnc_mac_show(void) +{ + int tid; + struct tcam_entry *te; + char *mac; + char buf[16]; + + mvOsPrintf(" Addr Mask Ports RXQ Name\n"); + for (tid = TE_MAC_BC; tid < TE_MAC_EOF; tid++) { + te = pnc_tcam_entry_get(tid); + if (te) { + mac = te->data.u.byte + MV_ETH_MH_SIZE; + mvOsPrintf(MV_MACQUAD_FMT, MV_MACQUAD(mac)); + mac = te->mask.u.byte + MV_ETH_MH_SIZE; + mvOsPrintf(" " MV_MACQUAD_FMT, MV_MACQUAD(mac)); + + pnc_port_sprintf(te, buf); + mvOsPrintf(" %10s", buf); + mvOsPrintf(" %d", sram_sw_get_rxq(te)); + mvOsPrintf(" %s\n", te->ctrl.text); + tcam_sw_free(te); + } + } +} + +/* + * pnc_rxq - Set RxQ for protocol + */ +int pnc_rxq_proto(unsigned int proto, unsigned int rxq) +{ + PNC_DBG("%s proto=%x rxq=%d\n", __func__, proto, rxq); + + switch (proto) { + + case MV_IP_ARP_TYPE: + rxq_arp = rxq; + if (pnc_inited) + pnc_etype_arp(); + break; + + case MV_IP_PROTO_TCP: + rxq_ip4_tcp = rxq; + if (pnc_inited) + pnc_ip4_tcp(); + break; + + case MV_IP_PROTO_UDP: + rxq_ip4_udp = rxq; + if (pnc_inited) + pnc_ip4_udp(); + break; + + case MV_IP_PROTO_IGMP: + rxq_ip4_igmp = rxq; + if (pnc_inited) + pnc_ip4_igmp(); + break; + default: + return PNC_ERR_INV; + } + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvPnc.h u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvPnc.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvPnc.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvPnc.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_PNC_H__ +#define __MV_PNC_H__ + +#ifdef CONFIG_MV_ETH_PNC + +extern MV_U8 *mvPncVirtBase; + +/* + * Errors + */ +#define ERR_ON_OOR(cond) if (cond) { mvOsPrintf("%s: out of range\n", __func__); return PNC_ERR_OOR; } +#define WARN_ON_OOR(cond) if (cond) { mvOsPrintf("%s: out of range\n", __func__); return; } +#define WARN_ON_OOM(cond) if (cond) { mvOsPrintf("%s: out of memory\n", __func__); return NULL; } + + /* + * Errors assigment + */ +#define PNC_ERR_OOR 1 /* out of range error */ +#define PNC_ERR_INV 1 /* invalid parameter */ + +/* + * TCAM topology definition. + * The TCAM is divided into sections per protocol encapsulation. + * Usually each section is designed to be to a lookup. + * Change sizes of sections according to the target product. + */ +enum { + /* MAC Lookup including Marvell/PON header */ + TE_MH_OMCI, /* GPON OMCI packet */ + TE_MAC_BC, /* broadcast */ + TE_MAC_FLOW_CTRL, /* Flow Control PAUSE frames */ + TE_MAC_MC_ALL, /* first multicast entry (always reserved for all MCASTs) */ + TE_MAC_MC_L = TE_MAC_MC_ALL + CONFIG_MV_ETH_PNC_MCAST_NUM, /* last multicast entry */ + TE_MAC_ME, /* mac to me per port */ + TE_MAC_ME_END = TE_MAC_ME + CONFIG_MV_ETH_PORTS_NUM - 1, + TE_MAC_EOF, + + /* L2 Lookup */ +#ifdef CONFIG_MV_ETH_PNC_SNAP + /* SNAP/LLC Lookup */ + TE_SNAP, + TE_SNAP_END = TE_SNAP + 4 - 1, +#endif /* CONFIG_MV_ETH_PNC_SNAP */ + + /* VLAN Lookup */ +#if (CONFIG_MV_ETH_PNC_VLAN_PRIO > 0) + TE_VLAN_PRI, + TE_VLAN_PRI_END = TE_VLAN_PRI + CONFIG_MV_ETH_PNC_VLAN_PRIO - 1, +#endif /* CONFIG_MV_ETH_PNC_VLAN_PRIO */ + + TE_VLAN_DEF, + + /* Ethertype Lookup */ + TE_ETYPE_ARP, + TE_ETYPE_IP4, + TE_ETYPE_IP6, + TE_PPPOE_IP4, + TE_PPPOE_IP6, + TE_ETYPE, /* custom ethertype */ + TE_ETYPE_EOF = TE_ETYPE + CONFIG_MV_ETH_PNC_ETYPE, + + /* IP4 Lookup */ +#if (CONFIG_MV_ETH_PNC_DSCP_PRIO > 0) + TE_IP4_DSCP, + TE_IP4_DSCP_END = TE_IP4_DSCP + CONFIG_MV_ETH_PNC_DSCP_PRIO - 1, +#endif /* CONFIG_MV_ETH_PNC_DSCP_PRIO > 0 */ + + TE_IP4_TCP, + TE_IP4_TCP_FRAG, + TE_IP4_UDP, + TE_IP4_UDP_FRAG, + TE_IP4_IGMP, + TE_IP4_ESP, + TE_IP4_EOF, + + /* IP6 Lookup */ + TE_IP6_TCP, + TE_IP6_UDP, + TE_IP6_EOF, + + /* Session Lookup for IPv4 (LU=4)and IPv6 */ + /* NFP session use all rest entries */ + TE_FLOW_NFP, + TE_FLOW_NFP_END = MV_ETH_TCAM_LINES - 4, + TE_FLOW_IP4_EOF, + TE_FLOW_IP6_A_EOF, + TE_FLOW_IP6_B_EOF, +}; + + +enum { + TCAM_LU_MAC, + TCAM_LU_L2, + TCAM_LU_IP4, + TCAM_LU_IP6, + TCAM_LU_FLOW_IP4, + TCAM_LU_FLOW_IP6_A, + TCAM_LU_FLOW_IP6_B, +}; + +/* + * Pre-defined FlowId assigment + */ +#define FLOWID_EOF_LU_MAC 0xFFF0 +#define FLOWID_EOF_LU_L2 0xFFF2 +#define FLOWID_EOF_LU_IP4 0xFFF4 +#define FLOWID_EOF_LU_IP6 0xFFF6 +#define FLOWID_EOF_LU_FLOW_IP4 0xFFF8 +#define FLOWID_EOF_LU_FLOW_IP6_A 0xFFFA +#define FLOWID_EOF_LU_FLOW_IP6_B 0xFFFB + + +/* + * Result info bits assigment + */ +#define RI_DROP (BIT0) /* drop */ + +#define RI_L4_OFFS 1 +#define RI_L4_MASK (3 << RI_L4_OFFS) +#define RI_L4_TCP (0 << RI_L4_OFFS) +#define RI_L4_UDP (1 << RI_L4_OFFS) +#define RI_L4_UN (2 << RI_L4_OFFS) + +#define RI_L3_OFFS 3 +#define RI_L3_MASK (7 << RI_L3_OFFS) +#define RI_L3_UN (0 << RI_L3_OFFS) +#define RI_L3_IP6 (1 << RI_L3_OFFS) +#define RI_L3_IP4_FRAG (2 << RI_L3_OFFS) +#define RI_L3_IP4 (3 << RI_L3_OFFS) +#define RI_L3_IP4_FRAG_F (6 << RI_L3_OFFS) + +#define RI_MCAST_OFFS 6 +#define RI_MCAST_MASK (3 << RI_MCAST_OFFS) +#define RI_MCAST_SPEC (0 << RI_MCAST_OFFS) +#define RI_MCAST_PNC_SPEC (1 << RI_MCAST_OFFS) +#define RI_MCAST_OTHER (2 << RI_MCAST_OFFS) +#define RI_MCAST_PNC_OTHER (3 << RI_MCAST_OFFS) +#define RI_MCAST_PNC_ONLY (4 << RI_MCAST_OFFS) + +#define RI_DA_MC (BIT10) /* multicast */ +#define RI_DA_BC (BIT11) /* broadcast */ +#define RI_DA_ME (BIT12) /* unicast */ +#define RI_IGMP (BIT13) /* IGMP */ +#define RI_ETYPE_8023 (BIT14) /* 802.3/LLC/SNAP encapsulation */ +#define RI_VLAN (BIT15) /* VLAN */ +#define RI_PPPOE (BIT16) /* PPPoE */ + +#define RI_NFP_FLOW (BIT18) /* NFP flowid is valid */ +#define RI_NFP_SWF_FLOW (BIT19) /* NFP_SWF flowid is valid */ +#define RI_OMCI (BIT20) /* OMCI packet */ + +/* + * Additional info bits assigment + */ +#define AI_DONE_BIT 0 +#define AI_DONE_MASK (1 << AI_DONE_BIT) + +/* PnC result info */ +#define NETA_PNC_DA_MC (RI_DA_MC >> 9) +#define NETA_PNC_DA_BC (RI_DA_BC >> 9) +#define NETA_PNC_DA_UC (RI_DA_ME >> 9) +#define NETA_PNC_IGMP (RI_IGMP >> 9) +#define NETA_PNC_SNAP (RI_ETYPE_8023 >> 9) +#define NETA_PNC_VLAN (RI_VLAN >> 9) +#define NETA_PNC_PPPOE (RI_PPPOE >> 9) +#define NETA_PNC_NFP (RI_NFP_FLOW >> 9) +#define NETA_PNC_SWF (RI_NFP_SWF_FLOW >> 9) +#define NETA_PNC_OMCI (RI_OMCI >> 9) +/*---------------------------------------------------------------------------*/ + +/* + * Export API + */ +MV_STATUS mvPncInit(MV_U8 *pncVirtBase); + +int pnc_default_init(void); + +/* Set number of Rx queues */ +void pnc_rxq_max(int rxq_max); + +/* Assign Rx queue to a protocol */ +int pnc_rxq_proto(unsigned int proto, unsigned int rxq); + +/* Get availible range on section */ +int pnc_rule_range(int sec, int *first, int *last); + +/* Get section for specific rule */ +int pnc_rule_sec(int tid); + +/* Delete rule */ +int pnc_rule_del(int tid); + +/* Add rule to detect OMCI packets */ +int pnc_mh_omci(unsigned int port, unsigned short data, unsigned short mask); + +/* Set MAC address of a port, or NULL for promiscuous */ +int pnc_mac_me(unsigned int port, unsigned char *mac, int rxq); + +/* Set Multicast MAC address to be accepted on the port */ +int pnc_mcast_me(unsigned int port, unsigned char *mac); + +/* Enable / Disable accept ALL Multicast */ +int pnc_mcast_all(unsigned int port, int en); + +/* Add TOS priority rule */ +int pnc_ip4_dscp(unsigned char dscp, unsigned char mask, int rxq); +void pnc_ipv4_dscp_show(void); + + +int pnc_te_del(unsigned int tid); + +/* 2 tuple match */ +int pnc_ipv4_2_tuples_add(unsigned int tid, unsigned int flow_hi, + unsigned int sip, unsigned int dip, unsigned int rxq); +int pnc_ipv6_2_tuples_add(unsigned int tid1, unsigned int tid2, unsigned int flow_id, + MV_U8 *sip, MV_U8 *dip, unsigned int rxq); + +/* 5 tuple match */ +int pnc_ipv4_5_tuples_add(unsigned int tid, unsigned int flow_hi, + unsigned int sip, unsigned int dip, + unsigned int proto, unsigned int ports, unsigned int rxq); + +void pnc_mac_show(void); + +#endif /* CONFIG_MV_ETH_PNC */ + +#endif /*__MV_PNC_H__ */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvTcam.c u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvTcam.c --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvTcam.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvTcam.c 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,786 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +#include "mvPnc.h" +#include "mvTcam.h" +#include "gbe/mvNetaRegs.h" + +#define DWORD_LEN 32 + +#define TCAM_DBG(x...) if (tcam_ctl_flags&TCAM_F_DEBUG) mvOsPrintf(x) +/*#define TCAM_DBG(x...)*/ + +#define WORD6_FMT "%4.4x %8.8x %8.8x %8.8x %8.8x %8.8x %8.8x" +#define WORD6_VAL(p) p[6]&0xFFFF, p[5], p[4], p[3], p[2], p[1], p[0] +#define WORD4_FMT "%8.8x %8.8x %8.8x %8.8x" +#define WORD4_VAL(p) p[3], p[2], p[1], p[0] + +/* + * SW control flags + */ +static int tcam_ctl_flags; +#define TCAM_F_DEBUG 0x1 +#define TCAM_F_WRITE 0x2 + +/* + * Keep short text per entry + */ +static char tcam_text[MV_ETH_TCAM_LINES][TCAM_TEXT]; + +/* + * Low-Level API: TCAM + */ +void tcam_sw_clear(struct tcam_entry *te) +{ + memset(te, 0, sizeof(struct tcam_entry)); +} + +/* + *@ainfo : match to `1` on additional info bits 6..0 + */ +void tcam_sw_set_ainfo(struct tcam_entry *te, unsigned int bits, unsigned int mask) +{ + int i; + MV_U32 key = te->data.u.word[AI_WORD]; + MV_U32 val; + + WARN_ON_OOR(bits > AI_MASK); + WARN_ON_OOR(mask > AI_MASK); + + for (i = 0; i < AI_BITS; i++) { + if (mask & (1 << i)) { + + val = 1 << (i + AI_OFFS); + + if (bits & (1 << i)) + key |= val; + else + key &= ~val; + } + } + te->data.u.word[AI_WORD] = key; + te->mask.u.word[AI_WORD] |= mask << AI_OFFS; +} + +static int tcam_sw_dump_ainfo(struct tcam_entry *te, char *buf) +{ + int i; + int off = 0; + + for (i = 0; i < AI_BITS; i++) + if (te->mask.u.word[AI_WORD] & (1 << (i + AI_OFFS))) + off += mvOsSPrintf(buf + off, " A%d=%d", i, + !!(te->data.u.word[AI_WORD] & (1 << (i + AI_OFFS)))); + + return off; +} + +/* + *@port : port + */ +void tcam_sw_set_port(struct tcam_entry *te, unsigned int port, unsigned int mask) +{ + WARN_ON_OOR(port > PORT_MASK); + WARN_ON_OOR(mask > PORT_MASK); + + te->data.u.word[PORT_WORD] &= ~(PORT_MASK << PORT_OFFS); + te->mask.u.word[PORT_WORD] &= ~(PORT_MASK << PORT_OFFS); + + te->data.u.word[PORT_WORD] |= port << PORT_OFFS; + te->mask.u.word[PORT_WORD] |= mask << PORT_OFFS; +} + +void tcam_sw_get_port(struct tcam_entry *te, unsigned int *port, unsigned int *mask) +{ + *port = (te->data.u.word[PORT_WORD] >> PORT_OFFS) & PORT_MASK; + *mask = (te->mask.u.word[PORT_WORD] >> PORT_OFFS) & PORT_MASK; +} + +void tcam_sw_set_lookup(struct tcam_entry *te, unsigned int lookup) +{ + WARN_ON_OOR(lookup > LU_MASK); + te->data.u.word[PORT_WORD] &= ~(LU_MASK << LU_OFFS); + te->data.u.word[PORT_WORD] |= lookup << LU_OFFS; + te->mask.u.word[PORT_WORD] |= LU_MASK << LU_OFFS; +} + +void tcam_sw_get_lookup(struct tcam_entry *te, unsigned int *lookup, unsigned int *mask) +{ + *lookup = (te->data.u.word[PORT_WORD] >> LU_OFFS) & LU_MASK; + *mask = (te->mask.u.word[PORT_WORD] >> LU_OFFS) & LU_MASK; +} + +/* offset:23..0 */ +void tcam_sw_set_byte(struct tcam_entry *te, unsigned int offset, unsigned char data) +{ + WARN_ON_OOR(offset >= TCAM_LEN * 4); + + te->data.u.byte[offset] = data; + te->mask.u.byte[offset] = 0xFF; +} + +void tcam_sw_set_mask(struct tcam_entry *te, unsigned int offset, unsigned char mask) +{ + WARN_ON_OOR(offset >= TCAM_LEN * 4); + + te->mask.u.byte[offset] = mask; +} + +int tcam_sw_cmp_byte(struct tcam_entry *te, unsigned int offset, unsigned char data) +{ + unsigned char mask; + + ERR_ON_OOR(offset >= TCAM_LEN * 4); + + mask = te->mask.u.byte[offset]; + + if ((te->data.u.byte[offset] & mask) == (data & mask)) + return 0; + + return 1; +} + +int tcam_sw_cmp_bytes(struct tcam_entry *te, unsigned int offset, unsigned int size, unsigned char *data) +{ + int i; + + ERR_ON_OOR((offset + size) >= TCAM_LEN * 4); + + for (i = 0; i < size; i++) { + if (tcam_sw_cmp_byte(te, offset + i, data[i])) + return 1; + } + return 0; +} + +/* + * Low-Level API: SRAM + */ +void sram_sw_set_flowid_lo(struct tcam_entry *te, unsigned int flowid) +{ + te->sram.word[0] |= flowid & 0xFFFF; + te->sram.word[1] |= 0x1; /* enable lsb */ +} +void sram_sw_set_flowid_hi(struct tcam_entry *te, unsigned int flowid) +{ + te->sram.word[0] |= flowid << 16; + te->sram.word[1] |= 0x2; /* enable msb */ +} + +/* mask:81..58 val:57..34 */ +void sram_sw_set_rinfo(struct tcam_entry *te, unsigned int rinfo) +{ + unsigned int word; + unsigned int i; + + WARN_ON_OOR(rinfo > RI_MASK); + + for (i = 0; i < RI_BITS; i++) { + if (rinfo & (1 << i)) { + + word = (RI_VALUE_OFFS + i) / DWORD_LEN; + te->sram.word[word] |= 1 << ((i + RI_VALUE_OFFS) % DWORD_LEN); + + word = (RI_MASK_OFFS + i) / DWORD_LEN; + te->sram.word[word] |= 1 << ((i + RI_MASK_OFFS) % DWORD_LEN); + } + } +} + +static int sram_sw_dump_rinfo(struct tcam_entry *te, char *buf) +{ + unsigned int word, shift, rinfo; + int i, off = 0; + + word = RI_VALUE_OFFS / DWORD_LEN; + shift = RI_VALUE_OFFS % DWORD_LEN; + rinfo = (te->sram.word[word] >> shift) & ((1 << RI_BITS) - 1); + + for (i = 0; i < RI_BITS; i++) + if (rinfo & (1 << i)) + off += mvOsSPrintf(buf + off, " R%d", i); + + return off; +} + +/* index:91..89 val:88..82 */ +void sram_sw_set_shift_update(struct tcam_entry *te, unsigned int index, unsigned int value) +{ + unsigned int word; + + WARN_ON_OOR(index > SHIFT_IDX_MASK); /* 0x7 */ + WARN_ON_OOR(value > SHIFT_VAL_MASK); /* 0x7F */ + + /* Reset value prior to set new one */ + word = SHIFT_IDX_OFFS / DWORD_LEN; + te->sram.word[word] &= ~(SHIFT_IDX_MASK << (SHIFT_IDX_OFFS % DWORD_LEN)); + te->sram.word[word] |= index << (SHIFT_IDX_OFFS % DWORD_LEN); + + word = SHIFT_VAL_OFFS / DWORD_LEN; + te->sram.word[word] &= ~(SHIFT_VAL_MASK << (SHIFT_VAL_OFFS % DWORD_LEN)); + te->sram.word[word] |= value << (SHIFT_VAL_OFFS % DWORD_LEN); + + TCAM_DBG("%s: w=%x i=0x%x v=0x%x\n", __func__, word, index, value); +} + +static int sram_sw_dump_shift_update(struct tcam_entry *te, char *buf) +{ + unsigned int word; + unsigned int index; + unsigned int value; + + word = SHIFT_VAL_OFFS / DWORD_LEN; + value = te->sram.word[word] >> (SHIFT_VAL_OFFS % DWORD_LEN); + value &= SHIFT_VAL_MASK; + + word = SHIFT_IDX_OFFS / DWORD_LEN; + index = te->sram.word[word] >> (SHIFT_IDX_OFFS % DWORD_LEN); + index &= SHIFT_IDX_MASK; + + if (value) + return mvOsSPrintf(buf, " [%d]=%d", index, value); + + return 0; +} + +/* rxq:95..93 info:92 */ +void sram_sw_set_rxq(struct tcam_entry *te, unsigned int rxq) +{ + unsigned int word; + + WARN_ON_OOR(rxq > RXQ_MASK); + + word = RXQ_QUEUE_OFFS / DWORD_LEN; + te->sram.word[word] &= ~(RXQ_MASK << (RXQ_QUEUE_OFFS % DWORD_LEN)); + te->sram.word[word] |= rxq << (RXQ_QUEUE_OFFS % DWORD_LEN); +} + +unsigned int sram_sw_get_rxq(struct tcam_entry *te) +{ + unsigned int word; + unsigned int rxq; + + word = RXQ_QUEUE_OFFS / DWORD_LEN; + rxq = te->sram.word[word] >> (RXQ_QUEUE_OFFS % DWORD_LEN); + rxq &= RXQ_MASK; + + return rxq; +} + +static int sram_sw_dump_rxq(struct tcam_entry *te, char *buf) +{ + unsigned int rxq; + + rxq = sram_sw_get_rxq(te); + if (rxq) + return mvOsSPrintf(buf, " Q%d", rxq); + + return 0; +} + +/* index:98..96 */ +void sram_sw_set_next_lookup_shift(struct tcam_entry *te, unsigned int index) +{ + unsigned int word; + + WARN_ON_OOR(index > SHIFT_IDX_MASK); + + word = NEXT_LU_SHIFT_OFFS / DWORD_LEN; + te->sram.word[word] |= index << (NEXT_LU_SHIFT_OFFS % DWORD_LEN); +} + +static int sram_sw_dump_next_lookup_shift(struct tcam_entry *te, char *buf) +{ + unsigned int word, value; + + word = NEXT_LU_SHIFT_OFFS / DWORD_LEN; + value = te->sram.word[word] >> (NEXT_LU_SHIFT_OFFS % DWORD_LEN); + value &= SHIFT_IDX_MASK; + + if (value) + return mvOsSPrintf(buf, " SH=%d", value); + + return 0; +} + +/* done:99 */ +void sram_sw_set_lookup_done(struct tcam_entry *te, unsigned int value) +{ + unsigned int word; + + word = LU_DONE_OFFS / DWORD_LEN; + if (value) + te->sram.word[word] |= 1 << (LU_DONE_OFFS % DWORD_LEN); + else + te->sram.word[word] &= ~(1 << (LU_DONE_OFFS % DWORD_LEN)); +} + +/* index:91..89 val:88..82 */ +void sram_sw_set_ainfo(struct tcam_entry *te, unsigned int bits, unsigned int mask) +{ + unsigned int word; + unsigned int i; + + WARN_ON_OOR(bits > AI_MASK); + WARN_ON_OOR(mask > AI_MASK); + + for (i = 0; i < AI_BITS; i++) + if (mask & (1 << i)) { + word = (AI_VALUE_OFFS + i) / DWORD_LEN; + if (bits & (1 << i)) + te->sram.word[word] |= (1 << ((i + AI_VALUE_OFFS) % DWORD_LEN)); + else + te->sram.word[word] &= ~(1 << ((i + AI_VALUE_OFFS) % DWORD_LEN)); + + word = (AI_MASK_OFFS + i) / DWORD_LEN; + te->sram.word[word] |= 1 << ((i + AI_MASK_OFFS) % DWORD_LEN); + } +} + +static int sram_sw_dump_ainfo(struct tcam_entry *te, char *buf) +{ + unsigned int word, shift, ainfo; + int i, off = 0; + + word = AI_VALUE_OFFS / DWORD_LEN; + shift = AI_VALUE_OFFS % DWORD_LEN; + ainfo = (te->sram.word[word] >> shift) & ((1 << AI_BITS) - 1); + + for (i = 0; i < AI_BITS; i++) { + if (ainfo & (1 << i)) + off += mvOsSPrintf(buf + off, " A%d", i); + } + + return off; +} + +/* 121..118 */ +void sram_sw_set_next_lookup(struct tcam_entry *te, unsigned int lookup) +{ + unsigned int word; + + WARN_ON_OOR(lookup > LU_MASK); + + word = LU_ID_OFFS / DWORD_LEN; + te->sram.word[word] |= lookup << (LU_ID_OFFS % DWORD_LEN); +} +static int sram_sw_dump_next_lookup(struct tcam_entry *te, char *buf) +{ + unsigned int word; + unsigned int lookup; + + word = LU_DONE_OFFS / DWORD_LEN; + lookup = te->sram.word[word] >> (LU_DONE_OFFS % DWORD_LEN); + lookup &= 0x1; + + if (lookup) + return mvOsSPrintf(buf, " LU=D"); + + word = LU_ID_OFFS / DWORD_LEN; + lookup = te->sram.word[word] >> (LU_ID_OFFS % DWORD_LEN); + lookup &= LU_MASK; + + if (lookup) + return mvOsSPrintf(buf, " LU=%d", lookup); + + return 0; +} + +/* + * tcam_sw_alloc - allocate new TCAM entry + * @lookup: lookup section + */ +struct tcam_entry *tcam_sw_alloc(unsigned int lookup) +{ + struct tcam_entry *te = mvOsMalloc(sizeof(struct tcam_entry)); + + WARN_ON_OOM(!te); + + tcam_sw_clear(te); + tcam_sw_set_lookup(te, lookup); + sram_sw_set_shift_update(te, 7, 0); + + return te; +} + +void tcam_sw_free(struct tcam_entry *te) +{ + mvOsFree(te); +} + +void tcam_sw_text(struct tcam_entry *te, char *text) +{ + strncpy(te->ctrl.text, text, TCAM_TEXT); + te->ctrl.text[TCAM_TEXT - 1] = 0; +} + +int tcam_sw_dump(struct tcam_entry *te, char *buf) +{ + unsigned int *word; + unsigned int off = 0; + + /* hw entry id */ + off += mvOsSPrintf(buf + off, "[%3d] ", te->ctrl.index); + + word = (unsigned int *)&te->data; + off += mvOsSPrintf(buf + off, WORD6_FMT " | ", WORD6_VAL(word)); + + word = (unsigned int *)&te->sram; + off += mvOsSPrintf(buf + off, WORD4_FMT, WORD4_VAL(word)); + + off += sram_sw_dump_next_lookup(te, buf + off); + off += sram_sw_dump_next_lookup_shift(te, buf + off); + off += sram_sw_dump_rinfo(te, buf + off); + off += sram_sw_dump_ainfo(te, buf + off); + off += sram_sw_dump_shift_update(te, buf + off); + off += sram_sw_dump_rxq(te, buf + off); + off += (te->ctrl.flags & TCAM_F_INV) ? mvOsSPrintf(buf + off, " [inv]") : 0; + off += mvOsSPrintf(buf + off, "\n "); + + word = (unsigned int *)&te->mask; + off += mvOsSPrintf(buf + off, WORD6_FMT, WORD6_VAL(word)); + off += tcam_sw_dump_ainfo(te, buf + off); + off += mvOsSPrintf(buf + off, " (%s)", te->ctrl.text); + off += mvOsSPrintf(buf + off, "\n"); + + return off; +} + +/* + * tcam_hw_inv - invalidate TCAM entry on HW + * @tid: entry index + */ +void tcam_hw_inv(int tid) +{ + MV_U32 va; + + WARN_ON_OOR(tid >= MV_ETH_TCAM_LINES); + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (0xd << TCAM_WORD_ENTRY_OFFS); + + MV_MEMIO32_WRITE(va, 1); + TCAM_DBG("%s: (inv) 0x%8x <-- 0x%x [%2x]\n", __func__, va, 1, tid); +} + +void tcam_hw_inv_all(void) +{ + MV_U32 va; + int tid = MV_ETH_TCAM_LINES; + + while (tid--) { + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (0xd << TCAM_WORD_ENTRY_OFFS); + + MV_MEMIO32_WRITE(va, 1); + TCAM_DBG("%s: (inv) 0x%8x <-- 0x%x [%2x]\n", __func__, va, 1, tid); + } +} + +/* + * tcam_hw_write - install TCAM entry on HW + * @tid: entry index + */ +int tcam_hw_write(struct tcam_entry *te, int tid) +{ + MV_U32 i, va, w32; + + TCAM_DBG("%s: tid=0x%x\n", __func__, tid); + ERR_ON_OOR(tid >= MV_ETH_TCAM_LINES); + + /* sram */ + for (i = 0; i < SRAM_LEN; i++) { + w32 = te->sram.word[i]; + /* last word triggers hardware */ + if (tcam_ctl_flags & TCAM_F_WRITE || w32 || (i == (SRAM_LEN - 1))) { + va = (MV_U32) mvPncVirtBase; + va |= (BIT16 | BIT17); + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (i << TCAM_WORD_ENTRY_OFFS); + MV_MEMIO32_WRITE(va, w32); + TCAM_DBG("%s: (sram) 0x%8x <-- 0x%x\n", __func__, va, w32); + } + } + + /* tcam */ + for (i = 0; i < TCAM_LEN - 1; i++) { + w32 = te->data.u.word[i]; + + if (tcam_ctl_flags & TCAM_F_WRITE || w32) { + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= ((2 * i) << TCAM_WORD_ENTRY_OFFS); + MV_MEMIO32_WRITE(va, w32); + TCAM_DBG("%s: (data) 0x%8x <-- 0x%x\n", __func__, va, w32); + } + } + + /* mask */ + for (i = 0; i < TCAM_LEN - 1; i++) { + w32 = te->mask.u.word[i]; + + if (tcam_ctl_flags & TCAM_F_WRITE || w32) { + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= ((2 * i + 1) << TCAM_WORD_ENTRY_OFFS); + MV_MEMIO32_WRITE(va, w32); + TCAM_DBG("%s: (mask) 0x%8x <-- 0x%x\n", __func__, va, w32); + } + } + + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (0xc << TCAM_WORD_ENTRY_OFFS); + + w32 = te->data.u.word[TCAM_LEN - 1] & 0xFFFF; + w32 |= (te->mask.u.word[TCAM_LEN - 1] << 16); + + MV_MEMIO32_WRITE(va, w32); + TCAM_DBG("%s: (last) 0x%8x <-- 0x%x\n", __func__, va, w32); + + /* FIXME: perf hit */ + if (te->ctrl.text[0]) { + TCAM_DBG("%s: (text) <-- %s\n", __func__, te->ctrl.text); + strncpy(tcam_text[tid], te->ctrl.text, TCAM_TEXT); + tcam_text[tid][TCAM_TEXT - 1] = 0; + } + + return 0; +} + +/* + * tcam_hw_read - load TCAM entry from HW + * @tid: entry index + */ +int tcam_hw_read(struct tcam_entry *te, int tid) +{ + MV_U32 i, va, w32; + + TCAM_DBG("%s: tid=0x%x\n", __func__, tid); + ERR_ON_OOR(tid >= MV_ETH_TCAM_LINES); + + te->ctrl.index = tid; + + /* sram */ + for (i = 0; i < SRAM_LEN; i++) { + va = (MV_U32) mvPncVirtBase; + va |= (BIT16 | BIT17); + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (i << TCAM_WORD_ENTRY_OFFS); + + te->sram.word[i] = w32 = MV_MEMIO32_READ(va); + TCAM_DBG("%s: (sram) 0x%8x --> 0x%x\n", __func__, va, w32); + } + + /* tcam */ + for (i = 0; i < TCAM_LEN - 1; i++) { + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= ((2 * i) << TCAM_WORD_ENTRY_OFFS); + + te->data.u.word[i] = w32 = MV_MEMIO32_READ(va); + TCAM_DBG("%s: (tcam) 0x%8x --> 0x%x\n", __func__, va, w32); + } + + /* mask */ + for (i = 0; i < TCAM_LEN - 1; i++) { + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= ((2 * i + 1) << TCAM_WORD_ENTRY_OFFS); + + te->mask.u.word[i] = w32 = MV_MEMIO32_READ(va); + TCAM_DBG("%s: (mask) 0x%8x --> 0x%x\n", __func__, va, w32); + } + + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (0xc << TCAM_WORD_ENTRY_OFFS); + + w32 = MV_MEMIO32_READ(va); + te->data.u.word[TCAM_LEN - 1] = w32 & 0xFFFF; + te->mask.u.word[TCAM_LEN - 1] = w32 >> 16; + TCAM_DBG("%s: (last) 0x%8x --> 0x%x\n", __func__, va, w32); + + va = (MV_U32) mvPncVirtBase; + va |= BIT17; + va |= (tid << TCAM_LINE_INDEX_OFFS); + va |= (0xd << TCAM_WORD_ENTRY_OFFS); + + w32 = MV_MEMIO32_READ(va); + te->ctrl.flags = w32 & TCAM_F_INV; + TCAM_DBG("%s: (inv) 0x%8x --> 0x%x\n", __func__, va, w32); + + /* text */ + TCAM_DBG("%s: (text) --> %s\n", __func__, tcam_text[tid]); + strncpy(te->ctrl.text, tcam_text[tid], TCAM_TEXT); + te->ctrl.text[TCAM_TEXT - 1] = 0; + + return 0; +} + +/* + * tcam_hw_record - record enable + */ +void tcam_hw_record(int port) +{ + TCAM_DBG("%s: port %d 0x%x <-- 1\n", __func__, port, MV_PNC_HIT_SEQ0_REG); + MV_REG_WRITE(MV_PNC_HIT_SEQ0_REG, (port << 1) | 1); +} + +/* + * tcam_hw_hits - dump hit sequence + */ +int tcam_hw_hits(char *buf) +{ + MV_U32 i, off = 0; + + off += mvOsSPrintf(buf + off, "seq hit\n"); + off += mvOsSPrintf(buf + off, "--- ---\n"); + + i = MV_REG_READ(MV_PNC_HIT_SEQ0_REG); + off += mvOsSPrintf(buf + off, "0 - %d\n", (i >> 10) & 0x3FF); + off += mvOsSPrintf(buf + off, "1 - %d\n", (i >> 20) & 0x3FF); + + i = MV_REG_READ(MV_PNC_HIT_SEQ1_REG); + off += mvOsSPrintf(buf + off, "2 - %d\n", (i >> 0) & 0x3FF); + off += mvOsSPrintf(buf + off, "3 - %d\n", (i >> 10) & 0x3FF); + off += mvOsSPrintf(buf + off, "4 - %d\n", (i >> 20) & 0x3FF); + + i = MV_REG_READ(MV_PNC_HIT_SEQ2_REG); + off += mvOsSPrintf(buf + off, "5 - %d\n", (i >> 0) & 0x3FF); + off += mvOsSPrintf(buf + off, "6 - %d\n", (i >> 10) & 0x3FF); + off += mvOsSPrintf(buf + off, "7 - %d\n", (i >> 20) & 0x3FF); + + return off; +} + +void tcam_hw_debug(int en) +{ + tcam_ctl_flags = en; +} + +/* + * tcam_hw_dump - print out TCAM registers + * @all - whether to dump all entries or valid only + */ +int tcam_hw_dump(int all) +{ + int i; + struct tcam_entry te; + char buff[1024]; + + for (i = 0; i < MV_ETH_TCAM_LINES; i++) { + tcam_sw_clear(&te); + tcam_hw_read(&te, i); + if (!all && (te.ctrl.flags & TCAM_F_INV)) + continue; + tcam_sw_dump(&te, buff); + mvOsPrintf(buff); + } + + return 0; +} + +/****************************************************************************** + * + * HW Init + * + ****************************************************************************** + */ +int tcam_hw_init(void) +{ + int i; + struct tcam_entry te; + + tcam_sw_clear(&te); + sram_sw_set_lookup_done(&te, 1); + + /* Perform full write */ + tcam_ctl_flags = TCAM_F_WRITE; + + for (i = 0; i < MV_ETH_TCAM_LINES; i++) { + sram_sw_set_flowid_lo(&te, i); + tcam_sw_text(&te, "empty"); + tcam_hw_write(&te, i); + tcam_hw_inv(i); + } + + /* Back to partial write */ + tcam_ctl_flags = 0; + + return 0; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvTcam.h u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvTcam.h --- u-boot-2009.08.orig/board/marvell/mv_hal/neta/pnc/mvTcam.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/neta/pnc/mvTcam.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,213 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_TCAM_H__ +#define __MV_TCAM_H__ + + +#define TCAM_LEN 7 /* TCAM key/mask in words */ +#define SRAM_LEN 4 /* SRAM in words */ + +#define TCAM_LINE_INDEX_OFFS 6 +#define TCAM_WORD_ENTRY_OFFS 2 + +#define AI_WORD 6 +#define AI_OFFS 0 +#define AI_BITS 7 +#define AI_MASK ((1 << AI_BITS) - 1) + +#define PORT_WORD 6 +#define PORT_OFFS 7 +#define PORT_BITS 5 +#define PORT_MASK ((1 << PORT_BITS) - 1) + +#define LU_WORD 6 +#define LU_OFFS 12 +#define LU_BITS 4 +#define LU_MASK ((1 << LU_BITS) - 1) + + +#define RI_BITS 24 +#define RI_MASK ((1 << RI_BITS) - 1) +#define SHIFT_VAL_BITS 7 +#define SHIFT_VAL_MASK ((1 << SHIFT_VAL_BITS) - 1) +#define SHIFT_IDX_BITS 3 +#define SHIFT_IDX_MASK ((1 << SHIFT_IDX_BITS) - 1) +#define RXQ_BITS 3 +#define RXQ_MASK ((1 << RXQ_BITS) - 1) + +#define RI_VALUE_OFFS 34 +#define RI_MASK_OFFS 58 +#define SHIFT_VAL_OFFS 82 /* shift update value offset */ +#define SHIFT_IDX_OFFS 89 /* shift update index offset */ +#define RXQ_INFO_OFFS 92 +#define RXQ_QUEUE_OFFS 93 +#define NEXT_LU_SHIFT_OFFS 96 +#define LU_DONE_OFFS 99 +#define AI_VALUE_OFFS 104 +#define AI_MASK_OFFS 111 +#define LU_ID_OFFS 118 + + +#define SHIFT_IP4_HLEN 126 /* IPv4 dynamic shift index */ +#define SHIFT_IP6_HLEN 127 /* IPv6 dynamic shift index */ + +/* + * TCAM misc/control + */ +#define TCAM_F_INV 1 +#define TCAM_TEXT 16 + +/* + * TCAM control + */ +struct tcam_ctrl { + unsigned int index; + unsigned int flags; + unsigned char text[TCAM_TEXT]; +}; + +/* + * TCAM key + */ +struct tcam_data { + union { + unsigned int word[TCAM_LEN]; + unsigned char byte[TCAM_LEN*4]; + } u; +}; + +/* + * TCAM mask + */ +struct tcam_mask { + union { + unsigned int word[TCAM_LEN]; + unsigned char byte[TCAM_LEN*4]; + } u; +}; + +/* + * SRAM entry + */ +struct sram_entry { + unsigned int word[SRAM_LEN]; +}; + +/* + * TCAM entry + */ +struct tcam_entry { + struct tcam_data data; + struct tcam_mask mask; + struct sram_entry sram; + struct tcam_ctrl ctrl; +} __attribute__((packed)); + +/* + * TCAM Low Level API + */ +struct tcam_entry *tcam_sw_alloc(unsigned int section); +void tcam_sw_free(struct tcam_entry *te); +int tcam_sw_dump(struct tcam_entry *te, char *buf); +void tcam_sw_clear(struct tcam_entry *te); + +void tcam_sw_set_port(struct tcam_entry *te, unsigned int port, unsigned int mask); +void tcam_sw_get_port(struct tcam_entry *te, unsigned int *port, unsigned int *mask); + +void tcam_sw_set_lookup(struct tcam_entry *te, unsigned int lookup); +void tcam_sw_get_lookup(struct tcam_entry *te, unsigned int *lookup, unsigned int *mask); +void tcam_sw_set_ainfo(struct tcam_entry *te, unsigned int bits, unsigned int mask); +void tcam_sw_set_byte(struct tcam_entry *te, unsigned int offset, unsigned char data); + +int tcam_sw_cmp_byte(struct tcam_entry *te, unsigned int offset, unsigned char data); +int tcam_sw_cmp_bytes(struct tcam_entry *te, unsigned int offset, unsigned int size, unsigned char *data); + +void tcam_sw_set_mask(struct tcam_entry *te, unsigned int offset, unsigned char mask); +void sram_sw_set_rinfo(struct tcam_entry *te, unsigned int bit); +void sram_sw_set_shift_update(struct tcam_entry *te, unsigned int index, unsigned int value); +void sram_sw_set_rxq(struct tcam_entry *te, unsigned int rxq); + +unsigned int sram_sw_get_rxq(struct tcam_entry *te); + +void sram_sw_set_next_lookup_shift(struct tcam_entry *te, unsigned int index); +void sram_sw_set_lookup_done(struct tcam_entry *te, unsigned int value); +void sram_sw_set_next_lookup_shift(struct tcam_entry *te, unsigned int value); +void sram_sw_set_ainfo(struct tcam_entry *te, unsigned int bits, unsigned int mask); +void sram_sw_set_next_lookup(struct tcam_entry *te, unsigned int lookup); +void sram_sw_set_flowid_lo(struct tcam_entry *te, unsigned int flowid); +void sram_sw_set_flowid_hi(struct tcam_entry *te, unsigned int flowid); +void tcam_sw_text(struct tcam_entry *te, char *text); +int tcam_hw_write(struct tcam_entry *te, int tid); +int tcam_hw_read(struct tcam_entry *te, int tid); +void tcam_hw_inv(int tid); +void tcam_hw_inv_all(void); +void tcam_hw_debug(int); +int tcam_hw_dump(int); +int tcam_hw_hits(char *buf); +void tcam_hw_record(int); +int tcam_hw_init(void); + +#endif + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/nfc/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/nfc/mvCompVer.txt 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: DOVE_HAL_3_1_2 +Unit HAL Version: 1.0.2 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfc.c u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfc.c --- u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfc.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfc.c 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,2286 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysNfcConfig.h" +#include "mvNfcRegs.h" +#ifdef MV_INCLUDE_PDMA +#include "pdma/mvPdma.h" +#include "pdma/mvPdmaRegs.h" +#endif +#include "mvNfc.h" + + +/*************/ +/* Constants */ +/*************/ + +#define NFC_NATIVE_READ_ID_CMD 0x0090 +#define NFC_READ_ID_ADDR_LEN 1 +#define NFC_ERASE_ADDR_LEN 3 +#define NFC_SP_READ_ADDR_LEN 3 +#define NFC_SP_BIG_READ_ADDR_LEN 4 +#define NFC_LP_READ_ADDR_LEN 5 +#define NFC_BLOCK_ADDR_BITS 0xFFFFFF +#define NFC_SP_COL_OFFS 0 +#define NFC_SP_COL_MASK (0xFF << NFC_SP_COL_OFFS) +#define NFC_LP_COL_OFFS 0 +#define NFC_LP_COL_MASK (0xFFFF << NFC_SP_COL_OFFS) +#define NFC_SP_PG_OFFS 8 +#define NFC_SP_PG_MASK (0xFFFFFF << NFC_SP_PG_OFFS) +#define NFC_LP_PG_OFFS 16 +#define NFC_LP_PG_MASK (0xFFFF << NFC_LP_PG_OFFS) +#define NFC_PG_CNT_OFFS 8 +#define NFC_PG_CNT_MASK (0xFF << NFC_PG_CNT_OFFS) + +#define NFC_READ_ID_PDMA_DATA_LEN 32 +#define NFC_READ_STATUS_PDMA_DATA_LEN 32 +#define NFC_READ_ID_PIO_DATA_LEN 8 +#define NFC_READ_STATUS_PIO_DATA_LEN 8 +#define NFC_RW_SP_PDMA_DATA_LEN 544 +#define NFC_RW_SP_NO_ECC_DATA_LEN 528 +#define NFC_RW_SP_HMNG_ECC_DATA_LEN 520 +#define NFC_RW_SP_G_NO_ECC_DATA_LEN 528 +#define NFC_RW_SP_G_HMNG_ECC_DATA_LEN 526 + +#define NFC_RW_LP_PDMA_DATA_LEN 2112 + +#define NFC_RW_LP_NO_ECC_DATA_LEN 2112 +#define NFC_RW_LP_HMNG_ECC_DATA_LEN 2088 +#define NFC_RW_LP_BCH_ECC_DATA_LEN 2080 + +#define NFC_RW_LP_G_NO_ECC_DATA_LEN 2112 +#define NFC_RW_LP_G_HMNG_ECC_DATA_LEN 2088 +#define NFC_RW_LP_G_BCH_ECC_DATA_LEN 2080 + +#define NFC_RW_LP_BCH1K_ECC_DATA_LEN 1024 +#define NFC_RW_LP_BCH704B_ECC_DATA_LEN 704 +#define NFC_RW_LP_BCH512B_ECC_DATA_LEN 512 + +#define NFC_CMD_STRUCT_SIZE (sizeof(MV_NFC_CMD)) +#define NFC_CMD_BUFF_SIZE(cmdb_0) ((cmdb_0 & NFC_CB0_LEN_OVRD_MASK) ? 16 : 12) +#define NFC_CMD_BUFF_ADDR (NFC_COMMAND_BUFF_0_REG_4PDMA) +#define NFC_DATA_BUFF_ADDR (NFC_DATA_BUFF_REG_4PDMA) + +/**********/ +/* Macros */ +/**********/ +#define ns_clk(ns, ns2clk) ((ns % ns2clk) ? (MV_U32)((ns/ns2clk)+1) : (MV_U32)(ns/ns2clk)) + +#define DBGPRINT(x) printk x +#define DBGLVL KERN_INFO + +/***********/ +/* Typedef */ +/***********/ + +/* Flash Timing Parameters */ +typedef struct { + /* Flash Timing */ + MV_U32 tADL; /* Address to write data delay */ + MV_U32 tCH; /* Enable signal hold time */ + MV_U32 tCS; /* Enable signal setup time */ + MV_U32 tWH; /* ND_nWE high duration */ + MV_U32 tWP; /* ND_nWE pulse time */ + MV_U32 tRH; /* ND_nRE high duration */ + MV_U32 tRP; /* ND_nRE pulse width */ + MV_U32 tR; /* ND_nWE high to ND_nRE low for read */ + MV_U32 tWHR; /* ND_nWE high to ND_nRE low for status read */ + MV_U32 tAR; /* ND_ALE low to ND_nRE low delay */ + MV_U32 tRHW; /* ND_nRE high to ND_nWE low delay */ + /* Physical Layout */ + MV_U32 pgPrBlk; /* Pages per block */ + MV_U32 pgSz; /* Page size */ + MV_U32 oobSz; /* Page size */ + MV_U32 blkNum; /* Number of blocks per device */ + MV_U32 id; /* Manufacturer and device IDs */ + MV_U32 seqDis; /* Enable/Disable sequential multipage read */ + MV_8 * model; /* Flash Model string */ + MV_U32 bb_page; /* Page containing bad block marking */ +}MV_NFC_FLASH_INFO; + +/* Flash command set */ +typedef struct { + MV_U16 read1; + MV_U16 exitCacheRead; + MV_U16 cacheReadRand; + MV_U16 cacheReadSeq; + MV_U16 read2; + MV_U16 program; + MV_U16 readStatus; + MV_U16 readId; + MV_U16 erase; + MV_U16 multiplaneErase; + MV_U16 reset; + MV_U16 lock; + MV_U16 unlock; + MV_U16 lockStatus; +} MV_NFC_FLASH_CMD_SET; + +/********/ +/* Data */ +/********/ + +/* Defined Flash Types */ +MV_NFC_FLASH_INFO flashDeviceInfo[] = { + { /* ST 8Gb */ + .tADL = 0, /* tADL, Address to write data delay */ + .tCH = 5, /* tCH, Enable signal hold time */ + .tCS = 20, /* tCS, Enable signal setup time */ + .tWH = 12, /* tWH, ND_nWE high duration */ + .tWP = 12, /* tWP, ND_nWE pulse time */ + .tRH = 12, /* tRH, ND_nRE high duration */ + .tRP = 12, /* tRP, ND_nRE pulse width */ + .tR = 25121, /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */ + .tWHR = 60, /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + .tRHW = 48, /* tRHW, ND_nRE high to ND_nWE low delay */ + .pgPrBlk = 64, /* Pages per block - detected */ + .pgSz = 2048, /* Page size */ + .oobSz = 64, /* Spare size */ + .blkNum = 2048, /* Number of blocks/sectors in the flash */ + .id = 0xD320, /* Device ID 0xDevice,Vendor */ + .model = "ST 8Gb 8bit", + .bb_page = 63, /* Manufacturer Bad block marking page in block */ + }, + { /* ST 32Gb */ + .tADL = 0, /* tADL, Address to write data delay */ + .tCH = 5, /* tCH, Enable signal hold time */ + .tCS = 20, /* tCS, Enable signal setup time */ + .tWH = 10, /* tWH, ND_nWE high duration */ + .tWP = 12, /* tWP, ND_nWE pulse time */ + .tRH = 10, /* tRH, ND_nRE high duration */ + .tRP = 12, /* tRP, ND_nRE pulse width */ + .tR = 25121, /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */ + .tWHR = 80, /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + .tRHW = 48, /* tRHW, ND_nRE high to ND_nWE low delay */ + .pgPrBlk = 64, /* Pages per block - detected */ + .pgSz = 4096, /* Page size */ + .oobSz = 128, /* Spare size */ + .blkNum = 16384,/* Number of blocks/sectors in the flash */ + .id = 0xD520, /* Device ID 0xVendor,device */ + .model = "ST 32Gb 8bit", + .bb_page = 63, /* Manufacturer Bad block marking page in block */ + }, + + { /* Samsung 16Gb */ + .tADL = 90, /* tADL, Address to write data delay */ + .tCH = 0, /* tCH, Enable signal hold time */ + .tCS = 5, /* tCS, Enable signal setup time */ + .tWH = 10, /* tWH, ND_nWE high duration */ + .tWP = 12, /* tWP, ND_nWE pulse time */ + .tRH = 12, /* tRH, ND_nRE high duration */ + .tRP = 12, /* tRP, ND_nRE pulse width */ + .tR = 49146, /* tR = data transfer from cell to register, maximum 60,000ns */ + .tWHR = 66, /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tAR = 66, /* tAR, ND_ALE low to ND_nRE low delay */ + .tRHW = 32, /* tRHW, ND_nRE high to ND_nWE low delay 32 clocks */ + .pgPrBlk = 128, /* Pages per block - detected */ + .pgSz = 2048, /* Page size */ + .oobSz = 64, /* Spare size */ + .blkNum = 8192, /* Number of blocks/sectors in the flash */ + .id = 0xD5EC, /* Device ID 0xDevice,Vendor */ + .model = "Samsung 16Gb 8bit", + .bb_page = 127, /* Manufacturer Bad block marking page in block */ + }, + + { /* Samsung 32Gb */ + .tADL = 0, /* tADL, Address to write data delay */ + .tCH = 5, /* tCH, Enable signal hold time */ + .tCS = 20, /* tCS, Enable signal setup time */ + .tWH = 10, /* tWH, ND_nWE high duration */ + .tWP = 15, /* tWP, ND_nWE pulse time */ + .tRH = 15, /* tRH, ND_nRE high duration */ + .tRP = 15, /* tRP, ND_nRE pulse width */ + .tR = 60000, /* tR = data transfer from cell to register, maximum 60,000ns */ + .tWHR = 60, /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + .tRHW = 48, /* tRHW, ND_nRE high to ND_nWE low delay */ + .pgPrBlk = 128, /* Pages per block - detected */ + .pgSz = 4096, /* Page size */ + .oobSz = 128, /* Spare size */ + .blkNum = 8192, /* Number of blocks/sectors in the flash */ + .id = 0xD7EC, /* Device ID 0xDevice,Vendor */ + .model = "Samsung 32Gb 8bit", + .bb_page = 127, /* Manufacturer Bad block marking page in block */ + }, + + { /* Micron 64Gb */ + .tADL = 0, /* tADL, Address to write data delay */ + .tCH = 20, /* tCH, Enable signal hold time */ + .tCS = 20, /* tCS, Enable signal setup time */ + .tWH = 45, /* tWH, ND_nWE high duration */ + .tWP = 45, /* tWP, ND_nWE pulse time */ + .tRH = 45, /* tRH, ND_nRE high duration */ + .tRP = 45, /* tRP, ND_nRE pulse width */ + .tR = 0, /* tR = data transfer from cell to register */ + .tWHR = 90, /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tAR = 65, /* tAR, ND_ALE low to ND_nRE low delay */ + .tRHW = 32, /* tRHW, ND_nRE high to ND_nWE low delay */ + .pgPrBlk = 256, /* Pages per block - detected */ + .pgSz = 8192, /* Page size */ + .oobSz = 448, /* Spare size */ + .blkNum = 4096, /* Number of blocks/sectors in the flash */ + .id = 0x882C, /* Device ID 0xDevice,Vendor */ + .model = "Micron 64Gb 8bit", + .bb_page = 0, /* Manufacturer Bad block marking page in block */ + } + + }; + +/* Defined Command set */ +#define MV_NFC_FLASH_SP_CMD_SET_IDX 0 +#define MV_NFC_FLASH_LP_CMD_SET_IDX 1 +static MV_NFC_FLASH_CMD_SET flashCmdSet[] = { + { + .read1 = 0x0000, + .read2 = 0x0050, + .program = 0x1080, + .readStatus = 0x0070, + .readId = 0x0090, + .erase = 0xD060, + .multiplaneErase = 0xD160, + .reset = 0x00FF, + .lock = 0x002A, + .unlock = 0x2423, + .lockStatus = 0x007A, + }, + { + .read1 = 0x3000, + .exitCacheRead = 0x003f, + .cacheReadRand = 0x3100, + .cacheReadSeq = 0x0031, + .read2 = 0x0050, + .program = 0x1080, + .readStatus = 0x0070, + .readId = 0x0090, + .erase = 0xD060, + .multiplaneErase = 0xD160, + .reset = 0x00FF, + .lock = 0x002A, + .unlock = 0x2423, + .lockStatus = 0x007A, + }}; +#define MV_NFC_REG_DBG +#ifdef MV_NFC_REG_DBG +MV_U32 mvNfcDbgFlag=1; + +MV_U32 nfc_dbg_read(MV_U32 addr) +{ + MV_U32 reg = MV_MEMIO_LE32_READ((addr)); + if (mvNfcDbgFlag) mvOsPrintf("NFC read 0x%08x = %08x\n", addr, reg); + return reg; +} + +MV_VOID nfc_dbg_write(MV_U32 addr, MV_U32 val) +{ + MV_MEMIO_LE32_WRITE((addr), (val)); + + if (mvNfcDbgFlag) mvOsPrintf("NFC write 0x%08x = %08x\n", addr, val); +} + +#undef MV_REG_READ +#undef MV_REG_WRITE +#define MV_REG_READ(x) nfc_dbg_read(x) +#define MV_REG_WRITE(x,y) nfc_dbg_write(x,y) +#endif + +/**************/ +/* Prototypes */ +/**************/ +static MV_STATUS mvDfcWait4Complete(MV_U32 statMask, MV_U32 usec); +static MV_STATUS mvNfcReadIdNative(MV_NFC_CHIP_SEL cs,MV_U16 *id); +static MV_STATUS mvNfcTimingSet(MV_U32 tclk, MV_NFC_FLASH_INFO *flInfo); +static MV_U32 mvNfcColBits(MV_U32 pg_size); +#ifdef CONFIG_MTD_NAND_NFC_INIT_RESET +static MV_STATUS mvNfcReset(void); +#endif + +/******************************************************************************* +* mvNfcInit +* +* DESCRIPTION: +* Initialize the NAND controller unit, and perform a detection of the +* attached NAND device. +* +* INPUT: +* nfcInfo - Flash information parameters. +* +* OUTPUT: +* nfcCtrl - Nand control and status information to be held by the user +* and passed to all other APIs. +* +* RETURN: +* MV_OK - On success, +* MV_BAD_PARAM - The required ECC mode not supported by flash. +* MV_NOT_SUPPORTED- The underlying flash device is not supported by HAL. +* MV_TIMEOUT - Error accessing the underlying flahs device. +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcInit(MV_NFC_INFO *nfcInfo, MV_NFC_CTRL *nfcCtrl) +{ + MV_U32 ctrl_reg; + MV_STATUS ret; + MV_U16 read_id = 0; + MV_U32 i; + /* Initial register values */ + ctrl_reg = 0; + + /* make sure ECC is disabled at this point - will be enabled only when issuing certain commands */ + MV_REG_BIT_RESET(NFC_CONTROL_REG, NFC_CTRL_ECC_EN_MASK); + if (nfcInfo->eccMode != MV_NFC_ECC_HAMMING) + MV_REG_BIT_RESET(NFC_ECC_CONTROL_REG, NFC_ECC_BCH_EN_MASK); + + if ((nfcInfo->eccMode == MV_NFC_ECC_BCH_1K) || + (nfcInfo->eccMode == MV_NFC_ECC_BCH_704B) || + (nfcInfo->eccMode == MV_NFC_ECC_BCH_512B)) + + { + /* Disable spare */ + ctrl_reg &= ~NFC_CTRL_SPARE_EN_MASK; + } + else + { + /* Enable spare */ + ctrl_reg |= NFC_CTRL_SPARE_EN_MASK; + } + + ctrl_reg &= ~NFC_CTRL_ECC_EN_MASK; + + /* Configure flash interface */ + if (nfcInfo->ifMode == MV_NFC_IF_1X16) + { + nfcCtrl->flashWidth = 16; + nfcCtrl->dfcWidth = 16; + ctrl_reg |= (NFC_CTRL_DWIDTH_M_MASK | NFC_CTRL_DWIDTH_C_MASK); + } + else if (nfcInfo->ifMode == MV_NFC_IF_2X8) + { + nfcCtrl->flashWidth = 8; + nfcCtrl->dfcWidth = 16; + ctrl_reg |= NFC_CTRL_DWIDTH_C_MASK; + } + else + { + nfcCtrl->flashWidth = 8; + nfcCtrl->dfcWidth = 8; + } + + /* Configure initial READ-ID byte count */ + ctrl_reg |= (0x2 << NFC_CTRL_RD_ID_CNT_OFFS); + + /* Configure the Arbiter */ + ctrl_reg |= NFC_CTRL_ND_ARB_EN_MASK; + + /* Write registers before device detection */ + MV_REG_WRITE(NFC_CONTROL_REG, ctrl_reg); + +#ifdef CONFIG_MTD_NAND_NFC_INIT_RESET + /* reset the device */ + if ((ret = mvNfcReset()) != MV_OK) { + return ret; + } +#endif + + /* Read the device ID */ + if ((ret = mvNfcReadIdNative(nfcCtrl->currCs,&read_id)) != MV_OK) { + printf("i'm here, can't read device ID...\n"); + return ret; + } + + /* Look for device ID in knwon device table */ + for (i=0; i<(sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO)); i++) + { + if (flashDeviceInfo[i].id == read_id) + break; + } + if (i == (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return MV_NOT_SUPPORTED; + else + nfcCtrl->flashIdx = i; + + /* Configure the command set based on page size */ + if (flashDeviceInfo[i].pgSz < MV_NFC_2KB_PAGE) + nfcCtrl->cmdsetIdx = MV_NFC_FLASH_SP_CMD_SET_IDX; + else + nfcCtrl->cmdsetIdx = MV_NFC_FLASH_LP_CMD_SET_IDX; + + /* calculate Timing parameters */ + if ((ret = mvNfcTimingSet(nfcInfo->tclk, &flashDeviceInfo[i])) != MV_OK) { + return ret; + } + + /* Configure the control register based on the device detected */ + ctrl_reg = MV_REG_READ(NFC_CONTROL_REG); + + /* Configure DMA */ + if (nfcInfo->ioMode == MV_NFC_PDMA_ACCESS) + ctrl_reg |= NFC_CTRL_DMA_EN_MASK; + else + ctrl_reg &= ~NFC_CTRL_DMA_EN_MASK; + + /* Configure Page size */ + ctrl_reg &= ~NFC_CTRL_PAGE_SZ_MASK; + switch (flashDeviceInfo[i].pgSz) + { + case MV_NFC_512B_PAGE: + ctrl_reg |= NFC_CTRL_PAGE_SZ_512B; + break; + + case MV_NFC_2KB_PAGE: + case MV_NFC_4KB_PAGE: + case MV_NFC_8KB_PAGE: + ctrl_reg |= NFC_CTRL_PAGE_SZ_2KB; + break; + + default: + return MV_BAD_PARAM; + } + + /* Disable sequential read if indicated */ + if (flashDeviceInfo[i].seqDis) + ctrl_reg |= NFC_CTRL_SEQ_DIS_MASK; + else + ctrl_reg &= ~NFC_CTRL_SEQ_DIS_MASK; + + /* Configure the READ-ID count and row address start based on page size */ + ctrl_reg &= ~(NFC_CTRL_RD_ID_CNT_MASK | NFC_CTRL_RA_START_MASK); + if (flashDeviceInfo[i].pgSz >= MV_NFC_2KB_PAGE) + { + ctrl_reg |= NFC_CTRL_RD_ID_CNT_LP; + ctrl_reg |= NFC_CTRL_RA_START_MASK; + } + else + { + ctrl_reg |= NFC_CTRL_RD_ID_CNT_SP; + } + + /* Confiugre pages per block */ + ctrl_reg &= ~NFC_CTRL_PG_PER_BLK_MASK; + switch (flashDeviceInfo[i].pgPrBlk) + { + case 32: + ctrl_reg |= NFC_CTRL_PG_PER_BLK_32; + break; + + case 64: + ctrl_reg |= NFC_CTRL_PG_PER_BLK_64; + break; + + case 128: + ctrl_reg |= NFC_CTRL_PG_PER_BLK_128; + break; + + case 256: + ctrl_reg |= NFC_CTRL_PG_PER_BLK_256; + break; + + default: + return MV_BAD_PARAM; + } + + /* Write the updated control register */ + MV_REG_WRITE(NFC_CONTROL_REG, ctrl_reg); + +#ifdef MV_INCLUDE_PDMA + /* DMA resource allocation */ + if (nfcInfo->ioMode == MV_NFC_PDMA_ACCESS) + { + /* Allocate command buffer */ + if ((nfcCtrl->cmdBuff.bufVirtPtr = mvOsIoUncachedMalloc(nfcInfo->osHandle, (NFC_CMD_STRUCT_SIZE * MV_NFC_MAX_DESC_CHAIN), + &nfcCtrl->cmdBuff.bufPhysAddr, &nfcCtrl->cmdBuff.memHandle)) == NULL) + return MV_OUT_OF_CPU_MEM; + nfcCtrl->cmdBuff.bufSize = (NFC_CMD_STRUCT_SIZE * MV_NFC_MAX_DESC_CHAIN); + nfcCtrl->cmdBuff.dataSize = (NFC_CMD_STRUCT_SIZE * MV_NFC_MAX_DESC_CHAIN); + + /* Allocate command DMA descriptors */ + if ((nfcCtrl->cmdDescBuff.bufVirtPtr = mvOsIoUncachedMalloc(nfcInfo->osHandle, (MV_PDMA_DESC_SIZE * (MV_NFC_MAX_DESC_CHAIN+1)), + &nfcCtrl->cmdDescBuff.bufPhysAddr, &nfcCtrl->cmdDescBuff.memHandle)) == NULL) + return MV_OUT_OF_CPU_MEM; + /* verify allignment to 128bits */ + if ((MV_U32)nfcCtrl->cmdDescBuff.bufVirtPtr & 0xF) + { + nfcCtrl->cmdDescBuff.bufVirtPtr = (MV_U8*)(((MV_U32)nfcCtrl->cmdDescBuff.bufVirtPtr & ~0xF) + MV_PDMA_DESC_SIZE); + nfcCtrl->cmdDescBuff.bufPhysAddr = ((nfcCtrl->cmdDescBuff.bufPhysAddr & ~0xF) + MV_PDMA_DESC_SIZE); + } + nfcCtrl->cmdDescBuff.bufSize = (MV_PDMA_DESC_SIZE * MV_NFC_MAX_DESC_CHAIN); + nfcCtrl->cmdDescBuff.dataSize = (MV_PDMA_DESC_SIZE * MV_NFC_MAX_DESC_CHAIN); + + /* Allocate data DMA descriptors */ + if ((nfcCtrl->dataDescBuff.bufVirtPtr = mvOsIoUncachedMalloc(nfcInfo->osHandle, (MV_PDMA_DESC_SIZE * (MV_NFC_MAX_DESC_CHAIN+1)), + &nfcCtrl->dataDescBuff.bufPhysAddr, &nfcCtrl->dataDescBuff.memHandle)) == NULL) + return MV_OUT_OF_CPU_MEM; + /* verify allignment to 128bits */ + if ((MV_U32)nfcCtrl->dataDescBuff.bufVirtPtr & 0xF) + { + nfcCtrl->dataDescBuff.bufVirtPtr = (MV_U8*)(((MV_U32)nfcCtrl->dataDescBuff.bufVirtPtr & ~0xF) + MV_PDMA_DESC_SIZE); + nfcCtrl->dataDescBuff.bufPhysAddr = ((nfcCtrl->dataDescBuff.bufPhysAddr & ~0xF) + MV_PDMA_DESC_SIZE); + } + nfcCtrl->dataDescBuff.bufSize = (MV_PDMA_DESC_SIZE * MV_NFC_MAX_DESC_CHAIN); + nfcCtrl->dataDescBuff.dataSize = (MV_PDMA_DESC_SIZE * MV_NFC_MAX_DESC_CHAIN); + + /* Allocate Data DMA channel */ + if (mvPdmaChanAlloc(MV_PDMA_NAND_DATA, nfcInfo->dataPdmaIntMask, &nfcCtrl->dataChanHndl) != MV_OK) + return MV_NO_RESOURCE; + + /* Allocate Command DMA channel */ + if (mvPdmaChanAlloc(MV_PDMA_NAND_COMMAND, nfcInfo->cmdPdmaIntMask, &nfcCtrl->cmdChanHndl) != MV_OK) + return MV_NO_RESOURCE; + } +#endif + + /* Initialize remaining fields in the CTRL structure */ + nfcCtrl->autoStatusRead = nfcInfo->autoStatusRead; + nfcCtrl->readyBypass = nfcInfo->readyBypass; + nfcCtrl->ioMode = nfcInfo->ioMode; + nfcCtrl->eccMode = nfcInfo->eccMode; + nfcCtrl->ifMode = nfcInfo->ifMode; + nfcCtrl->currCs = MV_NFC_CS_NONE; + nfcCtrl->regsPhysAddr = nfcInfo->regsPhysAddr; +#ifdef MV_INCLUDE_PDMA + nfcCtrl->dataPdmaIntMask = nfcInfo->dataPdmaIntMask; + nfcCtrl->cmdPdmaIntMask = nfcInfo->cmdPdmaIntMask; +#endif + + return MV_OK; +} + + +/******************************************************************************* +* mvNfcSelectChip +* +* DESCRIPTION: +* Set the currently active chip for next commands. +* +* INPUT: +* nfcCtrl - Nand control structure. +* chip - The chip number to operate on. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcSelectChip(MV_NFC_CTRL *nfcCtrl, MV_NFC_CHIP_SEL chip) +{ + nfcCtrl->currCs = chip; + return MV_OK; +} + + +/******************************************************************************* +* mvNfcDataLength +* +* DESCRIPTION: +* Get the length of data based on the NFC configuration +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - Command to be executed +* +* OUTPUT: +* data_len - length of data to be transfered +* +* RETURN: +* MV_OK - On success, +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcDataLength(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *data_len) +{ + /* Decide read data size based on page size */ + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) /* Small Page */ + { + if (nfcCtrl->ifMode == MV_NFC_IF_2X8) + { + if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_SP_G_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_SP_G_NO_ECC_DATA_LEN; + } + else + { + if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_SP_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_SP_NO_ECC_DATA_LEN; + } + } + else /* Large Page */ + { + if (nfcCtrl->ifMode == MV_NFC_IF_2X8) + { + if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_2K) + *data_len = NFC_RW_LP_G_BCH_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_1K) + *data_len = NFC_RW_LP_BCH1K_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_704B) + *data_len = NFC_RW_LP_BCH704B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_512B) + *data_len = NFC_RW_LP_BCH512B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_LP_G_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_LP_G_NO_ECC_DATA_LEN; + } + else + { + if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_2K) + *data_len = NFC_RW_LP_BCH_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_1K) + *data_len = NFC_RW_LP_BCH1K_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_704B) + *data_len = NFC_RW_LP_BCH704B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_512B) + *data_len = NFC_RW_LP_BCH512B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_LP_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_LP_NO_ECC_DATA_LEN; + } + } + return MV_OK; +} + +/******************************************************************************* +* mvNfcTransferDataLength +* +* DESCRIPTION: +* Get the length of data to be transfered based on the command type and +* NFC configuration +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - Command to be executed +* +* OUTPUT: +* data_len - length of data to be transfered +* +* RETURN: +* MV_OK - On success, +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcTransferDataLength(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 * data_len) +{ + switch (cmd) + { + case MV_NFC_CMD_READ_ID: + if (nfcCtrl->ioMode == MV_NFC_PDMA_ACCESS) + *data_len = NFC_READ_ID_PDMA_DATA_LEN; + else + *data_len = NFC_READ_ID_PIO_DATA_LEN; + break; + + case MV_NFC_CMD_READ_STATUS: + if (nfcCtrl->ioMode == MV_NFC_PDMA_ACCESS) + *data_len = NFC_READ_STATUS_PDMA_DATA_LEN; + else + *data_len = NFC_READ_STATUS_PIO_DATA_LEN; + break; + + case MV_NFC_CMD_READ_MONOLITHIC: /* Read a single 512B or 2KB page */ + case MV_NFC_CMD_READ_MULTIPLE: + case MV_NFC_CMD_READ_NAKED: + case MV_NFC_CMD_READ_LAST_NAKED: + case MV_NFC_CMD_READ_DISPATCH: + case MV_NFC_CMD_WRITE_MONOLITHIC: /* Program a single page of 512B or 2KB */ + case MV_NFC_CMD_WRITE_MULTIPLE: + case MV_NFC_CMD_WRITE_NAKED: + case MV_NFC_CMD_WRITE_LAST_NAKED: + case MV_NFC_CMD_WRITE_DISPATCH: + case MV_NFC_CMD_EXIT_CACHE_READ: + case MV_NFC_CMD_CACHE_READ_SEQ: + case MV_NFC_CMD_CACHE_READ_START: + if (nfcCtrl->ioMode == MV_NFC_PDMA_ACCESS) + { + /* Decide read data size based on page size */ + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) /* Small Page */ + { + *data_len = NFC_RW_SP_PDMA_DATA_LEN; + } + else /* Large Page */ + { + if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_2K) + *data_len = NFC_RW_LP_BCH_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_1K) + *data_len = NFC_RW_LP_BCH1K_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_704B) + *data_len = NFC_RW_LP_BCH704B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_512B) + *data_len = NFC_RW_LP_BCH512B_ECC_DATA_LEN; + else /* Hamming and No-Ecc */ + *data_len = NFC_RW_LP_PDMA_DATA_LEN; + } + } + else /* PIO mode */ + { + /* Decide read data size based on page size */ + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) /* Small Page */ + { + if (nfcCtrl->ifMode == MV_NFC_IF_2X8) + { + if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_SP_G_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_SP_G_NO_ECC_DATA_LEN; + } + else + { + if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_SP_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_SP_NO_ECC_DATA_LEN; + } + } + else /* Large Page */ + { + if (nfcCtrl->ifMode == MV_NFC_IF_2X8) + { + if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_2K) + *data_len = NFC_RW_LP_G_BCH_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_1K) + *data_len = NFC_RW_LP_BCH1K_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_704B) + *data_len = NFC_RW_LP_BCH704B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_512B) + *data_len = NFC_RW_LP_BCH512B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_LP_G_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_LP_G_NO_ECC_DATA_LEN; + } + else + { + if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_2K) + *data_len = NFC_RW_LP_BCH_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_1K) + *data_len = NFC_RW_LP_BCH1K_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_704B) + *data_len = NFC_RW_LP_BCH704B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_BCH_512B) + *data_len = NFC_RW_LP_BCH512B_ECC_DATA_LEN; + else if (nfcCtrl->eccMode == MV_NFC_ECC_HAMMING) + *data_len = NFC_RW_LP_HMNG_ECC_DATA_LEN; + else /* No ECC */ + *data_len = NFC_RW_LP_NO_ECC_DATA_LEN; + } + } + } + break; + + case MV_NFC_CMD_ERASE: + case MV_NFC_CMD_MULTIPLANE_ERASE: + case MV_NFC_CMD_RESET: + case MV_NFC_CMD_WRITE_DISPATCH_START: + case MV_NFC_CMD_WRITE_DISPATCH_END: + return MV_BAD_PARAM; + + default: + return MV_BAD_PARAM; + + }; + + return MV_OK; +} + +/******************************************************************************* +* mvNfcBuildCommand +* +* DESCRIPTION: +* Build the command buffer +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - Command to be executed +* cmdb - Command buffer cmdb[0:3] to fill +* +* OUTPUT: +* cmdb - Command buffer filled +* +* RETURN: +* None +*******************************************************************************/ +static MV_STATUS mvNfcBuildCommand(MV_NFC_CTRL *nfcCtrl, MV_NFC_MULTI_CMD *descInfo, MV_U32 * cmdb) +{ + cmdb[0] = 0; + cmdb[1] = 0; + cmdb[2] = 0; + cmdb[3] = 0; + if (nfcCtrl->autoStatusRead) + cmdb[0] |= NFC_CB0_AUTO_RS_MASK; + + if ((nfcCtrl->currCs == MV_NFC_CS_1) || (nfcCtrl->currCs == MV_NFC_CS_3)) + cmdb[0] |= NFC_CB0_CSEL_MASK; + + if ((nfcCtrl->currCs == MV_NFC_CS_2) || (nfcCtrl->currCs == MV_NFC_CS_3)) + cmdb[2] |= NFC_CB2_CS_2_3_SELECT_MASK; + + if (nfcCtrl->readyBypass) + cmdb[0] |= NFC_CB0_RDY_BYP_MASK; + + switch (descInfo->cmd) + { + case MV_NFC_CMD_READ_ID: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].readId & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + cmdb[0] |= ((NFC_READ_ID_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[0] |= NFC_CB0_CMD_TYPE_READ_ID; + break; + + case MV_NFC_CMD_READ_STATUS: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].readStatus & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + cmdb[0] |= NFC_CB0_CMD_TYPE_STATUS; + break; + + case MV_NFC_CMD_ERASE: + case MV_NFC_CMD_MULTIPLANE_ERASE: + + if(descInfo->cmd == MV_NFC_CMD_ERASE) + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].erase & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + if(descInfo->cmd == MV_NFC_CMD_MULTIPLANE_ERASE) + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].multiplaneErase & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + + cmdb[0] |= ((NFC_ERASE_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[0] |= NFC_CB0_DBC_MASK; + cmdb[0] |= NFC_CB0_CMD_TYPE_ERASE; + cmdb[1] |= (descInfo->pageAddr & NFC_BLOCK_ADDR_BITS); + break; + + case MV_NFC_CMD_RESET: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].reset & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + cmdb[0] |= NFC_CB0_CMD_TYPE_RESET; + break; + + case MV_NFC_CMD_CACHE_READ_SEQ: + cmdb[0] = (flashCmdSet[nfcCtrl->cmdsetIdx].cacheReadSeq & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + break; + + case MV_NFC_CMD_CACHE_READ_RAND: + cmdb[0] = (flashCmdSet[nfcCtrl->cmdsetIdx].cacheReadRand & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) + { + cmdb[1] |= ((descInfo->pageAddr << NFC_SP_PG_OFFS) & NFC_SP_PG_MASK); + if (descInfo->pageAddr & ~NFC_SP_PG_MASK) + cmdb[0] |= ((NFC_SP_BIG_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + else + cmdb[0] |= ((NFC_SP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + } + else + { + cmdb[0] |= ((NFC_LP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[0] |= NFC_CB0_DBC_MASK; + cmdb[1] |= ((descInfo->pageAddr << NFC_LP_PG_OFFS) & NFC_LP_PG_MASK); + cmdb[2] |= (descInfo->pageAddr >> (32 - NFC_LP_PG_OFFS)); + } + cmdb[0] |= NFC_CB0_CMD_TYPE_READ; + break; + + case MV_NFC_CMD_EXIT_CACHE_READ: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].exitCacheRead & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + break; + + case MV_NFC_CMD_CACHE_READ_START: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].read1 & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) + { + cmdb[1] |= ((descInfo->pageAddr << NFC_SP_PG_OFFS) & NFC_SP_PG_MASK); + if (descInfo->pageAddr & ~NFC_SP_PG_MASK) + cmdb[0] |= ((NFC_SP_BIG_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + else + cmdb[0] |= ((NFC_SP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + } + else + { + cmdb[0] |= ((NFC_LP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[0] |= NFC_CB0_DBC_MASK; + cmdb[1] |= ((descInfo->pageAddr << NFC_LP_PG_OFFS) & NFC_LP_PG_MASK); + cmdb[2] |= (descInfo->pageAddr >> (32 - NFC_LP_PG_OFFS)); + } + cmdb[0] |= NFC_CB0_CMD_TYPE_READ; + cmdb[0] |= NFC_CB0_LEN_OVRD_MASK; + break; + + case MV_NFC_CMD_READ_MONOLITHIC: /* Read a single 512B or 2KB page */ + case MV_NFC_CMD_READ_MULTIPLE: + case MV_NFC_CMD_READ_NAKED: + case MV_NFC_CMD_READ_LAST_NAKED: + case MV_NFC_CMD_READ_DISPATCH: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].read1 & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) + { + cmdb[1] |= ((descInfo->pageAddr << NFC_SP_PG_OFFS) & NFC_SP_PG_MASK); + if (descInfo->pageAddr & ~NFC_SP_PG_MASK) + cmdb[0] |= ((NFC_SP_BIG_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + else + cmdb[0] |= ((NFC_SP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + } + else + { + cmdb[0] |= ((NFC_LP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[0] |= NFC_CB0_DBC_MASK; + cmdb[1] |= ((descInfo->pageAddr << NFC_LP_PG_OFFS) & NFC_LP_PG_MASK); + cmdb[2] |= (descInfo->pageAddr >> (32 - NFC_LP_PG_OFFS)); + } + cmdb[0] |= NFC_CB0_CMD_TYPE_READ; + + if (descInfo->length) + { + cmdb[0] |= NFC_CB0_LEN_OVRD_MASK; + cmdb[3] |= (descInfo->length & 0xFFFF); + } + + /* Check for extended command syntax */ + switch (descInfo->cmd) + { + case MV_NFC_CMD_READ_MULTIPLE: + cmdb[0] |= NFC_CB0_CMD_XTYPE_MULTIPLE; + break; + case MV_NFC_CMD_READ_NAKED: + cmdb[0] |= NFC_CB0_CMD_XTYPE_NAKED; + break; + case MV_NFC_CMD_READ_LAST_NAKED: + cmdb[0] |= NFC_CB0_CMD_XTYPE_LAST_NAKED; + break; + case MV_NFC_CMD_READ_DISPATCH: + cmdb[0] |= NFC_CB0_CMD_XTYPE_DISPATCH; + break; + default: + break; + }; + break; + + case MV_NFC_CMD_WRITE_MONOLITHIC: /* Program a single page of 512B or 2KB */ + case MV_NFC_CMD_WRITE_MULTIPLE: + /*case MV_NFC_CMD_WRITE_NAKED:*/ + case MV_NFC_CMD_WRITE_LAST_NAKED: + case MV_NFC_CMD_WRITE_DISPATCH: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].program & (NFC_CB0_CMD1_MASK | NFC_CB0_CMD2_MASK)); + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) + { + if (descInfo->pageAddr & ~NFC_SP_PG_MASK) + cmdb[0] |= ((NFC_SP_BIG_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + else + cmdb[0] |= ((NFC_SP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[1] |= ((descInfo->pageAddr << NFC_SP_PG_OFFS) & NFC_SP_PG_MASK); + } + else + { + cmdb[0] |= ((NFC_LP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[1] |= ((descInfo->pageAddr << NFC_LP_PG_OFFS) & NFC_LP_PG_MASK); + cmdb[2] |= (descInfo->pageAddr >> (32 - NFC_LP_PG_OFFS)); + } + cmdb[0] |= NFC_CB0_DBC_MASK; + cmdb[0] |= NFC_CB0_CMD_TYPE_WRITE; + + /* Check for extended syntax */ + switch (descInfo->cmd) + { + case MV_NFC_CMD_WRITE_MULTIPLE: + cmdb[0] |= NFC_CB0_CMD_XTYPE_MULTIPLE; + break; + case MV_NFC_CMD_WRITE_NAKED: + cmdb[0] |= NFC_CB0_CMD_XTYPE_NAKED; + break; + case MV_NFC_CMD_WRITE_LAST_NAKED: + cmdb[0] |= NFC_CB0_CMD_XTYPE_LAST_NAKED; + break; + case MV_NFC_CMD_WRITE_DISPATCH: + cmdb[0] |= NFC_CB0_CMD_XTYPE_DISPATCH; + break; + default: + break; + }; + break; + + case MV_NFC_CMD_WRITE_DISPATCH_START: + cmdb[0] |= (flashCmdSet[nfcCtrl->cmdsetIdx].program & NFC_CB0_CMD1_MASK); + if (flashDeviceInfo[nfcCtrl->flashIdx].pgSz < MV_NFC_2KB_PAGE) + { + if (descInfo->pageAddr & ~NFC_SP_PG_MASK) + cmdb[0] |= ((NFC_SP_BIG_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + else + cmdb[0] |= ((NFC_SP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[1] |= ((descInfo->pageAddr << NFC_SP_PG_OFFS) & NFC_SP_PG_MASK); + } + else + { + cmdb[0] |= ((NFC_LP_READ_ADDR_LEN << NFC_CB0_ADDR_CYC_OFFS) & NFC_CB0_ADDR_CYC_MASK); + cmdb[1] |= ((descInfo->pageAddr << NFC_LP_PG_OFFS) & NFC_LP_PG_MASK); + cmdb[2] |= (descInfo->pageAddr >> (32 - NFC_LP_PG_OFFS)); + } + cmdb[0] |= NFC_CB0_CMD_TYPE_WRITE; + cmdb[0] |= NFC_CB0_CMD_XTYPE_DISPATCH; + break; + + case MV_NFC_CMD_WRITE_NAKED: + cmdb[0] |= NFC_CB0_CMD_TYPE_WRITE; + cmdb[0] |= NFC_CB0_CMD_XTYPE_NAKED; + if (descInfo->length) + { + cmdb[0] |= NFC_CB0_LEN_OVRD_MASK; + cmdb[3] |= (descInfo->length & 0xFFFF); + } + break; + + case MV_NFC_CMD_WRITE_DISPATCH_END: + cmdb[0] |= ((flashCmdSet[nfcCtrl->cmdsetIdx].program >> 8) & NFC_CB0_CMD1_MASK); + cmdb[0] |= NFC_CB0_CMD_TYPE_WRITE; + cmdb[0] |= NFC_CB0_CMD_XTYPE_DISPATCH; + break; + + default: + return MV_BAD_PARAM; + } + + /* update page count */ + cmdb[2] |= (((descInfo->pageCount - 1) << NFC_PG_CNT_OFFS) & NFC_PG_CNT_MASK); + + return MV_OK; +} + +#ifdef MV_INCLUDE_PDMA +/******************************************************************************* +* mvNfcCommandMultiple +* +* DESCRIPTION: +* Issue a command to the NAND controller. +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - The command to issue. +* pageAddr - The page number to perform the command on (If the command +* requires a flash offset), block address in erase. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_TIMEOUT - Timeout while waiting for command request. +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcCommandMultiple(MV_NFC_CTRL *nfcCtrl, MV_NFC_MULTI_CMD *descInfo, MV_U32 descCnt) +{ + MV_U32 reg, i, buff; + MV_U32 errCode = MV_OK; + MV_U32 cmdb[4]; + MV_NFC_CMD * cmdVirtPtr = (MV_NFC_CMD*)nfcCtrl->cmdBuff.bufVirtPtr; + MV_NFC_CMD * cmdPhysPtr = (MV_NFC_CMD*)nfcCtrl->cmdBuff.bufPhysAddr; + + MV_PDMA_DESC * cmdDescVirtPtr = (MV_PDMA_DESC*)nfcCtrl->cmdDescBuff.bufVirtPtr; + MV_PDMA_DESC * cmdDescPhysPtr = (MV_PDMA_DESC*)nfcCtrl->cmdDescBuff.bufPhysAddr; + MV_PDMA_DESC * dataDescVirtPtr = (MV_PDMA_DESC*)nfcCtrl->dataDescBuff.bufVirtPtr; + MV_PDMA_DESC * dataDescPhysPtr = (MV_PDMA_DESC*)nfcCtrl->dataDescBuff.bufPhysAddr; + MV_U32 xferLen; + MV_U32 dataDescCount = 0; + MV_U32 nPage; + MV_U32 timeout = 10000; + MV_STATUS ret; + + /* Check MAX descriptor count */ + if (descCnt > MV_NFC_MAX_DESC_CHAIN) + return MV_BAD_PARAM; + + /* If not in PDMA fail operation */ + if (nfcCtrl->ioMode != MV_NFC_PDMA_ACCESS) + return MV_BAD_PARAM; + + /* Check that a chip was selected */ + if (nfcCtrl->currCs == MV_NFC_CS_NONE) + return MV_FAIL; + + /* Start the whole command chain through setting the ND_RUN */ + /* Setting ND_RUN bit to start the new transaction - verify that controller in idle state */ + while(timeout > 0) { + reg = MV_REG_READ(NFC_CONTROL_REG); + if (!(reg & NFC_CTRL_ND_RUN_MASK)) + break; + timeout--; + } + if(timeout == 0) + return MV_BAD_STATE; + + for (i=0; ieccMode != MV_NFC_ECC_DISABLE) + { + if ( (descInfo[i].cmd == MV_NFC_CMD_READ_ID) || (descInfo[i].cmd == MV_NFC_CMD_READ_STATUS) || + (descInfo[i].cmd == MV_NFC_CMD_ERASE) || (descInfo[i].cmd == MV_NFC_CMD_RESET)) + { + /* disable ECC for these commands */ + MV_REG_BIT_RESET(NFC_CONTROL_REG, NFC_CTRL_ECC_EN_MASK); + if (nfcCtrl->eccMode != MV_NFC_ECC_HAMMING) + MV_REG_BIT_RESET(NFC_ECC_CONTROL_REG, NFC_ECC_BCH_EN_MASK); + } + else + { + /* enable ECC for all other commands */ + MV_REG_BIT_SET(NFC_CONTROL_REG, NFC_CTRL_ECC_EN_MASK); + if (nfcCtrl->eccMode != MV_NFC_ECC_HAMMING) + MV_REG_BIT_SET(NFC_ECC_CONTROL_REG, NFC_ECC_BCH_EN_MASK); + } + } + + /* Build the command buffer */ + if ((ret = mvNfcBuildCommand(nfcCtrl, &descInfo[i], cmdb)) != MV_OK) + return ret; + + + /* Fill Command data */ + cmdVirtPtr[i].cmdb0 = cmdb[0]; + cmdVirtPtr[i].cmdb1 = cmdb[1]; + cmdVirtPtr[i].cmdb2 = cmdb[2]; + cmdVirtPtr[i].cmdb3 = cmdb[3]; + + + /* Hook to the previous descriptor if exists */ + if (i != 0) + { + cmdDescVirtPtr[i-1].physDescPtr = (MV_U32)&cmdDescPhysPtr[i]; + cmdVirtPtr[i-1].cmdb0 |= NFC_CB0_NEXT_CMD_MASK; + } + + /* Fill Command Descriptor */ + cmdDescVirtPtr[i].physDescPtr = 0x1; + cmdDescVirtPtr[i].physSrcAddr = (MV_U32)&cmdPhysPtr[i]; + cmdDescVirtPtr[i].physDestAddr = nfcCtrl->regsPhysAddr + NFC_CMD_BUFF_ADDR; + cmdDescVirtPtr[i].commandValue = mvPdmaCommandRegCalc(&nfcCtrl->cmdChanHndl, MV_PDMA_MEM_TO_PERIPH, + NFC_CMD_BUFF_SIZE(cmdb[0])); + + /* Check if data dma need to be operated for this command */ + if ((descInfo[i].cmd != MV_NFC_CMD_ERASE) && + (descInfo[i].cmd != MV_NFC_CMD_MULTIPLANE_ERASE) && + (descInfo[i].cmd != MV_NFC_CMD_RESET) && + (descInfo[i].cmd != MV_NFC_CMD_EXIT_CACHE_READ) && + (descInfo[i].cmd != MV_NFC_CMD_CACHE_READ_START) && + (descInfo[i].cmd != MV_NFC_CMD_READ_DISPATCH) && + (descInfo[i].cmd != MV_NFC_CMD_WRITE_DISPATCH_START) && + (descInfo[i].cmd != MV_NFC_CMD_WRITE_DISPATCH_END)) + { + for(nPage = 0; nPage < descInfo[i].pageCount; nPage++) + { + if (dataDescCount != 0) + dataDescVirtPtr[dataDescCount-1].physDescPtr = (MV_U32)&dataDescPhysPtr[dataDescCount]; + /* Fill Data Descriptor */ + if ((descInfo[i].cmd == MV_NFC_CMD_READ_MONOLITHIC) || + (descInfo[i].cmd == MV_NFC_CMD_READ_MULTIPLE) || + (descInfo[i].cmd == MV_NFC_CMD_CACHE_READ_SEQ) || + (descInfo[i].cmd == MV_NFC_CMD_EXIT_CACHE_READ) || + (descInfo[i].cmd == MV_NFC_CMD_CACHE_READ_RAND) || + (descInfo[i].cmd == MV_NFC_CMD_READ_NAKED) || + (descInfo[i].cmd == MV_NFC_CMD_READ_LAST_NAKED) || + (descInfo[i].cmd == MV_NFC_CMD_READ_DISPATCH) || + (descInfo[i].cmd == MV_NFC_CMD_READ_ID) || + (descInfo[i].cmd == MV_NFC_CMD_READ_STATUS)) + { + if(descInfo[i].numSgBuffs == 1) { + /* A single buffer, use physAddr */ + dataDescVirtPtr[dataDescCount].physSrcAddr = nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR; + dataDescVirtPtr[dataDescCount].physDestAddr = descInfo[i].physAddr + nPage*xferLen; + dataDescVirtPtr[dataDescCount].commandValue = mvPdmaCommandRegCalc(&nfcCtrl->dataChanHndl, MV_PDMA_PERIPH_TO_MEM, (descInfo[i].length ? descInfo[i].length : xferLen)); + } else { + /* Scatter-gather operation, use sgBuffAdd */ + for(buff = 0; buff < descInfo[i].numSgBuffs; buff++) { + if (buff != 0) + dataDescVirtPtr[dataDescCount-1].physDescPtr = (MV_U32)&dataDescPhysPtr[dataDescCount]; + dataDescVirtPtr[dataDescCount].physSrcAddr = nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR; + dataDescVirtPtr[dataDescCount].physDestAddr = descInfo[i].sgBuffAddr[buff]; + dataDescVirtPtr[dataDescCount].commandValue = mvPdmaCommandRegCalc(&nfcCtrl->dataChanHndl, MV_PDMA_PERIPH_TO_MEM, descInfo[i].sgBuffSize[buff]); + dataDescCount++; + } + dataDescCount--; + } + } + else /* Write */ + { + if(descInfo[i].numSgBuffs == 1) { + /* A single buffer, use physAddr */ + dataDescVirtPtr[dataDescCount].physSrcAddr = descInfo[i].physAddr + nPage*xferLen; + dataDescVirtPtr[dataDescCount].physDestAddr = nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR; + dataDescVirtPtr[dataDescCount].commandValue = mvPdmaCommandRegCalc(&nfcCtrl->dataChanHndl, MV_PDMA_MEM_TO_PERIPH, (descInfo[i].length ? descInfo[i].length : xferLen)); + } else { + /* Scatter-gather operation, use sgBuffAdd */ + for(buff = 0; buff < descInfo[i].numSgBuffs; buff++) { + if (buff != 0) + dataDescVirtPtr[dataDescCount-1].physDescPtr = (MV_U32)&dataDescPhysPtr[dataDescCount]; + dataDescVirtPtr[dataDescCount].physSrcAddr = descInfo[i].sgBuffAddr[buff]; + dataDescVirtPtr[dataDescCount].physDestAddr = nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR; + dataDescVirtPtr[dataDescCount].commandValue = mvPdmaCommandRegCalc(&nfcCtrl->dataChanHndl, MV_PDMA_MEM_TO_PERIPH, descInfo[i].sgBuffSize[buff]); + dataDescCount++; + } + dataDescCount--; + } + } + + dataDescVirtPtr[dataDescCount].physDescPtr = 0x1; + dataDescCount++; + + if(dataDescCount > MV_NFC_MAX_DESC_CHAIN) + { + return MV_OUT_OF_RANGE; + } + } + } + } + +#if 0 + DBGPRINT ((DBGLVL "\ncmdDescPhysPtr = %08x, Count = %d\n", (MV_U32)cmdDescPhysPtr, descCnt)); + for(nPage = 0; nPage < descCnt; nPage++) + { + DBGPRINT ((DBGLVL " Command[%d] physDescPtr = %08x\n", nPage, cmdDescVirtPtr[nPage].physDescPtr)); + DBGPRINT ((DBGLVL " Command[%d] physSrcAddr = %08x\n", nPage, cmdDescVirtPtr[nPage].physSrcAddr)); + DBGPRINT ((DBGLVL " Command[%d] physDestAddr = %08x\n", nPage, cmdDescVirtPtr[nPage].physDestAddr)); + DBGPRINT ((DBGLVL " Command[%d] commandValue = %08x\n", nPage, cmdDescVirtPtr[nPage].commandValue)); + DBGPRINT ((DBGLVL " NDCB0 = %08x, NDCB1 = %08x, NDCB2 = %08x, NDCB3 = %08x\n", + cmdVirtPtr[nPage].cmdb0, cmdVirtPtr[nPage].cmdb1, cmdVirtPtr[nPage].cmdb2, cmdVirtPtr[nPage].cmdb3)); + } + + DBGPRINT ((DBGLVL "dataDescPhysPtr = %08x, Count = %d\n", (MV_U32)dataDescPhysPtr, dataDescCount)); + for(nPage = 0; nPage < dataDescCount; nPage++) + { + DBGPRINT ((DBGLVL " Data[%d] physDescPtr = %08x\n", nPage, dataDescVirtPtr[nPage].physDescPtr)); + DBGPRINT ((DBGLVL " Data[%d] physSrcAddr = %08x\n", nPage, dataDescVirtPtr[nPage].physSrcAddr)); + DBGPRINT ((DBGLVL " Data[%d] physDestAddr = %08x\n", nPage, dataDescVirtPtr[nPage].physDestAddr)); + DBGPRINT ((DBGLVL " Data[%d] commandValue = %08x\n", nPage, dataDescVirtPtr[nPage].commandValue)); + } +#endif + if (dataDescCount) + { + /* enable interrupts in the last data descriptor. */ + mvPdmaCommandIntrEnable(&nfcCtrl->dataChanHndl, + &(dataDescVirtPtr[dataDescCount - 1].commandValue)); + /* operate the data DMA */ + if (mvPdmaChanTransfer(&nfcCtrl->dataChanHndl, MV_PDMA_PERIPH_TO_MEM, + 0,0,0, (MV_U32)dataDescPhysPtr) != MV_OK) + return MV_HW_ERROR; + } + + /* operate the command DMA */ + if (mvPdmaChanTransfer(&nfcCtrl->cmdChanHndl, MV_PDMA_MEM_TO_PERIPH, + 0, 0, 0, (MV_U32)cmdDescPhysPtr) != MV_OK) + return MV_HW_ERROR; + + /* Clear all old events on the status register */ + reg = MV_REG_READ(NFC_STATUS_REG); + MV_REG_WRITE(NFC_STATUS_REG, reg); + + /* Start the whole command chain through setting the ND_RUN */ + /* Setting ND_RUN bit to start the new transaction - verify that controller in idle state */ + while(timeout > 0) { + reg = MV_REG_READ(NFC_CONTROL_REG); + if (!(reg & NFC_CTRL_ND_RUN_MASK)) + break; + timeout--; + } + if(timeout == 0) + return MV_BAD_STATE; + + reg |= NFC_CTRL_ND_RUN_MASK; + MV_REG_WRITE(NFC_CONTROL_REG, reg); + + return MV_OK; +} +#endif + +/******************************************************************************* +* mvNfcCommandPio +* +* DESCRIPTION: +* Issue a command to the NAND controller. +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd_descr - The command to issue, page address, page number, data length +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_TIMEOUT - Timeout while waiting for command request. +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcCommandPio(MV_NFC_CTRL *nfcCtrl, MV_NFC_MULTI_CMD * cmd_desc, MV_BOOL next) +{ + MV_U32 reg; + MV_U32 errCode = MV_OK; + MV_U32 cmdb_pio[4]; + MV_U32* cmdb; + MV_U32 timeout = 10000; + MV_STATUS ret; + + /* Check that a chip was selected */ + if (nfcCtrl->currCs == MV_NFC_CS_NONE) + return MV_FAIL; + + /* Clear all old events on the status register */ + reg = MV_REG_READ(NFC_STATUS_REG); + MV_REG_WRITE(NFC_STATUS_REG, reg); + + /* Setting ND_RUN bit to start the new transaction - verify that controller in idle state */ + while(timeout > 0) { + reg = MV_REG_READ(NFC_CONTROL_REG); + if (!(reg & NFC_CTRL_ND_RUN_MASK)) + break; + timeout--; + } + + if(timeout == 0) + return MV_BAD_STATE; + + reg |= NFC_CTRL_ND_RUN_MASK; + MV_REG_WRITE(NFC_CONTROL_REG, reg); + + /* Wait for Command WRITE request */ + if ((errCode = mvDfcWait4Complete(NFC_SR_WRCMDREQ_MASK, 1)) != MV_OK) + return errCode; + /* Build 12 byte Command */ + if (nfcCtrl->ioMode == MV_NFC_PDMA_ACCESS) + cmdb = (MV_U32*)nfcCtrl->cmdBuff.bufVirtPtr; + else /* PIO mode */ + cmdb = cmdb_pio; + + if (nfcCtrl->eccMode != MV_NFC_ECC_DISABLE) + { + switch (cmd_desc->cmd) { + case MV_NFC_CMD_READ_MONOLITHIC: + case MV_NFC_CMD_READ_MULTIPLE: + case MV_NFC_CMD_READ_NAKED: + case MV_NFC_CMD_READ_LAST_NAKED: + case MV_NFC_CMD_WRITE_MONOLITHIC: + case MV_NFC_CMD_WRITE_MULTIPLE: + case MV_NFC_CMD_WRITE_NAKED: + case MV_NFC_CMD_WRITE_LAST_NAKED: + if (nfcCtrl->eccMode != MV_NFC_ECC_DISABLE) { + MV_REG_BIT_SET(NFC_CONTROL_REG, NFC_CTRL_ECC_EN_MASK); + if (nfcCtrl->eccMode != MV_NFC_ECC_HAMMING) + MV_REG_BIT_SET(NFC_ECC_CONTROL_REG, NFC_ECC_BCH_EN_MASK); + } + break; + + default: + /* disable ECC for non-data commands */ + MV_REG_BIT_RESET(NFC_CONTROL_REG, NFC_CTRL_ECC_EN_MASK); + MV_REG_BIT_RESET(NFC_ECC_CONTROL_REG, NFC_ECC_BCH_EN_MASK); + break; + }; + } + + /* Build the command buffer */ + if ((ret = mvNfcBuildCommand(nfcCtrl, cmd_desc, cmdb)) != MV_OK) + return ret; + + /* If next command, link to it */ + if (next) + cmdb[0] |= NFC_CB0_NEXT_CMD_MASK; + + /* issue command */ + MV_REG_WRITE(NFC_COMMAND_BUFF_0_REG, cmdb[0]); + MV_REG_WRITE(NFC_COMMAND_BUFF_0_REG, cmdb[1]); + MV_REG_WRITE(NFC_COMMAND_BUFF_0_REG, cmdb[2]); + MV_REG_WRITE(NFC_COMMAND_BUFF_0_REG, cmdb[3]); + + return MV_OK; +} + + +/******************************************************************************* +* mvNfcStatusGet +* +* DESCRIPTION: +* Retrieve the NAND controller status to monitor the NAND access sequence. +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - The last issued command to get the status for. +* +* OUTPUT: +* value - Relevant only if one of the MV_NFC_STATUS_BBD OR +* MV_NFC_STATUS_COR_ERROR errors is turned on. +* For MV_NFC_STATUS_COR_ERROR: Holds the errors count. +* For MV_NFC_STATUS_BBD: Holds the bad block address. +* If error value is not desired, pass NULL as input. +* +* RETURN: +* A bitmask of the MV_NFC_STATUS_XXX status bits. +*******************************************************************************/ +MV_U32 mvNfcStatusGet(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *value) +{ + MV_U32 reg, ret; + + if ((reg = MV_REG_READ(NFC_STATUS_REG)) == 0) + return 0; + + if (value) + *value = ((reg & NFC_SR_ERR_CNT_MASK) >> NFC_SR_ERR_CNT_OFFS); + + if ((nfcCtrl->currCs == MV_NFC_CS_0) || (nfcCtrl->currCs == MV_NFC_CS_2)) + { + /* Clear out all non related interrupts */ + reg &= (NFC_SR_CS0_BBD_MASK | NFC_SR_CS0_CMDD_MASK | NFC_SR_CS0_PAGED_MASK | + NFC_SR_RDY0_MASK | NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | + NFC_SR_WRDREQ_MASK | NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK); + + ret = (reg & (NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | + NFC_SR_WRDREQ_MASK | NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK)); + + if (reg & NFC_SR_CS0_BBD_MASK) + ret |= MV_NFC_STATUS_BBD; + if (reg & NFC_SR_CS0_CMDD_MASK) + ret |= MV_NFC_STATUS_CMDD; + if (reg & NFC_SR_CS0_PAGED_MASK) + ret |= MV_NFC_STATUS_PAGED; + if (reg & NFC_SR_RDY0_MASK) + ret |= MV_NFC_STATUS_RDY; + } + else if ((nfcCtrl->currCs == MV_NFC_CS_1) || (nfcCtrl->currCs == MV_NFC_CS_3)) + { + reg &= (NFC_SR_CS1_BBD_MASK | NFC_SR_CS1_CMDD_MASK | NFC_SR_CS1_PAGED_MASK | + NFC_SR_RDY1_MASK | NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | + NFC_SR_WRDREQ_MASK | NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK); + + ret = (reg & (NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | + NFC_SR_WRDREQ_MASK | NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK)); + + if (reg & NFC_SR_CS1_BBD_MASK) + ret |= MV_NFC_STATUS_BBD; + if (reg & NFC_SR_CS1_CMDD_MASK) + ret |= MV_NFC_STATUS_CMDD; + if (reg & NFC_SR_CS1_PAGED_MASK) + ret |= MV_NFC_STATUS_PAGED; + if (reg & NFC_SR_RDY1_MASK) + ret |= MV_NFC_STATUS_RDY; + } + else + { + reg &= (NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | + NFC_SR_WRDREQ_MASK | NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK); + + ret = reg; + } + + /* Clear out all reported events */ + MV_REG_WRITE(NFC_STATUS_REG, reg); + + return ret; +} + + +/******************************************************************************* +* mvNfcIntrSet +* +* DESCRIPTION: +* Enable / Disable a given set of the Nand controller interrupts. +* +* INPUT: +* inatMask - A bitmask of the interrupts to enable / disable. +* enable - MV_TRUE: Unmask the interrupts +* MV_FALSE: Mask the interrupts. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcIntrSet(MV_NFC_CTRL *nfcCtrl, MV_U32 intMask, MV_BOOL enable) +{ + MV_U32 reg; + MV_U32 msk = (intMask & (NFC_SR_WRCMDREQ_MASK | NFC_SR_RDDREQ_MASK | NFC_SR_WRDREQ_MASK | + NFC_SR_CORERR_MASK | NFC_SR_UNCERR_MASK)); + + if ((nfcCtrl->currCs == MV_NFC_CS_0) || (nfcCtrl->currCs == MV_NFC_CS_2)) + { + if (intMask & MV_NFC_STATUS_BBD) + msk |= NFC_SR_CS0_BBD_MASK; + if (intMask & MV_NFC_STATUS_CMDD) + msk |= NFC_SR_CS0_CMDD_MASK; + if (intMask & MV_NFC_STATUS_PAGED) + msk |= NFC_SR_CS0_PAGED_MASK; + if (intMask & MV_NFC_STATUS_RDY) + msk |= NFC_SR_RDY0_MASK; + } + else if ((nfcCtrl->currCs == MV_NFC_CS_1) || (nfcCtrl->currCs == MV_NFC_CS_3)) + { + if (intMask & MV_NFC_STATUS_BBD) + msk |= NFC_SR_CS1_BBD_MASK; + if (intMask & MV_NFC_STATUS_CMDD) + msk |= NFC_SR_CS1_CMDD_MASK; + if (intMask & MV_NFC_STATUS_PAGED) + msk |= NFC_SR_CS1_PAGED_MASK; + if (intMask & MV_NFC_STATUS_RDY) + msk |= NFC_SR_RDY0_MASK; + } + + reg = MV_REG_READ(NFC_CONTROL_REG); + if (enable) + reg &= ~msk; + else + reg |= msk; + + MV_REG_WRITE(NFC_CONTROL_REG, reg); + + return MV_OK; +} + + +/******************************************************************************* +* mvNfcReadWrite +* +* DESCRIPTION: +* Perform a read / write operation of a previously issued command. +* When working in PIO mode, this function will perform the read / write +* operation from / to the supplied buffer. +* when working in PDMA mode, this function will trigger the PDMA to start +* the data transfer. +* In all cases, the user is responsible to make sure that the data +* transfer operation was done successfully by polling the command done bit. +* Before calling this function, the Data-Read/Write request interrupts +* should be disabled (the one relevant to the command being processed). +* +* INPUT: +* nfcCtrl - Nand control structure. +* cmd - The previously issued command. +* virtBufAddr - [Relevant only when working in PIO mode] +* The virtual address of the buffer to read to / write from. +* physBufAddr - [Relevant only when working in PDMA mode] +* The physical address of the buffer to read to / write from. +* The buffer should be cache coherent for PDMA access. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_FAIL - On failure +*******************************************************************************/ +MV_STATUS mvNfcReadWrite(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *virtBufAddr, MV_U32 physBuffAddr) +{ + MV_U32 data_len = 0; + MV_U32 i; + MV_STATUS errCode; + + if ((errCode = mvNfcTransferDataLength(nfcCtrl, cmd, &data_len)) != MV_OK) + return errCode; + + switch (cmd) + { + case MV_NFC_CMD_READ_ID: + case MV_NFC_CMD_READ_STATUS: + case MV_NFC_CMD_READ_MONOLITHIC: /* Read a single 512B or 2KB page */ + case MV_NFC_CMD_READ_MULTIPLE: + case MV_NFC_CMD_READ_NAKED: + case MV_NFC_CMD_READ_LAST_NAKED: + case MV_NFC_CMD_READ_DISPATCH: + /* Issue command based on IO mode */ + if (nfcCtrl->ioMode == MV_NFC_PDMA_ACCESS) + { +#ifdef MV_INCLUDE_PDMA + /* operate the DMA */ + if (mvPdmaChanTransfer(&nfcCtrl->dataChanHndl, MV_PDMA_PERIPH_TO_MEM, + nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR, + physBuffAddr, data_len, 0) != MV_OK) + return MV_HW_ERROR; +#else + return MV_NOT_SUPPORTED; +#endif + } + else /* PIO mode */ + { + for (i=0; iioMode == MV_NFC_PDMA_ACCESS) + { +#ifdef MV_INCLUDE_PDMA + /* operate the DMA */ + if (mvPdmaChanTransfer(&nfcCtrl->dataChanHndl, MV_PDMA_MEM_TO_PERIPH, + physBuffAddr, nfcCtrl->regsPhysAddr + NFC_DATA_BUFF_ADDR, + data_len, 0) != MV_OK) + return MV_HW_ERROR; +#else + return MV_NOT_SUPPORTED; +#endif + } + else /* PIO mode */ + { + for (i=0; iflashIdx].pgSz < MV_NFC_2KB_PAGE) /* Small Page */ + { + *colOffset = (address & 0xFF); + *row = (address >> 9); + } + else /* Large Page */ + { + *colOffset = (address & (flashDeviceInfo[nfcCtrl->flashIdx].pgSz - 1)); + + /* Calculate the page bits */ + *row = (address >> mvNfcColBits(flashDeviceInfo[nfcCtrl->flashIdx].pgSz)); + } +} + +/******************************************************************************* +* mvNfcAddress2BlockConvert +* +* DESCRIPTION: +* Convert an absolute flash address to erasable block address +* +* INPUT: +* nfcCtrl - Nand control structure. +* address - The absolute flash address. +* +* OUTPUT: +* blk - block address +* +* RETURN: +* None +*******************************************************************************/ +MV_VOID mvNfcAddress2BlockConvert(MV_NFC_CTRL *nfcCtrl, MV_U32 address, MV_U32 *blk) +{ + *blk = (address / (flashDeviceInfo[nfcCtrl->flashIdx].pgSz * flashDeviceInfo[nfcCtrl->flashIdx].pgPrBlk)); +} + +/******************************************************************************* +* mvNfcAddress2BlockConvert +* +* DESCRIPTION: +* Convert an absolute flash address to erasable block address +* +* INPUT: +* nfcCtrl - Nand control structure. +* address - The absolute flash address. +* +* OUTPUT: +* blk - block address +* +* RETURN: +* None +*******************************************************************************/ +MV_8 * mvNfcFlashModelGet(MV_NFC_CTRL *nfcCtrl) +{ + static MV_8 * unk_dev = "Unknown Flash Device"; + + if (nfcCtrl->flashIdx >= (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return unk_dev; + + return flashDeviceInfo[nfcCtrl->flashIdx].model; +} + +/******************************************************************************* +* mvNfcFlashPageSizeGet +* +* DESCRIPTION: +* Retrieve the logical page size of a given flash. +* +* INPUT: +* nfcCtrl - Nand control structure. +* +* OUTPUT: +* size - Flash page size in bytes. +* totalSize - Page size including spare area. +* (Pass NULL if not needed). +* +* RETURN: +* MV_NOT_FOUND - Bad flash index. +*******************************************************************************/ +MV_STATUS mvNfcFlashPageSizeGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *size, MV_U32 *totalSize) +{ + if (nfcCtrl->flashIdx >= (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return MV_NOT_FOUND; + if(size == NULL) + return MV_BAD_PTR; + + if(nfcCtrl->ifMode == MV_NFC_IF_2X8) + *size = flashDeviceInfo[nfcCtrl->flashIdx].pgSz << 1; + else + *size = flashDeviceInfo[nfcCtrl->flashIdx].pgSz; + + if(totalSize) { + mvNfcTransferDataLength(nfcCtrl, MV_NFC_CMD_READ_MONOLITHIC, totalSize); + if(nfcCtrl->ifMode == MV_NFC_IF_2X8) + *totalSize = (*totalSize) << 1; + if(flashDeviceInfo[nfcCtrl->flashIdx].pgSz > MV_NFC_2KB_PAGE) + *totalSize = (*totalSize) << 1; + } + return MV_OK; +} + +/******************************************************************************* +* mvNfcFlashBlockSizeGet +* +* DESCRIPTION: +* Retrieve the logical block size of a given flash. +* +* INPUT: +* nfcCtrl - Nand control structure. +* +* OUTPUT: +* size - Flash size in bytes. +* +* RETURN: +* MV_NOT_FOUND - Bad flash index. +*******************************************************************************/ +MV_STATUS mvNfcFlashBlockSizeGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *size) +{ + if (nfcCtrl->flashIdx >= (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return MV_NOT_FOUND; + if(size == NULL) + return MV_BAD_PTR; + + if(nfcCtrl->ifMode == MV_NFC_IF_2X8) + *size = ((flashDeviceInfo[nfcCtrl->flashIdx].pgSz << 1) * flashDeviceInfo[nfcCtrl->flashIdx].pgPrBlk); + else + *size = (flashDeviceInfo[nfcCtrl->flashIdx].pgSz * flashDeviceInfo[nfcCtrl->flashIdx].pgPrBlk); + + return MV_OK; +} + +/******************************************************************************* +* mvNfcFlashBlockNumGet +* +* DESCRIPTION: +* Retrieve the number of logical blocks of a given flash. +* +* INPUT: +* nfcCtrl - Nand control structure. +* +* OUTPUT: +* numBlocks - Flash number of blocks. +* +* RETURN: +* MV_NOT_FOUND - Bad flash index. +*******************************************************************************/ +MV_STATUS mvNfcFlashBlockNumGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *numBlocks) +{ + if (nfcCtrl->flashIdx >= (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return MV_NOT_FOUND; + if(numBlocks == NULL) + return MV_BAD_PTR; + + *numBlocks = flashDeviceInfo[nfcCtrl->flashIdx].blkNum; + + return MV_OK; +} + + +/******************************************************************************* +* mvNfcFlashIdGet +* +* DESCRIPTION: +* Retrieve the flash device ID. +* +* INPUT: +* nfcCtrl - Nand control structure. +* +* OUTPUT: +* flashId - Flash ID. +* +* RETURN: +* MV_NOT_FOUND - Bad flash index. +*******************************************************************************/ +MV_STATUS mvNfcFlashIdGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *flashId) +{ + if (nfcCtrl->flashIdx >= (sizeof(flashDeviceInfo)/sizeof(MV_NFC_FLASH_INFO))) + return MV_NOT_FOUND; + + if(flashId == NULL) + return MV_BAD_PTR; + + *flashId = flashDeviceInfo[nfcCtrl->flashIdx].id; + + return MV_OK; +} + +/******************************************************************************* +* mvNfcUnitStateStore - Store the NFC Unit state. +* +* DESCRIPTION: +* This function stores the NFC unit registers before the unit is suspended. +* The stored registers are placed into the input buffer which will be used for +* the restore operation. +* +* INPUT: +* regsData - Buffer to store the unit state registers (Must +* include at least 64 entries) +* len - Number of entries in regsData input buffer. +* +* OUTPUT: +* regsData - Unit state registers. The registers are stored in +* pairs of (reg, value). +* len - Number of entries in regsData buffer (Must be even). +* +* RETURS: +* MV_ERROR on failure. +* MV_OK on success. +* +*******************************************************************************/ +MV_STATUS mvNfcUnitStateStore(MV_U32 *stateData, MV_U32 *len) +{ + MV_U32 i; + + if((stateData == NULL) || (len == NULL)) + return MV_BAD_PARAM; + + i = 0; + + stateData[i++] = NFC_CONTROL_REG; + stateData[i++] = MV_REG_READ(NFC_CONTROL_REG); + + stateData[i++] = NFC_TIMING_0_REG; + stateData[i++] = MV_REG_READ(NFC_TIMING_0_REG); + + stateData[i++] = NFC_TIMING_1_REG; + stateData[i++] = MV_REG_READ(NFC_TIMING_1_REG); + + stateData[i++] = NFC_ECC_CONTROL_REG; + stateData[i++] = MV_REG_READ(NFC_ECC_CONTROL_REG); + *len = i; + + return MV_OK; +} + + +/******************************************************************************* +* mvDfcWait4Complete +* +* DESCRIPTION: +* Wait for event or process to complete +* +* INPUT: +* statMask: bit to wait from in status register NDSR +* usec: Max uSec to wait for event +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - On success, +* MV_TIMEOUT - Error accessing the underlying flahs device. +*******************************************************************************/ +static MV_STATUS mvDfcWait4Complete(MV_U32 statMask, MV_U32 usec) +{ + MV_U32 i, sts; + + for (i=0; itADL, clk2ns) << NFC_TMNG0_TADL_OFFS) & NFC_TMNG0_TADL_MASK); + reg |= ((ns_clk(flInfo->tCH, clk2ns) << NFC_TMNG0_TCH_OFFS) & NFC_TMNG0_TCH_MASK); + reg |= ((ns_clk(flInfo->tCS, clk2ns) << NFC_TMNG0_TCS_OFFS) & NFC_TMNG0_TCS_MASK); + reg |= ((ns_clk(flInfo->tWH, clk2ns) << NFC_TMNG0_TWH_OFFS) & NFC_TMNG0_TWH_MASK); + reg |= ((ns_clk(flInfo->tWP, clk2ns) << NFC_TMNG0_TWP_OFFS) & NFC_TMNG0_TWP_MASK); + reg |= ((ns_clk(flInfo->tRH, clk2ns) << NFC_TMNG0_TRH_OFFS) & NFC_TMNG0_TRH_MASK); + reg |= ((ns_clk(flInfo->tRP, clk2ns) << NFC_TMNG0_TRP_OFFS) & NFC_TMNG0_TRP_MASK); + MV_REG_WRITE(NFC_TIMING_0_REG, reg); + + /* Configure the Timing-1 register */ + reg = 0; + reg |= ((ns_clk(flInfo->tR, clk2ns) << NFC_TMNG1_TR_OFFS) & NFC_TMNG1_TR_MASK); + reg |= ((ns_clk(flInfo->tWHR, clk2ns) << NFC_TMNG1_TWHR_OFFS) & NFC_TMNG1_TWHR_MASK); + reg |= ((ns_clk(flInfo->tAR, clk2ns) << NFC_TMNG1_TAR_OFFS) & NFC_TMNG1_TAR_MASK); + reg |= (((flInfo->tRHW / 16) << NFC_TMNG1_TRHW_OFFS) & NFC_TMNG1_TRHW_MASK); + reg |= NFC_TMNG1_WAIT_MODE_MASK; + MV_REG_WRITE(NFC_TIMING_1_REG, reg); + + return MV_OK; +} + +/******************************************************************************* +* mvNfcColBits +* +* DESCRIPTION: +* Calculate number of bits representing column part of the address +* +* INPUT: + pg_size: page size +* +* OUTPUT: +* None. +* +* RETURN: +* Number of bits representing a column +*******************************************************************************/ +static MV_U32 mvNfcColBits(MV_U32 pg_size) +{ + MV_U32 shift = 0; + while(pg_size) + { + ++shift; + pg_size >>=1; + }; + + return (shift-1); +} + +/******************************************************************************* +* mvNfcEccModeSet +* +* DESCRIPTION: +* Set the ECC mode at runtime to BCH, Hamming or No Ecc. +* +* INPUT: +* nfcCtrl - Nand control structure. +* MV_NFC_ECC_MODE eccMode: ECC type (BCH, Hamming or No Ecc) +* +* OUTPUT: +* None. +* +* RETURN: +* previous ECC mode. +*******************************************************************************/ +MV_NFC_ECC_MODE mvNfcEccModeSet(MV_NFC_CTRL *nfcCtrl, MV_NFC_ECC_MODE eccMode) +{ + MV_NFC_ECC_MODE prevEccMode; + + prevEccMode = nfcCtrl->eccMode; + nfcCtrl->eccMode = eccMode; + return prevEccMode; +} + +/******************************************************************************* +* mvNfcBadBlockPageNumber +* +* DESCRIPTION: +* Get the page number within the block holding the bad block indication +* +* INPUT: +* nfcCtrl - Nand control structure. +* +* OUTPUT: +* None +* +* RETURN: +* page number having the bad block indicator +*******************************************************************************/ +MV_U32 mvNfcBadBlockPageNumber(MV_NFC_CTRL *nfcCtrl) +{ + return flashDeviceInfo[nfcCtrl->flashIdx].bb_page; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfc.h u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfc.h --- u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfc.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfc.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,425 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVNFCH +#define __INCMVNFCH + +/****************************************************************************** + * Usage model: + * The following describes the usage model for the below APIs. + * the sequences below does not handle errors, and assume all stages pass + * successfully. + * Nand Read of 2 pages, PDMA mode: + * - mvNfcInit(MV_NFC_PDMA_ACCESS) + * - mvNfcSelectChip(...) + * - [If interrupt mode] + * Enable RD_DATA_REQ & CMD_DONE interrupts. + * - mvNfcCommandIssue(MV_NFC_CMD_READ) + * - [In interrupt mode] + * Block till one of the above interrupts is triggered. + * - [In polling mode] + * Poll on mvNfcStatusGet() till STATUS_RDD_REQ is returned. + * - [In interrupt mode] + * Disable the RD_DATA_REQ interrupt. + * - mvNfcReadWrite() + * - Block till CMD_DONE interrupt is issued (Or Error). + * OR + * Poll on mvNfcStatusGet() till CMD_DONE is returned. (Or Error). + * - Wait for PDMA done interrupt to signal data ready in buffer. + * ==> At this stage, data is ready in the read buffer. + * - [If interrupt mode] + * Enable RD_DATA_REQ & CMD_DONE interrupts. + * - mvNfcCommandIssue(MV_NFC_CMD_READ_LAST_NAKED) + * - [In interrupt mode] + * Block till one of the above interrupts is triggered. + * - [In polling mode] + * Poll on mvNfcStatusGet() till STATUS_RDD_REQ is returned. + * - [In interrupt mode] + * Disable the RD_DATA_REQ interrupt. + * - mvNfcReadWrite() + * - Block till CMD_DONE interrupt is issued (Or Error). + * OR + * Poll on mvNfcStatusGet() till CMD_DONE is returned. (Or Error). + * - Wait for PDMA done interrupt to signal data ready in buffer. + * ==> At this stage, second page data is ready in the read buffer. + * - mvNfcSelectChip(MV_NFC_CS_NONE) + * + * Nand Write of single page, PIO mode: + * - mvNfcInit(MV_NFC_PIO_ACCESS) + * - mvNfcSelectChip(...) + * - [If interrupt mode] + * Enable WR_DATA_REQ & CMD_DONE interrupts. + * - mvNfcCommandIssue(MV_NFC_CMD_WRITE_MONOLITHIC) + * - [In interrupt mode] + * Block till one of the above interrupts is triggered. + * - [In polling mode] + * Poll on mvNfcStatusGet() till STATUS_WRD_REQ is returned. + * - [In interrupt mode] + * Disable the WR_DATA_REQ interrupt. + * - mvNfcReadWrite() + * - Block till CMD_DONE interrupt is issued (Or Error). + * OR + * Poll on mvNfcStatusGet() till CMD_DONE is returned. (Or Error). + * ==> At this stage, data was written to the flash device. + * - mvNfcSelectChip(MV_NFC_CS_NONE) + * + * Nand Erase of a single block: + * - mvNfcInit(...) + * - mvNfcSelectChip(...) + * - [If interrupt mode] + * Enable CMD_DONE interrupts. + * - mvNfcCommandIssue(MV_NFC_CMD_ERASE) + * - [In interrupt mode] + * Block till the above interrupt is triggered. + * - [In polling mode] + * Poll on mvNfcStatusGet() till STATUS_CMD_DONE is returned. + * ==> At this stage, flash block was erased from the flash device. + * - mvNfcSelectChip(MV_NFC_CS_NONE) + * + ******************************************************************************/ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysNfcConfig.h" + +/********************************/ +/* Enums and structures */ +/********************************/ + +/* Maximum Chain length */ +#define MV_NFC_MAX_DESC_CHAIN 0x800 + +/* Supported page sizes */ +#define MV_NFC_512B_PAGE 512 +#define MV_NFC_2KB_PAGE 2048 +#define MV_NFC_4KB_PAGE 4096 +#define MV_NFC_8KB_PAGE 8192 + +#define MV_NFC_MAX_CHUNK_SIZE (2048) + +/* Nand controller status bits. */ +#define MV_NFC_STATUS_CMD_REQ 0x1 +#define MV_NFC_STATUS_RDD_REQ 0x2 +#define MV_NFC_STATUS_WRD_REQ 0x4 +#define MV_NFC_STATUS_COR_ERROR 0x8 +#define MV_NFC_STATUS_UNC_ERROR 0x10 +#define MV_NFC_STATUS_BBD 0x20 /* Bad Block Detected */ +#define MV_NFC_STATUS_CMDD 0x80 /* Command Done */ +#define MV_NFC_STATUS_PAGED 0x200 /* Page Done */ +#define MV_NFC_STATUS_RDY 0x800 /* Device Ready */ + +/* Nand controller interrupt bits. */ +#define MV_NFC_WR_CMD_REQ_INT 0x1 +#define MV_NFC_RD_DATA_REQ_INT 0x2 +#define MV_NFC_WR_DATA_REQ_INT 0x4 +#define MV_NFC_CORR_ERR_INT 0x8 +#define MV_NFC_UNCORR_ERR_INT 0x10 +#define MV_NFC_CS1_BAD_BLK_DETECT_INT 0x20 +#define MV_NFC_CS0_BAD_BLK_DETECT_INT 0x40 +#define MV_NFC_CS1_CMD_DONE_INT 0x80 +#define MV_NFC_CS0_CMD_DONE_INT 0x100 +#define MV_NFC_DEVICE_READY_INT 0x800 + +/* Max number of buffers chunks for as single read / write operation */ +#define MV_NFC_RW_MAX_BUFF_NUM 16 + +/* ECC mode options. */ +typedef enum { + MV_NFC_ECC_HAMMING = 0, //1 bit + MV_NFC_ECC_BCH_2K, //4 bit + MV_NFC_ECC_BCH_1K, //8 bit + MV_NFC_ECC_BCH_704B, //12 bit + MV_NFC_ECC_BCH_512B, //16 bit + MV_NFC_ECC_DISABLE, + MV_NFC_ECC_MAX_CNT +}MV_NFC_ECC_MODE; + +typedef enum { + MV_NFC_PIO_ACCESS, + MV_NFC_PDMA_ACCESS +}MV_NFC_IO_MODE; + +typedef enum { + MV_NFC_PIO_READ, + MV_NFC_PIO_WRITE, + MV_NFC_PIO_NONE +}MV_NFC_PIO_RW_MODE; + + +typedef enum { + MV_NFC_IF_1X8, + MV_NFC_IF_1X16, + MV_NFC_IF_2X8 +}MV_NFC_IF_MODE; + + +/* Flash device CS. */ +typedef enum { + MV_NFC_CS_0, + MV_NFC_CS_1, + MV_NFC_CS_2, + MV_NFC_CS_3, + MV_NFC_CS_NONE +}MV_NFC_CHIP_SEL; + + +/* + * ioMode The access mode by which the unit will operate (PDMA / PIO). + * eccMode The ECC mode to configure the controller to. + * ifMode The NAND chip connection mode, 8-bit / 16-bit / gang mode. + * autoStatusRead Whether to automatically read the flash status after each + * erase / write commands. + * tclk System TCLK. + * readyBypass Whether to wait for the RnB sugnal to be deasserted after + * waiting the tR or skip it and move directly to the next step. + * osHandle OS specific handle used for allocating command buffer + * regsPhysAddr Physical address of internal registers (used in DMA + * mode only) + * dataPdmaIntMask Interrupt mask for PDMA data channel (used in DMA mode + * only). + * cmdPdmaIntMask Interrupt mask for PDMA command channel (used in DMA + * mode only). + */ +typedef struct { + MV_NFC_IO_MODE ioMode; + MV_NFC_ECC_MODE eccMode; + MV_NFC_IF_MODE ifMode; + MV_BOOL autoStatusRead; + MV_U32 tclk; + MV_BOOL readyBypass; + MV_VOID * osHandle; + MV_U32 regsPhysAddr; +#ifdef MV_INCLUDE_PDMA + MV_U32 dataPdmaIntMask; + MV_U32 cmdPdmaIntMask; +#endif +}MV_NFC_INFO; + + +typedef enum { + MV_NFC_CMD_READ_ID = 0, + MV_NFC_CMD_READ_STATUS, + MV_NFC_CMD_ERASE, + MV_NFC_CMD_MULTIPLANE_ERASE, + MV_NFC_CMD_RESET, + + MV_NFC_CMD_CACHE_READ_SEQ, + MV_NFC_CMD_CACHE_READ_RAND, + MV_NFC_CMD_EXIT_CACHE_READ, + MV_NFC_CMD_CACHE_READ_START, + MV_NFC_CMD_READ_MONOLITHIC, + MV_NFC_CMD_READ_MULTIPLE, + MV_NFC_CMD_READ_NAKED, + MV_NFC_CMD_READ_LAST_NAKED, + MV_NFC_CMD_READ_DISPATCH, + + MV_NFC_CMD_WRITE_MONOLITHIC, + MV_NFC_CMD_WRITE_MULTIPLE, + MV_NFC_CMD_WRITE_NAKED, + MV_NFC_CMD_WRITE_LAST_NAKED, + MV_NFC_CMD_WRITE_DISPATCH, + MV_NFC_CMD_WRITE_DISPATCH_START, + MV_NFC_CMD_WRITE_DISPATCH_END, + + MV_NFC_CMD_COUNT /* This should be the last enum */ + +}MV_NFC_CMD_TYPE; + + +/* + * Nand information structure. + * flashId The ID of the flash information structure representing the timing + * and physical layout data of the flash device. + * cmdsetId The ID of the command-set structure holding the access + * commands for the flash device. + * flashWidth Flash device interface width in bits. + * autoStatusRead Whether to automatically read the flash status after each + * erase / write commands. + * tclk System TCLK. + * readyBypass Whether to wait for the RnB signal to be deasserted after + * waiting the tR or skip it and move directly to the next step. + * ioMode Controller access mode (PDMA / PIO). + * eccMode Flash ECC mode (Hamming, BCH, None). + * ifMode Flash interface mode. + * currC The current flash CS currently being accessed. + * dataChanHndl Pointer to the data DMA channel + * cmdChanHndl Pointer to the command DMA Channel + * cmdBuff Command buffer information (used in DMA only) + * regsPhysAddr Physical address of internal registers (used in DMA + * mode only) + * dataPdmaIntMask Interrupt mask for PDMA data channel (used in DMA mode + * only). + * cmdPdmaIntMask Interrupt mask for PDMA command channel (used in DMA + * mode only). + */ +typedef struct { + MV_U32 flashIdx; + MV_U32 cmdsetIdx; + MV_U32 flashWidth; + MV_U32 dfcWidth; + MV_BOOL autoStatusRead; + MV_BOOL readyBypass; + MV_NFC_IO_MODE ioMode; + MV_NFC_ECC_MODE eccMode; + MV_NFC_IF_MODE ifMode; + MV_NFC_CHIP_SEL currCs; +#ifdef MV_INCLUDE_PDMA + MV_PDMA_CHANNEL dataChanHndl; + MV_PDMA_CHANNEL cmdChanHndl; +#endif + MV_BUF_INFO cmdBuff; + MV_BUF_INFO cmdDescBuff; + MV_BUF_INFO dataDescBuff; + MV_U32 regsPhysAddr; +#ifdef MV_INCLUDE_PDMA + MV_U32 dataPdmaIntMask; + MV_U32 cmdPdmaIntMask; +#endif +}MV_NFC_CTRL; + +/* + * Nand multi command information structure. + * cmd The command to be issued. + * pageAddr The flash page address to operate on. + * pageCount Number of pages to read / write. + * virtAddr The virtual address of the buffer to copy data to / + * from (For relevant commands). + * physAddr The physical address of the buffer to copy data to / + * from (For relevant commands). + * The following parameters might only be used when working in Gagned PDMA + * and the pageCount must be set to 1. + * For ganged mode, the use might need to split the NAND stack read / + * write buffer into several buffers according to what the HW expects. + * e.g. NAND stack expects data in the following format: + * --------------------------- + * | Data (4K) | Spare | ECC | + * --------------------------- + * While NAND controller expects data to be in the following format: + * ----------------------------------------------------- + * | Data (2K) | Spare | ECC | Data (2K) | Spare | ECC | + * ----------------------------------------------------- + * numSgBuffs Number of buffers to split the HW buffer into + * If 1, then buffOffset & buffSize are ignored. + * sgBuffAddr Array holding the address of the buffers into which the + * HW data should be split (Or read into). + * sgBuffSize Array holding the size of each sub-buffer, entry "i" + * represents the size in bytes of the buffer starting at + * offset buffOffset[i]. + */ +typedef struct { + MV_NFC_CMD_TYPE cmd; + MV_U32 pageAddr; + MV_U32 pageCount; + MV_U32 *virtAddr; + MV_U32 physAddr; + MV_U32 numSgBuffs; + MV_U32 sgBuffAddr[MV_NFC_RW_MAX_BUFF_NUM]; + MV_U32 *sgBuffAddrVirt[MV_NFC_RW_MAX_BUFF_NUM]; + MV_U32 sgBuffSize[MV_NFC_RW_MAX_BUFF_NUM]; + MV_U32 length; +}MV_NFC_MULTI_CMD; + +typedef struct { + MV_U32 cmdb0; + MV_U32 cmdb1; + MV_U32 cmdb2; + MV_U32 cmdb3; +}MV_NFC_CMD; + + +/********************************/ +/* Functions API */ +/********************************/ + +MV_STATUS mvNfcInit(MV_NFC_INFO *nfcInfo, MV_NFC_CTRL *nfcCtrl); +MV_STATUS mvNfcSelectChip(MV_NFC_CTRL *nfcCtrl, MV_NFC_CHIP_SEL chip); +MV_STATUS mvNfcCommandPio(MV_NFC_CTRL *nfcCtrl, MV_NFC_MULTI_CMD * cmd_desc, MV_BOOL next); +MV_STATUS mvNfcCommandMultiple(MV_NFC_CTRL *nfcCtrl, MV_NFC_MULTI_CMD *descInfo, MV_U32 descCnt); +MV_U32 mvNfcStatusGet(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *value); +MV_STATUS mvNfcIntrSet(MV_NFC_CTRL *nfcCtrl, MV_U32 intMask, MV_BOOL enable); +MV_STATUS mvNfcReadWrite(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *virtBufAddr, MV_U32 physBuffAddr); +MV_VOID mvNfcReadWritePio(MV_NFC_CTRL *nfcCtrl, MV_U32 * buff, MV_U32 data_len, MV_NFC_PIO_RW_MODE mode); +MV_VOID mvNfcAddress2RowConvert(MV_NFC_CTRL *nfcCtrl, MV_U32 address, MV_U32 *row, MV_U32 *colOffset); +MV_VOID mvNfcAddress2BlockConvert(MV_NFC_CTRL *nfcCtrl, MV_U32 address, MV_U32 *blk); +MV_8 * mvNfcFlashModelGet(MV_NFC_CTRL *nfcCtrl); +MV_STATUS mvNfcFlashPageSizeGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *size, MV_U32 *totalSize); +MV_STATUS mvNfcFlashBlockSizeGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *size); +MV_STATUS mvNfcFlashBlockNumGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *numBlocks); +MV_STATUS mvNfcDataLength(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 *data_len); +MV_STATUS mvNfcTransferDataLength(MV_NFC_CTRL *nfcCtrl, MV_NFC_CMD_TYPE cmd, MV_U32 * data_len); +MV_STATUS mvNfcFlashIdGet(MV_NFC_CTRL *nfcCtrl, MV_U32 *flashId); +MV_STATUS mvNfcUnitStateStore(MV_U32 *stateData, MV_U32 *len); +MV_NFC_ECC_MODE mvNfcEccModeSet(MV_NFC_CTRL *nfcCtrl, MV_NFC_ECC_MODE eccMode); +MV_U32 mvNfcBadBlockPageNumber(MV_NFC_CTRL *nfcCtrl); + +#ifdef __cplusplus +} +#endif + + +#endif /* __INCMVNFCH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfcRegs.h u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfcRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/nfc/mvNfcRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/nfc/mvNfcRegs.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,313 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVNFCREGSH +#define __INCMVNFCREGSH + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvSysNfcConfig.h" + +/* NAND Flash Control Register */ +#define NFC_CONTROL_REG (MV_NFC_REGS_BASE + 0x0) +#define NFC_CTRL_WRCMDREQ_MASK (0x1 << 0) +#define NFC_CTRL_RDDREQ_MASK (0x1 << 1) +#define NFC_CTRL_WRDREQ_MASK (0x1 << 2) +#define NFC_CTRL_CORRERR_MASK (0x1 << 3) +#define NFC_CTRL_UNCERR_MASK (0x1 << 4) +#define NFC_CTRL_CS1_BBD_MASK (0x1 << 5) +#define NFC_CTRL_CS0_BBD_MASK (0x1 << 6) +#define NFC_CTRL_CS1_CMDD_MASK (0x1 << 7) +#define NFC_CTRL_CS0_CMDD_MASK (0x1 << 8) +#define NFC_CTRL_CS1_PAGED_MASK (0x1 << 9) +#define NFC_CTRL_CS0_PAGED_MASK (0x1 << 10) +#define NFC_CTRL_RDY_MASK (0x1 << 11) +#define NFC_CTRL_ND_ARB_EN_MASK (0x1 << 12) +#define NFC_CTRL_PG_PER_BLK_OFFS 13 +#define NFC_CTRL_PG_PER_BLK_MASK (0x3 << NFC_CTRL_PG_PER_BLK_OFFS) +#define NFC_CTRL_PG_PER_BLK_32 (0x0 << NFC_CTRL_PG_PER_BLK_OFFS) +#define NFC_CTRL_PG_PER_BLK_64 (0x2 << NFC_CTRL_PG_PER_BLK_OFFS) +#define NFC_CTRL_PG_PER_BLK_128 (0x1 << NFC_CTRL_PG_PER_BLK_OFFS) +#define NFC_CTRL_PG_PER_BLK_256 (0x3 << NFC_CTRL_PG_PER_BLK_OFFS) +#define NFC_CTRL_RA_START_MASK (0x1 << 15) +#define NFC_CTRL_RD_ID_CNT_OFFS 16 +#define NFC_CTRL_RD_ID_CNT_MASK (0x7 << NFC_CTRL_RD_ID_CNT_OFFS) +#define NFC_CTRL_RD_ID_CNT_SP (0x2 << NFC_CTRL_RD_ID_CNT_OFFS) +#define NFC_CTRL_RD_ID_CNT_LP (0x4 << NFC_CTRL_RD_ID_CNT_OFFS) +#define NFC_CTRL_CLR_PG_CNT_MASK (0x1 << 20) +#define NFC_CTRL_FORCE_CSX_MASK (0x1 << 21) +#define NFC_CTRL_ND_STOP_MASK (0x1 << 22) +#define NFC_CTRL_SEQ_DIS_MASK (0x1 << 23) +#define NFC_CTRL_PAGE_SZ_OFFS 24 +#define NFC_CTRL_PAGE_SZ_MASK (0x3 << NFC_CTRL_PAGE_SZ_OFFS) +#define NFC_CTRL_PAGE_SZ_512B (0x0 << NFC_CTRL_PAGE_SZ_OFFS) +#define NFC_CTRL_PAGE_SZ_2KB (0x1 << NFC_CTRL_PAGE_SZ_OFFS) +#define NFC_CTRL_DWIDTH_M_MASK (0x1 << 26) +#define NFC_CTRL_DWIDTH_C_MASK (0x1 << 27) +#define NFC_CTRL_ND_RUN_MASK (0x1 << 28) +#define NFC_CTRL_DMA_EN_MASK (0x1 << 29) +#define NFC_CTRL_ECC_EN_MASK (0x1 << 30) +#define NFC_CTRL_SPARE_EN_MASK (0x1 << 31) + +/* NAND Interface Timing Parameter 0 Register */ +#define NFC_TIMING_0_REG (MV_NFC_REGS_BASE + 0x4) +#define NFC_TMNG0_TRP_OFFS 0 +#define NFC_TMNG0_TRP_MASK (0x7 << NFC_TMNG0_TRP_OFFS) +#define NFC_TMNG0_TRH_OFFS 3 +#define NFC_TMNG0_TRH_MASK (0x7 << NFC_TMNG0_TRH_OFFS) +#define NFC_TMNG0_ETRP_MASK (0x1 << 6) +#define NFC_TMNG0_SEL_NRE_EDGE_MASK (0x1 << 7) +#define NFC_TMNG0_TWP_OFFS 8 +#define NFC_TMNG0_TWP_MASK (0x7 << NFC_TMNG0_TWP_OFFS) +#define NFC_TMNG0_TWH_OFFS 11 +#define NFC_TMNG0_TWH_MASK (0x7 << NFC_TMNG0_TWH_OFFS) +#define NFC_TMNG0_TCS_OFFS 16 +#define NFC_TMNG0_TCS_MASK (0x7 << NFC_TMNG0_TCS_OFFS) +#define NFC_TMNG0_TCH_OFFS 19 +#define NFC_TMNG0_TCH_MASK (0x7 << NFC_TMNG0_TCH_OFFS) +#define NFC_TMNG0_RD_CNT_DEL_OFFS 22 +#define NFC_TMNG0_RD_CNT_DEL_MASK (0xF << NFC_TMNG0_RD_CNT_DEL_OFFS) +#define NFC_TMNG0_SEL_CNTR_MASK (0x1 << 26) +#define NFC_TMNG0_TADL_OFFS 27 +#define NFC_TMNG0_TADL_MASK (0x1F << NFC_TMNG0_TADL_OFFS) + +/* NAND Interface Timing Parameter 1 Register */ +#define NFC_TIMING_1_REG (MV_NFC_REGS_BASE + 0xC) +#define NFC_TMNG1_TAR_OFFS 0 +#define NFC_TMNG1_TAR_MASK (0xF << NFC_TMNG1_TAR_OFFS) +#define NFC_TMNG1_TWHR_OFFS 4 +#define NFC_TMNG1_TWHR_MASK (0xF << NFC_TMNG1_TWHR_OFFS) +#define NFC_TMNG1_TRHW_OFFS 8 +#define NFC_TMNG1_TRHW_MASK (0x3 << NFC_TMNG1_TRHW_OFFS) +#define NFC_TMNG1_PRESCALE_MASK (0x1 << 14) +#define NFC_TMNG1_WAIT_MODE_MASK (0x1 << 15) +#define NFC_TMNG1_TR_OFFS 16 +#define NFC_TMNG1_TR_MASK (0xFFFF << NFC_TMNG1_TR_OFFS) + +/* NAND Controller Status Register - NDSR */ +#define NFC_STATUS_REG (MV_NFC_REGS_BASE + 0x14) +#define NFC_SR_WRCMDREQ_MASK (0x1 << 0) +#define NFC_SR_RDDREQ_MASK (0x1 << 1) +#define NFC_SR_WRDREQ_MASK (0x1 << 2) +#define NFC_SR_CORERR_MASK (0x1 << 3) +#define NFC_SR_UNCERR_MASK (0x1 << 4) +#define NFC_SR_CS1_BBD_MASK (0x1 << 5) +#define NFC_SR_CS0_BBD_MASK (0x1 << 6) +#define NFC_SR_CS1_CMDD_MASK (0x1 << 7) +#define NFC_SR_CS0_CMDD_MASK (0x1 << 8) +#define NFC_SR_CS1_PAGED_MASK (0x1 << 9) +#define NFC_SR_CS0_PAGED_MASK (0x1 << 10) +#define NFC_SR_RDY0_MASK (0x1 << 11) +#define NFC_SR_RDY1_MASK (0x1 << 12) +#define NFC_SR_ALLIRQ_MASK (0x1FFF << 0) +#define NFC_SR_TRUSTVIO_MASK (0x1 << 15) +#define NFC_SR_ERR_CNT_OFFS 16 +#define NFC_SR_ERR_CNT_MASK (0x1F << NFC_SR_ERR_CNT_OFFS) + +/* NAND Controller Page Count Register */ +#define NFC_PAGE_COUNT_REG (MV_NFC_REGS_BASE + 0x18) +#define NFC_PCR_PG_CNT_0_OFFS 0 +#define NFC_PCR_PG_CNT_0_MASK (0xFF << NFC_PCR_PG_CNT_0_OFFS) +#define NFC_PCR_PG_CNT_1_OFFS 16 +#define NFC_PCR_PG_CNT_1_MASK (0xFF << NFC_PCR_PG_CNT_1_OFFS) + +/* NAND Controller Bad Block 0 Register */ +#define NFC_BAD_BLOCK_0_REG (MV_NFC_REGS_BASE + 0x1C) + +/* NAND Controller Bad Block 1 Register */ +#define NFC_BAD_BLOCK_1_REG (MV_NFC_REGS_BASE + 0x20) + +/* NAND ECC Controle Register */ +#define NFC_ECC_CONTROL_REG (MV_NFC_REGS_BASE + 0x28) +#define NFC_ECC_BCH_EN_MASK (0x1 << 0) +#define NFC_ECC_THRESHOLD_OFFS 1 +#define NFC_ECC_THRESHOLF_MASK (0x3F << NFC_ECC_THRESHOLD_OFFS) +#define NFC_ECC_SPARE_OFFS 7 +#define NFC_ECC_SPARE_MASK (0xFF << NFC_ECC_SPARE_OFFS) + +/* NAND Busy Length Count */ +#define NFC_BUSY_LEN_CNT_REG (MV_NFC_REGS_BASE + 0x2C) +#define NFC_BUSY_CNT_0_OFFS 0 +#define NFC_BUSY_CNT_0_MASK (0xFFFF << NFC_BUSY_CNT_0_OFFS) +#define NFC_BUSY_CNT_1_OFFS 16 +#define NFC_BUSY_CNT_1_MASK (0xFFFF << NFC_BUSY_CNT_1_OFFS) + +/* NAND Mutex Lock */ +#define NFC_MUTEX_LOCK_REG (MV_NFC_REGS_BASE + 0x30) +#define NFC_MUTEX_LOCK_MASK (0x1 << 0) + +/* NAND Partition Command Match */ +#define NFC_PART_CMD_MACTH_1_REG (MV_NFC_REGS_BASE + 0x34) +#define NFC_PART_CMD_MACTH_2_REG (MV_NFC_REGS_BASE + 0x38) +#define NFC_PART_CMD_MACTH_3_REG (MV_NFC_REGS_BASE + 0x3C) +#define NFC_CMDMAT_CMD1_MATCH_OFFS 0 +#define NFC_CMDMAT_CMD1_MATCH_MASK (0xFF << NFC_CMDMAT_CMD1_MATCH_OFFS) +#define NFC_CMDMAT_CMD1_ROWADD_MASK (0x1 << 8) +#define NFC_CMDMAT_CMD1_NKDDIS_MASK (0x1 << 9) +#define NFC_CMDMAT_CMD2_MATCH_OFFS 10 +#define NFC_CMDMAT_CMD2_MATCH_MASK (0xFF << NFC_CMDMAT_CMD2_MATCH_OFFS) +#define NFC_CMDMAT_CMD2_ROWADD_MASK (0x1 << 18) +#define NFC_CMDMAT_CMD2_NKDDIS_MASK (0x1 << 19) +#define NFC_CMDMAT_CMD3_MATCH_OFFS 20 +#define NFC_CMDMAT_CMD3_MATCH_MASK (0xFF << NFC_CMDMAT_CMD3_MATCH_OFFS) +#define NFC_CMDMAT_CMD3_ROWADD_MASK (0x1 << 28) +#define NFC_CMDMAT_CMD3_NKDDIS_MASK (0x1 << 29) +#define NFC_CMDMAT_VALID_CNT_OFFS 30 +#define NFC_CMDMAT_VALID_CNT_MASK (0x3 << NFC_CMDMAT_VALID_CNT_OFFS) + +/* NAND Controller Data Buffer */ +#define NFC_DATA_BUFF_REG_4PDMA (MV_NFC_REGS_OFFSET + 0x40) +#define NFC_DATA_BUFF_REG (MV_NFC_REGS_BASE + 0x40) + +/* NAND Controller Command Buffer 0 */ +#define NFC_COMMAND_BUFF_0_REG_4PDMA (MV_NFC_REGS_OFFSET + 0x48) +#define NFC_COMMAND_BUFF_0_REG (MV_NFC_REGS_BASE + 0x48) +#define NFC_CB0_CMD1_OFFS 0 +#define NFC_CB0_CMD1_MASK (0xFF << NFC_CB0_CMD1_OFFS) +#define NFC_CB0_CMD2_OFFS 8 +#define NFC_CB0_CMD2_MASK (0xFF << NFC_CB0_CMD2_OFFS) +#define NFC_CB0_ADDR_CYC_OFFS 16 +#define NFC_CB0_ADDR_CYC_MASK (0x7 << NFC_CB0_ADDR_CYC_OFFS) +#define NFC_CB0_DBC_MASK (0x1 << 19) +#define NFC_CB0_NEXT_CMD_MASK (0x1 << 20) +#define NFC_CB0_CMD_TYPE_OFFS 21 +#define NFC_CB0_CMD_TYPE_MASK (0x7 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_READ (0x0 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_WRITE (0x1 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_ERASE (0x2 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_READ_ID (0x3 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_STATUS (0x4 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_RESET (0x5 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_NAKED_CMD (0x6 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CMD_TYPE_NAKED_ADDR (0x7 << NFC_CB0_CMD_TYPE_OFFS) +#define NFC_CB0_CSEL_MASK (0x1 << 24) +#define NFC_CB0_AUTO_RS_MASK (0x1 << 25) +#define NFC_CB0_ST_ROW_EN_MASK (0x1 << 26) +#define NFC_CB0_RDY_BYP_MASK (0x1 << 27) +#define NFC_CB0_LEN_OVRD_MASK (0x1 << 28) +#define NFC_CB0_CMD_XTYPE_OFFS 29 +#define NFC_CB0_CMD_XTYPE_MASK (0x7 << NFC_CB0_CMD_XTYPE_OFFS) +#define NFC_CB0_CMD_XTYPE_MONOLITHIC (0x0 << NFC_CB0_CMD_XTYPE_OFFS) +#define NFC_CB0_CMD_XTYPE_LAST_NAKED (0x1 << NFC_CB0_CMD_XTYPE_OFFS) +#define NFC_CB0_CMD_XTYPE_MULTIPLE (0x4 << NFC_CB0_CMD_XTYPE_OFFS) +#define NFC_CB0_CMD_XTYPE_NAKED (0x5 << NFC_CB0_CMD_XTYPE_OFFS) +#define NFC_CB0_CMD_XTYPE_DISPATCH (0x6 << NFC_CB0_CMD_XTYPE_OFFS) + +/* NAND Controller Command Buffer 1 */ +#define NFC_COMMAND_BUFF_1_REG (MV_NFC_REGS_BASE + 0x4C) +#define NFC_CB1_ADDR1_OFFS 0 +#define NFC_CB1_ADDR1_MASK (0xFF << NFC_CB1_ADDR1_OFFS) +#define NFC_CB1_ADDR2_OFFS 8 +#define NFC_CB1_ADDR2_MASK (0xFF << NFC_CB1_ADDR2_OFFS) +#define NFC_CB1_ADDR3_OFFS 16 +#define NFC_CB1_ADDR3_MASK (0xFF << NFC_CB1_ADDR3_OFFS) +#define NFC_CB1_ADDR4_OFFS 24 +#define NFC_CB1_ADDR4_MASK (0xFF << NFC_CB1_ADDR4_OFFS) + +/* NAND Controller Command Buffer 2 */ +#define NFC_COMMAND_BUFF_2_REG (MV_NFC_REGS_BASE + 0x50) +#define NFC_CB2_ADDR5_OFFS 0 +#define NFC_CB2_ADDR5_MASK (0xFF << NFC_CB2_ADDR5_OFFS) +#define NFC_CB2_CS_2_3_SELECT_MASK (0x80 << NFC_CB2_ADDR5_OFFS) +#define NFC_CB2_PAGE_CNT_OFFS 8 +#define NFC_CB2_PAGE_CNT_MASK (0xFF << NFC_CB2_PAGE_CNT_OFFS) +#define NFC_CB2_ST_CMD_OFFS 16 +#define NFC_CB2_ST_CMD_MASK (0xFF << NFC_CB2_ST_CMD_OFFS) +#define NFC_CB2_ST_MASK_OFFS 24 +#define NFC_CB2_ST_MASK_MASK (0xFF << NFC_CB2_ST_MASK_OFFS) + +/* NAND Controller Command Buffer 3 */ +#define NFC_COMMAND_BUFF_3_REG (MV_NFC_REGS_BASE + 0x54) +#define NFC_CB3_NDLENCNT_OFFS 0 +#define NFC_CB3_NDLENCNT_MASK (0xFFFF << NFC_CB3_NDLENCNT_OFFS) +#define NFC_CB3_ADDR6_OFFS 16 +#define NFC_CB3_ADDR6_MASK (0xFF << NFC_CB3_ADDR6_OFFS) +#define NFC_CB3_ADDR7_OFFS 24 +#define NFC_CB3_ADDR7_MASK (0xFF << NFC_CB3_ADDR7_OFFS) + +/* NAND Arbitration Control */ +#define NFC_ARB_CONTROL_REG (MV_NFC_REGS_BASE + 0x5C) +#define NFC_ARB_CNT_OFFS 0 +#define NFC_ARB_CNT_MASK (0xFFFF << NFC_ARB_CNT_OFFS) + +/* NAND Partition Table for Chip Select */ +#define NFC_PART_TBL_4CS_REG(x) (MV_NFC_REGS_BASE + (x * 0x4)) +#define NFC_PT4CS_BLOCKADD_OFFS 0 +#define NFC_PT4CS_BLOCKADD_MASK (0xFFFFFF << NFC_PT4CS_BLOCKADD_OFFS) +#define NFC_PT4CS_TRUSTED_MASK (0x1 << 29) +#define NFC_PT4CS_LOCK_MASK (0x1 << 30) +#define NFC_PT4CS_VALID_MASK (0x1 << 31) + +/* NAND XBAR2AXI Bridge Configuration Register */ +#define NFC_XBAR2AXI_BRDG_CFG_REG (MV_NFC_REGS_BASE + 0x1022C) +#define NFC_XBC_CS_EXPAND_EN_MASK (0x1 << 2) + +#ifdef __cplusplus +} +#endif + + +#endif /* __INCMVNFCREGSH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/pci-if/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/mvCompVer.txt 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIf.c u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIf.c --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIf.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIf.c 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,344 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPciIf.h" +#include "mvSysPexApi.h" + +/* #if defined(MV_INCLUDE_PCI) */ +/* #include "ctrlEnv/sys/mvSysPci.h" */ +/* #endif */ + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvPciInit - Initialize PCI interfaces +* +* DESCRIPTION: +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode) +{ + MV_PEX_TYPE pexType; + if (PCI_IF_MODE_HOST == pciIfmode) { + pexType = MV_PEX_ROOT_COMPLEX; + } else if (PCI_IF_MODE_DEVICE == pciIfmode) { + pexType = MV_PEX_END_POINT; + } else { + mvOsPrintf("%s: ERROR!!! Bus %d type %d neither root complex nor" + " end point\n", __func__, pciIf, pciIfmode); + return MV_FAIL; + } + return mvSysPexInit(pciIf, pexType); +} + +/* PCI configuration space read write */ +/******************************************************************************* +* mvPciConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPciIfConfigRead(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff) +{ + return mvPexConfigRead(pciIf, bus, dev, func, regOff); +} + +/******************************************************************************* +* mvPciConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + return mvPexConfigWrite(pciIf, bus, dev, func, regOff, data); +} + +/******************************************************************************* +* mvPciMasterEnable - Enable/disale PCI interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable) +{ + return mvPexMasterEnable(pciIf, enable); +} + +/******************************************************************************* +* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PCI slave is allowed to respond to PCI IO space access (bit 0) +* and PCI memory space access (bit 1). +* +* INPUT: +* pciIf - PCI interface number. +* dev - PCI device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + return mvPexSlaveEnable(pciIf, bus, dev, enable); +} + +/******************************************************************************* +* mvPciLocalBusNumSet - Set PCI interface local bus number. +* +* DESCRIPTION: +* This function sets given PCI interface its local bus number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters, otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) +{ + return mvPexLocalBusNumSet(pciIf, busNum); +} + +/******************************************************************************* +* mvPciLocalBusNumGet - Get PCI interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf) +{ + return mvPexLocalBusNumGet(pciIf); +} + +/******************************************************************************* +* mvPciLocalDevNumSet - Set PCI interface local device number. +* +* DESCRIPTION: +* This function sets given PCI interface its local device number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters, otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) +{ + return mvPexLocalDevNumSet(pciIf, devNum); +} + +/******************************************************************************* +* mvPciLocalDevNumGet - Get PCI interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf) +{ + return mvPexLocalDevNumGet(pciIf); +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf) +{ + return PCI_IF_TYPE_PEX; +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) +{ + return pciIf; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIf.h u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIf.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIf.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,126 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFH +#define __INCPCIIFH + +#include "mvSysHwConfig.h" +#include "pci-if/mvPciIfRegs.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif +#if defined(MV_INCLUDE_PCI) +#include "pci/mvPci.h" +#endif +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef enum _mvPCIIfType { + PCI_IF_TYPE_CONVEN_PCIX, + PCI_IF_TYPE_PEX +} PCI_IF_TYPE; + +typedef enum _mvPCIIfMode { + PCI_IF_MODE_HOST, + PCI_IF_MODE_DEVICE +} PCI_IF_MODE; + +/* Global Functions prototypes */ + +/* mvPciIfInit - Initialize PCI interfaces*/ +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); + +/* mvPciIfConfigRead - Read from configuration space */ +MV_U32 mvPciIfConfigRead(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff); + +/* mvPciIfConfigWrite - Write to configuration space */ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable); + +/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); + +/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); + +/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); + +/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); + +/* mvPciIfTypeGet - Get PCI If type*/ +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); + +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); + +/* mvPciIfAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPciIfAddrDecShow(MV_VOID); + +#endif /* #ifndef __INCPCIIFH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIfRegs.h u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIfRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/mvPciIfRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/mvPciIfRegs.h 2011-04-04 13:57:35.005596391 -0400 @@ -0,0 +1,235 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFREGSH +#define __INCPCIIFREGSH + +/* defines */ +#define MAX_PCI_DEVICES 32 +#define MAX_PCI_FUNCS 8 +#define MAX_PCI_BUSSES 128 + +/***************************************/ +/* PCI Configuration registers */ +/***************************************/ + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +/* Standard registers */ +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C + +/* PCI Device and Vendor ID Register (PDVIR) */ +#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ +#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) + +#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ +#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) + +/* PCI Status and Command Register (PSCR) */ +#define PSCR_IO_EN BIT0 /* IO Enable */ +#define PSCR_MEM_EN BIT1 /* Memory Enable */ +#define PSCR_MASTER_EN BIT2 /* Master Enable */ +#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ +#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ +#define PSCR_VGA BIT5 /* VGA Palette Snoops */ +#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En) */ +#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions */ +#define PSCR_CAP_LIST BIT20 /* Capability List Support */ +#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ +#define PSCR_UDF_EN BIT22 /* User definable features */ +#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ +#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ + +#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ +#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) + +#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ +#define PSCR_MABORT BIT29 /* Recieved Master Abort */ +#define PSCR_SYSERR BIT30 /* Signalled system error */ +#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ + +/* PCI configuration register offset=0x08 fields + (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ + +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) + +#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F */ +#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) + +#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class */ +#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) + +#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class */ +#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) + +/* PCI configuration register offset=0x0C fields + (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ + +#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) + +#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ +#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) + +#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) + +#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ +#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) + +#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) + +#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ +#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ + +/* PCI Bar Base Low Register (PBBLR) */ +#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) + +#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to +address bits [31:4] */ +#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) + +#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to +address bits [31:2] */ +#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) + +#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ +#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) +#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) + +/* PCI Bar Base High Fegister (PBBHR) */ +#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ +#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + +/* PCI configuration register offset=0x2C fields + (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ + +#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) + +#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) + +/* PCI configuration register offset=0x30 fields + (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ + +#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ +#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) + +/* PCI configuration register offset=0x34 fields + (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ + +#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) + +/* PCI configuration register offset=0x3C fields + (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ + +#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) + +#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A, B, C, D) */ +#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) + +#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ +#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) + +#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ +#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) + +#endif /* #ifndef __INCPCIIFREGSH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.c u-boot-2009.08/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.c --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,753 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "pci-if/pci_util/mvPciUtils.h" +#include "pex/mvPex.h" +#include "mvCtrlEnvLib.h" +#include "pci-if/mvPciIf.h" + +/* #define MV_DEBUG */ +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_PCI_DEVICE *pPciAgent); + +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_PCI_DEVICE *pPciAgent); + +/******************************************************************************* +* mvPciScan - Scan a PCI interface bus +* +* DESCRIPTION: +* Performs a full scan on a PCI interface and returns all possible details +* on the agents found on the bus. +* +* INPUT: +* pciIf - PCI Interface +* pPciAgents - Pointer to an Array of the pci agents to be detected +* pPciAgentsNum - pPciAgents array maximum number of elements +* +* OUTPUT: +* pPciAgents - Array of the pci agents detected on the bus +* pPciAgentsNum - Number of pci agents detected on the bus +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPciScan(MV_U32 pciIf, MV_PCI_DEVICE *pPciAgents, MV_U32 * pPciAgentsNum) +{ + + MV_U32 devIndex, funcIndex = 0, busIndex = 0, detectedDevNum = 0; + MV_U32 localBus = mvPexLocalBusNumGet(pciIf); + MV_PCI_DEVICE *pPciDevice; + MV_PCI_DEVICE *pMainDevice; + + DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); + /* Parameter checking */ + if (pciIf >= mvCtrlPciIfMaxIfGet()) { + DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); + return MV_BAD_PARAM; + } + if (NULL == pPciAgents) { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); + return MV_BAD_PARAM; + } + if (NULL == pPciAgentsNum) { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); + return MV_BAD_PARAM; + } + + DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); + /* Master enable the MV PCI master */ + if (MV_OK != mvPciIfMasterEnable(pciIf, MV_TRUE)) { + DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); + return MV_ERROR; + + } + + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); + + /* go through all busses */ + for (busIndex = localBus; busIndex < MAX_PCI_BUSSES; busIndex++) { + /* go through all possible devices on the local bus */ + for (devIndex = 0; devIndex < MAX_PCI_DEVICES; devIndex++) { + /* always start with function equal to zero */ + funcIndex = 0; + + pPciDevice = &pPciAgents[detectedDevNum]; + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); + + if (MV_ERROR == pciDetectDevice(pciIf, busIndex, devIndex, funcIndex, pPciDevice)) { + /* no device detected , try the next address */ + continue; + } + + /* We are here ! means we have detected a device */ + /* always we start with only one function per device */ + pMainDevice = pPciDevice; + pPciDevice->funtionsNum = 1; + + /* move on */ + detectedDevNum++; + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) { + DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); + return MV_ERROR; + } + + /* check the detected device if it is a multi functional device then + scan all device functions */ + if (pPciDevice->isMultiFunction == MV_TRUE) { + /* start with function number 1 because we have already detected + function 0 */ + for (funcIndex = 1; funcIndex < MAX_PCI_FUNCS; funcIndex++) { + pPciDevice = &pPciAgents[detectedDevNum]; + + if (MV_ERROR == pciDetectDevice(pciIf, + busIndex, + devIndex, funcIndex, pPciDevice)) { + /* no device detected means no more functions ! */ + continue; + } + /* We are here ! means we have detected a device */ + + /* move on */ + pMainDevice->funtionsNum++; + detectedDevNum++; + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) { + DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); + return MV_ERROR; + } + } + } + } + } + + /* return the number of devices actually detected on the bus ! */ + *pPciAgentsNum = detectedDevNum; + + return MV_OK; +} + +/******************************************************************************* +* pciDetectDevice - Detect a pci device parameters +* +* DESCRIPTION: +* This function detect if a pci agent exist on certain address ! +* and if exists then it fills all possible information on the +* agent +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* MV_ERROR if no device , MV_OK otherwise +* +*******************************************************************************/ + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData; + + /* no Parameters checking ! because it is static function and it is assumed + that all parameters were checked in the calling function */ + + /* Try read the PCI Vendor ID and Device ID */ + + /* We will scan only ourselves and the PCI slots that exist on the + board, because we may have a case that we have one slot that has + a Cardbus connector, and because CardBus answers all IDsels we want + to scan only this slot and ourseleves. + + */ +#if defined(MV_INCLUDE_PCI) + if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && + (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && + (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && + (DB_88F5181_DDR1_MNG != mvBoardIdGet()) && (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE)) + return MV_ERROR; + +#endif /* defined(MV_INCLUDE_PCI) */ + + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_DEVICE_AND_VENDOR_ID); + + if (PCI_ERROR_CODE == pciData) { + /* no device exist */ + return MV_ERROR; + } + + /* we are here ! means a device is detected */ + + /* fill basic information */ + pPciAgent->busNumber = bus; + pPciAgent->deviceNum = dev; + pPciAgent->function = func; + + /* Fill the PCI Vendor ID and Device ID */ + + pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; + pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; + + /* Read Status and command */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_STATUS_AND_COMMAND); + + /* Fill related Status and Command information */ + + if (pciData & PSCR_TAR_FAST_BB) + pPciAgent->isFastB2BCapable = MV_TRUE; + else + pPciAgent->isFastB2BCapable = MV_FALSE; + + if (pciData & PSCR_CAP_LIST) + pPciAgent->isCapListSupport = MV_TRUE; + else + pPciAgent->isCapListSupport = MV_FALSE; + + if (pciData & PSCR_66MHZ_EN) + pPciAgent->is66MHZCapable = MV_TRUE; + else + pPciAgent->is66MHZCapable = MV_FALSE; + + /* Read Class Code and Revision */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_CLASS_CODE_AND_REVISION_ID); + + pPciAgent->baseClassCode = (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; + + pPciAgent->subClassCode = (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; + + pPciAgent->progIf = (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; + + pPciAgent->revisionID = (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; + + /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); + + pPciAgent->pciCacheLine = (pciData & PBHTLTCLR_CACHELINE_MASK) >> PBHTLTCLR_CACHELINE_OFFS; + pPciAgent->pciLatencyTimer = (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; + + switch (pciData & PBHTLTCLR_HEADER_MASK) { + case PBHTLTCLR_HEADER_STANDARD: + + pPciAgent->pciHeader = MV_PCI_STANDARD; + break; + case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: + + pPciAgent->pciHeader = MV_PCI_PCI2PCI_BRIDGE; + break; + } + + if (pciData & PBHTLTCLR_MULTI_FUNC) + pPciAgent->isMultiFunction = MV_TRUE; + else + pPciAgent->isMultiFunction = MV_FALSE; + + if (pciData & PBHTLTCLR_BISTCAP) + pPciAgent->isBISTCapable = MV_TRUE; + else + pPciAgent->isBISTCapable = MV_FALSE; + + /* read this device pci bars */ + + pciDetectDeviceBars(pciIf, bus, dev, func, pPciAgent); + + /* check if we are bridge */ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS) && (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) { + + /* Read P2P_BUSSES_NUM */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, P2P_BUSSES_NUM); + + pPciAgent->p2pPrimBusNum = (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; + + pPciAgent->p2pSecBusNum = (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; + + pPciAgent->p2pSubBusNum = (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; + + pPciAgent->p2pSecLatencyTimer = (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; + + /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, P2P_IO_BASE_LIMIT_SEC_STATUS); + + pPciAgent->p2pSecStatus = (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; + + pPciAgent->p2pIObase = (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; + + /* clear low address (should be zero) */ + pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; + + pPciAgent->p2pIOLimit = (pciData & PIBLSS_IO_LIMIT_MASK); + + /* fill low address with 0xfff */ + pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; + + switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) { + case PIBLSS_ADD_CAP_16BIT: + + pPciAgent->bIO32 = MV_FALSE; + + break; + case PIBLSS_ADD_CAP_32BIT: + + pPciAgent->bIO32 = MV_TRUE; + + /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, P2P_IO_BASE_LIMIT_UPPER_16); + + pPciAgent->p2pIObase |= (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; + + pPciAgent->p2pIOLimit |= (pciData & PRBU_IO_UPP_LIMIT_MASK); + + break; + } + + /* Read P2P_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, P2P_MEM_BASE_LIMIT); + + pPciAgent->p2pMemBase = (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; + + /* clear low address */ + pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; + + pPciAgent->p2pMemLimit = (pciData & PMBL_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; + + /* Read P2P_PREF_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, P2P_PREF_MEM_BASE_LIMIT); + + pPciAgent->p2pPrefMemBase = (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; + + /* get high address only */ + pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; + + pPciAgent->p2pPrefMemLimit = (pciData & PRMBL_PREF_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; + + switch (pciData & PRMBL_ADD_CAP_MASK) { + case PRMBL_ADD_CAP_32BIT: + + pPciAgent->bPrefMem64 = MV_FALSE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = 0; + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = 0; + + break; + case PRMBL_ADD_CAP_64BIT: + + pPciAgent->bPrefMem64 = MV_TRUE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, + bus, dev, func, + P2P_PREF_BASE_UPPER_32); + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, + bus, dev, func, + P2P_PREF_LIMIT_UPPER_32); + + break; + + } + + } else { /* no bridge */ + + /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); + + pPciAgent->subSysVenID = (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; + pPciAgent->subSysID = (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; + + /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_EXPANSION_ROM_BASE_ADDR_REG); + + if (pciData & PERBAR_EXPROMEN) + pPciAgent->isExpRom = MV_TRUE; + else + pPciAgent->isExpRom = MV_FALSE; + + pPciAgent->expRomAddr = (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; + } + + if (MV_TRUE == pPciAgent->isCapListSupport) { + /* Read PCI_CAPABILTY_LIST_POINTER */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_CAPABILTY_LIST_POINTER); + + pPciAgent->capListPointer = (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; + } + + /* Read PCI_INTERRUPT_PIN_AND_LINE */ + pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_INTERRUPT_PIN_AND_LINE); + + pPciAgent->irqLine = (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; + + pPciAgent->intPin = (MV_PCI_INT_PIN) (pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; + + pPciAgent->minGrant = (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; + pPciAgent->maxLatency = (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; + + mvPciClassNameGet(pPciAgent->baseClassCode, (MV_8 *) pPciAgent->type); + + return MV_OK; +} + +/******************************************************************************* +* pciDetectDeviceBars - Detect a pci device bars +* +* DESCRIPTION: +* This function detects all pci agent bars +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* Detected bars number +* +*******************************************************************************/ +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData, barIndex, detectedBar = 0; + MV_U32 tmpBaseHigh = 0, tmpBaseLow = 0; + MV_U32 pciMaxBars = 0; + + pPciAgent->barsNum = 0; + + /* check if we are bridge */ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS) && (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + pciMaxBars = 2; + else /* no bridge */ + pciMaxBars = 6; + + /* read this device pci bars */ + for (barIndex = 0; barIndex < pciMaxBars; barIndex++) { + /* Read PCI_MEMORY_BAR_BASE_ADDR */ + tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + pPciAgent->pciBar[detectedBar].barOffset = PCI_MEMORY_BAR_BASE_ADDR(barIndex); + + /* check if the bar is 32bit or 64bit bar */ + switch (pciData & PBBLR_TYPE_MASK) { + case PBBLR_TYPE_32BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; + break; + case PBBLR_TYPE_64BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; + break; + } + + /* check if it is memory or IO bar */ + if (pciData & PBBLR_IOSPACE) + pPciAgent->pciBar[detectedBar].barMapping = PCI_IO_BAR; + else + pPciAgent->pciBar[detectedBar].barMapping = PCI_MEMORY_BAR; + + /* if it is memory bar then check if it is prefetchable */ + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) { + if (pciData & PBBLR_PREFETCH_EN) + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; + else + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; + + pPciAgent->pciBar[detectedBar].barBaseLow = pciData & PBBLR_MEM_BASE_MASK; + } else { /* IO Bar */ + + pPciAgent->pciBar[detectedBar].barBaseLow = pciData & PBBLR_IO_BASE_MASK; + } + + pPciAgent->pciBar[detectedBar].barBaseHigh = 0; + + if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) { + barIndex++; + + tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = + mvPciIfConfigRead(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + } + + /* calculating full base address (64bit) */ + pPciAgent->pciBar[detectedBar].barBaseAddr = (MV_U64) pPciAgent->pciBar[detectedBar].barBaseHigh; + + pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; + + pPciAgent->pciBar[detectedBar].barBaseAddr |= (MV_U64) pPciAgent->pciBar[detectedBar].barBaseLow; + + /* get the sizes of the the bar */ + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && + (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) { + /* write oxffffffff to the bar to get the size */ + /* start with sizelow ( original value was saved in tmpBaseLow ) */ + mvPciIfConfigWrite(pciIf, + bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex - 1), 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex - 1)); + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex - 1), tmpBaseLow); + + /* now do the same for BaseHigh */ + + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex), 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeHigh = + mvPciIfConfigRead(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex), tmpBaseHigh); + + if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow) && + (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar */ + + /* we though this was a 64bit bar , and it seems this + was wrong ! so decrement barIndex */ + barIndex--; + continue; + } + + /* calculate the full 64 bit size */ + + if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } else { + + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } + + } else { /* 32bit bar */ + + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex), 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar */ + continue; + } + + /* restore original value */ + mvPciIfConfigWrite(pciIf, bus, dev, func, PCI_MEMORY_BAR_BASE_ADDR(barIndex), tmpBaseLow); + + /* calculate size low */ + + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + else + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + pPciAgent->pciBar[detectedBar].barSize = + (MV_U64) pPciAgent->pciBar[detectedBar].barSizeLow; + + } + + /* we are here ! this means we have already detected a bar for + this device , now move on */ + + detectedBar++; + pPciAgent->barsNum++; + } + + return detectedBar; +} + +/******************************************************************************* +* mvPciClassNameGet - get PCI class name +* +* DESCRIPTION: +* This function returns the PCI class name +* +* INPUT: +* baseClassCode - Base Class Code. +* +* OUTPUT: +* pType - the class name +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) +{ + switch (baseClassCode) { + case 0x0: + strcpy(pType, "Old generation device"); + break; + case 0x1: + strcpy(pType, "Mass storage controller"); + break; + case 0x2: + strcpy(pType, "Network controller"); + break; + case 0x3: + strcpy(pType, "Display controller"); + break; + case 0x4: + strcpy(pType, "Multimedia device"); + break; + case 0x5: + strcpy(pType, "Memory controller"); + break; + case 0x6: + strcpy(pType, "Bridge Device"); + break; + case 0x7: + strcpy(pType, "Simple Communication controllers"); + break; + case 0x8: + strcpy(pType, "Base system peripherals"); + break; + case 0x9: + strcpy(pType, "Input Devices"); + break; + case 0xa: + strcpy(pType, "Docking stations"); + break; + case 0xb: + strcpy(pType, "Processors"); + break; + case 0xc: + strcpy(pType, "Serial bus controllers"); + break; + case 0xd: + strcpy(pType, "Wireless controllers"); + break; + case 0xe: + strcpy(pType, "Intelligent I/O controllers"); + break; + case 0xf: + strcpy(pType, "Satellite communication controllers"); + break; + case 0x10: + strcpy(pType, "Encryption/Decryption controllers"); + break; + case 0x11: + strcpy(pType, "Data acquisition and signal processing controllers"); + break; + default: + strcpy(pType, "Unknown device"); + break; + } + + return MV_OK; + +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.h u-boot-2009.08/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,303 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + Documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvPciUtilsh +#define __INCmvPciUtilsh + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + +/* includes */ +#include "mvCommon.h" +#include "mvSysHwConfig.h" + +#include "pci-if/mvPciIf.h" +#include "pci-if/mvPciIfRegs.h" + +/* PCI base address low bar mask */ +#define PCI_ERROR_CODE 0xffffffff + +#define PCI_BRIDGE_CLASS 0x6 +#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 + +#define P2P_BUSSES_NUM 0x18 +#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C +#define P2P_MEM_BASE_LIMIT 0x20 +#define P2P_PREF_MEM_BASE_LIMIT 0x24 +#define P2P_PREF_BASE_UPPER_32 0x28 +#define P2P_PREF_LIMIT_UPPER_32 0x2C +#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 +#define P2P_EXP_ROM 0x38 + +/* P2P_BUSSES_NUM (PBM) */ + +#define PBM_PRIME_BUS_NUM_OFFS 0 +#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) + +#define PBM_SEC_BUS_NUM_OFFS 8 +#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) + +#define PBM_SUB_BUS_NUM_OFFS 16 +#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) + +#define PBM_SEC_LAT_TMR_OFFS 24 +#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) + +/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ + +#define PIBLSS_IO_BASE_OFFS 0 +#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) + +#define PIBLSS_ADD_CAP_OFFS 0 +#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) + +#define PIBLSS_LOW_ADDR_OFFS 0 +#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) + +#define PIBLSS_HIGH_ADDR_OFFS 12 +#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) + +#define PIBLSS_IO_LIMIT_OFFS 8 +#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) + +#define PIBLSS_SEC_STATUS_OFFS 16 +#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) + +/* P2P_MEM_BASE_LIMIT (PMBL)*/ + +#define PMBL_MEM_BASE_OFFS 0 +#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) + +#define PMBL_MEM_LIMIT_OFFS 16 +#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) + +#define PMBL_LOW_ADDR_OFFS 0 +#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) + +#define PMBL_HIGH_ADDR_OFFS 20 +#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) + +/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ + +#define PRMBL_PREF_MEM_BASE_OFFS 0 +#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) + +#define PRMBL_PREF_MEM_LIMIT_OFFS 16 +#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin->addrWin.baseLow; + pexBar.addrWin.size = addrDecWin->addrWin.size; + pexBar.enable = MV_TRUE; + + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /******************************************************************************/ + /* DRAM bar */ + /******************************************************************************/ + + bar = PEX_DRAM_BAR; + pexBar.addrWin.size = 0; + + for (target = SDRAM_CS0; target < MV_DRAM_MAX_CS; target++) { + addrDecWin = &addrWinMap[target]; + if ((addrDecWin->enable == MV_FALSE) && (target != SDRAM_CS0)) + continue; + + if (addrDecWin->enable == MV_TRUE) { + /* the base is the base of DRAM CS0 always */ + if (SDRAM_CS0 == target) { + pexBar.addrWin.baseHigh = addrDecWin->addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin->addrWin.baseLow; + } + + /* increment the bar size to be the sum of the size of all + ** DRAM chips selecs */ + pexBar.addrWin.size += addrDecWin->addrWin.size; + + /* set a Pex window for this target ! + ** DRAM CS always will have a Pex Window , and is not a + ** part of the priority table */ + mvOsMemcpy(&pexWin.winInfo, addrDecWin, sizeof(MV_UNIT_WIN_INFO)); + + /* we disable the windows at first because we are not + ** sure that it is witihin bar boundries */ + pexWin.winInfo.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinWrite(pexIf, pexCurrWin++, &pexWin)) { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + } + + /* check if the size of the bar is illeggal */ + if (!MV_IS_POWER_OF_2(pexBar.addrWin.size)) { + /* try to get a good size */ + pexBar.addrWin.size = 1 << (mvLog2(pexBar.addrWin.size) + 1); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf, bar, &pexBar.addrWin)) { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n", bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } else { + pexBar.enable = MV_TRUE; + + /* configure the bar */ + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* after the bar was configured then we enable the Pex windows */ + for (winNum = 0; winNum < pexCurrWin; winNum++) { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) { + mvOsPrintf("mvPexInit: Can't enable window =%d\n", winNum); + return MV_ERROR; + } + } + } + + /******************************************************************************/ + /* DEVICE bar */ + /******************************************************************************/ + + /* Open the Device BAR for non linux only */ +#ifndef MV_DISABLE_PEX_DEVICE_BAR + + /* then device bar */ + bar = PEX_DEVICE_BAR; + + /* save the starting window */ + pexStartWindow = pexCurrWin; + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = 0xffffffff; + pexBar.addrWin.baseHigh = 0; + maxBase = 0; + + for (target = DEV_TO_TARGET(START_DEV_CS); target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++) { + addrDecWin = &addrWinMap[target]; + + if (addrDecWin->enable == MV_TRUE) { + /* get the minimum base */ + if (addrDecWin->addrWin.baseLow < pexBar.addrWin.baseLow) + pexBar.addrWin.baseLow = addrDecWin->addrWin.baseLow; + + /* get the maximum base */ + if (addrDecWin->addrWin.baseLow > maxBase) { + maxBase = addrDecWin->addrWin.baseLow; + sizeOfMaxBase = addrDecWin->addrWin.size; + } + + /* search in the priority table for this target */ + for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; winIndex++) { + if (pexDevBarPrioTable[winIndex] != target) { + continue; + } else if (pexDevBarPrioTable[winIndex] == target) { + /*found it */ + /* if the index of this target in the prio table is valid + ** then we set the Pex window for this target, a valid index is + ** an index that is lower than the number of the windows that + ** was not configured yet */ + + /* we subtract 2 always because the default and expantion + ** rom windows are always configured */ + if (pexCurrWin < PEX_MAX_TARGET_WIN - 2) { + /* set a Pex window for this target ! */ + mvOsMemcpy(&pexWin.winInfo, addrDecWin, + sizeof(MV_UNIT_WIN_INFO)); + + /* we disable the windows at first because we are not + ** sure that it is witihin bar boundries */ + pexWin.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != + mvPexTargetWinWrite(pexIf, pexCurrWin++, &pexWin)) { + mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); + return MV_ERROR; + } + } + } + } + } + } + + pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; + pexBar.enable = MV_TRUE; + + /* check if the size of the bar is illegal */ + if (!MV_IS_POWER_OF_2(pexBar.addrWin.size)) { + /* try to get a good size */ + pexBar.addrWin.size = 1 << (mvLog2(pexBar.addrWin.size) + 1); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf, bar, &pexBar.addrWin)) { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n", bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } else { + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* now enable the windows */ + for (winNum = pexStartWindow; winNum < pexCurrWin; winNum++) { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", winNum); + return MV_ERROR; + } + } + } + +#endif + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinWrite +* +* DESCRIPTION: +* Set PEX to peripheral target address window BAR +* +* INPUT: +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PEX BAR target window was set correctly, +* MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PEX target window). +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinWrite(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pexWin) +{ + MV_U32 baseReg, sizeReg; + PEX_WIN_REG_INFO winRegInfo; + MV_UNIT_WIN_INFO *pAddrDecWin = &pexWin->winInfo; + + if (winNum >= PEX_MAX_TARGET_WIN) { + mvOsPrintf("mvPexTargetWinWrite: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + if (MV_TRUE == pAddrDecWin->enable) { + /* 1) Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf, winNum, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvPexTargetWinWrite: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_FALSE == pexIsWinWithinBar(pexIf, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvPexTargetWinWrite: Win %d should be in bar boundries\n", winNum); + return MV_BAD_PARAM; + } + + /* 3) Check if size is a power of 2. */ + if (!MV_IS_POWER_OF_2(pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvPexTargetWinWrite: Size is not a power of 2.\n"); + return MV_BAD_PARAM; + } + } + + /* read base register */ + if (winRegInfo.baseLowRegOffs) + baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + else + baseReg = 0; + + if (winRegInfo.sizeRegOffs) + sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + else + sizeReg = 0; + + sizeReg = (pAddrDecWin->addrWin.size / PXWCR_SIZE_ALIGNMENT - 1) << PXWCR_SIZE_OFFS; + baseReg = pAddrDecWin->addrWin.baseLow & PXWBR_BASE_MASK; + + /* enable\disable */ + if (MV_TRUE == pAddrDecWin->enable) + sizeReg |= PXWCR_WIN_EN; + else + sizeReg &= ~PXWCR_WIN_EN; + + /* clear bit location */ + sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; + + /* set bar Mapping */ + if (pexWin->targetBar == 1) + sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; + else if (pexWin->targetBar == 2) + sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; + + /* set attributes */ + sizeReg &= ~PXWCR_ATTRIB_MASK; + sizeReg |= pAddrDecWin->attrib << PXWCR_ATTRIB_OFFS; + /* set target ID */ + sizeReg &= ~PXWCR_TARGET_MASK; + sizeReg |= pAddrDecWin->targetId << PXWCR_TARGET_OFFS; + + /* 3) Write to address decode Base Address Register */ + if (winRegInfo.baseLowRegOffs) + MV_REG_WRITE(winRegInfo.baseLowRegOffs, baseReg); + + /* write size reg */ + if (winRegInfo.sizeRegOffs) { + if ((MV_PEX_WIN_DEFAULT == winNum) || (MV_PEX_WIN_EXP_ROM == winNum)) { + /* clear size because there is no size field */ + sizeReg &= ~PXWCR_SIZE_MASK; + /* clear enable because there is no enable field */ + sizeReg &= ~PXWCR_WIN_EN; + } + MV_REG_WRITE(winRegInfo.sizeRegOffs, sizeReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRead +* +* DESCRIPTION: +* Get the PEX to peripheral target address window BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PEX target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRead(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pexWin) +{ + MV_U32 sizeReg, baseReg; + MV_U32 sizeRegVal; + PEX_WIN_REG_INFO winRegInfo; + MV_UNIT_WIN_INFO *pAddrDecWin = &pexWin->winInfo; + + /* Parameter checking */ + if (winNum >= PEX_MAX_TARGET_WIN) { + mvOsPrintf("mvPexTargetWinRead: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* read base register */ + if (winRegInfo.baseLowRegOffs) + baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + else + baseReg = 0; + + /* read size reg */ + if (winRegInfo.sizeRegOffs) + sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + else + sizeReg = 0; + + /* Extract size */ + sizeRegVal = (sizeReg & PXWCR_SIZE_MASK) >> PXWCR_SIZE_OFFS; + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * PXWCR_SIZE_ALIGNMENT; + /* Extract base address */ + pAddrDecWin->addrWin.baseLow = baseReg & PXWBR_BASE_MASK; + pAddrDecWin->addrWin.baseHigh = 0; + + if (sizeReg & PXWCR_WIN_EN) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + +#if 0 + if (-1 == pAddrDecWin->addrWin.size) + return MV_ERROR; +#endif + + /* get target bar */ + if ((sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1) + pexWin->targetBar = 1; + else if ((sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR2) + pexWin->targetBar = 2; + + /* attrib and targetId */ + pAddrDecWin->attrib = (sizeReg & PXWCR_ATTRIB_MASK) >> PXWCR_ATTRIB_OFFS; + pAddrDecWin->targetId = (sizeReg & PXWCR_TARGET_MASK) >> PXWCR_TARGET_OFFS; + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinEnable - Enable/disable a PEX BAR window +* +* DESCRIPTION: +* This function enable/disable a PEX BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PEX accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf, MV_U32 winNum, MV_BOOL enable) +{ + MV_PEX_DEC_WIN pexWin; + PEX_WIN_REG_INFO winRegInfo; + MV_UNIT_WIN_INFO *addrDecWin = &pexWin.winInfo; + + /* Parameter checking */ + if (winNum >= PEX_MAX_TARGET_WIN) { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* if the address windows is disabled , we only disable the appropriare + ** pex window and ignore other settings */ + if (MV_FALSE == enable) { + /* this is not relevant to default and expantion rom windows */ + if (winRegInfo.sizeRegOffs) { + if ((MV_PEX_WIN_DEFAULT != winNum) && (MV_PEX_WIN_EXP_ROM != winNum)) + MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } else { + if (MV_OK != mvPexTargetWinRead(pexIf, winNum, &pexWin)) { + mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinRead Failed\n"); + return MV_ERROR; + } + + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf, winNum, &addrDecWin->addrWin)) { + mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_FALSE == pexIsWinWithinBar(pexIf, &addrDecWin->addrWin)) { + mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", winNum); + return MV_BAD_PARAM; + } + + /* this is not relevant to default and expantion rom windows */ + if (winRegInfo.sizeRegOffs) { + if ((MV_PEX_WIN_DEFAULT != winNum) && (MV_PEX_WIN_EXP_ROM != winNum)) + MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemap - Set PEX to target address window remap. +* +* DESCRIPTION: +* The PEX interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pexIf - PEX interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, MV_PEX_REMAP_WIN *pAddrWin) +{ + PEX_WIN_REG_INFO winRegInfo; + + if (MV_PEX_WIN_DEFAULT == winNum) { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) { + mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d." + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pexIf, winNum, pAddrWin->addrWin.baseLow, pAddrWin->addrWin.size); + return MV_ERROR; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != winRegInfo.remapHighRegOffs) + MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); + + if (pAddrWin->enable == MV_TRUE) + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs, PXWRR_REMAP_EN); + else + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs, PXWRR_REMAP_EN); + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemapEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + + if (MV_PEX_WIN_DEFAULT == winNum) { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", winNum); + return MV_BAD_PARAM; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + if (enable == MV_TRUE) + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs, PXWRR_REMAP_EN); + else + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs, PXWRR_REMAP_EN); + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarSet - Set PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *pAddrWin) +{ + MV_U32 regBaseLow; + MV_U32 regSize, sizeToReg; + + /* check parameters */ + if (barNum >= PEX_MAX_BARS) { + mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (pAddrWin->addrWin.size == 0) { + mvOsPrintf("mvPexBarSet: Size zero is illegal\n"); + return MV_BAD_PARAM; + } + + /* Check if the window complies with PEX spec */ + if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, pAddrWin->addrWin.size)) { + mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested bar overlaps with current bars */ + if (MV_TRUE == pexBarOverlapDetect(pexIf, barNum, &pAddrWin->addrWin)) { + mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = (pAddrWin->addrWin.size / PXBCR_BAR_SIZE_ALIGNMENT) - 1; + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) { /* internal registers have no size */ + regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf, barNum)); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) { + mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n", barNum); + return MV_BAD_PARAM; + } + + regSize &= ~PXBCR_BAR_SIZE_MASK; + regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS); + MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf, barNum), regSize); + } + + /* set size */ + /* Read base address low */ + regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE(barNum))); + + /* clear current base */ + if (PEX_INTER_REGS_BAR == barNum) { + regBaseLow &= ~PXBIR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); + } else { + regBaseLow &= ~PXBR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); + } + + /* if we had a previous value that contain the bar type (MeM\IO), we want to + ** restore it */ + regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; + + /* write base low */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE(barNum)), regBaseLow); + + if (pAddrWin->addrWin.baseHigh != 0) { + /* Read base address high */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE_HIGH(barNum)), + pAddrWin->addrWin.baseHigh); + } + + /* lastly enable the Bar */ + if (pAddrWin->enable == MV_TRUE) { + if (PEX_INTER_REGS_BAR != barNum) { /* internal registers are enabled always */ + MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf, barNum), PXBCR_BAR_EN); + } + } else if (MV_FALSE == pAddrWin->enable) { + if (PEX_INTER_REGS_BAR != barNum) { /* internal registers are enabled always */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf, barNum), PXBCR_BAR_EN); + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarGet - Get PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *pAddrWin) +{ + if (barNum >= PEX_MAX_BARS) { + mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + /* read base low */ + pAddrWin->addrWin.baseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE(barNum))); + + if (PEX_INTER_REGS_BAR == barNum) + pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; + else + pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; + + /* read base high */ + pAddrWin->addrWin.baseHigh = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE_HIGH(barNum))); + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) { /* internal registers have no size */ + pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf, barNum)); + /* check if enable or not */ + if (pAddrWin->addrWin.size & PXBCR_BAR_EN) + pAddrWin->enable = MV_TRUE; + else + pAddrWin->enable = MV_FALSE; + + /* now get the size */ + pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; + pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; + pAddrWin->addrWin.size = (pAddrWin->addrWin.size + 1) * PXBCR_BAR_SIZE_ALIGNMENT; + } else { /* PEX_INTER_REGS_BAR */ + pAddrWin->addrWin.size = INTER_REGS_SIZE; + pAddrWin->enable = MV_TRUE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) +{ + MV_PEX_BAR pexBar; + + if (barNum >= PEX_MAX_BARS) { + mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (PEX_INTER_REGS_BAR == barNum) { + if (MV_TRUE == enable) + return MV_OK; + else + return MV_ERROR; + } + + if (MV_FALSE == enable) { + /* disable bar and quit */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf, barNum), PXBCR_BAR_EN); + return MV_OK; + } + + /* else */ + if (mvPexBarGet(pexIf, barNum, &pexBar) != MV_OK) { + mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); + return MV_ERROR; + } + + if (MV_TRUE == pexBar.enable) { + /* it is already enabled !!! */ + return MV_OK; + } + + /* else enable the bar */ + pexBar.enable = MV_TRUE; + if (mvPexBarSet(pexIf, barNum, &pexBar) != MV_OK) { + mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); + return MV_ERROR; + } + + return MV_OK; +} + +/******************************************************************************* +* pexWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 win; + MV_PEX_DEC_WIN pexWin; + + for (win = 0; win < PEX_MAX_TARGET_WIN - 2; win++) { + /* don't check our target or illegal targets */ + if (winNum == win) + continue; + + /* Get window parameters */ + if (MV_OK != mvPexTargetWinRead(pexIf, win, &pexWin)) { + mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", win); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == pexWin.winInfo.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &pexWin.winInfo.addrWin)) { + mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", winNum, win); + return MV_TRUE; + } + } + return MV_FALSE; +} + +/******************************************************************************* +* pexIsWinWithinBar - Detect if address is within PEX bar boundries +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR addrDecWin; + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) { + mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled bars */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) + return MV_TRUE; + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, MV_U32 barNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR barDecWin; + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + /* don't check our target or illegal targets */ + if (barNum == bar) + continue; + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) { + mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* don't check disabled bars */ + if (barDecWin.enable == MV_FALSE) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &barDecWin.addrWin)) { + mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", barNum, bar); + return MV_TRUE; + } + } + return MV_FALSE; +} + +/******************************************************************************* +* pexBarIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PEX spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) +{ + /* PCI spec restrict BAR base to be aligned to BAR size */ + if (MV_IS_NOT_ALIGN(baseLow, size)) + return MV_ERROR; + else + return MV_TRUE; + + return MV_TRUE; +} + +/******************************************************************************* +* pexBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PEX BARs registers offsets are inconsecutive. +* This function gets a PEX BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - The PEX BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum, PEX_WIN_REG_INFO *pWinRegInfo) +{ + if ((winNum >= 0) && (winNum <= 3)) { + pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf, winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf, winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf, winNum); + pWinRegInfo->remapHighRegOffs = 0; + } else if ((winNum >= 4) && (winNum <= 5)) { + pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf, winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf, winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf, winNum); + pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf, winNum); + } else if (MV_PEX_WIN_DEFAULT == winNum) { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = 0; + pWinRegInfo->remapHighRegOffs = 0; + } else if (MV_PEX_WIN_EXP_ROM == winNum) { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); + pWinRegInfo->remapHighRegOffs = 0; + } + + return MV_OK; +} + +/******************************************************************************* +* pexBarNameGet - Get the string name of PEX BAR. +* +* DESCRIPTION: +* This function get the string name of PEX BAR. +* +* INPUT: +* bar - PEX bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PEX BAR. +* +*******************************************************************************/ +const MV_8 *pexBarNameGet(MV_U32 bar) +{ + switch (bar) { + case PEX_INTER_REGS_BAR: + return "Internal Regs Bar0...."; + case PEX_DRAM_BAR: + return "DRAM Bar1............."; + case PEX_DEVICE_BAR: + return "Devices Bar2.........."; + default: + return "Bar unknown"; + } +} + +#if 0 +/******************************************************************************* +* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar, winNum; + + for (pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++) { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) + continue; + mvOsOutput("\n"); + mvOsOutput("PEX%d:\n", pexIf); + mvOsOutput("-----\n"); + + mvOsOutput("\nPex Bars \n\n"); + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + memset(&pexBar, 0, sizeof(MV_PEX_BAR)); + + mvOsOutput("%s ", pexBarNameGet(bar)); + + if (mvPexBarGet(pexIf, bar, &pexBar) == MV_OK) { + if (pexBar.enable) { + mvOsOutput("base %08x, ", pexBar.addrWin.baseLow); + mvSizePrint(pexBar.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + mvOsOutput("\nPex Decode Windows\n\n"); + + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) { + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvPexTargetWinGet(pexIf, winNum, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("default win - "); + + if (mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("Expansion ROM - "); + + if (mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + } +} + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPex.c u-boot-2009.08/board/marvell/mv_hal/pex/mvPex.c --- u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPex.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pex/mvPex.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,1109 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysPexConfig.h" +#include "mvPexRegs.h" +/* #include "pci-if/mvPciIf.h" */ +#include "mvPex.h" + +/* #define MV_DEBUG */ +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_PEX_HAL_DATA pexHalData[MV_PEX_MAX_IF]; + +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_PEX_HAL_DATA *halData) +{ + MV_PEX_MODE pexMode; + MV_U32 regVal; + MV_U32 status; + MV_U16 ctrlModel, phyRegVal; + + mvOsMemcpy(&pexHalData[pexIf], halData, sizeof(MV_PEX_HAL_DATA)); + + /* First implement Guideline (GL# PCI Express-2) Wrong Default Value */ + /* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */ + /* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */ + ctrlModel = pexHalData[pexIf].ctrlModel; + if ((ctrlModel != MV_1281_DEV_ID) && + (ctrlModel != MV_6281_DEV_ID) && + (ctrlModel != MV_6282_DEV_ID) && + (ctrlModel != MV_6280_DEV_ID) && + (ctrlModel != MV_6192_DEV_ID) && + (ctrlModel != MV_6190_DEV_ID) && + (ctrlModel != MV_6180_DEV_ID) && + (ctrlModel != MV_6183_DEV_ID) && + (ctrlModel != MV_6183L_DEV_ID) && + (ctrlModel != MV_78100_DEV_ID) && + (ctrlModel != MV_78200_DEV_ID) && + (ctrlModel != MV_76100_DEV_ID) && + (ctrlModel != MV_6323_DEV_ID) && + (ctrlModel != MV_6322_DEV_ID) && + (ctrlModel != MV_6321_DEV_ID) && + (ctrlModel != MV_78XX0_DEV_ID) && + (ctrlModel != MV_6510_DEV_ID) && + (ctrlModel != MV_6530_DEV_ID) && + (ctrlModel != MV_6550_DEV_ID) && + (ctrlModel != MV_6560_DEV_ID) && + (ctrlModel != MV_6710_DEV_ID) && + (ctrlModel != MV_78130_DEV_ID) && + (ctrlModel != MV_78160_DEV_ID) && + (ctrlModel != MV_78230_DEV_ID) && + (ctrlModel != MV_78260_DEV_ID) && + (ctrlModel != MV_78460_DEV_ID) && + (ctrlModel != MV_78000_DEV_ID)) { + /* Read current value of TXAMP */ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80820000); /* Write the read command */ + + regVal = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); /* Extract the data */ + + /* Prepare new data for write */ + regVal &= ~0x7; /* Clear bits [2:0] */ + regVal |= 0x4; /* Set the new value */ + regVal &= ~0x80000000; /* Set "write" command */ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */ + } else { + /* Implement 1.0V termination GL for 88F1281 device only */ + /* BIT0 - Common mode feedback */ + /* BIT3 - TxBuf, extra drive for 1.0V termination */ + if (ctrlModel == MV_1281_DEV_ID) { + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80860000); /* Write the read command */ + regVal = MV_REG_READ(0x41b00); /* Extract the data */ + regVal |= (BIT0 | BIT3); + regVal &= ~0x80000000; /* Set "write" command */ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */ + + MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */ + regVal = MV_REG_READ(0x31b00); /* Extract the data */ + regVal |= (BIT0 | BIT3); + regVal &= ~0x80000000; /* Set "write" command */ + MV_REG_WRITE(0x31b00, regVal); /* Write the write command */ + } + } + if ((ctrlModel == MV_6281_DEV_ID) || + (ctrlModel == MV_6282_DEV_ID) || + (ctrlModel == MV_6280_DEV_ID) || + (ctrlModel == MV_6192_DEV_ID) || + (ctrlModel == MV_6190_DEV_ID) || + (ctrlModel == MV_6180_DEV_ID)) { + regVal = MV_REG_READ(0x100e4); /* This register currently doesn't appear in the FS */ + regVal |= 0x3 << 25; + MV_REG_WRITE(0x100e4, regVal); + } + + if (ctrlModel == MV_6282_DEV_ID) { + mvPexPhyRegRead(pexIf, 0x92, &phyRegVal); + phyRegVal &= ~(0x80F0); + phyRegVal |= 0x8080; + mvPexPhyRegWrite(pexIf, 0x92, phyRegVal); + } else if ((ctrlModel == MV_6510_DEV_ID) || + (ctrlModel == MV_6530_DEV_ID) || (ctrlModel == MV_6550_DEV_ID) || (ctrlModel == MV_6560_DEV_ID)) { + regVal = MV_REG_READ(0x100e4); /* This register currently doesn't appear in the FS */ + regVal |= 0x3 << 25; + MV_REG_WRITE(0x100e4, regVal); + mvPexPhyRegRead(pexIf, 0x92, &phyRegVal); + phyRegVal &= ~(0x80F0); + phyRegVal |= 0x8080; + mvPexPhyRegWrite(pexIf, 0x92, phyRegVal); + } + + if (mvPexModeGet(pexIf, &pexMode) != MV_OK) { + mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n", pexMode.pexType); + return MV_ERROR; + } + + /* Check that required PEX type is the one set in reset time */ + if (pexType != pexMode.pexType) { + /* No Link. Shut down the Phy */ + mvPexPhyPowerDown(pexIf); + mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n", pexType, pexMode.pexType); + return MV_ERROR; + } + + if (MV_PEX_ROOT_COMPLEX == pexType) { + mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf)); + mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf)); + + /* Local device master Enable */ + mvPexMasterEnable(pexIf, MV_TRUE); + + /* Local device slave Enable */ + mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf), mvPexLocalDevNumGet(pexIf), MV_TRUE); + /* Interrupt disable */ + status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND)); + status |= PXSAC_INT_DIS; + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status); + } + + /* now wait 500 ms to be sure the link is valid (spec compliant) */ + mvOsDelay(500); + /* Check if we have link */ + if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) { + /*mvOsPrintf("PEX%d interface detected no Link.\n", pexIf);*/ + return MV_NO_SUCH; + } +#if 0 + if (MV_PEX_WITDH_X1 == pexMode.pexWidth) + mvOsPrintf("PEX%d interface detected Link X1\n", pexIf); + else + mvOsPrintf("PEX%d interface detected Link X4\n", pexIf); +#endif +#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT + mvPexVrtBrgInit(pexIf); +#endif + return MV_OK; +} + +/******************************************************************************* +* mvPexModeGet - Get Pex Mode +* +* DESCRIPTION: +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* pexMode - Pex mode structure +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_U32 mvPexModeGet(MV_U32 pexIf, MV_PEX_MODE *pexMode) +{ + MV_U32 pexData; + + if (pexIf >= MV_PEX_MAX_IF) + return MV_BAD_PARAM; +#if 0 /* maen - disabled because there is a conflict with SysPexInit + sysPexInit need pexMode, however pexHalData[pexIf].maxPexIf is needed in mvPexModeGe */ + */ + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) { + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + } +#endif + + pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); + + switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) { + case PXCR_DEV_TYPE_CTRL_CMPLX: + pexMode->pexType = MV_PEX_ROOT_COMPLEX; + break; + case PXCR_DEV_TYPE_CTRL_POINT: + pexMode->pexType = MV_PEX_END_POINT; + break; + + } + + /* Check if we have link */ + if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) { + pexMode->pexLinkUp = MV_FALSE; + + /* If there is no link, the auto negotiation data is worthless */ + pexMode->pexWidth = MV_PEX_WITDH_INVALID; + } else { + pexMode->pexLinkUp = MV_TRUE; + + /* We have link. The link width is now valid */ + pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); + pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> PXLCSR_NEG_LNK_WDTH_OFFS); + } + + return MV_OK; +} + +/* PEX configuration space read write */ + +/******************************************************************************* +* mvPexConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPexConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigRead(pexIf, bus, dev, func, regOff); +} + +MV_U32 mvPexHwConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev, localBus; + + if (pexIf >= MV_PEX_MAX_IF) + return 0xFFFFFFFF; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) { + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n", pexIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PEX_DEVICES) { + DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); + return 0xFFFFFFFF; + } + + if (func >= MAX_PEX_FUNCS) { + DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); + return 0xFFFFFFFF; + } + + if (bus >= MAX_PEX_BUSSES) { + DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); + return MV_ERROR; + } + + DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", + pexIf, bus, dev, func, regOff)); + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + /* Speed up the process. In case on no link, return MV_ERROR */ + if ((dev != localDev) || (bus != localBus)) { + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + return MV_ERROR; + } + + /* in PCI Express we have only one device number */ + /* and this number is the first number we encounter + else that the localDev */ + /* spec pex define return on config read/write on any device */ + if (bus == localBus) { + if (localDev == 0) { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1) && (dev != localDev)) + return MV_ERROR; + } else { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0) && (dev != localDev)) + return MV_ERROR; + } + if (func != 0) /* i.e bridge */ + return MV_ERROR; + } + + /* Creating PEX address to be passed */ + pexData = (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |= (((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + + pexData |= PXCAR_CONFIG_EN; + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ", pexData)); + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if (pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + return MV_ERROR; + + /* cleaning Master Abort */ + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), PXSAC_MABORT); +#if 0 + /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ + /* This guideline is relevant for all devices except of the following devices: + 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above + 88F6183 A0 and above, 88F6183L */ + ctrlModel = pexHalData[pexIf].ctrlModel; + if (((dev != localDev) || (bus != localBus)) && + (!(MV_5281_DEV_ID == ctrlModel) && + !((MV_5181_DEV_ID == ctrlModel) && (mvCtrlRevGet() >= MV_5181L_A0_REV)) && + !(MV_1281_DEV_ID == ctrlModel) && + !(MV_6183_DEV_ID == ctrlModel) && + !(MV_6183L_DEV_ID == ctrlModel) && + !(MV_6281_DEV_ID == ctrlModel) && + !(MV_6282_DEV_ID == ctrlModel) && + !(MV_6192_DEV_ID == ctrlModel) && + !(MV_6190_DEV_ID == ctrlModel) && + !(MV_6180_DEV_ID == ctrlModel) && !(MV_6280_DEV_ID == ctrlModel) && !(MV_78XX0_DEV_ID == ctrlModel) + )) { + + /* PCI-Express configuration read work-around */ + + /* we will use one of the Punit (AHBToMbus) windows to access the xbar + and read the data from there */ + /* + Need to configure the 2 free Punit (AHB to MBus bridge) + address decoding windows: + Configure the flash Window to handle Configuration space requests + for PEX0/1: + 1. write 0x7931/0x7941 to the flash window and the size, + 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn + 2. write base to flash window + + Configuration transactions from the CPU should write/read the data + to/from address of the form: + addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) + addr[27:24] = extended register number + addr[23:16] = bus number + addr[15:11] = device number + addr[10:8] = function number + addr[7:0] = register number + */ + +#include "ctrlEnv/sys/mvAhbToMbus.h" + { + MV_U32 winNum; + MV_AHB_TO_MBUS_DEC_WIN originWin; + MV_U32 pciAddr = 0; + MV_U32 remapLow = 0, remapHigh = 0; + + /* + We will use DEV_CS2\Flash window for this workarround + */ + + winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); + + /* save remap values if exist */ + if ((1 == winNum) || (0 == winNum)) { + remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); + remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); + + } + + /* save the original window values */ + mvAhbToMbusWinGet(winNum, &originWin); + + if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) { + /* set the window as xbar window */ + if (pexIf) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((originWin.addrWin.size >> 16) - 1)) << 16)); + } else { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((originWin.addrWin.size >> 16) - 1)) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), originWin.addrWin.baseLow); + + /*pciAddr = originWin.addrWin.baseLow; */ + pciAddr = (MV_U32) CPU_MEMIO_UNCACHED_ADDR((MV_U32) originWin.addrWin.baseLow); + + } else { + /* set the window as xbar window */ + if (pexIf) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16) - 1)) << 16)); + } else { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16) - 1)) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), PEX_CONFIG_RW_WA_BASE); + + pciAddr = (MV_U32) CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); + } + + /* remap should be as base */ + if ((1 == winNum) || (0 == winNum)) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum), pciAddr); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum), 0); + + } + + /* extended register space */ + pciAddr |= (bus << 16); + pciAddr |= (dev << 11); + pciAddr |= (func << 8); + pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + + pexData = *(MV_U32 *) pciAddr; + pexData = MV_32BIT_LE(pexData); /* Data always in LE */ + + /* restore the original window values */ + mvAhbToMbusWinSet(winNum, &originWin); + + /* restore original remap values */ + if ((1 == winNum) || (0 == winNum)) { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum), remapLow); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum), remapHigh); + + } + } + } else +#endif + { + /* Read the Data returned in the PEX Data register */ + pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); + + } + + DB(mvOsPrintf("mvPexConfigRead: got : %x \n", pexData)); + + return pexData; + +} + +/******************************************************************************* +* mvPexConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigWrite(pexIf, bus, dev, func, regOff, data); +} + +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev, localBus; + + if (pexIf >= MV_PEX_MAX_IF) + return MV_BAD_PARAM; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) { + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + } + + if (dev >= MAX_PEX_DEVICES) { + mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + } + + if (func >= MAX_PEX_FUNCS) { + mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); + return MV_ERROR; + } + + if (bus >= MAX_PEX_BUSSES) { + mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); + return MV_ERROR; + } + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + /* in PCI Express we have only one device number other than ourselves */ + /* and this number is the first number we encounter + else than the localDev that can be any valid dev number */ + /* pex spec define return on config read/write on any device */ + if (bus == localBus) { + if (localDev == 0) { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1) && (dev != localDev)) + return MV_ERROR; + } else { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0) && (dev != localDev)) + return MV_ERROR; + } + + } + + /* if we are not accessing ourselves , then check the link */ + if ((dev != localDev) || (bus != localBus)) { + /* workarround */ + /* when no link return MV_ERROR */ + + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + return MV_ERROR; + } + + pexData = 0; + + /* Creating PEX address to be passed */ + pexData |= (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |= (((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + pexData |= PXCAR_CONFIG_EN; + + DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", + pexIf, bus, func, dev, regOff, data, pexData)); + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + /* Clear CPU pipe. Important where CPU can perform OOO execution */ + CPU_PIPE_FLUSH; + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if (pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + return MV_ERROR; + + /* Write the Data passed to the PEX Data register */ + MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexMasterEnable - Enable/disale PEX interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pexIf - PEX interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND)); + + if (MV_TRUE == enable) + pexCommandStatus |= PXSAC_MASTER_EN; + else + pexCommandStatus &= ~PXSAC_MASTER_EN; + + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), pexCommandStatus); + + return MV_OK; +} + +/******************************************************************************* +* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PEX slave is allowed to respond to PEX IO space access (bit 0) +* and PEX memory space access (bit 1). +* +* INPUT: +* pexIf - PEX interface number. +* dev - PEX device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 RegOffs; + + /* Parameter checking */ + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + if (dev >= MAX_PEX_DEVICES) { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + + } + + RegOffs = PEX_STATUS_AND_COMMAND; + + pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); + + if (MV_TRUE == enable) + pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); + else + pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); + + mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexLocalBusNumSet - Set PEX interface local bus number. +* +* DESCRIPTION: +* This function sets given PEX interface its local bus number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + if (busNum >= MAX_PEX_BUSSES) { + mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); + return MV_ERROR; + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; + + pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + return MV_OK; +} + +/******************************************************************************* +* mvPexLocalBusNumGet - Get PEX interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + if (pexIf >= MV_PEX_MAX_IF) + return 0xFFFFFFFF; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) { + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n", pexIf); + return 0xFFFFFFFF; + } + } + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_BUS_NUM_MASK; + + return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); +} + +/******************************************************************************* +* mvPexLocalDevNumSet - Set PEX interface local device number. +* +* DESCRIPTION: +* This function sets given PEX interface its local device number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + if (pexIf >= MV_PEX_MAX_IF) + return MV_BAD_PARAM; + + /* Parameter checking */ + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + if (devNum >= MAX_PEX_DEVICES) { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", devNum); + return MV_BAD_PARAM; + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; + + pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + return MV_OK; +} + +/******************************************************************************* +* mvPexLocalDevNumGet - Get PEX interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + /* Parameter checking */ + + if (PEX_DEFAULT_IF != pexIf) { + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", pexIf); + return 0xFFFFFFFF; + } + } + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_DEV_NUM_MASK; + + return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); +} + +MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) +{ + + MV_U32 regAddr; + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); + *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); +} + +MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) +{ + + MV_U32 regAddr; + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (((regOffset & 0x3fff) << 16) | value); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); +} + +/******************************************************************************* +* mvPexActiveStateLinkPMEnable +* +* DESCRIPTION: +* Enable Active Link State Power Management +* +* INPUT: +* pexIf - PEX interface number. +* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 reg; + + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; + if (enable == MV_TRUE) + reg |= PXPMER_L1_ASPM_EN_MASK; + MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); + + /* Enable / Disable L0/1 entry */ + reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) + & ~PXLCSR_ASPM_CNT_MASK; + if (enable == MV_TRUE) + reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); + + return MV_OK; +} + +/******************************************************************************* +* mvPexForceX1 +* +* DESCRIPTION: +* shut down lanes 1-3 if recognize that attached to an x1 end-point +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_U32 mvPexForceX1(MV_U32 pexIf) +{ + MV_U32 regData = 0; + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK); + regData |= PXCR_CONF_LINK_X1; + + MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); + return MV_OK; +} + +/******************************************************************************* +* mvPexIfEnable +* +* DESCRIPTION: +* This function Enables PCI Express interface. +* +* INPUT: +* pexIf - PEX interface number. +* pexType - MV_PEX_ROOT_COMPLEX - root complex device +* MV_PEX_END_POINT - end point device +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexIfEnable(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ +/* TODO: alior: this was asked by CV, bit us reserved in the spec, but causing problems, disabling for now. */ + /* MV_REG_BIT_SET(PEX_CTRL_REG(pexIf), PXCR_AUTO_SPEED_CTRL_MASK); */ + + /* Set pex mode incase S@R not exist */ + if (pexType == MV_PEX_END_POINT) { + MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf), PXCR_DEV_TYPE_CTRL_MASK); + /* Change pex mode in capability reg */ + MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_CAPABILITY_REG), BIT22); + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_CAPABILITY_REG), BIT20); + } else { + MV_REG_BIT_SET(PEX_CTRL_REG(pexIf), PXCR_DEV_TYPE_CTRL_MASK); + } + return; +} + +MV_VOID mvPexPhyPowerDown(MV_U32 pexIf) +{ + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x20800087); + return; +} + +#if 0 +/* These APIs will be removed, OS glue should call the mvCtrlPwerClkxxx() */ +/* functions directly. */ +MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) +{ + if (pexIf >= pexHalData[pexIf].maxPexIf) { + mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); + return MV_FALSE; + } + return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); +} + +MV_VOID mvPexPowerDown(MV_U32 pexIf) +{ + MV_U32 ctrlModel = pexHalData[pexIf].ctrlModel; + + if ((ctrlModel == MV_78XX0_DEV_ID) || + (ctrlModel == MV_76100_DEV_ID) || (ctrlModel == MV_78100_DEV_ID) || (ctrlModel == MV_78200_DEV_ID)) { + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + } else { + MV_REG_WRITE((0x41B00 - (pexIf) * 0x10000), 0x20800087); + } +} +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPex.h u-boot-2009.08/board/marvell/mv_hal/pex/mvPex.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPex.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pex/mvPex.h 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,216 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXH +#define __INCPEXH + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + /* NOTE: not supported in this driver */ + + /* defines */ + /* The number of supported PEX interfaces depend on Marvell controller */ + /* device number. This device number ID is located on the PEX unit*/ + /* configuration header. This creates a loop where calling PEX */ + /* configuration read/write routine results a call to get PEX configuration */ + /* information etc. This macro defines a default PEX interface. This PEX */ + /* interface is sure to exist.*/ +#define PEX_DEFAULT_IF 0 + + /* typedefs */ + /* The Marvell controller supports both root complex and end point devices */ + /* This enumeration describes the PEX type. */ + typedef enum _mvPexType { + MV_PEX_ROOT_COMPLEX, /* root complex device */ + MV_PEX_END_POINT /* end point device */ + } MV_PEX_TYPE; + + typedef enum _mvPexWidth { + MV_PEX_WITDH_X1 = 1, + MV_PEX_WITDH_X2, + MV_PEX_WITDH_X3, + MV_PEX_WITDH_X4, + MV_PEX_WITDH_INVALID + } MV_PEX_WIDTH; + + /* PEX Bar attributes */ + typedef struct _mvPexMode { + MV_PEX_TYPE pexType; + MV_PEX_WIDTH pexWidth; + MV_BOOL pexLinkUp; + } MV_PEX_MODE; + + /* PEX Bar attributes */ + typedef struct _mvPexBar { + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + } MV_PEX_BAR; + + /* PEX Remap Window attributes */ + typedef struct _mvPexRemapWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + + } MV_PEX_REMAP_WIN; + + /* PEX Window attributes */ + typedef struct _mvPexDecWin { + MV_TARGET target; /* Target for addr decode window */ + MV_UNIT_WIN_INFO winInfo; + MV_U32 targetBar; + MV_BOOL slvWrSpltCnt; + } MV_PEX_DEC_WIN; + + /* PEX Wins registers offsets are inconsecutive. This struct describes WIN */ + /* register offsets and its function where its is located. */ + /* Also, PEX address remap registers offsets are inconsecutive. This struct */ + /* describes address remap register offsets */ + typedef struct _pexWinRegInfo { + MV_U32 baseLowRegOffs; + MV_U32 baseHighRegOffs; + MV_U32 sizeRegOffs; + MV_U32 remapLowRegOffs; + MV_U32 remapHighRegOffs; + + } PEX_WIN_REG_INFO; + + typedef struct { + MV_U16 ctrlModel; + MV_U16 maxPexIf; + } MV_PEX_HAL_DATA; + + /* Global Functions prototypes */ + /* mvPexInit - Initialize PEX interfaces */ + MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_PEX_HAL_DATA *halData); + + /* mvPexModeGet - Get Pex If mode */ + MV_U32 mvPexModeGet(MV_U32 pexIf, MV_PEX_MODE *pexMode); + + /* mvPexConfigRead - Read from configuration space */ + MV_U32 mvPexConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff); + + /* mvPexConfigWrite - Write to configuration space */ + MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data); + + /* mvPexMasterEnable - Enable/disale PEX interface master transactions. */ + MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); + + /* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. */ + MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable); + + /* mvPexLocalBusNumSet - Set PEX interface local bus number. */ + MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); + + /* mvPexLocalBusNumGet - Get PEX interface local bus number. */ + MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); + + /* mvPexLocalDevNumSet - Set PEX interface local device number. */ + MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); + + /* mvPexLocalDevNumGet - Get PEX interface local device number. */ + MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); + /* mvPexForceX1 - Force PEX interface to X1 mode. */ + MV_U32 mvPexForceX1(MV_U32 pexIf); + + /* mvPexIsPowerUp - Is PEX interface Power up? */ + MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); + + /* mvPexPowerDown - Power Down */ + MV_VOID mvPexPhyPowerDown(MV_U32 pexIf); + + /* mvPexPhyRegRead - Pex phy read */ + MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); + + /* mvPexPhyRegWrite - Pex phy write */ + MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); + + MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); + /* mvPexIfEnable - Enable Pex interface. */ + MV_VOID mvPexIfEnable(MV_U32 pexIf, MV_PEX_TYPE pexType); + + /* mvPexWinInit - Window init */ + MV_STATUS mvPexWinInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_UNIT_WIN_INFO *addrWinMap); + const MV_8 *pexBarNameGet(MV_U32 bar); + + /* mvPexTargetWinWrite - Window set */ + MV_STATUS mvPexTargetWinWrite(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pexWin); + + /* mvPexTargetWinRead - Window get */ + MV_STATUS mvPexTargetWinRead(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pexWin); + + MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); + MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf, MV_U32 winNum, MV_BOOL enable); + MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *pAddrWin); + MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *pAddrWin); + MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum, PEX_WIN_REG_INFO *pWinRegInfo); + +#ifdef __cplusplus +} +#endif +#endif /* #ifndef __INCPEXH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPexRegs.h u-boot-2009.08/board/marvell/mv_hal/pex/mvPexRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvPexRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pex/mvPexRegs.h 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,923 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXREGSH +#define __INCPEXREGSH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "mvSysPexConfig.h" + +/* defines */ +#define MAX_PEX_DEVICES 32 +#define MAX_PEX_FUNCS 8 +#define MAX_PEX_BUSSES 256 + +/*********************************************************/ +/* PCI Express Configuration Cycles Generation Registers */ +/*********************************************************/ + +#define PEX_CFG_ADDR_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x18F8) +#define PEX_CFG_DATA_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x18FC) + +#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit)%2 * 0x40000) + ((unit)/2 * 0x2000) + 0x1B00) + +/* PCI Express Configuration Address Register */ +/* PEX_CFG_ADDR_REG (PXCAR) */ +#define PXCAR_REG_NUM_OFFS 2 +#define PXCAR_REG_NUM_MAX 0x3F +#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) +#define PXCAR_FUNC_NUM_OFFS 8 +#define PXCAR_FUNC_NUM_MAX 0x7 +#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) +#define PXCAR_DEVICE_NUM_OFFS 11 +#define PXCAR_DEVICE_NUM_MAX 0x1F +#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) +#define PXCAR_BUS_NUM_OFFS 16 +#define PXCAR_BUS_NUM_MAX 0xFF +#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) +#define PXCAR_EXT_REG_NUM_OFFS 24 +#define PXCAR_EXT_REG_NUM_MAX 0xF + +/* in pci express register address is now the legacy register address (8 bits) + with the new extended register address (more 4 bits) , below is the mask of + the upper 4 bits of the full register address */ +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) +#define PXCAR_CONFIG_EN BIT31 + +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) + +/* The traditional PCI spec defined 6-bit field to describe register offset. */ +/* The new PCI Express extend the register offset by an extra 4-bits. */ +/* The below macro assign 10-bit register offset into the apprpreate */ +/* fields in the CFG_ADDR_REG */ +#define PXCAR_REG_OFFS_SET(regOffs) \ + ((regOff & PXCAR_REG_NUM_MASK) | \ + (((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS)) + +/***********************************/ +/* PCI Express Interrupt registers */ +/***********************************/ +#define PEX_CAUSE_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1900) +#define PEX_MASK_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1910) + +#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ +/* of the PCI Express */ +/* PCI Express Interrupt Cause */ +/* PEX_INT_CAUSE_REG (PXICR) */ +/* PEX_INT_MASK_REG */ +/* + NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets + upon an error event occurrence. A write of 0 clears the bit. A write of 1 has + no affect. Bits[24:27} are set and cleared upon reception of interrupt + emulation messages. + Mask bit per cause bit. If a bit is set to 1, the corresponding event is + enabled. Mask does not affect setting of the Interrupt Cause register bits; + it only affects the assertion of the interrupt . */ + +#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction + while master is disabled */ +#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to + PCI Express internal register */ +#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ +#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ +#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ +#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected */ +#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected */ +#define PXICR_FERR_DET BIT10 /* Fatal Error Detected */ +#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication */ +#define PXICR_BIST BIT12 /* PCI-Express BIST activated */ +#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ + +#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ +#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message. */ +#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message */ +#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message. */ +#define PXICR_RCV_CRS BIT19 /* Received CRS completion status */ +#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication */ +#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication */ +#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication */ +#define PXICR_LINK_FAIL BIT23 /* Link Failure indication. */ +#define PXICR_RCV_INTA BIT24 /* IntA status. */ +#define PXICR_RCV_INTB BIT25 /* IntB status. */ +#define PXICR_RCV_INTC BIT26 /* IntC status. */ +#define PXICR_RCV_INTD BIT27 /* IntD status. */ +#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ + +/********************************************/ +/* PCI Express Control and Status Registers */ +/********************************************/ +#define PEX_CTRL_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A00) +#define PEX_LINK_CAPABILITIES_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x6C) +#define PEX_STATUS_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A04) +#define PEX_COMPLT_TMEOUT_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A10) +#define PEX_PWR_MNG_EXT_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A18) +#define PEX_FLOW_CTRL_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A20) +#define PEX_ACK_TMR_4X_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A30) +#define PEX_ACK_TMR_1X_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A40) +#define PEX_TL_CTRL_REG(pexIf) (MV_PEX_IF_REGS_BASE(pexIf) - (pexIf)*0x10000) + +#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A50) +/* PCI Express Control Register */ +/* PEX_CTRL_REG (PXCR) */ + +#define PXCR_CONF_LINK_OFFS 0 +#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control */ +#define PXCR_DEV_TYPE_CTRL_MASK BIT1 +#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_AUTO_SPEED_CTRL_MASK BIT10 +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable */ + +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable */ + +#define PXCR_RSRV1_OFFS 5 +#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) +#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) + +#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master */ +#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) + +#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets */ +#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) + +#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset. */ +#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ +#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling */ +#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling */ + +/* PCI Express Status Register */ +/* PEX_STATUS_REG (PXSR) */ + +#define PXSR_DL_DOWN BIT0 /* DL_Down indication. */ + +#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ +#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) + +#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ +#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) + +#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication */ +#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication */ +#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication */ +#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication */ + +/* PCI Express Completion Timeout Register */ +/* PEX_COMPLT_TMEOUT_REG (PXCTR) */ + +#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ +#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) + +/* PCI Express Power Management Extended Register */ +/* PEX_PWR_MNG_EXT_REG (PXPMER) */ + +#define PXPMER_L1_ASPM_EN_OFFS 1 +#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) + +/* PCI Express Flow Control Register */ +/* PEX_FLOW_CTRL_REG (PXFCR) */ + +#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit + Initial Value. */ +#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) + +#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers + Flow Control Credit Initial Value */ +#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) + +#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control + Credit Initial Value Infinite */ + +#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) + +#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ +#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) + +/* PCI Express Acknowledge Timers (4X) Register */ +/* PEX_ACK_TMR_4X_REG (PXAT4R) */ +#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ +#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) +#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ +#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + +/* PCI Express Acknowledge Timers (1X) Register */ +/* PEX_ACK_TMR_1X_REG (PXAT1R) */ + +#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout + Value for 1X Link */ +#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) + +#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout + Value for 1X */ +#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + +/* PCI Express TL Control Register */ +/* PEX_TL_CTRL_REG (PXTCR) */ + +#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx */ +#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) + +/* PCI Express Debug MAC Control Register */ +/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ + +#define PXDMCR_LINKUP BIT4 + +/**********************************************/ +/* PCI Express Configuration Header Registers */ +/**********************************************/ + +#define PEX_CFG_DIRECT_ACCESS(pexIf, cfgReg) (MV_PEX_IF_REGS_BASE(pexIf) + (cfgReg)) + +#define PEX_DEVICE_AND_VENDOR_ID 0x000 +#define PEX_STATUS_AND_COMMAND 0x004 +#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 +#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) +#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) +#define PEX_BAR0_INTER_REG 0x010 +#define PEX_BAR0_INTER_REG_HIGH 0x014 +#define PEX_BAR1_REG 0x018 +#define PEX_BAR1_REG_HIGH 0x01C +#define PEX_BAR2_REG 0x020 +#define PEX_BAR2_REG_HIGH 0x024 + +#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PEX_CAPABILTY_LIST_POINTER 0x034 +#define PEX_INTERRUPT_PIN_AND_LINE 0x03C + +/* capability list */ +#define PEX_POWER_MNG_CAPABILITY 0x040 +#define PEX_POWER_MNG_STATUS_CONTROL 0x044 + +#define PEX_MSI_MESSAGE_CONTROL 0x050 +#define PEX_MSI_MESSAGE_ADDR 0x054 +#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 +#define PEX_MSI_MESSAGE_DATA 0x05C + +#define PEX_CAPABILITY_REG 0x60 +#define PEX_DEV_CAPABILITY_REG 0x64 +#define PEX_DEV_CTRL_STAT_REG 0x68 +#define PEX_LINK_CAPABILITY_REG 0x6C +#define PEX_LINK_CTRL_STAT_REG 0x70 + +#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 +#define PEX_UNCORRECT_ERR_STAT_REG 0x104 +#define PEX_UNCORRECT_ERR_MASK_REG 0x108 +#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C +#define PEX_CORRECT_ERR_STAT_REG 0x110 +#define PEX_CORRECT_ERR_MASK_REG 0x114 +#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 +#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C +#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 +#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 +#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 + +/* PCI Express Device and Vendor ID Register */ +/* PEX_DEVICE_AND_VENDOR_ID (PXDAVI) */ + +#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ +#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) + +#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ +#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) + +/* PCI Express Command and Status Register */ +/* PEX_STATUS_AND_COMMAND (PXSAC) */ + +#define PXSAC_IO_EN BIT0 /* IO Enable */ +#define PXSAC_MEM_EN BIT1 /* Memory Enable */ +#define PXSAC_MASTER_EN BIT2 /* Master Enable */ +#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ +#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ +#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ +#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ +#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ +#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ +#define PXSAC_SYSERR BIT30 /* Signalled system error */ +#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ + +/* PCI Express Class Code and Revision ID Register */ +/* PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI) */ + +#define PXCCARI_REVID_OFFS 0 /* Revision ID */ +#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) + +#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) + +#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F */ +#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) + +#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class */ +#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) + +#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class */ +#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) + +/* PCI Express BIST, Header Type and Cache Line Size Register */ +/* PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL) */ + +#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) + +#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) + +#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ +#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) + +#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) + +#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ +#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ +#define PXBHTLTCL_BISTCAP_OFFS 31 +#define PXBHTLTCL_BISTCAP_MASK BIT31 +#define PXBHTLTCL_BISTCAP_VAL 0 + +/* PCI Express Subsystem Device and Vendor ID */ +/* PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI) */ + +#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) + +#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) + +/* PCI Express Capability List Pointer Register */ +/* PEX_CAPABILTY_LIST_POINTER (PXCLP) */ + +#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) + +/* PCI Express Interrupt Pin and Line Register */ +/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL) */ + +#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) + +#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A, B, C, D) */ +#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) + +/* PCI Express Power Management Capability Header Register */ +/* PEX_POWER_MNG_CAPABILITY (PXPMC) */ + +#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) + +#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) + +#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version */ +#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) + +#define PXPMC_DSI BIT21 /* Device Specific Initialization */ + +#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ +#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) + +#define PXPMC_D1_SUP BIT25 /* D1 Power Management support */ + +#define PXPMC_D2_SUP BIT26 /* D2 Power Management support */ + +#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support */ +#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) + +/* PCI Express Power Management Control and Status Register */ +/* PEX_POWER_MNG_STATUS_CONTROL (PXPMSC) */ + +#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ +#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) + +#define PXPMSC_PME_EN BIT8 /* PM_PME Message Generation Enable */ + +#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select */ +#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) + +#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ +#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) + +#define PXPMSC_PME_STAT BIT15 /* PME Status */ + +#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ +#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) + +/* PCI Express MSI Message Control Register */ +/* PEX_MSI_MESSAGE_CONTROL (PXMMC) */ + +#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) + +#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) + +#define PXMMC_MSI_EN BIT18 /* MSI Enable */ + +#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ +#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) + +#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ +#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) + +#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ + +/* PCI Express MSI Message Address Register */ +/* PEX_MSI_MESSAGE_ADDR (PXMMA) */ + +#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to + Address[31:2] of the MSI MWr TLP */ +#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) + +/* PCI Express MSI Message Address (High) Register */ +/* PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA) */ + +#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to + Address[63:32] of the MSI MWr TLP */ +#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS) + +/* PCI Express MSI Message Data Register */ +/* PEX_MSI_MESSAGE_DATA (PXMMD) */ + +#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ +#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS) + +/* PCI Express Capability Register */ +/* PEX_CAPABILITY_REG (PXCR) */ + +#define PXCR_CAP_ID_OFFS 0 /* Capability ID */ +#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) + +#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) + +#define PXCR_CAP_VER_OFFS 16 /* Capability Version */ +#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) + +#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type */ +#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) + +#define PXCR_SLOT_IMP BIT24 /* Slot Implemented */ + +#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number */ +#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) + +/* PCI Express Device Capabilities Register */ +/* PEX_DEV_CAPABILITY_REG (PXDCR) */ + +#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported */ +#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) + +#define PXDCR_EP_L0S_ACC_LAT_OFFS 6 /* Endpoint L0s Acceptable Latency */ +#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) + +#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency */ +#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) + +#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present */ +#define PXDCR_ATT_BUT_PRS_MASK BIT12 +#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 + +#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present */ +#define PXDCR_ATT_IND_PRS_MASK BIT13 +#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 + +#define PXDCR_PWR_IND_PRS_OFFS 14 /* Power Indicator Present */ +#define PXDCR_PWR_IND_PRS_MASK BIT14 +#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 + +#define PXDCR_CAP_SPL_VAL_OFFS 18 /* Captured Slot Power Limit + Value */ +#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) + +#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit + Scale */ +#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) + +/* PCI Express Device Control Status Register */ +/* PEX_DEV_CTRL_STAT_REG (PXDCSR) */ + +#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable */ +#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable */ +#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable */ +#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) + Reporting Enable */ +#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering */ + +#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size */ +#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_EN_NS BIT11 /* Enable No Snoop */ + +#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size */ +#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) + +#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected */ +#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected. */ +#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected. */ +#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ +#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved */ + +#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending */ +#define PXDCSR_TRANS_PEND_MASK BIT21 +#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) + +/* PCI Express Link Capabilities Register */ +/* PEX_LINK_CAPABILITY_REG (PXLCR) */ + +#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed */ +#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) + +#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width */ +#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) + +#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support */ +#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) + +#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency */ +#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) + +#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ +#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) + +/* PCI Express Link Control Status Register */ +/* PEX_LINK_CTRL_STAT_REG (PXLCSR) */ + +#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ +#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) + +#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ +#define PXLCSR_RCB_MASK BIT3 +#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) +#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) + +#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ +#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ +#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ +#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ + +#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ +#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) + +#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ +#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) +#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) + +#define PXLCSR_LNK_TRN BIT27 /* Link Training */ + +#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ +#define PXLCSR_SLT_CLK_CFG_MASK BIT28 +#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) +#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) + +/* PCI Express Advanced Error Report Header Register */ +/* PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR) */ + +/* PCI Express Uncorrectable Error Status Register */ +/* PEX_UNCORRECT_ERR_STAT_REG (PXUESR) */ + +/* PCI Express Uncorrectable Error Mask Register */ +/* PEX_UNCORRECT_ERR_MASK_REG (PXUEMR) */ + +/* PCI Express Uncorrectable Error Severity Register */ +/* PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR) */ + +/* PCI Express Correctable Error Status Register */ +/* PEX_CORRECT_ERR_STAT_REG (PXCESR) */ + +/* PCI Express Correctable Error Mask Register */ +/* PEX_CORRECT_ERR_MASK_REG (PXCEMR) */ + +/* PCI Express Advanced Error Capability and Control Register */ +/* PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR) */ + +/* PCI Express Header Log First DWORD Register */ +/* PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR) */ + +/* PCI Express Header Log Second DWORD Register */ +/* PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR) */ + +/* PCI Express Header Log Third DWORD Register */ +/* PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR) */ + +/* PCI Express Header Log Fourth DWORD Register */ +/* PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR) */ + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + +#define MV_PEX_WIN_DEFAULT 6 +#define MV_PEX_WIN_EXP_ROM 7 +#define PEX_MAX_TARGET_WIN 8 + +#define PEX_MAX_BARS 3 +#define PEX_INTER_REGS_BAR 0 +#define PEX_DRAM_BAR 1 +#define PEX_DEVICE_BAR 2 + +/*************************************/ +/* PCI Express BAR Control Registers */ +/*************************************/ +#define PEX_BAR_CTRL_REG(pexIf, bar) (MV_PEX_IF_REGS_BASE(pexIf) + 0x1804 + (bar-1)*4) +#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (MV_PEX_IF_REGS_BASE(pexIf) + 0x180C) + +/* PCI Express BAR Control Register */ +/* PEX_BAR_CTRL_REG (PXBCR) */ + +#define PXBCR_BAR_EN BIT0 +#define PXBCR_BAR_SIZE_OFFS 16 +#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) +#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Expansion ROM BAR Control Register */ +/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ + +#define PXERBCR_EXPROM_EN BIT0 +#define PXERBCR_EXPROMSZ_OFFS 19 +#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) + +/************************************************/ +/* PCI Express Address Window Control Registers */ +/************************************************/ +#define PEX_WIN0_3_CTRL_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x1820 + (winNum) * 0x10) +#define PEX_WIN0_3_BASE_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x1824 + (winNum) * 0x10) +#define PEX_WIN0_3_REMAP_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x182C + (winNum) * 0x10) +#define PEX_WIN4_5_CTRL_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x1860 + (winNum - 4) * 0x20) +#define PEX_WIN4_5_BASE_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x1864 + (winNum - 4) * 0x20) +#define PEX_WIN4_5_REMAP_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x186C + (winNum - 4) * 0x20) +#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf, winNum) \ + (MV_PEX_IF_REGS_BASE(pexIf) + 0x1870 + (winNum - 4) * 0x20) + +#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (MV_PEX_IF_REGS_BASE(pexIf) + 0x18B0) +#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (MV_PEX_IF_REGS_BASE(pexIf) + 0x18C0) +#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (MV_PEX_IF_REGS_BASE(pexIf) + 0x18C4) + +/* PCI Express Window Control Register */ +/* PEX_WIN_CTRL_REG (PXWCR) */ + +#define PXWCR_WIN_EN BIT0 /* Window Enable. */ + +#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR. */ +#define PXWCR_WIN_BAR_MAP_MASK BIT1 +#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) + +#define PXWCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) + +#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) + +#define PXWCR_SIZE_OFFS 16 /* size */ +#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) +#define PXWCR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Window Base Register */ +/* PEX_WIN_BASE_REG (PXWBR) */ + +#define PXWBR_BASE_OFFS 16 /* address[31:16] */ +#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) +#define PXWBR_BASE_ALIGNMENT 0x10000 + +/* PCI Express Window Remap Register */ +/* PEX_WIN_REMAP_REG (PXWRR) */ + +#define PXWRR_REMAP_EN BIT0 +#define PXWRR_REMAP_OFFS 16 +#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) +#define PXWRR_REMAP_ALIGNMENT 0x10000 + +/* PCI Express Window Remap (High) Register */ +/* PEX_WIN_REMAP_HIGH_REG (PXWRHR) */ + +#define PXWRHR_REMAP_HIGH_OFFS 0 +#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) + +/* PCI Express Default Window Control Register */ +/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ + +#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) +#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Control Register */ +/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR) */ + +#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) +#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Remap Register */ +/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR) */ + +#define PXWERRR_REMAP_EN BIT0 +#define PXWERRR_REMAP_OFFS 16 +#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) +#define PXWERRR_REMAP_ALIGNMENT 0x10000 + +/* PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA) */ +/* PCI Express BAR0 Internal Register */ +/* PEX BAR0_INTER_REG (PXBIR) */ + +#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) + +#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ +#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) +#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) + +/* PCI Express BAR0 Internal (High) Register */ +/* PEX BAR0_INTER_REG_HIGH (PXBIRH) */ + +#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ +#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + +#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ +#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB + +/* PCI Express BAR1 Register */ +/* PCI Express BAR2 Register */ +/* PEX BAR1_REG (PXBR) */ +/* PEX BAR2_REG (PXBR) */ + +#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) + +#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ +#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) +#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) + +/* PCI Express BAR1 (High) Register */ +/* PCI Express BAR2 (High) Register */ +/* PEX BAR1_REG_HIGH (PXBRH) */ +/* PEX BAR2_REG_HIGH (PXBRH) */ + +#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ +#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) + +/* PCI Express Expansion ROM BAR Register */ +/* PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR) */ + +#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) + +#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) + +#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) + +#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) + +#ifdef __cplusplus + } +#endif /* __cplusplus */ +#endif /* #ifndef __INCPEXREGSH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvVrtBrgPex.c u-boot-2009.08/board/marvell/mv_hal/pex/mvVrtBrgPex.c --- u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvVrtBrgPex.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pex/mvVrtBrgPex.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,267 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPex.h" + +/* #define MV_DEBUG */ +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +typedef struct { + MV_U32 data; + MV_U32 mask; +} PEX_HEADER_DATA; + +/* local function forwad decleration */ +MV_U32 mvPexHwConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff); +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data); +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); + +PEX_HEADER_DATA configHdr[16] = { + {0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ + {0x00100007, 0x0000ffff}, /*[status register, command register] */ + {0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ + {0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ + {0x00000000, 0x00000000}, /*[base address 0] */ + {0x00000000, 0x00000000}, /*[base address 1] */ + {0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, + secondary bus number, primary bus number] */ + {0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ + {0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ + {0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ + {0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ + {0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ + {0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ + {0x00000000, 0x00000000}, /*[reserved, capability pointer] */ + {0x00000000, 0x00000000}, /*[expansion ROM base address] */ + {0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ +}; + +#define HEADER_WRITE(data, offset) configHdr[offset/4].data = \ + ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ + (data & configHdr[offset/4].mask)) +#define HEADER_READ(offset) configHdr[offset/4].data + +/******************************************************************************* +* mvVrtBrgPexInit - Initialize PEX interfaces +* +* Description: +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) +{ + /* reset PEX tree to recover previous U-boot/Boot configurations */ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + + resetPexConfig(pexIf, localBus, 1); + return MV_OK; +} + +MV_U32 mvPexVrtBrgConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff) +{ + + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_U32 val; + if (bus == localBus) { + if (dev > 1) { + /* on the local device allow only device #0 & #1 */ + return 0xffffffff; + } else if (dev == localDev) { + /* read the memory controller registers */ + return mvPexHwConfigRead(pexIf, bus, dev, func, regOff); + } else { + /* access the virtual brg header */ + return HEADER_READ(regOff); + } + } else if (bus == (localBus + 1)) { + /* access the device behind the virtual bridge */ + if ((dev == localDev) || (dev > 1)) { + return 0xffffffff; + } else { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead(pexIf, bus, 0, func, regOff); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return val; + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead(pexIf, bus, dev, func, regOff); + mvPexLocalDevNumSet(pexIf, localDev); + return val; +} + +MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_STATUS status; + + if (bus == localBus) { + if (dev > 1) { + /* on the local device allow only device #0 & #1 */ + return MV_ERROR; + } else if (dev == localDev) { + /* read the memory controller registers */ + return mvPexHwConfigWrite(pexIf, bus, dev, func, regOff, data); + } else { + /* access the virtual brg header */ + HEADER_WRITE(data, regOff); + return MV_OK; + } + } else if (bus == (localBus + 1)) { + /* access the device behind the virtual bridge */ + if ((dev == localDev) || (dev > 1)) { + return MV_ERROR; + } else { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + /* return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); */ + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite(pexIf, bus, 0, func, regOff, data); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return status; + + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite(pexIf, bus, dev, func, regOff, data); + mvPexLocalDevNumSet(pexIf, localDev); + return status; +} + +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) +{ + MV_U32 tData; + MV_U32 i; + + /* restore the PEX configuration to initialization state */ + /* in case PEX P2P call recursive and reset config */ + tData = mvPexHwConfigRead(pexIf, bus, dev, 0x0, 0x0); + if (tData != 0xffffffff) { + /* agent had been found - check whether P2P */ + tData = mvPexHwConfigRead(pexIf, bus, dev, 0x0, 0x8); + if ((tData & 0xffff0000) == 0x06040000) { /* P2P */ + /* get the sec bus and the subordinate */ + MV_U32 secBus; + tData = mvPexHwConfigRead(pexIf, bus, dev, 0x0, 0x18); + secBus = ((tData >> 8) & 0xff); + + /* now scan on sec bus */ + for (i = 0; i < 0xff; i++) + resetPexConfig(pexIf, secBus, i); + + /* now reset this device */ + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + } + } +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvVrtBrgPex.h u-boot-2009.08/board/marvell/mv_hal/pex/mvVrtBrgPex.h --- u-boot-2009.08.orig/board/marvell/mv_hal/pex/mvVrtBrgPex.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/pex/mvVrtBrgPex.h 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,86 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCVRTBRGPEXH +#define __INCVRTBRGPEXH + +#ifdef __cplusplus +extern "C" { +#endif + + /* Global Functions prototypes */ + /* mvPexInit - Initialize PEX interfaces */ + MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); + + /* mvPexConfigRead - Read from configuration space */ + MV_U32 mvPexVrtBrgConfigRead(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, MV_U32 regOff); + + /* mvPexConfigWrite - Write to configuration space */ + MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +#ifdef __cplusplus +} +#endif +#endif /* #ifndef __INCPEXH */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/ev96122mii.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/ev96122mii.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/ev96122mii.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/ev96122mii.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,213 @@ +#include +/******************************************************************************** +* ev96122mii.c +* +* DESCRIPTION: +* SMI access routines for EV-96122 board +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include + +/* + * For each platform, all we need is + * 1) Assigning functions into + * fgtReadMii : to read MII registers, and + * fgtWriteMii : to write MII registers. + * + * 2) Register Interrupt (Not Defined Yet.) +*/ + +/* + * EV-96122 Specific Definition +*/ + +#define SMI_OP_CODE_BIT_READ 1 +#define SMI_OP_CODE_BIT_WRITE 0 +#define SMI_BUSY 1<<28 +#define READ_VALID 1<<27 + +#ifdef FIREFOX +#define ETHER_SMI_REG 0x10 +#define internalRegBaseAddr 0x80008000 +#define NONE_CACHEABLE 0x00000000 +#define CACHEABLE 0x00000000 +#define SMI_RX_TIMEOUT 1000 +#else +#define ETHER_SMI_REG 0x080810 +#define internalRegBaseAddr 0x14000000 +#define NONE_CACHEABLE 0xa0000000 +#define CACHEABLE 0x80000000 +#define SMI_RX_TIMEOUT 10000000 +#endif + +typedef unsigned int SMI_REG; + +#ifdef LE /* Little Endian */ +#define SHORT_SWAP(X) (X) +#define WORD_SWAP(X) (X) +#define LONG_SWAP(X) ((l64)(X)) + +#else /* Big Endian */ +#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) + +#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ + (((X)&0xff00)<<8)+ \ + (((X)&0xff0000)>>8)+ \ + (((X)&0xff000000)>>24) + +#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ + (((X)&0xff00ULL)<<40)+ \ + (((X)&0xff0000ULL)<<24)+ \ + (((X)&0xff000000ULL)<<8)+ \ + (((X)&0xff00000000ULL)>>8)+ \ + (((X)&0xff0000000000ULL)>>24)+ \ + (((X)&0xff000000000000ULL)>>40)+ \ + (((X)&0xff00000000000000ULL)>>56)) + +#endif + +#define GT_REG_READ(offset, pData) \ +*pData = ( (volatile unsigned int)*((unsigned int *) \ + (NONE_CACHEABLE | internalRegBaseAddr | (offset))) ); \ +*pData = WORD_SWAP(*pData) + +#define GT_REG_WRITE(offset, data) \ +(volatile unsigned int)*((unsigned int *)(NONE_CACHEABLE | \ + internalRegBaseAddr | (offset))) = WORD_SWAP(data) + +typedef enum _bool{false,true} bool; + +/***************************************************************************** +* +* bool etherReadMIIReg (unsigned int portNumber , unsigned int MIIReg, +* unsigned int* value) +* +* Description +* This function will access the MII registers and will read the value of +* the MII register , and will retrieve the value in the pointer. +* Inputs +* portNumber - one of the 2 possiable Ethernet ports (0-1). +* MIIReg - the MII register offset. +* Outputs +* value - pointer to unsigned int which will receive the value. +* Returns Value +* true if success. +* false if fail to make the assignment. +* Error types (and exceptions if exist) +*/ + +GT_BOOL gtBspReadMii (GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value) +{ +SMI_REG smiReg; +unsigned int phyAddr; +unsigned int timeOut = 10; /* in 100MS units */ +int i; + +/* first check that it is not busy */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(smiReg & SMI_BUSY) + { + for(i = 0 ; i < SMI_RX_TIMEOUT ; i++); + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (smiReg & SMI_BUSY); + } +/* not busy */ + + phyAddr = portNumber; + + smiReg = (phyAddr << 16) | (SMI_OP_CODE_BIT_READ << 26) | (MIIReg << 21) | + SMI_OP_CODE_BIT_READ<<26; + + GT_REG_WRITE (ETHER_SMI_REG,*((unsigned int*)&smiReg)); + timeOut = 10; /* initialize the time out var again */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(!(smiReg & READ_VALID)) + { + i=0; + while(i < SMI_RX_TIMEOUT) + { + i++; + } + { + } + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (!(smiReg & READ_VALID)); + } + *value = (unsigned int)(smiReg & 0xffff); + + return true; + + +} + +/***************************************************************************** +* +* bool etherWriteMIIReg (unsigned int portNumber , unsigned int MIIReg, +* unsigned int value) +* +* Description +* This function will access the MII registers and will write the value +* to the MII register. +* Inputs +* portNumber - one of the 2 possiable Ethernet ports (0-1). +* MIIReg - the MII register offset. +* value -the value that will be written. +* Outputs +* Returns Value +* true if success. +* false if fail to make the assignment. +* Error types (and exceptions if exist) +*/ + +GT_BOOL gtBspWriteMii (GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int value) +{ +SMI_REG smiReg; +unsigned int phyAddr; +unsigned int timeOut = 10; /* in 100MS units */ +int i; + +/* first check that it is not busy */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(smiReg & SMI_BUSY) + { + for(i = 0 ; i < SMI_RX_TIMEOUT ; i++); + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (smiReg & SMI_BUSY); + } +/* not busy */ + + phyAddr = portNumber; + + smiReg = 0; /* make sure no garbage value in reserved bits */ + smiReg = smiReg | (phyAddr << 16) | (SMI_OP_CODE_BIT_WRITE << 26) | + (MIIReg << 21) | (value & 0xffff); + + GT_REG_WRITE (ETHER_SMI_REG,*((unsigned int*)&smiReg)); + + return(true); +} + + +void gtBspMiiInit(GT_QD_DEV* dev) +{ + return; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/makefile u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/makefile --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/makefile 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,49 @@ +# makefile - build main object file +# +# modification history +# -------------------- +# 04-15-02,mj created +# +####################################################################### + +DEMONAME = msDiag +WORK_TO_DO = $(DEMONAME).o + +exe : $(WORK_TO_DO) + +# Include common variable definitions +include $(TOOL_DIR)/make.defs + +.PHONY : exe + +QDLIB = $(LIB_DIR)/$(PROJ_NAME).o + +OBJDIRS = $(subst /,\,$(dir $(QDLIB))) + +#CSOURCES = osSem.c ev96122mii.c testApi.c qdSim.c msApiInit.c utils.c vctTest.c +#CSOURCES = osSem.c testApi.c qdSim.c utils.c vctTest.c +CSOURCES = osSem.c testApi.c qdSim.c utils.c vctTest.c msApiMultiInit.c + +COBJECTS = $(CSOURCES:.c=.o) +AOBJECTS = $(ASOURCES:.s=.o) +ifeq ($(OBJECTS),) +OBJECTS = $(COBJECTS) $(AOBJECTS) +endif + +ifeq ($(TARGET_CPU),ARM) +EXTRA_DEFINE += -DFIREFOX +endif + +$(DEMONAME).o : $(OBJECTS) $(QDLIB) + $(LD) $(LDFLAGS) -Map $(DEMONAME).map -o $(DEMONAME).o $(OBJECTS) $(QDLIB) + +$(OBJECTS) : %.o : %.c +.c.o : + $(CC) $(CFLAGS) $(EXTRA_DEFINE) $(EXTRA_INCLUDE) $(ADDED_CFLAGS) -c $< -o $(notdir $@) + +.PHONY : clean +clean : + $(RM) *.o + $(RM) *.map + +#end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/msApiInit.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/msApiInit.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/msApiInit.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/msApiInit.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,115 @@ +#include +/******************************************************************************** +* msApiInit.c +* +* DESCRIPTION: +* MS API initialization routine +* +* DEPENDENCIES: Platform +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" +/* +#define MULTI_ADDR_MODE +#define MANUAL_MODE +*/ + +GT_SYS_CONFIG cfg; +GT_QD_DEV diagDev; +GT_QD_DEV *dev=&diagDev; + + +/* + * Initialize the QuarterDeck. This should be done in BSP driver init routine. + * Since BSP is not combined with QuarterDeck driver, we are doing here. +*/ + +GT_STATUS qdStart(int cpuPort, int useQdSim, int devId) /* devId is used for simulator only */ +{ +GT_STATUS status; + + /* + * Register all the required functions to QuarterDeck Driver. + */ + memset((char*)&cfg,0,sizeof(GT_SYS_CONFIG)); + memset((char*)&diagDev,0,sizeof(GT_QD_DEV)); + + if(useQdSim == 0) /* use EV-96122 */ + { + cfg.BSPFunctions.readMii = gtBspReadMii; + cfg.BSPFunctions.writeMii = gtBspWriteMii; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + gtBspMiiInit(dev); + } + else /* use QuaterDeck Simulator (No QD Device Required.) */ + { + cfg.BSPFunctions.readMii = qdSimRead; + cfg.BSPFunctions.writeMii = qdSimWrite; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + + qdSimInit(devId,0); + } + + cfg.initPorts = GT_TRUE; /* Set switch ports to Forwarding mode. If GT_FALSE, use Default Setting. */ + cfg.cpuPortNum = cpuPort; +#ifdef MANUAL_MODE /* not defined. this is only for sample */ + /* user may want to use this mode when there are two QD switchs on the same MII bus. */ + cfg.mode.scanMode = SMI_MANUAL_MODE; /* Use QD located at manually defined base addr */ + cfg.mode.baseAddr = 0x10; /* valid value in this case is either 0 or 0x10 */ +#else +#ifdef MULTI_ADDR_MODE + cfg.mode.scanMode = SMI_MULTI_ADDR_MODE; /* find a QD in indirect access mode */ + cfg.mode.baseAddr = 1; /* this is the phyAddr used by QD family device. + Valid value are 1 ~ 31.*/ +#else + cfg.mode.scanMode = SMI_AUTO_SCAN_MODE; /* Scan 0 or 0x10 base address to find the QD */ + cfg.mode.baseAddr = 0; +#endif +#endif + if((status=qdLoadDriver(&cfg, dev)) != GT_OK) + { + MSG_PRINT(("qdLoadDriver return Failed\n")); + return status; + } + + MSG_PRINT(("Device ID : 0x%x\n",dev->deviceId)); + MSG_PRINT(("Base Reg Addr : 0x%x\n",dev->baseRegAddr)); + MSG_PRINT(("No of Ports : %d\n",dev->numOfPorts)); + MSG_PRINT(("CPU Ports : %d\n",dev->cpuPortNum)); + + /* + * start the QuarterDeck + */ + if((status=sysEnable(dev)) != GT_OK) + { + MSG_PRINT(("sysConfig return Failed\n")); + return status; + } + + MSG_PRINT(("QuarterDeck has been started.\n")); + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/msApiMultiInit.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/msApiMultiInit.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/msApiMultiInit.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/msApiMultiInit.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,424 @@ +#include +/******************************************************************************** +* msApiInit.c +* +* DESCRIPTION: +* MS API initialization routine for devices supporting Multi Address Mode, +* such as 88E6183. Following setup will be used for this sample code. +* +* ------------------ +* |CPU Ethernet Dev| +* ------------------ +* | +* | +* | 8--------------9 8--------------9 8-------------- +* |----| QD Device 0|------| QD Device 1|-----| QD Device 2| +* -------------- -------------- -------------- +* 0 1 2 ... 7 0 1 2 ... 7 0 1 2 ... 7 +* +* +* Ethernet port of CPU is connected to port 8 of Device 0, +* port 9 of Device 0 is connected to port 8 of Device 1, and +* port 9 of Device 1 is connected to port 8 of Device 2. +* +* Device 0 uses Phy Address 1, +* Device 1 uses Phy Address 2, and +* Device 2 uses Phy Address 3 +* Notes: Phy Address 0 cannot be used in a Multi Chip Address Mode. +* +* Each Switch Device has to be configured to Multi Chip Address Mode. +* For detailed information for Multi Chip Address Mode configuration, +* please refer to your device's Datasheet. +* +* DEPENDENCIES: Platform +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +/* +#define MULTI_ADDR_MODE +#define MANUAL_MODE +*/ + +#define MULTI_ADDR_MODE +#define N_OF_QD_DEVICES 2 /* number of 88E6183 devices connected */ + +#define DEVICE0_ID 1 +#define DEVICE1_ID DEVICE0_ID + 1 +#define DEVICE2_ID DEVICE0_ID + 2 + +#define DEVICE0_PHY_ADDR 0x11 +#define DEVICE1_PHY_ADDR DEVICE0_PHY_ADDR + 1 +#define DEVICE2_PHY_ADDR DEVICE0_PHY_ADDR + 2 + +#define S_CPU_DEVICE DEVICE0_ID + +#define DEVICE0_CPU_PORT 7 +#define DEVICE0_CASCADE_PORT 6 +#define DEVICE1_CPU_PORT 7 +#define DEVICE1_CASCADE_PORT 6 +#define DEVICE2_CPU_PORT 7 +#define DEVICE2_CASCADE_PORT 6 + +extern GT_QD_DEV qddev[4]; + +GT_QD_DEV *qdMultiDev[N_OF_QD_DEVICES] = {0,}; +GT_QD_DEV *qdDev0 = &qddev[1]; +GT_QD_DEV *qdDev1 = NULL; +GT_QD_DEV *qdDev2 = NULL; + +/* + * read mii register - see qdFFmii.c + */ +extern GT_BOOL ffReadMii(GT_QD_DEV* dev, + unsigned int portNumber , + unsigned int MIIReg, unsigned int* value + ); + +/* + * write mii register - see qdFFmii.c + */ +extern GT_BOOL ffWriteMii(GT_QD_DEV* dev, + unsigned int portNumber , + unsigned int MIIReg, + unsigned int value + ); + +GT_STATUS RubyStart(int phyAddr, GT_QD_DEV* d) +{ + GT_STATUS status = GT_FAIL; + GT_SYS_CONFIG cfg; + + memset((char*)&cfg,0,sizeof(GT_SYS_CONFIG)); + MSG_PRINT(("Size of GT_QD_DEV %i\n",sizeof(GT_QD_DEV))); + + if(d == NULL) + { + MSG_PRINT(("Device Structure is NULL.\n")); + return GT_FAIL; + } + + memset((char*)d,0,sizeof(GT_QD_DEV)); + + cfg.BSPFunctions.readMii = ffReadMii; + cfg.BSPFunctions.writeMii = ffWriteMii; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + + cfg.initPorts = GT_TRUE; /* Set switch ports to Forwarding mode. If GT_FALSE, use Default Setting. */ + cfg.cpuPortNum = 10; + + cfg.mode.scanMode = SMI_MULTI_ADDR_MODE; + cfg.mode.baseAddr = phyAddr; /* valid value in this case is either 0 or 0x10 */ + + if((status=qdLoadDriver(&cfg, d)) != GT_OK) + { + MSG_PRINT(("qdLoadDriver return Failed\n")); + return status; + } + + MSG_PRINT(("Device ID : 0x%x\n",d->deviceId)); + MSG_PRINT(("PHY Addr : 0x%x\n",d->phyAddr)); + MSG_PRINT(("Base Addr : 0x%x\n",d->baseRegAddr)); + MSG_PRINT(("CPU Ports : %d\n",d->cpuPortNum)); + MSG_PRINT(("N Ports : %d\n",d->numOfPorts)); + MSG_PRINT(("Device Group : 0x%x\n",d->devName)); + MSG_PRINT(("QDDev : %#x\n",(unsigned long)&d)); + + /* + * start the QuarterDeck + */ + if((status=sysEnable(d)) != GT_OK) + { + MSG_PRINT(("sysConfig return Failed\n")); + return status; + } + + return GT_OK; +} + +GT_STATUS SwStart(int phyAddr, GT_QD_DEV* d) +{ + return RubyStart(phyAddr,d); +} + +GT_QD_DEV* loadDev(GT_QD_DEV* dev, int mode, int phyAddr, int cpuPort, unsigned int cfgMode) +{ + GT_QD_DEV* d = dev; + GT_STATUS status = GT_FAIL; + GT_SYS_CONFIG cfg; + + if((int)dev == -1) + goto printUse; + + memset((char*)&cfg,0,sizeof(GT_SYS_CONFIG)); + + if(d == NULL) + { + d = (GT_QD_DEV*)malloc(sizeof(GT_QD_DEV)); + + if(d == NULL) + { + MSG_PRINT(("Failed to allocate Device Structure\n")); + return NULL; + } + } + + memset((char*)d,0,sizeof(GT_QD_DEV)); + + cfg.BSPFunctions.readMii = ffReadMii; + cfg.BSPFunctions.writeMii = ffWriteMii; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + + cfg.initPorts = GT_TRUE; /* Set switch ports to Forwarding mode. If GT_FALSE, use Default Setting. */ + cfg.cpuPortNum = cpuPort; + cfg.skipInitSetup = (GT_U32)cfgMode; + + switch(mode) + { + case SMI_MANUAL_MODE: /* Use QD located at manually defined base addr */ + case SMI_MULTI_ADDR_MODE: /* Use QD in multi chip address mode */ + cfg.mode.scanMode = mode; + cfg.mode.baseAddr = phyAddr; /* valid value in this case is either 0 or 0x10 */ + break; + case SMI_AUTO_SCAN_MODE: /* Scan 0 or 0x10 base address to find the QD */ + cfg.mode.scanMode = mode; + cfg.mode.baseAddr = 0; + break; + default: + MSG_PRINT(("Unknown Mode %i\n",mode)); + goto printUse; + } + + if((status=qdLoadDriver(&cfg, d)) != GT_OK) + { + MSG_PRINT(("qdLoadDriver return Failed\n")); + goto loadErr; + } + + MSG_PRINT(("Device ID : 0x%x\n",d->deviceId)); + MSG_PRINT(("PHY Addr : 0x%x\n",d->phyAddr)); + MSG_PRINT(("Base Addr : 0x%x\n",d->baseRegAddr)); + MSG_PRINT(("CPU Ports : %d\n",d->cpuPortNum)); + + /* + * start the QuarterDeck + */ + if((status=sysEnable(d)) != GT_OK) + { + MSG_PRINT(("sysConfig return Failed\n")); + goto loadErr; + } + + return d; + +printUse: + MSG_PRINT(("Usage: loadDev(Dev,mode,phyAddr,cpuPort)\n",SMI_AUTO_SCAN_MODE)); + MSG_PRINT(("\tSMI_AUTO_SCAN_MODE : %i\n",SMI_AUTO_SCAN_MODE)); + MSG_PRINT(("\tSMI_MANUAL_MODE : %i\n",SMI_MANUAL_MODE)); + MSG_PRINT(("\tSMI_MULTI_ADDR_MODE : %i\n",SMI_MULTI_ADDR_MODE)); + MSG_PRINT(("Example: loadDev(0,1,0x10,5)\n")); + MSG_PRINT(("for Manual mode, phy base address 0x10, and cpu port 5\n")); + +loadErr: + + if(dev) + return NULL; + + if(d) + free(d); + + return NULL; +} + +/* + * Initialize each Switch Devices. This should be done in BSP driver init routine. + * Since BSP is not combined with QuarterDeck driver, we are doing here. + * This routine will setup Switch Devices according to the above description. +*/ +GT_STATUS qdMultiDevStart() +{ + GT_STATUS status = GT_FAIL; + int cpuPort; + int cascadePort; + int i,j; + + /* + * Create QD Device Structure for each device. + */ + for(i=0; inumOfPorts; j++) + { + if((j == cpuPort) || (j == cascadePort)) + { + if((status=gprtSetInterswitchPort(qdMultiDev[i],j,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetInterswitchPort returned %i (port %i, mode TRUE)\n",status,j)); + break; + } + } + else + { + if((status=gprtSetInterswitchPort(qdMultiDev[i],j,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetInterswitchPort returned %i (port %i, mode FALSE)\n",status,j)); + break; + } + } + + if((status=gprtSetCPUPort(qdMultiDev[i],j,cpuPort)) != GT_OK) + { + MSG_PRINT(("gprtSetCPUPort returned %i\n",status)); + break; + } + } + + /* + 3. Set Cascading Port information (for From_CPU fram) for each device. + */ + MSG_PRINT(("Setting Cascade Port...\n")); + if((status=gsysSetCascadePort(qdMultiDev[i],cascadePort)) != GT_OK) + { + MSG_PRINT(("gsysSetCascadePort returned %i\n",status)); + continue; + } + + /* + 4. Set Device ID (if required) + */ + MSG_PRINT(("Setting Device ID (%i)...\n",DEVICE0_ID+i)); + if((status=gsysSetDeviceNumber(qdMultiDev[i],DEVICE0_ID+i)) != GT_OK) + { + MSG_PRINT(("gsysSetDeviceNumber returned %i\n",status)); + continue; + } + + } + + return GT_OK; + +errorExit: + + /* code will be reached here only if N_OF_QD_DEVICES > 3 */ + for(i=0; i +/******************************************************************************** +* msSample.h +* +* DESCRIPTION: +* Types definitions for Sample program +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __pfTesth +#define __pfTesth + +#ifdef _VXWORKS +#include "vxWorks.h" +#include "logLib.h" +#endif +#include "stdio.h" +#include "stdarg.h" +#include "stdlib.h" +#include "time.h" +#include "string.h" + +#include "msApi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef GT_U32 (*GT_API_VOID) (GT_QD_DEV*); +typedef int (*GT_CMP_FUNC) (void*, int, int); + +typedef GT_STATUS (*GT_API_SET_BOOL) (GT_QD_DEV*, GT_BOOL); +typedef GT_STATUS (*GT_API_GET_BOOL) (GT_QD_DEV*, GT_BOOL*); + +typedef GT_STATUS (*GT_API_SET_U16) (GT_QD_DEV*, GT_U16); +typedef GT_STATUS (*GT_API_GET_U16) (GT_QD_DEV*, GT_U16*); + +typedef GT_STATUS (*GT_API_SET_U32) (GT_QD_DEV*, GT_U32); +typedef GT_STATUS (*GT_API_GET_U32) (GT_QD_DEV*, GT_U32*); + +typedef GT_STATUS (*GT_API_MAC_ADDR) (GT_QD_DEV*, GT_ETHERADDR*); + +typedef GT_STATUS (*GT_API_SET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL); +typedef GT_STATUS (*GT_API_GET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL*); + +typedef GT_STATUS (*GT_API_SET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16); +typedef GT_STATUS (*GT_API_GET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16*); + +typedef GT_STATUS (*GT_API_SET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32); +typedef GT_STATUS (*GT_API_GET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32*); + +typedef GT_STATUS (*GT_API_SET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8); +typedef GT_STATUS (*GT_API_GET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8*); + +typedef struct _TEST_API +{ + union + { + GT_API_SET_BOOL bool; + GT_API_SET_U16 u16; + GT_API_SET_U32 u32; + GT_API_MAC_ADDR mac; + GT_API_SET_PORT_BOOL port_bool; + GT_API_SET_PORT_U8 port_u8; + GT_API_SET_PORT_U16 port_u16; + GT_API_SET_PORT_U32 port_u32; + } setFunc; + + union + { + GT_API_GET_BOOL bool; + GT_API_GET_U16 u16; + GT_API_GET_U32 u32; + GT_API_MAC_ADDR mac; + GT_API_GET_PORT_BOOL port_bool; + GT_API_GET_PORT_U8 port_u8; + GT_API_GET_PORT_U16 port_u16; + GT_API_GET_PORT_U32 port_u32; + } getFunc; + +}TEST_API; + +typedef struct _TEST_STRUCT +{ + char strTest[16]; + GT_API_VOID testFunc; + GT_U32 testResults; +} TEST_STRUCT; + +#define MSG_PRINT(x) testPrint x + +#define MAX_MAC_ENTRIES 8192 +#define TEST_MAC_ENTRIES 64 +#define MAX_BUCKET_SIZE 2048 + +typedef struct _TEST_ATU_ENTRY +{ + GT_ATU_ENTRY atuEntry[TEST_MAC_ENTRIES]; +}TEST_ATU_ENTRY; + +typedef struct _ATU_ENTRY_INFO +{ + GT_ATU_ENTRY atuEntry; + GT_U16 hash; + GT_U16 bucket; +} ATU_ENTRY_INFO; + +extern GT_SYS_CONFIG pfTestSysCfg; +extern ATU_ENTRY_INFO *gAtuEntry; +extern GT_QD_DEV *dev; + +GT_STATUS qdStart(int,int,int); +GT_STATUS qdSimSetPhyInt(unsigned int portNumber, unsigned short u16Data); +GT_STATUS qdSimSetGlobalInt(unsigned short u16Data); + +GT_STATUS testAll(GT_QD_DEV*); +void testPrint(char* format, ...); +GT_U32 testATU(GT_QD_DEV *dev); +GT_STATUS testATUStress(GT_QD_DEV *dev); +GT_U32 testVTU(GT_QD_DEV *dev); + +extern FGT_INT_HANDLER qdIntHandler; + +int vtuEntryCmpFunc(void* buf, int a, int b); +int atuEntryCmpFunc(void* buf, int a, int b); +GT_STATUS gtSort(int list[], GT_CMP_FUNC cmpFunc, void* buf, GT_U32 len); +GT_U16 createATUList(GT_QD_DEV *dev, TEST_ATU_ENTRY atuEntry[], GT_U16 entrySize, GT_U16 dbNumSize, + GT_U16 sameMacsInEachDb, GT_U16 bSize); +GT_STATUS testFillUpAtu(GT_QD_DEV *dev, ATU_ENTRY_INFO *atuEntry, GT_U8 atuSize, + GT_U32 dbNum, GT_U16 first2Bytes, GT_ATU_UC_STATE state); +GT_U16 runQDHash(GT_U8* eaddr, GT_U16 dbNum, int bSize, GT_U16* pHash, + GT_U16* preBucket, GT_U16* posBucket); +GT_STATUS testDisplayATUList(GT_QD_DEV *dev); + +#ifdef USE_SEMAPHORE +GT_SEM osSemCreate(GT_SEM_BEGIN_STATE state); +GT_STATUS osSemDelete(GT_SEM smid); +GT_STATUS osSemWait(GT_SEM smid, GT_U32 timeOut); +GT_STATUS osSemSignal(GT_SEM smid); +#endif + +GT_BOOL gtBspReadMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value); +GT_BOOL gtBspWriteMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int value); +void gtBspMiiInit(GT_QD_DEV* dev); + +GT_BOOL qdSimRead (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL qdSimWrite (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int value); +void qdSimInit(GT_DEVICE devId, int baseAddr); + + +#if 1 /* This is for testing */ + +#define TEST_MASK 0 +#define TEST_MASK_0 0 +#define TEST_MASK_1 1 +#define TEST_MASK_2 2 +#define TEST_MASK_3 3 +#define TEST_MASK_4 4 +#define TEST_MASK_5 5 +#define TEST_MASK_6 6 +#define TEST_MASK_7 7 + +#define GET_TEST_MASK(_index, _mask) \ + ((_index == 0)?_mask##_0: \ + (_index == 1)?_mask##_1: \ + (_index == 2)?_mask##_2: \ + (_index == 3)?_mask##_3: \ + (_index == 4)?_mask##_4: \ + (_index == 5)?_mask##_5: \ + (_index == 6)?_mask##_6: \ + (_index == 7)?_mask##_7:0) + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __pfTesth */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/osSem.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/osSem.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/osSem.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/osSem.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,232 @@ +#include +/******************************************************************************** +* osSem.c +* +* DESCRIPTION: +* Semaphore related routines +* +* DEPENDENCIES: +* OS Dependent. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifdef _VXWORKS +#include "vxWorks.h" +#include "semLib.h" +#include "errnoLib.h" +#include "objLib.h" +int sysClkRateGet(void); + +#elif defined(WIN32) +#include "windows.h" +/* #include "wdm.h" */ +#elif defined(LINUX) +#include "/usr/include/semaphore.h" +typedef sem_t semaphore ; +#endif + +#include + +GT_SEM osSemCreate( GT_SEM_BEGIN_STATE state); +GT_STATUS osSemDelete(GT_SEM smid); +GT_STATUS osSemWait( GT_SEM smid, GT_U32 timeOut); +GT_STATUS osSemSignal(GT_SEM smid); + +/******************************************************************************* +* osSemCreate +* +* DESCRIPTION: +* Create semaphore. +* +* INPUTS: +* name - semaphore Name +* init - init value of semaphore counter +* count - max counter (must be >= 1) +* +* OUTPUTS: +* smid - semaphore Id +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_SEM osSemCreate(GT_SEM_BEGIN_STATE state) +{ +#ifdef _VXWORKS +#if 0 + return (GT_SEM)semBCreate(SEM_Q_FIFO, state); +#else + GT_SEM semid; + semid =(GT_SEM)semBCreate(SEM_Q_FIFO, state); + return semid; +#endif + +#elif defined(WIN32) + return (GT_SEM)CreateSemaphore(NULL, state, 1, NULL); +#elif defined(LINUX) + semaphore lxSem; + + sem_init(&lxSem, state, 1); + return lxSem; +#else + return 1; +#endif + return GT_OK; +} + +/******************************************************************************* +* osSemDelete +* +* DESCRIPTION: +* Delete semaphore. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemDelete(GT_SEM smid) +{ +#ifdef _VXWORKS + STATUS rc; + + rc = semDelete((SEM_ID) smid); + if (rc != OK) + return GT_FAIL; + +#elif defined(WIN32) + if (CloseHandle((HANDLE)smid) == 0) + return GT_FAIL; + +#elif defined(LINUX) + sem_destroy((semaphore*) smid); +#else + return GT_OK; +#endif + + return GT_OK; +} + +/******************************************************************************* +* osSemWait +* +* DESCRIPTION: +* Wait on semaphore. +* +* INPUTS: +* smid - semaphore Id +* timeOut - time out in miliseconds or 0 to wait forever +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* OS_TIMEOUT - on time out +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemWait(GT_SEM smid, GT_U32 timeOut) +{ +#ifdef _VXWORKS + STATUS rc; + + if (timeOut == 0) + rc = semTake ((SEM_ID) smid, WAIT_FOREVER); + else + { + int num, delay; + + num = sysClkRateGet(); + delay = (num * timeOut) / 1000; + if (delay < 1) + rc = semTake ((SEM_ID) smid, 1); + else + rc = semTake ((SEM_ID) smid, delay); + } + + if (rc != OK) + { + if (errno == S_objLib_OBJ_TIMEOUT) + return GT_TIMEOUT; + else + return GT_FAIL; + } + +#elif defined(WIN32) + DWORD rc; + + rc = WaitForSingleObject((HANDLE)smid, timeOut); + + if (rc == WAIT_ABANDONED) + return GT_FAIL; + if (rc == WAIT_TIMEOUT) + return GT_TIMEOUT; + +#elif defined(LINUX) + sem_wait((semaphore*) smid) ; +#else + return GT_OK; + +#endif + + return GT_OK; +} + +/******************************************************************************* +* osSemSignal +* +* DESCRIPTION: +* Signal a semaphore. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemSignal(GT_SEM smid) +{ +#ifdef _VXWORKS + STATUS rc; + rc = semGive ((SEM_ID) smid); + if (rc != OK) + return GT_FAIL; + +#elif defined(WIN32) + if(ReleaseSemaphore((HANDLE) smid, 1, NULL) == 0) + return GT_FAIL; + +#elif defined(LINUX) + sem_post((semaphore*) smid) ; +#else + return GT_OK; +#endif + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/qdFFmii.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/qdFFmii.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/qdFFmii.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/qdFFmii.c 2011-04-04 13:57:35.015595622 -0400 @@ -0,0 +1,156 @@ +/******************************************************************************* +* Copyright 2002, Marvell International Ltd. +* This code contains confidential information of Marvell semiconductor, inc. +* no rights are granted herein under any patent, mask work right or copyright +* of Marvell or any third party. +* Marvell reserves the right at its sole discretion to request that this code +* be immediately returned to Marvell. This code is provided "as is". +* Marvell makes no warranties, express, implied or otherwise, regarding its +* accuracy, completeness or performance. +*********************************************************************************/ +/* + * FILENAME: $Workfile: qdFFmii.c $ + * REVISION: $Revision: 8 $ + * LAST UPDATE: $Modtime: 3/03/03 3:24a $ + * + * DESCRIPTION: SMI access routines for Firefox board + * + */ +#include "mv_platform.h" +#include "mv_os.h" +#include "mv_qd.h" + +/* + * For each platform, all we need is + * 1) Assigning functions into + * fgtReadMii : to read MII registers, and + * fgtWriteMii : to write MII registers. + * + * 2) Register Interrupt (Not Defined Yet.) +*/ + +/* + * Firefox Specific Definition + */ +#define SMI_OP_CODE_BIT_READ 1 +#define SMI_OP_CODE_BIT_WRITE 0 +#define SMI_BUSY 1<<28 +#define READ_VALID 1<<27 + +#define SMI_TIMEOUT_COUNTER 1000 + +/***************************************************************************** +* +* GT_BOOL qdFFReadMii (GT_QD_DEV* dev, unsigned int portNumber , +* unsigned int MIIReg, unsigned int* value) +* +* Description +* This function will access the MII registers and will read the value of +* the MII register , and will retrieve the value in the pointer. +* Inputs +* portNumber - one of the 2 possiable Ethernet ports (0-1). +* MIIReg - the MII register offset. +* Outputs +* value - pointer to unsigned int which will receive the value. +* Returns Value +* true if success. +* false if fail to make the assignment. +* Error types (and exceptions if exist) +*/ +GT_BOOL ffReadMii (GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value) +{ + GT_U32 smiReg; + unsigned int phyAddr; + unsigned int timeOut = SMI_TIMEOUT_COUNTER; /* in 100MS units */ + int i; + + /* first check that it is not busy */ + smiReg = gtOsGtRegRead(GT_REG_ETHER_SMI_REG); + if (smiReg & SMI_BUSY) + { + for(i=0; ibaseRegAddr,29,&u32Data) != GT_OK) + { + return GT_FAIL; + } + + if(gsysWriteMiiReg(dev, (GT_U32)dev->baseRegAddr,29,(GT_U16)(u32Data|0x4)) != GT_OK) + { + return GT_FAIL; + } + + /* + * ReSet Bit6 of Register 30 of any phy + */ + if(gsysReadMiiReg(dev,dev->baseRegAddr,30,&u32Data) != GT_OK) + { + return GT_FAIL; + } + + if(gsysWriteMiiReg(dev, (GT_U32)dev->baseRegAddr,30,(GT_U16)(u32Data&(~0x40))) != GT_OK) + { + return GT_FAIL; + } + return GT_OK; +} + +/* +* Initialize the QuarterDeck. This should be done in BSP driver init routine. +* Since BSP is not combined with QuarterDeck driver, we are doing here. +*/ +GT_STATUS qdStart(void) /* devId is used for simulator only */ +{ + GT_STATUS status; + /* + * Register all the required functions to QuarterDeck Driver. + */ + cfg.BSPFunctions.readMii = ffReadMii; + cfg.BSPFunctions.writeMii = ffWriteMii; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else /* USE_SEMAPHORE */ + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif /* USE_SEMAPHORE */ + + cfg.initPorts = GT_TRUE; + cfg.cpuPortNum = GT_CPU_SWITCH_PORT; + qd_dev->cpuPortNum = GT_CPU_SWITCH_PORT; + if((status = qdLoadDriver(&cfg, qd_dev)) != GT_OK) { + gtOsPrintf("qdLoadDriver is failed: status = 0x%x\n", status); + return status; + } + + /* + * start the QuarterDeck + */ + if (qd_dev->deviceId == GT_88E6063) { + phyPatch(qd_dev); + } + + /* to which VID should we set the CPU_PORT? (1 is temporary)*/ + if((status = gvlnSetPortVid(qd_dev, GT_CPU_SWITCH_PORT, 5)) != GT_OK) { + gtOsPrintf("gprtSetPortVid returned fail for CPU port.\n"); + return status; + } + +#ifdef QD_TRAILER_MODE + /* set ingress trailer mode*/ + gprtSetIngressMode(qd_dev, GT_CPU_SWITCH_PORT, GT_TRAILER_INGRESS); + /* set egress trailer*/ + gprtSetTrailerMode(qd_dev, GT_CPU_SWITCH_PORT, GT_TRUE); +#endif + +#ifdef QD_HEADER_MODE + if((status = gprtSetHeaderMode(qd_dev, GT_CPU_SWITCH_PORT, GT_TRUE)) != GT_OK) + { + gtOsPrintf("gprtSetHeaderMode return Failed\n"); + return status; + } +#endif + + return GT_OK; +} + + +void qdClose(void) +{ + if (qd_dev->devEnabled) + qdUnloadDriver(qd_dev); +} + + +GT_STATUS qdInit(void) +{ + GT_STATUS status = GT_OK; + unsigned int i; + + status = qdStart(); + if (GT_OK != status) + { + gtOsPrintf("qdStart is failed: status = 0x%x\n", status); + return status; + } + +#ifdef DB_6093_88E6218 + /* start 88E6090 device, assumes SMI Address 0x11 and CPU Port 10 */ + + if(loadDev(qd_ext, SMI_MULTI_ADDR_MODE, 0x11, 10) == NULL) + { + gtOsPrintf("Failed to start External Device. Please check the SMI Address 0x11!\n"); + } + + /* allow larger than 1522 bytes of frame (header + marvell tag) */ + gsysSetMaxFrameSize(qd_dev,GT_FALSE); + +#endif + + for (i=0; inumOfPorts; i++) + { + /* default port prio to three */ + gcosSetPortDefaultTc(qd_dev, i, 3); + /* disable IP TOS Prio */ + gqosIpPrioMapEn(qd_dev, i, GT_FALSE); + /* disable QOS Prio */ + gqosUserPrioMapEn(qd_dev, i, GT_FALSE); + /* Force flow control for all ports */ + gprtSetForceFc(qd_dev, i, GT_FALSE); + } + + /* Enable port #6 */ + status = gstpSetPortState(qd_dev, 6, GT_PORT_FORWARDING); + + if((status = gprtClearAllCtr(qd_dev)) != GT_OK) + { + return status; + } + for (i=0; inumOfPorts; i++) + { + short sdata; + + hwReadPortReg(qd_dev, i, 0x4, &sdata); + gtOsPrintf("Control reg for port[%d] is: %x\n",i,sdata); + + hwReadPortReg(qd_dev, i, 0x0, &sdata); + gtOsPrintf("Status reg for port[%d] is: %x\n",i,sdata); + + } + qdStatus(); +#endif /* QD_DEBUG */ + + gtOsPrintf("QD initiated\n"); + + return status; +} + +static const char* qdPortStpStates[] = + {"DISABLE", + "BLOCKING", + "LEARNING", + "FORWARDING"}; + +static char* qdPortListToStr(GT_LPORT* portList, int portListNum, + char* portListStr) +{ + int port, idx, strIdx=0; + + for(idx=0; idx +/******************************************************************************** +* qdInt.c +* +* DESCRIPTION: +* This sample shows how to call QuarterDeck Interrupt handler when QD INT +* raised, and how to take care each Interrupt Cause. +* +* DEPENDENCIES: NONE. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + +#ifdef QD_DEBUG +#ifdef _VXWORKS +#define INT_MSG_PRINT logMsg +#else +#define INT_MSG_PRINT printf +#endif +#else /* QD_DEBUG */ +#define INT_MSG_PRINT(_x,_a0,_a1,_a2,_a3,_a4,_a5) while(0){} +#endif + +GT_U32 QDIntMask = GT_VTU_PROB|GT_ATU_PROB|GT_PHY_INTERRUPT; + +/* + * To enable quarterDeck interrupt, you need to call eventSetActive() and + * gprtPhyIntEnable(), as following sample routine. + * sampleQDIntEnable will enable all interrupt causes. + * For Port, GT_ATU_FULL, GT_ATU_DONE, GT_PHY_INTERRUPT, and GT_EE_INTERRUPT + * are enabled. + * For every Phy (0 ~ 4), GT_SPEED_CHANGED, GT_DUPLEX_CHANGED, GT_PAGE_RECEIVED, + * GT_AUTO_NEG_COMPLETED, GT_LINK_STATUS_CHANGED, GT_SYMBOL_ERROR, + * GT_FALSE_CARRIER, GT_FIFO_FLOW, GT_CROSSOVER_CHANGED, GT_POLARITY_CHANGED, + * and GT_JABBER are enabled. +*/ +GT_STATUS qdIntEnable(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_U16 data; + int port; + + /* + * Enable QuarterDeck interrupt for ATUFull, ATUDone, PHYInt, and EEInt. + * If writing 0 into eventSetActive(), all port interrupt will be disabled. + */ + data = QDIntMask; + if((status = eventSetActive(dev,data)) != GT_OK) + { + MSG_PRINT(("eventSetActive returned fail.\n")); + return status; + } + + /* + * Enable Phy interrupt for every possible interrupt cause. + * If writing 0 into gprtPhyIntEnable(), all port interrupt will be disabled. + */ + data = GT_SPEED_CHANGED|GT_DUPLEX_CHANGED|GT_LINK_STATUS_CHANGED; + + for(port=0; port<3; port++) + { + if((status = gprtPhyIntEnable(dev,port,data)) != GT_OK) + { + MSG_PRINT(("gprtPhyIntEnable returned fail.\n")); + return status; + } + } + + return GT_OK; +} + +/* + * Disable QuarterDeck Interrupt. +*/ +GT_STATUS qdIntDisable(GT_QD_DEV *dev) +{ + GT_STATUS status; + int port; + + /* + * Writing 0 into eventSetActive(), all port interrupt will be disabled. + */ + if((status = eventSetActive(dev,0)) != GT_OK) + { + MSG_PRINT(("eventSetActive returned fail.\n")); + return status; + } + + for(port=0; port<3; port++) + { + if((status = gprtPhyIntEnable(dev,port,0)) != GT_OK) + { + MSG_PRINT(("gprtPhyIntEnable returned fail.\n")); + return status; + } + } + + return GT_OK; +} + + +/* + * Assume that the following function, sampleQDIntVector(), is registered + * when BSP calls intConnect for QD Interrupt. + * This sample will show how to deal with QuarterDeck Interrupt. +*/ +GT_STATUS qdIntVector(GT_QD_DEV *dev) +{ + GT_U16 intCause,data,phyIntCause; + GT_VTU_INT_STATUS vtuIntStatus; + GT_ATU_INT_STATUS atuIntStatus; + int port; + + /* + * Disable QuarterDeck Interrupt in System Level. + * ToDo... + */ + + /* + * Check if QD generated the interrupt. + */ + if(eventGetIntStatus(dev,&intCause) != GT_TRUE) + { + /* QD didn't generate the interrupt. */ + return GT_FAIL; + } + + /* + * QD generated interrupt with the reason in intCause. + */ + if(intCause & GT_VTU_PROB) + { + INT_MSG_PRINT("VTU PROB INT for Dev %#x.\n",(int)dev,0,0,0,0,0); + /* + * VTU member violation, miss violation, or full violation. + */ + do + { + if(gvtuGetIntStatus(dev, &vtuIntStatus) != GT_OK) + { + /* reading VTU Int Status Failed */ + INT_MSG_PRINT("VTU INT Status read failure.\n",0,0,0,0,0,0); + break; + } + INT_MSG_PRINT("VTU INT : Cause %#x, SPID %i, VID %i\n",vtuIntStatus.vtuIntCause,vtuIntStatus.spid,vtuIntStatus.vid,0,0,0); + } while (vtuIntStatus.vtuIntCause); + } + + if(intCause & GT_ATU_PROB) + { + /* + * ATU cannot load or learn a new mapping due to all the available + * locations for an address being locked. + * ToDo... + */ + INT_MSG_PRINT("ATU PROB INT for Dev %#x.\n",(int)dev,0,0,0,0,0); + + do + { + if(gatuGetIntStatus(dev, &atuIntStatus) != GT_OK) + { + /* reading ATU Int Status Failed */ + INT_MSG_PRINT("ATU INT Status read failure.\n",0,0,0,0,0,0); + break; + } + INT_MSG_PRINT("ATU INT : Cause %#x, SPID %i, DBNum %i\n",atuIntStatus.atuIntCause,atuIntStatus.spid,atuIntStatus.dbNum,0,0,0); + INT_MSG_PRINT("ATU INT : MAC %02x-%02x-%02x-%02x-%02x-%02x\n", + atuIntStatus.macAddr.arEther[0], + atuIntStatus.macAddr.arEther[1], + atuIntStatus.macAddr.arEther[2], + atuIntStatus.macAddr.arEther[3], + atuIntStatus.macAddr.arEther[4], + atuIntStatus.macAddr.arEther[5]); + } while (atuIntStatus.atuIntCause); + + } + + if(intCause & GT_ATU_DONE) + { + /* + * There is a transitions from a one to a zero on ATUBusy bit + * (Refer to ATU Operation Register.) + * ToDo... + */ + INT_MSG_PRINT("ATU Done INT for Dev %#x.\n",(int)dev,0,0,0,0,0); + } + +#if 1 + + if(intCause & GT_PHY_INTERRUPT) + { + /* + * At least one of the Phy generated interrupt. + * We need to read Phy Interrupt Summary and go through each phy + * based on the summary. + */ + + if(gprtGetPhyIntPortSummary(dev,&data) != GT_OK) + { + return GT_FAIL; + } + + INT_MSG_PRINT("Phy INT (Port Vector %#x).\n",(int)data,0,0,0,0,0); + + port = 0; + while(data) + { + if(data & 0x01) + { + /* + * Call gprtGetPhyIntStatus to get intCause + */ + if(gprtGetPhyIntStatus(dev,port,&phyIntCause) != GT_OK) + { + /* + * Something wrong with the system. Need to do the + * necessary work. + * ToDo... + */ + } + + INT_MSG_PRINT("Port %i: %#x.\n",port,phyIntCause,0,0,0,0); + + if(phyIntCause & GT_SPEED_CHANGED) + { + /* + * Speed has been changed. + * ToDo... + */ + INT_MSG_PRINT("SPEED CHANGE\n",0,0,0,0,0,0); + } + + if(phyIntCause & GT_DUPLEX_CHANGED) + { + /* + * Duplex mode has been changed. + * ToDo... + */ + INT_MSG_PRINT("DUPLEX CHANGE\n",0,0,0,0,0,0); + } + + if(phyIntCause & GT_PAGE_RECEIVED) + { + /* + * Page received. + * ToDo... + */ + + INT_MSG_PRINT("PAGE RECEIVED\n",0,0,0,0,0,0); + } + + if(phyIntCause & GT_AUTO_NEG_COMPLETED) + { + /* + * AutoNegotiation completed. + * ToDo... + */ + INT_MSG_PRINT("AUTO NEG COMPLETED\n",0,0,0,0,0,0); + + } + + if(phyIntCause & GT_LINK_STATUS_CHANGED) + { + /* + * Link Status changed. + * ToDo... + */ + + INT_MSG_PRINT("LINK CHANGE\n",0,0,0,0,0,0); + } + + if(phyIntCause & GT_SYMBOL_ERROR) + { + /* + * Symbol error + * ToDo... + */ + + } + + if(phyIntCause & GT_FALSE_CARRIER) + { + /* + * False Carrier. + * ToDo... + */ + + } + + if(phyIntCause & GT_FIFO_FLOW) + { + /* + * Fifo Overflow/underflow error + * ToDo... + */ + + } + + if(phyIntCause & GT_CROSSOVER_CHANGED) + { + /* + * MDI/MDIX crossover changed. + * ToDo... + */ + + } + + if(phyIntCause & GT_POLARITY_CHANGED) + { + /* + * Polarity changed. + * ToDo... + */ + + } + + if(phyIntCause & GT_JABBER) + { + /* + * Jabber + * ToDo... + */ + + } + } + + data >>= 1; + port++; + } + } + + if(intCause & GT_EE_INTERRUPT) + { + /* + * EEPROM is done loading registers. + * ToDo... + */ + + } + + + /* + * Now, all the QuarterDeck related interrupt have been cleared, + * so it's OK to enable QuarterDeck Interrupt in System Level. + * ToDo... + */ + +#endif + + return GT_OK; + +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/qdSim.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/qdSim.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/qdSim.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/qdSim.c 2011-04-04 13:57:35.025596119 -0400 @@ -0,0 +1,2004 @@ +#include +/******************************************************************************** +* qdSim.c +* +* DESCRIPTION: +* Simulate QuaterDeck Device(88E6052)'s register map. When QuareterDeck API +* try to read/write a bit or bits into QuaterDeck, the simulator will redirect to +* its own memory place and performing the function very close to QuaterDeck. +* For example, +* 1) user can set/reset a certain bit of QuarterDeck registers(Phy,Port,and General registers). +* 2) user can access ATU (flush, load, purge, etc. with max MAC addresses of 32) +* 3) user can manually generate an Interrupt and test the Interrupt routine. +* 4) when user read a register, it will clear a certain register if it's a Self Clear register. +* 5) when user write a register, it will return ERROR if it's read only register. +* +* +* DEPENDENCIES: QuaterDeck (88E6052) Register MAP. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include +#include + +#define IS_BROADCAST_ADDR(_addr) \ + (((_addr)[0] == 0xFF) && ((_addr)[1] == 0xFF) && \ + ((_addr)[2] == 0xFF) && ((_addr)[3] == 0xFF) && \ + ((_addr)[4] == 0xFF) && ((_addr)[5] == 0xFF)) + +#define IS_GLOBAL_REG(_port) ((int)(_port) == qdSimDev.qdSimGlobalRegBase) +#define IS_PORT_REG(_port) (((int)(_port) >= qdSimDev.qdSimPortBase) && ((int)(_port) < qdSimDev.qdSimPortBase + qdSimDev.qdSimNumOfPorts)) +#define IS_PHY_REG(_port) (((int)(_port) >= qdSimDev.qdSimPhyBase) && ((int)(_port) < qdSimDev.qdSimPhyBase + qdSimDev.qdSimNumOfPhys)) + +typedef struct _QD_SIM_DEV +{ + int qdSimUsed; + unsigned int qdSimDevId; + int qdSimNumOfPorts; + int qdSimPortBase; + int qdSimNumOfPhys; + int qdSimPhyBase; + int qdSimGlobalRegBase; + int qdSimPortStatsClear[10]; + int qdSimStatsCapturedPort; + int vtuSize; + int atuSize; +} QD_SIM_DEV; + +static QD_SIM_DEV qdSimDev = {0}; + +void qdSimRegsInit(); +GT_BOOL qdSimRead (GT_QD_DEV *dev, unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL qdSimWrite(GT_QD_DEV *dev, unsigned int portNumber , unsigned int miiReg, unsigned int value); + +/* + * This Array will simulate the QuarterDeck Registers. + * To use it, qdSimRegs has to be initialized with its default values and + * Call qdSimRead and qdSimWrite functions. +*/ +#define MAX_SMI_ADDRESS 0x20 +#define MAX_REG_ADDRESS 0x20 +#define MAX_ATU_ADDRESS 0x800 +#define MAX_QD_VTU_ENTRIES 0x40 + +GT_U16 qdSimRegs[MAX_SMI_ADDRESS][MAX_REG_ADDRESS]; + +typedef struct _QDSIM_ATU_ENTRY +{ + GT_U16 atuData; + GT_U16 DBNum; + GT_U8 atuMac[6]; +} QDSIM_ATU_ENTRY; + +/* + Since QuarterDeck Simulator supports only fixed size of atu entry, + we are going with array list not dynamic linked list. +*/ +typedef struct _QDSIM_ATU_NODE +{ + QDSIM_ATU_ENTRY atuEntry; + GT_U32 nextEntry; +} QDSIM_ATU_NODE; + +typedef struct _QDSIM_ATU_LIST +{ + int atuSize; + GT_U32 head; +} QDSIM_ATU_LIST; + +QDSIM_ATU_NODE ATUNode[MAX_ATU_ADDRESS]; +QDSIM_ATU_LIST ATUList; + +typedef struct _QDSIM_VTU_ENTRY +{ + GT_U16 DBNum; + GT_U16 memberTag[10]; + GT_U16 vid; +} QDSIM_VTU_ENTRY; + +/* + Since QuarterDeck Simulator supports only fixed size of atu entry, + we are going with array list not dynamic linked list. +*/ +typedef struct _QDSIM_VTU_NODE +{ + QDSIM_VTU_ENTRY vtuEntry; + GT_U32 nextEntry; +} QDSIM_VTU_NODE; + +typedef struct _QDSIM_VTU_LIST +{ + int vtuSize; + GT_U32 head; +} QDSIM_VTU_LIST; + +QDSIM_VTU_NODE VTUNode[MAX_QD_VTU_ENTRIES]; +QDSIM_VTU_LIST VTUList; + +/******************************************************************************* +* qdMemSet +* +* DESCRIPTION: +* Set a block of memory +* +* INPUTS: +* start - start address of memory block for setting +* simbol - character to store, converted to an unsigned char +* size - size of block to be set +* +* OUTPUTS: +* None +* +* RETURNS: +* Pointer to set memory block +* +* COMMENTS: +* None +* +*******************************************************************************/ +void * qdMemSet +( + IN void * start, + IN int symbol, + IN GT_U32 size +) +{ + GT_U32 i; + char* buf; + + buf = (char*)start; + + for(i=0; i src2. +* +* COMMENTS: +* None +* +*******************************************************************************/ +int qdMemCmp +( + IN char src1[], + IN char src2[], + IN GT_U32 size +) +{ + GT_U32 i; + int value; + + for(i=0; iatuMac)) + { + if(ATUList.atuSize != 0) + { + if (ATUNode[node].atuEntry.DBNum == entry->DBNum) + return node; + else + { + for(i=0; iDBNum) + return node; + node = ATUNode[node].nextEntry; + } + } + + } + return MAX_ATU_ADDRESS; + } + + for(i=0; iatuMac) > 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + break; + } + node = ATUNode[node].nextEntry; + } + + if (i == ATUList.atuSize) + return MAX_ATU_ADDRESS; + + return node; +} + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimATUAdd(QDSIM_ATU_ENTRY* entry) +{ + int i, freeNode, preNode, node; + + preNode = node = ATUList.head; + + if (ATUList.atuSize >= MAX_ATU_ADDRESS) + return GT_FALSE; + + /* find a free entry from our global memory. */ + for(i=0; iatuMac) >= 0) + break; + preNode = node; + node = ATUNode[node].nextEntry; + } + + /* if the same Mac address is in the list and dbnum is identical, then just update and return. */ + if (i != ATUList.atuSize) + if(cmpEtherMac(ATUNode[node].atuEntry.atuMac,entry->atuMac) == 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + { + ATUNode[node].atuEntry.atuData = entry->atuData; + return GT_TRUE; + } + } + + qdMemCpy(ATUNode[freeNode].atuEntry.atuMac, entry->atuMac, 6); + ATUNode[freeNode].atuEntry.atuData = entry->atuData; + ATUNode[freeNode].atuEntry.DBNum = entry->DBNum; + + /* Add it to head */ + if (i == 0) + { + ATUNode[freeNode].nextEntry = ATUList.head; + ATUList.head = freeNode; + } + /* Add it to tail */ + else if (i == ATUList.atuSize) + { + ATUNode[preNode].nextEntry = freeNode; + ATUNode[freeNode].nextEntry = ATUList.head; + } + /* Add it in the middle of the list */ + else + { + ATUNode[freeNode].nextEntry = ATUNode[preNode].nextEntry; + ATUNode[preNode].nextEntry = freeNode; + } + ATUList.atuSize++; + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimATUDel(QDSIM_ATU_ENTRY* entry) +{ + int i, preNode, node; + + preNode = node = ATUList.head; + + /* find the entry */ + for(i=0; iatuMac) == 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + break; + } + preNode = node; + node = ATUNode[node].nextEntry; + } + + if (i == ATUList.atuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Delete it from head */ + if (i == 0) + { + ATUList.head = ATUNode[node].nextEntry; + } + /* Delete it in the middle of the list */ + else if (i != ATUList.atuSize-1) + { + ATUNode[preNode].nextEntry = ATUNode[node].nextEntry; + } + ATUList.atuSize--; + ATUNode[node].nextEntry = MAX_ATU_ADDRESS; + + return GT_TRUE; +} + + +GT_BOOL qdSimATUFlushUnlockedEntry() +{ + int i; + + for (i=0; iatuData = qdSimRegs[qdSimDev.qdSimGlobalRegBase][12]; + entry->atuMac[0] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] >> 8) & 0xFF; + entry->atuMac[1] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] & 0xFF; + entry->atuMac[2] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] >> 8) & 0xFF; + entry->atuMac[3] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] & 0xFF; + entry->atuMac[4] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] >> 8) & 0xFF; + entry->atuMac[5] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] & 0xFF; + entry->DBNum = qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] & 0xF; + return; +} + +void qdSimSetATUInfo(QDSIM_ATU_ENTRY* entry) +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][12] = entry->atuData; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] = (entry->atuMac[0]<<8) | entry->atuMac[1]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] = (entry->atuMac[2]<<8) | entry->atuMac[3]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] = (entry->atuMac[4]<<8) | entry->atuMac[5]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (entry->DBNum & 0xF); + + return; +} + +void qdSimReSetATUInfo() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][12] = 0; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] = 0xFFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] = 0xFFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] = 0xFFFF; + + return; +} + +GT_BOOL qdSimATUOperation(unsigned int value) +{ + QDSIM_ATU_ENTRY entry; + int index; + + switch((value & 0x7000) >> 12) + { + case 1: + /* Flush ALL */ + qdSimATUInit(); + break; + case 2: + /* Flush all unlocked entries */ + return qdSimATUFlushUnlockedEntry(); + case 3: + /* Load or Purge entry */ + qdSimGetATUInfo(&entry); + if(entry.atuData & 0xF) + return qdSimATUAdd(&entry); + else + return qdSimATUDel(&entry); + break; + case 4: + /* Get Next Entry */ + qdSimGetATUInfo(&entry); + index = qdSimATUFindNext(&entry); + if (index == MAX_ATU_ADDRESS) + { + qdSimReSetATUInfo(); + return GT_TRUE; + } + else + { + qdSimSetATUInfo(&ATUNode[index].atuEntry); + return GT_TRUE; + } + break; + case 5: + /* Flush ALL in a DBNum */ + return qdSimATUFlushInDB(value & 0xF); + break; + case 6: + /* Flush all unlocked entries */ + return qdSimATUFlushUnlockedInDB(value & 0xF); + default: + break; + } + return GT_TRUE; +} + +/* + VTU Related Routines +*/ + +/* + entry index, if found. + MAX_QD_VTU_ENTRIES, otherwise. +*/ +int qdSimVTUFindNext(QDSIM_VTU_ENTRY* entry) +{ + int i; + int node = VTUList.head; + + if (entry->vid == 0xFFF) + { + if(VTUList.vtuSize != 0) + return node; + else + return MAX_QD_VTU_ENTRIES; + } + + for(i=0; i entry->vid) + break; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + return MAX_QD_VTU_ENTRIES; + + return node; +} + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUAdd(QDSIM_VTU_ENTRY* entry) +{ + int i, freeNode, preNode, node; + + preNode = node = VTUList.head; + + if (VTUList.vtuSize >= qdSimDev.vtuSize) + return GT_FALSE; + + /* find a free entry from our global memory. */ + for(i=0; i= entry->vid) + break; + preNode = node; + node = VTUNode[node].nextEntry; + } + + /* if the same vid is in the list, then just update and return. */ + if (i != VTUList.vtuSize) + if(VTUNode[node].vtuEntry.vid == entry->vid) + { + qdMemCpy(&VTUNode[node].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + return GT_TRUE; + } + + qdMemCpy(&VTUNode[freeNode].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + + /* Add it to head */ + if (i == 0) + { + VTUNode[freeNode].nextEntry = VTUList.head; + VTUList.head = freeNode; + } + /* Add it to tail */ + else if (i == VTUList.vtuSize) + { + VTUNode[preNode].nextEntry = freeNode; + VTUNode[freeNode].nextEntry = VTUList.head; + } + /* Add it in the middle of the list */ + else + { + VTUNode[freeNode].nextEntry = VTUNode[preNode].nextEntry; + VTUNode[preNode].nextEntry = freeNode; + } + VTUList.vtuSize++; + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUDel(QDSIM_VTU_ENTRY* entry) +{ + int i, preNode, node; + + preNode = node = VTUList.head; + + /* find the entry */ + for(i=0; ivid) + break; + preNode = node; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Delete it from head */ + if (i == 0) + { + VTUList.head = VTUNode[node].nextEntry; + } + /* Delete it in the middle of the list */ + else if (i != VTUList.vtuSize-1) + { + VTUNode[preNode].nextEntry = VTUNode[node].nextEntry; + } + VTUList.vtuSize--; + VTUNode[node].nextEntry = MAX_QD_VTU_ENTRIES; + + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUUpdate(QDSIM_VTU_ENTRY* entry) +{ + int i; + int node = VTUList.head; + + /* find the entry */ + for(i=0; ivid) + break; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Update the found entry */ + qdMemCpy(&VTUNode[node].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + + return GT_TRUE; +} + +void qdSimVTUInit() +{ + int i; + + qdMemSet((char*)VTUNode, 0, sizeof(VTUNode)); + + /* MAX_ATU_ADDRESS means entry i is free, otherwise, it's not free */ + for (i=0; iDBNum = qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] & 0xF; + entry->vid = qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] & 0x1FFF; + entry->memberTag[0] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] & 0x3; + entry->memberTag[1] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 4) & 0x3; + entry->memberTag[2] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 8) & 0x3; + entry->memberTag[3] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 12) & 0x3; + entry->memberTag[4] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] & 0x3; + entry->memberTag[5] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 4) & 0x3; + entry->memberTag[6] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 8) & 0x3; + entry->memberTag[7] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 12) & 0x3; + entry->memberTag[8] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] & 0x3; + entry->memberTag[9] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] >> 4) & 0x3; + + return; +} + +void qdSimSetVTUInfo(QDSIM_VTU_ENTRY* entry) +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= entry->DBNum; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = (entry->vid & 0xFFF) | 0x1000; + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = entry->memberTag[0] | + (entry->memberTag[1] << 4) | + (entry->memberTag[2] << 8) | + (entry->memberTag[3] << 12); + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = entry->memberTag[4] | + (entry->memberTag[5] << 4) | + (entry->memberTag[6] << 8) | + (entry->memberTag[7] << 12); + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] = entry->memberTag[8] | + (entry->memberTag[9] << 4); + + return; +} + +void qdSimReSetVTUInfo() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0xFFF; + + return; +} + +void qdSimVTUGetViolation() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= 1; /* assume port 1 causes the violation */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 1; /* assume vid 1 causes the violation */ +} + +void qdSimVTUResetBusy() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0x8000; + + return; +} + +GT_BOOL qdSimVTUOperation(unsigned int value) +{ + QDSIM_VTU_ENTRY entry; + int index; + + if(!(value & 0x8000)) + return GT_FALSE; + + qdSimVTUResetBusy(); + + switch((value & 0x7000) >> 12) + { + case 1: + /* Flush ALL */ + qdSimVTUInit(); + break; + case 3: + /* Load or Purge entry */ + qdSimGetVTUInfo(&entry); + if(entry.vid & 0x1000) + { + entry.vid &= ~0x1000; + return qdSimVTUAdd(&entry); + } + else + return qdSimVTUDel(&entry); + break; + case 4: + /* Get Next Entry */ + qdSimGetVTUInfo(&entry); + entry.vid &= ~0x1000; + index = qdSimVTUFindNext(&entry); + if (index == MAX_QD_VTU_ENTRIES) + { + qdSimReSetVTUInfo(); + return GT_TRUE; + } + else + { + qdSimSetVTUInfo(&VTUNode[index].vtuEntry); + return GT_TRUE; + } + break; + case 7: + qdSimVTUGetViolation(); + break; + default: + break; + } + return GT_TRUE; +} + +void qdSimStatsInit() +{ + int i; + + for(i=0; i> 12) + { + case 1: + /* Flush ALL */ + for(i=0; i= (unsigned int)qdSimDev.qdSimNumOfPorts) + return GT_FALSE; + qdSimDev.qdSimPortStatsClear[value & 0x3F] = 1; + break; + case 4: + /* Read a counter */ + if(qdSimDev.qdSimPortStatsClear[qdSimDev.qdSimStatsCapturedPort] == 1) + { + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; + } + else + { + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = qdSimDev.qdSimStatsCapturedPort; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = value & 0x3F; + } + break; + case 5: + if ((value & 0x3F) >= (unsigned int)qdSimDev.qdSimNumOfPorts) + return GT_FALSE; + qdSimDev.qdSimStatsCapturedPort = value & 0x3F; + break; + default: + return GT_FALSE; + } + return GT_TRUE; +} + +#define QD_PHY_CONTROL_RW (QD_PHY_RESET|QD_PHY_LOOPBACK|QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_POWER|QD_PHY_RESTART_AUTONEGO|QD_PHY_DUPLEX) +#define QD_PHY_CONTROL_RO (~QD_PHY_CONTROL_RW) + +GT_BOOL qdSimPhyControl(unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + + /* reset all the Read Only bits. */ + value &= QD_PHY_CONTROL_RW; + + /* If powerDown is set, add Reset and Restart Auto bits. */ + if(value & QD_PHY_POWER) + { + value |= (QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + + /* If Power Down was set, clear Reset and Restart Auto bits. */ + if(qdSimRegs[portNumber][miiReg] & QD_PHY_POWER) + { + value &= ~(QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + + /* If Reset or Restart Auto set, replace with current value and clear Reset/Restart Auto. */ + if (value & (QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO)) + { + value &= ~(QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + else + { + value &= ~(QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_DUPLEX); + qdSimRegs[portNumber][miiReg] &= (QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_DUPLEX); + qdSimRegs[portNumber][miiReg] |= (GT_U16)value; + return GT_TRUE; + } + + return GT_TRUE; +} + +void qdSimRegsInit_6021() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit_6063() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit_6083() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit() +{ + int i; + + qdMemSet(qdSimRegs, 0xff, sizeof(qdSimRegs)); + + /* + PHY Registers Setup + */ + for(i=0; i= MAX_SMI_ADDRESS) + portNumber -= MAX_SMI_ADDRESS; + + if ((portNumber >= MAX_SMI_ADDRESS) || (miiReg >= MAX_REG_ADDRESS)) + return GT_FALSE; + + switch(qdSimDev.qdSimDevId) + { + case GT_88E6051: + case GT_88E6052: + return qdSimRead_6052(portNumber, miiReg, value); + case GT_88E6021: + return qdSimRead_6021(portNumber, miiReg, value); + case GT_88E6063: + case GT_FF_HG: + case GT_FF_EG: + case GT_FH_VPN: + return qdSimRead_6063(portNumber, miiReg, value); + case GT_88E6083: + return qdSimRead_6083(portNumber, miiReg, value); + default: + break; + } + + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6052 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6021 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 9) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + break; + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6063 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 12) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6083 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + case QD_REG_VTU_DATA3_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 12) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + + +GT_BOOL qdSimWrite (GT_QD_DEV *dev,unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + if (portNumber >= MAX_SMI_ADDRESS) + portNumber -= MAX_SMI_ADDRESS; + + if ((portNumber >= MAX_SMI_ADDRESS) || (miiReg >= MAX_REG_ADDRESS)) + return GT_FALSE; + + switch(qdSimDev.qdSimDevId) + { + case GT_88E6051: + case GT_88E6052: + return qdSimWrite_6052(portNumber, miiReg, value); + case GT_88E6021: + return qdSimWrite_6021(portNumber, miiReg, value); + case GT_88E6063: + case GT_FF_HG: + case GT_FF_EG: + case GT_FH_VPN: + return qdSimWrite_6063(portNumber, miiReg, value); + case GT_88E6083: + return qdSimWrite_6083(portNumber, miiReg, value); + + default: + break; + } + + return GT_TRUE; +} + +GT_STATUS qdSimSetPhyInt(unsigned int portNumber, unsigned short u16Data) +{ + if(!qdSimDev.qdSimUsed) + return GT_FAIL; + + qdSimRegs[portNumber][QD_PHY_INT_STATUS_REG] = u16Data; + if(u16Data) + qdSimRegs[0][QD_PHY_INT_PORT_SUMMARY_REG] |= (1< + +/******************************************************************************** +* gtSimRegs.h +* +* DESCRIPTION: +* This file includes the declaration of the struct to hold the addresses +* of switch (global & per-port). +* +* DEPENDENCIES: +* QuarterDeck register MAP. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __qdSimRegsh +#define __qdSimRegsh + +/* QuarterDeck Per Port Registers */ +#define QD_REG_PORT_STATUS 0x0 +#define QD_REG_SWITCH_ID 0x3 +#define QD_REG_PORT_CONTROL 0x4 +#define QD_REG_PORT_VLAN_MAP 0x6 +#define QD_REG_PVID 0x7 +#define QD_REG_RATE_CTRL 0xA +#define QD_REG_PAV 0xB +#define QD_REG_RXCOUNTER 0x10 +#define QD_REG_TXCOUNTER 0x11 +#define QD_REG_Q_COUNTER 0x1B + +/* QuarterDeck Global Registers */ +#define QD_REG_GLOBAL_STATUS 0x0 +#define QD_REG_MACADDR_01 0x1 +#define QD_REG_MACADDR_23 0x2 +#define QD_REG_MACADDR_45 0x3 +#define QD_REG_GLOBAL_CONTROL 0x4 + +/* the following VTU entries are added for Fullsail and Clippership */ +#define QD_REG_VTU_OPERATION 0x5 +#define QD_REG_VTU_VID_REG 0x6 +#define QD_REG_VTU_DATA1_REG 0x7 +#define QD_REG_VTU_DATA2_REG 0x8 +#define QD_REG_VTU_DATA3_REG 0x9 +#define QD_REG_STATS_OPERATION 0x1D +#define QD_REG_STATS_COUNTER3_2 0x1E +#define QD_REG_STATS_COUNTER1_0 0x1F + +#define QD_REG_ATU_CONTROL 0xA +#define QD_REG_ATU_OPERATION 0xB +#define QD_REG_ATU_DATA_REG 0xC +#define QD_REG_ATU_MAC_BASE 0xD +#define QD_REG_ATU_MAC_01 0xD +#define QD_REG_ATU_MAC_23 0xE +#define QD_REG_ATU_MAC_45 0xF +#define QD_REG_IP_PRI_BASE 0x10 +#define QD_REG_IP_PRI_REG0 0x10 +#define QD_REG_IP_PRI_REG1 0x11 +#define QD_REG_IP_PRI_REG2 0x12 +#define QD_REG_IP_PRI_REG3 0x13 +#define QD_REG_IP_PRI_REG4 0x14 +#define QD_REG_IP_PRI_REG5 0x15 +#define QD_REG_IP_PRI_REG6 0x16 +#define QD_REG_IP_PRI_REG7 0x17 +#define QD_REG_IEEE_PRI 0x18 + +/* Definition for QD_REG_PORT_STATUS */ +#define QD_PORT_STATUS_DUPLEX 0x200 + +/* Definitions for MIB Counter */ +#define GT_STATS_NO_OP 0x0 +#define GT_STATS_FLUSH_ALL 0x1 +#define GT_STATS_FLUSH_PORT 0x2 +#define GT_STATS_READ_COUNTER 0x4 +#define GT_STATS_CAPTURE_PORT 0x5 + +#define QD_PHY_CONTROL_REG 0 +#define QD_PHY_AUTONEGO_AD_REG 4 +#define QD_PHY_NEXTPAGE_TX_REG 7 +#define QD_PHY_SPEC_CONTROL_REG 16 +#define QD_PHY_INT_ENABLE_REG 18 +#define QD_PHY_INT_STATUS_REG 19 +#define QD_PHY_INT_PORT_SUMMARY_REG 20 + +/* Bit Definition for QD_PHY_CONTROL_REG */ +#define QD_PHY_RESET 0x8000 +#define QD_PHY_LOOPBACK 0x4000 +#define QD_PHY_SPEED 0x2000 +#define QD_PHY_AUTONEGO 0x1000 +#define QD_PHY_POWER 0x800 +#define QD_PHY_ISOLATE 0x400 +#define QD_PHY_RESTART_AUTONEGO 0x200 +#define QD_PHY_DUPLEX 0x100 + +#define QD_PHY_POWER_BIT 11 +#define QD_PHY_RESTART_AUTONEGO_BIT 9 + +/* Bit Definition for QD_PHY_AUTONEGO_AD_REG */ +#define QD_PHY_NEXTPAGE 0x8000 +#define QD_PHY_REMOTEFAULT 0x4000 +#define QD_PHY_PAUSE 0x400 +#define QD_PHY_100_FULL 0x100 +#define QD_PHY_100_HALF 0x80 +#define QD_PHY_10_FULL 0x40 +#define QD_PHY_10_HALF 0x20 + +#define QD_PHY_MODE_AUTO_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF | QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_100_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF) +#define QD_PHY_MODE_10_AUTO (QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_AUTO_FULL (QD_PHY_100_FULL | QD_PHY_10_FULL) +#define QD_PHY_MODE_AUTO_HALF (QD_PHY_100_HALF | QD_PHY_10_HALF) + +#define QD_PHY_MODE_100_FULL QD_PHY_100_FULL +#define QD_PHY_MODE_100_HALF QD_PHY_100_HALF +#define QD_PHY_MODE_10_FULL QD_PHY_10_FULL +#define QD_PHY_MODE_10_HALF QD_PHY_10_HALF + +/* Bit definition for QD_PHY_INT_ENABLE_REG */ +#define QD_PHY_INT_SPEED_CHANGED 0x4000 +#define QD_PHY_INT_DUPLEX_CHANGED 0x2000 +#define QD_PHY_INT_PAGE_RECEIVED 0x1000 +#define QD_PHY_INT_AUTO_NEG_COMPLETED 0x800 +#define QD_PHY_INT_LINK_STATUS_CHANGED 0x400 +#define QD_PHY_INT_SYMBOL_ERROR 0x200 +#define QD_PHY_INT_FALSE_CARRIER 0x100 +#define QD_PHY_INT_FIFO_FLOW 0x80 +#define QD_PHY_INT_CROSSOVER_CHANGED 0x40 +#define QD_PHY_INT_POLARITY_CHANGED 0x2 +#define QD_PHY_INT_JABBER 0x1 + +#endif /* __qdSimRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/README u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/README --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/README 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/README 2011-04-04 13:57:35.025596119 -0400 @@ -0,0 +1,28 @@ +This directory includes a test program that runs on Marvell platform, such as +DB-88E6218, RD-88E6218, DB-88E6318, and RD-88E6318 with VxWorks. +It is not part of the DSDT Driver Suite, rather, +it runs through each and every API of the Driver Suite to test it out. + +Please notes that it is provided for "Reference Only" and some of the system +specific files cannot be compiled unless related BSP is provided. + +The test program covers : + +1) How to initialize single or multiple Marvell SOHO Switchs. + msApiInit.c : Single Address Mode Device + msApiMultiInit.c : Multiple Address Mode Device + + Refer to Device DataSheet for detailed information of each Address Mode. + +2) How to utilize each APIs. (testApi.c) + +3) How to provide two platform specific MII access routines. + (qdFFMii.c for 88E6218 board, ev96122mii.c for EV-96122 board) + +4) How to enable SOHO Switch Interrupt, if applicable. (qdInt.c) + +5) How to run VCT(Virtual Cable Tester) test. (vctTest.c) + +6) How to provide Semaphore routines if required. (osSem.c) + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/sampleTest.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/sampleTest.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/sampleTest.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/sampleTest.c 2011-04-04 13:57:35.025596119 -0400 @@ -0,0 +1,447 @@ +#include +/******************************************************************************** +* sample.c +* +* DESCRIPTION: +* This is a sample program shows how to use DSDT APIs. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + +#define N_OF_QD_DEVICES 2 +extern GT_QD_DEV *qdMultiDev[N_OF_QD_DEVICES]; + +GT_STATUS qdMultiDevStart(); +GT_STATUS sampleIsolatedCPUPort(GT_QD_DEV *dev, GT_U8* macAddr); +GT_STATUS setTagMode(int vid, char* tag); +GT_STATUS crossChipTrunkSetup(); + + +GT_STATUS enableTag() +{ + char tag[4] = {0xc0,0,0,0x1}; + setTagMode(2,tag); + return GT_OK; +} + + +GT_STATUS sampleTest() +{ + GT_U8 macAddr[6] = {0x0,0x23,0x45,0x67,0x89,0xab}; + qdMultiDevStart(); + enableTag(); + sampleIsolatedCPUPort(qdMultiDev[0],macAddr); + crossChipTrunkSetup(); + return GT_OK; +} + +/* + 0) Remove CPU port from VLAN Member Table. + (this sample deals with Port Based Vlan only.) + 1) Mirror ARPs to the CPU with To_CPU Marvell Tag + 2) Convert unicast frames directed to the CPU into To_CPU Marvell Tag + Assumption : Device ID, Cascading Port, CPU Port, and Interswitch Port are + already set properly. For more information, please refer to the + sample/MultiDevice/msApiInit.c +*/ + +GT_STATUS sampleIsolatedCPUPort(GT_QD_DEV *dev, GT_U8* macAddr) +{ + GT_STATUS status; + int i; + GT_LPORT memPorts[16], cpuPort; + GT_U8 memPortsLen, index; + GT_ATU_ENTRY macEntry; + + cpuPort = (GT_LPORT)dev->cpuPortNum; + + /* + * Remove CPU port from VLAN Member Table. + */ + for(i=0; inumOfPorts; i++) + { + if((status = gvlnGetPortVlanPorts(dev,(GT_LPORT)i,memPorts,&memPortsLen)) != GT_OK) + { + MSG_PRINT(("gvlnGetPortVlanPorts return Failed\n")); + return status; + } + + for(index=0; indexcpuPortNum; + macEntry.prio = 0; /* Priority (2bits). When these bits are used they override + any other priority determined by the frame's data */ + macEntry.entryState.ucEntryState = GT_UC_TO_CPU_STATIC; + macEntry.DBNum = 0; + macEntry.trunkMember = GT_FALSE; + + if((status = gfdbAddMacEntry(dev,&macEntry)) != GT_OK) + { + MSG_PRINT(("gsysSetARPDest return Failed\n")); + return status; + } + + + return GT_OK; +} + + +/* + Assumption 1: Device ID, Cascading Port, CPU Port, and Interswitch Port are + already set properly. For more information, please refer to the + sample/MultiDevice/msApiInit.c + + Assumption 2: Port 0,1,2 of Device 0 and Port 0 of Device 1 are member of a + trunk with Trunk ID 1. +*/ + +GT_STATUS sampleFixedCrossChipTrunk(GT_QD_DEV *dev[]) +{ + GT_STATUS status; + int i; + GT_U32 mask, trunkBit, trunkId; + + /* + * Enable Trunk for each member of the Trunk and set the Trunk ID (1). + */ + + trunkId = 1; + + if((dev[0] == NULL) || (!dev[0]->devEnabled)) + { + printf("Device 0 is not initialized\n"); + return GT_FAIL; + } + if((dev[1] == NULL) || (!dev[1]->devEnabled)) + { + printf("Device 1 is not initialized\n"); + return GT_FAIL; + } + + /* setup for Device 0 port 0 */ + if((status = gprtSetTrunkPort(dev[0],0,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 0 port 1 */ + if((status = gprtSetTrunkPort(dev[0],1,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 0 port 2 */ + if((status = gprtSetTrunkPort(dev[0],2,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 1 port 0 */ + if((status = gprtSetTrunkPort(dev[1],0,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + + /* + * Set Trunk Route Table for the given Trunk ID. + */ + + /* setup for Device 0, trunk ID 1 : port 0,1,2, and 9 (cascading port, assumption1) */ + if((status = gsysSetTrunkRouting(dev[0],trunkId,0x7|0x200)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + + /* setup for Device 1, trunk ID 1 : port 0, and 8 (cascading port, assumption1) */ + if((status = gsysSetTrunkRouting(dev[1],trunkId,0x1|0x100)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + + + /* + * Set Trunk Mask Table for load balancing. + */ + + /* + Trunk Mask Table for Device 0: + + 10 9 8 7 6 5 4 3 2 1 0 + TrunkMask[0] 1 1 1 1 1 1 1 1 0 0 1 + TrunkMask[1] 1 1 1 1 1 1 1 1 0 1 0 + TrunkMask[2] 1 1 1 1 1 1 1 1 1 0 0 + TrunkMask[3] 1 1 1 1 1 1 1 1 0 0 0 + TrunkMask[4] 1 1 1 1 1 1 1 1 0 0 1 + TrunkMask[5] 1 1 1 1 1 1 1 1 0 1 0 + TrunkMask[6] 1 1 1 1 1 1 1 1 1 0 0 + TrunkMask[7] 1 1 1 1 1 1 1 1 0 0 0 + + + Trunk Mask Table for Device 1: + + 10 9 8 7 6 5 4 3 2 1 0 + TrunkMask[0] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[1] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[2] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[3] 1 1 1 1 1 1 1 1 1 1 1 + TrunkMask[4] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[5] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[6] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[7] 1 1 1 1 1 1 1 1 1 1 1 + + */ + + /* setup for Device 0 */ + for(i=0; i<8; i++) + { + if((i%4) == 3) + { + trunkBit = 0; + } + else + { + trunkBit = 1 << (i%4); + } + + mask = 0x7F8 | trunkBit; + + if((status = gsysSetTrunkMaskTable(dev[0],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + + } + + /* setup for Device 1 */ + for(i=0; i<8; i++) + { + if((i%4) == 3) + { + trunkBit = 1; + } + else + { + trunkBit = 0; + } + + mask = 0x7FE | trunkBit; + + if((status = gsysSetTrunkMaskTable(dev[1],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + + } + return GT_OK; +} + +#define MAX_PORT_IN_TRUNK 4 + +typedef struct _TRUNK_SET { + GT_U32 devIndex; + GT_U32 port; +} TRUNK_SET; + +typedef struct _TRUNK_MEMBER { + GT_U32 trunkId; + GT_U32 nTrunkPort; + TRUNK_SET trunkSet[MAX_PORT_IN_TRUNK]; +} TRUNK_MEMBER; + +GT_STATUS sampleCrossChipTrunk(GT_QD_DEV *dev[], TRUNK_MEMBER* tm); + +/* + Setup Trunk with the following member ports: + Port 0,1,2 of Device 0, and + Port 0 of Device 1, + where Device 0 is the first Switch Device Structure in qdMultiDev array + and Device 1 is the second Switch Device Structure in qdMultiDev array. +*/ +GT_STATUS crossChipTrunkSetup() +{ + TRUNK_MEMBER tm; + + tm.trunkId = 1; + tm.nTrunkPort = 4; + tm.trunkSet[0].devIndex = 0; + tm.trunkSet[0].port = 0; + tm.trunkSet[1].devIndex = 0; + tm.trunkSet[1].port = 1; + tm.trunkSet[2].devIndex = 0; + tm.trunkSet[2].port = 2; + tm.trunkSet[3].devIndex = 1; + tm.trunkSet[3].port = 0; + + return sampleCrossChipTrunk(qdMultiDev, &tm); +} + +GT_STATUS sampleCrossChipTrunk(GT_QD_DEV *dev[], TRUNK_MEMBER* tm) +{ + GT_STATUS status; + int i,j,index; + GT_U32 mask, trunkId; + TRUNK_SET* ts; + GT_U32 portVec[N_OF_QD_DEVICES]; + GT_U32 casecadeVec = 0xC0; /* Port 6 and 7. ToDo : get this value from user or device */ + + /* + * Enable Trunk for each member of the Trunk and set the Trunk ID (1). + */ + + printf("Setting TRUNK\n"); + printf("Trunk ID : %i\n",(unsigned int)tm->trunkId); + printf("N Ports : %i\n",(unsigned int)tm->nTrunkPort); + printf("1st Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[0].devIndex,(unsigned int)tm->trunkSet[0].port); + printf("2nd Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[1].devIndex,(unsigned int)tm->trunkSet[1].port); + printf("3rd Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[2].devIndex,(unsigned int)tm->trunkSet[2].port); + printf("4th Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[3].devIndex,(unsigned int)tm->trunkSet[3].port); + + trunkId = tm->trunkId; + + for(i=0; inTrunkPort; i++) + { + ts = &tm->trunkSet[i]; + + if(ts->devIndex >= N_OF_QD_DEVICES) + { + printf("Device %i is supported. Max Device Number is %i\n",(unsigned int)ts->devIndex,N_OF_QD_DEVICES-1); + return GT_FAIL; + } + + if((dev[ts->devIndex] == NULL) || (!dev[ts->devIndex]->devEnabled)) + { + printf("Device %i is not initialized\n",(unsigned int)ts->devIndex); + return GT_FAIL; + } + + /* enabled trunk on the given port */ + if((status = gprtSetTrunkPort(dev[ts->devIndex],ts->port,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + portVec[ts->devIndex] |= (1 << ts->port); + } + + /* + * Set Trunk Route Table for the given Trunk ID. + */ + printf("Setting TRUNK Routing Table\n"); + for(i=0; idevEnabled)) + { + printf("Device %i is not initialized\n",i); + break; + } + + if((status = gsysSetTrunkRouting(dev[i],trunkId,portVec[i]|casecadeVec)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + } + + /* + * Set Trunk Mask Table for load balancing. + */ + printf("Setting TRUNK Mask for Load Balancing\n"); + for(i=0; i<8; i++) + { + /* choose a port to be used for the given addr combo index */ + index = i % tm->nTrunkPort; + ts = &tm->trunkSet[index]; + + for(j=0; jdevEnabled)) + { + printf("Device %i is not initialized\n",j); + continue; + } + + if(portVec[j] == 0) + continue; + + if((status = gsysGetTrunkMaskTable(dev[j],i,&mask)) != GT_OK) + { + MSG_PRINT(("gsysGetTrunkMaskTable return Failed\n")); + return status; + } + + mask &= ~portVec[j]; + + if(ts->devIndex == j) + mask |= (1 << ts->port); + + if((status = gsysSetTrunkMaskTable(dev[j],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + } + } + + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/testApi.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/testApi.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/testApi.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/testApi.c 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,8717 @@ +#include +/******************************************************************************** +* testApi.c +* +* DESCRIPTION: +* API test functions +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +/* +#define TEST_DEBUG +*/ +#define MAX_TEST_RUN 16 + +ATU_ENTRY_INFO *gAtuEntry = NULL; +int gAgeDelayTime = 0; + +GT_U32 testSysCtrl(GT_QD_DEV *dev); +GT_U32 testPort(GT_QD_DEV *dev); +GT_U32 testATU(GT_QD_DEV *dev); +GT_U32 testVlan(GT_QD_DEV *dev); +GT_U32 testSTP(GT_QD_DEV *dev); +GT_U32 testPhy(GT_QD_DEV *dev); +GT_U32 testPortStatus(GT_QD_DEV *dev); +GT_U32 testQoSRule(GT_QD_DEV *dev); +GT_U32 testQoSMap(GT_QD_DEV *dev); +GT_U32 testRMON(GT_QD_DEV *dev); +GT_U32 testVTU(GT_QD_DEV *dev); +GT_U32 testSysStatus(GT_QD_DEV *dev); +GT_U32 testPortRateCtrl(GT_QD_DEV *dev); +GT_U32 testPortPAV(GT_QD_DEV *dev); +GT_U32 testInterrupt(GT_QD_DEV *dev); +GT_U32 testPCSCtrl(GT_QD_DEV *dev); +GT_U32 testPIRL(GT_QD_DEV *dev); + +TEST_STRUCT testStruct[] = + { + {"SysCtrl :", testSysCtrl, 0}, + {"PortCtrl :", testPort, 0}, + {"ATU :", testATU, 0}, + {"VLAN :", testVlan, 0}, + {"STP :", testSTP, 0}, + {"PhyCtrl :", testPhy, 0}, + {"Port Status:", testPortStatus, 0}, + {"QoS Rule :", testQoSRule, 0}, + {"QoS Map :", testQoSMap, 0}, + {"RMON :", testRMON, 0}, + {"VTU :", testVTU, 0}, + {"Sys Status :", testSysStatus, 0}, + {"Port Rate :", testPortRateCtrl, 0}, + {"Port PAV :", testPortPAV, 0}, + {"PCSCtrl :", testPCSCtrl, 0}, + /*Interrupt is tested only on simulator + {"Interrupt :", testInterrupt, GT_OK}, + */ + {"PIRL :", testPIRL, 0}, + {"", NULL,GT_OK} + }; +#if 0 +TEST_STRUCT testStructG[] = + { + {"SysCtrl(G) :", testSysCtrlG, 0}, + {"PortCtrl(G) :", testPortG, 0}, + {"ATU(G) :", testATUG, 0}, + {"VLAN(G) :", testVlanG, 0}, + {"STP(G) :", testSTPG, 0}, + {"PhyCtrl(G) :", testPhyG, 0}, + {"Port Status(G):", testPortStatusG, 0}, + {"QoS Rule(G) :", testQoSRuleG, 0}, + {"QoS Map(G) :", testQoSMapG, 0}, + {"RMON(G) :", testRMONG, 0}, + {"VTU(G) :", testVTUG, 0}, + {"Sys Status(G) :", testSysStatusG, 0}, + {"Port Rate(G) :", testPortRateCtrlG, 0}, + {"Port PAV(G) :", testPortPAVG, 0}, + /*Interrupt is tested only on simulator + {"Interrupt :", testInterrupt, GT_OK}, + */ + {"", NULL,GT_OK} + }; +#endif + +void testDisplayStatus(GT_STATUS status) +{ + switch(status) + { + case GT_OK : + MSG_PRINT(("Passed.\n")); + break; + case GT_FAIL : + MSG_PRINT(("Failed.\n")); + break; + case GT_BAD_PARAM : + MSG_PRINT(("Bad Parameter.\n")); + break; + case GT_NOT_SUPPORTED : + MSG_PRINT(("Not Supported.\n")); + break; + case GT_NOT_FOUND : + MSG_PRINT(("Not Found.\n")); + break; + case GT_NO_MORE : + MSG_PRINT(("No more Item.\n")); + break; + case GT_NO_SUCH : + MSG_PRINT(("No Such Item.\n")); + break; + default: + MSG_PRINT(("Failed.\n")); + break; + } +} + +void printATUEntry(GT_ATU_ENTRY *entry) +{ + MSG_PRINT(("(%02x-%02x-%02x-%02x-%02x-%02x), DBNum %i, PortVec %#x, Pri %#x, State %#x\n", + entry->macAddr.arEther[0], + entry->macAddr.arEther[1], + entry->macAddr.arEther[2], + entry->macAddr.arEther[3], + entry->macAddr.arEther[4], + entry->macAddr.arEther[5], + entry->DBNum, + entry->portVec, + entry->prio, + entry->entryState.mcEntryState)); +} + +void dumpMemory(char* startAddr, int length) +{ int i; + + printf("\n"); + while(length>16) + { + for(i=0; i<16; i++) + printf("%02x ",(unsigned char)*startAddr++); + printf("\n"); + length -= 16; + } + for(i=0; igetFunc.bool(dev,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 1 */ + if((status=api->setFunc.bool(dev,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.bool(dev,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != GT_TRUE) + { + MSG_PRINT(("Test Value Mismatch (expected GT_TRUE).\n")); + testResult = GT_FAIL; + } + + /* Set to 0 */ + if((status=api->setFunc.bool(dev,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.bool(dev,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != GT_FALSE) + { + MSG_PRINT(("Test Value Mismatch (expected GT_FALSE).\n")); + testResult = GT_FAIL; + } + + /* Set to original value */ + if((status=api->setFunc.bool(dev,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + return testResult; +} + +GT_STATUS testU16Type(GT_QD_DEV *dev, TEST_API* api, int testLimit) +{ + GT_STATUS status; + GT_U16 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + + /* Get the Original value */ + if((status=api->getFunc.u16(dev,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U16 Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U16)testLimit; i++) + { + if((status=api->setFunc.u16(dev,i)) != GT_OK) + { + MSG_PRINT(("Writing U16 Value Failed (%#x, value %i).\n", status,i)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.u16(dev,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U16 Value Failed (%#x, value %i).\n", status,i)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("Test Value Mismatch (write %i, read %i).\n",i,tmpValue)); + testResult = GT_FAIL; + } + } + + /* Set to original value */ + if((status=api->setFunc.u16(dev,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing U16 Value Failed (%#x, org value %i).\n", status, orgValue)); + return status; + } + + return testResult; +} + + +GT_STATUS testU32Type(GT_QD_DEV *dev, TEST_API* api, int testLimit) +{ + GT_STATUS status; + GT_U32 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + + /* Get the Original value */ + if((status=api->getFunc.u32(dev,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U32)testLimit; i++) + { + if((status=api->setFunc.u32(dev,i)) != GT_OK) + { + MSG_PRINT(("Writing U32 Value Failed (%#x, value %i).\n", status,i)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.u32(dev,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Value Failed (%#x, value %i).\n", status,i)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("Test Value Mismatch (write %i, read %i).\n",i,tmpValue)); + testResult = GT_FAIL; + } + } + + /* Set to original value */ + if((status=api->setFunc.u32(dev,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing U32 Value Failed (%#x, org value %i).\n", status, orgValue)); + return status; + } + + return testResult; +} + + +GT_STATUS testMacType(GT_QD_DEV *dev, TEST_API* api) +{ + GT_STATUS status; + GT_ETHERADDR orgMac, tmpMacIn, tmpMacOut; + GT_STATUS testResult = GT_OK; + + /* Get the Discard Excessive state */ + if((status=api->getFunc.mac(dev,&orgMac)) != GT_OK) + { + MSG_PRINT(("Reading MAC Address Failed (%#x).\n", status)); + return status; + } + + tmpMacIn.arEther[0] = 0xAA; + tmpMacIn.arEther[1] = 0xAA; + tmpMacIn.arEther[2] = 0xAA; + tmpMacIn.arEther[3] = 0xAA; + tmpMacIn.arEther[4] = 0xAA; + tmpMacIn.arEther[5] = 0xAA; + + /* Set the Discard Excessive state */ + if((status=api->setFunc.mac(dev,&tmpMacIn)) != GT_OK) + { + MSG_PRINT(("Writing MAC Address Failed (%#x).\n", status)); + return status; + } + + /* Get the Discardl Excessive state */ + if((status=api->getFunc.mac(dev,&tmpMacOut)) != GT_OK) + { + MSG_PRINT(("Reading MAC Address Failed (%#x).\n", status)); + return status; + } + + if(memcmp(&tmpMacIn,&tmpMacOut,6) != 0) + { + MSG_PRINT(("Unexpected MAC address(%#x-%#x-%#x-%#x-%#x-%#x)\n", + tmpMacOut.arEther[0], + tmpMacOut.arEther[1], + tmpMacOut.arEther[2], + tmpMacOut.arEther[3], + tmpMacOut.arEther[4], + tmpMacOut.arEther[5])); + + testResult = GT_FAIL; + } + + tmpMacIn.arEther[0] = 0x54; + tmpMacIn.arEther[1] = 0x55; + tmpMacIn.arEther[2] = 0x55; + tmpMacIn.arEther[3] = 0x55; + tmpMacIn.arEther[4] = 0x55; + tmpMacIn.arEther[5] = 0x55; + + /* Set the Discard Excessive state */ + if((status=api->setFunc.mac(dev,&tmpMacIn)) != GT_OK) + { + MSG_PRINT(("Writing MAC Address Failed (%#x).\n", status)); + return status; + } + + /* Get the Discardl Excessive state */ + if((status=api->getFunc.mac(dev,&tmpMacOut)) != GT_OK) + { + MSG_PRINT(("Reading MAC Address Failed (%#x).\n", status)); + return status; + } + + if(memcmp(&tmpMacIn,&tmpMacOut,6) != 0) + { + MSG_PRINT(("Unexpected MAC address(%#x-%#x-%#x-%#x-%#x-%#x)\n", + tmpMacOut.arEther[0], + tmpMacOut.arEther[1], + tmpMacOut.arEther[2], + tmpMacOut.arEther[3], + tmpMacOut.arEther[4], + tmpMacOut.arEther[5])); + + testResult = GT_FAIL; + } + + tmpMacIn.arEther[0] = 0x00; + tmpMacIn.arEther[1] = 0x00; + tmpMacIn.arEther[2] = 0x00; + tmpMacIn.arEther[3] = 0x00; + tmpMacIn.arEther[4] = 0x00; + tmpMacIn.arEther[5] = 0x01; + + /* Set the Discard Excessive state */ + if((status=api->setFunc.mac(dev,&tmpMacIn)) != GT_OK) + { + MSG_PRINT(("Writing MAC Address Failed (%#x).\n", status)); + return status; + } + + /* Get the Discardl Excessive state */ + if((status=api->getFunc.mac(dev,&tmpMacOut)) != GT_OK) + { + MSG_PRINT(("Reading MAC Address Failed (%#x).\n", status)); + return status; + } + + if(memcmp(&tmpMacIn,&tmpMacOut,6) != 0) + { + MSG_PRINT(("Unexpected MAC address(%#x-%#x-%#x-%#x-%#x-%#x)\n", + tmpMacOut.arEther[0], + tmpMacOut.arEther[1], + tmpMacOut.arEther[2], + tmpMacOut.arEther[3], + tmpMacOut.arEther[4], + tmpMacOut.arEther[5])); + + testResult = GT_FAIL; + } + + /* Set the Discard Excessive state with original value */ + if((status=api->setFunc.mac(dev,&orgMac)) != GT_OK) + { + MSG_PRINT(("Writing MAC Address Failed (%#x).\n", status)); + return status; + } + + return testResult; +} + + +GT_STATUS testPortBoolType(GT_QD_DEV *dev, TEST_API* api) +{ + GT_STATUS status; + GT_BOOL orgValue, tmpValue; + GT_STATUS testResult = GT_OK; + GT_LPORT port; + int portIndex; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + /* Get the Original value */ + if((status=api->getFunc.port_bool(dev,port,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 1 */ + if((status=api->setFunc.port_bool(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_bool(dev,port,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != GT_TRUE) + { + MSG_PRINT(("Test Value Mismatch (expected GT_TRUE).\n")); + testResult = GT_FAIL; + } + + /* Set to 0 */ + if((status=api->setFunc.port_bool(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_bool(dev,port,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading Bool Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != GT_FALSE) + { + MSG_PRINT(("Test Value Mismatch (expected GT_FALSE).\n")); + testResult = GT_FAIL; + } + + /* Set to original value */ + if((status=api->setFunc.port_bool(dev,port,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing Bool Value Failed (%#x).\n", status)); + return status; + } + + if (testResult != GT_OK) + return testResult; + + } + return testResult; +} + + +GT_STATUS testPortU8Type(GT_QD_DEV *dev, TEST_API* api, int testLimit) +{ + GT_STATUS status; + GT_U8 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + GT_LPORT port; + int portIndex; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + /* Get the Original value */ + if((status=api->getFunc.port_u8(dev,port,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U8 Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U8)testLimit; i++) + { + if((status=api->setFunc.port_u8(dev,port,i)) != GT_OK) + { + MSG_PRINT(("Writing U8 Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_u8(dev,port,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U8 Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("U16 Value Mismatch (port %i, write %#x, read %#x).\n", portIndex,i,tmpValue)); + testResult = GT_FAIL; + } + } + + /* Set to original value */ + if((status=api->setFunc.port_u8(dev,port,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing U8 Value Failed (%#x).\n", status)); + return status; + } + + if (testResult != GT_OK) + return testResult; + + } + return testResult; +} + +GT_STATUS testPortU16Type(GT_QD_DEV *dev, TEST_API* api, int testLimit) +{ + GT_STATUS status; + GT_U16 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + GT_LPORT port; + int portIndex; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + /* Get the Original value */ + if((status=api->getFunc.port_u16(dev,port,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U16 Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U16)testLimit; i++) + { + if((status=api->setFunc.port_u16(dev,port,i)) != GT_OK) + { + MSG_PRINT(("Writing U16 Value Failed (%#x).\n", status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_u16(dev,port,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U16 Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("U16 Value Mismatch (port %i, write %#x, read %#x).\n", portIndex,i,tmpValue)); + testResult = GT_FAIL; + return GT_FAIL; /* MJ Temp */ + } + } + + /* Set to original value */ + if((status=api->setFunc.port_u16(dev,port,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing U16 Value Failed (%#x).\n", status)); + return status; + } + + if (testResult != GT_OK) + return testResult; + + } + return testResult; +} + +GT_STATUS testPortU32Type(GT_QD_DEV *dev, TEST_API* api, int testLimit) +{ + GT_STATUS status; + GT_U32 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + GT_LPORT port; + int portIndex; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + /* Get the Original value */ + if((status=api->getFunc.port_u32(dev,port,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U32)testLimit; i++) + { + if((status=api->setFunc.port_u32(dev,port,i)) != GT_OK) + { + MSG_PRINT(("Writing U32 Value Failed (port%i,data%i,%#x).\n", port,i,status)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_u32(dev,port,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Value Failed (%#x).\n", status)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("U16 Value Mismatch (port %i, write %#x, read %#x).\n", port,i,tmpValue)); + testResult = GT_FAIL; + } + } + + /* Set to original value */ + if((status=api->setFunc.port_u32(dev,port,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing Org Value Failed (value %i,%#x).\n", orgValue,status)); + return status; + } + + if (testResult != GT_OK) + return testResult; + + } + return testResult; +} + +GT_STATUS testU32U32Type(GT_QD_DEV *dev, TEST_API* api, int indexLimit, int testLimit) +{ + GT_STATUS status; + GT_U32 orgValue, tmpValue, i; + GT_STATUS testResult = GT_OK; + int index; + + for(index=0; indexgetFunc.port_u32(dev,index,&orgValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Org Value Failed (%#x).\n", status)); + return status; + } + + /* Set to 0 */ + for(i=0; i<(GT_U32)testLimit; i++) + { + if((status=api->setFunc.port_u32(dev,index,i)) != GT_OK) + { + MSG_PRINT(("Writing U32 Value Failed (%#x) index:%i,value:%i.\n", status,index,i)); + return status; + } + + /* Get the modified value */ + if((status=api->getFunc.port_u32(dev,index,&tmpValue)) != GT_OK) + { + MSG_PRINT(("Reading U32 Value Failed (%#x) index:%i,value:%i.\n", status,index,i)); + return status; + } + + if(tmpValue != i) + { + MSG_PRINT(("U16 Value Mismatch (index %i, write %#x, read %#x).\n", index,i,tmpValue)); + testResult = GT_FAIL; + } + } + + /* Set to original value */ + if((status=api->setFunc.port_u32(dev,index,orgValue)) != GT_OK) + { + MSG_PRINT(("Writing U32 Org Value Failed (%#x) index:%i,value:%i.\n", status,index,orgValue)); + return status; + } + + if (testResult != GT_OK) + return testResult; + + } + return testResult; +} + +GT_STATUS testTrunkPortSetup(GT_QD_DEV *dev, int portIndex) +{ + GT_STATUS status; + GT_U32 orgTrunkId, trunkId, tmpId; + GT_LPORT port; + GT_BOOL orgEn, tmpEn; + + port = (GT_LPORT)portIndex; + + if((status = gprtGetTrunkPort(dev,port,&orgEn,&orgTrunkId)) != GT_OK) + { + MSG_PRINT(("Getting Org. TrunkPort setup failed (port%i, status:%#x).\n", port,status)); + return status; + } + + for(trunkId=0; trunkId<16; trunkId++) + { + if((status = gprtSetTrunkPort(dev,port,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("Setting TrunkPort setup failed (port%i,trunkId:%i,status:%#x).\n", port,trunkId,status)); + return status; + } + + if((status = gprtGetTrunkPort(dev,port,&tmpEn,&tmpId)) != GT_OK) + { + MSG_PRINT(("Getting TrunkPort setup failed (port%i, status:%#x).\n", port,status)); + return status; + } + + if((tmpEn != GT_TRUE) || (tmpId != trunkId)) + { + MSG_PRINT(("TrunkPort Enable failed (ID:%i,%i).\n", trunkId,tmpId)); + return status; + } + + } + + if((status = gprtSetTrunkPort(dev,port,GT_FALSE,trunkId)) != GT_OK) + { + MSG_PRINT(("Setting TrunkPort setup failed (port%i,trunkId:%i,status:%#x).\n", port,trunkId,status)); + return status; + } + + if((status = gprtGetTrunkPort(dev,port,&tmpEn,&tmpId)) != GT_OK) + { + MSG_PRINT(("Getting TrunkPort setup failed (port%i, status:%#x).\n", port,status)); + return status; + } + + if(tmpEn != GT_FALSE) + { + MSG_PRINT(("TrunkPort Disable failed (En:%i,%i).\n", GT_FALSE,tmpEn)); + return status; + } + + if((status = gprtSetTrunkPort(dev,port,orgEn,orgTrunkId)) != GT_OK) + { + MSG_PRINT(("Setting TrunkPort setup failed (port%i,trunkId:%i,status:%#x).\n", port,trunkId,status)); + return status; + } + + return GT_OK; +} + +GT_U32 testSysCtrlG(GT_QD_DEV *dev ) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + GT_U32 data; + TEST_API testAPI; + + /* + * PPU Setup API + */ + testAPI.getFunc.bool = gsysGetPPUEn; + testAPI.setFunc.bool = gsysSetPPUEn; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("PPU Setup API test ")); + testDisplayStatus(status); + + /* + * Cascade Port Setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetCascadePort; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetCascadePort; + if((status = testU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Cascade Port Setup API test ")); + testDisplayStatus(status); + /* + * Device Number Setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetDeviceNumber; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetDeviceNumber; + if((status = testU32Type(dev,&testAPI,32)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Device Number Setup API test ")); + testDisplayStatus(status); + + /* + * Core Tag Type setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetCoreTagType; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetCoreTagType; + if((status = testU16Type(dev,&testAPI,64)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Core Tag Type Setup API test ")); + testDisplayStatus(status); + + /* + * IngressMonitorDest setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetIngressMonitorDest; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetIngressMonitorDest; + if((status = testU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IngressMonitorDest Setup API test ")); + testDisplayStatus(status); + + /* + * EngressMonitorDest setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetEgressMonitorDest; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetEgressMonitorDest; + if((status = testU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("EngressMonitorDest Setup API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + return testResults; + default: + break; + } + + /* + * ARPDest setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetARPDest; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetARPDest; + if((status = testU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ARPDest Setup API test ")); + testDisplayStatus(status); + + /* + * Rsvd2CpuEnables setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetRsvd2CpuEnables; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetRsvd2CpuEnables; + if((status = testU16Type(dev,&testAPI,0x8001)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Rsvd2CpuEnables Setup API test ")); + testDisplayStatus(status); + + /* + * Rsvd2Cpu setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetRsvd2Cpu; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetRsvd2Cpu; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Rsvd2Cpu Setup API test ")); + testDisplayStatus(status); + + /* + * MGMTPri setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetMGMTPri; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetMGMTPri; + if((status = testU16Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MGMTPri Setup API test ")); + testDisplayStatus(status); + + /* + * UseDoubleTagData setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetUseDoubleTagData; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetUseDoubleTagData; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("UseDoubleTagData Setup API test ")); + testDisplayStatus(status); + + /* + * PreventLoops setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetPreventLoops; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetPreventLoops; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("PreventLoops Setup API test ")); + testDisplayStatus(status); + + /* + * FlowControlMessage setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetFlowControlMessage; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetFlowControlMessage; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FlowControlMessage Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetForceFlowControlPri setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetForceFlowControlPri; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetForceFlowControlPri; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ForceFlowControlPri Setup API test ")); + testDisplayStatus(status); + + /* + * FcPri setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetFCPri; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetFCPri; + if((status = testU16Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FCPri Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetHashTrunk setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetHashTrunk; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetHashTrunk; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("HashTrunk Setup API test ")); + testDisplayStatus(status); + + /* + * FlowCtrlDelay Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gsysGetFlowCtrlDelay; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gsysSetFlowCtrlDelay; + if((status = testU32U32Type(dev,&testAPI,3,0x2000)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FlowCtrlDelay Setup API test ")); + testDisplayStatus(status); + + /* + * DevRoutingTable Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gsysGetDevRoutingTable; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gsysSetDevRoutingTable; + if((status = testU32U32Type(dev,&testAPI,32,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DevRoutingTable Setup API test ")); + testDisplayStatus(status); + + /* + * TrunkMaskTable Setup + */ + switch (dev->deviceId) + { + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + data = 4; + break; + default: + data = 8; + break; + } + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gsysGetTrunkMaskTable; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gsysSetTrunkMaskTable; + if((status = testU32U32Type(dev,&testAPI,data,(1<<(dev->numOfPorts-1)))) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("TrunkMaskTable Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetTrunkRouting Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gsysGetTrunkRouting; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gsysSetTrunkRouting; + if((status = testU32U32Type(dev,&testAPI,8,(1<<(dev->numOfPorts-1)))) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("TrunkRouting Setup API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6092: + case GT_88E6095: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + if (dev->revision < 2) + return testResults; + break; + case GT_88E6131: + case GT_88E6108: + default: + break; + } + + /* + * gsysSetRateLimitMode Setup + */ + testAPI.getFunc.bool = (GT_API_GET_BOOL)gsysGetRateLimitMode; + testAPI.setFunc.bool = (GT_API_SET_BOOL)gsysSetRateLimitMode; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Rate Limit Mode Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetAgeInt Setup + */ + testAPI.getFunc.bool = gsysGetAgeInt; + testAPI.setFunc.bool = gsysSetAgeInt; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Age Interrupt Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetForceSnoopPri setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetForceSnoopPri; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetForceSnoopPri; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ForceSnoopPri Setup API test ")); + testDisplayStatus(status); + + /* + * Snoop Pri setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetSnoopPri; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetSnoopPri; + if((status = testU16Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Snoop Pri Setup API test ")); + testDisplayStatus(status); + + /* + * gsysSetForceARPPri setup API + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetForceARPPri; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetForceARPPri; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ForceARPPri Setup API test ")); + testDisplayStatus(status); + + /* + * ARP Pri setup API + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gsysGetARPPri; + testAPI.setFunc.u16 = (GT_API_SET_U16)gsysSetARPPri; + if((status = testU16Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ARP Pri Setup API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6131: + case GT_88E6108: + return testResults; + default: + break; + } + + /* + * Use Port Schedule API + */ + testAPI.getFunc.bool = gsysGetUsePortSchedule; + testAPI.setFunc.bool = gsysSetUsePortSchedule; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Use Port Schedule API test ")); + testDisplayStatus(status); + + /* + * Use Old Header API + */ + testAPI.getFunc.bool = gsysGetOldHader; + testAPI.setFunc.bool = gsysSetOldHader; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Use Old Header API test ")); + testDisplayStatus(status); + + /* + * Recursive Stripping Disable API + */ + testAPI.getFunc.bool = gsysGetRecursiveStrippingDisable; + testAPI.setFunc.bool = gsysSetRecursiveStrippingDisable; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Recursive Stripping Disable API test ")); + testDisplayStatus(status); + + /* + * CPU Port + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gsysGetCPUPort; + testAPI.setFunc.u32 = (GT_API_SET_U32)gsysSetCPUPort; + if((status = testU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("CPU Port API test ")); + testDisplayStatus(status); + + return testResults; +} + +GT_U32 testSysCtrl(GT_QD_DEV *dev ) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + /* Sw Reset */ + if((status=gsysSwReset(dev)) != GT_OK) + { + MSG_PRINT(("gsysSwReset returned Fail (%#x).\n", status)); + testResults |= 1 << status; + return testResults; + } + testResult = GT_OK; + + /* + * Testing Discard Excessive State API + */ + testAPI.getFunc.bool = gsysGetDiscardExcessive; + testAPI.setFunc.bool = gsysSetDiscardExcessive; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DiscardExcessive API test ")); + testDisplayStatus(status); + + /* + * Testing Scheduling Mose API + */ + testAPI.getFunc.bool = gsysGetSchedulingMode; + testAPI.setFunc.bool = gsysSetSchedulingMode; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Scheduling Mode API test ")); + testDisplayStatus(status); + + + /* + * Testing Max Frame Size API + */ + testAPI.getFunc.bool = gsysGetMaxFrameSize; + testAPI.setFunc.bool = gsysSetMaxFrameSize; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MAX Frame Size API test ")); + testDisplayStatus(status); + + + /* + * Testing WatchDog API + */ + testAPI.getFunc.bool = gsysGetWatchDog; + testAPI.setFunc.bool = gsysSetWatchDog; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("WatchDog API test ")); + testDisplayStatus(status); + + + /* + * Testing PerPortDuplexPauseMac API + */ + testAPI.getFunc.bool = gsysGetPerPortDuplexPauseMac; + testAPI.setFunc.bool = gsysSetPerPortDuplexPauseMac; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Per Port Duplex Pause Mac API test ")); + testDisplayStatus(status); + + +#if 0 + /* + * Retransmit Mode API + */ + testAPI.getFunc.bool = gsysGetRetransmitMode; + testAPI.setFunc.bool = gsysSetRetransmitMode; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Retransmit Mode API test ")); + testDisplayStatus(status); + + /* + * Limit Backoff API + */ + testAPI.getFunc.bool = gsysGetLimitBackoff; + testAPI.setFunc.bool = gsysSetLimitBackoff; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Limit Backoff API test ")); + testDisplayStatus(status); + + /* + * Rsv Queue's Request Priority API + */ + testAPI.getFunc.bool = gsysGetRsvReqPri; + testAPI.setFunc.bool = gsysSetRsvReqPri; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Rsv Queue's Request Priority API test ")); + testDisplayStatus(status); +#endif + + /* + * Testing DuplexPauseMac API + */ + testAPI.getFunc.mac = gsysGetDuplexPauseMac; + testAPI.setFunc.mac = gsysSetDuplexPauseMac; + if((status = testMacType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Duplex Pause Mac API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + testResults |= testSysCtrlG(dev); + break; + default: + break; + } + +#if 0 + /* Reload EEPROM value */ + if((status=gsysReLoad(dev)) != GT_OK) + { + MSG_PRINT(("gsysReLoad returned Fail (%#x).\n", status)); + testResults |= 1 << status; + return testResults; + } +#endif + + return testResults; +} + +GT_U32 testPCSCtrl(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + testResult = GT_OK; + + /* + * Inband Auto-Nego Bypass Setup API + */ + testAPI.getFunc.port_bool = gpcsGetAnBypassMode; + testAPI.setFunc.port_bool = gpcsSetAnBypassMode; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Inband Auto-Nego Bypass Setup API test ")); + testDisplayStatus(status); + + /* + * PCS Inband Auto-Nego Setup API + */ + testAPI.getFunc.port_bool = gpcsGetPCSAnEn; + testAPI.setFunc.port_bool = gpcsSetPCSAnEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("PCS Inband Auto-Nego Setup API test ")); + testDisplayStatus(status); + + /* + * Link Value Setup + */ + testAPI.getFunc.port_bool = gpcsGetLinkValue; + testAPI.setFunc.port_bool = gpcsSetLinkValue; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Link Value Setup API test ")); + testDisplayStatus(status); + + /* + * Forced Link Setup + */ + testAPI.getFunc.port_bool = gpcsGetForcedLink; + testAPI.setFunc.port_bool = gpcsSetForcedLink; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Forced Link Setup API test ")); + testDisplayStatus(status); + + /* + * Duplex Value Setup + */ + testAPI.getFunc.port_bool = gpcsGetDpxValue; + testAPI.setFunc.port_bool = gpcsSetDpxValue; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Duplex Value Setup API test ")); + testDisplayStatus(status); + + /* + * Forced Duplex Setup + */ + testAPI.getFunc.port_bool = gpcsGetForcedDpx; + testAPI.setFunc.port_bool = gpcsSetForcedDpx; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Forced Duplex Setup API test ")); + testDisplayStatus(status); + + /* + * Forced Speed Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gpcsGetForceSpeed; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gpcsSetForceSpeed; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Forced Speed Setup API test ")); + testDisplayStatus(status); + + /* + * Flow control Value Setup + */ + testAPI.getFunc.port_bool = gpcsGetFCValue; + testAPI.setFunc.port_bool = gpcsSetFCValue; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Flow Control Value Setup API test ")); + testDisplayStatus(status); + + /* + * Forced Flow control Setup + */ + testAPI.getFunc.port_bool = gpcsGetForcedFC; + testAPI.setFunc.port_bool = gpcsSetForcedFC; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Forced Flow Control Setup API test ")); + testDisplayStatus(status); + + return testResults; +} + +GT_U32 testPortEnhancedFE(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + int portIndex; + + testResult = GT_OK; + + /* + * Drop on Lock + */ + testAPI.getFunc.port_bool = gprtGetDropOnLock; + testAPI.setFunc.port_bool = gprtSetDropOnLock; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Drop on Lock API test ")); + testDisplayStatus(status); + + /* + * Double Tag + */ + testAPI.getFunc.port_bool = gprtGetDoubleTag; + testAPI.setFunc.port_bool = gprtSetDoubleTag; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Double Tag API test ")); + testDisplayStatus(status); + + /* + * Interswitch Port + */ + testAPI.getFunc.port_bool = gprtGetInterswitchPort; + testAPI.setFunc.port_bool = gprtSetInterswitchPort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Interswith port setup API test ")); + testDisplayStatus(status); + + /* + * Learning Disable + */ + testAPI.getFunc.port_bool = gprtGetLearnDisable; + testAPI.setFunc.port_bool = gprtSetLearnDisable; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Learning Disable API test ")); + testDisplayStatus(status); + + /* + * FCS Ignore + */ + testAPI.getFunc.port_bool = gprtGetIgnoreFCS; + testAPI.setFunc.port_bool = gprtSetIgnoreFCS; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FCS Ignore API test ")); + testDisplayStatus(status); + + /* + * VTU Priority Override + */ + testAPI.getFunc.port_bool = gprtGetVTUPriOverride; + testAPI.setFunc.port_bool = gprtSetVTUPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("VTU Priority Override API test ")); + testDisplayStatus(status); + + /* + * SA Priority Override + */ + testAPI.getFunc.port_bool = gprtGetSAPriOverride; + testAPI.setFunc.port_bool = gprtSetSAPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA Priority Override API test ")); + testDisplayStatus(status); + + /* + * DA Priority Override + */ + testAPI.getFunc.port_bool = gprtGetDAPriOverride; + testAPI.setFunc.port_bool = gprtSetDAPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DA Priority Override API test ")); + testDisplayStatus(status); + + /* + * CPU Port Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetCPUPort; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetCPUPort; + if((status = testPortU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("CPU Port Setup API test ")); + testDisplayStatus(status); + + /* + * Locked Port Setup + */ + testAPI.getFunc.port_bool = gprtGetLockedPort; + testAPI.setFunc.port_bool = gprtSetLockedPort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Locked Port Setup API test ")); + testDisplayStatus(status); + + /* + * Ignore Wrong Data Setup + */ + testAPI.getFunc.port_bool = gprtGetIgnoreWrongData; + testAPI.setFunc.port_bool = gprtSetIgnoreWrongData; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Ignore Wrong Data Setup API test ")); + testDisplayStatus(status); + + /* + * UseCoreTag Setup + */ + testAPI.getFunc.port_bool = gprtGetUseCoreTag; + testAPI.setFunc.port_bool = gprtSetUseCoreTag; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("UseCoreTag Setup API test ")); + testDisplayStatus(status); + + /* + * DiscardTagged Setup + */ + testAPI.getFunc.port_bool = gprtGetDiscardTagged; + testAPI.setFunc.port_bool = gprtSetDiscardTagged; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DiscardTagged Setup API test ")); + testDisplayStatus(status); + + /* + * DiscardUntagged Setup + */ + testAPI.getFunc.port_bool = gprtGetDiscardUntagged; + testAPI.setFunc.port_bool = gprtSetDiscardUntagged; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DiscardUntagged Setup API test ")); + testDisplayStatus(status); + + /* + * MapDA Setup + */ + testAPI.getFunc.port_bool = gprtGetMapDA; + testAPI.setFunc.port_bool = gprtSetMapDA; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MapDA Setup API test ")); + testDisplayStatus(status); + + /* + * DefaultForward Setup + */ + testAPI.getFunc.port_bool = gprtGetDefaultForward; + testAPI.setFunc.port_bool = gprtSetDefaultForward; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DefaultForward Setup API test ")); + testDisplayStatus(status); + + /* + * EgressMonitorSource Setup + */ + testAPI.getFunc.port_bool = gprtGetEgressMonitorSource; + testAPI.setFunc.port_bool = gprtSetEgressMonitorSource; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("EgressMonitorSource Setup API test ")); + testDisplayStatus(status); + + /* + * IngressMonitorSource Setup + */ + testAPI.getFunc.port_bool = gprtGetIngressMonitorSource; + testAPI.setFunc.port_bool = gprtSetIngressMonitorSource; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IngressMonitorSource Setup API test ")); + testDisplayStatus(status); + + /* + * MessagePort Setup + */ + testAPI.getFunc.port_bool = gprtGetMessagePort; + testAPI.setFunc.port_bool = gprtSetMessagePort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MessagePort Setup API test ")); + testDisplayStatus(status); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + if((status = testTrunkPortSetup(dev,portIndex)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + portIndex = 0xFF; + break; + } + } + MSG_PRINT(("TrunkPort Setup API test ")); + testDisplayStatus(status); + + /* + * AGE Int Setup + */ + testAPI.getFunc.port_bool = geventGetAgeIntEn; + testAPI.setFunc.port_bool = geventSetAgeIntEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("AGE Interrupt Setup API test ")); + testDisplayStatus(status); + + /* + * SA Filtering + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetSAFiltering; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetSAFiltering; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA Filtering Setup API test ")); + testDisplayStatus(status); + + /* + * ARP to CPU Setup + */ + testAPI.getFunc.port_bool = gprtGetARPtoCPU; + testAPI.setFunc.port_bool = gprtSetARPtoCPU; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ARP to CPU Setup API test ")); + testDisplayStatus(status); + + /* + * Egress Flood + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetEgressFlood; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetEgressFlood; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Egress Flood Setup API test ")); + testDisplayStatus(status); + + /* + * Port Scheduling + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetPortSched; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetPortSched; + if((status = testPortU32Type(dev,&testAPI,2)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Port Scheduling Setup API test ")); + testDisplayStatus(status); + + /* + * Provider Tag + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetProviderTag; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetProviderTag; + if((status = testPortU32Type(dev,&testAPI,0xFF)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Provider Tag Setup API test ")); + testDisplayStatus(status); + + return testResults; +} + +GT_U32 testPortG(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + int portIndex; + + testResult = GT_OK; + + /* + * Drop on Lock + */ + testAPI.getFunc.port_bool = gprtGetDropOnLock; + testAPI.setFunc.port_bool = gprtSetDropOnLock; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Drop on Lock API test ")); + testDisplayStatus(status); + + /* + * Double Tag + */ + testAPI.getFunc.port_bool = gprtGetDoubleTag; + testAPI.setFunc.port_bool = gprtSetDoubleTag; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Double Tag API test ")); + testDisplayStatus(status); + + /* + * Interswitch Port + */ + testAPI.getFunc.port_bool = gprtGetInterswitchPort; + testAPI.setFunc.port_bool = gprtSetInterswitchPort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Interswith port setup API test ")); + testDisplayStatus(status); + + /* + * Learning Disable + */ + testAPI.getFunc.port_bool = gprtGetLearnDisable; + testAPI.setFunc.port_bool = gprtSetLearnDisable; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Learning Disable API test ")); + testDisplayStatus(status); + + /* + * FCS Ignore + */ + testAPI.getFunc.port_bool = gprtGetIgnoreFCS; + testAPI.setFunc.port_bool = gprtSetIgnoreFCS; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FCS Ignore API test ")); + testDisplayStatus(status); + + /* + * VTU Priority Override + */ + testAPI.getFunc.port_bool = gprtGetVTUPriOverride; + testAPI.setFunc.port_bool = gprtSetVTUPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("VTU Priority Override API test ")); + testDisplayStatus(status); + + /* + * SA Priority Override + */ + testAPI.getFunc.port_bool = gprtGetSAPriOverride; + testAPI.setFunc.port_bool = gprtSetSAPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA Priority Override API test ")); + testDisplayStatus(status); + + /* + * DA Priority Override + */ + testAPI.getFunc.port_bool = gprtGetDAPriOverride; + testAPI.setFunc.port_bool = gprtSetDAPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DA Priority Override API test ")); + testDisplayStatus(status); + + /* + * CPU Port Setup + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetCPUPort; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetCPUPort; + if((status = testPortU32Type(dev,&testAPI,dev->numOfPorts)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("CPU Port Setup API test ")); + testDisplayStatus(status); + + /* + * Locked Port Setup + */ + testAPI.getFunc.port_bool = gprtGetLockedPort; + testAPI.setFunc.port_bool = gprtSetLockedPort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Locked Port Setup API test ")); + testDisplayStatus(status); + + /* + * Ignore Wrong Data Setup + */ + testAPI.getFunc.port_bool = gprtGetIgnoreWrongData; + testAPI.setFunc.port_bool = gprtSetIgnoreWrongData; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Ignore Wrong Data Setup API test ")); + testDisplayStatus(status); + + /* + * UseCoreTag Setup + */ + testAPI.getFunc.port_bool = gprtGetUseCoreTag; + testAPI.setFunc.port_bool = gprtSetUseCoreTag; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("UseCoreTag Setup API test ")); + testDisplayStatus(status); + + /* + * DiscardTagged Setup + */ + testAPI.getFunc.port_bool = gprtGetDiscardTagged; + testAPI.setFunc.port_bool = gprtSetDiscardTagged; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DiscardTagged Setup API test ")); + testDisplayStatus(status); + + /* + * DiscardUntagged Setup + */ + testAPI.getFunc.port_bool = gprtGetDiscardUntagged; + testAPI.setFunc.port_bool = gprtSetDiscardUntagged; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DiscardUntagged Setup API test ")); + testDisplayStatus(status); + + /* + * MapDA Setup + */ + testAPI.getFunc.port_bool = gprtGetMapDA; + testAPI.setFunc.port_bool = gprtSetMapDA; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MapDA Setup API test ")); + testDisplayStatus(status); + + /* + * DefaultForward Setup + */ + testAPI.getFunc.port_bool = gprtGetDefaultForward; + testAPI.setFunc.port_bool = gprtSetDefaultForward; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DefaultForward Setup API test ")); + testDisplayStatus(status); + + /* + * EgressMonitorSource Setup + */ + testAPI.getFunc.port_bool = gprtGetEgressMonitorSource; + testAPI.setFunc.port_bool = gprtSetEgressMonitorSource; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("EgressMonitorSource Setup API test ")); + testDisplayStatus(status); + + /* + * IngressMonitorSource Setup + */ + testAPI.getFunc.port_bool = gprtGetIngressMonitorSource; + testAPI.setFunc.port_bool = gprtSetIngressMonitorSource; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IngressMonitorSource Setup API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + return testResults; + default: + break; + } + + /* + * MessagePort Setup + */ + testAPI.getFunc.port_bool = gprtGetMessagePort; + testAPI.setFunc.port_bool = gprtSetMessagePort; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("MessagePort Setup API test ")); + testDisplayStatus(status); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + if((status = testTrunkPortSetup(dev,portIndex)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + portIndex = 0xFF; + break; + } + } + MSG_PRINT(("TrunkPort Setup API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6092: + case GT_88E6095: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + if (dev->revision < 1) + return testResults; + break; + case GT_88E6131: + case GT_88E6108: + break; + default: + return testResults; + } + + /* + * Discard Broadcast Mode Setup + */ + testAPI.getFunc.port_bool = gprtGetDiscardBCastMode; + testAPI.setFunc.port_bool = gprtSetDiscardBCastMode; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Discard BCast Setup API test ")); + testDisplayStatus(status); + + /* + * FC On RateLimit Mode Setup + */ + testAPI.getFunc.port_bool = gprtGetFCOnRateLimitMode; + testAPI.setFunc.port_bool = gprtSetFCOnRateLimitMode; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("FC On RateLimit Setup API test ")); + testDisplayStatus(status); + + return testResults; +} + +GT_U32 testPort(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + testResult = GT_OK; + + /* + * Force FlowControl + */ + testAPI.getFunc.port_bool = gprtGetForceFc; + testAPI.setFunc.port_bool = gprtSetForceFc; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Force FlowControl API test ")); + testDisplayStatus(status); + + /* + * Trailer Mode + */ + testAPI.getFunc.port_bool = gprtGetTrailerMode; + testAPI.setFunc.port_bool = gprtSetTrailerMode; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Trailer Mode API test ")); + testDisplayStatus(status); + + /* + * Ingress Mode + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetIngressMode; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetIngressMode; + if((status = testPortU32Type(dev,&testAPI,3)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Ingress Mode API test ")); + testDisplayStatus(status); + + + /* + * Muticast Rate Limit + * This feature is only avalable on 6021/6051/6052 + * It is replace with Rate Control Register in Clippership and beyond + */ + if( (dev->deviceId == GT_88E6021) || + (dev->deviceId == GT_88E6051) || + (dev->deviceId == GT_88E6052) + ){ + + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetMcRateLimit; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetMcRateLimit; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Multicast Rate Limit API test ")); + testDisplayStatus(status); + }; + + /* + * IGMP Snoop + */ + testAPI.getFunc.port_bool = gprtGetIGMPSnoop; + testAPI.setFunc.port_bool = gprtSetIGMPSnoop; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IGMP Snoop API test ")); + testDisplayStatus(status); + + /* + * Header Mode + */ + testAPI.getFunc.port_bool = gprtGetHeaderMode; + testAPI.setFunc.port_bool = gprtSetHeaderMode; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Header Mode API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + testResults |= testPortG(dev); + break; + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + testResults |= testPortEnhancedFE(dev); + break; + default: + break; + } + return testResults; +} + +GT_U32 testPortRCforEnhancedFE(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + testResult = GT_OK; + + /* + * VID NRL En + */ + testAPI.getFunc.port_bool = grcGetVidNrlEn; + testAPI.setFunc.port_bool = grcSetVidNrlEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("VID NRL En API test ")); + testDisplayStatus(status); + + /* + * SA NRL En + */ + testAPI.getFunc.port_bool = grcGetSaNrlEn; + testAPI.setFunc.port_bool = grcSetSaNrlEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA NRL En API test ")); + testDisplayStatus(status); + + /* + * DA NRL En + */ + testAPI.getFunc.port_bool = grcGetDaNrlEn; + testAPI.setFunc.port_bool = grcSetDaNrlEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DA NRL En API test ")); + testDisplayStatus(status); + + + /* + * Egress Limit Mode + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)grcGetELimitMode; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)grcSetELimitMode; + if((status = testPortU32Type(dev,&testAPI,3)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Egress Limit Mode API test ")); + testDisplayStatus(status); + + /* + * Rsvd NRL En + */ + testAPI.getFunc.bool = grcGetRsvdNrlEn; + testAPI.setFunc.bool = grcSetRsvdNrlEn; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Rsvd NRL En API test ")); + testDisplayStatus(status); + + return testResults; +} + +GT_U32 testPortRateCtrl(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, tmpResult; + GT_U32 testResults = 0; + TEST_API testAPI; + GT_LPORT port; + int portIndex; + GT_BURST_RATE bLimit, rbLimit, obLimit; + GT_BURST_SIZE bSize, rbSize, obSize; + GT_U32 RateCtrl[5]; + + testResult = GT_OK; + + /* + * Ingress Rate Limit Mode + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)grcGetLimitMode; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)grcSetLimitMode; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Ingress Rate Limit Mode API test ")); + testDisplayStatus(status); + + + /* + * Priority 3 Frames Rate Limit + */ + testAPI.getFunc.port_bool = grcGetPri3Rate; + testAPI.setFunc.port_bool = grcSetPri3Rate; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Priority 3 Frames Rate Limit API test ")); + testDisplayStatus(status); + + /* + * Priority 2 Frames Rate Limit + */ + testAPI.getFunc.port_bool = grcGetPri2Rate; + testAPI.setFunc.port_bool = grcSetPri2Rate; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Priority 2 Frames Rate Limit API test ")); + testDisplayStatus(status); + + /* + * Priority 1 Frames Rate Limit + */ + testAPI.getFunc.port_bool = grcGetPri1Rate; + testAPI.setFunc.port_bool = grcSetPri1Rate; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Priority 1 Frames Rate Limit API test ")); + testDisplayStatus(status); + + /* + * Priority 0 Frames Rate Limit + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)grcGetPri0Rate; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)grcSetPri0Rate; + if((status = testPortU32Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Priority 0 Frames Rate Limit API test ")); + testDisplayStatus(status); + + /* + * Included Bytes in Rate Control API + */ + tmpResult = GT_OK; + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + GT_BOOL limitMGMT, countIFG, countPre; + GT_BOOL orgLimitMGMT, orgCountIFG, orgCountPre; + GT_BOOL tmpLimitMGMT, tmpCountIFG, tmpCountPre; + + port = portIndex; + + if((status = grcGetBytesCount(dev,port,&orgLimitMGMT,&orgCountIFG,&orgCountPre)) != GT_OK) + { + MSG_PRINT(("grcSetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + tmpResult = status; + break; + } + + limitMGMT = GT_TRUE; + countIFG = GT_FALSE; + countPre = GT_TRUE; + + if((status = grcSetBytesCount(dev,port,limitMGMT,countIFG,countPre)) != GT_OK) + { + MSG_PRINT(("grcSetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = grcGetBytesCount(dev,port,&tmpLimitMGMT,&tmpCountIFG,&tmpCountPre)) + != GT_OK) + { + MSG_PRINT(("grcGetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if ((limitMGMT != tmpLimitMGMT) || + (countIFG != tmpCountIFG) || + (countPre != tmpCountPre)) + { + MSG_PRINT(("grcGetBytesCount returned unexpected value(s)\n")); + MSG_PRINT(("Expecting: limitMgmg %i, countIFG %i, countPre %i\n", + limitMGMT,countIFG,countPre)); + MSG_PRINT(("Returned : limitMgmg %i, countIFG %i, countPre %i\n", + tmpLimitMGMT,tmpCountIFG,tmpCountPre)); + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + } + + limitMGMT = GT_FALSE; + countIFG = GT_TRUE; + countPre = GT_FALSE; + + if((status = grcSetBytesCount(dev,port,limitMGMT,countIFG,countPre)) != GT_OK) + { + MSG_PRINT(("grcSetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = grcGetBytesCount(dev,port,&tmpLimitMGMT,&tmpCountIFG,&tmpCountPre)) + != GT_OK) + { + MSG_PRINT(("grcGetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if ((limitMGMT != tmpLimitMGMT) || + (countIFG != tmpCountIFG) || + (countPre != tmpCountPre)) + { + MSG_PRINT(("grcGetBytesCount returned unexpected value(s)\n")); + MSG_PRINT(("Expecting: limitMgmg %i, countIFG %i, countPre %i\n", + limitMGMT,countIFG,countPre)); + MSG_PRINT(("Returned : limitMgmg %i, countIFG %i, countPre %i\n", + tmpLimitMGMT,tmpCountIFG,tmpCountPre)); + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + } + + if((status = grcSetBytesCount(dev,port,orgLimitMGMT,orgCountIFG,orgCountPre)) + != GT_OK) + { + MSG_PRINT(("grcSetBytesCount returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + } + if(tmpResult != GT_OK) + { + MSG_PRINT(("Count Bytes API test Failed.\n")); + testResult = tmpResult; + testResults |= 1 << testResult; + } + else + { + MSG_PRINT(("Count Bytes API test Passed.\n")); + } + + /* + * Egress Rate Limit + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)grcGetEgressRate; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)grcSetEgressRate; + if((status = testPortU32Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Egress Rate Limit API test ")); + testDisplayStatus(status); + + switch(dev->deviceId) + { + case GT_88E6092: + case GT_88E6095: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + if (dev->revision < 1) + return testResults; + break; + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + testResults |= testPortRCforEnhancedFE(dev); + break; + case GT_88E6131: + case GT_88E6108: + break; + default: + return testResults; + } + + /* + * Burst Size based Rate Limit API + */ + RateCtrl[0] = 0x7FFFF; /* No_Limit, 64k ~ 256M */ + RateCtrl[1] = 0x7FFFD; /* No_Limit, 128k ~ 256M */ + RateCtrl[2] = 0x7FFF9; /* No_Limit, 256k ~ 256M */ + RateCtrl[3] = 0x7FFE1; /* No_Limit, 512k ~ 256M */ + RateCtrl[4] = 0; + if(grcGetBurstRate(dev,0,&rbSize,&rbLimit) == GT_NOT_SUPPORTED) + testResult = GT_NOT_SUPPORTED; + else + { + testResult = GT_OK; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + if((status=grcGetBurstRate(dev,portIndex,&obSize,&obLimit)) != GT_OK) + { + MSG_PRINT(("Get Burst Rate returned wrong (bsize %i, rate %i)\n",obSize,obLimit)); + testResult = GT_FAIL; + testResults |= 1 << status; + break; + } + + for(bSize=GT_BURST_SIZE_12K; bSize<=GT_BURST_SIZE_96K+1; bSize++) + { + for(bLimit=GT_BURST_NO_LIMIT; bLimit<=GT_BURST_256M+1; bLimit++) + { + if((status=grcSetBurstRate(dev,portIndex,bSize,bLimit)) != GT_OK) + { + if(RateCtrl[bSize] & (1<numOfPorts; portIndex++) + { + if((status=grcGetTCPBurstRate(dev,portIndex,&obLimit)) != GT_OK) + { + MSG_PRINT(("Get TCP Burst Rate returned wrong (rate %i)\n",obLimit)); + testResult = GT_FAIL; + testResults |= 1 << status; + break; + } + + for(bLimit=GT_BURST_NO_LIMIT; bLimit<=GT_BURST_256M; bLimit++) + { + if(grcSetTCPBurstRate(dev,portIndex,bLimit) != GT_OK) + { + if(RateCtrl[0] & (1<numOfPorts)-1)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Port Association Vector API test ")); + testDisplayStatus(status); + + /* + * Ingress Monitor + */ + testAPI.getFunc.port_bool = gpavGetIngressMonitor; + testAPI.setFunc.port_bool = gpavSetIngressMonitor; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Ingress Monitor API test ")); + testDisplayStatus(status); + + return testResults; +} + + +GT_U32 testATUSetup(GT_QD_DEV *dev ) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + /* + * Learn2All Setup API + */ + testAPI.getFunc.bool = gfdbGetLearn2All; + testAPI.setFunc.bool = gfdbSetLearn2All; + if((status = testBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Learn2All Setup API test ")); + testDisplayStatus(status); + + return testResults; +} + + +GT_STATUS testDisplayATUList(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY tmpMacEntry; + GT_U32 dbNum,i; + int entries; + + MSG_PRINT(("ATU List:\n")); + + switch(dev->deviceId) + { + case GT_88E6051: + case GT_88E6052: + case GT_FF_HG: + case GT_FF_EG: + dbNum = 1; + break; + case GT_88E6021: + case GT_88E6061: + case GT_88E6063: + case GT_FH_VPN: + case GT_88E6083: + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + dbNum = 16; + break; + case GT_88E6065: + dbNum = 64; + break; + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + dbNum = 256; + break; + default: + dbNum = 1; + break; + } + + for(i=0; i TEST_MAC_ENTRIES) + entrySize = TEST_MAC_ENTRIES; + + if (entrySize*maxDbNum > (256 << atuSize)) + { + entrySize = (256 << atuSize) / maxDbNum; + } + + macEntry = NULL; + for(dbNum=0; dbNum < maxDbNum; dbNum++) + macList[dbNum] = NULL; + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + sapphire = GT_TRUE; + aging15 = GT_TRUE; + moveAllowed = GT_TRUE; + break; + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + moveAllowed = GT_TRUE; + sapphire = GT_FALSE; + aging15 = GT_TRUE; + break; + default: + moveAllowed = GT_FALSE; + sapphire = GT_FALSE; + aging15 = GT_FALSE; + break; + } + /* Set ATU Size will cause ATU reset and SW reset, so call before any other setup. */ + MSG_PRINT(("Setting ATU Size : %i\n",256< entrySize*maxDbNum) + { + MSG_PRINT(("Cannot create ATU List for testing... \n")); + goto errorExit; + } + + for(i=0; i0) + timer--; + +#ifdef TEST_DEBUG + testDisplayATUList(dev); +#endif + /* + Now we have entrySize*16 entries in the table. + */ + + /* Get Atu Dynamic Count, which should be dynamicMacs. */ + if((status = gfdbGetAtuDynamicCount(dev,&u32Data1)) != GT_OK) + { + MSG_PRINT(("gfdbGetAtuDynamicCount returned ")); + testDisplayStatus(status); + goto errorExit; + } + + MSG_PRINT(("Dynamic Macs in the table : %d\n", dynamicMacs)); + if (u32Data1 != dynamicMacs) + { + MSG_PRINT(("Atu Dynamic Count returned %d.(should be %d)\n", u32Data1,dynamicMacs)); + testResult = GT_FAIL; + } + + /* Get First Entry in the Table, which should be macEntry[0]. */ + + for (dbNum=0; dbNumnumOfPorts; port++) + { + if(port == portDest) + continue; + + if((status = gfdbMoveInDB(dev,GT_MOVE_ALL,(GT_U8)dbNum,port,portDest)) != GT_OK) + { + MSG_PRINT(("gfdbMove returned ")); + testDisplayStatus(status); + if (status == GT_NOT_SUPPORTED) + break; + goto errorExit; + } + } + + /* verify Move, First Entry has been deleted from previous test */ + for(i=1; inumOfPorts; port++) + { + if(port == portDest) + continue; + + if((status = gfdbMove(dev,GT_MOVE_ALL,port,portDest)) != GT_OK) + { + MSG_PRINT(("gfdbMove returned ")); + testDisplayStatus(status); + if (status == GT_NOT_SUPPORTED) + break; + goto errorExit; + } + } + + /* verify Move. First Entry has been deleted from previous test */ + for(i=1; i= 5) + return GT_BAD_PARAM; + + maxMacs = 256 << atuSize; + bSize = 64 << atuSize; + binSize = 4; + + gtMemSet(buckets,0,MAX_BUCKET_SIZE); + + i = entry = 0; + + while(1) + { + if (i == 0xFFFFFFFF) + { + MSG_PRINT(("32bit is not enough.\n")); + return GT_FAIL; + } + + i++; + + if ((i & 0xFFFFFF) == 0) + { + MSG_PRINT(("loop %#x : entry %#x\n", i,entry)); + dumpMemory(buckets,bSize); + } + + *(GT_U16*)eaddr = first2Bytes; + eaddr[2] = (i >> 24) & 0xff; + eaddr[3] = (i >> 16) & 0xff; + eaddr[4] = (i >> 8) & 0xff; + eaddr[5] = i & 0xff; + bucket = runQDHash(eaddr, dbNum, bSize, &hash, &preBucket, &tmpBucket); + if(buckets[bucket] == binSize) + continue; + addr = bucket*binSize + buckets[bucket]; + buckets[bucket]++; + memcpy(atuEntry[addr].atuEntry.macAddr.arEther,eaddr,6); + atuEntry[addr].atuEntry.entryState.ucEntryState = state; + atuEntry[addr].atuEntry.portVec = 1; + atuEntry[addr].atuEntry.prio = 0; + atuEntry[addr].atuEntry.DBNum = (GT_U8)dbNum; + atuEntry[addr].hash = hash; + atuEntry[addr].bucket = bucket; +#if 0 + MSG_PRINT(("EADDR : %02x-%02x-%02x-%02x, ", eaddr[2],eaddr[3],eaddr[4],eaddr[5])); + MSG_PRINT(("Hash : %03x, ", hash)); + MSG_PRINT(("bucket : %03x, ", preBucket)); + MSG_PRINT(("bucket(db) : %03x, ", bucket)); + MSG_PRINT(("bins : %02x\n", buckets[bucket]-1)); +#endif + entry++; + if (entry >= maxMacs) + { + MSG_PRINT(("loop %#x\n", i)); + break; + } + + } + + return GT_OK; +} + +/* + 1. Set ATU Size. + 2. Disable AGING. + 3. Disable Learning. + 4. Flush all the ATU entries. + 5. Check Dynamic Counts. + 6. Create Filled ATU Table in system memory with EntryState = 0x7. + 7. Write the table into the device. + 8. Compare ATU Entries. + 9. Create Filled ATU Table in system memory with EntryState = 0x7. + 10.Write the table into the device. + 11.Compare ATU Entries. (Only First Entry in each bucket got replaced.) + 12.Create Filled ATU Table in system memory with EntryState = 0xF. + 13.Write the table into the device. + 14.Compare ATU Entries. + 15.Write the table which was created in step 9. + 16.Make it sure that no entry is written. +*/ +GT_STATUS testFilledATU(GT_QD_DEV *dev,GT_U8 atuSize, GT_U32 dbNum) +{ + GT_STATUS testResult, status; + ATU_ENTRY_INFO *atuEntry; + ATU_ENTRY_INFO *tmpAtuEntry; + ATU_ENTRY_INFO *tmpSingleAtuEntry; + GT_ATU_ENTRY tmpMacEntry; + GT_U16 maxMacs, i; + GT_BOOL found; + GT_U32 u32Data; + + if(atuSize > 5) + return GT_FAIL; + + testResult = GT_OK; + maxMacs = 256 << atuSize; + + if (gAtuEntry == NULL) + gAtuEntry = (ATU_ENTRY_INFO *)malloc(sizeof(ATU_ENTRY_INFO)*4096); + + atuEntry = gAtuEntry; + + gtMemSet(atuEntry,0,sizeof(ATU_ENTRY_INFO)*maxMacs); + + MSG_PRINT(("Setting ATU Size : %i\n",256<atuEntry.macAddr.arEther[0]; + tmpMacEntry.macAddr.arEther[1] = tmpSingleAtuEntry->atuEntry.macAddr.arEther[1]; + tmpMacEntry.macAddr.arEther[2] = tmpSingleAtuEntry->atuEntry.macAddr.arEther[2]; + tmpMacEntry.macAddr.arEther[3] = tmpSingleAtuEntry->atuEntry.macAddr.arEther[3]; + tmpMacEntry.macAddr.arEther[4] = tmpSingleAtuEntry->atuEntry.macAddr.arEther[4]; + tmpMacEntry.macAddr.arEther[5] = tmpSingleAtuEntry->atuEntry.macAddr.arEther[5]; + tmpMacEntry.DBNum = tmpSingleAtuEntry->atuEntry.DBNum; + + if((status = gfdbFindAtuMacEntry(dev,&tmpMacEntry,&found)) != GT_OK) + { + MSG_PRINT(("gfdbFindAtuMacEntry returned ")); + testDisplayStatus(status); + MSG_PRINT(("Entry to find : (%#x-%#x-%#x-%#x-%#x-%#x)\n", + tmpMacEntry.macAddr.arEther[0], + tmpMacEntry.macAddr.arEther[1], + tmpMacEntry.macAddr.arEther[2], + tmpMacEntry.macAddr.arEther[3], + tmpMacEntry.macAddr.arEther[4], + tmpMacEntry.macAddr.arEther[5])); + free(tmpAtuEntry); + return status; + } + + if (found == GT_FALSE) + { + MSG_PRINT(("Cannot find the Entry : (%#x-%#x-%#x-%#x-%#x-%#x)\n", + tmpMacEntry.macAddr.arEther[0], + tmpMacEntry.macAddr.arEther[1], + tmpMacEntry.macAddr.arEther[2], + tmpMacEntry.macAddr.arEther[3], + tmpMacEntry.macAddr.arEther[4], + tmpMacEntry.macAddr.arEther[5])); + + free(tmpAtuEntry); + testResult = GT_FAIL; + return testResult; + } + + if(memcmp(&tmpMacEntry, &(tmpSingleAtuEntry->atuEntry), sizeof(GT_ATU_ENTRY))) + { + MSG_PRINT(("gfdbFindAtuMacEntry returned wrong entry.\n")); + dumpMemory((char*)&tmpMacEntry,sizeof(GT_ATU_ENTRY)); + MSG_PRINT(("Expecting:\n")); + dumpMemory((char*)&(tmpSingleAtuEntry->atuEntry),sizeof(GT_ATU_ENTRY)); + + testResult = GT_FAIL; + } + else + { + if(((i & 0x3F) == 0) && (i != 0)) + MSG_PRINT(("Compared %i ATU Entries.\n",i)); + } + } + + /* + * Entry State 0xF + */ + + MSG_PRINT(("Getting ATU List(%i).\n",maxMacs)); + gtMemSet(atuEntry,0,sizeof(ATU_ENTRY_INFO)*maxMacs); + if((status=testFillUpAtu(dev,atuEntry,atuSize,dbNum,0xAA00,GT_UC_STATIC)) != GT_OK) + { + MSG_PRINT(("testFillUpAtu returned ")); + testDisplayStatus(status); + free(tmpAtuEntry); + return status; + } + + MSG_PRINT(("Writing ATU List(%i).\n",maxMacs)); + for(i=0; ideviceId) + { + case GT_88E6051: + case GT_FF_EG: + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_4096; + break; + + case GT_88E6021: + case GT_88E6060: + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + /* dbNum test is not performed at this time */ + dbNumSupport = GT_TRUE; + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_256; + atuEnd = ATU_SIZE_2048; + break; + + case GT_88E6052: + case GT_FF_HG: + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_2048; + break; + + case GT_88E6063: + case GT_FH_VPN: + case GT_88E6083: + /* dbNum test is not performed at this time */ + dbNumSupport = GT_TRUE; + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_2048; + break; + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + /* dbNum test is not performed at this time */ + dbNumSupport = GT_TRUE; + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_4096; + atuEnd = ATU_SIZE_4096; + break; + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + /* dbNum test is not performed at this time */ + dbNumSupport = GT_TRUE; + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_4096; + atuEnd = ATU_SIZE_8192; + break; + default: + MSG_PRINT(("Cannot run ATU test.(Unknown device)\n")); + return GT_FAIL; + } + + switch (dev->deviceId) + { + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + if(testATUSetup(dev) != GT_OK) + return GT_FAIL; + default: + break; + } + + for(arg=0; arg<1; arg++) + { + for(atuSize=atuStart; atuSize<=atuEnd; atuSize++) + { + if(dbNumSupport == GT_TRUE) + { + dbNum = (64< 16) + dbNum = 16; + } + else + dbNum = 1; + + for(sameMacs=0;sameMacs<=dbNum;sameMacs+=4) + { + MSG_PRINT(("Running ATU Test : arg %i, macEntries %i, dbNum %i, atuSize %i\n", + arg, TEST_MAC_ENTRIES, dbNum, 256 << atuSize)); + if((status=testAtuDbNum(dev,arg,TEST_MAC_ENTRIES,dbNum,sameMacs,atuSize)) != GT_OK) + { + MSG_PRINT(("ATU Test Fail(%d), arg %i,dbNum %i,sameMacs %i,atuSize %i\n", + status,arg,dbNum,sameMacs,256<deviceId) + { + case GT_88E6051: + case GT_FF_EG: + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_4096; + break; + + case GT_88E6021: + case GT_88E6060: + case GT_88E6031: + case GT_88E6035: + case GT_88E6055: + case GT_88E6061: + case GT_88E6065: + dbNumSupport = GT_TRUE; + atuStart = ATU_SIZE_256; + atuEnd = ATU_SIZE_2048; + break; + + case GT_88E6052: + case GT_FF_HG: + dbNumSupport = GT_FALSE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_2048; + break; + + case GT_88E6063: + case GT_FH_VPN: + case GT_88E6083: + dbNumSupport = GT_TRUE; + atuStart = ATU_SIZE_512; + atuEnd = ATU_SIZE_2048; + break; + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + dbNumSupport = GT_TRUE; + atuStart = ATU_SIZE_4096; + atuEnd = ATU_SIZE_4096; + break; + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + dbNumSupport = GT_TRUE; + maxDbNum = 256; + atuStart = ATU_SIZE_4096; + atuEnd = ATU_SIZE_4096; + break; + case GT_88E6131: + case GT_88E6108: + dbNumSupport = GT_TRUE; + maxDbNum = 256; + atuStart = ATU_SIZE_1024; + atuEnd = ATU_SIZE_1024; + break; + default: + MSG_PRINT(("Cannot run ATU test.(Unknown device)\n")); + return GT_FAIL; + } + + for(arg=0; arg<3; arg++) + { + for(atuSize=atuStart; atuSize<=atuEnd; atuSize++) + { + if(dbNumSupport == GT_TRUE) + { + if(atuStart == atuEnd) + { + dbNum = maxDbNum; + } + else + { + dbNum = (64< maxDbNum) + dbNum = maxDbNum; + } + } + else + dbNum = 1; + + for(sameMacs=0;sameMacs<=4;sameMacs+=2) + { + MSG_PRINT(("Running ATU Test: arg %i,macEntries %i,dbNum %i,atuSize %i,sameMac %i\n", + arg, TEST_MAC_ENTRIES, dbNum, 256 << atuSize, sameMacs)); + if((status=testAtuDbNum(dev,arg,TEST_MAC_ENTRIES,dbNum,sameMacs,atuSize)) != GT_OK) + { + MSG_PRINT(("ATU Test Fail(%d), arg %i,dbNum %i,sameMacs %i,atuSize %i\n", + status,arg,dbNum,sameMacs,256<< atuSize)); + testResult = GT_FAIL; + break; + } + else + { + MSG_PRINT(("ATU Test Pass with arg %i\n", arg)); + } + MSG_PRINT((" \n")); + } + if (testResult != GT_OK) + break; + + } + if (testResult != GT_OK) + break; + } + + MSG_PRINT(("Exercising Full ATU Table...\n")); + for(atuSize=atuStart; atuSize<=atuEnd; atuSize++) + { + if((status = testFilledATU(dev,atuSize,0)) != GT_OK) + testResult = GT_FAIL; + if((status = testFilledATU(dev,atuSize,maxDbNum-1)) != GT_OK) + testResult = GT_FAIL; + } + + /* Sw Reset */ + if((status=gsysSwReset(dev)) != GT_OK) + { + MSG_PRINT(("gsysSwReset returned Fail (%#x).\n", status)); + return status; + } + + return testResult; +} + + +/******************************************************************************* +* testVlan +* +* DESCRIPTION: +* Testing Vlan related APIs. (Set/Get) +* (EgressMode, VlanTunnel, PortVlanPorts, PortUserPriLsb, and PortVid access) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on fail +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U32 testVlan(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, mapTest; + GT_U32 testResults = 0; + TEST_API testAPI; + GT_LPORT port; + GT_LPORT portList[MAX_SWITCH_PORTS]; + GT_LPORT tmpPortList[MAX_SWITCH_PORTS]; + GT_LPORT orgPortList[MAX_SWITCH_PORTS]; + GT_U8 i, portCount, orgCount, tmpCount; + int portIndex; + + testResult = GT_OK; + + /* + * Egress Mode + */ + testAPI.getFunc.port_u32 = (GT_API_GET_PORT_U32)gprtGetEgressMode; + testAPI.setFunc.port_u32 = (GT_API_SET_PORT_U32)gprtSetEgressMode; + if((status = testPortU32Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Egress Mode API test ")); + testDisplayStatus(status); + + /* + * Vlan Tunnel + */ + testAPI.getFunc.port_bool = gprtGetVlanTunnel; + testAPI.setFunc.port_bool = gprtSetVlanTunnel; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Vlan Tunnel API test ")); + testDisplayStatus(status); + + /* + * user priority (VPT) LSB bit + */ + testAPI.getFunc.port_bool = gvlnGetPortUserPriLsb; + testAPI.setFunc.port_bool = gvlnSetPortUserPriLsb; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("user priority (VPT) LSB bit API test ")); + testDisplayStatus(status); + + /* + * Port VID + */ + testAPI.getFunc.port_u16 = gvlnGetPortVid; + testAPI.setFunc.port_u16 = gvlnSetPortVid; + if((status = testPortU16Type(dev,&testAPI,7)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Port VID API test ")); + testDisplayStatus(status); + + /* Port Vlan Mapping */ + mapTest = GT_OK; + + portCount = (4 < (dev->numOfPorts-1))?4:(dev->numOfPorts-1); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + if((status = gvlnGetPortVlanPorts(dev,port,orgPortList,&orgCount)) != GT_OK) + { + MSG_PRINT(("gvlnGetPortVlanPorts returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gvlnSetPortVlanPorts(dev,port,portList,portCount)) != GT_OK) + { + MSG_PRINT(("gvlnSetPortVlanPorts returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gvlnGetPortVlanPorts(dev,port,tmpPortList,&tmpCount)) != GT_OK) + { + MSG_PRINT(("gvlnGetPortVlanPorts returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (portCount != tmpCount) + { + MSG_PRINT(("gvlnGetPortVlanPorts returned wrong portCount(%i:%i).\n",portCount,tmpCount)); + mapTest = GT_FAIL; + testResults |= 1 << mapTest; + } + + for(i=0; inumOfPorts) + { + case 3: + nPhys = 2; + break; + default: + nPhys = 5; + break; + } + + for(portIndex=0; portIndexcpuPortNum) + continue; + + /* Test Reset API */ + MSG_PRINT(("Reset Phy (port %i).\n",port)); + if((status = gprtPhyReset(dev,port)) != GT_OK) + { + MSG_PRINT(("gprtPhyReset returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u16Data & 0x1000)) + { + MSG_PRINT(("gprtPhyReset failed.\n")); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Reset, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + + + /* + * Set AutoNego disable, LoopBack enable, 100Mbps, Duplex On, + */ + if((status = gprtPortAutoNegEnable(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtPortAutoNegEnable returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortLoopback(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortLoopback returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortSpeed(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortSpeed returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortDuplexMode(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortDuplexMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(0x6100 != (u16Data & 0x6100)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x6100).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + { + if(u16Data & 0x1000) + { + MSG_PRINT(("Set Failed (%#x, should be 0x6100).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Loopback and 100Full, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + } + + /* + * Set 10Mbps, Half Duplex. + */ + if((status = gprtSetPortLoopback(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortLoopback returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortSpeed(dev,port,PHY_SPEED_10_MBPS)) != GT_OK) + { + MSG_PRINT(("gprtSetPortSpeed returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortDuplexMode(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortDuplexMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(u16Data != 0x0000) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0000).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After 10Half, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + + /* + * Set Power Down + */ + if((status = gprtPortPowerDown(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtPortPowerDown returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* Power Down bit should be set. */ + if(!(u16Data & 0x0800)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0800).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After PowerDown, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + + /* + * Set Power Up + */ + if((status = gprtPortPowerDown(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtPortPowerDown returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After power up, Power Down bit should be cleared.*/ + if(u16Data &= 0x0800) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0000).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Power back up, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + + /* + * Set Autonego and Restart AutoNego. + */ + if((status = gprtPortAutoNegEnable(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtPortAutoNegEnable returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtPortRestartAutoNeg(dev,port)) != GT_OK) + { + MSG_PRINT(("gprtPortRestartAutoNeg returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u16Data & 0x1000)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x1000).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Auto, Phy (port %i) Reg 0 : %#x.\n",port,u16Data)); + + + /* + * Enable PAUSE + */ + if((status = gprtSetPause(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,4,&u16Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u16Data & 0x400)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x400).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Pause set, Phy (port %i) Reg 4 : %#x.\n",port,u16Data)); + + /* + * Disable PAUSE + */ + if((status = gprtSetPause(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gprtGetPhyReg(dev,port,4,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(u16Data & 0x400) + { + MSG_PRINT(("Set Failed (%#x, should be 0x00).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Pause reset, Phy (port %i) Reg 4 : %#x.\n",port,u16Data)); + + /* + * Disable PAUSE + */ + for(mode=SPEED_AUTO_DUPLEX_AUTO;mode<=SPEED_AUTO_DUPLEX_HALF;mode++) + { + switch(mode) + { + case SPEED_1000_DUPLEX_AUTO: + case SPEED_1000_DUPLEX_FULL: + case SPEED_1000_DUPLEX_HALF: + continue; + default: + break; + } + + if((status = gprtSetPortAutoMode(dev,port,mode)) != GT_OK) + { + MSG_PRINT(("gprtSetPortAutoMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + /* Autonego should be enabled. */ + if(gprtGetPhyReg(dev,port,0,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u16Data & 0x1000)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x1000).\n", u16Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + { + if(gprtGetPhyReg(dev,port,4,&u16Data) != GT_OK) + { + MSG_PRINT(("gprtGetPhyReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + switch(mode) + { + case SPEED_AUTO_DUPLEX_AUTO: + tmpData = 0x1e0; + break; + case SPEED_100_DUPLEX_AUTO: + tmpData = 0x180; + break; + case SPEED_10_DUPLEX_AUTO: + tmpData = 0x060; + break; + case SPEED_AUTO_DUPLEX_FULL: + tmpData = 0x140; + break; + case SPEED_AUTO_DUPLEX_HALF: + tmpData = 0x0a0; + break; + default: + tmpData = 0; + break; + } + + if((u16Data & 0x1e0) != tmpData) + { + MSG_PRINT(("Set AutoMode(%i) Failed (%#x, should be %#x).\n", mode,u16Data,tmpData)); + testResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + else + MSG_PRINT(("After Mode(%d) set, Phy (port %i) Reg 4 : %#x.\n",mode,port,u16Data)); + + } + } + + + } + return testResults; +} + +GT_U32 testPhy2(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + GT_LPORT port; + GT_U32 u32Data, tmpData; + GT_PHY_AUTO_MODE mode; + int portIndex, nPhys; + + testResult = GT_OK; + switch(dev->numOfPorts) + { + case 3: + nPhys = 2; + break; + default: + nPhys = 5; + break; + } + + for(portIndex=0; portIndexcpuPortNum) + continue; + + /* Test Reset API */ + MSG_PRINT(("Reset Phy (port %i).\n",port)); + if((status = gprtPhyReset(dev,port)) != GT_OK) + { + MSG_PRINT(("gprtPhyReset returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev, dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u32Data & 0x1000)) + { + MSG_PRINT(("gprtPhyReset failed.\n")); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Reset, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + + + /* + * Set AutoNego disable, LoopBack enable, 100Mbps, Duplex On, + */ + if((status = gprtPortAutoNegEnable(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtPortAutoNegEnable returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortLoopback(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortLoopback returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortSpeed(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortSpeed returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortDuplexMode(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortDuplexMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev, dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(0x6100 != (u32Data & 0x6100)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x6100).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + { + if(u32Data & 0x1000) + { + MSG_PRINT(("Set Failed (%#x, should be 0x6100).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Loopback and 100Full, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + } + + /* + * Set 10Mbps, Half Duplex. + */ + if((status = gprtSetPortLoopback(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortLoopback returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortSpeed(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortSpeed returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtSetPortDuplexMode(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPortDuplexMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(u32Data != 0x0000) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0000).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After 10Half, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + + /* + * Set Power Down + */ + if((status = gprtPortPowerDown(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtPortPowerDown returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* Power Down bit should be set. */ + if(!(u32Data & 0x0800)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0800).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After PowerDown, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + + /* + * Set Power Up + */ + if((status = gprtPortPowerDown(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtPortPowerDown returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After power up, Power Down bit should be cleared.*/ + if(u32Data &= 0x0800) + { + MSG_PRINT(("Set Failed (%#x, should be 0x0000).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Power back up, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + + /* + * Set Autonego and Restart AutoNego. + */ + if((status = gprtPortAutoNegEnable(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtPortAutoNegEnable returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gprtPortRestartAutoNeg(dev,port)) != GT_OK) + { + MSG_PRINT(("gprtPortRestartAutoNeg returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u32Data & 0x1000)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x1000).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Auto, Phy (port %i) Reg 0 : %#x.\n",port,u32Data)); + + + /* + * Enable PAUSE + */ + if((status = gprtSetPause(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,4,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u32Data & 0x400)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x400).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Pause set, Phy (port %i) Reg 4 : %#x.\n",port,u32Data)); + + /* + * Disable PAUSE + */ + if((status = gprtSetPause(dev,port,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,4,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(u32Data & 0x400) + { + MSG_PRINT(("Set Failed (%#x, should be 0x00).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("After Pause reset, Phy (port %i) Reg 4 : %#x.\n",port,u32Data)); + + /* + * Disable PAUSE + */ + for(mode=SPEED_AUTO_DUPLEX_AUTO;mode<=SPEED_AUTO_DUPLEX_HALF;mode++) + { + if((status = gprtSetPortAutoMode(dev,port,mode)) != GT_OK) + { + MSG_PRINT(("gprtSetPortAutoMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + /* Autonego should be enabled. */ + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,0,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + /* After reset AutoNego should be enabled. */ + if(!(u32Data & 0x1000)) + { + MSG_PRINT(("Set Failed (%#x, should be 0x1000).\n", u32Data)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + { + if(gsysReadMiiReg(dev,dev->baseRegAddr+port,4,&u32Data) != GT_OK) + { + MSG_PRINT(("gsysReadMiiReg returned Fail.\n")); + testResults |= 1 << GT_FAIL; + return testResults; + } + + switch(mode) + { + case SPEED_AUTO_DUPLEX_AUTO: + tmpData = 0x1e0; + break; + case SPEED_100_DUPLEX_AUTO: + tmpData = 0x180; + break; + case SPEED_10_DUPLEX_AUTO: + tmpData = 0x060; + break; + case SPEED_AUTO_DUPLEX_FULL: + tmpData = 0x140; + break; + case SPEED_AUTO_DUPLEX_HALF: + tmpData = 0x0a0; + break; + default: + tmpData = 0; + break; + } + + if((u32Data & 0x1e0) != tmpData) + { + MSG_PRINT(("Set AutoMode(%i) Failed (%#x, should be %#x).\n", mode,u32Data,tmpData)); + testResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + else + MSG_PRINT(("After Mode(%d) set, Phy (port %i) Reg 4 : %#x.\n",mode,port,u32Data)); + + } + } + + + } + return testResults; +} + +GT_U32 testPhy(GT_QD_DEV *dev) +{ + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + MSG_PRINT(("Not Implemented.\n")); + break; + default: + return testPhy1(dev); + } + return 0; +} + +GT_STATUS readStatistics(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + GT_PORT_STAT portStat; + + MSG_PRINT(("Current Port Statistics\n")); + for (port=0; portnumOfPorts; port++) + { + if((status = gprtGetPortCtr(dev,port,&portStat)) != GT_OK) + { + MSG_PRINT(("gprtGetPortCtr returned fail.\n")); + return status; + } + + MSG_PRINT(("Port %i : Rx %i, Tx %i.\n",port,portStat.rxCtr,portStat.txCtr)); + } + + MSG_PRINT(("After Clear Port Statistics\n")); + for (port=0; portnumOfPorts; port++) + { + if((status = gprtClearAllCtr(dev)) != GT_OK) + { + MSG_PRINT(("gprtClearAllCtr returned fail.\n")); + return status; + } + + if((status = gprtGetPortCtr(dev,port,&portStat)) != GT_OK) + { + MSG_PRINT(("gprtGetPortCtr returned fail.\n")); + return status; + } + + MSG_PRINT(("Port %i : Rx %i, Tx %i.\n",port,portStat.rxCtr,portStat.txCtr)); + } + return GT_OK; +} + +GT_STATUS testGoodPkt(GT_QD_DEV *dev) +{ + GT_STATUS status; + + if((status = gprtSetCtrMode(dev,GT_CTR_ALL)) != GT_OK) + { + MSG_PRINT(("gprtSetCtrMode returned fail.\n")); + return status; + } + return GT_OK; +} + +GT_STATUS testBadPkt(GT_QD_DEV *dev) +{ + GT_STATUS status; + + if((status = gprtSetCtrMode(dev,GT_CTR_ERRORS)) != GT_OK) + { + MSG_PRINT(("gprtSetCtrMode returned fail.\n")); + return status; + } + return GT_OK; +} + + +GT_U32 testPortStatus(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + GT_LPORT port; + GT_BOOL mode; + GT_U32 u32Mode; + GT_U16 u16Mode; + int portIndex; + + testResult = GT_OK; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + MSG_PRINT(("Port %i :\n",port)); + + if((status = gprtGetPartnerLinkPause(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetPartnerLinkPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("His Link Pause : %i ",(int)mode)); + + if((status = gprtGetSelfLinkPause(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetSelfLinkPause returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("My Link Pause : %i\n",(int)mode)); + + if((status = gprtGetLinkState(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetLinkState returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Link Status : %i ",(int)mode)); + + if((status = gprtGetResolve(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetResolve returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Resolve : %i\n",(int)mode)); + + if((status = gprtGetPortMode(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetPortMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Port Mode : %i ",(int)mode)); + + if((status = gprtGetPhyMode(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetPhyMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Phy Mode : %i\n",(int)mode)); + + if((status = gprtGetSpeed(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetSpeed returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Port Speed : %i ",(int)mode)); + + if((status = gprtGetDuplex(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetDuplex returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Port Duplex : %i\n",(int)mode)); + + MSG_PRINT(("Setting Port Duplex : %i\n",1-(int)mode)); + if((status = gprtSetDuplex(dev,port,1-mode)) != GT_OK) + { + MSG_PRINT(("gprtSetDuplex returned ")); + testDisplayStatus(status); + switch(dev->deviceId) + { + case GT_88E6021: + if(port != dev->cpuPortNum) + break; + else + { + testResults |= 1 << status; + if(status == GT_FAIL) + return testResults; + } + case GT_88E6051: + case GT_88E6052: + case GT_FF_HG: + case GT_FF_EG: + break; + case GT_88E6063: + case GT_FH_VPN: + if(port < 5) + break; + else + { + testResults |= 1 << status; + if(status == GT_FAIL) + return testResults; + } + break; + default: + break; + } + + } + else + { + GT_BOOL tmpMode; + if((status = gprtGetDuplex(dev,port,&tmpMode)) != GT_OK) + { + MSG_PRINT(("gprtGetDuplex returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + if(tmpMode != (1-mode)) + { + MSG_PRINT(("Setting Port Duplex Failed (current mode %i)\n",tmpMode)); + testResults |= 1 << GT_FAIL; + testResult = GT_FAIL; + } + else + MSG_PRINT(("Setting Port Duplex Passed.\n")); + + MSG_PRINT(("Setting Port Duplex : %i\n",mode)); + if((status = gprtSetDuplex(dev,port,mode)) != GT_OK) + { + MSG_PRINT(("gprtSetDuplex returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + if(status == GT_FAIL) + return testResults; + } + + if((status = gprtGetDuplex(dev,port,&tmpMode)) != GT_OK) + { + MSG_PRINT(("gprtGetDuplex returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + if(tmpMode != mode) + { + MSG_PRINT(("Setting Port Duplex Failed (current mode %i)\n",tmpMode)); + testResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + else + MSG_PRINT(("Setting Port Duplex Passed.\n")); + + } + + if((status = gprtGetTxPaused(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetTxPaused returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("TxPaused : %i ",(int)mode)); + + if((status = gprtGetFlowCtrl(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetFlowCtrl returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("FlowCtrl : %i\n",(int)mode)); + + if((status = gprtGetPxMode(dev,port,&u32Mode)) != GT_OK) + { + MSG_PRINT(("gprtGetPxMode returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("PxMode : %i ",(int)u32Mode)); + + if((status = gprtGetMiiInterface(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetMiiInterface returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Mii Interface : %i\n",(int)mode)); + + if((status = gprtGetHdFlowDis(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetHdFlowDis returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("HD Flow Dis. : %i ",(int)mode)); + + if((status = gprtGetFdFlowDis(dev,port,&mode)) != GT_OK) + { + MSG_PRINT(("gprtGetFdFlowDis returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("FD Flow Dis. : %i\n",(int)mode)); + + if((status = gprtGetOutQSize(dev,port,&u16Mode)) != GT_OK) + { + MSG_PRINT(("gprtGetOutQSize returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + MSG_PRINT(("Out Q Size : %i\n",(int)u16Mode)); + + } + + return testResults; +} + +GT_U32 testQoSRule(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + TEST_API testAPI; + + testResult = GT_OK; + + /* + * Priority Map Rule (IEEE if Both IEEE and IP) + */ + testAPI.getFunc.port_bool = gqosGetPrioMapRule; + testAPI.setFunc.port_bool = gqosSetPrioMapRule; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Priority Map Rule API test ")); + testDisplayStatus(status); + + /* + * IP Priority Map Rule (use IP) + */ + testAPI.getFunc.port_bool = gqosGetIpPrioMapEn; + testAPI.setFunc.port_bool = gqosIpPrioMapEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IP Priority Map Rule API test ")); + testDisplayStatus(status); + + /* + * IEEE Priority Map Rule (use IEEE Tag) + */ + testAPI.getFunc.port_bool = gqosGetUserPrioMapEn; + testAPI.setFunc.port_bool = gqosUserPrioMapEn; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("IEEE Priority Map Rule API test ")); + testDisplayStatus(status); + + /* + * VID FPri Override + */ + testAPI.getFunc.port_bool = gqosGetVIDFPriOverride; + testAPI.setFunc.port_bool = gqosSetVIDFPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("VID FPri Override API test ")); + testDisplayStatus(status); + + /* + * SA FPri Override + */ + testAPI.getFunc.port_bool = gqosGetSAFPriOverride; + testAPI.setFunc.port_bool = gqosSetSAFPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA FPri Override API test ")); + testDisplayStatus(status); + + /* + * DA FPri Override + */ + testAPI.getFunc.port_bool = gqosGetDAFPriOverride; + testAPI.setFunc.port_bool = gqosSetDAFPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DA FPri Override API test ")); + testDisplayStatus(status); + + /* + * VID QPri Override + */ + testAPI.getFunc.port_bool = gqosGetVIDQPriOverride; + testAPI.setFunc.port_bool = gqosSetVIDQPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("VID QPri Override API test ")); + testDisplayStatus(status); + + /* + * SA QPri Override + */ + testAPI.getFunc.port_bool = gqosGetSAQPriOverride; + testAPI.setFunc.port_bool = gqosSetSAQPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("SA QPri Override API test ")); + testDisplayStatus(status); + + /* + * DA QPri Override + */ + testAPI.getFunc.port_bool = gqosGetDAQPriOverride; + testAPI.setFunc.port_bool = gqosSetDAQPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("DA QPri Override API test ")); + testDisplayStatus(status); + + /* + * ARP QPri Override + */ + testAPI.getFunc.port_bool = gqosGetARPQPriOverride; + testAPI.setFunc.port_bool = gqosSetARPQPriOverride; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ARP QPri Override API test ")); + testDisplayStatus(status); + + /* + * Force QPri + */ + testAPI.getFunc.port_bool = gqosGetForceQPri; + testAPI.setFunc.port_bool = gqosSetForceQPri; + if((status = testPortBoolType(dev,&testAPI)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Force QPri API test ")); + testDisplayStatus(status); + + /* + * QPri Value + */ + testAPI.getFunc.port_u8 = gqosGetQPriValue; + testAPI.setFunc.port_u8 = gqosSetQPriValue; + if((status = testPortU8Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("QPri Value API test ")); + testDisplayStatus(status); + + /* + * Default FPri Value + */ + testAPI.getFunc.port_u8 = gqosGetDefFPri; + testAPI.setFunc.port_u8 = gqosSetDefFPri; + if((status = testPortU8Type(dev,&testAPI,8)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Default FPri Value API test ")); + testDisplayStatus(status); + + /* + * ARP QPri Value + */ + testAPI.getFunc.u16 = (GT_API_GET_U16)gqosGetArpQPri; + testAPI.setFunc.u16 = (GT_API_SET_U16)gqosSetArpQPri; + if((status = testU16Type(dev,&testAPI,4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("ARP QPri Value API test ")); + testDisplayStatus(status); + + + return testResults; +} + +GT_U32 testQoSMapG(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, sectionResult; + GT_U32 testResults = 0; + GT_U8 priority, remapped, tmpPri; + GT_LPORT port; + int portIndex; + + testResult = sectionResult = GT_OK; + + for(priority=0; priority<8; priority++) + { + remapped = 7 - priority; + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + if((status = gqosSetTagRemap(dev,portIndex, priority, remapped)) != GT_OK) + { + MSG_PRINT(("gqosSetTagRemap returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + tmpPri = 8; + if((status = gqosGetTagRemap(dev,portIndex, priority, &tmpPri)) != GT_OK) + { + MSG_PRINT(("gqosGetTagRemap returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (tmpPri != remapped) + { + MSG_PRINT(("QoS Remapping setup problem (pri:%#x,remap:%#x,port).\n",priority, remapped, port)); + sectionResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + } + } + + if(sectionResult == GT_OK) + { + MSG_PRINT(("QoS Remapping setup Pass.\n")); + } + else + { + MSG_PRINT(("Qos Remapping setup Fail.\n")); + testResult = sectionResult; + sectionResult = GT_OK; + } + + return testResults; +} + +GT_U32 testQoSMap(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, sectionResult; + GT_U32 testResults = 0; + GT_U8 priority, trClass; + TEST_API testAPI; + + testResult = sectionResult = GT_OK; + + /* + * Default Traffic Class Map + */ + testAPI.getFunc.port_u8 = gcosGetPortDefaultTc; + testAPI.setFunc.port_u8 = gcosSetPortDefaultTc; + if((status = testPortU8Type(dev,&testAPI, 4)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Default Traffic Class Setup ")); + testDisplayStatus(status); + + for(priority=0; priority<8; priority++) + { + if((status = gcosSetUserPrio2Tc(dev,priority,(priority&0x3))) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gcosGetUserPrio2Tc(dev,priority,&trClass)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (trClass != (priority&0x3)) + { + MSG_PRINT(("IEEE traffic Class setup problem (tr:%#x,pr:%#x).\n",trClass,priority)); + sectionResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + } + + if(sectionResult == GT_OK) + { + MSG_PRINT(("IEEE traffic Class setup Pass.\n")); + } + else + { + MSG_PRINT(("IEEE traffic Class setup Fail.\n")); + testResult = sectionResult; + sectionResult = GT_OK; + } + + for(priority=0; priority<0x40; priority++) + { + if((status = gcosSetDscp2Tc(dev,priority,(priority&0x3))) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gcosGetDscp2Tc(dev,priority,&trClass)) != GT_OK) + { + MSG_PRINT(("gcosGetDscp2Tc returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (trClass != (priority&0x3)) + { + MSG_PRINT(("IP traffic Class setup problem (tr:%#x,pr:%#x).\n",trClass,priority)); + sectionResult = GT_FAIL; + testResults |= 1 << GT_FAIL; + } + } + if(sectionResult == GT_OK) + { + MSG_PRINT(("IP traffic Class setup Pass.\n")); + } + else + { + MSG_PRINT(("IP traffic Class setup Fail.\n")); + testResult = sectionResult; + sectionResult = GT_OK; + } + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + testResults |= testQoSMapG(dev); + break; + default: + break; + } + return testResults; +} + + +GT_U32 testInterrupt(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult; + GT_U32 testResults = 0; + GT_LPORT port; + GT_U16 data, portIntCause, phyIntCause, tmpData; + int portIndex, phyCount; + + MSG_PRINT(("\ntesting Interrupt Handler : \n")); + + testResult = GT_OK; + + MSG_PRINT(("\nSetting up Interrupt Test...\n")); + + /* Enable QuarterDeck interrupt for ATUFull, ATUDone, PHYInt, and EEInt */ + data = GT_ATU_FULL|GT_ATU_DONE|GT_PHY_INTERRUPT|GT_EE_INTERRUPT; + if((status = eventSetActive(dev,data)) != GT_OK) + { + MSG_PRINT(("eventSetActive returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + /* + Enable Phy interrupt for Link Status Change, Speed Change, + * AutoNego Complete, and Duplex Changed for all phys. + */ + data = GT_SPEED_CHANGED|GT_DUPLEX_CHANGED|GT_AUTO_NEG_COMPLETED|GT_LINK_STATUS_CHANGED; + + switch(dev->deviceId) + { + case GT_88E6021: + phyCount = 2; + break; + case GT_88E6051: + phyCount = 4; + break; + case GT_88E6052: + case GT_88E6063: + case GT_FF_HG: + case GT_FF_EG: + case GT_FH_VPN: + phyCount = 5; + break; + default: + MSG_PRINT(("Unknown DEVICE. Assuming 88E6052.\n")); + phyCount = 5; + break; + } + + for(portIndex=0; portIndexInUnicasts)); + MSG_PRINT(("InBroadcasts %08i \n", statsCounter->InBroadcasts)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("InFCSErr %08i ", statsCounter->InFCSErr)); + MSG_PRINT(("AlignErr %08i \n", statsCounter->AlignErr)); + MSG_PRINT(("InGoodOctets %08i ", statsCounter->InGoodOctets)); + MSG_PRINT(("InBadOctets %08i \n", statsCounter->InBadOctets)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("In64Octets %08i ", statsCounter->In64Octets)); + MSG_PRINT(("In127Octets %08i \n", statsCounter->In127Octets)); + MSG_PRINT(("In255Octets %08i ", statsCounter->In255Octets)); + MSG_PRINT(("In511Octets %08i \n", statsCounter->In511Octets)); + MSG_PRINT(("In1023Octets %08i ", statsCounter->In1023Octets)); + MSG_PRINT(("InMaxOctets %08i \n", statsCounter->InMaxOctets)); + MSG_PRINT(("Jabber %08i ", statsCounter->Jabber)); + MSG_PRINT(("Oversize %08i \n", statsCounter->Oversize)); + MSG_PRINT(("InDiscards %08i ", statsCounter->InDiscards)); + MSG_PRINT(("Filtered %08i \n", statsCounter->Filtered)); + MSG_PRINT(("OutUnicasts %08i ", statsCounter->OutUnicasts)); + MSG_PRINT(("OutBroadcasts %08i \n", statsCounter->OutBroadcasts)); + MSG_PRINT(("OutPause %08i ", statsCounter->OutPause)); + MSG_PRINT(("OutMulticasts %08i \n", statsCounter->OutMulticasts)); + MSG_PRINT(("OutFCSErr %08i ", statsCounter->OutFCSErr)); + MSG_PRINT(("OutGoodOctets %08i \n", statsCounter->OutGoodOctets)); + MSG_PRINT(("Out64Octets %08i ", statsCounter->Out64Octets)); + MSG_PRINT(("Out127Octets %08i \n", statsCounter->Out127Octets)); + MSG_PRINT(("Out255Octets %08i ", statsCounter->Out255Octets)); + MSG_PRINT(("Out511Octets %08i \n", statsCounter->Out511Octets)); + MSG_PRINT(("Out1023Octets %08i ", statsCounter->Out1023Octets)); + MSG_PRINT(("OutMaxOctets %08i \n", statsCounter->OutMaxOctets)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); + MSG_PRINT(("Excessive %08i ", statsCounter->Excessive)); + MSG_PRINT(("Multiple %08i \n", statsCounter->Multiple)); + MSG_PRINT(("Single %08i ", statsCounter->Single)); + MSG_PRINT(("Deferred %08i \n", statsCounter->Deferred)); + MSG_PRINT(("OutDiscards %08i \n", statsCounter->OutDiscards)); +} + +GT_STATUS testDisplayRMONCounter(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_STATS_COUNTER_SET statsCounterSet; + + MSG_PRINT(("Getting counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + return status; + } + + testDisplayCounter(&statsCounterSet); + return GT_OK; +} + +GT_U32 testRMON1(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, tmpResult; + GT_U32 testResults = 0; + GT_STATS_COUNTERS counter; + GT_STATS_COUNTER_SET statsCounterSet; + GT_U32 statsData; + GT_LPORT port; + int portIndex; + + testResult=GT_OK; + + MSG_PRINT(("\ntesting RMON Counter :\n")); + MSG_PRINT(("RMON testing assumes no more activities in the device.\n")); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + tmpResult = GT_OK; + port = portIndex; + + MSG_PRINT(("Getting all counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + MSG_PRINT(("Getting individual counter for port %i.\n", port)); + + for(counter=STATS_InUnicasts; counter<=STATS_OutDiscards; counter++) + { + if((status = gstatsGetPortCounter(dev,port, counter, &statsData)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortCounter returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (statsData != *((GT_U32*)&statsCounterSet + counter)) + { + MSG_PRINT(("gstatsGetPortCounter(%i) mismatches gstatsGetPortAllCounter (%i : %i).\n", + counter,statsData,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Comparing counters: (PASS)\n")); + } + else + { + MSG_PRINT(("Comparing counters: (FAIL)\n")); + } + + if (!(port % 2)) + continue; + + MSG_PRINT(("Flushing the counter for port %i\n",port)); + + tmpResult = GT_OK; + + if((status = gstatsFlushPort(dev,port)) != GT_OK) + { + MSG_PRINT(("gstatsFlushPort returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gstatsGetPortAllCounters(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS_InUnicasts; counter<=STATS_OutDiscards; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (counter : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush: (FAIL)\n")); + } + + } + + /* Now RMON counters of the ports with even numbers are flushed */ + MSG_PRINT(("Flushing the counters for all port\n")); + tmpResult = GT_OK; + if((status = gstatsFlushAll(dev)) != GT_OK) + { + MSG_PRINT(("gstatsFlushAll returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + if((status = gstatsGetPortAllCounters(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS_InUnicasts; counter<=STATS_OutDiscards; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (stats : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush ALL: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush ALL: (FAIL)\n")); + } + + return testResults; +} + +void testDisplayCounter2(GT_STATS_COUNTER_SET2 *statsCounter) +{ + MSG_PRINT(("InGoodOctetsHi %08i ", statsCounter->InGoodOctetsHi)); + MSG_PRINT(("InGoodOctetsLo %08i \n", statsCounter->InGoodOctetsLo)); + MSG_PRINT(("InBadOctets %08i ", statsCounter->InBadOctets)); + MSG_PRINT(("OutDiscards %08i \n", statsCounter->OutDiscards)); + MSG_PRINT(("InGoodFrames %08i ", statsCounter->InGoodFrames)); + MSG_PRINT(("InBadFrames %08i \n", statsCounter->InBadFrames)); + MSG_PRINT(("InBroadcasts %08i ", statsCounter->InBroadcasts)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("64Octets %08i ", statsCounter->Octets64)); + MSG_PRINT(("127Octets %08i \n", statsCounter->Octets127)); + MSG_PRINT(("255Octets %08i ", statsCounter->Octets255)); + MSG_PRINT(("511Octets %08i \n", statsCounter->Octets511)); + MSG_PRINT(("1023Octets %08i ", statsCounter->Octets1023)); + MSG_PRINT(("MaxOctets %08i \n", statsCounter->OctetsMax)); + MSG_PRINT(("OutOctetsHi %08i ", statsCounter->OutOctetsHi)); + MSG_PRINT(("OutOctetsLo %08i \n", statsCounter->OutOctetsLo)); + MSG_PRINT(("OutFrames %08i ", statsCounter->OutFrames)); + MSG_PRINT(("Excessive %08i \n", statsCounter->Excessive)); + MSG_PRINT(("OutMulticasts %08i ", statsCounter->OutMulticasts)); + MSG_PRINT(("OutBroadcasts %08i ", statsCounter->OutBroadcasts)); + MSG_PRINT(("InBadMACCtrl %08i ", statsCounter->InBadMACCtrl)); + MSG_PRINT(("OutPause %08i \n", statsCounter->OutPause)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("InDiscards %08i \n", statsCounter->InDiscards)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("Oversize %08i ", statsCounter->Oversize)); + MSG_PRINT(("Jabber %08i \n", statsCounter->Jabber)); + MSG_PRINT(("MACRcvErr %08i ", statsCounter->MACRcvErr)); + MSG_PRINT(("InFCSErr %08i \n", statsCounter->InFCSErr)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); +} + +GT_STATUS testDisplayRMONCounter2(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_STATS_COUNTER_SET2 statsCounterSet; + + MSG_PRINT(("Getting counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters2(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters2 returned ")); + testDisplayStatus(status); + return status; + } + + testDisplayCounter2(&statsCounterSet); + return GT_OK; +} + +GT_U32 testRMON2(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, tmpResult; + GT_U32 testResults = 0; + GT_STATS_COUNTERS2 counter; + GT_STATS_COUNTER_SET2 statsCounterSet; + GT_U32 statsData; + GT_LPORT port; + int portIndex; + TEST_API testAPI; + + testResult=GT_OK; + + /* + * Histogram Mode Setup + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gstatsGetHistogramMode; + testAPI.setFunc.u32 = (GT_API_SET_U32)gstatsSetHistogramMode; + if((status = testU32Type(dev,&testAPI,3)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Histogram Mode Setup API test ")); + testDisplayStatus(status); + MSG_PRINT(("\ntesting RMON Counter :\n")); + MSG_PRINT(("RMON testing assumes no more activities in the device.\n")); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + tmpResult = GT_OK; + port = portIndex; + + MSG_PRINT(("Getting all counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters2(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters2 returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + MSG_PRINT(("Getting individual counter for port %i.\n", port)); + + for(counter=STATS2_InGoodOctetsHi; counter<=STATS2_Late; counter++) + { + if((status = gstatsGetPortCounter2(dev,port, counter, &statsData)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortCounter2 returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (statsData != *((GT_U32*)&statsCounterSet + counter)) + { + MSG_PRINT(("gstatsGetPortCounter2(%i) mismatches gstatsGetPortAllCounter2 (%i : %i).\n", + counter,statsData,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Comparing counters: (PASS)\n")); + } + else + { + MSG_PRINT(("Comparing counters: (FAIL)\n")); + } + + if (!(port % 2)) + continue; + + MSG_PRINT(("Flushing the counter for port %i\n",port)); + + tmpResult = GT_OK; + + if((status = gstatsFlushPort(dev,port)) != GT_OK) + { + MSG_PRINT(("gstatsFlushPort returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gstatsGetPortAllCounters2(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS2_InGoodOctetsHi; counter<=STATS2_Late; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (counter : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush: (FAIL)\n")); + } + + } + + /* Now RMON counters of the ports with even numbers are flushed */ + MSG_PRINT(("Flushing the counters for all port\n")); + tmpResult = GT_OK; + if((status = gstatsFlushAll(dev)) != GT_OK) + { + MSG_PRINT(("gstatsFlushAll returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + if((status = gstatsGetPortAllCounters2(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS2_InGoodOctetsHi; counter<=STATS2_Late; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (stats : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush ALL: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush ALL: (FAIL)\n")); + } + + return testResults; +} + +void testDisplayCounter3(GT_STATS_COUNTER_SET3 *statsCounter) +{ + MSG_PRINT(("InGoodOctetsLo %08i ", statsCounter->InGoodOctetsLo)); + MSG_PRINT(("InGoodOctetsHi %08i \n", statsCounter->InGoodOctetsHi)); + MSG_PRINT(("InBadOctets %08i ", statsCounter->InBadOctets)); + MSG_PRINT(("OutFCSErr %08i \n", statsCounter->OutFCSErr)); + MSG_PRINT(("InUnicasts %08i ", statsCounter->InUnicasts)); + MSG_PRINT(("Deferred %08i \n", statsCounter->Deferred)); + MSG_PRINT(("InBroadcasts %08i ", statsCounter->InBroadcasts)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("64Octets %08i ", statsCounter->Octets64)); + MSG_PRINT(("127Octets %08i \n", statsCounter->Octets127)); + MSG_PRINT(("255Octets %08i ", statsCounter->Octets255)); + MSG_PRINT(("511Octets %08i \n", statsCounter->Octets511)); + MSG_PRINT(("1023Octets %08i ", statsCounter->Octets1023)); + MSG_PRINT(("MaxOctets %08i \n", statsCounter->OctetsMax)); + MSG_PRINT(("OutOctetsLo %08i ", statsCounter->OutOctetsLo)); + MSG_PRINT(("OutOctetsHi %08i \n", statsCounter->OutOctetsHi)); + MSG_PRINT(("OutUnicasts %08i ", statsCounter->OutUnicasts)); + MSG_PRINT(("Excessive %08i \n", statsCounter->Excessive)); + MSG_PRINT(("OutMulticasts %08i ", statsCounter->OutMulticasts)); + MSG_PRINT(("OutBroadcasts %08i \n", statsCounter->OutBroadcasts)); + MSG_PRINT(("Single %08i ", statsCounter->Single)); + MSG_PRINT(("OutPause %08i \n", statsCounter->OutPause)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("Multiple %08i \n", statsCounter->Multiple)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("Oversize %08i ", statsCounter->Oversize)); + MSG_PRINT(("Jabber %08i \n", statsCounter->Jabber)); + MSG_PRINT(("InMACRcvErr %08i ", statsCounter->InMACRcvErr)); + MSG_PRINT(("InFCSErr %08i \n", statsCounter->InFCSErr)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); +} + +GT_STATUS testDisplayRMONCounter3(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_STATS_COUNTER_SET3 statsCounterSet; + + MSG_PRINT(("Getting counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters3(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters3 returned ")); + testDisplayStatus(status); + return status; + } + + testDisplayCounter3(&statsCounterSet); + return GT_OK; +} + +GT_U32 testRMON3(GT_QD_DEV *dev) +{ + GT_STATUS status, testResult, tmpResult; + GT_U32 testResults = 0; + GT_STATS_COUNTERS3 counter; + GT_STATS_COUNTER_SET3 statsCounterSet; + GT_U32 statsData; + GT_LPORT port; + int portIndex; + TEST_API testAPI; + + testResult=GT_OK; + + /* + * Histogram Mode Setup + */ + testAPI.getFunc.u32 = (GT_API_GET_U32)gstatsGetHistogramMode; + testAPI.setFunc.u32 = (GT_API_SET_U32)gstatsSetHistogramMode; + if((status = testU32Type(dev,&testAPI,3)) != GT_OK) + { + testResult = GT_FAIL; + testResults |= 1 << status; + } + MSG_PRINT(("Histogram Mode Setup API test ")); + testDisplayStatus(status); + MSG_PRINT(("\ntesting RMON Counter :\n")); + MSG_PRINT(("RMON testing assumes no more activities in the device.\n")); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + tmpResult = GT_OK; + port = portIndex; + + MSG_PRINT(("Getting all counters for port %i.\n", port)); + + if((status = gstatsGetPortAllCounters3(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters3 returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + MSG_PRINT(("Getting individual counter for port %i.\n", port)); + + for(counter=STATS3_InGoodOctetsLo; counter<=STATS3_Late; counter++) + { + if((status = gstatsGetPortCounter3(dev,port, counter, &statsData)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortCounter3 returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if (statsData != *((GT_U32*)&statsCounterSet + counter)) + { + MSG_PRINT(("gstatsGetPortCounter3(%i) mismatches gstatsGetPortAllCounter3 (%i : %i).\n", + counter,statsData,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Comparing counters: (PASS)\n")); + } + else + { + MSG_PRINT(("Comparing counters: (FAIL)\n")); + } + + if (!(port % 2)) + continue; + + MSG_PRINT(("Flushing the counter for port %i\n",port)); + + tmpResult = GT_OK; + + if((status = gstatsFlushPort(dev,port)) != GT_OK) + { + MSG_PRINT(("gstatsFlushPort returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + if((status = gstatsGetPortAllCounters3(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS3_InGoodOctetsLo; counter<=STATS3_Late; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (counter : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush: (FAIL)\n")); + } + + } + + /* Now RMON counters of the ports with even numbers are flushed */ + MSG_PRINT(("Flushing the counters for all port\n")); + tmpResult = GT_OK; + if((status = gstatsFlushAll(dev)) != GT_OK) + { + MSG_PRINT(("gstatsFlushAll returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + if((status = gstatsGetPortAllCounters3(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned ")); + testDisplayStatus(status); + testResults |= 1 << status; + return testResults; + } + + for(counter=STATS3_InGoodOctetsLo; counter<=STATS3_Late; counter++) + { + if (*((GT_U32*)&statsCounterSet + counter) != 0) + { + MSG_PRINT(("gstatsFlushPort(%i) failed (stats : %i).\n", + counter,*((GT_U32*)&statsCounterSet + counter))); + testResult = GT_FAIL; + tmpResult = GT_FAIL; + testResults |= 1 << tmpResult; + continue; + } + } + + } + + if(tmpResult == GT_OK) + { + MSG_PRINT(("Flush ALL: (PASS)\n")); + } + else + { + MSG_PRINT(("Flush ALL: (FAIL)\n")); + } + + return testResults; +} + +GT_U32 testRMON(GT_QD_DEV *dev) +{ + GT_U32 testResults; + + switch(dev->deviceId) + { + case GT_88E6153: + case GT_88E6183: + testResults = testRMON2(dev); + break; + case GT_88E6093: + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + testResults = testRMON3(dev); + break; + default: + testResults = testRMON1(dev); + break; + } + + return testResults; +} + +void testDisplayVTUEntry(GT_QD_DEV *dev, GT_VTU_ENTRY *vtuEntry) +{ + GT_LPORT port; + int portIndex; + + MSG_PRINT(("DBNum:%i, VID:%i, ",vtuEntry->DBNum,vtuEntry->vid)); + MSG_PRINT(("Tag: ")); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + MSG_PRINT(("%#x ",port,vtuEntry->vtuData.memberTagP[port])); + } + MSG_PRINT(("\n")); + + MSG_PRINT(("%i,%i,%i,%i,%i,%i,%i\n", + vtuEntry->vidPriOverride, + vtuEntry->vidPriority, + vtuEntry->vidExInfo.useVIDFPri, + vtuEntry->vidExInfo.vidFPri, + vtuEntry->vidExInfo.useVIDQPri, + vtuEntry->vidExInfo.vidQPri, + vtuEntry->vidExInfo.vidNRateLimit + )); + +} + +void testDisplayVTUList(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_VTU_ENTRY vtuEntry; + + memset(&vtuEntry,0,sizeof(GT_VTU_ENTRY)); + vtuEntry.vid = 0xfff; + if((status = gvtuGetEntryFirst(dev,&vtuEntry)) != GT_OK) + { + MSG_PRINT(("gvtuGetEntryCount returned ")); + testDisplayStatus(status); + return; + } + + testDisplayVTUEntry(dev,&vtuEntry); + + while(1) + { + if((status = gvtuGetEntryNext(dev,&vtuEntry)) != GT_OK) + { + break; + } + testDisplayVTUEntry(dev,&vtuEntry); + } + +} + +GT_STATUS testWriteVTU(GT_QD_DEV *dev, GT_VTU_ENTRY *vtuEntry, GT_U32 vid, GT_U32 DBNum, GT_U32 portVec) +{ + int i; + + vtuEntry->vid = vid & 0xFFF; + vtuEntry->DBNum = DBNum & 0xF; + vtuEntry->vidPriOverride = 0; + vtuEntry->vidPriority = 0; + + for(i=0; i<16; i++) + { + if((portVec>>i) & 0x1) + vtuEntry->vtuData.memberTagP[i] = 3; + else + vtuEntry->vtuData.memberTagP[i] = 0; + + } + + return GT_OK; +} + +/* + VTU APIs Test Scenario: + 1) Flush VTU entries and check Entry Count. + 2) Create a list of 16 VID entries based on arg param. + (descending, ascending, and random order) + 3) Add a Entry. + 4) check Entry Count, call EntryFirst and EntryNext. + 5) Add 16/64/4096 more Entries.(Last entry should be failed to be added) + 6) Delete 2 valid entries and 1 invalid entry + 7) Check Entry Count, and try to find a valid entry and deleted entry. +*/ + +GT_STATUS testVTUCtrl(GT_QD_DEV *dev,int arg) +{ +#define MAX_VTU_ENTRIES 4096 + GT_STATUS status, testResult, tmpResult; + GT_VTU_ENTRY vtuEntry[MAX_VTU_ENTRIES+1]; + GT_VTU_ENTRY tmpVtuEntry; + GT_U32 u32Data1, u32Data2, u32Data3, maxDbNum, priType; + GT_BOOL found; + int i, j, portIndex; + GT_LPORT port; + int maxVtuEntries; + GT_BOOL supportMaxEntry = GT_FALSE; + + testResult = GT_OK; + maxDbNum = 1; + + switch(dev->deviceId) + { + case GT_88E6021: + maxVtuEntries = 16; + maxDbNum = 1; + priType = 0; /* no VID Priority override support */ + break; + case GT_88E6063: + case GT_FH_VPN: + case GT_88E6083: + maxVtuEntries = 64; + maxDbNum = 16; + priType = 0; /* no VID Priority override support */ + break; + case GT_88E6153: + case GT_88E6183: + case GT_88E6093: + maxVtuEntries = 64; + maxDbNum = 16; + supportMaxEntry = GT_TRUE; + priType = 1; /* VID Priority override support */ + break; + case GT_88E6031: + case GT_88E6061: + maxVtuEntries = 16; + maxDbNum = 16; + priType = 2; /* Extended VID Priority override support */ + break; + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + maxVtuEntries = 64; + maxDbNum = 64; + priType = 3; /* Extended VID Priority override support */ + break; + case GT_88E6095: + case GT_88E6092: + case GT_88E6152: + case GT_88E6155: + case GT_88E6182: + case GT_88E6185: + case GT_88E6131: + case GT_88E6108: + maxVtuEntries = 64; + maxDbNum = 256; + supportMaxEntry = GT_TRUE; + priType = 1; /* VID Priority override support */ + break; + default: + maxVtuEntries = 16; + priType = 0; /* no VID Priority override support */ + break; + } + + /* 1) Flush VTU entries and check Entry Count */ + MSG_PRINT(("Flushing VTU entries: ")); + if((status = gvtuFlush(dev)) != GT_OK) + { + MSG_PRINT(("gvtuFlush returned ")); + testDisplayStatus(status); + return status; + } + + if((status = gvtuGetEntryCount(dev,&u32Data1)) != GT_OK) + { + MSG_PRINT(("gvtuGetEntryCount returned ")); + testDisplayStatus(status); + return status; + } + + if(u32Data1 != 0) + { + MSG_PRINT(("\nEntryCount %i (Failed, should be 0)\n",u32Data1)); + testResult = GT_FAIL; + } + else + { + MSG_PRINT(("(PASS)\n")); + } + + /* + 2) Create a list of 16 VID entries based on arg param. + (descending, ascending, and random order) + */ + MSG_PRINT(("Creating a list of %i VID\n",maxVtuEntries+1)); + srand((unsigned)time(NULL)); + switch (arg) + { + case 0: /* Ascending order */ + /* check if it supports MX_VTU_ENTRIES */ + if (maxVtuEntries == MAX_VTU_ENTRIES) + { + for(i=0; inumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[i].vtuData.memberTagP[port] = (vtuEntry[i].vid+port)%4; + } + switch(priType) + { + case 0: + break; + case 1: + vtuEntry[i].vidPriOverride = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if(vtuEntry[i].vidPriOverride == GT_TRUE) + vtuEntry[i].vidPriority = (GT_U8)(rand() & 0x7); + break; + case 2: + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + case 3: + vtuEntry[i].vidExInfo.useVIDFPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDFPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidFPri = (GT_U8)(rand() & 0x7); + vtuEntry[i].vidExInfo.useVIDQPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDQPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidQPri = (GT_U8)(rand() & 0x3); + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + default: + break; + } + } + break; + } + + u32Data1 = (rand()%1024) + 1; + u32Data2 = (rand()%32) + 1; + for(i=0; inumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[i].vtuData.memberTagP[port] = (vtuEntry[i].vid+port)%4; + } + switch(priType) + { + case 0: + break; + case 1: + vtuEntry[i].vidPriOverride = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if(vtuEntry[i].vidPriOverride == GT_TRUE) + vtuEntry[i].vidPriority = (GT_U8)(rand() & 0x7); + break; + case 2: + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + case 3: + vtuEntry[i].vidExInfo.useVIDFPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDFPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidFPri = (GT_U8)(rand() & 0x7); + vtuEntry[i].vidExInfo.useVIDQPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDQPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidQPri = (GT_U8)(rand() & 0x3); + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + default: + break; + } + } + break; + + case 1: /* Descending order */ + /* check if it supports MX_VTU_ENTRIES */ + if (maxVtuEntries == MAX_VTU_ENTRIES) + { + for(i=0; inumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[i].vtuData.memberTagP[port] = (vtuEntry[i].vid+port)%4; + } + switch(priType) + { + case 0: + break; + case 1: + vtuEntry[i].vidPriOverride = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if(vtuEntry[i].vidPriOverride == GT_TRUE) + vtuEntry[i].vidPriority = (GT_U8)(rand() & 0x7); + break; + case 2: + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + case 3: + vtuEntry[i].vidExInfo.useVIDFPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDFPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidFPri = (GT_U8)(rand() & 0x7); + vtuEntry[i].vidExInfo.useVIDQPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDQPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidQPri = (GT_U8)(rand() & 0x3); + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + default: + break; + } + } + memset(&vtuEntry[i],0,sizeof(GT_VTU_ENTRY)); + vtuEntry[i].DBNum = 2; + vtuEntry[i].vid = 5; /* choose any value. this entry is only for checking error. */ + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[i].vtuData.memberTagP[port] = (vtuEntry[i].vid+port)%4; + } + + break; + + } + u32Data1 = (rand()%1024) + 1; + u32Data2 = (rand()%32) + 1; + for(i=0; inumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[maxVtuEntries-i].vtuData.memberTagP[port] = (vtuEntry[maxVtuEntries-i].vid+port)%4; + } + switch(priType) + { + case 0: + break; + case 1: + vtuEntry[i].vidPriOverride = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if(vtuEntry[i].vidPriOverride == GT_TRUE) + vtuEntry[i].vidPriority = (GT_U8)(rand() & 0x7); + break; + case 2: + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + case 3: + vtuEntry[i].vidExInfo.useVIDFPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDFPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidFPri = (GT_U8)(rand() & 0x7); + vtuEntry[i].vidExInfo.useVIDQPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDQPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidQPri = (GT_U8)(rand() & 0x3); + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + default: + break; + } + } + break; + + default: /* random order */ + for(i=0; i i)?(maxDbNum-i)%maxDbNum:(i-maxDbNum)%maxDbNum; + vtuEntry[i].vid = (rand() & 0xF) | ((rand() & 0xF) << 4) | ((rand() & 0xF) << 8); + for(j=0; jnumOfPorts; portIndex++) + { + port = portIndex; + + vtuEntry[i].vtuData.memberTagP[port] = (vtuEntry[i].vid+port)%4; + } + switch(priType) + { + case 0: + break; + case 1: + vtuEntry[i].vidPriOverride = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if(vtuEntry[i].vidPriOverride == GT_TRUE) + vtuEntry[i].vidPriority = (GT_U8)(rand() & 0x7); + break; + case 2: + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + case 3: + vtuEntry[i].vidExInfo.useVIDFPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDFPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidFPri = (GT_U8)(rand() & 0x7); + vtuEntry[i].vidExInfo.useVIDQPri = (rand() & 0x1)?GT_TRUE:GT_FALSE; + if (vtuEntry[i].vidExInfo.useVIDQPri == GT_TRUE) + vtuEntry[i].vidExInfo.vidQPri = (GT_U8)(rand() & 0x3); + vtuEntry[i].vidExInfo.vidNRateLimit = (rand() & 0x1)?GT_TRUE:GT_FALSE; + break; + default: + break; + } + } + break; + + } + +#if 0 /* display VTU entries */ + for(i=0; ideviceId) + { + case GT_88E6031: + case GT_88E6061: + restrict = GT_TRUE; + break; + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + restrict = GT_FALSE; + break; + default: + return GT_NOT_SUPPORTED; + } + + /* Ingress Rate */ + data = rand() % 200001; + if(data == 0) + data = 64; + else if(data < 1000) + data = data - (data % 64); + else if(data < 100000) + data = data - (data % 1000); + else + data = data - (data % 10000); + + pdata->ingressRate = data; + + pdata->accountQConf = (rand() & 0x1)?GT_TRUE:GT_FALSE; + pdata->accountFiltered = (rand() & 0x1)?GT_TRUE:GT_FALSE; + pdata->ebsLimitAction = (rand() & 0x1); + if (restrict) + { + pdata->bktRateType = 0; + pdata->bktTypeMask = (rand() & 0xF); + } + else + { + pdata->bktRateType = (rand() & 0x1); + if (pdata->bktRateType == 0) + pdata->bktTypeMask = (rand() & 0x7F); + else + pdata->bktTypeMask = 0; + } + + pdata->byteTobeCounted = (rand() % 3); + + *vec = rand() & ((1<numOfPorts) - 1); + if(*vec == 0) + *vec = 0x7; + + if(pdata->ebsLimitAction == 0) + { + return GT_OK; + } + + for(port=0; portnumOfPorts; port++) + { + if(*vec & (1 << port)) + pdata->fcDeassertMode[port] = port & 0x1; + } + + return GT_OK; +} + +GT_U32 testPIRL(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_U32 testResults = 0; + GT_U32 i, portVec[12], tmpPortVec, pirlSize; + GT_PIRL_DATA pirlData[12], tmpPirlData; + + srand((unsigned)time(NULL)); + + memset(&pirlData[0],0,sizeof(GT_PIRL_DATA)); + + switch (dev->deviceId) + { + case GT_88E6031: + pirlSize = 3; + break; + case GT_88E6061: + case GT_88E6035: + pirlSize = 6; + break; + case GT_88E6055: + case GT_88E6065: + pirlSize = 12; + break; + default: + return 1 << GT_NOT_SUPPORTED; + } + + + MSG_PRINT(("Try Invalid PIRL API call\n")); + + /* try PIRL APIs without Activating it */ + + pirlData[0].ingressRate = 64; + + if((status = gpirlUpdateParam(dev, 0, &pirlData[0])) == GT_OK) + { + MSG_PRINT(("gpirlUpdateParam returned ")); + testDisplayStatus(status); + testResults |= 1 << GT_FAIL; + } + if (status == GT_NOT_SUPPORTED) + return status; + + portVec[0] = 0x7; + + if((status = gpirlUpdatePortVec(dev, 0, portVec[0])) == GT_OK) + { + MSG_PRINT(("gpirlUpdateParam returned ")); + testDisplayStatus(status); + testResults |= 1 << GT_FAIL; + } + + if (testResults) + { + MSG_PRINT(("Invalid PIRL API call failed\n")); + } + else + { + MSG_PRINT(("Invalid PIRL API call successed\n")); + } + + + /* Activate PIRL */ + MSG_PRINT(("Filling up the PIRL Data...\n")); + for(i=0; inormCableLen) + { + case GT_LESS_THAN_50M: + MSG_PRINT(("Cable Length is less than 50M.\n")); + break; + case GT_50M_80M: + MSG_PRINT(("Cable Length is between 50M and 80M.\n")); + break; + case GT_80M_110M: + MSG_PRINT(("Cable Length is between 80M and 110M.\n")); + break; + case GT_110M_140M: + MSG_PRINT(("Cable Length is between 110M and 140M.\n")); + break; + case GT_MORE_THAN_140: + MSG_PRINT(("Cable Length is over 140M.\n")); + break; + default: + MSG_PRINT(("Cable Length is unknown.\n")); + break; + } + break; + case GT_OPEN_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is open.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + case GT_SHORT_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is short.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + default: + MSG_PRINT(("Unknown Test Result.\n")); + break; + } +} + +GT_STATUS dumpATUInfo(ATU_ENTRY_INFO *atuInfo, int entry) +{ + int i; + + for(i=0; iatuEntry); + atuInfo++; + } + return GT_OK; +} + +GT_STATUS testWriteATU(GT_QD_DEV *dev,GT_U8 atuSize,GT_U8 dbNum,GT_U32 entryState,GT_U32 macHiAddr,GT_U32 entries) +{ + GT_STATUS status; + ATU_ENTRY_INFO *atuEntry; + GT_U16 maxMacs, i; + + if(atuSize >= 5) + return GT_FAIL; + + if(entries == 0) + maxMacs = 256 << atuSize; + else + maxMacs = entries; + + if (gAtuEntry == NULL) + gAtuEntry = (ATU_ENTRY_INFO *)malloc(sizeof(ATU_ENTRY_INFO)*4096); + + atuEntry = gAtuEntry; + + gtMemSet(atuEntry,0,sizeof(ATU_ENTRY_INFO)*maxMacs); + + MSG_PRINT(("Getting ATU List(%i).\n",maxMacs)); + if((status=testFillUpAtu(dev,atuEntry,atuSize,dbNum,(GT_U16)macHiAddr,entryState)) != GT_OK) + { + MSG_PRINT(("testFillUpAtu returned ")); + testDisplayStatus(status); + return status; + } + + MSG_PRINT(("Writing ATU List(%i).\n",maxMacs)); + for(i=0; ibaseRegAddr; + + MSG_PRINT(("Switch Status (offset 0): ")); + gsysReadMiiReg(dev,regBaseAddr+0xF,0,&u32Data); + MSG_PRINT(("%#04x\n",u32Data & 0xFFFF)); + + MSG_PRINT(("VTU Status (offset 5) : ")); + gsysReadMiiReg(dev,regBaseAddr+0xF,5,&u32Data); + MSG_PRINT(("%#04x\n",u32Data & 0xFFFF)); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + MSG_PRINT(("Port %i Status (offset 0): ", port)); + gsysReadMiiReg(dev,regBaseAddr+0x8+port,0,&u32Data); + MSG_PRINT(("%#04x\n",u32Data & 0xFFFF)); + } + return GT_OK; +} +GT_STATUS testHelp() +{ + MSG_PRINT(("qdStart - to Initialize QuarterDeck driver\n")); + MSG_PRINT(("testSysCtrl - to test System Control API\n")); + MSG_PRINT(("testPort - to test Port Control API\n")); + MSG_PRINT(("testATU - to test ATU related API\n")); + MSG_PRINT(("testRMON - to test RMON related API\n")); + MSG_PRINT(("testVTU - to test VTU related API\n")); + MSG_PRINT(("testSysStatus - to test System Status related API\n")); + MSG_PRINT(("testVlan - to test Vlan related API\n")); + MSG_PRINT(("testSTP - to test STP related API\n")); + MSG_PRINT(("testPhy - to test Phy related API\n")); + MSG_PRINT(("testPortStatus - to test Port Status related API\n")); + MSG_PRINT(("testQosRule - to test QoS Rule related API\n")); + MSG_PRINT(("testQosMap - to test QoS Map related API\n")); + MSG_PRINT(("testPortRateCtrl - to test Port Rate Control API\n")); + MSG_PRINT(("testPortPAV - to test Port Association Vector API\n")); + MSG_PRINT(("testInterrupt - to test Interrupt related API\n")); + MSG_PRINT(("testAll - to run all the test specified above.\n")); + MSG_PRINT(("\n")); + MSG_PRINT(("vctTest - to run Virtual Cable Test on a given port.\n")); + MSG_PRINT(("defaultVlan - to setup Vlan for firewall app\n")); + MSG_PRINT(("readStatistics - to read statistics\n")); + MSG_PRINT(("testGoodPkt - to setup Good Packet only mode\n")); + MSG_PRINT(("testBadPkt - to setup Bad Packet only mode\n")); + MSG_PRINT(("testDisplayATUList - to display ATU list in the device\n")); + MSG_PRINT(("testDisplayRMONCounter - to display RMON counter of a port\n")); + MSG_PRINT(("testDisplayVTUList - to display VTU list in the device\n")); + MSG_PRINT(("qdStatusShow - to display the status of the device\n")); + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/utils.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/utils.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Diag/utils.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Diag/utils.c 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,711 @@ +#include +/******************************************************************************** +* utils.c +* +* DESCRIPTION: +* Collection of Utility functions +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +static GT_U16 hashMode = 0; +int testPrintEnable = 1; + +void testPrint(char* format, ...) +{ + va_list argP; + char dbgStr[1000] = ""; + + if(testPrintEnable == 0) + return; + + va_start(argP, format); + + vsprintf(dbgStr, format, argP); + + printf("%s",dbgStr); + + return; +} + +int vtuEntryCmpFunc(void* buf, int a, int b) +{ + GT_VTU_ENTRY* vtuEntry = (GT_VTU_ENTRY*)buf; + + if ((vtuEntry+a)->vid > (vtuEntry+b)->vid) + return 1; + else if ((vtuEntry+a)->vid < (vtuEntry+b)->vid) + return -1; + else + return 0; +} + +int atuEntryCmpFunc(void* buf, int a, int b) +{ + GT_ATU_ENTRY *atuEntry = (GT_ATU_ENTRY *)buf; + GT_U8* aChar,* bChar; + int i; + + aChar = (GT_U8*)((atuEntry+a)->macAddr.arEther); + bChar = (GT_U8*)((atuEntry+b)->macAddr.arEther); + + for (i=0; i<6; i++) + { + if(*aChar > *bChar) + return 1; + else if (*aChar < *bChar) + return -1; + aChar++; + bChar++; + } + + return 0; + +} + +/* insertion sort */ +GT_STATUS gtSort(int list[], GT_CMP_FUNC cmpFunc, void* buf, GT_U32 len) +{ + GT_U32 index; + int curValue, preValue; + + if (len <= 1) + return GT_FAIL; + + preValue = list[0]; + + for (index = 1; index < len; ++index) + { + curValue = list[index]; + if ((*cmpFunc)(buf, preValue, curValue) > 0) + { + /* out of order: list[index-1] > list[index] */ + GT_U32 index2; + list[index] = preValue; /* move up the larger item first */ + + /* find the insertion point for the smaller item */ + for (index2 = index - 1; index2 > 0;) + { + int temp_val = list[index2 - 1]; + if ((*cmpFunc)(buf, temp_val, curValue) > 0) + { + list[index2--] = temp_val; + /* still out of order, move up 1 slot to make room */ + } + else + break; + } + list[index2] = curValue; /* insert the smaller item right here */ + } + else + { + /* in order, advance to next element */ + preValue = curValue; + } + } + return GT_OK; +} + + +GT_U16 hashFunction(char eaddr[]) +{ + GT_U16 crc_reg; + GT_U8 crc_in; + int i,j; + + crc_reg=0; + + for(i=0; i<6; i++) + { + crc_in = eaddr[5-i]; + for(j=0; j<8; j++) + { + crc_reg = ((((crc_in & 1) ^ ((crc_reg>>15) & 1)) ^ + ((crc_reg>>14) & 1)) << 15) | /* bit 15 */ + ((crc_reg & 0x3FFC) << 1) | /* bit 14:3 */ + ((((crc_in & 1) ^ ((crc_reg>>15) & 1)) ^ + ((crc_reg>>1) & 1)) << 2) | /* bit 2 */ + ((crc_reg & 1) << 1) | /* bit 1 */ + ((crc_in & 1) ^ ((crc_reg>>15) & 1)); /* bit 0 */ + + crc_in >>= 1; + } + } + + return crc_reg; +} + + +GT_U16 hashToBucket(GT_U16 hash, GT_U16 mode) +{ + GT_U16 bucket; + + switch (mode) + { + case 0: + bucket = + (((hash >> 7) & 1) << 10) | /* bit 10 */ + (((hash >> 11) & 1) << 9) | /* bit 9 */ + (((hash >> 3 ) & 1) << 8) | /* bit 8 */ + (((hash >> 14) & 1) << 7) | /* bit 7 */ + (((hash >> 12) & 1) << 6) | /* bit 6 */ + (((hash >> 10) & 1) << 5) | /* bit 5 */ + (((hash >> 8 ) & 1) << 4) | /* bit 4 */ + (((hash >> 6 ) & 1) << 3) | /* bit 3 */ + (((hash >> 4 ) & 1) << 2) | /* bit 2 */ + (((hash >> 2 ) & 1) << 1) | /* bit 1 */ + (( hash >> 0 ) & 1); /* bit 0 */ + break; + case 1: + bucket = + (((hash >> 2) & 1) << 10) | /* bit 10 */ + (((hash >> 12) & 1) << 9) | /* bit 9 */ + (((hash >> 0 ) & 1) << 8) | /* bit 8 */ + (((hash >> 10) & 1) << 7) | /* bit 7 */ + (((hash >> 8 ) & 1) << 6) | /* bit 6 */ + (((hash >> 7 ) & 1) << 5) | /* bit 5 */ + (((hash >> 6 ) & 1) << 4) | /* bit 4 */ + (((hash >> 5 ) & 1) << 3) | /* bit 3 */ + (((hash >> 4 ) & 1) << 2) | /* bit 2 */ + (((hash >> 3 ) & 1) << 1) | /* bit 1 */ + (( hash >> 1 ) & 1); /* bit 0 */ + break; + case 2: + bucket = + (((hash >> 13) & 1) << 10)| /* bit 10 */ + (((hash >> 15) & 1) << 9) | /* bit 9 */ + (((hash >> 3 ) & 1) << 8) | /* bit 8 */ + (((hash >> 14) & 1) << 7) | /* bit 7 */ + (((hash >> 12) & 1) << 6) | /* bit 6 */ + (((hash >> 11) & 1) << 5) | /* bit 5 */ + (((hash >> 10) & 1) << 4) | /* bit 4 */ + (((hash >> 9 ) & 1) << 3) | /* bit 3 */ + (((hash >> 8 ) & 1) << 2) | /* bit 2 */ + (((hash >> 7 ) & 1) << 1) | /* bit 1 */ + (( hash >> 5 ) & 1); /* bit 0 */ + break; + case 3: + bucket = + (((hash >> 10) & 1) << 10)| /* bit 10 */ + (((hash >> 8 ) & 1) << 9) | /* bit 9 */ + (((hash >> 7 ) & 1) << 8) | /* bit 8 */ + (((hash >> 13) & 1) << 7) | /* bit 7 */ + (((hash >> 12) & 1) << 6) | /* bit 6 */ + (((hash >> 10) & 1) << 5) | /* bit 5 */ + (((hash >> 9 ) & 1) << 4) | /* bit 4 */ + (((hash >> 6 ) & 1) << 3) | /* bit 3 */ + (((hash >> 5 ) & 1) << 2) | /* bit 2 */ + (((hash >> 3 ) & 1) << 1) | /* bit 1 */ + (( hash >> 2 ) & 1); /* bit 0 */ + break; + default: + /* treat as case 0 */ + bucket = + (((hash >> 7) & 1) << 10) | /* bit 10 */ + (((hash >> 11) & 1) << 9) | /* bit 9 */ + (((hash >> 3 ) & 1) << 8) | /* bit 8 */ + (((hash >> 14) & 1) << 7) | /* bit 7 */ + (((hash >> 12) & 1) << 6) | /* bit 6 */ + (((hash >> 10) & 1) << 5) | /* bit 5 */ + (((hash >> 8 ) & 1) << 4) | /* bit 4 */ + (((hash >> 6 ) & 1) << 3) | /* bit 3 */ + (((hash >> 4 ) & 1) << 2) | /* bit 2 */ + (((hash >> 2 ) & 1) << 1) | /* bit 1 */ + (( hash >> 0 ) & 1); /* bit 0 */ + break; + } + return bucket; +} + +GT_U16 dbNumMap(GT_U32 bucket, GT_U32 dbNum) +{ + return (GT_U16)(bucket + dbNum); +} + +GT_U16 runQDHash(GT_U8* eaddr, GT_U16 dbNum, int bSize, GT_U16* pHash, GT_U16* preBucket, GT_U16* posBucket) +{ + GT_U16 hash, bucket; + + hash = hashFunction(eaddr); + if (pHash) + *pHash = hash; + bucket = hashToBucket(hash,hashMode); + bucket &= (bSize-1); + if (preBucket) + *preBucket = bucket; + bucket = dbNumMap(bucket,dbNum); + if (posBucket) + *posBucket = bucket; + bucket &= (bSize-1); + + return bucket; +} + +GT_U16 hashTest(unsigned int maxMacs, int maxDbNum, int bSize) +{ + char eaddr[6] = {0,0,0,0,0,0}; + char buckets[MAX_BUCKET_SIZE]; + GT_U32 i, dbNum; + GT_U16 hash, bucket, tmpBucket; + + gtMemSet(buckets,0,MAX_BUCKET_SIZE); + + for(dbNum=0; dbNum<(GT_U32)maxDbNum; dbNum++) + { + MSG_PRINT(("DBNum %i:\n", dbNum)); + for(i=1; i> 24) & 0xff); + eaddr[3] = (char)((i >> 16) & 0xff); + eaddr[4] = (char)((i >> 8) & 0xff); + eaddr[5] = (char)(i & 0xff); + tmpBucket=runQDHash((GT_U8*)eaddr, (GT_U16)dbNum, bSize, &hash, &bucket, NULL); + buckets[tmpBucket]++; + MSG_PRINT(("EADDR : %02x-%02x-%02x-%02x, ", eaddr[2],eaddr[3],eaddr[4],eaddr[5])); + MSG_PRINT(("Hash : %03x, ", hash)); + MSG_PRINT(("bucket : %03x, ", bucket)); + MSG_PRINT(("bins : %02x\n", buckets[tmpBucket]-1)); + } + + } + + return 0; +} + +GT_U16 hashFindEntriesInBucket(unsigned int maxMacs, int bucketNum, int bSize) +{ + char eaddr[6] = {0,0,0,0,0,0}; + char buckets[MAX_BUCKET_SIZE]; + GT_U32 i, dbNum; + GT_U16 hash, bucket, tmpBucket; + + gtMemSet(buckets,0,MAX_BUCKET_SIZE); + + dbNum = 0; + MSG_PRINT(("DBNum %i:\n", dbNum)); + for(i=1; i> 24) & 0xff); + eaddr[3] = (char)((i >> 16) & 0xff); + eaddr[4] = (char)((i >> 8) & 0xff); + eaddr[5] = (char)(i & 0xff); + tmpBucket=runQDHash((GT_U8*)eaddr, (GT_U16)dbNum, bSize, &hash, &bucket, NULL); + buckets[tmpBucket]++; + if (tmpBucket != bucketNum) + continue; + MSG_PRINT(("EADDR : %02x-%02x-%02x-%02x, ", eaddr[2],eaddr[3],eaddr[4],eaddr[5])); + MSG_PRINT(("Hash : %03x, ", hash)); + MSG_PRINT(("bucket : %03x, ", bucket)); + MSG_PRINT(("bins : %02x\n", buckets[tmpBucket]-1)); + } + + return 0; +} + +void displayHash(char* eaddr, GT_U16 dbNum, GT_U32 bSize) +{ + GT_U16 hash, posBucket, preBucket; + + posBucket=runQDHash(eaddr, dbNum, bSize, &hash, &preBucket, NULL); + MSG_PRINT(("EADDR : %02x-%02x-%02x-%02x, ", eaddr[2],eaddr[3],eaddr[4],eaddr[5])); + MSG_PRINT(("Hash : %03x, ", hash)); + MSG_PRINT(("bucket : %03x, ", preBucket)); + MSG_PRINT(("bucket(db) : %03x, ", posBucket)); + MSG_PRINT(("bSize : %03x\n", bSize)); +} + +GT_U16 hashWrap(int bSize, int entry) +{ + char eaddr[6] = {0,0,0,0,0,0}; + char buckets[MAX_BUCKET_SIZE]; + GT_U32 i, maxMacs; + GT_U16 hash, bucket, tmpBucket, preBucket; + int wrapping = 0; + maxMacs =0xFFFFFFFF; + gtMemSet(buckets,0,MAX_BUCKET_SIZE); + + MSG_PRINT(("Wrapped Entry :\n")); + for(i=1; i> 24) & 0xff); + eaddr[3] = (char)((i >> 16) & 0xff); + eaddr[4] = (char)((i >> 8) & 0xff); + eaddr[5] = (char)(i & 0xff); + tmpBucket = runQDHash(eaddr, 15, bSize, &hash, &preBucket, &bucket); + buckets[tmpBucket]++; + if(bucket != tmpBucket) + { + wrapping++; + MSG_PRINT(("EADDR : %02x-%02x-%02x-%02x, ", eaddr[2],eaddr[3],eaddr[4],eaddr[5])); + MSG_PRINT(("Hash : %03x, ", hash)); + MSG_PRINT(("bucket : %03x, ", preBucket)); + MSG_PRINT(("bucket(db) : %03x, ", tmpBucket)); + MSG_PRINT(("bins : %02x\n", buckets[tmpBucket]-1)); + } + if (wrapping >= entry) + break; + } + + return wrapping; +} + +/* + This routine will create ATU Entry List. + Input + entrySize - entry size for each dbNum + dbNumSize - number of DBNums + sameMacs - how many same MAC addresses are in the ATU database. + Each of the same addresses are beloging to different DBNum. +*/ +GT_U16 createATUList(GT_QD_DEV *dev,TEST_ATU_ENTRY entry[], GT_U16 entrySize, GT_U16 dbNumSize, GT_U16 sameMacs, GT_U16 bSize) +{ + GT_U16 i; + char* buckets; + GT_U16 dynamicMacs = 0; + GT_U16 bucket,dbNum,binSize; + GT_BOOL exPrio, fqPri; + + if(dbNumSize == 0) + return entrySize+1; + if(entrySize < sameMacs) + return entrySize+1; + + buckets = (char*)malloc(MAX_BUCKET_SIZE); + if(buckets == NULL) + { + printf("No more available memories\n"); + return -1; + } + gtMemSet(buckets,0,MAX_BUCKET_SIZE); + +#ifndef TEST_DEBUG + srand((unsigned)time(NULL)); +#else + srand((unsigned)1); +#endif + + binSize = 4; + switch(dev->deviceId) + { + case GT_88E6131: + case GT_88E6108: + hashMode = 1; + exPrio = GT_FALSE; + fqPri = GT_FALSE; + break; + case GT_88E6031: + case GT_88E6061: + hashMode = 1; + exPrio = GT_TRUE; + fqPri = GT_FALSE; + break; + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + hashMode = 1; + exPrio = GT_TRUE; + fqPri = GT_TRUE; + break; + default: + exPrio = GT_FALSE; + fqPri = GT_FALSE; + hashMode = 0; + break; + } + + for(i=0; i= binSize) + { + /* if bucket is full, find another entry. */ + break; + } + else + { + continue; + } + } + + if (dbNum == dbNumSize) + { + /* we found a entry which meets our requirement. */ + entry[0].atuEntry[i].portVec = (GT_U32)(rand() & 0x3FF) % (1<numOfPorts); + if(entry[0].atuEntry[i].portVec == 0) + entry[0].atuEntry[i].portVec = 0x3; + if(!exPrio) + { + entry[0].atuEntry[i].prio = (GT_U8)(rand() & 0x3); + } + else + { + entry[0].atuEntry[i].exPrio.macQPri = (GT_U8)(rand() & 0x3); + if(fqPri) + { + entry[0].atuEntry[i].exPrio.macFPri = (GT_U8)(rand() & 0x7); + entry[0].atuEntry[i].exPrio.useMacFPri = GT_TRUE; + } + } + + if(entry[0].atuEntry[i].macAddr.arEther[0] & 0x1) + { + entry[0].atuEntry[i].entryState.mcEntryState = GT_MC_STATIC; + } + else + { + entry[0].atuEntry[i].entryState.ucEntryState = GT_UC_DYNAMIC; + dynamicMacs+=dbNumSize; + } + + buckets[tmpBucket[0]]++; + for (dbNum=1; dbNum= binSize) + continue; + else + { +#ifdef TEST_DEBUG + MSG_PRINT(("MAC : %02x-%02x-%02x-%02x-%02x-%02x, ", + entry[dbNum].atuEntry[i].macAddr.arEther[0], + entry[dbNum].atuEntry[i].macAddr.arEther[1], + entry[dbNum].atuEntry[i].macAddr.arEther[2], + entry[dbNum].atuEntry[i].macAddr.arEther[3], + entry[dbNum].atuEntry[i].macAddr.arEther[4], + entry[dbNum].atuEntry[i].macAddr.arEther[5] )); + MSG_PRINT(("dbNum : %04x, ", dbNum)); + MSG_PRINT(("bucket : %03x, bins : %02x\n", bucket,buckets[bucket])); +#endif + buckets[bucket]++; + break; + } + + } while (1); + + entry[dbNum].atuEntry[i].portVec = (GT_U32)(rand() & 0x3FF) % (1<numOfPorts); + if(entry[dbNum].atuEntry[i].portVec == 0) + entry[dbNum].atuEntry[i].portVec = 0x3; + if(!exPrio) + { + entry[dbNum].atuEntry[i].prio = (GT_U8)(rand() & 0x3); + } + else + { + entry[dbNum].atuEntry[i].exPrio.macQPri = (GT_U8)(rand() & 0x3); + if(fqPri) + { + entry[dbNum].atuEntry[i].exPrio.macFPri = (GT_U8)(rand() & 0x7); + entry[dbNum].atuEntry[i].exPrio.useMacFPri = GT_TRUE; + } + } + entry[dbNum].atuEntry[i].DBNum = (GT_U8)dbNum; + + if(entry[dbNum].atuEntry[i].macAddr.arEther[0] & 0x1) + { + entry[dbNum].atuEntry[i].entryState.mcEntryState = GT_MC_STATIC; + } + else + { + entry[dbNum].atuEntry[i].entryState.ucEntryState = GT_UC_DYNAMIC; + dynamicMacs++; + } + } + } + } + + free(buckets); + + return dynamicMacs; +} + + +GT_STATUS testFixedAtu(GT_QD_DEV *dev,GT_U8 dbNum,GT_U8 atuSize) +{ + GT_STATUS status; + GT_ATU_ENTRY macEntry[16]; + int i; + GT_U32 u32Data1; + + /* Set ATU Size will cause ATU reset and SW reset, so call before any other setup. */ + MSG_PRINT(("Setting ATU Size\n")); + if((status = gfdbSetAtuSize(dev,atuSize)) != GT_OK) + { + MSG_PRINT(("gfdbSetAtuSize returned fail.\n")); + return status; + } + + /* Disable Aging */ + MSG_PRINT(("Disable Aging Timeout... \n")); + if((status = gfdbSetAgingTimeout(dev,0)) != GT_OK) + { + MSG_PRINT(("gfdbSetAgingTimeout returned fail.\n")); + return status; + } + + /* Disable Learning */ + MSG_PRINT(("Disable Learning... \n")); + if((status = gfdbLearnEnable(dev,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gfdbSetAtuSize returned fail.\n")); + return status; + } + + /* Flush all addresses from the ATU table. */ + MSG_PRINT(("Flush out all the entries in the ATU Table ... \n")); + if((status = gfdbFlush(dev,GT_FLUSH_ALL)) != GT_OK) + { + MSG_PRINT(("gfdbFlush returned fail.\n")); + return status; + } + + /* Get Atu Dynamic Count, which should be 0, since we flush them all. */ + if((status = gfdbGetAtuDynamicCount(dev,&u32Data1)) != GT_OK) + { + MSG_PRINT(("gfdbGetAtuDynamicCount returned fail.\n")); + return status; + } + + MSG_PRINT(("Atu Dynamic Count : %d.\n", u32Data1)); + + /* Now ATU table is clean. Play with our own MAC entries */ + MSG_PRINT(("Setup Testing Table... \n")); + + gtMemSet(macEntry,0,sizeof(macEntry)); + + /* bucket 0xee */ + *(GT_U16*)&macEntry[0].macAddr.arEther[4] = 0xd1b; + macEntry[0].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[0].DBNum = dbNum; + + *(GT_U16*)&macEntry[1].macAddr.arEther[4] = 0xd1e; + macEntry[1].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[1].DBNum = dbNum; + + *(GT_U16*)&macEntry[2].macAddr.arEther[4] = 0xddb; + macEntry[2].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[2].DBNum = dbNum; + + *(GT_U16*)&macEntry[3].macAddr.arEther[4] = 0xdde; + macEntry[3].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[3].DBNum = dbNum; + + /* bucket 0xef */ + *(GT_U16*)&macEntry[4].macAddr.arEther[4] = 0xd1a; + macEntry[4].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[4].DBNum = dbNum; + + *(GT_U16*)&macEntry[5].macAddr.arEther[4] = 0xd1f; + macEntry[5].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[5].DBNum = dbNum; + + *(GT_U16*)&macEntry[6].macAddr.arEther[4] = 0xdda; + macEntry[6].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[6].DBNum = dbNum; + + *(GT_U16*)&macEntry[7].macAddr.arEther[4] = 0xddf; + macEntry[7].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[7].DBNum = dbNum; + + /* bucket 0xf0 */ + *(GT_U16*)&macEntry[8].macAddr.arEther[4] = 0x440; + macEntry[8].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[8].DBNum = dbNum; + + *(GT_U16*)&macEntry[9].macAddr.arEther[4] = 0x485; + macEntry[9].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[9].DBNum = dbNum; + + *(GT_U16*)&macEntry[10].macAddr.arEther[4] = 0x1123; + macEntry[10].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[10].DBNum = dbNum; + + *(GT_U16*)&macEntry[11].macAddr.arEther[4] = 0x1223; + macEntry[11].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[11].DBNum = dbNum; + + /* bucket 0xf0 */ + *(GT_U16*)&macEntry[12].macAddr.arEther[4] = 0x441; + macEntry[12].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[12].DBNum = dbNum; + + *(GT_U16*)&macEntry[13].macAddr.arEther[4] = 0x484; + macEntry[13].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[13].DBNum = dbNum; + + *(GT_U16*)&macEntry[14].macAddr.arEther[4] = 0xb41; + macEntry[14].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[14].DBNum = dbNum; + + *(GT_U16*)&macEntry[15].macAddr.arEther[4] = 0x444; + macEntry[15].entryState.ucEntryState = GT_UC_DYNAMIC; + macEntry[15].DBNum = dbNum; + + + for(i=0; i<16; i++) + { + displayHash(macEntry[i].macAddr.arEther,dbNum,64< +/******************************************************************************** +* testApi.c +* +* DESCRIPTION: +* API test functions +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +void displayVCTResult +( + GT_TEST_STATUS *cableStatus, + GT_CABLE_LEN *cableLen +) +{ + switch(*cableStatus) + { + case GT_TEST_FAIL: + MSG_PRINT(("Cable Test Failed\n")); + break; + case GT_NORMAL_CABLE: + MSG_PRINT(("Cable Test Passed. No problem found.\n")); + switch(cableLen->normCableLen) + { + case GT_LESS_THAN_50M: + MSG_PRINT(("Cable Length is less than 50M.\n")); + break; + case GT_50M_80M: + MSG_PRINT(("Cable Length is between 50M and 80M.\n")); + break; + case GT_80M_110M: + MSG_PRINT(("Cable Length is between 80M and 110M.\n")); + break; + case GT_110M_140M: + MSG_PRINT(("Cable Length is between 110M and 140M.\n")); + break; + case GT_MORE_THAN_140: + MSG_PRINT(("Cable Length is over 140M.\n")); + break; + default: + MSG_PRINT(("Cable Length is unknown.\n")); + break; + } + break; + case GT_IMPEDANCE_MISMATCH: + MSG_PRINT(("Cable Test Passed with Impedance Mismatch.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + case GT_OPEN_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is open.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + case GT_SHORT_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is short.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + default: + MSG_PRINT(("Unknown Test Result.\n")); + break; + } +} + + +GT_STATUS vctTest(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_CABLE_STATUS cableStatus; + int i; + + if (dev == 0) + { + MSG_PRINT(("QD driver is not initialized\n")); + return GT_FAIL; +#if 0 + dev = &qdDev; + memset(dev, 0, sizeof(GT_QD_DEV)); + dev->fgtReadMii = gtBspReadMii; + dev->fgtWriteMii = gtBspWriteMii; +#endif + } + + /* + * Start and get Cable Test Result + */ + if((status = gvctGetCableDiag(dev,port, &cableStatus)) != GT_OK) + { + MSG_PRINT(("gvctGetCableDiag return Failed\n")); + return status; + } + + MSG_PRINT(("Cable Test Result for Port %i\n",port)); + + if(cableStatus.phyType == PHY_100M) + { + MSG_PRINT(("RX PAIR :\n")); + displayVCTResult(&cableStatus.cableStatus[MDI_RX_PAIR], + &cableStatus.cableLen[MDI_RX_PAIR]); + MSG_PRINT(("TX PAIR :\n")); + displayVCTResult(&cableStatus.cableStatus[MDI_TX_PAIR], + &cableStatus.cableLen[MDI_TX_PAIR]); + } + else /* phyType must be PHY_1000M */ + { + for(i=0; ifgtReadMii = gtBspReadMii; + dev->fgtWriteMii = gtBspWriteMii; +#endif + } + + /* + * Start getting Extended Information. + */ + if((status = gvctGet1000BTExtendedStatus(dev,port, &extendedStatus)) != GT_OK) + { + MSG_PRINT(("gvctGetCableDiag return Failed\n")); + return status; + } + + if (!extendedStatus.isValid) + { + MSG_PRINT(("Not able to get Extended Status.\n")); + return status; + + } + + /* Pair Polarity */ + MSG_PRINT(("Pair Polarity:\n")); + for(i=0; i + +/******************************************************************************** +* gtDrvConfig.h +* +* DESCRIPTION: +* Includes driver level configuration and initialization function. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 4 $ +* +*******************************************************************************/ + +#ifndef __gtDrvConfigh +#define __gtDrvConfigh + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* driverConfig +* +* DESCRIPTION: +* This function initializes the driver level of the quarterDeck software. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success, or +* GT_OUT_OF_CPU_MEM - if failed to allocate CPU memory, +* GT_FAIL - otherwise. +* +* COMMENTS: +* 1. This function should perform the following: +* - Initialize the global switch configuration structure. +* - Initialize Mii Interface +* - Set the CPU port into trailer mode (Ingress and Egress). +* +*******************************************************************************/ +GT_STATUS driverConfig(IN GT_QD_DEV *dev); + +/******************************************************************************* +* driverEnable +* +* DESCRIPTION: +* This function enables the switch for full operation, after the driver +* Config function was called. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverEnable(IN GT_QD_DEV *dev); + +/******************************************************************************* +* driverIsPhyAttached +* +* DESCRIPTION: +* This function reads and returns Phy ID (register 3) of Marvell Phy. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* phyId - if Marvell Phy exists +* 0 - otherwise +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U32 driverIsPhyAttached +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort +); + +/******************************************************************************* +* driverGetPhyID +* +* DESCRIPTION: +* This function reads and returns Phy ID (register 3) of Marvell Phy. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* phyId - if Marvell Phy exists +* GT_INVALID_PORT - otherwise +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U32 driverGetPhyID +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort +); + +/******************************************************************************* +* driverGetSerdesPort +* +* DESCRIPTION: +* This function converts port to Serdes port +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* hwPort - port number where the Phy is connected +* +* RETURNS: +* GT_OK - if success +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverGetSerdesPort(GT_QD_DEV *dev, GT_U8* hwPort); + + +/******************************************************************************* +* driverPagedAccessStart +* +* DESCRIPTION: +* This function stores page register and Auto Reg Selection mode if needed. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* pageType - type of the page registers +* +* OUTPUTS: +* autoOn - GT_TRUE if Auto Reg Selection enabled, GT_FALSE otherwise. +* pageReg - Page Register Data +* +* RETURNS: +* GT_OK - if success +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverPagedAccessStart +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_U8 pageType, + OUT GT_BOOL *autoOn, + OUT GT_U16 *pageReg +); + + +/******************************************************************************* +* driverPagedAccessStop +* +* DESCRIPTION: +* This function restores page register and Auto Reg Selection mode if needed. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* pageType - type of the page registers +* autoOn - GT_TRUE if Auto Reg Selection enabled, GT_FALSE otherwise. +* pageReg - Page Register Data +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - if success +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverPagedAccessStop +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_U8 pageType, + IN GT_BOOL autoOn, + IN GT_U16 pageReg +); + + +/******************************************************************************* +* driverFindPhyInformation +* +* DESCRIPTION: +* This function gets information of Phy connected to the given port. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* phyId - Phy ID +* +* RETURNS: +* GT_OK - if found Marvell Phy, +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverFindPhyInformation +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + OUT GT_PHY_INFO *phyInfo +); + + +#ifdef __cplusplus +} +#endif + +#endif /* __gtDrvConfigh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvEvents.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvEvents.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvEvents.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvEvents.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,87 @@ +#include + +/******************************************************************************** +* gtDrvEvents.h +* +* DESCRIPTION: +* This file includes function declarations for QuarterDeck interrupts +* configuration and handling. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 1 $ +* +*******************************************************************************/ + +#ifndef __gtDrvEventsh +#define __gtDrvEventsh + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* drvEventInit +* +* DESCRIPTION: +* This function initializes the driver's interrupt handling mechanism. +* +* INPUTS: +* intVecNum - The interrupt vector the switch is connected to. +* isrFunc - A pointer to the Interrupt Service Routine to be +* connected to the given interrupt vector. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success, +* GT_FAIL - otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS drvEventsInit +( + IN GT_QD_DEV *dev, + IN GT_U32 intVecNum, + IN GT_VOIDFUNCPTR isrFunc +); + + + +/******************************************************************************* +* eventQdSr +* +* DESCRIPTION: +* QuarterDeck interrupt service routine. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* None. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_BOOL eventQdSr +( + IN GT_QD_DEV *dev, + OUT GT_U16* intCause +); + +#ifdef __cplusplus +} +#endif + +#endif /* __gtDrvEventsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvSwRegs.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvSwRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvSwRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtDrvSwRegs.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,235 @@ +#include + +/******************************************************************************** + * * gtDrvSwRegs.h + * * + * * DESCRIPTION: + * * definitions of the register map of QuarterDeck Device + * * + * * DEPENDENCIES: + * * + * * FILE REVISION NUMBER: + * * + * *******************************************************************************/ +#ifndef __gtDrvSwRegsh +#define __gtDrvSwRegsh + +/* QuarterDeck Per Port Registers */ +#define QD_REG_PORT_STATUS 0x0 +#define QD_REG_PCS_CONTROL 0x1 /* for Sapphire family */ +#define QD_REG_LIMIT_PAUSE_CONTROL 0x2 /* Jamming control register */ +#define QD_REG_SWITCH_ID 0x3 +#define QD_REG_PORT_CONTROL 0x4 +#define QD_REG_PORT_CONTROL1 0x5 +#define QD_REG_PORT_VLAN_MAP 0x6 +#define QD_REG_PVID 0x7 +#define QD_REG_PORT_CONTROL2 0x8 /* for Sapphire family */ +#define QD_REG_INGRESS_RATE_CTRL 0x9 /* for Sapphire family */ +#define QD_REG_EGRESS_RATE_CTRL 0xA /* for Sapphire family */ +#define QD_REG_RATE_CTRL0 0x9 +#define QD_REG_RATE_CTRL 0xA +#define QD_REG_PAV 0xB +#define QD_REG_PORT_ATU_CONTROL 0xC +#define QD_REG_PRI_OVERRIDE 0xD +#define QD_REG_POLICY_CONTROL 0xE +#define QD_REG_PORT_ETH_TYPE 0xF +#define QD_REG_RX_COUNTER 0x10 +#define QD_REG_TX_COUNTER 0x11 +#define QD_REG_DROPPED_COUNTER 0x12 + +#define QD_REG_INDISCARD_LO_COUNTER 0x10 +#define QD_REG_INDISCARD_HI_COUNTER 0x11 +#define QD_REG_INFILTERED_COUNTER 0x12 +#define QD_REG_OUTFILTERED_COUNTER 0x13 + +#define QD_REG_LED_CONTROL 0x16 + +#define QD_REG_Q_COUNTER 0x1B +#define QD_REG_RATE_CONTROL 0x0A +#define QD_REG_PORT_ASSOCIATION 0x0B +#define QD_REG_IEEE_PRI_REMAP_3_0 0x18 /* for Sapphire family */ +#define QD_REG_IEEE_PRI_REMAP_7_4 0x19 /* for Sapphire family */ + +#define QD_REG_PROVIDER_TAG 0x1A /* for Schooner family */ + +/* QuarterDeck Global Registers */ +#define QD_REG_GLOBAL_STATUS 0x0 +#define QD_REG_MACADDR_01 0x1 +#define QD_REG_MACADDR_23 0x2 +#define QD_REG_MACADDR_45 0x3 +#define QD_REG_GLOBAL_CONTROL 0x4 +#define QD_REG_GLOBAL_CONTROL2 0x1C /* for Sapphire, Schooner family */ +#define QD_REG_CORETAG_TYPE 0x19 /* for Ruby family */ +#define QD_REG_IP_MAPPING_TABLE 0x19 /* for Amber family */ +#define QD_REG_MONITOR_CONTROL 0x1A /* for Ruby family */ +#define QD_REG_MANGEMENT_CONTROL 0x1A /* for Schooner family */ +#define QD_REG_TOTAL_FREE_COUNTER 0x1B /* for Schooner family */ + +/* QuarterDeck Global 2 Registers */ +#define QD_REG_PHYINT_SOURCE 0x0 +#define QD_REG_DEVINT_SOURCE 0x0 +#define QD_REG_DEVINT_MASK 0x1 +#define QD_REG_MGMT_ENABLE_2X 0x2 +#define QD_REG_MGMT_ENABLE 0x3 +#define QD_REG_FLOWCTRL_DELAY 0x4 +#define QD_REG_MANAGEMENT 0x5 +#define QD_REG_ROUTING_TBL 0x6 +#define QD_REG_TRUNK_MASK_TBL 0x7 +#define QD_REG_TRUNK_ROUTING 0x8 +#define QD_REG_INGRESS_RATE_COMMAND 0x9 +#define QD_REG_INGRESS_RATE_DATA 0xA +#define QD_REG_PVT_ADDR 0xB +#define QD_REG_PVT_DATA 0xC +#define QD_REG_SWITCH_MAC 0xD +#define QD_REG_ATU_STATS 0xE +#define QD_REG_PRIORITY_OVERRIDE 0xF +#define QD_REG_EEPROM_COMMAND 0x14 +#define QD_REG_EEPROM_DATA 0x15 +#define QD_REG_PTP_COMMAND 0x16 +#define QD_REG_PTP_DATA 0x17 +#define QD_REG_SMI_PHY_CMD 0x18 +#define QD_REG_SMI_PHY_DATA 0x19 +#define QD_REG_SCRATCH_MISC 0x1A +#define QD_REG_WD_CONTROL 0x1B +#define QD_REG_QOS_WEIGHT 0x1C +#define QD_REG_SDET_POLARITY 0x1D + + +/* Definition for STU,VTU,RMON,and ATU Registers */ +#define QD_REG_ATU_FID_REG 0x1 +#define QD_REG_VTU_FID_REG 0x2 +#define QD_REG_STU_SID_REG 0x3 +#define QD_REG_VTU_OPERATION 0x5 +#define QD_REG_VTU_VID_REG 0x6 +#define QD_REG_VTU_DATA1_REG 0x7 +#define QD_REG_VTU_DATA2_REG 0x8 +#define QD_REG_VTU_DATA3_REG 0x9 +#define QD_REG_STATS_OPERATION 0x1D +#define QD_REG_STATS_COUNTER3_2 0x1E +#define QD_REG_STATS_COUNTER1_0 0x1F + +#define QD_REG_ATU_CONTROL 0xA +#define QD_REG_ATU_OPERATION 0xB +#define QD_REG_ATU_DATA_REG 0xC +#define QD_REG_ATU_MAC_BASE 0xD +#define QD_REG_IP_PRI_BASE 0x10 +#define QD_REG_IEEE_PRI 0x18 + + +/* Definitions for MIB Counter */ +#define GT_STATS_NO_OP 0x0 +#define GT_STATS_FLUSH_ALL 0x1 +#define GT_STATS_FLUSH_PORT 0x2 +#define GT_STATS_READ_COUNTER 0x4 +#define GT_STATS_CAPTURE_PORT 0x5 + +#define QD_PHY_CONTROL_REG 0 +#define QD_PHY_AUTONEGO_AD_REG 4 +#define QD_PHY_NEXTPAGE_TX_REG 7 +#define QD_PHY_AUTONEGO_1000AD_REG 9 +#define QD_PHY_SPEC_CONTROL_REG 16 +#define QD_PHY_INT_ENABLE_REG 18 +#define QD_PHY_INT_STATUS_REG 19 +#define QD_PHY_INT_PORT_SUMMARY_REG 20 + +/* Definitions for VCT registers */ +#define QD_REG_MDI0_VCT_STATUS 16 +#define QD_REG_MDI1_VCT_STATUS 17 +#define QD_REG_MDI2_VCT_STATUS 18 +#define QD_REG_MDI3_VCT_STATUS 19 +#define QD_REG_ADV_VCT_CONTROL_5 23 +#define QD_REG_ADV_VCT_CONTROL_8 20 +#define QD_REG_PAIR_SKEW_STATUS 20 +#define QD_REG_PAIR_SWAP_STATUS 21 + + +/* Bit Definition for QD_PHY_CONTROL_REG */ +#define QD_PHY_RESET 0x8000 +#define QD_PHY_LOOPBACK 0x4000 +#define QD_PHY_SPEED 0x2000 +#define QD_PHY_AUTONEGO 0x1000 +#define QD_PHY_POWER 0x800 +#define QD_PHY_ISOLATE 0x400 +#define QD_PHY_RESTART_AUTONEGO 0x200 +#define QD_PHY_DUPLEX 0x100 +#define QD_PHY_SPEED_MSB 0x40 + +#define QD_PHY_POWER_BIT 11 +#define QD_PHY_RESTART_AUTONEGO_BIT 9 + +/* Bit Definition for QD_PHY_AUTONEGO_AD_REG */ +#define QD_PHY_NEXTPAGE 0x8000 +#define QD_PHY_REMOTEFAULT 0x4000 +#define QD_PHY_PAUSE 0x400 +#define QD_PHY_100_FULL 0x100 +#define QD_PHY_100_HALF 0x80 +#define QD_PHY_10_FULL 0x40 +#define QD_PHY_10_HALF 0x20 + +#define QD_PHY_MODE_AUTO_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF | QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_100_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF) +#define QD_PHY_MODE_10_AUTO (QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_AUTO_FULL (QD_PHY_100_FULL | QD_PHY_10_FULL) +#define QD_PHY_MODE_AUTO_HALF (QD_PHY_100_HALF | QD_PHY_10_HALF) + +#define QD_PHY_MODE_100_FULL QD_PHY_100_FULL +#define QD_PHY_MODE_100_HALF QD_PHY_100_HALF +#define QD_PHY_MODE_10_FULL QD_PHY_10_FULL +#define QD_PHY_MODE_10_HALF QD_PHY_10_HALF + +/* Gigabit Phy related definition */ +#define QD_GIGPHY_1000X_FULL_CAP 0x8 +#define QD_GIGPHY_1000X_HALF_CAP 0x4 +#define QD_GIGPHY_1000T_FULL_CAP 0x2 +#define QD_GIGPHY_1000T_HALF_CAP 0x1 + +#define QD_GIGPHY_1000X_CAP (QD_GIGPHY_1000X_FULL_CAP|QD_GIGPHY_1000X_HALF_CAP) +#define QD_GIGPHY_1000T_CAP (QD_GIGPHY_1000T_FULL_CAP|QD_GIGPHY_1000T_HALF_CAP) + +#define QD_GIGPHY_1000X_FULL 0x20 +#define QD_GIGPHY_1000X_HALF 0x40 + +#define QD_GIGPHY_1000T_FULL 0x200 +#define QD_GIGPHY_1000T_HALF 0x100 + +/* Bit definition for QD_PHY_INT_ENABLE_REG */ +#define QD_PHY_INT_SPEED_CHANGED 0x4000 +#define QD_PHY_INT_DUPLEX_CHANGED 0x2000 +#define QD_PHY_INT_PAGE_RECEIVED 0x1000 +#define QD_PHY_INT_AUTO_NEG_COMPLETED 0x800 +#define QD_PHY_INT_LINK_STATUS_CHANGED 0x400 +#define QD_PHY_INT_SYMBOL_ERROR 0x200 +#define QD_PHY_INT_FALSE_CARRIER 0x100 +#define QD_PHY_INT_FIFO_FLOW 0x80 +#define QD_PHY_INT_CROSSOVER_CHANGED 0x40 +#define QD_PHY_INT_POLARITY_CHANGED 0x2 +#define QD_PHY_INT_JABBER 0x1 + + +/* Bit definition for DEVICE Interrupt */ +#define QD_DEV_INT_WATCHDOG 0x8000 +#define QD_DEV_INT_JAMLIMIT 0x4000 +#define QD_DEV_INT_DUPLEX_MISMATCH 0x2000 + +/* Definition for Multi Address Mode */ +#define QD_REG_SMI_COMMAND 0x0 +#define QD_REG_SMI_DATA 0x1 + +/* Bit definition for QD_REG_SMI_COMMAND */ +#define QD_SMI_BUSY 0x8000 +#define QD_SMI_MODE 0x1000 +#define QD_SMI_MODE_BIT 12 +#define QD_SMI_OP_BIT 10 +#define QD_SMI_OP_SIZE 2 +#define QD_SMI_DEV_ADDR_BIT 5 +#define QD_SMI_DEV_ADDR_SIZE 5 +#define QD_SMI_REG_ADDR_BIT 0 +#define QD_SMI_REG_ADDR_SIZE 5 + +#define QD_SMI_CLAUSE45 0 +#define QD_SMI_CLAUSE22 1 + +#define QD_SMI_WRITE 0x01 +#define QD_SMI_READ 0x02 + +#endif /* __gtDrvSwRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtHwCntl.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtHwCntl.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtHwCntl.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/driver/gtHwCntl.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,891 @@ +#include + +/******************************************************************************** +* gtHwCntl.h +* +* DESCRIPTION: +* Functions declarations for Hw accessing quarterDeck phy, internal and +* global registers. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +* +*******************************************************************************/ + +#ifndef __gtHwCntlh +#define __gtHwCntlh + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* This macro is used to calculate the register's SMI */ +/* device address, according to the baseAddr */ +/* field in the Switch configuration struct. */ +#define CALC_SMI_DEV_ADDR(_dev, _portNum, _accessType) \ + portToSmiMapping(_dev, _portNum, _accessType) + +/* This macro calculates the mask for partial read / */ +/* write of register's data. */ +#define CALC_MASK(fieldOffset,fieldLen,mask) \ + if((fieldLen + fieldOffset) >= 16) \ + mask = (0 - (1 << fieldOffset)); \ + else \ + mask = (((1 << (fieldLen + fieldOffset))) - (1 << fieldOffset)) + +#define GT_GET_PAGE_ADDR(_regAddr) ((_regAddr<29)?22:29) + +/* Start address of phy related register. */ +#define PHY_REGS_START_ADDR 0x0 +#define PHY_REGS_START_ADDR_8PORT 0x0 + +/* Start address of ports related register. */ +#define PORT_REGS_START_ADDR 0x8 +#define PORT_REGS_START_ADDR_8PORT 0x10 + +/* Start address of global register. */ +#define GLOBAL_REGS_START_ADDR 0xF +#define GLOBAL_REGS_START_ADDR_8PORT 0x1B + +#define PHY_ACCESS 1 +#define PORT_ACCESS 2 +#define GLOBAL_REG_ACCESS 3 +#define GLOBAL2_REG_ACCESS 4 + +#define QD_SMI_ACCESS_LOOP 1000 +#define QD_SMI_TIMEOUT 2 + + +/****************************************************************************/ +/* Phy registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadPhyReg +* +* DESCRIPTION: +* This function reads a switch's port phy register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWritePhyReg +* +* DESCRIPTION: +* This function writes to a switch's port phy register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* hwGetPhyRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port phy register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwSetPhyRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port phy register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +); + +/******************************************************************************* +* hwPhyReset +* +* DESCRIPTION: +* This function performs softreset and waits until reset completion. +* +* INPUTS: +* portNum - Port number to write the register for. +* u16Data - data should be written into Phy control register. +* if this value is 0xFF, normal operation occcurs (read, +* update, and write back.) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS hwPhyReset +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U16 u16Data +); + + +/******************************************************************************* +* hwReadPagedPhyReg +* +* DESCRIPTION: +* This function reads a switch's port phy register in page mode. +* +* INPUTS: +* portNum - Port number to read the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* anyPage - register list(vector) that are common to all pages +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWritePagedPhyReg +* +* DESCRIPTION: +* This function writes to a switch's port phy register in page mode. +* +* INPUTS: +* portNum - Port number to write the register for. +* pageNum - Page number of the register to be written. +* regAddr - The register's address. +* anyPage - Register list(vector) that are common to all pages +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + IN GT_U16 data +); + +/******************************************************************************* +* hwGetPagedPhyRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port phy register +* in page mode. +* +* INPUTS: +* portNum - Port number to read the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* anyPage - Register list(vector) that are common to all pages +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPagedPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U32 anyPage, + OUT GT_U16 *data +); + +/******************************************************************************* +* hwSetPagedPhyRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port phy register +* in page mode +* +* INPUTS: +* portNum - Port number to write the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* anyPage - Register list(vector) that are common to all pages +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPagedPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U32 anyPage, + IN GT_U16 data +); + + +/****************************************************************************/ +/* Per port registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadPortReg +* +* DESCRIPTION: +* This function reads a switch's port register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadPortReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWritePortReg +* +* DESCRIPTION: +* This function writes to a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePortReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* hwGetPortRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPortRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwSetPortRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPortRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +); + +/******************************************************************************* +* hwSetPortRegBits +* +* DESCRIPTION: +* This function writes to specified bits in a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* mask - The bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. When Data is 0x1002 and mask is 0xF00F, 0001b is written to bit[31:24] +* and 0010b is written to bit[3:0] +* +*******************************************************************************/ +GT_STATUS hwSetPortRegBits +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 mask, + IN GT_U16 data +); + +/****************************************************************************/ +/* Global registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadGlobalReg +* +* DESCRIPTION: +* This function reads a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWriteGlobalReg +* +* DESCRIPTION: +* This function writes to a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* hwGetGlobalRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetGlobalRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwSetGlobalRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetGlobalRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +); + + +/****************************************************************************/ +/* Global 2 registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadGlobal2Reg +* +* DESCRIPTION: +* This function reads a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWriteGlobal2Reg +* +* DESCRIPTION: +* This function writes to a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* hwGetGlobal2RegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetGlobal2RegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwSetGlobal2RegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS hwSetGlobal2RegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +); + +/******************************************************************************* +* hwSetGlobal2RegBits +* +* DESCRIPTION: +* This function writes to specified bits in a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* mask - The bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. When Data is 0x1002 and mask is 0xF00F, 0001b is written to bit[31:24] +* and 0010b is written to bit[3:0] +* +*******************************************************************************/ +GT_STATUS hwSetGlobal2RegBits +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 mask, + IN GT_U16 data +); + +/******************************************************************************* +* hwReadMiiReg +* +* DESCRIPTION: +* This function reads a switch register. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadMiiReg +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* hwWriteMiiReg +* +* DESCRIPTION: +* This function writes a switch register. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteMiiReg +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + IN GT_U16 data +); + +#ifdef __cplusplus +} +#endif +#endif /* __gtHwCntlh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/gtVct.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/gtVct.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/gtVct.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/gtVct.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,181 @@ +/******************************************************************************* +* Copyright 2002, GALILEO TECHNOLOGY, LTD. +* +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. NO RIGHTS ARE GRANTED +* HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT OF MARVELL OR ANY THIRD +* PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE DISCRETION TO REQUEST THAT THIS +* CODE BE IMMEDIATELY RETURNED TO MARVELL. THIS CODE IS PROVIDED "AS IS". +* MARVELL MAKES NO WARRANTIES, EXPRESS, IMPLIED OR OTHERWISE, REGARDING ITS +* ACCURACY, COMPLETENESS OR PERFORMANCE. MARVELL COMPRISES MARVELL TECHNOLOGY +* GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, MARVELL INTERNATIONAL LTD. (MIL), +* MARVELL TECHNOLOGY, INC. (MTI), MARVELL SEMICONDUCTOR, INC. (MSI), MARVELL +* ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. (MJKK), GALILEO TECHNOLOGY LTD. (GTL) +* AND GALILEO TECHNOLOGY, INC. (GTI). +******************************************************************************** +* gtPhy.h +* +* DESCRIPTION: +* API definitions for Marvell Phy functionality. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 1 $ +*******************************************************************************/ + +#ifndef __gtPhyh +#define __gtPhyh + +#include "msApi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MARVELL_OUI_MSb 0x0141 +#define MARVELL_OUI_LSb 0x0C00 +#define OUI_LSb_MASK 0xFC00 +#define PHY_MODEL_MASK 0x03F0 +#define PHY_REV_MASK 0x000F + +#define DEV_E3082 0x8 << 4 +#define DEV_E104X 0x2 << 4 +#define DEV_E1111 0xC << 4 +#define DEV_E1112 0x9 << 4 +#define DEV_E114X 0xD << 4 +#define DEV_E1149 0xA << 4 +#define DEV_E1181 0xE << 4 +#define DEV_EC010 0x3 << 4 +#define DEV_G15LV 0xB << 4 /* 88E6165 internal copper phy, 88E1240 */ +#define DEV_S15LV 0x0 << 4 /* 88E6165 internal SERDES */ +#define DEV_G65G 0x27 << 4 /* 88E6375 internal copper phy, 88E1340 */ + +typedef struct _GT_PHY_INFO +{ + GT_U32 phyId; /* Marvell PHY ID (register 3) */ + GT_U32 anyPage; /* each bit represents if the corresponding register is any page */ + GT_U32 flag; /* see below for definition */ + GT_U8 vctType; /* VCT Register Type */ + GT_U8 exStatusType; /* EX Status Register Type */ + GT_U8 dteType; /* DTE Register Type */ + GT_U8 pktGenType; /* Pkt Generator Reg. Type */ + GT_U8 macIfLoopType; /* MAC IF Loopback Reg. Type */ + GT_U8 lineLoopType; /* Line Loopback Reg. Type */ + GT_U8 exLoopType; /* External Loopback Reg. Type */ + GT_U8 pageType; /* Page Restriction Type */ +} GT_PHY_INFO; + +/* GT_PHY_INFO flag definition */ +#define GT_PHY_VCT_CAPABLE 0x0001 +#define GT_PHY_DTE_CAPABLE 0x0002 +#define GT_PHY_EX_CABLE_STATUS 0x0004 +#define GT_PHY_ADV_VCT_CAPABLE 0x0008 +#define GT_PHY_PKT_GENERATOR 0x0010 +#define GT_PHY_MAC_IF_LOOP 0x0100 +#define GT_PHY_LINE_LOOP 0x0200 +#define GT_PHY_EXTERNAL_LOOP 0x0400 +#define GT_PHY_RESTRICTED_PAGE 0x0800 +#define GT_PHY_GIGABIT 0x8000 +#define GT_PHY_COPPER 0x4000 +#define GT_PHY_FIBER 0x2000 +#define GT_PHY_SERDES_CORE 0x1000 + +/* VCT Register Type */ +#define GT_PHY_VCT_TYPE1 1 /* 10/100 Fast Ethernet */ +#define GT_PHY_VCT_TYPE2 2 /* 1000M without page support */ +#define GT_PHY_VCT_TYPE3 3 /* 1000M without page but with work around */ +#define GT_PHY_VCT_TYPE4 4 /* 1000M with page support */ + +/* ADV VCT Register Type */ +#define GT_PHY_ADV_VCT_TYPE1 5 /* 88E1181 type device, not supported */ +#define GT_PHY_ADV_VCT_TYPE2 6 /* 88E6165 family devies */ + +/* Extended Status Type */ +#define GT_PHY_EX_STATUS_TYPE1 1 /* 88E1111, 88E1141, 88E1145 */ +#define GT_PHY_EX_STATUS_TYPE2 2 /* 88E1112 */ +#define GT_PHY_EX_STATUS_TYPE3 3 /* 88E1149 */ +#define GT_PHY_EX_STATUS_TYPE4 4 /* 88E1181 */ +#define GT_PHY_EX_STATUS_TYPE5 5 /* 88E1116 */ +#define GT_PHY_EX_STATUS_TYPE6 6 /* 88E6165 family devices */ + +/* DTE Register Type */ +#define GT_PHY_DTE_TYPE1 1 /* 10/100 Fast Ethernet with workaround */ +#define GT_PHY_DTE_TYPE2 2 /* 1000M without page support */ +#define GT_PHY_DTE_TYPE3 3 /* 1000M without page but with work around */ +#define GT_PHY_DTE_TYPE4 4 /* 1000M with page support */ +#define GT_PHY_DTE_TYPE5 5 /* 10/100 Fast Ethernet */ + +/* Pkt Generator Register Type */ +#define GT_PHY_PKTGEN_TYPE1 1 /* Uses Register 30 */ +#define GT_PHY_PKTGEN_TYPE2 2 /* Uses Register 16 */ +#define GT_PHY_PKTGEN_TYPE3 3 /* Uses Register 25 */ + +/* MAC Interface Loopback Register Type */ +#define GT_PHY_LOOPBACK_TYPE0 0 /* Don't do anything */ +#define GT_PHY_LOOPBACK_TYPE1 1 /* 0.14 only */ +#define GT_PHY_LOOPBACK_TYPE2 2 /* For DEV_G15LV like device */ +#define GT_PHY_LOOPBACK_TYPE3 3 /* For DEV_S15LV like device */ +#define GT_PHY_LOOPBACK_TYPE4 4 /* For DEV_E1111 like device */ + +/* Line Loopback Register Type */ +#define GT_PHY_LINE_LB_TYPE1 1 /* 0_2.14 */ +#define GT_PHY_LINE_LB_TYPE2 2 /* 21_2.14 */ +#define GT_PHY_LINE_LB_TYPE3 3 /* 20.14 */ +#define GT_PHY_LINE_LB_TYPE4 4 /* 16.12 */ + +/* External Loopback Register Type */ +#define GT_PHY_EX_LB_TYPE0 0 /* Don't do anything */ +#define GT_PHY_EX_LB_TYPE1 1 /* For DEV_E1111 like dev */ +#define GT_PHY_EX_LB_TYPE2 2 /* For DEV_E1149 like dev */ + +/* Restricted Page Access Type */ +#define GT_PHY_PAGE_WRITE_BACK 0 /* For every device */ +#define GT_PHY_PAGE_DIS_AUTO1 1 /* For 88E1111 type */ +#define GT_PHY_PAGE_DIS_AUTO2 2 /* For 88E1121 type */ +#define GT_PHY_NO_PAGE 3 /* No Pages */ + + +/* definition for formula to calculate actual distance */ +#ifdef FP_SUPPORT +#define FORMULA_PHY100M(_data) ((_data)*0.7861 - 18.862) +#define FORMULA_PHY1000M(_data) ((_data)*0.8018 - 28.751) +#else +#define FORMULA_PHY100M(_data) (((long)(_data)*7861 - 188620)/10000 + (((((long)(_data)*7861 - 188620)%10000) >= 5000)?1:0)) +#define FORMULA_PHY1000M(_data) (((long)(_data)*8018 - 287510)/10000 + (((((long)(_data)*8018 - 287510)%10000) >= 5000)?1:0)) +#endif + +#define GT_ADV_VCT_CALC(_data) \ + (((long)(_data)*8333 - 191667)/10000 + (((((long)(_data)*8333 - 191667)%10000) >= 5000)?1:0)) + +#define GT_ADV_VCT_CALC_SHORT(_data) \ + (((long)(_data)*7143 - 71429)/10000 + (((((long)(_data)*7143 - 71429)%10000) >= 5000)?1:0)) + +/* macro to check VCT Failure */ +#define IS_VCT_FAILED(_reg) \ + (((_reg) & 0xFF) == 0xFF) + +/* macro to find out if Amplitude is zero */ +#define IS_ZERO_AMPLITUDE(_reg) \ + (((_reg) & 0x7F00) == 0) + +/* macro to retrieve Amplitude */ +#define GET_AMPLITUDE(_reg) \ + (((_reg) & 0x7F00) >> 8) + +/* macro to find out if Amplitude is positive */ +#define IS_POSITIVE_AMPLITUDE(_reg) \ + (((_reg) & 0x8000) == 0x8000) + +typedef struct _VCT_REGISTER +{ + GT_U8 page; + GT_U8 regOffset; +} VCT_REGISTER; + + +#ifdef __cplusplus +} +#endif + +#endif /* __gtPhyh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/msApiInternal.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/msApiInternal.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/msApiInternal.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/msApi/msApiInternal.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,1429 @@ +#include + +/******************************************************************************** +* msApiPrototype.h +* +* DESCRIPTION: +* API Prototypes for QuarterDeck Device +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApiInternal_h +#define __msApiInternal_h + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef GT_USE_SIMPLE_PORT_MAPPING +#define GT_LPORT_2_PORT(_lport) (GT_U8)((_lport) & 0xff) +#define GT_PORT_2_LPORT(_port) (GT_LPORT)((_port) & 0xff) +#define GT_LPORTVEC_2_PORTVEC(_lvec) (GT_U32)((_lvec) & 0xffff) +#define GT_PORTVEC_2_LPORTVEC(_pvec) (GT_U32)((_pvec) & 0xffff) +#define GT_LPORT_2_PHY(_lport) (GT_U8)((_lport) & 0xff) +#else +#define GT_LPORT_2_PORT(_lport) lport2port(dev->validPortVec, _lport) +#define GT_PORT_2_LPORT(_port) port2lport(dev->validPortVec, _port) +#define GT_LPORTVEC_2_PORTVEC(_lvec) lportvec2portvec(dev->validPortVec, _lvec) +#define GT_PORTVEC_2_LPORTVEC(_pvec) portvec2lportvec(dev->validPortVec, _pvec) +#define GT_LPORT_2_PHY(_lport) lport2phy(dev,_lport) +#endif + +#define GT_IS_PORT_SET(_portVec, _port) \ + ((_portVec) & (0x1 << (_port))) + +#define GT_IS_IRLUNIT_VALID(_dev,_unit) \ + (((_dev)->deviceId == GT_88E6065)?(_unit < 12): \ + (((_dev)->deviceId == GT_88E6055)?(_unit < 12): \ + (((_dev)->deviceId == GT_88E6061)?(_unit < 6): \ + (((_dev)->deviceId == GT_88E6035)?(_unit < 6): \ + (_unit < 3))))) + + +/* The following macro converts a binary */ +/* value (of 1 bit) to a boolean one. */ +/* 0 --> GT_FALSE */ +/* 1 --> GT_TRUE */ +#define BIT_2_BOOL(binVal,boolVal) \ + (boolVal) = (((binVal) == 0) ? GT_FALSE : GT_TRUE) + +/* The following macro converts a boolean */ +/* value to a binary one (of 1 bit). */ +/* GT_FALSE --> 0 */ +/* GT_TRUE --> 1 */ +#define BOOL_2_BIT(boolVal,binVal) \ + (binVal) = (((boolVal) == GT_TRUE) ? 1 : 0) + +/* The following macro converts a binary */ +/* value (of 1 bit) to a boolean one. */ +/* 0 --> GT_TRUE */ +/* 1 --> GT_FALSE */ +#define BIT_2_BOOL_R(binVal,boolVal) \ + (boolVal) = (((binVal) == 0) ? GT_TRUE : GT_FALSE) + +/* The following macro converts a boolean */ +/* value to a binary one (of 1 bit). */ +/* GT_FALSE --> 1 */ +/* GT_TRUE --> 0 */ +#define BOOL_2_BIT_R(boolVal,binVal) \ + (binVal) = (((boolVal) == GT_TRUE) ? 0 : 1) + +/* Bit definition for devStorage */ +/* Ingress/Egress Rate type (grcSetPri0Rate, grcSetEgressRate) */ +#define GT_RATE_ENUM_NOT_USED 0x10000 +#define GT_RATE_ENUM_USED 0x00000 + +/* device name - devName */ +#define DEV_88E6051 0x0001 /* quarterdeck 6051 */ +#define DEV_88E6052 0x0002 /* quarterdeck 6052 */ +#define DEV_88E6021 0x0004 /* fullsail */ +#define DEV_88E6060 0x0008 /* Gondola */ +#define DEV_88E6063 0x0010 /* clippership 6063 */ +#define DEV_FF_EG 0x0020 /* FireFox-EG */ +#define DEV_FF_HG 0x0040 /* FireFox-HG */ +#define DEV_FH_VPN 0x0080 /* FireHawk-VPN */ +#define DEV_88E6083 0x0100 /* Octane 6083 */ +#define DEV_88E6181 0x0200 /* Sapphire 88E6181 */ +#define DEV_88E6183 0x0400 /* Sapphire 88E6153,88E6183 */ +#define DEV_88E6093 0x0800 /* 88E6093 */ +#define DEV_88E6092 0x1000 /* 88E6092 */ +#define DEV_88E6095 0x2000 /* 88E6095 */ +#define DEV_88E6182 0x4000 /* Jade 88E6152, 88E6182 */ +#define DEV_88E6185 0x8000 /* Jade 88E6155, 88E6185 */ +#define DEV_88E6108 0x10000 /* 88E6108 */ +#define DEV_88E6061 0x20000 /* 88E6031, 88E6061 */ +#define DEV_88E6065 0x40000 /* 88E6035, 88E6055, 88E6065 */ +#define DEV_88E6096 0x80000 /* 88E6096, 88E6046 */ +#define DEV_88E6097 0x100000 /* 88E6097, 88E6047 */ +#define DEV_88E6161 0x200000 /* 88E6161 */ +#define DEV_88E6165 0x400000 /* 88E6165 */ + +#define DEV_88E6351 0x800000 /* 88E6351 */ +#define DEV_88E6175 0x1000000 /* 88E6175 */ +#define DEV_88E6171 0x2000000 /* 88E6125 and 88E6171 */ +#define DEV_88E6371 0x4000000 /* 88E6321, 88E6350 */ + +#define DEV_88E6097_FAMILY ( DEV_88E6096 | DEV_88E6097 ) +#define DEV_88E6165_FAMILY ( DEV_88E6161 | DEV_88E6165 ) + +#define DEV_88E6351_AVB_FAMILY ( DEV_88E6351 | DEV_88E6371 ) +#define DEV_88E6351_NO_AVB_FAMILY ( DEV_88E6175 | DEV_88E6171 ) +#define DEV_88E6351_FAMILY ( DEV_88E6351_AVB_FAMILY | DEV_88E6351_NO_AVB_FAMILY) + +#define DEV_88E6095_FAMILY ( DEV_88E6092 | DEV_88E6095 ) +#define DEV_88E6185_FAMILY ( DEV_88E6182 | DEV_88E6185 | DEV_88E6108) + +#define DEV_88E6065_FAMILY ( DEV_88E6061 | DEV_88E6065 ) + +#define DEV_NEW_FEATURE_IN_REV (DEV_88E6095_FAMILY | DEV_88E6182 | DEV_88E6185) + +#define DEV_BURST_RATE ( DEV_88E6108 ) +#define DEV_DROP_BCAST ( DEV_88E6108 ) +#define DEV_ARP_PRI ( DEV_88E6108 ) +#define DEV_SNOOP_PRI ( DEV_88E6108 ) +#define DEV_SERDES_CORE ( DEV_88E6108 | DEV_88E6165_FAMILY ) + +#define DEV_AGE_INTERRUPT \ + ( DEV_88E6108 | DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_AGE_INT_GLOBAL2 \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_AGE_OUT_INT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_AGE_HOLD \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_DEVICE_INTERRUPT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_DEVICE_INT_TYPE1 \ + ( DEV_88E6097_FAMILY ) /* Serdes Int bit[10:8] */ +#define DEV_DEVICE_INT_TYPE2 \ + ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) /* Serdes Int bit[12:11], Phy Int bit[4:0] */ + +#define DEV_WATCHDOG_EVENT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_PORT_BASED_AGE_INT ( DEV_88E6065_FAMILY ) + +#define DEV_DEV_PHY_INTERRUPT \ + ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) /* device interrupt includes phy int */ + +#define DEV_AVB_INTERRUPT \ + ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_AUTO_REFRESH_LOCKED \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_PPU_PHY_ACCESS \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_PPU_PHY_ACCESS_RES ( DEV_88E6097_FAMILY ) + +#define DEV_PPU_READ_ONLY \ + ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_PPU_SERDES_ACCESS_RES ( DEV_88E6165_FAMILY ) + +#define DEV_NO_EGRESS_POLICY \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +/* DEV_8PORT_SWITCH is used to access the given device's Register Map */ +#define DEV_8PORT_SWITCH ( DEV_88E6083 | DEV_88E6181 | DEV_88E6183 | \ + DEV_88E6093 | DEV_88E6097_FAMILY | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_PORT_SECURITY ( DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_BROADCAST_INVALID ( DEV_88E6051 | DEV_88E6052 | DEV_FF_EG | DEV_FF_HG) + +/* Configurable ATU Size */ +#define DEV_ATU_256_2048 ( DEV_88E6021 | DEV_88E6060 | DEV_88E6065_FAMILY ) +#define DEV_ATU_562_2048 \ + ( DEV_88E6052 | DEV_88E6063 | DEV_FF_HG | \ + DEV_FH_VPN | DEV_88E6083 ) + +#define DEV_ATU_SIZE_FIXED DEV_GIGABIT_SWITCH + +#define DEV_ATU_1024 (DEV_88E6108) /* Not used */ +#define DEV_ATU_8192 (DEV_88E6095_FAMILY | DEV_88E6182 | DEV_88E6185) /* Not used */ + +#define DEV_ATU_LIMIT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_ATU_LIMIT_READ \ + ( DEV_88E6351_FAMILY ) + +#define DEV_DBNUM_FULL \ + ( DEV_88E6021 | DEV_88E6060 | DEV_88E6063 | \ + DEV_FH_VPN | DEV_88E6083 | \ + DEV_88E6183 | DEV_88E6093 | DEV_88E6061 ) + +#define DEV_DBNUM_64 ( DEV_88E6065 ) +#define DEV_DBNUM_256 ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) +#define DEV_DBNUM_4096 \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_STATIC_ADDR \ + ( DEV_88E6021 | DEV_FF_EG | DEV_FF_HG | \ + DEV_88E6052 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_TRAILER \ + ( DEV_88E6021 | DEV_FF_HG | DEV_88E6052 | \ + DEV_88E6063 | DEV_FH_VPN | DEV_88E6083 ) + +#define DEV_TRAILER_P5 ( DEV_FF_EG ) +#define DEV_TRAILER_P4P5 ( DEV_88E6060 ) + +#define DEV_HEADER \ + ( DEV_FF_HG | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_HEADER_P5 ( DEV_FF_EG ) +#define DEV_HEADER_P4P5 ( DEV_88E6060 ) + +/* DEV_QoS : Devices with multiple Queues for QoS Priority Support */ +#define DEV_QoS \ + ( DEV_88E6021 | DEV_FF_HG | DEV_88E6051 | \ + DEV_88E6052 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6181 | DEV_88E6183 | \ + DEV_88E6093 | DEV_88E6095_FAMILY | \ + DEV_88E6185_FAMILY | DEV_88E6065_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_QoS_FPRI_QPRI ( DEV_88E6065_FAMILY ) +#define DEV_QoS_WEIGHT ( DEV_88E6097 | DEV_88E6165 | DEV_88E6351_AVB_FAMILY | DEV_88E6175 ) + +#define DEV_TAGGING DEV_QoS + +#define DEV_EGRESS_DOUBLE_TAGGING \ + ( DEV_QoS & ~(DEV_88E6051 | DEV_88E6092 | DEV_88E6182 | \ + DEV_88E6061 ) ) + +#define DEV_INGRESS_DOUBLE_TAGGING \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095 | DEV_88E6185 | DEV_88E6108 ) + +#define DEV_PRIORITY_REMAPPING \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095 | DEV_88E6185 | DEV_88E6108 | \ + DEV_88E6065 | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + + +#define DEV_802_1Q ( DEV_88E6021 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095 | DEV_88E6092 | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_802_1S ( DEV_88E6095 | DEV_88E6185 | DEV_88E6108 | DEV_88E6065 ) +#define DEV_802_1S_STU ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_802_1W ( DEV_88E6183 | DEV_88E6093 | DEV_88E6095 | \ + DEV_88E6185 | DEV_88E6108 | DEV_88E6065 | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_ATU_15SEC_AGING ( DEV_GIGABIT_SWITCH | DEV_88E6065_FAMILY ) +#define DEV_ATU_RM_PORTS ( DEV_88E6093_FAMILY | DEV_88E6065 ) +#define DEV_ATU_EXT_PRI ( DEV_88E6065_FAMILY ) + +#define DEV_VTU_EXT_INFO ( DEV_88E6065_FAMILY ) + +#define DEV_RMON ( DEV_88E6021 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6092 | DEV_88E6095 | DEV_88E6185_FAMILY | \ + DEV_88E6065 | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_RMON_TYPE_1 ( DEV_88E6021 | DEV_88E6063 | DEV_FH_VPN | DEV_88E6083 ) +#define DEV_RMON_TYPE_2 ( DEV_88E6183 ) +#define DEV_RMON_TYPE_3 \ + ( DEV_88E6093 | DEV_88E6095 | DEV_88E6092 | \ + DEV_88E6185_FAMILY | DEV_88E6065 | \ + DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_RMON_REALTIME_SUPPORT \ + ( DEV_88E6065 | DEV_88E6065_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_RMON_PORT_BITS ( DEV_88E6065 | DEV_88E6065_FAMILY ) + +#define DEV_IGMP_SNOOPING \ + ( DEV_88E6021 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_PORT_MONITORING \ + ( DEV_88E6060 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_ENABLE_MONITORING \ + ( DEV_88E6060 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6065_FAMILY ) + +#define DEV_MC_RATE_PERCENT \ + ( DEV_88E6021 | DEV_88E6051 | DEV_88E6052 ) + +#define DEV_MC_RATE_KBPS \ + ( DEV_FF_HG | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 ) + +#define DEV_INGRESS_RATE_KBPS \ + ( DEV_FF_HG | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6181 | DEV_88E6183 | \ + DEV_88E6093 | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY) + +#define DEV_EGRESS_RATE_KBPS \ + ( DEV_FF_HG | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6181 | DEV_88E6183 | \ + DEV_88E6093 | DEV_88E6095 | DEV_88E6185 | \ + DEV_88E6108 | DEV_88E6065_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_ELIMIT_FRAME_BASED \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_PIRL_RESOURCE \ + ( DEV_88E6065_FAMILY ) + +#define DEV_PIRL2_RESOURCE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_RESTRICTED_PIRL_RESOURCE \ + ( DEV_88E6061 ) + +#define DEV_RESTRICTED_PIRL2_RESOURCE \ + ( DEV_88E6096 | DEV_88E6161 | DEV_88E6171 ) + + +#define DEV_NONE_RATE_LIMIT \ + ( DEV_88E6065 ) + +#define DEV_MII_DUPLEX_CONFIG \ + ( DEV_88E6021 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 ) + +#define DEV_QD_PLUS \ + ( DEV_88E6021 | DEV_FF_EG | DEV_FF_HG | \ + DEV_88E6060 | DEV_88E6063 | DEV_FH_VPN | \ + DEV_88E6083 | DEV_88E6181 | DEV_88E6183 | \ + DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_FASTETH_SWITCH \ + ( DEV_88E6051 | DEV_88E6052 | DEV_88E6021 | \ + DEV_FF_EG | DEV_FF_HG | DEV_88E6060 | \ + DEV_88E6063 | DEV_FH_VPN | DEV_88E6083 | \ + DEV_88E6065_FAMILY ) + +#define DEV_ENHANCED_FE_SWITCH ( DEV_88E6065_FAMILY ) + +#define DEV_EXTERNAL_PHY \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY ) + +#define DEV_EXTERNAL_PHY_ONLY ( DEV_88E6181 | DEV_88E6183 | DEV_88E6182 | DEV_88E6185 ) + +#define DEV_INTERNAL_GPHY ( DEV_88E6108 ) + +#define DEV_FC_WITH_VALUE \ + ( DEV_88E6093 | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_FC_STATUS \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_FC_DIS_STATUS ( DEV_88E6065_FAMILY ) + +#define DEV_CORE_TAG ( DEV_88E6093 | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_PCS_LINK ( DEV_88E6093 | DEV_88E6095_FAMILY | \ + DEV_88E6185_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_MGMII_STATUS ( DEV_88E6093 | DEV_88E6095_FAMILY | \ + DEV_88E6185_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY ) + +#define DEV_MGMII_REVERSE_STATUS ( DEV_88E6165_FAMILY ) + +#define DEV_88E6183_FAMILY ( DEV_88E6183 | DEV_88E6185_FAMILY ) +#define DEV_88E6093_FAMILY ( DEV_88E6093 | DEV_88E6095_FAMILY | \ + DEV_88E6185_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_UNMANAGED_SWITCH ( DEV_88E6181 ) + +#define DEV_PCS \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY ) + +#define DEV_GIGABIT_SWITCH \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_GIGABIT_MANAGED_SWITCH \ + ( DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_CASCADE_PORT \ + ( DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + + +#define DEV_CROSS_CHIP_VLAN \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_CROSS_CHIP_PORT_VLAN \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_TRUNK ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_8_TRUNKING ( DEV_88E6092 | DEV_88E6182 ) + +#define DEV_TRUNK_NEW_ID_LOCATION \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_REDUCED_TRUNK ( DEV_88E6065_FAMILY ) + +#define DEV_STACKING \ + ( DEV_88E6095 | DEV_88E6185 | DEV_88E6108 | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_FRAME_SIZE_1632 \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) /* Not used */ + +#define DEV_FLOW_CTRL_DELAY \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +/* port based CPU Port */ +#define DEV_ENHANCED_CPU_PORT \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_CPU_DEST_PER_PORT \ + ( DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_CPU_PORT ( DEV_88E6065_FAMILY ) +#define DEV_MULTICAST ( DEV_88E6065_FAMILY ) + +#define DEV_CPU_DEST \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_MIRROR_DEST \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_QVLAN_ONLY \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY ) +#define DEV_5BIT_PORT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_SDET_POLARITY \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY ) +#define DEV_LIMITED_SDET \ + ( DEV_88E6165_FAMILY ) /* only port 4 & 5 support SDET Polarity */ + +/* supports Reserved Multicast, etc */ +#define DEV_ENHANCED_MULTICAST \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_ENHANCED_MULTICAST_2X \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + + +#define DEV_ARP_DEST_SUPPORT ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_MARVELL_TAG_FLOW_CTRL \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_USE_DOUBLE_TAG_DATA \ + ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) /* Not Used */ + +#define DEV_MARVELL_TAG_LOOP_BLOCK ( DEV_88E6095_FAMILY | DEV_88E6185_FAMILY ) + +#define DEV_LOOPBACK_FILTER \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_FLOOD_BROADCAST \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_TAG_FLOW_CONTROL \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_ALWAYS_USE_VTU ( DEV_88E6097_FAMILY ) + +#define DEV_RM_ONE_PTAG \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + + +#define DEV_PRIORITY_OVERRIDE \ + ( DEV_88E6183 | DEV_88E6093 | DEV_88E6095 | \ + DEV_88E6185 | DEV_88E6108 | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_EXT_PRIORITY_OVERRIDE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_PRIORITY_OVERRIDE_TABLE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_FQPRI_IN_TABLE ( DEV_88E6065 ) + +#define DEV_FQPRI_OVERRIDE ( DEV_88E6065 ) + +#define DEV_Px_MODE ( DEV_88E6065_FAMILY ) + +#define DEV_SA_FILTERING \ + ( DEV_88E6065 | DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_ARP_TO_CPU \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_EGRESS_FLOOD \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_FORCE_MAP ( DEV_88E6065_FAMILY ) + +#define DEV_PORT_SCHEDULE ( DEV_88E6065 ) + +#define DEV_PORT_MIXED_SCHEDULE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_OUT_Q_SIZE \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_OUT_Q_512 \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) +#define DEV_FULL_Q_COUNTER \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_PROVIDER_TAG ( DEV_88E6065_FAMILY ) + +#define DEV_OLD_HEADER ( DEV_88E6065_FAMILY ) + +#define DEV_RECURSIVE_TAG_STRIP ( DEV_88E6065_FAMILY ) + +#define DEV_FORCE_WITH_VALUE \ + ( DEV_88E6181 | DEV_88E6183 | DEV_88E6093 | \ + DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +/* Grouping ATU Entry State for Unicast */ + +#define DEV_UC_7_DYNAMIC \ + ( DEV_88E6065_FAMILY | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6183 | DEV_88E6093 | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_UC_NO_PRI_TO_CPU_STATIC_NRL \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_UC_TO_CPU_STATIC_NRL \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_UC_NO_PRI_STATIC_NRL \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_UC_STATIC_NRL \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_UC_NO_PRI_TO_CPU_STATIC \ + ( DEV_88E6065_FAMILY | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_UC_TO_CPU_STATIC \ + ( DEV_88E6065_FAMILY | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_UC_NO_PRI_STATIC \ + ( DEV_88E6065_FAMILY | DEV_88E6095_FAMILY | DEV_88E6185_FAMILY | \ + DEV_88E6183 | DEV_88E6093 | DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_UC_STATIC ( DEV_STATIC_ADDR ) + + +/* Grouping ATU Entry State for Multicast */ + +#define DEV_MC_MGM_STATIC_UNLIMITED_RATE \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_MC_PRIO_MGM_STATIC_UNLIMITED_RATE \ + ( DEV_88E6065_FAMILY | DEV_88E6097_FAMILY | \ + DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_MC_STATIC_UNLIMITED_RATE ( DEV_STATIC_ADDR & ~DEV_88E6052 ) + +#define DEV_MC_MGM_STATIC ( DEV_STATIC_ADDR ) + +#define DEV_MC_STATIC ( DEV_STATIC_ADDR ) +#define DEV_MC_PRIO_MGM_STATIC ( DEV_STATIC_ADDR ) + +#define DEV_MC_PRIO_STATIC_UNLIMITED_RATE ( DEV_STATIC_ADDR & ~ (DEV_88E6083|DEV_88E6052) ) + +#define DEV_MC_PRIO_STATIC ( DEV_STATIC_ADDR & ~DEV_88E6083 ) + + +/* Grouping Devices that support Pause Limit */ +#define DEV_PAUSE_LIMIT \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +/* Grouping Devices that support Frame Mode */ +#define DEV_FRAME_MODE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | \ + DEV_88E6351_FAMILY ) + +#define DEV_POLICY \ + ( DEV_88E6097 | DEV_88E6165 | DEV_88E6351_AVB_FAMILY | DEV_88E6175 ) + +#define DEV_PORT_ETYPE \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_FID_REG \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_FRAME_TO_REGISTER \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_RMU_MODE ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_SWITCH_MAC_REG \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_ATU_STATS \ + ( DEV_88E6097_FAMILY | DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) + +#define DEV_JUMBO_MODE \ + ( DEV_88E6165_FAMILY | DEV_88E6351_FAMILY ) +#define DEV_PTP ( DEV_88E6165_FAMILY | DEV_88E6351_AVB_FAMILY ) +#define DEV_PTP_2 ( DEV_88E6351_AVB_FAMILY ) +#define DEV_TAI ( DEV_88E6351_AVB_FAMILY ) +#define DEV_AVB_POLICY ( DEV_88E6351_AVB_FAMILY ) +#define DEV_QAV ( DEV_88E6351_AVB_FAMILY ) + +#define DEV_TSM_RESOURCE ( DEV_88E6351_AVB_FAMILY ) + +#define DEV_200BASE_CFG ( DEV_88E6351_FAMILY ) +#define DEV_RGMII_TIMING ( DEV_88E6351_FAMILY ) +#define DEV_Q_COUNTER_TABLE ( DEV_88E6351_FAMILY ) +#define DEV_LED_CFG ( DEV_88E6351_FAMILY ) + +#define DEV_MAC_AVB ( DEV_88E6351_AVB_FAMILY ) + +#define DEV_CLK_125 ( DEV_88E6351_FAMILY ) + +#define DEV_QAVB_PRIORITY_OVERRIDE_TABLE \ + ( DEV_88E6351_AVB_FAMILY ) +#define DEV_FRAME_PRIORITY_OVERRIDE_TABLE \ + ( DEV_88E6351_FAMILY ) + +#define DEV_SCRATCH_MISC_CTRL ( DEV_88E6351_FAMILY ) +#define DEV_IP_MAPPING_TABLE ( DEV_88E6351_FAMILY ) +#define DEV_EEPROM ( DEV_88E6351_FAMILY ) + + +/* Macros to utilize Device Group */ + +#define IS_IN_DEV_GROUP(dev,_group) (dev->devName & (_group)) + +/* need to check port number(_hwPort) later */ +#define IS_VALID_API_CALL(dev,_hwPort, _devName) \ + ((_hwPort == GT_INVALID_PORT) ? GT_BAD_PARAM : \ + (!(dev->devName & (_devName)) ? GT_NOT_SUPPORTED : GT_OK)) + +#define DOES_DEVPORT_SUPPORT_PCS(dev, _hwPort) \ + (!(dev->devName & DEV_GIGABIT_SWITCH) || \ + (dev->devName & DEV_INTERNAL_GPHY) || \ + (!(dev->devName & DEV_EXTERNAL_PHY_ONLY) && (((_hwPort) < 8) || ((_hwPort) > 10))) \ + ? 0 : 1) + +#define IS_CONFIGURABLE_PHY(dev,_hwPort) driverIsPhyAttached(dev,_hwPort) +#define GT_GET_PHY_ID(dev,_hwPort) driverGetPhyID(dev,_hwPort) + +#define GT_GET_SERDES_PORT(dev,_hwPort) driverGetSerdesPort(dev,_hwPort) + +#define GT_GIG_PHY_INT_MASK(dev,_portVct) ((_portVct) = (_portVct) & 0xF7) + + +#define RECOMMENDED_ESB_LIMIT(dev, _bps) \ + ((IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE))?16777200:0xFFFFFF) + +#define RECOMMENDED_CBS_LIMIT(dev, _bps) \ + ((IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE))?393216:0x200000) + +#define RECOMMENDED_BUCKET_INCREMENT(dev, _bps) \ + ((IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE))?174: \ + ((_bps) < 1000)?0x3d: \ + ((_bps) < 10000)?0x1f:0x4) + +#define FACTOR_FROM_BUCKET_INCREMENT(dev, _bInc, _f) \ + { \ + if(IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) \ + { \ + if((_bInc) == 174) {(_f) = 64;} \ + else {(_f) = 0;} \ + } \ + else \ + { \ + if((_bInc) == 0x3d) {(_f) = 64;} \ + else if((_bInc) == 0x1f) {(_f) = 128;} \ + else if((_bInc) == 0x4) {(_f) = 1000;} \ + else {(_f) = 0;} \ + } \ + } + + +#define TSM_GET_CBS(_rate,_cts) ((_rate)/((_cts)*8)) +#define TSM_GET_RATE(_cbs,_cts) ((_cbs)*8*(_cts)) + + +#define GT_PTP_BUILD_TIME(_time1, _time2) (((_time1) << 16) | (_time2)) +#define GT_PTP_L16_TIME(_time1) ((_time1) & 0xFFFF) +#define GT_PTP_H16_TIME(_time1) (((_time1) >> 16) & 0xFFFF) + +/* + * typedef: enum GT_ATU_STATS_OP + * + * Description: Enumeration of the ATU Statistics operation + * + * Enumerations: + * GT_ATU_STATS_ALL - count all valid entry + * GT_ATU_STATS_NON_STATIC - count all vaild non-static entry + * GT_ATU_STATS_ALL_FID - count all valid entry in the given DBNum(or FID) + * GT_ATU_STATS_NON_STATIC_FID - count all valid non-static entry in the given DBNum(or FID) + */ +typedef enum +{ + GT_ATU_STATS_ALL = 0, + GT_ATU_STATS_NON_STATIC, + GT_ATU_STATS_ALL_FID, + GT_ATU_STATS_NON_STATIC_FID +}GT_ATU_STATS_OP; + + +/* + * typedef: struct GT_ATU_STAT + * + * Description: + * This structure is used to count ATU entries. + * + * Fields: + * op - counter type + * DBNum - required only if op is either GT_ATU_STATS_FID or + * GT_ATU_STATS_NON_STATIC_FID + */ +typedef struct +{ + GT_ATU_STATS_OP op; + GT_U32 DBNum; +} GT_ATU_STAT; + + +typedef struct _EXTRA_OP_DATA +{ + GT_U32 moveFrom; + GT_U32 moveTo; + GT_U32 intCause; + GT_U32 reserved; +} GT_EXTRA_OP_DATA; + +/******************************************************************************* +* gvtuGetViolation +* +* DESCRIPTION: +* Get VTU Violation data +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation +( + IN GT_QD_DEV* dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +); + +/******************************************************************************* +* gvtuGetViolation2 +* +* DESCRIPTION: +* Get VTU Violation data (for Gigabit Device) +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation2 +( + IN GT_QD_DEV* dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +); + +/******************************************************************************* +* gvtuGetViolation3 +* +* DESCRIPTION: +* Get VTU Violation data (for Spinnaker family Device) +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation3 +( + IN GT_QD_DEV* dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +); + +/******************************************************************************* +* gatuGetViolation +* +* DESCRIPTION: +* Get ATU Violation data +* +* INPUTS: +* None. +* +* OUTPUTS: +* atuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gatuGetViolation +( + IN GT_QD_DEV *dev, + OUT GT_ATU_INT_STATUS *atuIntStatus +); + +/******************************************************************************* +* gsysSetRetransmitMode +* +* DESCRIPTION: +* This routine set the Retransmit Mode. +* +* INPUTS: +* en - GT_TRUE Retransimt Mode is enabled, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetRetransmitMode +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRetransmitMode +* +* DESCRIPTION: +* This routine get the Retransmit Mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE Retransmit Mode is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetRetransmitMode +( + IN GT_QD_DEV* dev, + IN GT_BOOL *en +); + +/******************************************************************************* +* gsysSetLimitBackoff +* +* DESCRIPTION: +* This routine set the Limit Backoff bit. +* +* INPUTS: +* en - GT_TRUE: uses QoS half duplex backoff operation +* GT_FALSE: uses normal half duplex backoff operation +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetLimitBackoff +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetLimitBackoff +* +* DESCRIPTION: +* This routine set the Limit Backoff bit. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE: uses QoS half duplex backoff operation +* GT_FALSE: uses normal half duplex backoff operation +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetLimitBackoff +( + IN GT_QD_DEV* dev, + IN GT_BOOL *en +); + +/******************************************************************************* +* gsysSetRsvRegPri +* +* DESCRIPTION: +* This routine set the Reserved Queue's Requesting Priority +* +* INPUTS: +* en - GT_TRUE: use the last received frome's priority +* GT_FALSE:use the last switched frame's priority +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetRsvReqPri +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRsvReqPri +* +* DESCRIPTION: +* This routine get the Reserved Queue's Requesting Priority +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE: use the last received frome's priority +* GT_FALSE:use the last switched frame's priority +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetRsvReqPri +( + IN GT_QD_DEV* dev, + IN GT_BOOL *en +); + +/******************************************************************************* +* gsysGetPtrCollision +* +* DESCRIPTION: +* This routine get the QC Pointer Collision. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE Discard is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* This feature is for both clippership and fullsail +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetPtrCollision +( + IN GT_QD_DEV* dev, + IN GT_BOOL *mode +); + +/******************************************************************************* +* gsysGetDpvCorrupt +* +* DESCRIPTION: +* This routine get the DpvCorrupt bit. This bit is set to a one when the +* QC detects a destination vector error +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE: destination vector corrupt, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* This feature is on clippership, but not on fullsail +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetDpvCorrupt +( + IN GT_BOOL *mode +); + +/******************************************************************************* +* gsysGetMissingPointers +* +* DESCRIPTION: +* This routine get the Missing Pointer bit. This bit is set to a one when +* the Register File detects less than 64 pointers in the Link List. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE: Missing Pointers error, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* This feature is on clippership, but not on fullsail +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetMissingPointers +( + IN GT_QD_DEV* dev, + IN GT_BOOL *mode +); + +/******************************************************************************* +* gtDbgPrint +* +* DESCRIPTION: +* . +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* +* COMMENTS: +* None +* +*******************************************************************************/ +void gtDbgPrint(char* format, ...); + + +/******************************************************************************* +* gtSemRegister +* +* DESCRIPTION: +* Assign QuarterDeck Semaphore functions to the given semaphore set. +* QuarterDeck maintains its own memory for the structure. +* +* INPUTS: +* semFunctions - point to the GT_SEM_ROUTINES +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtSemRegister +( + IN GT_QD_DEV* dev, + IN GT_SEM_ROUTINES* semRoutines +); + + +/******************************************************************************* +* gpirlInitialize +* +* DESCRIPTION: +* This routine initializes PIRL Resources. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlInitialize +( + IN GT_QD_DEV *dev +); + +/******************************************************************************* +* gpirl2Initialize +* +* DESCRIPTION: +* This routine initializes PIRL2 Resources. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2Initialize +( + IN GT_QD_DEV *dev +); + + + +/******************************************************************************* +* lport2port +* +* DESCRIPTION: +* This function converts logical port number to physical port number +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_U8 lport2port +( + IN GT_U16 portVec, + IN GT_LPORT port +); + +/******************************************************************************* +* port2lport +* +* DESCRIPTION: +* This function converts physical port number to logical port number +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_LPORT port2lport +( + IN GT_U16 portVec, + IN GT_U8 hwPort +); + +/******************************************************************************* +* lportvec2portvec +* +* DESCRIPTION: +* This function converts logical port vector to physical port vector +* +* INPUTS: +* portVec - physical port list in vector +* lVec - logical port vector +* OUTPUTS: +* None. +* RETURNS: +* physical port vector +* +* COMMENTS: +* +*******************************************************************************/ +GT_U32 lportvec2portvec +( + IN GT_U16 portVec, + IN GT_U32 lVec +); + +/******************************************************************************* +* portvec2lportvec +* +* DESCRIPTION: +* This function converts physical port vector to logical port vector +* +* INPUTS: +* portVec - physical port list in vector +* pVec - physical port vector +* OUTPUTS: +* None. +* RETURNS: +* logical port vector +* +* COMMENTS: +* +*******************************************************************************/ +GT_U32 portvec2lportvec +( + IN GT_U16 portVec, + IN GT_U32 pVec +); + + +/******************************************************************************* +* lport2phy +* +* DESCRIPTION: +* This function converts logical port number to physical phy number. +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_U8 lport2phy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +#ifdef __cplusplus +} +#endif + +#endif /* __msApiInternal_h */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtMiiSmiIf.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtMiiSmiIf.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtMiiSmiIf.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtMiiSmiIf.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,156 @@ +#include + +/******************************************************************************** +* gtMiiSmiIf.h +* +* DESCRIPTION: +* Includes functions prototypes for initializing and accessing the +* MII / SMI interface. +* This is the only file to be included from upper layers. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 2 $ +* +*******************************************************************************/ + +#ifndef __gtMiiSmiIfh +#define __gtMiiSmiIfh + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* miiSmiIfInit +* +* DESCRIPTION: +* This function initializes the MII / SMI interface. +* +* INPUTS: +* None. +* +* OUTPUTS: +* highSmiDevAddr - Indicates whether to use the high device register +* addresses when accessing switch's registers (of all kinds) +* i.e, the devices registers range is 0x10 to 0x1F, or to +* use the low device register addresses (range 0x0 to 0xF). +* GT_TRUE - use high addresses (0x10 to 0x1F). +* GT_FALSE - use low addresses (0x0 to 0xF). +* +* RETURNS: +* DEVICE_ID - on success +* 0 - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U16 miiSmiIfInit +( + IN GT_QD_DEV *dev, + OUT GT_BOOL * highSmiDevAddr +); + +/******************************************************************************* +* miiSmiManualIfInit +* +* DESCRIPTION: +* This function returns Device ID from the given base address +* +* INPUTS: +* baseAddr - either 0x0 or 0x10. Indicates whether to use the low device +* register address or high device register address. +* The device register range is from 0x0 to 0xF or from 0x10 +* to 0x1F for 5 port switchs and from 0x0 to 0x1B for 8 port +* switchs. +* +* OUTPUTS: +* None. +* +* RETURNS: +* DEVICE_ID - on success +* 0 - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U16 miiSmiManualIfInit +( + IN GT_QD_DEV *dev, + IN GT_U32 baseAddr +); + +/******************************************************************************* +* miiSmiIfReadRegister +* +* DESCRIPTION: +* This function reads a register throw the SMI / MII interface, to be used +* by upper layers. +* +* INPUTS: +* phyAddr - The PHY address to be read. +* regAddr - The register address to read. +* +* OUTPUTS: +* data - The register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS miiSmiIfReadRegister +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + OUT GT_U16 *data +); + + +/******************************************************************************* +* miiSmiIfWriteRegister +* +* DESCRIPTION: +* This function writes to a register throw the SMI / MII interface, to be +* used by upper layers. +* +* INPUTS: +* phyAddr - The PHY address to be read. +* regAddr - The register address to read. +* data - The data to be written to the register. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS miiSmiIfWriteRegister +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + IN GT_U16 data +); + +#ifdef __cplusplus +} +#endif + +#endif /* __gtMiiSmiIfh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtSem.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtSem.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtSem.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/gtSem.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,153 @@ +#include + +/******************************************************************************** +* gtOs.h +* +* DESCRIPTION: +* Operating System wrapper +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 3 $ +*******************************************************************************/ + +#ifndef __gtSemh +#define __gtSemh + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***** Defines ********************************************************/ + +#define OS_WAIT_FOREVER 0 + +#define OS_MAX_TASKS 30 +#define OS_MAX_TASK_NAME_LENGTH 10 + +#define OS_MAX_QUEUES 30 +#define OS_MAX_QUEUE_NAME_LENGTH 10 + +#define OS_MAX_EVENTS 10 + +#define OS_MAX_SEMAPHORES 50 + +#define OS_EOF (-1) + + +/******************************************************************************* +* gtSemCreate +* +* DESCRIPTION: +* Create semaphore. +* +* INPUTS: +* state - beginning state of the semaphore, either SEM_EMPTY or SEM_FULL +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_SEM if success. Otherwise, NULL +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_SEM gtSemCreate +( + IN GT_QD_DEV *dev, + IN GT_SEM_BEGIN_STATE state +); + +/******************************************************************************* +* gtSemDelete +* +* DESCRIPTION: +* Delete semaphore. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtSemDelete +( + IN GT_QD_DEV *dev, + IN GT_SEM smid +); + +/******************************************************************************* +* gtSemTake +* +* DESCRIPTION: +* Wait for semaphore. +* +* INPUTS: +* smid - semaphore Id +* timeOut - time out in miliseconds or 0 to wait forever +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* OS_TIMEOUT - on time out +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtSemTake +( + IN GT_QD_DEV *dev, + IN GT_SEM smid, + IN GT_U32 timeOut +); + +/******************************************************************************* +* gtSemGive +* +* DESCRIPTION: +* release the semaphore which was taken previously. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtSemGive +( + IN GT_QD_DEV *dev, + IN GT_SEM smid +); + +#ifdef __cplusplus +} +#endif + +#endif /* __gtSemh */ +/* Do Not Add Anything Below This Line */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/platformDeps.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/platformDeps.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/h/platform/platformDeps.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/h/platform/platformDeps.h 2011-04-04 13:57:35.035598019 -0400 @@ -0,0 +1,31 @@ +#include + +/******************************************************************************** +* platformDeps.h +* +* DESCRIPTION: +* platform dependent definitions +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __platformDepsh +#define __platformDepsh + +#include +#ifdef __cplusplus +extern "C" { +#endif + +GT_BOOL defaultMiiRead (unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL defaultMiiWrite (unsigned int portNumber , unsigned int miiReg, unsigned int value); + +#ifdef __cplusplus +} +#endif + +#endif /* platformDepsh */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiDefs.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiDefs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiDefs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiDefs.h 2011-04-04 13:57:35.045596301 -0400 @@ -0,0 +1,3862 @@ +#include + +/******************************************************************************** +* msApiDefs.h +* +* DESCRIPTION: +* API definitions for QuarterDeck Device +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApiDefs_h +#define __msApiDefs_h + +#ifdef __cplusplus +extern "C" { +#endif +#include +/* Debug function */ +#ifdef DEBUG_QD +#define DBG_INFO(x) gtDbgPrint x +#else +#define DBG_INFO(x); +#endif /* DEBUG_QD */ + +typedef GT_U32 GT_SEM; + +#define ETHERNET_HEADER_SIZE GT_ETHERNET_HEADER_SIZE +#define IS_MULTICAST_MAC GT_IS_MULTICAST_MAC +#define IS_BROADCAST_MAC GT_IS_BROADCAST_MAC + +#define GT_INVALID_PHY 0xFF +#define GT_INVALID_PORT 0xFF +#define GT_INVALID_PORT_VEC 0xFFFFFFFF + +#define GT_UNUSED_PARAM(_a) (_a)=(_a) + +/* + * Logical Port value based on a Port + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |0| reserved | port | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * + * The following macros should be used to extract specific info + * from a Logical Port index + */ +typedef GT_U32 GT_LPORT; +typedef GT_U32 GT_ETYPE; + + +/* Define the different device type that may exist in system */ +typedef enum +{ + GT_88E6021 = 0x021, + GT_88E6051 = 0x051, + GT_88E6052 = 0x052, + GT_88E6060 = 0x060, + GT_88E6063 = 0x153, + GT_FH_VPN = 0xF53, + GT_FF_EG = 0xF91, + GT_FF_HG = 0xF93, + + GT_88E6083 = 0x083, + + GT_88E6181 = 0x1A0, + + GT_88E6153 = 0x1A1, + GT_88E6183 = 0x1A3, + + GT_88E6093 = 0x093, + GT_88E6092 = 0x097, + GT_88E6045 = 0x094, + GT_88E6095 = 0x095, + + GT_88E6152 = 0x1A4, + GT_88E6155 = 0x1A5, + GT_88E6182 = 0x1A6, + GT_88E6185 = 0x1A7, + + GT_88E6121 = 0x104, + GT_88E6122 = 0x105, + GT_88E6131 = 0x106, + GT_88E6108 = 0x107, + + GT_88E6031 = 0x031, + GT_88E6035 = 0x035, + GT_88E6055 = 0x055, + GT_88E6061 = 0x061, + GT_88E6065 = 0x065, + + GT_88E6046 = 0x048, + GT_88E6047 = 0x049, + GT_88E6085 = 0x04A, + GT_88E6096 = 0x098, + GT_88E6097 = 0x099, + + GT_88E6123 = 0x121, + GT_88E6140 = 0x141, + GT_88E6161 = 0x161, + GT_88E6165 = 0x165, + + GT_88E6351 = 0x375, + GT_88E6175 = 0x175, + GT_88E6125 = 0x124, /* was 88E6124 */ + GT_88E6171 = 0x171, + GT_88E6321 = 0x324, /* was 88E6325 */ + GT_88E6350 = 0x371, /* was 88E6371 */ + GT_KW2_INT = 0x044 /* Internal Swiych in KW2 */ + +}GT_DEVICE; + + +/* Definition for the revision number of the device */ +typedef enum +{ + GT_REV_0 = 0, + GT_REV_1, + GT_REV_2, + GT_REV_3 +}GT_DEVICE_REV; + + +/* ToDo: No Used */ +typedef enum +{ + INTR_MODE_DISABLE =0, + INTR_MODE_ENABLE +}INTERRUPT_MODE; + +/* Definition for the Port Speed */ +typedef enum +{ + PORT_SPEED_10_MBPS = 0, + PORT_SPEED_100_MBPS = 1, + PORT_SPEED_200_MBPS = 2, /* valid only if device support */ + PORT_SPEED_1000_MBPS = 2 , /* valid only if device support */ + PORT_SPEED_UNKNOWN = 3 +} GT_PORT_SPEED_MODE; + +/* Definition for the forced Port Speed */ +typedef enum +{ + PORT_FORCE_SPEED_10_MBPS = 0, + PORT_FORCE_SPEED_100_MBPS = 1, + PORT_FORCE_SPEED_200_MBPS = 2, /* valid only if device support */ + PORT_FORCE_SPEED_1000_MBPS = 2, /* valid only if device support */ + PORT_DO_NOT_FORCE_SPEED =3 +} GT_PORT_FORCED_SPEED_MODE; + +/* Definition for the forced Port Duplex mode */ +typedef enum +{ + PORT_DO_NOT_FORCE_DUPLEX, + PORT_FORCE_FULL_DUPLEX, + PORT_FORCE_HALF_DUPLEX +} GT_PORT_FORCED_DUPLEX_MODE; + +/* Definition for the forced Port Link */ +typedef enum +{ + PORT_DO_NOT_FORCE_LINK, + PORT_FORCE_LINK_UP, + PORT_FORCE_LINK_DOWN +} GT_PORT_FORCED_LINK_MODE; + +/* Definition for the forced flow control mode */ +typedef enum +{ + PORT_DO_NOT_FORCE_FC, + PORT_FORCE_FC_ENABLED, + PORT_FORCE_FC_DISABLED +} GT_PORT_FORCED_FC_MODE; + +/* Definition for the PPU state */ +typedef enum +{ + PPU_STATE_DISABLED_AT_RESET, + PPU_STATE_ACTIVE, + PPU_STATE_DISABLED_AFTER_RESET, + PPU_STATE_POLLING +} GT_PPU_STATE; + + +/* + * Typedef: enum GT_PORT_CONFIG_MODE + * + * Description: Defines port's interface type configuration mode determined at + * reset. This definition may not represent the device under use. + * Please refer to the device datasheet for detailed information. + * + */ +typedef enum +{ + PORTCFG_GMII_125MHZ = 0, /* Px_GTXCLK = 125MHz, 1000BASE */ + PORTCFG_FD_MII_0MHZ = 1, /* Px_GTXCLK = 0 MHz, Power Save */ + PORTCFG_FDHD_MII_25MHZ = 2, /* Px_GTXCLK = 25MHz, 100BASE */ + PORTCFG_FDHD_MII_2_5MHZ = 3, /* Px_GTXCLK = 2.5MHz, 10BASE */ + PORTCFG_FD_SERDES = 4, /* Default value */ + PORTCFG_FD_1000BASE_X = 5, + PORTCFG_MGMII = 6, /* duplex, speed determined by the PPU */ + PORTCFG_DISABLED = 7 +} GT_PORT_CONFIG_MODE; + + +typedef enum +{ + GT_SA_FILTERING_DISABLE = 0, + GT_SA_DROP_ON_LOCK, + GT_SA_DROP_ON_UNLOCK, + GT_SA_DROP_TO_CPU +} GT_SA_FILTERING; + + +/* Definition for the Ingree/Egress Frame Mode */ +typedef enum +{ + GT_FRAME_MODE_NORMAL = 0, /* Normal Network */ + GT_FRAME_MODE_DSA, /* Distributed Switch Architecture */ + GT_FRAME_MODE_PROVIDER, /* Provider */ + GT_FRAME_MODE_ETHER_TYPE_DSA /* Ether Type DSA */ +} GT_FRAME_MODE; + +/* + * Typedef: enum GT_JUMBO_MODE + * + * Description: Defines Jumbo Frame Size allowed to be tx and rx + * + * Fields: + * GT_JUMBO_MODE_1522 - Rx and Tx frames with max byte of 1522. + * GT_JUMBO_MODE_2048 - Rx and Tx frames with max byte of 2048. + * GT_JUMBO_MODE_10240 - Rx and Tx frames with max byte of 10240. + * + */ +typedef enum +{ + GT_JUMBO_MODE_1522 = 0, + GT_JUMBO_MODE_2048, + GT_JUMBO_MODE_10240 +} GT_JUMBO_MODE; + + +/* + * Typedef: enum GT_PRI_OVERRIDE + * + * Description: Defines the priority override + * + * Fields: + * PRI_OVERRIDE_NONE - Normal frame priority processing occurs. + * PRI_OVERRIDE_FRAME_QUEUE - + * Both frame and queue overrides take place on the frame. + * PRI_OVERRIDE_FRAME - + * Overwite the frame's FPri (frame priority). + * If the frame egresses tagged, the priority in the frame will be + * the overwritten priority value. + * PRI_OVERRIDE_QUEUE - + * Overwite the frame's QPri (queue priority). + * QPri is used internally to map the frame to one of the egress + * queues inside the switch. + * + */ +typedef enum +{ + PRI_OVERRIDE_NONE = 0, + PRI_OVERRIDE_FRAME_QUEUE, + PRI_OVERRIDE_FRAME, + PRI_OVERRIDE_QUEUE +} GT_PRI_OVERRIDE; + + +/* + * Typedef: enum GT_FRAME_POLICY + * + * Description: Defines the policy of the frame + * + * Fields: + * FRAME_POLICY_NONE - Normal frame switching + * FRAME_POLICY_MIRROR - Mirror(copy) frame to the MirrorDest port + * FRAME_POLICY_TRAP - Trap(re-direct) frame to the CPUDest port + * FRAME_POLICY_DISCARD - Discard(filter) the frame + * + */ +typedef enum +{ + FRAME_POLICY_NONE = 0, + FRAME_POLICY_MIRROR, + FRAME_POLICY_TRAP, + FRAME_POLICY_DISCARD +} GT_FRAME_POLICY; + + +/* + * Typedef: enum GT_POLICY_TYPE + * + * Description: Defines the policy type + * + * Fields: + * POLICY_TYPE_DA - Policy based on Destination Address + * POLICY_TYPE_SA - Policy based on Source Address + * POLICY_TYPE_VTU - Policy based on VID + * POLICY_TYPE_ETYPE - based on Ether Type of a frame + * POLICY_TYPE_PPPoE - Policy for the frame with Ether Type of 0x8863 + * POLICY_TYPE_VBAS - Policy for the frame with Ether Type of 0x8200 + * POLICY_TYPE_OPT82 - Policy for the frame with DHCP Option 82 + * POLICY_TYPE_UDP - Policy for the frame with Broadcast IPv4 UDP or + * Multicast IPv6 UDP + */ +typedef enum +{ + POLICY_TYPE_DA, + POLICY_TYPE_SA, + POLICY_TYPE_VTU, + POLICY_TYPE_ETYPE, + POLICY_TYPE_PPPoE, + POLICY_TYPE_VBAS, + POLICY_TYPE_OPT82, + POLICY_TYPE_UDP +} GT_POLICY_TYPE; + + +/* + * Typedef: enum GT_PRI_OVERRIDE_FTYPE + * + * Description: Definition of the frame type for priority override + * + * Fields: + * FTYPE_DSA_TO_CPU_BPDU - + * Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). + * Not used on non-DSA Control frames. + * FTYPE_DSA_TO_CPU_F2R - + * Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register + * Reply). Not used on non-DSA Control frames. + * FTYPE_DSA_TO_CPU_IGMP - + * Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) + * and on non-DSA Control frames that are IGMP or MLD trapped + * FTYPE_DSA_TO_CPU_TRAP - + * Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and + * on non-DSA Control frames that are Policy Trapped + * FTYPE_DSA_TO_CPU_ARP - + * Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and + * on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). + * FTYPE_DSA_TO_CPU_MIRROR - + * Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and + * on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). + * FTYPE_DSA_TO_CPU_RESERVED - + * Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not + * used on non-DSA Control frames. + * FTYPE_DSA_TO_CPU_UCAST_MGMT - + * Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast + * MGMT). Not used on non-DSA Control frames. + * FTYPE_DSA_FROM_CPU - + * Used on DSA From_CPU frames. Not used on non-DSA Control frame + * FTYPE_DSA_CROSS_CHIP_FC - + * Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow + * Control). Not used on non-DSA Control frames. + * FTYPE_DSA_CROSS_CHIP_EGRESS_MON - + * Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). + * Not used on non-DSA Control frames. + * FTYPE_DSA_CROSS_CHIP_INGRESS_MON - + * Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). + * Not used on non-DSA Control frames. + * FTYPE_PORT_ETYPE_MATCH - + * Used on normal network ports (see gprtSetFrameMode API) + * on frames whose Ethertype matches the port's PortEType register. + * Not used on non-DSA Control frames. + * FTYPE_BCAST_NON_DSA_CONTROL - + * Used on Non-DSA Control frames that contain a Broadcast + * destination address. Not used on DSA Control frames. + * FTYPE_PPPoE_NON_DSA_CONTROL - + * Used on Non-DSA Control frames that contain an Ether Type 0x8863 + * (i.e., PPPoE frames). Not used on DSA Control frames. + * FTYPE_IP_NON_DSA_CONTROL - + * Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether + * Type. Not used on DSA Control frames. + */ +typedef enum +{ + FTYPE_DSA_TO_CPU_BPDU = 0, + FTYPE_DSA_TO_CPU_F2R, + FTYPE_DSA_TO_CPU_IGMP, + FTYPE_DSA_TO_CPU_TRAP, + FTYPE_DSA_TO_CPU_ARP, + FTYPE_DSA_TO_CPU_MIRROR, + FTYPE_DSA_TO_CPU_RESERVED, + FTYPE_DSA_TO_CPU_UCAST_MGMT, + FTYPE_DSA_FROM_CPU, + FTYPE_DSA_CROSS_CHIP_FC, + FTYPE_DSA_CROSS_CHIP_EGRESS_MON, + FTYPE_DSA_CROSS_CHIP_INGRESS_MON, + FTYPE_PORT_ETYPE_MATCH, + FTYPE_BCAST_NON_DSA_CONTROL, + FTYPE_PPPoE_NON_DSA_CONTROL, + FTYPE_IP_NON_DSA_CONTROL +} GT_PRI_OVERRIDE_FTYPE; + + +/* + * Typedef: struct GT_QPRI_TBL_ENTRY + * + * Description: This structure is used for the entry of Queue Priority Override + * Table. + * + * Fields: + * qPriEn - GT_TRUE to enable Queue Priority, GT_FALSE otherwise + * qPriority - priority to be overridden ( 0 ~ 3 ) only if qPriEn is GT_TRUE + * When qPriEn is GT_FALSE, qPriority should be ignored. + * + * Notes: If device does not support qPriAvbEn, qPriAvbEn and qAvbPriority fields + * will be ignored. + */ +typedef struct +{ + GT_BOOL qPriEn; + GT_U32 qPriority; +}GT_QPRI_TBL_ENTRY; + + +/* + * Typedef: struct GT_FPRI_TBL_ENTRY + * + * Description: This structure is used for the entry of Frame Priority Override + * Table. + * + * Fields: + * fPriEn - GT_TRUE to enable Frame Priority, GT_FALSE otherwise + * fPriority - priority to be overridden ( 0 ~ 7 ) only if fPriEn is GT_TRUE + * When fPriEn is GT_FALSE, fPriority should be ignored. + */ +typedef struct +{ + GT_BOOL fPriEn; + GT_U32 fPriority; +}GT_FPRI_TBL_ENTRY; + + +/* Maximam number of ports a switch may have. */ +#define MAX_SWITCH_PORTS 11 +#define VERSION_MAX_LEN 30 +#define MAX_QOS_WEIGHTS 128 + +/* + * Typedef: struct GT_QoS_WEIGHT + * + * Description: This structure is used for Programmable Round Robin Weights. + * + * Fields: + * len - length of the valid queue data + * queue - upto 128 queue data + */ +typedef struct +{ + GT_U32 len; + GT_U8 queue[MAX_QOS_WEIGHTS]; +}GT_QoS_WEIGHT; + + + +/* + * Typedef: struct GT_VERSION + * + * Description: This struct holds the package version. + * + * Fields: + * version - string array holding the version. + * + */ +typedef struct +{ + GT_U8 version[VERSION_MAX_LEN]; +}GT_VERSION; + + +/* + * typedef: struct GT_RMU + * + * Description: This struct holds the Remote Management Unit mode. + * + * Fields: + * rmuEn - enable or disable RMU + * port - logical port where RMU is enabled + */ +typedef struct +{ + GT_BOOL rmuEn; + GT_LPORT port; +} GT_RMU; + + + +/* + * Typedef: + * + * Description: Defines the different sizes of the Mac address table. + * + * Fields: + * ATU_SIZE_256 - 256 entries Mac address table. + * ATU_SIZE_512 - 512 entries Mac address table. + * ATU_SIZE_1024 - 1024 entries Mac address table. + * ATU_SIZE_2048 - 2048 entries Mac address table. + * ATU_SIZE_4096 - 4096 entries Mac address table. + * ATU_SIZE_8192 - 8192 entries Mac address table. + * + */ +typedef enum +{ + ATU_SIZE_256, + ATU_SIZE_512, + ATU_SIZE_1024, + ATU_SIZE_2048, + ATU_SIZE_4096, + ATU_SIZE_8192 +}ATU_SIZE; + + +/* + * typedef: enum GT_PORT_STP_STATE + * + * Description: Enumeration of the port spanning tree state. + * + * Enumerations: + * GT_PORT_DISABLE - port is disabled. + * GT_PORT_BLOCKING - port is in blocking/listening state. + * GT_PORT_LEARNING - port is in learning state. + * GT_PORT_FORWARDING - port is in forwarding state. + */ +typedef enum +{ + GT_PORT_DISABLE = 0, + GT_PORT_BLOCKING, + GT_PORT_LEARNING, + GT_PORT_FORWARDING +} GT_PORT_STP_STATE; + + +/* + * typedef: enum GT_EGRESS_MODE + * + * Description: Enumeration of the port egress mode. + * + * Enumerations: + * GT_UNMODIFY_EGRESS - frames are transmited unmodified. + * GT_TAGGED_EGRESS - all frames are transmited tagged. + * GT_UNTAGGED_EGRESS - all frames are transmited untagged. + * GT_ADD_TAG - always add a tag. (or double tag) + */ +typedef enum +{ + GT_UNMODIFY_EGRESS = 0, + GT_UNTAGGED_EGRESS, + GT_TAGGED_EGRESS, + GT_ADD_TAG +} GT_EGRESS_MODE; + +/* typedef: enum GT_DOT1Q_MODE */ + +typedef enum +{ + GT_DISABLE = 0, + GT_FALLBACK, + GT_CHECK, + GT_SECURE +} GT_DOT1Q_MODE; + + +/* typedef: enum GT_SW_MODE */ + +typedef enum +{ + GT_CPU_ATTATCHED = 0, /* ports come up disabled */ + GT_BACKOFF, /* EEPROM attac mode with old half duplex backoff mode */ + GT_STAND_ALONE, /* ports come up enabled, ignore EEPROM */ + GT_EEPROM_ATTATCHED /* EEPROM defined prot states */ +} GT_SW_MODE; + + +/* + * Typedef: enum GT_ATU_OPERARION + * + * Description: Defines the different ATU and VTU operations + * + * Fields: + * FLUSH_ALL - Flush all entries. + * FLUSH_UNLOCKED - Flush all unlocked entries in ATU. + * LOAD_PURGE_ENTRY - Load / Purge entry. + * GET_NEXT_ENTRY - Get next ATU or VTU entry. + * FLUSH_ALL_IN_DB - Flush all entries in a particular DBNum. + * FLUSH_UNLOCKED_IN_DB - Flush all unlocked entries in a particular DBNum. + * SERVICE_VIOLATONS - sevice violations of VTU + * + */ +typedef enum +{ + FLUSH_ALL = 1, /* for both atu and vtu */ + FLUSH_UNLOCKED, /* for atu only */ + LOAD_PURGE_ENTRY, /* for both atu and vtu */ + GET_NEXT_ENTRY, /* for both atu and vtu */ + FLUSH_ALL_IN_DB, /* for atu only */ + FLUSH_UNLOCKED_IN_DB, /* for atu only */ + SERVICE_VIOLATIONS /* for vtu only */ +} GT_ATU_OPERATION, GT_VTU_OPERATION; + + +/* + * typedef: enum GT_FLUSH_CMD + * + * Description: Enumeration of the address translation unit flush operation. + * + * Enumerations: + * GT_FLUSH_ALL - flush all entries. + * GT_FLUSH_ALL_UNBLK - flush all unblocked (or unlocked). + * GT_FLUSH_ALL_UNLOCKED - flush all unblocked (or unlocked). + */ +typedef enum +{ + GT_FLUSH_ALL = 1, + GT_FLUSH_ALL_UNBLK = 2, + GT_FLUSH_ALL_UNLOCKED = 2 +}GT_FLUSH_CMD; + +/* + * typedef: enum GT_MOVE_CMD + * + * Description: Enumeration of the address translation unit move or remove operation. + * When destination port is set to 0xF, Remove operation occurs. + * + * Enumerations: + * GT_MOVE_ALL - move all entries. + * GT_MOVE_ALL_UNBLK - move all unblocked (or unlocked). + * GT_MOVE_ALL_UNLOCKED - move all unblocked (or unlocked). + */ +typedef enum +{ + GT_MOVE_ALL = 1, + GT_MOVE_ALL_UNBLK = 2, + GT_MOVE_ALL_UNLOCKED = 2 +}GT_MOVE_CMD; + + +/* + * typedef: enum GT_ATU_UC_STATE + * + * Description: + * Enumeration of the address translation unit entry state of unicast + * entris. + * + * Enumerations: + * GT_UC_INVALID - invalid entry. + * GT_UC_DYNAMIC - unicast dynamic entry. + * GT_UC_NO_PRI_TO_CPU_STATIC_NRL + * - static unicast entry that will be forwarded to CPU without + * forcing priority and without rate limiting. + * GT_UC_TO_CPU_STATIC_NRL + * - static unicast entry that will be forwarded to CPU without + * rate limiting. + * GT_UC_NO_PRI_STATIC_NRL + * - static unicast entry without forcing priority and without. + * rate limiting. + * GT_UC_NO_PRI_STATIC_AVB_ENTRY + * - static unicast AVB entry without forcing priority if MacAvb is enabled. + * GT_UC_STATIC_NRL - static unicast entry without rate limiting. + * GT_UC_STATIC_AVB_ENTRY - static unicast AVB entry if MacAvb is enabled . + * GT_UC_NO_PRI_TO_CPU_STATIC + * - static unicast entry that will be forwarded to CPU without + * forcing priority. + * GT_UC_TO_CPU_STATIC - static unicast entry that will be forwarded to CPU. + * GT_UC_NO_PRI_STATIC - static unicast entry without forcing priority. + * GT_UC_STATIC - static unicast entry. + * + * Note: Please refer to the device datasheet for detailed unicast entry states + * that are supported by the device. + */ +typedef enum +{ + GT_UC_INVALID = 0, + GT_UC_DYNAMIC = 0x1, + + GT_UC_NO_PRI_TO_CPU_STATIC_NRL = 0x8, + GT_UC_TO_CPU_STATIC_NRL = 0x9, + GT_UC_NO_PRI_STATIC_NRL = 0xA, + GT_UC_NO_PRI_STATIC_AVB_ENTRY = 0xA, + GT_UC_STATIC_NRL = 0xB, + GT_UC_STATIC_AVB_ENTRY = 0xB, + + GT_UC_NO_PRI_TO_CPU_STATIC = 0xC, + GT_UC_TO_CPU_STATIC = 0xD, + GT_UC_NO_PRI_STATIC = 0xE, + GT_UC_STATIC = 0xF +} GT_ATU_UC_STATE; + + +/* + * typedef: enum GT_ATU_MC_STATE + * + * Description: + * Enumeration of the address translation unit entry state of multicast + * entris. + * + * Enumerations: + * GT_MC_INVALID - invalid entry. + * GT_MC_MGM_STATIC - static multicast management entries. + * GT_MC_STATIC - static multicast regular entris. + * GT_MC_STATIC_AVB_ENTRY- static AVB entry if MacAvb is enalbed. + * GT_MC_PRIO_MGM_STATIC - static multicast management entries with + * priority. + * GT_MC_PRIO_STATIC - static multicast regular entris with priority. + * GT_MC_PRIO_STATIC_AVB_ENTRY - static multicast AVB Entry with priority if MacAvb is enabled + * GT_MC_PRIO_STATIC_UNLIMITED_RATE - static multicast regular entris with priority + * and without rate limiting. + * GT_MC_MGM_STATIC_UNLIMITED_RATE - static multicast management entries without + * rate limiting. + * GT_MC_STATIC_UNLIMITED_RATE - static multicast regular entris without + * rate limiting. + * GT_MC_PRIO_MGM_STATIC_UNLIMITED_RATE - static multicast management entries with + * priority and without rate limiting. + * + * Note: Please refer to the device datasheet for detailed multicast entry states + * that are supported by the device. + */ +typedef enum +{ + GT_MC_INVALID = 0, + GT_MC_MGM_STATIC_UNLIMITED_RATE = 0x4, + GT_MC_STATIC_UNLIMITED_RATE = 0x5, + GT_MC_STATIC_AVB_ENTRY = 0x5, + GT_MC_MGM_STATIC = 0x6, + GT_MC_STATIC = 0x7, + GT_MC_PRIO_MGM_STATIC_UNLIMITED_RATE = 0xC, + GT_MC_PRIO_STATIC_UNLIMITED_RATE = 0xD, + GT_MC_PRIO_STATIC_AVB_ENTRY = 0xD, + GT_MC_PRIO_MGM_STATIC = 0xE, + GT_MC_PRIO_STATIC = 0xF +} GT_ATU_MC_STATE; + + +/* + * typedef: struct GT_ATU_EXT_PRI + * + * Description: + * Extanded priority information for the address tarnslaton unit entry. + * + * macFPri data is used to override the frame priority on any frame associated + * with this MAC, if the useMacFPri is GT_TRUE and the port's SA and/or + * DA FPriOverride are enabled. SA Frame Priority Overrides can only occur on + * MAC addresses that are Static or where the Port is Locked, and where the port + * is mapped source port for the MAC address. + * + * macQPri data is used to override the queue priority on any frame associated + * with this MAC, if the EntryState indicates Queue Priority Override and the + * port's SA and/or DA QPriOverride are enabled. + * + * Fields: + * useMacFPri - Use MAC frame priority override. When this is GT_TRUE, + * MacFPri data can be used to override the frame priority on + * any frame associated with this MAC. + * macFPri - MAC frame priority data (0 ~ 7). + * macQPri - MAC queue priority data (0 ~ 3). + * + * Comment: + * Please refer to the device datasheet to find out if this feature is supported. + * When this structure is implemented, the followings are the devices supporting + * this feature: + * 88E6065, 88E6035, and 88E6055 support all extanded priority data. + * 88E6061 and 88E6031 support only macQPri data + */ +typedef struct +{ + GT_BOOL useMacFPri; + GT_U8 macFPri; + GT_U8 macQPri; +} GT_ATU_EXT_PRI; + + +/* + * typedef: struct GT_ATU_ENTRY + * + * Description: address tarnslaton unit Entry + * + * Fields: + * macAddr - mac address + * trunkMember- GT_TRUE if entry belongs to a Trunk. This field will be + * ignored if device does not support Trunk. + * portVec - port Vector. + * If trunkMember field is GT_TRUE, this value represents trunk ID. + * prio - entry priority. + * entryState - the entry state. + * DBNum - ATU MAC Address Database number. If multiple address + * databases are not being used, DBNum should be zero. + * If multiple address databases are being used, this value + * should be set to the desired address database number. + * exPrio - extanded priority information. If device support extanded + * priority, prio field should be ignored. + * + * Comment: + * The entryState union Type is determine according to the Mac Type. + */ +typedef struct +{ + GT_ETHERADDR macAddr; + GT_BOOL trunkMember; + GT_U32 portVec; + GT_U8 prio; + GT_U8 reserved; + GT_U16 DBNum; + union + { + GT_ATU_UC_STATE ucEntryState; + GT_ATU_MC_STATE mcEntryState; + } entryState; + GT_ATU_EXT_PRI exPrio; +} GT_ATU_ENTRY; + + +/* + * typedef: struct GT_VTU_DATA + * + * Description: VLAN tarnslaton unit Data Register + * + * Fields: + * memberTagP - Membership and Egress Tagging + * memberTagP[0] is for Port 0, MemberTagP[1] is for port 1, and so on + * + * Comment: + * MAX_SWITCH_PORTS is 10 for Octane. + * In the case of FullSail, there are 3 ports. So, the rest 7 is ignored in memeberTagP + */ +typedef struct +{ + GT_U8 memberTagP[MAX_SWITCH_PORTS]; + GT_U8 portStateP[MAX_SWITCH_PORTS]; +} GT_VTU_DATA; + +/* + * definition for MEMBER_TAG + */ +#define MEMBER_EGRESS_UNMODIFIED 0 +#define NOT_A_MEMBER 1 +#define MEMBER_EGRESS_UNTAGGED 2 +#define MEMBER_EGRESS_TAGGED 3 + +/* + * typedef: struct GT_VTU_EXT_INFO + * + * Description: + * Extanded VTU Entry information for Priority Override and Non Rate Limit. + * Frame Priority is used to as the tag's PRI bits if the frame egresses + * the switch tagged. The egresss queue the frame is switch into is not + * modified by the Frame Priority Override. + * Queue Priority is used to determine the egress queue the frame is + * switched into. If the frame egresses tagged, the priority in the frame + * will not be modified by a Queue Priority Override. + * NonRateLimit for VID is used to indicate any frames associated with this + * VID are to bypass ingress and egress rate limiting, if the ingress + * port's VID NRateLimit is also enabled. + * + * Fields: + * useVIDFPri - Use VID frame priority override. When this is GT_TRUE and + * VIDFPriOverride of the ingress port of the frame is enabled, + * vidFPri data is used to override the frame priority on + * any frame associated with this VID. + * vidFPri - VID frame priority data (0 ~ 7). + * useVIDQPri - Use VID queue priority override. When this is GT_TRUE and + * VIDQPriOverride of the ingress port of the frame is enabled, + * vidQPri data can be used to override the queue priority on + * any frame associated with this VID. + * vidQPri - VID queue priority data (0 ~ 3). + * vidNRateLimit - bypass rate ingress and egress limiting + * + * Comment: + * Please refer to the device datasheet to find out if this feature is supported. + * When this structure is implemented, the followings are the devices supporting + * this feature: + * 88E6065, 88E6035, and 88E6055 support all data. + * 88E6061 and 88E6031 support only vidNRateLimit. + */ +typedef struct +{ + GT_BOOL useVIDFPri; + GT_U8 vidFPri; + GT_BOOL useVIDQPri; + GT_U8 vidQPri; + GT_BOOL vidNRateLimit; +} GT_VTU_EXT_INFO; + + +/* + * typedef: struct GT_VTU_ENTRY + * + * Description: VLAN tarnslaton unit Entry + * Each field in the structure is device specific, i.e., some fields may not + * be supported by the used switch device. In such case, those fields are + * ignored by the DSDT driver. Please refer to the datasheet for the list of + * supported fields. + * + * Fields: + * DBNum - database number or FID (forwarding information database) + * vid - VLAN ID + * vtuData - VTU data + * vidPriOverride - override the priority on any frame associated with this VID + * vidPriority - VID Priority bits (0 ~ 7) + * sid - 802.1s Port State Database ID + * vidPolicy - indicate that the frame with this VID uses VID Policy + * (see gprtSetPolicy API). + * vidExInfo - extanded information for VTU entry. If the device supports extanded + * information, vidPriorityOverride and vidPriority values are + * ignored. + */ +typedef struct +{ + GT_U16 DBNum; + GT_U16 vid; + GT_VTU_DATA vtuData; + GT_BOOL vidPriOverride; + GT_U8 vidPriority; + GT_U8 sid; + GT_BOOL vidPolicy; + GT_VTU_EXT_INFO vidExInfo; +} GT_VTU_ENTRY; + + +/* + * Typedef: enum GT_STU_OPERARION + * + * Description: Defines the STU operations + * + * Fields: + * LOAD_PURGE_STU_ENTRY - Load / Purge entry. + * GET_NEXT_STU_ENTRY - Get next STU entry. + * + */ +typedef enum +{ + LOAD_PURGE_STU_ENTRY = 5, + GET_NEXT_STU_ENTRY =6 +} GT_STU_OPERATION; + + +/* + * typedef: struct GT_STU_ENTRY + * + * Description: 802.1s Port State Information Database (STU) Entry + * + * Fields: + * sid - STU ID + * portState - Per VLAN Port States for each port. + */ +typedef struct +{ + GT_U16 sid; + GT_PORT_STP_STATE portState[MAX_SWITCH_PORTS]; +} GT_STU_ENTRY; + + +/* + * typedef: struct GT_VTU_INT_STATUS + * + * Description: VLAN tarnslaton unit interrupt status + * + * Fields: + * intCause - VTU Interrupt Cause + * GT_VTU_FULL_VIOLATION,GT_MEMEBER_VIOLATION,or + * GT_MISS_VIOLATION + * SPID - source port number + * if intCause is GT_VTU_FULL_VIOLATION, it means nothing + * vid - VLAN ID + * if intCause is GT_VTU_FULL_VIOLATION, it means nothing + */ +typedef struct +{ + GT_U16 vtuIntCause; + GT_U8 spid; + GT_U16 vid; +} GT_VTU_INT_STATUS; + +/* + * typedef: struct GT_ATU_INT_STATUS + * + * Description: VLAN tarnslaton unit interrupt status + * + * Fields: + * intCause - ATU Interrupt Cause + * GT_FULL_VIOLATION,GT_MEMEBER_VIOLATION, + * GT_MISS_VIOLATION, GT_AGE_VIOLATION, or + * GT_AGE_OUT_VIOLATION + * SPID - source port number + * if intCause is GT_FULL_VIOLATION, it means nothing + * DBNum - DB Num (or FID) + * if intCause is GT_FULL_VIOLATION, it means nothing + * macAddr - MAC Address + */ +typedef struct +{ + GT_U16 atuIntCause; + GT_U8 spid; + GT_U8 dbNum; + GT_ETHERADDR macAddr; +} GT_ATU_INT_STATUS; + +/* +* Definition for VTU interrupt +*/ +#define GT_MEMBER_VIOLATION 0x4 +#define GT_MISS_VIOLATION 0x2 +#define GT_VTU_FULL_VIOLATION 0x1 +/* +* Definitions for ATU interrupt in Gigabit switch are the same as +* the ones for VTU interrupt. Here we just redefine the FULL_VIOLATION for +* both VTU and ATU. +*/ +#define GT_FULL_VIOLATION 0x1 + +#define GT_AGE_VIOLATION 0x8 +#define GT_AGE_OUT_VIOLATION 0x10 + + +/* + * Typedef: enum GT_PVT_OPERATION + * + * Description: Defines the PVT (Cross Chip Port VLAN Table) Operation type + * + * Fields: + * PVT_INITIALIZE - Initialize all resources to the inital state + * PVT_WRITE - Write to the selected PVT entry + * PVT_READ - Read from the selected PVT entry + */ +typedef enum +{ + PVT_INITIALIZE = 0x1, + PVT_WRITE = 0x3, + PVT_READ = 0x4 +} GT_PVT_OPERATION; + + +/* + * typedef: struct GT_PVT_OP_DATA + * + * Description: data required by PVT (Cross Chip Port VLAN Table) Operation + * + * Fields: + * pvtAddr - pointer to the desired entry of PVT + * pvtData - Cross Chip Port VLAN data for the entry pointed by pvtAddr + */ +typedef struct +{ + GT_U32 pvtAddr; + GT_U32 pvtData; +} GT_PVT_OP_DATA; + + +/* + * typedef: enum GT_PIRL_FC_DEASSERT + * + * Description: Enumeration of the port flow control de-assertion mode on PIRL. + * + * Enumerations: + * GT_PIRL_FC_DEASSERT_EMPTY - + * De-assert when the ingress rate resource has become empty + * GT_PIRL_FC_DEASSERT_CBS_LIMIT - + * De-assert when the ingress rate resource has enough room as + * specified by the CBSLimit. + */ +typedef enum +{ + GT_PIRL_FC_DEASSERT_EMPTY = 0, + GT_PIRL_FC_DEASSERT_CBS_LIMIT +} GT_PIRL_FC_DEASSERT; + + +/* + * typedef: enum GT_PIRL_ELIMIT_MODE + * + * Description: Enumeration of the port egress rate limit counting mode. + * + * Enumerations: + * GT_PIRL_ELIMIT_FRAME - + * Count the number of frames + * GT_PIRL_ELIMIT_LAYER1 - + * Count all Layer 1 bytes: + * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes) + * GT_PIRL_ELIMIT_LAYER2 - + * Count all Layer 2 bytes: Frame's DA to CRC + * GT_PIRL_ELIMIT_LAYER3 - + * Count all Layer 3 bytes: + * Frame's DA to CRC - 18 - 4 (if frame is tagged) + */ +typedef enum +{ + GT_PIRL_ELIMIT_FRAME = 0, + GT_PIRL_ELIMIT_LAYER1, + GT_PIRL_ELIMIT_LAYER2, + GT_PIRL_ELIMIT_LAYER3 +} GT_PIRL_ELIMIT_MODE; + + +/* typedef: enum GT_RATE_LIMIT_MODE + * The ingress limit mode in the rate control register (0xA) + */ + +typedef enum +{ + GT_LIMT_ALL = 0, /* limit and count all frames */ + GT_LIMIT_FLOOD, /* limit and count Broadcast, Multicast and flooded unicast frames */ + GT_LIMIT_BRDCST_MLTCST, /* limit and count Broadcast and Multicast frames */ + GT_LIMIT_BRDCST /* limit and count Broadcast frames */ +} GT_RATE_LIMIT_MODE; + +/* typedef: enum GT_PRI0_RATE + * The ingress data rate limit for priority 0 frames + */ + +typedef enum +{ + GT_NO_LIMIT = 0, /* Not limited */ + GT_128K, /* 128K bits/sec */ + GT_256K, /* 256K bits/sec */ + GT_512K, /* 512 bits/sec */ + GT_1M, /* 1M bits/sec */ + GT_2M, /* 2M bits/sec */ + GT_4M, /* 4M bits/sec */ + GT_8M, /* 8M bits/sec */ + GT_16M, /* 16M bits/sec, Note: supported only by Gigabit Ethernet Switch */ + GT_32M, /* 32M bits/sec, Note: supported only by Gigabit Ethernet Switch */ + GT_64M, /* 64M bits/sec, Note: supported only by Gigabit Ethernet Switch */ + GT_128M, /* 128M bits/sec, Note: supported only by Gigabit Ethernet Switch */ + GT_256M /* 256M bits/sec, Note: supported only by Gigabit Ethernet Switch */ +} GT_PRI0_RATE,GT_EGRESS_RATE; + + +/* + * Typedef: union GT_ERATE_TYPE + * + * Description: Egress Rate + * + * Fields: + * definedRate - GT_EGRESS_RATE enum type should be used on the following devices: + * 88E6218, 88E6318, 88E6063, 88E6083, 88E6181, 88E6183, 88E6093 + * 88E6095, 88E6185, 88E6108, 88E6065, 88E6061, and their variations. + * kbRate - rate in kbps that should be used on the following devices: + * 88E6097, 88E6096 with count mode of non frame, such as + * ALL_LAYER1, ALL_LAYER2, and ALL_LAYER3 + * 64kbps ~ 1Mbps : increments of 64kbps, + * 1Mbps ~ 100Mbps : increments of 1Mbps, and + * 100Mbps ~ 1000Mbps: increments of 10Mbps + * Therefore, the valid values are: + * 64, 128, 192, 256, 320, 384,..., 960, + * 1000, 2000, 3000, 4000, ..., 100000, + * 110000, 120000, 130000, ..., 1000000. + * fRate - frame per second that should be used on the following devices: + * 88E6097, 88E6096 with count mode of frame (GT_PIRL_COUNT_FRAME) + */ +typedef union +{ + GT_EGRESS_RATE definedRate; + GT_U32 kbRate; + GT_U32 fRate; +} GT_ERATE_TYPE; + +/* + * Formula for Rate Limit of Gigabit Switch family and Enhanced FastEthernet Switch + */ +#define GT_GET_RATE_LIMIT(_kbps) \ + ((_kbps)?(8000000 / (28 * (_kbps))):0) +#define GT_GET_RATE_LIMIT2(_kbps) \ + ((_kbps)?(8000000 / (32 * (_kbps)) + (8000000 % (32 * (_kbps))?1:0)):0) +#define GT_GET_RATE_LIMIT3(_kbps) \ + ((_kbps)?(8000000 / (40 * (_kbps)) + (8000000 % (40 * (_kbps))?1:0)):0) + +#define MAX_RATE_LIMIT 256000 /* unit of Kbps */ +#define MIN_RATE_LIMIT 65 /* unit of Kbps */ + + +#define GT_GET_RATE_LIMIT_PER_FRAME(_frames, _dec) \ + ((_frames)?(1000000000 / (32 * (_frames)) + (1000000000 % (32 * (_frames))?1:0)):0) + +#define GT_GET_RATE_LIMIT_PER_BYTE(_kbps, _dec) \ + ((_kbps)?((8000000*(_dec)) / (32 * (_kbps)) + ((8000000*(_dec)) % (32 * (_kbps))?1:0)):0) + +/* + * typedef: enum GT_BURST_SIZE + * The ingress data rate limit burst size windows selection + */ + +typedef enum +{ + GT_BURST_SIZE_12K = 0, /* 12K byte burst size */ + GT_BURST_SIZE_24K, /* 24K byte burst size */ + GT_BURST_SIZE_48K, /* 48K byte burst size */ + GT_BURST_SIZE_96K /* 96K byte burst size */ +} GT_BURST_SIZE; + +/* + * typedef: enum GT_BURST_RATE + * The ingress data rate limit based on burst size + */ + +typedef enum +{ + GT_BURST_NO_LIMIT = 0, /* Not limited */ + GT_BURST_64K, /* 64K bits/sec */ + GT_BURST_128K, /* 128K bits/sec */ + GT_BURST_256K, /* 256K bits/sec */ + GT_BURST_384K, /* 384K bits/sec */ + GT_BURST_512K, /* 512 bits/sec */ + GT_BURST_640K, /* 640K bits/sec */ + GT_BURST_768K, /* 768K bits/sec */ + GT_BURST_896K, /* 896K bits/sec */ + GT_BURST_1M, /* 1M bits/sec */ + GT_BURST_1500K, /* 1.5M bits/sec */ + GT_BURST_2M, /* 2M bits/sec */ + GT_BURST_4M, /* 4M bits/sec */ + GT_BURST_8M, /* 8M bits/sec */ + GT_BURST_16M, /* 16M bits/sec */ + GT_BURST_32M, /* 32M bits/sec */ + GT_BURST_64M, /* 64M bits/sec */ + GT_BURST_128M, /* 128M bits/sec */ + GT_BURST_256M /* 256M bits/sec */ +} GT_BURST_RATE; + +/* + * Formula for burst based Rate Limit + */ +#define GT_GET_BURST_RATE_LIMIT(_bsize,_kbps) \ + ((_kbps)?(((_bsize)+1)*8000000 / (32 * (_kbps)) + \ + (((_bsize)+1)*8000000 % (32 * (_kbps))?1:0)) \ + :0) + +/* + * Typedef: enum GT_PIRL_OPERATION + * + * Description: Defines the PIRL (Port Ingress Rate Limit) Operation type + * + * Fields: + * PIRL_INIT_ALL_RESOURCE - Initialize all resources to the inital state + * PIRL_INIT_RESOURCE - Initialize selected resources to the inital state + * PIRL_WRITE_RESOURCE - Write to the selected resource/register + * PIRL_READ_RESOURCE - Read from the selected resource/register + */ +typedef enum +{ + PIRL_INIT_ALL_RESOURCE = 0x1, + PIRL_INIT_RESOURCE = 0x2, + PIRL_WRITE_RESOURCE = 0x3, + PIRL_READ_RESOURCE = 0x4 +} GT_PIRL_OPERATION, GT_PIRL2_OPERATION; + + +/* + * typedef: struct GT_PIRL_OP_DATA + * + * Description: data required by PIRL Operation + * + * Fields: + * irlUnit - Ingress Rate Limit Unit that defines one of IRL resources. + * irlReg - Ingress Rate Limit Register. + * irlData - Ingress Rate Limit Data. + */ +typedef struct +{ + GT_U32 irlUnit; + GT_U32 irlReg; + GT_U32 irlData; +} GT_PIRL_OP_DATA; + +/* + * typedef: struct GT_PIRL2_OP_DATA + * + * Description: data required by PIRL Operation + * + * Fields: + * irlPort - Ingress Rate Limiting port (physical port number). + * irlRes - Ingress Rate Limit Resource. + * irlReg - Ingress Rate Limit Register. + * irlData - Ingress Rate Limit Data. + */ +typedef struct +{ + GT_U32 irlPort; + GT_U32 irlRes; + GT_U32 irlReg; + GT_U32 irlData; +} GT_PIRL2_OP_DATA; + +/* + * Typedef: enum GT_PIRL_ACTION + * + * Description: Defines the Action that should be taken when + * there there are not enough tokens to accept the entire incoming frame + * + * Fields: + * PIRL_ACTION_ACCEPT - accept the frame + * PIRL_ACTION_USE_LIMIT_ACTION - use ESB Limit Action + */ +typedef enum +{ + PIRL_ACTION_USE_LIMIT_ACTION = 0x0, + PIRL_ACTION_ACCEPT = 0x1 +} GT_PIRL_ACTION; + +/* + * Typedef: enum GT_ESB_LIMIT_ACTION + * + * Description: Defines the ESB Limit Action that should be taken when + * the incoming port information rate exceeds the EBS_Limit. + * + * Fields: + * ESB_LIMIT_ACTION_DROP - drop packets + * ESB_LIMIT_ACTION_FC - send flow control packet + */ +typedef enum +{ + ESB_LIMIT_ACTION_DROP = 0x0, + ESB_LIMIT_ACTION_FC = 0x1 +} GT_ESB_LIMIT_ACTION; + + +/* + * Typedef: enum GT_BUCKET_RATE_TYPE + * + * Description: Defines the Bucket Rate Type + * + * Fields: + * BUCKET_TYPE_TRAFFIC_BASED - bucket is traffic type based + * BUCKET_TYPE_RATE_BASED - bucket is rate based + */ +typedef enum +{ + BUCKET_TYPE_TRAFFIC_BASED = 0x0, + BUCKET_TYPE_RATE_BASED = 0x1 +} GT_BUCKET_RATE_TYPE; + +/* + * Definition for GT_BUCKET_TYPE_TRAFFIC_BASED + * + * Description: Defines the Traffic Type that is used when Bucket Rate Type + * is traffic type based (BUCKET_TYPE_TRAFFIC_BASED). + * Please refer to the device datasheet in order to check which traffic + * types are supported. + * + * Definition: + * BUCKET_TRAFFIC_UNKNOWN_UNICAST - unknown unicast frame + * BUCKET_TRAFFIC_UNKNOWN_MULTICAST- unknown multicast frame + * BUCKET_TRAFFIC_BROADCAST - broadcast frame + * BUCKET_TRAFFIC_MULTICAST - multicast frame + * BUCKET_TRAFFIC_UNICAST - unicast frame + * BUCKET_TRAFFIC_MGMT_FRAME - management frame + * BUCKET_TRAFFIC_ARP - arp frame + * BUCKET_TRAFFIC_TCP_DATA - TCP Data + * BUCKET_TRAFFIC_TCP_CTRL - TCP Ctrl (if any of the TCP Flags[5:0] are set) + * BUCKET_TRAFFIC_UDP - UDP + * BUCKET_TRAFFIC_NON_TCPUDP - covers IGMP,ICMP,GRE,IGRP,L2TP + * BUCKET_TRAFFIC_IMS - Ingress Monitor Source + * BUCKET_TRAFFIC_POLICY_MIRROR - Policy Mirror + * BUCKET_TRAFFIC_PLICY_TRAP - Policy Trap + */ +#define BUCKET_TRAFFIC_UNKNOWN_UNICAST 0x01 +#define BUCKET_TRAFFIC_UNKNOWN_MULTICAST 0x02 +#define BUCKET_TRAFFIC_BROADCAST 0x04 +#define BUCKET_TRAFFIC_MULTICAST 0x08 +#define BUCKET_TRAFFIC_UNICAST 0x10 +#define BUCKET_TRAFFIC_MGMT_FRAME 0x20 +#define BUCKET_TRAFFIC_ARP 0x40 +#define BUCKET_TRAFFIC_TCP_DATA 0x100 +#define BUCKET_TRAFFIC_TCP_CTRL 0x200 +#define BUCKET_TRAFFIC_UDP 0x400 +#define BUCKET_TRAFFIC_NON_TCPUDP 0x800 +#define BUCKET_TRAFFIC_IMS 0x1000 +#define BUCKET_TRAFFIC_POLICY_MIRROR 0x2000 +#define BUCKET_TRAFFIC_PLICY_TRAP 0x4000 + +/* + * typedef: enum GT_PIRL_COUNT_MODE + * + * Description: Enumeration of the port egress rate limit counting mode. + * + * Enumerations: + * GT_PIRL_COUNT_ALL_LAYER1 - + * Count all Layer 1 bytes: + * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes) + * GT_PIRL_COUNT_ALL_LAYER2 - + * Count all Layer 2 bytes: Frame's DA to CRC + * GT_PIRL_COUNT_ALL_LAYER3 - + * Count all Layer 3 bytes: + * Frame's DA to CRC - 18 - 4 (if frame is tagged) + */ +typedef enum +{ + GT_PIRL_COUNT_ALL_LAYER1 = 0, + GT_PIRL_COUNT_ALL_LAYER2, + GT_PIRL_COUNT_ALL_LAYER3 +} GT_PIRL_COUNT_MODE; + +/* + * typedef: enum GT_PIRL2_COUNT_MODE + * + * Description: Enumeration of the port egress rate limit counting mode. + * + * Enumerations: + * GT_PIRL2_COUNT_FRAME - + * Count the number of frames + * GT_PIRL2_COUNT_ALL_LAYER1 - + * Count all Layer 1 bytes: + * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes) + * GT_PIRL2_COUNT_ALL_LAYER2 - + * Count all Layer 2 bytes: Frame's DA to CRC + * GT_PIRL2_COUNT_ALL_LAYER3 - + * Count all Layer 3 bytes: + * Frame's DA to CRC - 18 - 4 (if frame is tagged) + */ +typedef enum +{ + GT_PIRL2_COUNT_FRAME = 0, + GT_PIRL2_COUNT_ALL_LAYER1, + GT_PIRL2_COUNT_ALL_LAYER2, + GT_PIRL2_COUNT_ALL_LAYER3 +} GT_PIRL2_COUNT_MODE; + + + +/* + * typedef: struct GT_PIRL_RESOURCE + * + * Description: data structure that represents a PIRL Resource + * + * Fields: + * accountQConf - account discarded frames due to queue congestion + * accountFiltered - account filtered frames + * ebsLimitAction - action should be taken when the incoming rate exceeds + * the ebsLimit. + * ESB_LIMIT_ACTION_DROP - drop packets + * ESB_LIMIT_ACTION_FC - send flow control packet + * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF) + * cbsLimit - Committed BUrst Size limit (expected to be 2kBytes) + * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval, + * where updateInterval indicates the rate at which the + * bucket needs to be updated with tokens, or 1/CIR, + * where CIR is the committed information rate in kbps. + * bucketDecrement indicates the amount of tokens that + * need to be removed per each bucket decrement. + * bktIncrement - the amount of tokens that need to be added for each + * byte of packet information. + * bktRateType - bucket is either rate based or traffic type based. + * BUCKET_TYPE_RATE_BASED, or + * BUCKET_TYPE_TRAFFIC_BASED + * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED. + * any combination of the following definitions: + * BUCKET_TRAFFIC_UNKNOWN_UNICAST, + * BUCKET_TRAFFIC_UNKNOWN_MULTICAST, + * BUCKET_TRAFFIC_BROADCAST, + * BUCKET_TRAFFIC_MULTICAST, + * BUCKET_TRAFFIC_UNICAST, + * BUCKET_TRAFFIC_MGMT_FRAME, and + * BUCKET_TRAFFIC_ARP + * byteTobeCounted - bytes to be counted for accounting + * GT_PIRL_COUNT_ALL_LAYER1, + * GT_PIRL_COUNT_ALL_LAYER2, or + * GT_PIRL_COUNT_ALL_LAYER3 + * + */ +typedef struct +{ + GT_BOOL accountQConf; + GT_BOOL accountFiltered; + GT_ESB_LIMIT_ACTION ebsLimitAction; + GT_U32 ebsLimit; + GT_U32 cbsLimit; + GT_U32 bktRateFactor; + GT_U32 bktIncrement; + GT_BUCKET_RATE_TYPE bktRateType; + GT_U32 bktTypeMask; + GT_PIRL_COUNT_MODE byteTobeCounted; +} GT_PIRL_RESOURCE; + +/* + * typedef: struct GT_PIRL_CUSTOM_RATE_LIMIT + * + * Description: The parameters that decides Ingress Rate Limit vary depending on + * the application. Since DSDT driver cannot cover all the cases, + * this structure is provided for the custom parameter setting. + * However, in most cases, user may ingore this structure by setting + * isValid to GT_FALSE. If Ingress Rate Limit is too much off from + * the expected rate, please contact FAE and gets the correct ebsLimit, + * cbsLimit,bktIncrement, and bktRateFactor value and use this structure + * to do custom parameter setting. + * + * isValid - If GT_TRUE, the paramers in this structure are used + * to program PIRL Resource's Rate Limit. And ingressRate + * in GT_PIRL_BUCKET_DATA structure are ignored. + * If GT_FALSE, ingressRate in GT_PIRL_BUCKET_DATA structure + * is used for Resource's Rate Limit. + * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF) + * cbsLimit - Committed Burst Size limit (expected to be 2kBytes) + * bktIncrement - the amount of tokens that need to be added for each + * byte of packet information. + * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval, + * where updateInterval indicates the rate at which the + * bucket needs to be updated with tokens, or 1/CIR, + * where CIR is the committed information rate in kbps. + * bucketDecrement indicates the amount of tokens that + * need to be removed per each bucket decrement. +*/ +typedef struct +{ + GT_BOOL isValid; + GT_U32 ebsLimit; + GT_U32 cbsLimit; + GT_U32 bktIncrement; + GT_U32 bktRateFactor; +} GT_PIRL_CUSTOM_RATE_LIMIT; + +/* + * typedef: struct GT_PIRL_BUCKET_DATA + * + * Description: data structure for PIRL Bucket programing that is resource based + * + * Fields: + * ingressRate - commited ingress rate in kbps. + * 64kbps ~ 1Mbps : increments of 64kbps, + * 1Mbps ~ 100Mbps : increments of 1Mbps, and + * 100Mbps ~ 200Mbps : increments of 10Mbps + * Therefore, the valid values are: + * 64, 128, 192, 256, 320, 384,..., 960, + * 1000, 2000, 3000, 4000, ..., 100000, + * 110000, 120000, 130000, ..., 200000. + * customSetup - custom ingress rate parameter setup. please refer to + * GT_PIRL_CUSTOM_RATE_LIMIT structure. + * accountQConf - account discarded frames due to queue congestion + * accountFiltered - account filtered frames + * esbLimitAction - action should be taken when the incoming rate exceeds + * the limit. + * ESB_LIMIT_ACTION_DROP - drop packets + * ESB_LIMIT_ACTION_FC - send flow control packet + * fcDeassertMode - port flow control de-assertion mode when limitAction is + * set to ESB_LIMIT_ACTION_FC. + * fcDeassertMode[0] for port 0, fcDeassertMode[1] for + * port 1, etc. If port x does not share the bucket, + * fcDeassertMode[x] data will be ignored. + * GT_PIRL_FC_DEASSERT_EMPTY - + * De-assert when the ingress rate resource has + * become empty. + * GT_PIRL_FC_DEASSERT_CBS_LIMIT - + * De-assert when the ingress rate resource has + * enough room as specified by the CBSLimit. + * bktRateType - bucket is either rate based or traffic type based. + * BUCKET_TYPE_RATE_BASED, or + * BUCKET_TYPE_TRAFFIC_BASED + * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED. + * any combination of the following definitions: + * BUCKET_TRAFFIC_UNKNOWN_UNICAST, + * BUCKET_TRAFFIC_UNKNOWN_MULTICAST, + * BUCKET_TRAFFIC_BROADCAST, + * BUCKET_TRAFFIC_MULTICAST, + * BUCKET_TRAFFIC_UNICAST, + * BUCKET_TRAFFIC_MGMT_FRAME, and + * BUCKET_TRAFFIC_ARP + * byteTobeCounted - bytes to be counted for accounting + * GT_PIRL_COUNT_ALL_LAYER1, + * GT_PIRL_COUNT_ALL_LAYER2, or + * GT_PIRL_COUNT_ALL_LAYER3 + * + */ +typedef struct +{ + GT_U32 ingressRate; + GT_PIRL_CUSTOM_RATE_LIMIT customSetup; + GT_BOOL accountQConf; + GT_BOOL accountFiltered; + GT_ESB_LIMIT_ACTION ebsLimitAction; + GT_PIRL_FC_DEASSERT fcDeassertMode[MAX_SWITCH_PORTS]; + GT_BUCKET_RATE_TYPE bktRateType; + GT_U32 bktTypeMask; + GT_PIRL_COUNT_MODE byteTobeCounted; +} GT_PIRL_DATA; + + +/* + * typedef: struct GT_PIRL2_RESOURCE + * + * Description: data structure that represents a PIRL Resource + * + * Fields: + * accountQConf - account discarded frames due to queue congestion + * accountFiltered - account filtered frames + * mgmtNrlEn - exclude management frame from ingress rate limiting calculation + * saNrlEn - exclude from ingress rate limiting calculation if the SA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * daNrlEn - exclude from ingress rate limiting calculation if the DA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * samplingMode - sample one out of so many frames/bytes for a stream of frames + * actionMode - action should be taken when there are not enough tokens + * to accept the entire incoming frame + * PIRL_ACTION_ACCEPT - accept the frame + * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction + * ebsLimitAction - action should be taken when the incoming rate exceeds + * the ebsLimit. + * ESB_LIMIT_ACTION_DROP - drop packets + * ESB_LIMIT_ACTION_FC - send flow control packet + * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF) + * cbsLimit - Committed BUrst Size limit (expected to be 2kBytes) + * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval, + * where updateInterval indicates the rate at which the + * bucket needs to be updated with tokens, or 1/CIR, + * where CIR is the committed information rate in kbps. + * bucketDecrement indicates the amount of tokens that + * need to be removed per each bucket decrement. + * bktIncrement - the amount of tokens that need to be added for each + * byte of packet information. + * fcDeassertMode - flow control de-assertion mode when limitAction is + * set to ESB_LIMIT_ACTION_FC. + * GT_PIRL_FC_DEASSERT_EMPTY - + * De-assert when the ingress rate resource has + * become empty. + * GT_PIRL_FC_DEASSERT_CBS_LIMIT - + * De-assert when the ingress rate resource has + * enough room as specified by the CBSLimit. + * bktRateType - bucket is either rate based or traffic type based. + * BUCKET_TYPE_RATE_BASED, or + * BUCKET_TYPE_TRAFFIC_BASED + * priORpt - determine the incoming frames that get rate limited using + * this ingress rate resource. + * GT_TRUE - typeMask OR priMask + * GT_FALSE - typeMask AND priMask + * priMask - priority bit mask that each bit indicates one of the four + * queue priorities. Setting each one of these bits indicates + * that this particular rate resource is slated to account for + * incoming frames with the enabled bits' priority. + * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED. + * any combination of the following definitions: + * BUCKET_TRAFFIC_UNKNOWN_UNICAST, + * BUCKET_TRAFFIC_UNKNOWN_MULTICAST, + * BUCKET_TRAFFIC_BROADCAST, + * BUCKET_TRAFFIC_MULTICAST, + * BUCKET_TRAFFIC_UNICAST, + * BUCKET_TRAFFIC_MGMT_FRAME, + * BUCKET_TRAFFIC_ARP, + * BUCKET_TRAFFIC_TCP_DATA, + * BUCKET_TRAFFIC_TCP_CTRL, + * BUCKET_TRAFFIC_UDP, + * BUCKET_TRAFFIC_NON_TCPUDP, + * BUCKET_TRAFFIC_IMS, + * BUCKET_TRAFFIC_POLICY_MIRROR, and + * BUCKET_TRAFFIC_PLICY_TRAP + * byteTobeCounted - bytes to be counted for accounting + * GT_PIRL2_COUNT_FRAME, + * GT_PIRL2_COUNT_ALL_LAYER1, + * GT_PIRL2_COUNT_ALL_LAYER2, or + * GT_PIRL2_COUNT_ALL_LAYER3 + * + */ +typedef struct +{ + GT_BOOL accountQConf; + GT_BOOL accountFiltered; + GT_BOOL mgmtNrlEn; + GT_BOOL saNrlEn; + GT_BOOL daNrlEn; + GT_BOOL samplingMode; + GT_PIRL_ACTION actionMode; + GT_ESB_LIMIT_ACTION ebsLimitAction; + GT_U32 ebsLimit; + GT_U32 cbsLimit; + GT_U32 bktRateFactor; + GT_U32 bktIncrement; + GT_PIRL_FC_DEASSERT fcDeassertMode; + GT_BUCKET_RATE_TYPE bktRateType; + GT_BOOL priORpt; + GT_U32 priMask; + GT_U32 bktTypeMask; + GT_PIRL2_COUNT_MODE byteTobeCounted; +} GT_PIRL2_RESOURCE; + + +/* + * typedef: struct GT_PIRL2_BUCKET_DATA + * + * Description: data structure for PIRL2 Bucket programing that is port based. + * + * Fields: + * ingressRate - commited ingress rate in kbps. + * 64kbps ~ 1Mbps : increments of 64kbps, + * 1Mbps ~ 100Mbps : increments of 1Mbps, and + * 100Mbps ~ 200Mbps : increments of 10Mbps + * Therefore, the valid values are: + * 64, 128, 192, 256, 320, 384,..., 960, + * 1000, 2000, 3000, 4000, ..., 100000, + * 110000, 120000, 130000, ..., 200000. + * customSetup - custom ingress rate parameter setup. please refer to + * GT_PIRL_CUSTOM_RATE_LIMIT structure. + * accountQConf - account discarded frames due to queue congestion + * accountFiltered - account filtered frames + * mgmtNrlEn - exclude management frame from ingress rate limiting calculation + * saNrlEn - exclude from ingress rate limiting calculation if the SA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * daNrlEn - exclude from ingress rate limiting calculation if the DA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * samplingMode - sample one out of so many frames/bytes for a stream of frames + * actionMode - action should be taken when there are not enough tokens + * to accept the entire incoming frame + * PIRL_ACTION_ACCEPT - accept the frame + * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction + * ebsLimitAction - action should be taken when the incoming rate exceeds + * the limit. + * ESB_LIMIT_ACTION_DROP - drop packets + * ESB_LIMIT_ACTION_FC - send flow control packet + * fcDeassertMode - flow control de-assertion mode when limitAction is + * set to ESB_LIMIT_ACTION_FC. + * GT_PIRL_FC_DEASSERT_EMPTY - + * De-assert when the ingress rate resource has + * become empty. + * GT_PIRL_FC_DEASSERT_CBS_LIMIT - + * De-assert when the ingress rate resource has + * enough room as specified by the CBSLimit. + * bktRateType - bucket is either rate based or traffic type based. + * BUCKET_TYPE_RATE_BASED, or + * BUCKET_TYPE_TRAFFIC_BASED + * priORpt - determine the incoming frames that get rate limited using + * this ingress rate resource. + * GT_TRUE - typeMask OR priMask + * GT_FALSE - typeMask AND priMask + * priMask - priority bit mask that each bit indicates one of the four + * queue priorities. Setting each one of these bits indicates + * that this particular rate resource is slated to account for + * incoming frames with the enabled bits' priority. + * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED. + * any combination of the following definitions: + * BUCKET_TRAFFIC_UNKNOWN_UNICAST, + * BUCKET_TRAFFIC_UNKNOWN_MULTICAST, + * BUCKET_TRAFFIC_BROADCAST, + * BUCKET_TRAFFIC_MULTICAST, + * BUCKET_TRAFFIC_UNICAST, + * BUCKET_TRAFFIC_MGMT_FRAME, + * BUCKET_TRAFFIC_ARP, + * BUCKET_TRAFFIC_TCP_DATA, + * BUCKET_TRAFFIC_TCP_CTRL, + * BUCKET_TRAFFIC_UDP, + * BUCKET_TRAFFIC_NON_TCPUDP, + * BUCKET_TRAFFIC_IMS, + * BUCKET_TRAFFIC_POLICY_MIRROR, and + * BUCKET_TRAFFIC_PLICY_TRAP + * byteTobeCounted - bytes to be counted for accounting + * GT_PIRL2_COUNT_FRAME, + * GT_PIRL2_COUNT_ALL_LAYER1, + * GT_PIRL2_COUNT_ALL_LAYER2, or + * GT_PIRL2_COUNT_ALL_LAYER3 + * + */ +typedef struct +{ + GT_U32 ingressRate; + GT_PIRL_CUSTOM_RATE_LIMIT customSetup; + GT_BOOL accountQConf; + GT_BOOL accountFiltered; + GT_BOOL mgmtNrlEn; + GT_BOOL saNrlEn; + GT_BOOL daNrlEn; + GT_BOOL samplingMode; + GT_PIRL_ACTION actionMode; + GT_ESB_LIMIT_ACTION ebsLimitAction; + GT_PIRL_FC_DEASSERT fcDeassertMode; + GT_BUCKET_RATE_TYPE bktRateType; + GT_BOOL priORpt; + GT_U32 priMask; + GT_U32 bktTypeMask; + GT_PIRL2_COUNT_MODE byteTobeCounted; +} GT_PIRL2_DATA; + + + +/* + * typedef: struct GT_PIRL_CUSTOM_TSM_CFG + * + * Description: The parameters that decides Ingress Rate Limit for AVB frames vary + * depending on the application. Since DSDT driver cannot cover all the cases, + * this structure is provided for the custom parameter setting. + * However, in most cases, user may ingore this structure by setting + * isValid to GT_FALSE. If Ingress Rate Limit is too much off from + * the expected rate, please contact FAE and gets the correct ebsLimit, + * cbsLimit, CTS interval, and action mode value and use this structure + * to do custom parameter setting. + * + * isValid - If GT_TRUE, the paramers in this structure are used + * to program PIRL Resource's Rate Limit. And ingressRate + * in GT_PIRL_TSM_DATA structure are ignored. + * If GT_FALSE, ingressRate in GT_PIRL_TSM_DATA structure + * is used for Resource's Rate Limit. + * ebsLimit - Excess Burst Size limit (0 ~ 0xFFFF) + * cbsLimit - Committed Burst Size limit (0 ~ 0xFFFF) + * ctsIntv - Class Time Slot Interval + * 0 - interval is 62.5us + * 1 - interval is 125us + * 2 - interval is 250us + * 3 - interval is 1000us + * actionMode - action should be taken when there are not enough tokens + * to accept the entire incoming frame + * PIRL_ACTION_ACCEPT - accept the frame + * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction +*/ +typedef struct +{ + GT_BOOL isValid; + GT_U32 ebsLimit; + GT_U32 cbsLimit; + GT_U32 ctsIntv; + GT_PIRL_ACTION actionMode; +} GT_PIRL_CUSTOM_TSM_CFG; + + +/* + * typedef: struct GT_PIRL2_TSM_DATA + * + * Description: data structure for PIRL2 TSM Ingress Rate Limit. + * + * Fields: + * ebsLimit - Excess Burst Size limit (0 ~ 0xFFFF) + * cbsLimit - Committed Burst Size limit (0 ~ 0xFFFF) + * ctsIntv - Class Time Slot Interval + * 0 - interval is 62.5us + * 1 - interval is 125us + * 2 - interval is 250us + * 3 - interval is 1000us + * actionMode - action should be taken when there are not enough tokens + * to accept the entire incoming frame + * PIRL_ACTION_ACCEPT - accept the frame + * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction + * mgmtNrlEn - exclude management frame from ingress rate limiting calculation + * priMask - priority bit mask that each bit indicates one of the four + * queue priorities. Setting each one of these bits indicates + * that this particular rate resource is slated to account for + * incoming frames with the enabled bits' priority. + * + */ +typedef struct +{ + GT_BOOL tsmMode; + GT_U32 ebsLimit; + GT_U32 cbsLimit; + GT_U32 ctsIntv; + GT_PIRL_ACTION actionMode; + GT_BOOL mgmtNrlEn; + GT_U32 priMask; +} GT_PIRL2_TSM_RESOURCE; + + + +/* + * typedef: struct GT_PIRL2_TSM_DATA + * + * Description: data structure for PIRL2 TSM Ingress Rate Limit. + * + * Fields: + * tsmMode - enable/disable TSM mode. + * The following fields are ignored if diable + * ingressRate - commited ingress rate in kbps.(min 64 for 64kbps) + * customSetup - custom ingress rate parameter setup. please refer to + * GT_PIRL_CUSTOM_TSM_CFG structure. + * mgmtNrlEn - exclude management frame from ingress rate limiting calculation + * priMask - priority bit mask that each bit indicates one of the four + * queue priorities. Setting each one of these bits indicates + * that this particular rate resource is slated to account for + * incoming frames with the enabled bits' priority. + * + */ +typedef struct +{ + GT_BOOL tsmMode; + GT_U32 ingressRate; + GT_PIRL_CUSTOM_TSM_CFG customSetup; + GT_BOOL mgmtNrlEn; + GT_U32 priMask; +} GT_PIRL2_TSM_DATA; + + + +#define MAX_PTP_CONSECUTIVE_READ 4 + +/* + * Typedef: enum GT_PTP_OPERATION + * + * Description: Defines the PTP (Precise Time Protocol) Operation type + * + * Fields: + * PTP_WRITE_DATA - Write data to the PTP register + * PTP_READ_DATA - Read data from PTP register + * PTP_READ_MULTIPLE_DATA - Read multiple data from PTP register + * PTP_READ_TIMESTAMP_DATA - Read timestamp data from PTP register + * valid bit will be reset after read + */ +typedef enum +{ + PTP_WRITE_DATA = 0x3, + PTP_READ_DATA = 0x4, + PTP_READ_MULTIPLE_DATA = 0x6, + PTP_READ_TIMESTAMP_DATA = 0x8, +} GT_PTP_OPERATION; + + +/* + * Typedef: enum GT_PTP_SPEC + * + * Description: Defines the PTP (Precise Time Protocol) SPEC type + * + * Fields: + * PTP_IEEE_1588 - IEEE 1588 + * PTP_IEEE_802_1AS - IEEE 802.1as + */ +typedef enum +{ + PTP_IEEE_1588 = 0x0, + PTP_IEEE_802_1AS = 0x1 +} GT_PTP_SPEC; + + +/* + * typedef: struct GT_PTP_OP_DATA + * + * Description: data required by PTP Operation + * + * Fields: + * ptpPort - physical port of the device + * ptpAddr - register address + * ptpData - data for ptp register. + * ptpMultiData- used for multiple read operation. + * nData - number of data to be read on multiple read operation. + */ +typedef struct +{ + GT_U32 ptpPort; + GT_U32 ptpBlock; + GT_U32 ptpAddr; + GT_U32 ptpData; + GT_U32 ptpMultiData[MAX_PTP_CONSECUTIVE_READ]; + GT_U32 nData; +} GT_PTP_OP_DATA; + + +/* + * typedef: struct GT_PTP_CONFIG + * + * Description: PTP configuration parameters + * + * Fields: + * ptpEType - PTP Ether Type + * msgIdTSEn - Message IDs that needs time stamp + * tsArrPtr - Time stamp arrival time counter pointer (either Arr0Time or Arr1Time) + * ptpArrIntEn - PTP port arrival interrupt enable + * ptpDepIntEn - PTP port departure interrupt enable + * transSpec - This is to differentiate between various timing protocols. + * msgIdStartBit - Message ID starting bit in the PTP common header + * disTSOverwrite - disable time stamp counter overwriting until the corresponding + * timer valid bit is cleared. + */ +typedef struct +{ + GT_U32 ptpEType; + GT_U32 msgIdTSEn; + GT_U32 tsArrPtr; + GT_U32 ptpArrIntEn; + GT_U32 ptpDepIntEn; + GT_PTP_SPEC transSpec; + GT_U32 msgIdStartBit; + GT_BOOL disTSOverwrite; +} GT_PTP_CONFIG; + + +/* + * typedef: struct GT_PTP_GLOBAL_CONFIG + * + * Description: PTP global configuration parameters + * + * Fields: + * ptpEType - PTP Ether Type + * msgIdTSEn - Message IDs that needs time stamp + * tsArrPtr - Time stamp arrival time counter pointer (either Arr0Time or Arr1Time) + */ +typedef struct +{ + GT_U32 ptpEType; + GT_U32 msgIdTSEn; + GT_U32 tsArrPtr; +} GT_PTP_GLOBAL_CONFIG; + + +/* + * typedef: struct GT_PTP_PORT_CONFIG + * + * Description: PTP configuration parameters for each port + * + * Fields: + * transSpec - This is to differentiate between various timing protocols. + * disTSpec - Disable Transport specific check + * etJump - offset to Ether type start address in bytes + * ipJump - offset to IP header start address counting from Ether type offset + * ptpArrIntEn - PTP port arrival interrupt enable + * ptpDepIntEn - PTP port departure interrupt enable + * disTSOverwrite - disable time stamp counter overwriting until the corresponding + * timer valid bit is cleared. + */ +typedef struct +{ + GT_PTP_SPEC transSpec; + GT_BOOL disTSpec; + GT_U32 etJump; + GT_U32 ipJump; + GT_BOOL ptpArrIntEn; + GT_BOOL ptpDepIntEn; + GT_BOOL disTSOverwrite; +} GT_PTP_PORT_CONFIG; + + +/* + * Typedef: enum GT_PTP_TIME + * + * Description: Defines the PTP Time to be read + * + * Fields: + * PTP_WRITE_DATA - Write data to the PTP register + * PTP_READ_DATA - Read data from PTP register + * PTP_READ_MULTIPLE_DATA - Read multiple data from PTP register + */ +typedef enum +{ + PTP_ARR0_TIME = 0x0, + PTP_ARR1_TIME = 0x1, + PTP_DEP_TIME = 0x2 +} GT_PTP_TIME; + + +/* + * Typedef: enum GT_PTP_INT_STATUS + * + * Description: Defines the PTP Port interrupt status for time stamp + * + * Fields: + * PTP_INT_NORMAL - No error condition occurred + * PTP_INT_OVERWRITE - PTP logic has to process more than one PTP frame + * that needs time stamping before the current read. + * Only the latest one is saved. + * PTP_INT_DROP - PTP logic has to process more than one PTP frame + * that needs time stamping before the current read. + * Only the oldest one is saved. + * + */ +typedef enum +{ + PTP_INT_NORMAL = 0x0, + PTP_INT_OVERWRITE = 0x1, + PTP_INT_DROP = 0x2 +} GT_PTP_INT_STATUS; + + +/* + * typedef: struct GT_PTP_TS_STATUS + * + * Description: PTP port status of time stamp + * + * Fields: + * isValid - time stamp is valid + * status - time stamp error status + * timeStamped - time stamp value of a PTP frame that needs to be time stamped + * ptpSeqId - sequence ID of the frame whose time stamp information has been captured + */ +typedef struct +{ + GT_BOOL isValid; + GT_U32 timeStamped; + GT_U32 ptpSeqId; + GT_PTP_INT_STATUS status; +} GT_PTP_TS_STATUS; + + +/* + * typedef: struct GT_PTP_PORT_DISCARD_STATS + * + * Description: PTP port discard statistics. The counter (4 bit wide) wraps around after 15. + * + * Fields: + * tsDepDisCtr - PTP departure frame discard counter for PTP frames that need time stamping. + * ntsDepDisCtr - PTP departure frame discard counter for PTP frames that do not need time stamping. + * tsArrDisCtr - PTP arrival frame discard counter for PTP frames that need time stamping. + * ntsArrDisCtr - PTP arrival frame discard counter for PTP frames that do not need time stamping. + */ +typedef struct +{ + GT_U32 tsDepDisCtr; + GT_U32 ntsDepDisCtr; + GT_U32 tsArrDisCtr; + GT_U32 ntsArrDisCtr; +} GT_PTP_PORT_DISCARD_STATS; + + +#ifdef CONFIG_AVB_FPGA + +typedef enum +{ + PTP_CLOCK_SRC_AD_DEVICE = 0, /* PTP Clock source is from A/D device */ + PTP_CLOCK_SRC_FPGA /* PTP Clock source is from Cesium FPGA */ +} GT_PTP_CLOCK_SRC; + +typedef enum +{ + PTP_P9_MODE_GMII = 0, /* Port 9 uses GMII connect to 88E1111 */ + PTP_P9_MODE_MII, /* Port 9 uses MII connect to 88E1111 */ + PTP_P9_MODE_MII_CONNECTOR, /* Port 9 connect to MII connector */ + PTP_P9_MODE_JUMPER /* Use Jumper setup */ +} GT_PTP_P9_MODE; + +typedef enum +{ + GT_PTP_SIGN_NEGATIVE = 0, /* apply Minus sign to the Duty Cycle */ + GT_PTP_SIGN_PLUS /* apply Plus sign to the Duty Cycle */ +} GT_PTP_SIGN; + +typedef struct +{ + GT_PTP_SIGN adjSign; /* determine the plus/minus sign of the duty cycle adj */ + GT_U32 cycleStep; /* number of steps which will be applied in adjusting the duty cycle high time + of the 8KHz clock cycle. + valid values are 0 ~ 7 */ + GT_U32 cycleInterval; /* define the interval of clock cycles for which a duty cycle adj will occur */ + GT_U32 cycleAdjust; /* define the number of 8KHz clock cycles for which duty cycle adj will occur + within each PTP clock clycle interval. + Note that (cycleAdjust <= cycleInterval) for proper operation */ +} GT_PTP_CLOCK_ADJUSTMENT; + +#endif + +/* + * typedef: struct GT_TAI_EVENT_CONFIG + * + * Description: TAI event capture configuration parameters + * + * Fields: + * eventOverwrite - event capture overwrite + * eventCtrStart - event counter start + * intEn - event capture interrupt enable + */ +typedef struct +{ + GT_BOOL eventOverwrite; + GT_BOOL eventCtrStart; + GT_BOOL intEn; +} GT_TAI_EVENT_CONFIG; + + +/* + * typedef: struct GT_TAI_EVENT_STATUS + * + * Description: TAI event capture status + * + * Fields: + * isValid - eventTime is valid + * eventTime - PTP global time when event is registered. + * eventCtr - event capture counter. increamented only if eventCtrStart is set. + * eventErr - isValid is already set when a new event is observed. + */ +typedef struct +{ + GT_BOOL isValid; + GT_U32 eventTime; + GT_U32 eventCtr; + GT_BOOL eventErr; +} GT_TAI_EVENT_STATUS; + + +typedef enum +{ + GT_TAI_TRIG_PERIODIC_PURSE = 0, /* generate periodic purse */ + GT_TAI_TRIG_ON_GIVEN_TIME /* generate purse when + PTP global time matches with given time */ +} GT_TAI_TRIG_MODE; + + +/* + * typedef: struct GT_TAI_TRIGGER_CONFIG + * + * Description: TAI trigger generator configuration parameters + * + * Fields: + * intEn - trigger generator interrupt enable + * mode - trigger mode, either GT_TAI_TRIG_PERIODIC_PURSE or + * GT_TAI_TRIG_ON_GIVEN_TIME + * trigGenAmt - if mode is GT_TAI_TRIG_PERIODIC_PURSE, + * this value is used as a clock period in TSClkPer increments + * If mode is GT_TAI_TRIG_ON_GIVEN_TIME, + * this value is used to compare with PTP global time. + * pulseWidth - pulse width in units of TSClkPer. + * this value should be 1 ~ 0xF. If it's 0, no changes made. + * this value is valid only in GT_TAI_TRIG_ON_GIVEN_TIME mode. + * trigClkComp - trigger mode clock compensation amount in pico sec. + * this value is valid only in GT_TAI_TRIG_PERIODIC_PURSE mode. + */ +typedef struct +{ + GT_BOOL intEn; + GT_TAI_TRIG_MODE mode; + GT_U32 trigGenAmt; + GT_U32 pulseWidth; + GT_U32 trigClkComp; +} GT_TAI_TRIGGER_CONFIG; + + +typedef enum +{ + GT_AVB_HI_FPRI, /* AVB Hi Frame Priority */ + GT_AVB_HI_QPRI, /* AVB Hi Queue Priority */ + GT_AVB_LO_FPRI, /* AVB Lo Frame Priority */ + GT_AVB_LO_QPRI, /* AVB Lo Queue Priority */ + GT_LEGACY_HI_FPRI, /* Legacy Hi Frame Priority */ + GT_LEGACY_HI_QPRI, /* Legacy Hi Queue Priority */ + GT_LEGACY_LO_FPRI, /* Legacy Lo Frame Priority */ + GT_LEGACY_LO_QPRI /* Legacy Lo Queue Priority */ +} GT_AVB_PRI_TYPE; + + +typedef enum +{ + GT_AVB_LEGACY_MODE, /* all frames entering the port are considered + legacy */ + GT_AVB_STANDARD_AVB_MODE, /* any tagged frame that ends up with an AVB frame + priority is considered AVB */ + GT_AVB_ENHANCED_AVB_MODE, /* any frame that ends up with an AVB frame priority + whose DA is contained in the ATU with an AVB Entry + state is considered AVB */ + GT_AVB_SECURE_AVB_MODE /* any frame that ends up with an AVB frame priority + whose DA is contained in the ATU with an AVB + entry state and whose DPV has this source port's + bit set to a one is considered AVB. */ +} GT_AVB_MODE; + + +/* + * Typedef: enum GT_AVB_FRAME_POLICY + * + * Description: Defines the policy of the frame + * + * Fields: + * AVB_FRAME_POLICY_NONE - Normal frame switching + * AVB_FRAME_POLICY_MIRROR - Mirror(copy) frame to the MirrorDest port + * AVB_FRAME_POLICY_TRAP - Trap(re-direct) frame to the CPUDest port + * + */ +typedef enum +{ + AVB_FRAME_POLICY_NONE = 0, + AVB_FRAME_POLICY_MIRROR, + AVB_FRAME_POLICY_TRAP +} GT_AVB_FRAME_POLICY; + + +/* + * Typedef: enum GT_AVB_FRAME_TYPE + * + * Description: + * Defines the AVB frame type. + * AVB Hi Frame is one that DA of the frame is contained in the ATU with an + * Entry State that indicates AVB with priority override where the overridden + * priority equals the Hi AVB frame priority(refer to gavbGetPriority API) and + * when the port's DA AvbOverride is enabled. + * AVB Lo Frame is one that DA of the frame is contained in the ATU with an + * Entry State that indicates AVB with priority override where the overridden + * priority equals the Lo AVB frame priority(refer to gavbGetPriority API) and + * when the port's DA AvbOverride is enabled. + * + * Fields: + * AVB_HI_FRAME - AVB Hi Frame + * AVB_LO_FRAME - AVB Lo Frame + */ +typedef enum +{ + AVB_HI_FRAME, + AVB_LO_FRAME +} GT_AVB_FRAME_TYPE; + + +/* + * typedef: enum GT_EVENT_TYPE + * + * Description: Enumeration of the available hardware driven events. + * + * Enumerations: + * GT_AVB_INT - AVB Interrupt Enable + * GT_DEVICE_INT - Device Interrupt (GT_DEVICE_INT_TYPE) Enable + * GT_STATS_DONE - Statistics Operation Done interrrupt Enable + * GT_VTU_PROB - VLAN Problem/Violation Interrupt Enable + * GT_VTU_DONE - VALN Table Operation Done Interrupt Enable + * GT_ATU_PROB - ATU Problem/Violation Interrupt Enable, for Gigabit Switch + * GT_ATU_FULL - ATU full interrupt enable, for Fast Ethernet Switch + * GT_ATU_DONE - ATU Done interrupt enable. + * GT_PHY_INT - PHY interrupt enable, for Fast Ethernet Switch + * GT_EE_INT - EEPROM Done interrupt enable. + */ +#define GT_AVB_INT 0x100 +#define GT_DEVICE_INT 0x80 +#define GT_STATS_DONE 0x40 +#define GT_VTU_PROB 0x20 +#define GT_VTU_DONE 0x10 +#define GT_ATU_PROB 0x8 +#define GT_ATU_FULL 0x8 +#define GT_ATU_DONE 0x4 +#define GT_PHY_INTERRUPT 0x2 /* Device may not support PHY Int. Please refer to datasheet. */ +#define GT_EE_INTERRUPT 0x1 + +#define GT_INT_MASK \ + (GT_AVB_INT | GT_DEVICE_INT | GT_STATS_DONE | GT_VTU_PROB | GT_VTU_DONE | GT_ATU_FULL | \ + GT_ATU_DONE | GT_PHY_INTERRUPT | GT_EE_INTERRUPT) +#define GT_NO_INTERNAL_PHY_INT_MASK \ + (GT_AVB_INT | GT_DEVICE_INT | GT_STATS_DONE | GT_VTU_PROB | GT_VTU_DONE | GT_ATU_PROB | \ + GT_ATU_DONE | GT_EE_INTERRUPT) + + +/* + * typedef: struct GT_DEV_EVENT + * + * Description: Device interrupt status + * + * Fields: + * event - Device Interrupts to be enabled + * GT_DEV_INT_WATCHDOG, GT_DEV_INT_JAMLIMIT, + * GT_DEV_INT_DUPLEX_MISMATCH, and/or GT_DEV_INT_SERDES_LINK + * portList - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt needs + * to be asserted. It's in vector format, Bit 10 is for port 10, + * Bit 9 is for port 9, etc. + * valid only if GT_DEV_INT_SERDES_LINK bit is set. + * phyList - Phy list where GT_DEV_INT_PHY interrupt needs to be asserted. + * It's in vector format, Bit 0 is for port 0, + * Bit 1 is for port 1, etc. + * valid only if GT_DEV_INT_PHY bit is set. + */ +typedef struct +{ + GT_U32 event; + GT_U32 portList; + GT_U32 phyList; +} GT_DEV_EVENT; + + +/* + * typedef: struct GT_DEV_INT_STATUS + * + * Description: Device interrupt status + * + * Fields: + * intCause - Device Interrupt Cause + * GT_DEV_INT_WATCHDOG, GT_DEV_INT_JAMLIMIT, + * GT_DEV_INT_DUPLEX_MISMATCH, and/or GT_DEV_INT_SERDES_LINK + * port - logical port where GT_DEV_INT_DUPLEX_MISMATCH occurred. + * valid only if GT_DEV_INT_DUPLEX_MISMATCH is set. + * linkInt - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt is + * asserted. It's in vector format, Bit 10 is for port 10, + * Bit 9 is for port 9, etc. + * valid only if GT_DEV_INT_SERDES_LINK bit is set. + * These bits are only valid of the port that is in 1000Base-X mode. + */ +typedef struct +{ + GT_U32 devIntCause; + GT_LPORT port; + GT_U32 linkInt; + GT_U32 phyInt; +} GT_DEV_INT_STATUS; + + +/* +* GT_DEVICE_INT +* +* Description: Enumeration of Device interrupt +* GT_DEV_INT_WATCHDOG - WatchDog event interrupt (WatchDog event can be +* configured with gwdSetEvent API) +* GT_DEV_INT_JAMLIMIT - any of the ports detect an Ingress Jam Limit violation +* (gprtSetPauseLimitIn API) +* GT_DEV_INT_DUPLEX_MISMATCH - any of the ports detect a duplex mismatch +* (i.e., the local port is in half duplex mode while +* the link partner is in full duplex mode) +* GT_DEV_INT_SERDES_LINK - SERDES link chage interrupt. +* An interrupt occurs when a SERDES port changes link +* status (link up or link down) +*/ + +#define GT_DEV_INT_WATCHDOG 0x8 +#define GT_DEV_INT_JAMLIMIT 0x4 +#define GT_DEV_INT_DUPLEX_MISMATCH 0x2 +#define GT_DEV_INT_SERDES_LINK 0x1 +#define GT_DEV_INT_PHY 0x10 + +/* +* GT_WATCHDOG_EVENT +* +* Description: Enumeration of WatchDog event +* GT_WD_QC - Queue Controller Watch Dog enable. +* When enabled, the QC's watch dog circuit checks for link +* list errors and any errors found in the QC. +* GT_WD_EGRESS - Egress Watch Dog enable. +* When enabled, each port's egress circuit checks for problems +* between the port and the Queue Controller. +* GT_WD_FORCE - Force a Watch Dog event. +*/ + +#define GT_WD_QC 0x1 +#define GT_WD_EGRESS 0x2 +#define GT_WD_FORCE 0x4 + + +/* +* typedef: struct GT_WD_EVENT_HISTORY +* +* Description: WatchDog Event History (cleared only by a hardware reset) +* wdEvent - When it's set to GT_TRUE, some enabled Watch Dog event occurred. +* The following events are possible: +* QC WatchDog Event (GT_WD_QC) +* Egress WatchDog Event (GT_WD_EGRESS) +* Forced WatchDog Event (GT_WD_FORCE) +* egressEvent-If any port's egress logic detects an egress watch dog issue, +* this field is set to GT_TRUE, regardless of the enabling GT_WD_EGRESS +* event. +*/ +typedef struct +{ + GT_BOOL wdEvent; + GT_BOOL egressEvent; +} GT_WD_EVENT_HISTORY; + + +/* +* typedef: enum GT_PHY_INT +* +* Description: Enumeration of PHY interrupt +*/ + +#define GT_SPEED_CHANGED 0x4000 +#define GT_DUPLEX_CHANGED 0x2000 +#define GT_PAGE_RECEIVED 0x1000 +#define GT_AUTO_NEG_COMPLETED 0x800 +#define GT_LINK_STATUS_CHANGED 0x400 +#define GT_SYMBOL_ERROR 0x200 +#define GT_FALSE_CARRIER 0x100 +#define GT_FIFO_FLOW 0x80 +#define GT_CROSSOVER_CHANGED 0x40 +#define GT_POLARITY_CHANGED 0x2 +#define GT_JABBER 0x1 + +#define GT_AUTO_NEG_ERROR 0x8000 +#define GT_DOWNSHIFT_DETECT 0x20 +#define GT_ENERGY_DETECT 0x10 + +/* +* typedef: enum GT_PHY_AUTO_MODE +* +* Description: Enumeration of Autonegotiation mode. +* Auto for both speed and duplex. +* Auto for speed only and Full duplex. +* Auto for speed only and Half duplex. (1000Mbps is not supported) +* Auto for duplex only and speed 1000Mbps. +* Auto for duplex only and speed 100Mbps. +* Auto for duplex only and speed 10Mbps. +* 1000Mbps Full duplex. +* 100Mbps Full duplex. +* 100Mbps Half duplex. +* 10Mbps Full duplex. +* 10Mbps Half duplex. +*/ + +typedef enum +{ + SPEED_AUTO_DUPLEX_AUTO, + SPEED_1000_DUPLEX_AUTO, + SPEED_100_DUPLEX_AUTO, + SPEED_10_DUPLEX_AUTO, + SPEED_AUTO_DUPLEX_FULL, + SPEED_AUTO_DUPLEX_HALF, + SPEED_1000_DUPLEX_FULL, + SPEED_1000_DUPLEX_HALF, + SPEED_100_DUPLEX_FULL, + SPEED_100_DUPLEX_HALF, + SPEED_10_DUPLEX_FULL, + SPEED_10_DUPLEX_HALF +}GT_PHY_AUTO_MODE; + + +/* +* typedef: enum GT_PHY_PAUSE_MODE +* +* Description: Enumeration of Pause Mode in the Phy. +* +* Enumerations: +* GT_PHY_NO_PAUSE - disable pause +* GT_PHY_PAUSE - support pause +* GT_PHY_ASYMMETRIC_PAUSE - support asymmetric pause +* GT_PHY_BOTH_PAUSE - support both pause and asymmetric pause +*/ +typedef enum +{ + GT_PHY_NO_PAUSE = 0, + GT_PHY_PAUSE, + GT_PHY_ASYMMETRIC_PAUSE, + GT_PHY_BOTH_PAUSE +} GT_PHY_PAUSE_MODE; + + +/* +* typedef: enum GT_PHY_SPEED +* +* Description: Enumeration of Phy Speed +* +* Enumerations: +* PHY_SPEED_10_MBPS - 10Mbps +* PHY_SPEED_100_MBPS - 100Mbps +* PHY_SPEED_1000_MBPS - 1000Mbps +*/ +typedef enum +{ + PHY_SPEED_10_MBPS, + PHY_SPEED_100_MBPS, + PHY_SPEED_1000_MBPS +} GT_PHY_SPEED; + + +/* +* typedef: enum GT_SERDES_MODE +* +* Description: Enumeration of Serdes mode +* +* Enumerations: +* PHY_SERDES_100FX - 100 FX +* PHY_SERDES_1000X - 1000 X +* PHY_SERDES_SGMII_PHY - SGMII PHY +* PHY_SERDES_SGMII_MAC - SGMII MAC +*/ +typedef enum +{ + PHY_SERDES_100FX = 0, + PHY_SERDES_1000X, + PHY_SERDES_SGMII_PHY, + PHY_SERDES_SGMII_MAC +} GT_SERDES_MODE; + + +/* +* typedef: enum GT_EDETECT_MODE +* +* Description: Enumeration of Energy Detect mode +* +* Enumerations: +* GT_EDETECT_OFF - Energy Detect disabled +* GT_EDETECT_SENSE_PULSE - Energy Detect enabled with sense and pulse +* GT_EDETECT_SENSE - Energy Detect enabled only with sense +*/ +typedef enum +{ + GT_EDETECT_OFF = 0, + GT_EDETECT_SENSE_PULSE, + GT_EDETECT_SENSE +} GT_EDETECT_MODE; + +/* + * typedef: enum GT_INGRESS_MODE + * + * Description: Enumeration of the port ingress mode. + * + * Enumerations: + * GT_UNMODIFY_INGRESS - frames are receive unmodified. + * GT_TRAILER_INGRESS - all frames are received with trailer. + * GT_UNTAGGED_INGRESS - remove tag on receive (for double tagging). + * GT_CPUPORT_INGRESS - no trailer. used to identify the CPU port for IGMP/MLD Snooping + */ +typedef enum +{ + GT_UNMODIFY_INGRESS = 0, /* 0x00 */ + GT_TRAILER_INGRESS, /* 0x01 */ + GT_UNTAGGED_INGRESS, /* 0x10 */ + GT_CPUPORT_INGRESS /* 0x11 */ +} GT_INGRESS_MODE; + + +/* + * typedef: enum GT_EGRESS_FLOOD + * + * Description: Enumeration of the port ingress mode. + * + * Enumerations: + * GT_BLOCK_EGRESS_UNKNOWN - do not egress frame with unknown DA + * GT_BLOCK_EGRESS_UNKNOWN_MULTICAST - do not egress frame with unknown multicast DA + * GT_BLOCK_EGRESS_UNKNOWN_UNIICAST - do not egress frame with unknown unicast DA + * GT_BLOCK_EGRESS_NONE - egress all frames with unknown DA + */ +typedef enum +{ + GT_BLOCK_EGRESS_UNKNOWN = 0, + GT_BLOCK_EGRESS_UNKNOWN_MULTICAST, + GT_BLOCK_EGRESS_UNKNOWN_UNICAST, + GT_BLOCK_EGRESS_NONE +} GT_EGRESS_FLOOD; + + +/* + * typedef: enum GT_MC_RATE + * + * Description: Enumeration of the port ingress mode. + * + * Enumerations: + * GT_MC_3_PERCENT_RL - multicast rate is limited to 3 percent. + * GT_MC_6_PERCENT_RL - multicast rate is limited to 6 percent. + * GT_MC_12_PERCENT_RL - multicast rate is limited to 12 percent. + * GT_MC_100_PERCENT_RL - unlimited multicast rate. + */ +typedef enum +{ + GT_MC_3_PERCENT_RL = 0, + GT_MC_6_PERCENT_RL, + GT_MC_12_PERCENT_RL, + GT_MC_100_PERCENT_RL, +} GT_MC_RATE; + + +/* + * typedef: enum GT_INGRESS_RATE_MODE + * + * Description: Enumeration of the port ingress rate limit mode. + * + * Enumerations: + * GT_RATE_PRI_BASE - Priority based rate limiting + * GT_RATE_BURST_BASE - Burst Size based rate limiting + */ +typedef enum +{ + GT_RATE_PRI_BASE = 0, + GT_RATE_BURST_BASE +} GT_INGRESS_RATE_MODE; + + +/* + * typedef: enum GT_PORT_SCHED_MODE + * + * Description: Enumeration of port scheduling mode + * + * Fields: + * GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling + * GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme + * GT_PORT_SCHED_STRICT_PRI3 - use a strict for priority 3 and weighted + * round robin for the priority 2,1,and 0 + * GT_PORT_SCHED_STRICT_PRI2_3 - use a strict for priority 2,3 and weighted + * round robin for the priority 1,and 0 + * + * Comment: + */ +typedef enum +{ + GT_PORT_SCHED_WEIGHTED_RRB = 0, + GT_PORT_SCHED_STRICT_PRI, + GT_PORT_SCHED_STRICT_PRI3, + GT_PORT_SCHED_STRICT_PRI2_3 +} GT_PORT_SCHED_MODE; + + +/* + * typedef: struct GT_PORT_STAT + * + * Description: port statistic struct. + * + * Fields: + * rxCtr - port receive counter. + * txCtr - port transmit counter. + * dropped - dropped frame counter. + * + * Comment: + * dropped frame counter is supported by only limited devices. + * At this moment, 88E6061/88E6065 are the devices supporting + * dropped frame counter. + */ +typedef struct +{ + GT_U16 rxCtr; + GT_U16 txCtr; + GT_U16 dropped; +} GT_PORT_STAT; + +/* + * typedef: struct GT_PORT_STAT2 + * + * Description: port statistic struct. + * + * Fields: + * inDiscardLo - InDiscards Low Frame Counter + * inDiscardHi - InDiscards High Frame Counter + * inFiltered - InFiltered Frame Counter + * outFiltered - OutFiltered Frame Counter + * + * Comment: + */ +typedef struct +{ + GT_U16 inDiscardLo; + GT_U16 inDiscardHi; + GT_U16 inFiltered; + GT_U16 outFiltered; +} GT_PORT_STAT2; + + +/* + ** typedef: struct GT_PORT_Q_COUNTERS + ** + ** Description: port queue statistic struct. + ** + ** Fields: + ** OutQ_Size - port egress queue size coi + ** Rsv_Size - ingress reserved e counter + ** + **/ +typedef struct +{ + GT_U16 OutQ_Size; + GT_U16 Rsv_Size; +} GT_PORT_Q_STAT; + +/* + * typedef: enum GT_CTR_MODE + * + * Description: Enumeration of the port counters mode. + * + * Enumerations: + * GT_CTR_ALL - In this mode the counters counts Rx receive and transmit + * frames. + * GT_CTR_ERRORS - In this mode the counters counts Rx Errors and collisions. + */ +typedef enum +{ + GT_CTR_ALL = 0, + GT_CTR_ERRORS, +} GT_CTR_MODE; + +typedef struct _GT_QD_DEV GT_QD_DEV; + +/* + * semaphore related definitions. + * User Applications may register Semaphore functions using following definitions + */ +typedef enum +{ + GT_SEM_EMPTY, + GT_SEM_FULL +} GT_SEM_BEGIN_STATE; + +typedef GT_SEM (*FGT_SEM_CREATE)( + GT_SEM_BEGIN_STATE state); +typedef GT_STATUS (*FGT_SEM_DELETE)( + GT_SEM semId); +typedef GT_STATUS (*FGT_SEM_TAKE)( + GT_SEM semId, GT_U32 timOut); +typedef GT_STATUS (*FGT_SEM_GIVE)( + GT_SEM semId); + +typedef struct +{ + FGT_SEM_CREATE semCreate; /* create semapore */ + FGT_SEM_DELETE semDelete; /* delete the semapore */ + FGT_SEM_TAKE semTake; /* try to get a semapore */ + FGT_SEM_GIVE semGive; /* return semaphore */ +}GT_SEM_ROUTINES; + +/* + * definitions for registering MII access functions. + * +*/ +typedef GT_BOOL (*FGT_READ_MII)( + GT_QD_DEV* dev, + unsigned int phyAddr, + unsigned int miiReg, + unsigned int* value); +typedef GT_BOOL (*FGT_WRITE_MII)( + GT_QD_DEV* dev, + unsigned int phyAddr, + unsigned int miiReg, + unsigned int value); +typedef GT_BOOL (*FGT_INT_HANDLER)( + GT_QD_DEV* dev, + GT_U16*); + +typedef struct _BSP_FUNCTIONS +{ + FGT_READ_MII readMii; /* read MII Registers */ + FGT_WRITE_MII writeMii; /* write MII Registers */ + FGT_SEM_CREATE semCreate; /* create semapore */ + FGT_SEM_DELETE semDelete; /* delete the semapore */ + FGT_SEM_TAKE semTake; /* try to get a semapore */ + FGT_SEM_GIVE semGive; /* return semaphore */ +}BSP_FUNCTIONS; + + +/* + * Type definition for MIB counter operation +*/ +typedef enum +{ + STATS_FLUSH_ALL, /* Flush all counters for all ports */ + STATS_FLUSH_PORT, /* Flush all counters for a port */ + STATS_READ_COUNTER, /* Read a specific counter from a port */ + STATS_READ_REALTIME_COUNTER, /* Read a realtime counter from a port */ + STATS_READ_ALL /* Read all counters from a port */ + +} GT_STATS_OPERATION; + +typedef struct _GT_STATS_COUNTER_SET +{ + GT_U32 InUnicasts; + GT_U32 InBroadcasts; + GT_U32 InPause; + GT_U32 InMulticasts; + GT_U32 InFCSErr; + GT_U32 AlignErr; + GT_U32 InGoodOctets; + GT_U32 InBadOctets; + GT_U32 Undersize; + GT_U32 Fragments; + GT_U32 In64Octets; /* 64 Octets */ + GT_U32 In127Octets; /* 65 to 127 Octets */ + GT_U32 In255Octets; /* 128 to 255 Octets */ + GT_U32 In511Octets; /* 256 to 511 Octets */ + GT_U32 In1023Octets; /* 512 to 1023 Octets */ + GT_U32 InMaxOctets; /* 1024 to Max Octets */ + GT_U32 Jabber; + GT_U32 Oversize; + GT_U32 InDiscards; + GT_U32 Filtered; + GT_U32 OutUnicasts; + GT_U32 OutBroadcasts; + GT_U32 OutPause; + GT_U32 OutMulticasts; + GT_U32 OutFCSErr; + GT_U32 OutGoodOctets; + GT_U32 Out64Octets; /* 64 Octets */ + GT_U32 Out127Octets; /* 65 to 127 Octets */ + GT_U32 Out255Octets; /* 128 to 255 Octets */ + GT_U32 Out511Octets; /* 256 to 511 Octets */ + GT_U32 Out1023Octets; /* 512 to 1023 Octets */ + GT_U32 OutMaxOctets; /* 1024 to Max Octets */ + GT_U32 Collisions; + GT_U32 Late; + GT_U32 Excessive; + GT_U32 Multiple; + GT_U32 Single; + GT_U32 Deferred; + GT_U32 OutDiscards; + +} GT_STATS_COUNTER_SET; + + +typedef enum +{ + STATS_InUnicasts = 0, + STATS_InBroadcasts, + STATS_InPause, + STATS_InMulticasts, + STATS_InFCSErr, + STATS_AlignErr, + STATS_InGoodOctets, + STATS_InBadOctets, + STATS_Undersize, + STATS_Fragments, + STATS_In64Octets, + STATS_In127Octets, + STATS_In255Octets, + STATS_In511Octets, + STATS_In1023Octets, + STATS_InMaxOctets, + STATS_Jabber, + STATS_Oversize, + STATS_InDiscards, + STATS_Filtered, + STATS_OutUnicasts, + STATS_OutBroadcasts, + STATS_OutPause, + STATS_OutMulticasts, + STATS_OutFCSErr, + STATS_OutGoodOctets, + STATS_Out64Octets, + STATS_Out127Octets, + STATS_Out255Octets, + STATS_Out511Octets, + STATS_Out1023Octets, + STATS_OutMaxOctets, + STATS_Collisions, + STATS_Late, + STATS_Excessive, + STATS_Multiple, + STATS_Single, + STATS_Deferred, + STATS_OutDiscards + +} GT_STATS_COUNTERS; +/* + * typedef: enum GT_HISTOGRAM_MODE + * + * Description: Enumeration of the histogram counters mode. + * + * Enumerations: + * GT_COUNT_RX_ONLY - In this mode, Rx Histogram Counters are counted. + * GT_COUNT_TX_ONLY - In this mode, Tx Histogram Counters are counted. + * GT_COUNT_RX_TX - In this mode, Rx and Tx Histogram Counters are counted. + */ +typedef enum +{ + GT_COUNT_RX_ONLY = 0, + GT_COUNT_TX_ONLY, + GT_COUNT_RX_TX +} GT_HISTOGRAM_MODE; + +/* + Counter set 2 is used by 88E6183 +*/ +typedef struct _GT_STATS_COUNTER_SET2 +{ + GT_U32 InGoodOctetsHi; + GT_U32 InGoodOctetsLo; + GT_U32 InBadOctets; + GT_U32 OutDiscards; + GT_U32 InGoodFrames; + GT_U32 InBadFrames; + GT_U32 InBroadcasts; + GT_U32 InMulticasts; + /* + Histogram Counters : Rx Only, Tx Only, or both Rx and Tx + (refer to Histogram Mode) + */ + GT_U32 Octets64; /* 64 Octets */ + GT_U32 Octets127; /* 65 to 127 Octets */ + GT_U32 Octets255; /* 128 to 255 Octets */ + GT_U32 Octets511; /* 256 to 511 Octets */ + GT_U32 Octets1023; /* 512 to 1023 Octets */ + GT_U32 OctetsMax; /* 1024 to Max Octets */ + GT_U32 OutOctetsHi; + GT_U32 OutOctetsLo; + GT_U32 OutFrames; + GT_U32 Excessive; + GT_U32 OutMulticasts; + GT_U32 OutBroadcasts; + GT_U32 InBadMACCtrl; + + GT_U32 OutPause; + GT_U32 InPause; + GT_U32 InDiscards; + GT_U32 Undersize; + GT_U32 Fragments; + GT_U32 Oversize; + GT_U32 Jabber; + GT_U32 MACRcvErr; + GT_U32 InFCSErr; + GT_U32 Collisions; + GT_U32 Late; + +} GT_STATS_COUNTER_SET2; + + +typedef enum +{ + STATS2_InGoodOctetsHi = 0, + STATS2_InGoodOctetsLo, + STATS2_InBadOctets, + + STATS2_OutDiscards, + STATS2_InGoodFrames, + STATS2_InBadFrames, + STATS2_InBroadcasts, + STATS2_InMulticasts, + STATS2_64Octets, + STATS2_127Octets, + STATS2_255Octets, + STATS2_511Octets, + STATS2_1023Octets, + STATS2_MaxOctets, + STATS2_OutOctetsHi, + STATS2_OutOctetsLo, + STATS2_OutFrames, + STATS2_Excessive, + STATS2_OutMulticasts, + STATS2_OutBroadcasts, + STATS2_InBadMACCtrl, + STATS2_OutPause, + STATS2_InPause, + STATS2_InDiscards, + STATS2_Undersize, + STATS2_Fragments, + STATS2_Oversize, + STATS2_Jabber, + STATS2_MACRcvErr, + STATS2_InFCSErr, + STATS2_Collisions, + STATS2_Late + +} GT_STATS_COUNTERS2; + +/* + Counter set 3 is used by 88E6093 and 88E6065 +*/ +typedef struct _GT_STATS_COUNTER_SET3 +{ + GT_U32 InGoodOctetsLo; /* offset 0 */ + GT_U32 InGoodOctetsHi; /* offset 1, not supported by 88E6065 */ + GT_U32 InBadOctets; /* offset 2 */ + GT_U32 OutFCSErr; /* offset 3 */ + GT_U32 InUnicasts; /* offset 4 */ + GT_U32 Deferred; /* offset 5 */ + GT_U32 InBroadcasts; /* offset 6 */ + GT_U32 InMulticasts; /* offset 7 */ + /* + Histogram Counters : Rx Only, Tx Only, or both Rx and Tx + (refer to Histogram Mode) + */ + GT_U32 Octets64; /* 64 Octets, offset 8 */ + GT_U32 Octets127; /* 65 to 127 Octets, offset 9 */ + GT_U32 Octets255; /* 128 to 255 Octets, offset 10 */ + GT_U32 Octets511; /* 256 to 511 Octets, offset 11 */ + GT_U32 Octets1023; /* 512 to 1023 Octets, offset 12 */ + GT_U32 OctetsMax; /* 1024 to Max Octets, offset 13 */ + GT_U32 OutOctetsLo; /* offset 14 */ + GT_U32 OutOctetsHi; /* offset 15, not supported by 88E6065 */ + GT_U32 OutUnicasts; /* offset 16 */ + GT_U32 Excessive; /* offset 17 */ + GT_U32 OutMulticasts; /* offset 18 */ + GT_U32 OutBroadcasts; /* offset 19 */ + GT_U32 Single; /* offset 20 */ + + GT_U32 OutPause; /* offset 21 */ + GT_U32 InPause; /* offset 22 */ + GT_U32 Multiple; /* offset 23 */ + GT_U32 Undersize; /* offset 24 */ + GT_U32 Fragments; /* offset 25 */ + GT_U32 Oversize; /* offset 26 */ + GT_U32 Jabber; /* offset 27 */ + GT_U32 InMACRcvErr; /* offset 28 */ + GT_U32 InFCSErr; /* offset 29 */ + GT_U32 Collisions; /* offset 30 */ + GT_U32 Late; /* offset 31 */ + +} GT_STATS_COUNTER_SET3; + + +typedef enum +{ + STATS3_InGoodOctetsLo = 0, + STATS3_InGoodOctetsHi, + STATS3_InBadOctets, + + STATS3_OutFCSErr, + STATS3_InUnicasts, + STATS3_Deferred, /* offset 5 */ + STATS3_InBroadcasts, + STATS3_InMulticasts, + STATS3_64Octets, + STATS3_127Octets, + STATS3_255Octets, /* offset 10 */ + STATS3_511Octets, + STATS3_1023Octets, + STATS3_MaxOctets, + STATS3_OutOctetsLo, + STATS3_OutOctetsHi, + STATS3_OutUnicasts, /* offset 16 */ + STATS3_Excessive, + STATS3_OutMulticasts, + STATS3_OutBroadcasts, + STATS3_Single, + STATS3_OutPause, + STATS3_InPause, + STATS3_Multiple, + STATS3_Undersize, /* offset 24 */ + STATS3_Fragments, + STATS3_Oversize, + STATS3_Jabber, + STATS3_InMACRcvErr, + STATS3_InFCSErr, + STATS3_Collisions, + STATS3_Late /* offset 31 */ + +} GT_STATS_COUNTERS3; + + + +/* + * typedef: struct GT_1000T_MASTER_SLAVE + * + * Description: 1000Base-T Master/Slave Configuration + * + * Fields: + * autoConfig - GT_TRUE for auto-config, GT_FALSE for manual setup. + * masterPrefer - GT_TRUE if Master configuration is preferred. + * + */ +typedef struct _GT_1000T_MASTER_SLAVE +{ + GT_BOOL autoConfig; + GT_BOOL masterPrefer; +} GT_1000T_MASTER_SLAVE; + + +#define GT_MDI_PAIR_NUM 4 /* (1,2),(3,6),(4,5),(7,8) */ +#define GT_CHANNEL_PAIR_NUM 2 /* (channel A,B),(channel C,D) */ + + +/* + * typedef: enum GT_PHY_LINK_STATUS + * + * Description: Enumeration of Link Status + * + * Enumerations: + * GT_PHY_LINK_OFF - No Link + * GT_PHY_LINK_COPPER - Link on Copper + * GT_PHY_LINK_FIBER - Link on Fiber + */ +typedef enum +{ + GT_PHY_LINK_OFF = 0, + GT_PHY_LINK_COPPER = 1, + GT_PHY_LINK_FIBER = 2 +} GT_PHY_LINK_STATUS; + + +/* Definition for packet generator */ + +/* Payload */ +typedef enum +{ + GT_PG_PAYLOAD_RANDOM = 0, /* Pseudo-random */ + GT_PG_PAYLOAD_5AA5 /* 5A,A5,5A,A5,... */ +} GT_PG_PAYLOAD; + +/* Length */ +typedef enum +{ + GT_PG_LENGTH_64 = 0, /* 64 bytes */ + GT_PG_LENGTH_1514 +} GT_PG_LENGTH; + +/* Error */ +typedef enum +{ + GT_PG_TX_NORMAL = 0, /* No Error */ + GT_PG_TX_ERROR /* Tx packets with CRC error and Symbol error */ +} GT_PG_TX; + +/* Structure for packet generator */ +typedef struct +{ + GT_PG_PAYLOAD payload; + GT_PG_LENGTH length; + GT_PG_TX tx; +} GT_PG; + + +/* + * typedef: enum GT_TEST_STATUS + * + * Description: Enumeration of VCT test status + * + * Enumerations: + * GT_TEST_FAIL - virtual cable test failed. + * GT_NORMAL_CABLE - normal cable. + * GT_IMPEDANCE_MISMATCH - impedance mismatch. + * GT_OPEN_CABLE - open in cable. + * GT_SHORT_CABLE - short in cable. + * + */ +typedef enum +{ + GT_TEST_FAIL, + GT_NORMAL_CABLE, + GT_IMPEDANCE_MISMATCH, + GT_OPEN_CABLE, + GT_SHORT_CABLE, +} GT_TEST_STATUS; + + +/* + * typedef: enum GT_NORMAL_CABLE_LEN + * + * Description: Enumeration for normal cable length + * + * Enumerations: + * GT_LESS_THAN_50M - cable length less than 50 meter. + * GT_50M_80M - cable length between 50 - 80 meter. + * GT_80M_110M - cable length between 80 - 110 meter. + * GT_110M_140M - cable length between 110 - 140 meter. + * GT_MORE_THAN_140 - cable length more than 140 meter. + * GT_UNKNOWN_LEN - unknown length. + * + */ +typedef enum +{ + GT_LESS_THAN_50M, + GT_50M_80M, + GT_80M_110M, + GT_110M_140M, + GT_MORE_THAN_140, + GT_UNKNOWN_LEN, + +} GT_NORMAL_CABLE_LEN; + + +/* + * typedef: enum GT_CABLE_LEN + * + * Description: Enumeration cable length + * + * Enumerations: + * normCableLen - cable lenght for normal cable. + * errCableLen - for cable failure the estimate fault distance in meters. + * + */ +typedef union +{ + GT_NORMAL_CABLE_LEN normCableLen; + GT_U8 errCableLen; + +} GT_CABLE_LEN; + +/* + * typedef: struct GT_CABLE_STATUS + * + * Description: virtual cable diagnostic status per MDI pair. + * + * Fields: + * cableStatus - VCT cable status. + * cableLen - VCT cable length. + * phyType - type of phy (100M phy or Gigabit phy) + */ +typedef struct +{ + GT_TEST_STATUS cableStatus[GT_MDI_PAIR_NUM]; + GT_CABLE_LEN cableLen[GT_MDI_PAIR_NUM]; + GT_U16 phyType; + +} GT_CABLE_STATUS; + + +/* + * typedef: enum GT_CABLE_TYPE + * + * Description: Enumeration of Cable Type + * + * Enumerations: + * GT_STRAIGHT_CABLE _ straight cable + * GT_CROSSOVER_CABLE - crossover cable + */ +typedef enum +{ + GT_STRAIGHT_CABLE, + GT_CROSSOVER_CABLE + +} GT_CABLE_TYPE; + + +/* + * typedef: enum GT_RX_CHANNEL + * + * Description: Enumeration of Receiver Channel Assignment + * + * Enumerations: + * GT_CHANNEL_A - Channel A + * GT_CHANNEL_B - Channel B + * GT_CHANNEL_C - Channel C + * GT_CHANNEL_D - Channel D + */ +typedef enum +{ + GT_CHANNEL_A, + GT_CHANNEL_B, + GT_CHANNEL_C, + GT_CHANNEL_D +} GT_RX_CHANNEL; + + +/* + * typedef: enum GT_POLARITY_STATUS + * + * Description: Enumeration of polarity status + * + * Enumerations: + * GT_POSITIVE - positive polarity + * GT_NEGATIVE - negative polarity + */ +typedef enum +{ + GT_POSITIVE, + GT_NEGATIVE + +} GT_POLARITY_STATUS; + + +/* + * typedef: struct GT_1000BT_EXTENDED_STATUS + * + * Description: Currently the 1000Base-T PCS can determine the cable polarity + * on pairs A,B,C,D; crossover on pairs A,B and C,D; and skew among + * the pares. These status enhance the capability of the virtual cable tester + * + * Fields: + * isValid - GT_TRUE if this structure have valid information, + * GT_FALSE otherwise. + * It is valid only if 1000BASE-T Link is up. + * pairSwap - GT_CROSSOVER_CABLE, if the cable is crossover, + * GT_STRAIGHT_CABLE, otherwise + * pairPolarity- GT_POSITIVE, if polarity is positive, + * GT_NEGATIVE, otherwise + * pairSkew - pair skew in units of ns + */ +typedef struct +{ + GT_BOOL isValid; + GT_CABLE_TYPE pairSwap[GT_CHANNEL_PAIR_NUM]; + GT_POLARITY_STATUS pairPolarity[GT_MDI_PAIR_NUM]; + GT_U32 pairSkew[GT_MDI_PAIR_NUM]; + +} GT_1000BT_EXTENDED_STATUS; + + +/* + * typedef: struct GT_ADV_EXTENDED_STATUS + * + * Description: Currently the 1000Base-T PCS can determine the cable polarity + * on pairs A,B,C,D; crossover on pairs A,B and C,D; and skew among + * the pares. These status enhance the capability of the virtual cable tester + * + * Fields: + * isValid - GT_TRUE if this structure have valid information, + * GT_FALSE otherwise. + * It is valid only if 1000BASE-T Link is up. + * pairSwap - Receive channel assignement + * pairPolarity- GT_POSITIVE, if polarity is positive, + * GT_NEGATIVE, otherwise + * pairSkew - pair skew in units of ns + * cableLen - cable length based on DSP + */ +typedef struct +{ + GT_BOOL isValid; + GT_RX_CHANNEL pairSwap[GT_MDI_PAIR_NUM]; + GT_POLARITY_STATUS pairPolarity[GT_MDI_PAIR_NUM]; + GT_U32 pairSkew[GT_MDI_PAIR_NUM]; + GT_U32 cableLen[GT_MDI_PAIR_NUM]; +} GT_ADV_EXTENDED_STATUS; + + +/* + * if isGigPhy in GT_CABLE_STATUS is not GT_TRUE, cableStatus and cableLen + * will have only 2 pairs available. + * One is RX Pair and the other is TX Pair. + */ +#define MDI_RX_PAIR 0 /* cableStatus[0] or cableLen[0] */ +#define MDI_TX_PAIR 1 /* cableStatus[1] or cableLen[1] */ + +/* definition for Phy Type */ +#define PHY_100M 0 /* 10/100M phy, E3082 or E3083 */ +#define PHY_1000M 1 /* Gigabit phy, the rest phys */ +#define PHY_10000M 2 /* 10 Gigabit phy, unused */ +#define PHY_1000M_B 3 /* Gigabit phy which needs work-around */ +#define PHY_1000M_MP 4 /* Gigabit phy with multiple page mode */ + + +/* Definition for Advance Virtual Cable Test */ + +/* + * typedef: enum GT_ADV_VCT_TRANS_CHAN_SEL + * + * Description: Enumeration of Advanced VCT Transmitter channel select + * + * Enumerations: + * GT_ADV_VCT_NO_CROSSPAIR - Transmitter channel select is 000 + * GT_ADV_VCT_CROSSPAIR - Transmitter channelselect is 100/101/110/111 + */ +typedef enum +{ + /* Advanced VCT Mode */ + GT_ADV_VCT_TCS_NO_CROSSPAIR = 0, + GT_ADV_VCT_TCS_CROSSPAIR_0 = 0x4, + GT_ADV_VCT_TCS_CROSSPAIR_1 = 0x5, + GT_ADV_VCT_TCS_CROSSPAIR_2 = 0x6, + GT_ADV_VCT_TCS_CROSSPAIR_3 = 0x7 +} GT_ADV_VCT_TRANS_CHAN_SEL; + + +typedef enum +{ + /* Advanced VCT Mode */ + GT_ADV_VCT_SAVG_2 = 0, + GT_ADV_VCT_SAVG_4 = 1, + GT_ADV_VCT_SAVG_8 = 2, + GT_ADV_VCT_SAVG_16 = 3, + GT_ADV_VCT_SAVG_32 = 4, + GT_ADV_VCT_SAVG_64 = 5, + GT_ADV_VCT_SAVG_128 = 6, + GT_ADV_VCT_SAVG_256 = 7 +} GT_ADV_VCT_SAMPLE_AVG; + +typedef enum +{ + /* Advanced VCT Mode */ + GT_ADV_VCT_MAX_PEAK =0x00, + GT_ADV_VCT_FIRST_PEAK =0x01, +} GT_ADV_VCT_MOD; + + +typedef unsigned int GT_ADV_VCT_PEAKDET_HYST; + +/* + * typedef: enum GT_ADV_VCT_MODE + * + * Description: Enumeration of Advanced VCT Mode and Transmitter channel select + * + * Enumerations: + * GT_ADV_VCT_FIRST_PEAK - first peak above a certain threshold is reported. + * GT_ADV_VCT_MAX_PEAK - maximum peak above a certain threshold is reported. + * GT_ADV_VCT_OFFSE - offset + * GT_ADV_VCT_SAMPLE_POINT - sample point + * + * GT_ADV_VCT_NO_CROSSPAIR - Transmitter channel select is 000 + * GT_ADV_VCT_CROSSPAIR - Transmitter channelselect is 100/101/110/111 + * Example: mode = GT_ADV_VCT_FIRST_PEAK | GT_ADV_VCT_CROSSPAIR. + */ +typedef struct +{ + GT_ADV_VCT_MOD mode; + GT_ADV_VCT_TRANS_CHAN_SEL transChanSel; + GT_ADV_VCT_SAMPLE_AVG sampleAvg; + GT_ADV_VCT_PEAKDET_HYST peakDetHyst; +} GT_ADV_VCT_MODE; + + +/* + * typedef: enum GT_ADV_VCT_STATUS + * + * Description: Enumeration of Advanced VCT status + * + * Enumerations: + * GT_ADV_VCT_FAIL - advanced virtual cable test failed. + * cable lengh cannot be determined. + * GT_ADV_VCT_NORMAL - normal cable. + * cable lengh may not be determined. + * GT_ADV_VCT_IMP_GREATER_THAN_115 - impedance mismatch > 115 ohms + * cable lengh is valid. + * GT_ADV_VCT_IMP_LESS_THAN_85 - impedance mismatch < 85 ohms + * cable lengh is valid. + * GT_ADV_VCT_OPEN - cable open + * cable lengh is valid. + * GT_ADV_VCT_SHORT - cable shorted + * cable lengh is valid. + * GT_ADV_VCT_CROSS_PAIR_SHORT - cross pair short. + * cable lengh for each channel is valid. + */ +typedef enum +{ + GT_ADV_VCT_FAIL, + GT_ADV_VCT_NORMAL, + GT_ADV_VCT_IMP_GREATER_THAN_115, + GT_ADV_VCT_IMP_LESS_THAN_85, + GT_ADV_VCT_OPEN, + GT_ADV_VCT_SHORT, + GT_ADV_VCT_CROSS_PAIR_SHORT +} GT_ADV_VCT_STATUS; + + +/* + * typedef: struct GT_CROSS_PAIR_LIST + * + * Description: strucuture for cross pair short channels. + * + * Fields: + * channel - cross pair short channel list + * channel[i] is GT_TRUE if the channel[i] is cross pair short + * with the current channel under test. + * dist2fault - estimated distance to the shorted location. + * valid only if related channel (above) is GT_TRUE. + */ +typedef struct _GT_CROSS_SHORT_LIST +{ + GT_BOOL channel[GT_MDI_PAIR_NUM]; + GT_16 dist2fault[GT_MDI_PAIR_NUM]; +} GT_CROSS_SHORT_LIST; + + +/* + * typedef: struct GT_ADV_CABLE_STATUS + * + * Description: strucuture for advanced cable status. + * + * Fields: + * cableStatus - VCT cable status for each channel. + * crossShort - cross pair short list for each channel. + * Valid only if relative cableStatus is GT_ADV_VCT_CROSS_PAIR_SHORT. + * dist2fault - estimated distance to fault for each channel. + * Valid if relative cableStatus is one of the followings: + * GT_ADV_VCT_NORMAL + * GT_ADV_VCT_IMP_GREATER_THAN_115 + * GT_ADV_VCT_IMP_LESS_THAN_85, + * GT_ADV_VCT_OPEN, or + * GT_ADV_VCT_SHORT + */ +typedef struct +{ + GT_ADV_VCT_STATUS cableStatus[GT_MDI_PAIR_NUM]; + union { + GT_CROSS_SHORT_LIST crossShort; + GT_16 dist2fault; + }u[GT_MDI_PAIR_NUM]; +} GT_ADV_CABLE_STATUS; + + +/* + * Definition: + * GT_LED_LINK_ACT_SPEED - off = no link, on = link, blink = activity, blink speed = link speed + * GT_LED_LINK_ACT - off = no link, on = link, blink = activity + * GT_LED_LINK - off = no link, on = link + * GT_LED_10_LINK_ACT - off = no link, on = 10, blink = activity + * GT_LED_10_LINK - off = no link, on = 10 + * GT_LED_100_LINK_ACT - off = no link, on = 100 link, blink = activity + * GT_LED_100_LINK - off = no link, on = 100 link + * GT_LED_1000_LINK_ACT - off = no link, on = 1000 link, blink = activity + * GT_LED_1000_LINK - off = no link, on = 1000 link + * GT_LED_10_100_LINK_ACT - off = no link, on = 10 or 100 link, blink = activity + * GT_LED_10_100_LINK - off = no link, on = 10 or 100 link + * GT_LED_10_1000_LINK_ACT - off = no link, on = 10 or 1000 link, blink = activity + * GT_LED_10_1000_LINK - off = no link, on = 10 or 1000 link + * GT_LED_100_1000_LINK_ACT- off = no link, on = 100 or 1000 link, blink = activity + * GT_LED_100_1000_LINK - off = no link, on = 100 or 1000 link + * GT_LED_SPECIAL - special leds + * GT_LED_DUPLEX_COL - off = half duplx, on = full duplex, blink = collision + * GT_LED_ACTIVITY - off = no link, blink on = activity + * GT_LED_PTP_ACT - blink on = PTP activity + * GT_LED_FORCE_BLINK - force blink + * GT_LED_FORCE_OFF - force off + * GT_LED_FORCE_ON - force on +*/ +#define GT_LED_LINK_ACT_SPEED 1 +#define GT_LED_LINK_ACT 2 +#define GT_LED_LINK 3 +#define GT_LED_10_LINK_ACT 4 +#define GT_LED_10_LINK 5 +#define GT_LED_100_LINK_ACT 6 +#define GT_LED_100_LINK 7 +#define GT_LED_1000_LINK_ACT 8 +#define GT_LED_1000_LINK 9 +#define GT_LED_10_100_LINK_ACT 10 +#define GT_LED_10_100_LINK 11 +#define GT_LED_10_1000_LINK_ACT 12 +#define GT_LED_10_1000_LINK 13 +#define GT_LED_100_1000_LINK_ACT 14 +#define GT_LED_100_1000_LINK 15 +#define GT_LED_SPECIAL 16 +#define GT_LED_DUPLEX_COL 17 +#define GT_LED_ACTIVITY 18 +#define GT_LED_PTP_ACT 19 +#define GT_LED_FORCE_BLINK 20 +#define GT_LED_FORCE_OFF 21 +#define GT_LED_FORCE_ON 22 +#define GT_LED_RESERVE 23 + + +/* + * typedef: enum GT_LED_CFG + * + * Description: Enumeration for LED configuration type + * + * Enumerations: + * GT_LED_CFG_LED0 - read/write led0 value (GT_LED_xxx definition) + * GT_LED_CFG_LED1 - read/write led1 value + * GT_LED_CFG_LED2 - read/write led2 value + * GT_LED_CFG_LED3 - read/write led3 value + * GT_LED_CFG_PULSE_STRETCH - read/write pulse stretch (0 ~ 4) + * GT_LED_CFG_BLINK_RATE - read/write blink rate (0 ~ 5) + * GT_LED_CFG_SPECIAL_CONTROL - read/write special control (port vector) + */ +typedef enum +{ + GT_LED_CFG_LED0, + GT_LED_CFG_LED1, + GT_LED_CFG_LED2, + GT_LED_CFG_LED3, + GT_LED_CFG_PULSE_STRETCH, + GT_LED_CFG_BLINK_RATE, + GT_LED_CFG_SPECIAL_CONTROL +} GT_LED_CFG; + + +/* + * typedef: enum GT_AVB_RECOVERED_CLOCK + * + * Description: Enumeration for recovered clock type + * + * Enumerations: + * GT_PRIMARY_RECOVERED_CLOCK - primary recovered clock + * GT_SECONDARY_RECOVERED_CLOCK - secondary recovered clock + */ +typedef enum +{ + GT_PRIMARY_RECOVERED_CLOCK, + GT_SECONDARY_RECOVERED_CLOCK +} GT_AVB_RECOVERED_CLOCK; + + +/* Define QAV interrupt bits */ + +#define GT_QAV_INT_STATUS_ENQ_LMT_BIT 0x8000 /* EnQ Limit Interrupt Enable */ +#define GT_QAV_INT_STATUS_ISO_DEL_BIT 0x0400 /* Iso Delay Interrupt Enable */ +#define GT_QAV_INT_STATUS_ISO_DIS_BIT 0x0200 /* Iso Discard Interrupt Enable */ +#define GT_QAV_INT_STATUS_ISO_LIMIT_EX_BIT 0x0100 /* Iso Packet Memory Exceeded Interrupt Enable */ + +#define GT_QAV_INT_ENABLE_ENQ_LMT_BIT 0x80 /* EnQ Limit Interrupt Enable */ +#define GT_QAV_INT_ENABLE_ISO_DEL_BIT 0x04 /* Iso Delay Interrupt Enable */ +#define GT_QAV_INT_ENABLE_ISO_DIS_BIT 0x02 /* Iso Discard Interrupt Enable */ +#define GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT 0x01 /* Iso Packet Memory Exceeded Interrupt Enable */ + + +/* + * Typedef: enum GT_EEPROM_OPERATION + * + * Description: Defines the EEPROM Operation type + * + * Fields: + * PTP_WRITE_DATA - Write data to the EEPROM register + * PTP_READ_DATA - Read data from EEPROM register + * PTP_RESTART - Restart EEPROM oprition + */ +typedef enum +{ + GT_EEPROM_NO_OP = 0x0, + GT_EEPROM_WRITE_DATA = 0x3, + GT_EEPROM_READ_DATA = 0x4, + GT_EEPROM_RESTART = 0x6, + GT_EEPROM_HALT = 0x7, +} GT_EEPROM_OPERATION; + + +/* + * typedef: struct GT_EEPROM_OP_DATA + * + * Description: data required by EEPROM Operation + * + * Fields: + * eepromPort - physical port of the device + * eepromAddr - register address + * eepromData - data for ptp register. + */ +typedef struct +{ + GT_U32 eepromPort; + GT_U32 eepromBlock; + GT_U32 eepromAddr; + GT_U32 eepromData; +} GT_EEPROM_OP_DATA; + +#define GT_EEPROM_OP_ST_RUNNING_MASK 0x800 +#define GT_EEPROM_OP_ST_WRITE_EN_MASK 0x400 + +#define GT_SCRAT_MISC_REG_SCRAT_0 0x00 /* Scratch Byte 0 */ +#define GT_SCRAT_MISC_REG_SCRAT_1 0x01 /* Scratch Byte 1 */ +#define GT_SCRAT_MISC_REG_GPIO_CFG 0x60 /* GPIO Configuration */ + /* 0x61 = Reserved for future use */ +#define GT_SCRAT_MISC_REG_GPIO_DIR 0x62 /* GPIO Direction */ +#define GT_SCRAT_MISC_REG_GPIO_DAT 0x63 /* GPIO Data */ +#define GT_SCRAT_MISC_REG_CFG_DAT0 0x70 /* CONFIG Data 0 */ +#define GT_SCRAT_MISC_REG_CFG_DAT1 0x71 /* CONFIG Data 1 */ +#define GT_SCRAT_MISC_REG_CFG_DAT2 0x72 /* CONFIG Data 2 */ +#define GT_SCRAT_MISC_REG_CFG_DAT3 0x73 /* CONFIG Data 3 */ +#define GT_SCRAT_MISC_REG_SYNCE 0x7C /* SyncE & TAICLK125’s Drive */ +#define GT_SCRAT_MISC_REG_P5_CLK 0x7D /* P5’s & CLK125’s Clock Drive */ +#define GT_SCRAT_MISC_REG_P6_CLK 0x7E /* P6’s Clock Drive */ +#define GT_SCRAT_MISC_REG_EEPROM 0x7F /* EEPROM Pad drive */ +#define GT_SCRAT_MISC_REG_MAX 0x80 /* Maximun register pointer */ + +#define GT_GPIO_BIT_0 0x1 +#define GT_GPIO_BIT_1 0x2 +#define GT_GPIO_BIT_2 0x4 +#define GT_GPIO_BIT_3 0x8 +#define GT_GPIO_BIT_4 0x10 +#define GT_GPIO_BIT_5 0x20 +#define GT_GPIO_BIT_6 0x40 + +typedef struct +{ + GT_U8 user : 3; + GT_U8 addr : 5; +}GT_CONFIG_DATA_0; + +typedef struct +{ + GT_U8 led : 2; + GT_U8 fourcol : 1; + GT_U8 normCx : 1; + GT_U8 jumbo : 1; + GT_U8 ee_we : 1; + GT_U8 fd_flow : 1; + GT_U8 hd_flow : 1; +}GT_CONFIG_DATA_1; + +typedef struct +{ + GT_U8 p5_mod : 3; + GT_U8 bit4 : 1; + GT_U8 p6_mod : 3; +}GT_CONFIG_DATA_2; + +typedef struct +{ + GT_U8 rmu_mod : 2; +}GT_CONFIG_DATA_3; + +typedef struct +{ + union { + GT_U8 Byte; + GT_CONFIG_DATA_0 Data; + } cfgData0; + union { + GT_U8 Byte; + GT_CONFIG_DATA_0 Data; + } cfgData1; + union { + GT_U8 Byte; + GT_CONFIG_DATA_0 Data; + } cfgData2; + union { + GT_U8 Byte; + GT_CONFIG_DATA_0 Data; + } cfgData3; +}GT_CONFIG_DATA; + + +/* definition for Trunking */ +#define IS_TRUNK_ID_VALID(_dev, _id) (((_id) < 16) ? 1 : 0) + + +/* definition for device scan mode */ +#define SMI_AUTO_SCAN_MODE 0 /* Scan 0 or 0x10 base address to find the QD */ +#define SMI_MANUAL_MODE 1 /* Use QD located at manually defined base addr */ +#define SMI_MULTI_ADDR_MODE 2 /* Use QD at base addr and use indirect access */ +typedef struct +{ + GT_U32 scanMode; /* check definition for device scan mode */ + GT_U32 baseAddr; /* meaningful if scanMode is not SMI_AUTO_SCAN_MODE */ +} GT_SCAN_MODE; + + +#define GT_SKIP_INIT_SETUP 0x736b6970 + +/* + * Typedef: struct GT_SYS_CONFIG + * + * Description: System configuration Parameters struct. + * + * Fields: + * devNum - Switch Device Number + * cpuPortNum - The physical port used to connect the device to CPU. + * This is the port to which packets destined to CPU are + * forwarded. + * initPorts - Whether to initialize the ports state. + * GT_FALSE - leave in default state. + * GT_TRUE - Initialize to Forwarding state. + * skipInitSetup - skip init setup, if value is GT_SKIP_INIT_SETUP + * perform init setup, otherwise + * Initializing port state is not affected by this variable. + * BSPFunctions - Group of BSP specific functions. + * SMI Read/Write and Semaphore Related functions. + */ +typedef struct +{ + GT_U8 devNum; + GT_U8 cpuPortNum; + GT_BOOL initPorts; + BSP_FUNCTIONS BSPFunctions; + GT_SCAN_MODE mode; + GT_U32 skipInitSetup; +}GT_SYS_CONFIG; + + + +/* + * Typedef: struct GT_QD_DEV + * + * Description: Includes Tapi layer switch configuration data. + * + * Fields: + * deviceId - The device type identifier. + * revision - The device revision number. + * baseRegAddr - Switch Base Register address. + * numOfPorts - Number of active ports. + * maxPorts - max ports. This field is only for driver's use. + * cpuPortNum - Logical port number whose physical port is connected to the CPU. + * maxPhyNum - max configurable Phy address. + * stpMode - current switch STP mode (0 none, 1 en, 2 dis) + * accessMode - shows how to find and access the device. + * phyAddr - SMI address used to access Switch registers(only for SMI_MULTI_ADDR_MODE). + * validPortVec - valid port list in vector format + * validPhyVec - valid phy list in vector format + * validSerdesVec - valid serdes list in vector format + * devGroup - the device group + * devName - name of the device + * devStorage - driver internal use (hold various temp information) + * multiAddrSem - Semaphore for Accessing SMI Device + * atuRegsSem - Semaphore for ATU access + * vtuRegsSem - Semaphore for VTU access + * statsRegsSem - Semaphore for RMON counter access + * pirlRegsSem - Semaphore for PIRL Resource access + * ptpRegsSem - Semaphore for PTP Resource access + * tblRegsSem - Semaphore for various Table Resource access, + * such as Trunk Tables and Device Table + * eepromRegsSem - Semaphore for eeprom control access + * phyRegsSem - Semaphore for PHY Device access + * fgtReadMii - platform specific SMI register Read function + * fgtWriteMii - platform specific SMI register Write function + * semCreate - function to create semapore + * semDelete - function to delete the semapore + * semTake - function to get a semapore + * semGive - function to return semaphore + * appData - application data that user may use + */ +struct _GT_QD_DEV +{ + GT_DEVICE deviceId; + GT_LPORT cpuPortNum; + GT_U8 revision; + GT_U8 devNum; + GT_U8 devEnabled; + GT_U8 baseRegAddr; + GT_U8 numOfPorts; + GT_U8 maxPorts; + GT_U8 maxPhyNum; + GT_U8 stpMode; + GT_U8 accessMode; + GT_U8 phyAddr; + GT_U16 reserved; + GT_U16 validPortVec; + GT_U16 validPhyVec; + GT_U16 validSerdesVec; + GT_U16 devGroup; + GT_U32 devName; + GT_U32 devStorage; + GT_SEM multiAddrSem; + GT_SEM atuRegsSem; + GT_SEM vtuRegsSem; + GT_SEM statsRegsSem; + GT_SEM pirlRegsSem; + GT_SEM ptpRegsSem; + GT_SEM tblRegsSem; + GT_SEM eepromRegsSem; + GT_SEM phyRegsSem; + + FGT_READ_MII fgtReadMii; + FGT_WRITE_MII fgtWriteMii; + + FGT_SEM_CREATE semCreate; /* create semaphore */ + FGT_SEM_DELETE semDelete; /* delete the semaphore */ + FGT_SEM_TAKE semTake; /* try to get a semaphore */ + FGT_SEM_GIVE semGive; /* return semaphore */ + void* appData; + +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* __msApi_h */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApi.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApi.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApi.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApi.h 2011-04-04 13:57:35.045596301 -0400 @@ -0,0 +1,22 @@ +#include + +/******************************************************************************** +* msApi.h +* +* DESCRIPTION: +* API definitions for QuarterDeck Device +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApi_h +#define __msApi_h + +#include +#include +#include + +#endif /* __msApi_h */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiMadConfig.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiMadConfig.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiMadConfig.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiMadConfig.h 2011-04-04 13:57:35.045596301 -0400 @@ -0,0 +1,31 @@ +#include + +/******************************************************************************** +* msApiMadConfig.h +* +* DESCRIPTION: +* Marvell Alaska Device (MAD) Configuration header file +* If DSDT does not need to load MAD driver for internal Gigabit Phy, +* MAD_INCLUDE should be undefined. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApiMadConfig_h +#define __msApiMadConfig_h + +#define MAD_INCLUDE + +/* + * uncomment the following #undef for DSDT not to include MAD +*/ +/* #undef MAD_INCLUDE */ + +#ifdef MAD_INCLUDE +#include +#endif + +#endif /* __msApiMadConfig_h */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiPrototype.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiPrototype.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiPrototype.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiPrototype.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,20761 @@ +#include + +/******************************************************************************** +* msApiPrototype.h +* +* DESCRIPTION: +* API Prototypes for QuarterDeck Device +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApiPrototype_h +#define __msApiPrototype_h + +#ifdef __cplusplus +extern "C" { +#endif + + +/* gtBrgFdb.c */ + +/******************************************************************************* +* gfdbSetAtuSize +* +* DESCRIPTION: +* Sets the Mac address table size. +* +* INPUTS: +* size - Mac address table size. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetAtuSize +( + IN GT_QD_DEV *dev, + IN ATU_SIZE size +); + + +/******************************************************************************* +* gfdbGetAgingTimeRange +* +* DESCRIPTION: +* Gets the maximal and minimum age times that the hardware can support. +* +* INPUTS: +* None. +* +* OUTPUTS: +* maxTimeout - max aging time in secounds. +* minTimeout - min aging time in secounds. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetAgingTimeRange +( + IN GT_QD_DEV *dev, + OUT GT_U32 *maxTimeout, + OUT GT_U32 *minTimeout +); + +/******************************************************************************* +* gfdbGetAgingTimeout +* +* DESCRIPTION: +* Gets the timeout period in seconds for aging out dynamically learned +* forwarding information. The returned value may not be the same as the value +* programmed with . Please refer to the description of +* . +* +* INPUTS: +* None. +* +* OUTPUTS: +* timeout - aging time in seconds. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetAgingTimeout +( + IN GT_QD_DEV *dev, + OUT GT_U32 *timeout +); + +/******************************************************************************* +* gfdbSetAgingTimeout +* +* DESCRIPTION: +* Sets the timeout period in seconds for aging out dynamically learned +* forwarding information. The standard recommends 300 sec. +* Supported aging timeout values are multiple of time-base, where time-base +* is either 15 or 16 seconds, depending on the Switch device. For example, +* 88E6063 uses time-base 16, and so supported aging timeouts are 0,16,32, +* 48,..., and 4080. If unsupported timeout value (bigger than 16) is used, +* the value will be rounded to the nearest supported value smaller than the +* given timeout. If the given timeout is less than 16, minimum timeout value +* 16 will be used instead. E.g.) 35 becomes 32 and 5 becomes 16. +* function can be used to find the time-base. +* +* INPUTS: +* timeout - aging time in seconds. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetAgingTimeout +( + IN GT_QD_DEV *dev, + IN GT_U32 timeout +); + + + +/******************************************************************************* +* gfdbGetAtuDynamicCount +* +* DESCRIPTION: +* Gets the current number of dynamic unicast entries in this +* Filtering Database. +* +* INPUTS: +* None. +* +* OUTPUTS: +* numDynEntries - number of dynamic entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - vlan does not exist. +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuDynamicCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numDynEntries +); + + + +/******************************************************************************* +* gfdbGetAtuEntryFirst +* +* DESCRIPTION: +* Gets first lexicographic MAC address entry from the ATU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* atuEntry - match Address translate unit entry. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - table is empty. +* +* COMMENTS: +* Search starts from Mac[00:00:00:00:00:00] +* +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuEntryFirst +( + IN GT_QD_DEV *dev, + OUT GT_ATU_ENTRY *atuEntry +); + + + +/******************************************************************************* +* gfdbGetAtuEntryNext +* +* DESCRIPTION: +* Gets next lexicographic MAC address from the specified Mac Addr. +* +* INPUTS: +* atuEntry - the Mac Address to start the search. +* +* OUTPUTS: +* atuEntry - match Address translate unit entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* Search starts from atu.macAddr[xx:xx:xx:xx:xx:xx] specified by the +* user. +* +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_ATU_ENTRY *atuEntry +); + + + +/******************************************************************************* +* gfdbFindAtuMacEntry +* +* DESCRIPTION: +* Find FDB entry for specific MAC address from the ATU. +* +* INPUTS: +* atuEntry - the Mac address to search. +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* atuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbFindAtuMacEntry +( + IN GT_QD_DEV *dev, + INOUT GT_ATU_ENTRY *atuEntry, + OUT GT_BOOL *found +); + + + +/******************************************************************************* +* gfdbFlush +* +* DESCRIPTION: +* This routine flush all or unblocked addresses from the MAC Address +* Table. +* +* INPUTS: +* flushCmd - the flush operation type. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbFlush +( + IN GT_QD_DEV *dev, + IN GT_FLUSH_CMD flushCmd +); + +/******************************************************************************* +* gfdbFlushInDB +* +* DESCRIPTION: +* This routine flush all or unblocked addresses from the particular +* ATU Database (DBNum). If multiple address databases are being used, this +* API can be used to flush entries in a particular DBNum database. +* +* INPUTS: +* flushCmd - the flush operation type. +* DBNum - ATU MAC Address Database Number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbFlushInDB +( + IN GT_QD_DEV *dev, + IN GT_FLUSH_CMD flushCmd, + IN GT_U32 DBNum +); + +/******************************************************************************* +* gfdbAddMacEntry +* +* DESCRIPTION: +* Creates the new entry in MAC address table. +* +* INPUTS: +* macEntry - mac address entry to insert to the ATU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* GT_OUT_OF_CPU_MEM - oaMalloc failed +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbAddMacEntry +( + IN GT_QD_DEV *dev, + IN GT_ATU_ENTRY *macEntry +); + + + +/******************************************************************************* +* gfdbDelMacEntry +* +* DESCRIPTION: +* Deletes MAC address entry. +* +* INPUTS: +* macAddress - mac address. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* For SVL mode vlan Id is ignored. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbDelMacEntry +( + IN GT_QD_DEV *dev, + IN GT_ETHERADDR *macAddress +); + +/******************************************************************************* +* gfdbDelAtuEntry +* +* DESCRIPTION: +* Deletes ATU entry. +* +* INPUTS: +* atuEntry - the ATU entry to be deleted. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbDelAtuEntry +( + IN GT_QD_DEV *dev, + IN GT_ATU_ENTRY *atuEntry +); + +/******************************************************************************* +* gfdbLearnEnable +* +* DESCRIPTION: +* Enable/disable automatic learning of new source MAC addresses on port +* ingress. +* +* INPUTS: +* en - GT_TRUE for enable or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbLearnEnable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + + +/******************************************************************************* +* gfdbGetLearnEnable +* +* DESCRIPTION: +* Get automatic learning status of new source MAC addresses on port ingress. +* +* INPUTS: +* None +* +* OUTPUTS: +* en - GT_TRUE if enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetLearnEnable +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gstpSetMode +* +* DESCRIPTION: +* This routine Enable the Spanning tree. +* +* INPUTS: +* en - GT_TRUE for enable, GT_FALSE for disable. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* when enabled, this function sets all port to blocking state, and inserts +* the BPDU MAC into the ATU to be captured to CPU, on disable all port are +* being modified to be in forwarding state. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpSetMode +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gstpSetPortState +* +* DESCRIPTION: +* This routine set the port state. +* +* INPUTS: +* port - the logical port number. +* state - the port state to set. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpSetPortState +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_STP_STATE state +); + + + +/******************************************************************************* +* gstpGetPortState +* +* DESCRIPTION: +* This routine returns the port state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - the current port state. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpGetPortState +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_STP_STATE *state +); + +/******************************************************************************* +* gprtSetEgressMode +* +* DESCRIPTION: +* This routine set the egress mode. +* +* INPUTS: +* port - the logical port number. +* mode - the egress mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EGRESS_MODE mode +); + + + +/******************************************************************************* +* gprtGetEgressMode +* +* DESCRIPTION: +* This routine get the egress mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the egress mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EGRESS_MODE *mode +); + + + +/******************************************************************************* +* gprtSetVlanTunnel +* +* DESCRIPTION: +* This routine sets the vlan tunnel mode. +* +* INPUTS: +* port - the logical port number. +* mode - the vlan tunnel mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetVlanTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + + +/******************************************************************************* +* gprtGetVlanTunnel +* +* DESCRIPTION: +* This routine get the vlan tunnel mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the vlan tunnel mode.. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetVlanTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/******************************************************************************* +* gprtSetIGMPSnoop +* +* DESCRIPTION: +* This routine set the IGMP Snoop. When set to one and this port receives +* IGMP frame, the frame is switched to the CPU port, overriding all other +* switching decisions, with exception for CPU's Trailer. +* CPU port is determined by the Ingress Mode bits. A port is considered +* the CPU port if its Ingress Mode are either GT_TRAILER_INGRESS or +* GT_CPUPORT_INGRESS. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for IGMP Snoop or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIGMPSnoop +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetIGMPSnoop +* +* DESCRIPTION: +* This routine get the IGMP Snoop mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: IGMP Snoop enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIGMPSnoop +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/* the following two APIs are added to support clippership */ + +/******************************************************************************* +* gprtSetHeaderMode +* +* DESCRIPTION: +* This routine set ingress and egress header mode of a switch port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for header mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetHeaderMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetHeaderMode +* +* DESCRIPTION: +* This routine gets ingress and egress header mode of a switch port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetHeaderMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/******************************************************************************* +* gprtSetProtectedMode +* +* DESCRIPTION: +* This routine set protected mode of a switch port. +* When this mode is set to GT_TRUE, frames are allowed to egress port +* defined by the 802.1Q VLAN membership for the frame's VID 'AND' +* by the port's VLANTable if 802.1Q is enabled on the port. Both must +* allow the frame to Egress. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for protected mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetProtectedMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetProtectedMode +* +* DESCRIPTION: +* This routine gets protected mode of a switch port. +* When this mode is set to GT_TRUE, frames are allowed to egress port +* defined by the 802.1Q VLAN membership for the frame's VID 'AND' +* by the port's VLANTable if 802.1Q is enabled on the port. Both must +* allow the frame to Egress. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetProtectedMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetForwardUnknown +* +* DESCRIPTION: +* This routine set Forward Unknown mode of a switch port. +* When this mode is set to GT_TRUE, normal switch operation occurs. +* When this mode is set to GT_FALSE, unicast frame with unknown DA addresses +* will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for protected mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetForwardUnknown +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetForwardUnknown +* +* DESCRIPTION: +* This routine gets Forward Unknown mode of a switch port. +* When this mode is set to GT_TRUE, normal switch operation occurs. +* When this mode is set to GT_FALSE, unicast frame with unknown DA addresses +* will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetForwardUnknown +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtGetSwitchReg +* +* DESCRIPTION: +* This routine reads Switch Port Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSwitchReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + OUT GT_U16 *data +); + +/******************************************************************************* +* gprtSetSwitchReg +* +* DESCRIPTION: +* This routine writes Switch Port Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetSwitchReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* gprtGetGlobalReg +* +* DESCRIPTION: +* This routine reads Switch Global Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + OUT GT_U16 *data +); + +/******************************************************************************* +* gprtSetGlobalReg +* +* DESCRIPTION: +* This routine writes Switch Global Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + IN GT_U16 data +); + + + +/******************************************************************************* +* gvlnSetPortVlanPorts +* +* DESCRIPTION: +* This routine sets the port VLAN group port membership list. +* +* INPUTS: +* port - logical port number to set. +* memPorts - array of logical ports. +* memPortsLen - number of members in memPorts array +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanPorts +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LPORT memPorts[], + IN GT_U8 memPortsLen +); + + + +/******************************************************************************* +* gvlnGetPortVlanPorts +* +* DESCRIPTION: +* This routine gets the port VLAN group port membership list. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* memPorts - array of logical ports. +* memPortsLen - number of members in memPorts array +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanPorts +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_LPORT memPorts[], + OUT GT_U8 *memPortsLen +); + + + + +/******************************************************************************* +* gvlnSetPortUserPriLsb +* +* DESCRIPTION: +* This routine Set the user priority (VPT) LSB bit, to be added to the +* user priority on the egress. +* +* INPUTS: +* port - logical port number to set. +* userPriLsb - GT_TRUE for 1, GT_FALSE for 0. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortUserPriLsb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL userPriLsb +); + + + +/******************************************************************************* +* gvlnGetPortUserPriLsb +* +* DESCRIPTION: +* This routine gets the user priority (VPT) LSB bit. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* userPriLsb - GT_TRUE for 1, GT_FALSE for 0. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortUserPriLsb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *userPriLsb +); + + +/******************************************************************************* +* gvlnSetPortVid +* +* DESCRIPTION: +* This routine Set the port default vlan id. +* +* INPUTS: +* port - logical port number to set. +* vid - the port vlan id. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVid +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 vid +); + + +/******************************************************************************* +* gvlnGetPortVid +* +* DESCRIPTION: +* This routine Get the port default vlan id. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* vid - the port vlan id. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVid +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *vid +); + +/******************************************************************************* +* gvlnSetPortVlanDBNum +* +* DESCRIPTION: +* This routine sets the port VLAN database number (DBNum). +* +* INPUTS: +* port - logical port number to set. +* DBNum - database number for this port +* +* OUTPUTS: +* None. +* +* RETURNS:IN GT_INGRESS_MODE mode +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanDBNum +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 DBNum +); + + +/******************************************************************************* +* gvlnGetPortVlanDBNum +* +* DESCRIPTION:IN GT_INGRESS_MODE mode +* This routine gets the port VLAN database number (DBNum). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* DBNum - database number for this port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanDBNum +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *DBNum +); + +/******************************************************************** +* gvlnSetPortVlanDot1qMode +* +* DESCRIPTION: +* This routine sets the port 802.1q mode (11:10) +* +* INPUTS: +* port - logical port number to set. +* mode - 802.1q mode for this port +* +* OUTPUTS: +* None. +* +* RETURNS:IN GT_INGRESS_MODE mode +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanDot1qMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_DOT1Q_MODE mode +); + +/******************************************************************************* +* gvlnGetPortVlanDot1qMode +* +* DESCRIPTION: +* This routine gets the port 802.1q mode (bit 11:10). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* mode - 802.1q mode for this port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanDot1qMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_DOT1Q_MODE *mode +); + + +/******************************************************************** +* gvlnSetPortVlanForceDefaultVID +* +* DESCRIPTION: +* This routine sets the port 802.1q mode (11:10) +* +* INPUTS: +* port - logical port number to set. +* mode - GT_TRUE, force to use default VID +* GT_FAULSE, otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanForceDefaultVID +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gvlnGetPortVlanForceDefaultVID +* +* DESCRIPTION: +* This routine gets the port mode for ForceDefaultVID (bit 12). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* mode - ForceDefaultVID mode for this port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanForceDefaultVID +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* eventSetActive +* +* DESCRIPTION: +* This routine enables/disables the receive of an hardware driven event. +* +* INPUTS: +* eventType - the event type. any combination of the folowing: +* GT_STATS_DONE, GT_VTU_PROB, GT_VTU_DONE, GT_ATU_FULL, +* GT_ATU_DONE, GT_PHY_INTERRUPT, GT_EE_INTERRUPT, and GT_DEVICE_INT +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Each switch device has its own set of event Types. Please refer to the +* device datasheet for the list of event types that the device supports. +* +*******************************************************************************/ +GT_STATUS eventSetActive +( + IN GT_QD_DEV *dev, + IN GT_U32 eventType +); + +/******************************************************************************* +* eventGetIntStatus +* +* DESCRIPTION: +* This routine reads an hardware driven event status. +* +* INPUTS: +* None. +* +* OUTPUTS: +* intCause - It provides the source of interrupt of the following: +* GT_STATS_DONE, GT_VTU_PROB, GT_VTU_DONE, GT_ATU_FULL, +* GT_ATU_DONE, GT_PHY_INTERRUPT, and GT_EE_INTERRUPT. +* For Gigabit Switch, GT_ATU_FULL is replaced with GT_ATU_FULL and +* GT_PHY_INTERRUPT is not supported. +* GT_DEVICE_INT may not be available on the devices, so please refer +* to the datasheet for details. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS eventGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_U16 *intCause +); + +/******************************************************************************* +* gvtuGetIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of VTU interrupt occured +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_MEMEBER_VIOLATION, +* GT_MISS_VIOLATION, +* GT_FULL_VIOLATION +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* FULL_VIOLATION is only for Fast Ethernet Switch (not for Gigabit Switch). +* +*******************************************************************************/ + +GT_STATUS gvtuGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +); + +/******************************************************************************* +* gvtuGetEntryCount +* +* DESCRIPTION: +* Gets the current number of entries in the VTU table +* +* INPUTS: +* None. +* +* OUTPUTS: +* numEntries - number of VTU entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - vlan does not exist. +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numEntries +); + +/******************************************************************************* +* gvtuGetEntryFirst +* +* DESCRIPTION: +* Gets first lexicographic entry from the VTU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuEntry - match VTU entry. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - table is empty. +* +* COMMENTS: +* Search starts from vid of all one's +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryFirst +( + IN GT_QD_DEV *dev, + OUT GT_VTU_ENTRY *vtuEntry +); + +/******************************************************************************* +* gvtuGetEntryNext +* +* DESCRIPTION: +* Gets next lexicographic VTU entry from the specified VID. +* +* INPUTS: +* vtuEntry - the VID to start the search. +* +* OUTPUTS: +* vtuEntry - match VTU entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* Search starts from the VID specified by the user. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_VTU_ENTRY *vtuEntry +); + +/******************************************************************************* +* gvtuFindVidEntry +* +* DESCRIPTION: +* Find VTU entry for a specific VID, it will return the entry, if found, +* along with its associated data +* +* INPUTS: +* vtuEntry - contains the VID to search for. +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* vtuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuFindVidEntry +( + IN GT_QD_DEV *dev, + INOUT GT_VTU_ENTRY *vtuEntry, + OUT GT_BOOL *found +); + +/******************************************************************************* +* gvtuFlush +* +* DESCRIPTION: +* This routine removes all entries from VTU Table. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuFlush +( + IN GT_QD_DEV *dev +); + +/******************************************************************************* +* gvtuAddEntry +* +* DESCRIPTION: +* Creates the new entry in VTU table based on user input. +* +* INPUTS: +* vtuEntry - vtu entry to insert to the VTU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_FULL - vtu table is full +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuAddEntry +( + IN GT_QD_DEV *dev, + IN GT_VTU_ENTRY *vtuEntry +); + +/******************************************************************************* +* gvtuDelEntry +* +* DESCRIPTION: +* Deletes VTU entry specified by user. +* +* INPUTS: +* vtuEntry - the VTU entry to be deleted +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuDelEntry +( + IN GT_QD_DEV *dev, + IN GT_VTU_ENTRY *vtuEntry +); + +/* gtPhyCtrl.c */ + +/******************************************************************************* +* gprtPhyReset +* +* DESCRIPTION: +* This routine preforms PHY reset. +* After reset, phy will be in Autonegotiation mode. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* data sheet register 0.15 - Reset +* data sheet register 0.13 - Speed +* data sheet register 0.12 - Autonegotiation +* data sheet register 0.8 - Duplex Mode +* +*******************************************************************************/ + +GT_STATUS gprtPhyReset +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + + +/******************************************************************************* +* gprtSetPortLoopback +* +* DESCRIPTION: +* Enable/Disable Internal Port Loopback. +* For 10/100 Fast Ethernet PHY, speed of Loopback is determined as follows: +* If Auto-Negotiation is enabled, this routine disables Auto-Negotiation and +* forces speed to be 10Mbps. +* If Auto-Negotiation is disabled, the forced speed is used. +* Disabling Loopback simply clears bit 14 of control register(0.14). Therefore, +* it is recommended to call gprtSetPortAutoMode for PHY configuration after +* Loopback test. +* For 10/100/1000 Gigagbit Ethernet PHY, speed of Loopback is determined as follows: +* If Auto-Negotiation is enabled and Link is active, the current speed is used. +* If Auto-Negotiation is disabled, the forced speed is used. +* All other cases, default MAC Interface speed is used. Please refer to the data +* sheet for the information of the default MAC Interface speed. +* +* INPUTS: +* port - logical port number +* enable - If GT_TRUE, enable loopback mode +* If GT_FALSE, disable loopback mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.14 - Loop_back +* +*******************************************************************************/ + +GT_STATUS gprtSetPortLoopback +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL enable +); + + +/******************************************************************************* +* gprtSetPortSpeed +* +* DESCRIPTION: +* Sets speed for a specific logical port. This function will keep the duplex +* mode and loopback mode to the previous value, but disable others, such as +* Autonegotiation. +* +* INPUTS: +* port - logical port number +* speed - port speed. +* PHY_SPEED_10_MBPS for 10Mbps +* PHY_SPEED_100_MBPS for 100Mbps +* PHY_SPEED_1000_MBPS for 1000Mbps +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.13 - Speed Selection (LSB) +* data sheet register 0.6 - Speed Selection (MSB) +* +*******************************************************************************/ + +GT_STATUS gprtSetPortSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PHY_SPEED speed +); + + +/******************************************************************************* +* gprtPortAutoNegEnable +* +* DESCRIPTION: +* Enable/disable an Auto-Negotiation for duplex mode on specific +* logical port. When Autonegotiation is disabled, phy will be in 10Mbps Half +* Duplex mode. Enabling Autonegotiation will set 100BASE-TX Full Duplex, +* 100BASE-TX Full Duplex, 100BASE-TX Full Duplex, and 100BASE-TX Full Duplex +* in AutoNegotiation Advertisement register. +* +* INPUTS: +* port - logical port number +* state - GT_TRUE for enable Auto-Negotiation for duplex mode, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.12 - Auto-Negotiation Enable +* data sheet register 4.8, 4.7, 4.6, 4.5 - Auto-Negotiation Advertisement +* +*******************************************************************************/ + +GT_STATUS gprtPortAutoNegEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + + +/******************************************************************************* +* gprtPortPowerDown +* +* DESCRIPTION: +* Enable/disable (power down) on specific logical port. When this function +* is called with normal operation request, phy will set to Autonegotiation +* mode. +* +* INPUTS: +* port - logical port number +* state - GT_TRUE: power down +* GT_FALSE: normal operation +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.11 - Power Down +* +*******************************************************************************/ + +GT_STATUS gprtPortPowerDown +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + + +/******************************************************************************* +* gprtPortRestartAutoNeg +* +* DESCRIPTION: +* Restart AutoNegotiation. If AutoNegotiation is not enabled, it'll enable +* it. Loopback and Power Down will be disabled by this routine. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.9 - Restart Auto-Negotiation +* +*******************************************************************************/ + +GT_STATUS gprtPortRestartAutoNeg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + + +/******************************************************************************* +* gprtSetPortDuplexMode +* +* DESCRIPTION: +* Sets duplex mode for a specific logical port. This function will keep +* the speed and loopback mode to the previous value, but disable others, +* such as Autonegotiation. +* +* INPUTS: +* port - logical port number +* dMode - dulpex mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.8 - Duplex Mode +* +*******************************************************************************/ + +GT_STATUS gprtSetPortDuplexMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL dMode +); + + +/******************************************************************************* +* gprtSetPortAutoMode +* +* DESCRIPTION: +* This routine sets up the port with given Auto Mode. +* Supported mode is as follows: +* - Auto for both speed and duplex. +* - Auto for speed only and Full duplex. +* - Auto for speed only and Half duplex. +* - Auto for duplex only and speed 1000Mbps. +* - Auto for duplex only and speed 100Mbps. +* - Auto for duplex only and speed 10Mbps. +* - Speed 1000Mbps and Full duplex. +* - Speed 1000Mbps and Half duplex. +* - Speed 100Mbps and Full duplex. +* - Speed 100Mbps and Half duplex. +* - Speed 10Mbps and Full duplex. +* - Speed 10Mbps and Half duplex. +* +* +* INPUTS: +* port - The logical port number +* mode - Auto Mode to be written +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* data sheet register 4.8, 4.7, 4.6, and 4.5 Autonegotiation Advertisement +* data sheet register 4.6, 4.5 Autonegotiation Advertisement for 1000BX +* data sheet register 9.9, 9.8 Autonegotiation Advertisement for 1000BT +*******************************************************************************/ + +GT_STATUS gprtSetPortAutoMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PHY_AUTO_MODE mode +); + +/******************************************************************************* +* gprtSetPause +* +* DESCRIPTION: +* This routine will set the pause bit in Autonegotiation Advertisement +* Register. And restart the autonegotiation. +* +* INPUTS: +* port - The logical port number +* state - GT_PHY_PAUSE_MODE enum value. +* GT_PHY_NO_PAUSE - disable pause +* GT_PHY_PAUSE - support pause +* GT_PHY_ASYMMETRIC_PAUSE - support asymmetric pause +* GT_PHY_BOTH_PAUSE - support both pause and asymmetric pause +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* data sheet register 4.10 Autonegotiation Advertisement Register +*******************************************************************************/ + +GT_STATUS gprtSetPause +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PHY_PAUSE_MODE state +); + +/******************************************************************************* +* gprtGetPhyReg +* +* DESCRIPTION: +* This routine reads Phy Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + OUT GT_U16 *data +); + +/******************************************************************************* +* gprtSetPhyReg +* +* DESCRIPTION: +* This routine writes Phy Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* gprtPhyIntEnable +* +* DESCRIPTION: +* Enable/Disable one PHY Interrupt +* This register determines whether the INT# pin is asserted when an interrupt +* event occurs. When an interrupt occurs, the corresponding bit is set and +* remains set until register 19 is read via the SMI. When interrupt enable +* bits are not set in register 18, interrupt status bits in register 19 are +* still set when the corresponding interrupt events occur. However, the INT# +* is not asserted. +* +* INPUTS: +* port - logical port number +* intType - the type of interrupt to enable/disable. any combination of +* GT_SPEED_CHANGED, +* GT_DUPLEX_CHANGED, +* GT_PAGE_RECEIVED, +* GT_AUTO_NEG_COMPLETED, +* GT_LINK_STATUS_CHANGED, +* GT_SYMBOL_ERROR, +* GT_FALSE_CARRIER, +* GT_FIFO_FLOW, +* GT_CROSSOVER_CHANGED, +* GT_POLARITY_CHANGED, and +* GT_JABBER +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* 88E3081 data sheet register 18 +* +*******************************************************************************/ + +GT_STATUS gprtPhyIntEnable +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_U16 intType +); + + +/******************************************************************************* +* gprtGetPhyIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of interrupt occured +* +* INPUTS: +* port - logical port number +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_SPEED_CHANGED, +* GT_DUPLEX_CHANGED, +* GT_PAGE_RECEIVED, +* GT_AUTO_NEG_COMPLETED, +* GT_LINK_STATUS_CHANGED, +* GT_SYMBOL_ERROR, +* GT_FALSE_CARRIER, +* GT_FIFO_FLOW, +* GT_CROSSOVER_CHANGED, +* GT_POLARITY_CHANGED, and +* GT_JABBER +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* 88E3081 data sheet register 19 +* +*******************************************************************************/ + +GT_STATUS gprtGetPhyIntStatus +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +OUT GT_U16* intType +); + +/******************************************************************************* +* gprtGetPhyIntPortSummary +* +* DESCRIPTION: +* Lists the ports that have active interrupts. It provides a quick way to +* isolate the interrupt so that the MAC or switch does not have to poll the +* interrupt status register (19) for all ports. Reading this register does not +* de-assert the INT# pin +* +* INPUTS: +* none +* +* OUTPUTS: +* GT_U8 *intPortMask - bit Mask with the bits set for the corresponding +* phys with active interrupt. E.g., the bit number 0 and 2 are set when +* port number 0 and 2 have active interrupt +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* 88E3081 data sheet register 20 +* +*******************************************************************************/ + +GT_STATUS gprtGetPhyIntPortSummary +( +IN GT_QD_DEV *dev, +OUT GT_U16 *intPortMask +); + + + +/******************************************************************************* +* gprtSetForceFc +* +* DESCRIPTION: +* This routine set the force flow control state. +* +* INPUTS: +* port - the logical port number. +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetForceFc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL force +); + + + +/******************************************************************************* +* gprtGetForceFc +* +* DESCRIPTION: +* This routine get the force flow control state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetForceFc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *force +); + + + +/******************************************************************************* +* gprtSetTrailerMode +* +* DESCRIPTION: +* This routine set the egress trailer mode. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for add trailer or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetTrailerMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + + +/******************************************************************************* +* gprtGetTrailerMode +* +* DESCRIPTION: +* This routine get the egress trailer mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for add trailer or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetTrailerMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gprtSetIngressMode +* +* DESCRIPTION: +* This routine set the ingress mode. +* +* INPUTS: +* port - the logical port number. +* mode - the ingress mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIngressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_INGRESS_MODE mode +); + + + +/******************************************************************************* +* gprtGetIngressMode +* +* DESCRIPTION: +* This routine get the ingress mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the ingress mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIngressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_INGRESS_MODE *mode +); + + + +/******************************************************************************* +* gprtSetMcRateLimit +* +* DESCRIPTION: +* This routine set the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* rate - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetMcRateLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_MC_RATE rate +); + + + +/******************************************************************************* +* gprtGetMcRateLimit +* +* DESCRIPTION: +* This routine Get the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* rate - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetMcRateLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_MC_RATE *rate +); + + + +/******************************************************************************* +* gprtSetCtrMode +* +* DESCRIPTION: +* This routine sets the port counters mode of operation. +* +* INPUTS: +* mode - the counter mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetCtrMode +( + IN GT_QD_DEV *dev, + IN GT_CTR_MODE mode +); + + + +/******************************************************************************* +* gprtClearAllCtr +* +* DESCRIPTION: +* This routine clears all port counters. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtClearAllCtr +( + IN GT_QD_DEV *dev +); + + +/******************************************************************************* +* gprtGetPortCtr +* +* DESCRIPTION: +* This routine gets the port counters. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* ctr - the counters value. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPortCtr +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_STAT *ctr +); + + + + +/******************************************************************************* +* gprtGetPartnerLinkPause +* +* DESCRIPTION: +* This routine retrives the link partner pause state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for enable or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPartnerLinkPause +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + + +/******************************************************************************* +* gprtGetSelfLinkPause +* +* DESCRIPTION: +* This routine retrives the link pause state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for enable or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSelfLinkPause +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + + +/******************************************************************************* +* gprtGetResolve +* +* DESCRIPTION: +* This routine retrives the resolve state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Done or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetResolve +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + + +/******************************************************************************* +* gprtGetLinkState +* +* DESCRIPTION: +* This routine retrives the link state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Up or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetLinkState +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + + +/******************************************************************************* +* gprtGetPortMode +* +* DESCRIPTION: +* This routine retrives the port mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for MII or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPortMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gprtGetPhyMode +* +* DESCRIPTION: +* This routine retrives the PHY mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for MII PHY or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gprtGetDuplex +* +* DESCRIPTION: +* This routine retrives the port duplex mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for Full or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDuplex +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gprtGetSpeed +* +* DESCRIPTION: +* This routine retrives the port speed. +* +* INPUTS: +* speed - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for 100Mb/s or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *speed +); + +/******************************************************************************* +* gprtSetDuplex +* +* DESCRIPTION: +* This routine sets the duplex mode of MII/SNI/RMII ports. +* +* INPUTS: +* port - the logical port number. +* (for FullSail, it will be port 2, and for ClipperShip, +* it could be either port 5 or port 6.) +* mode - GT_TRUE for Full Duplex, +* GT_FALSE for Half Duplex. +* +* OUTPUTS: None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDuplex +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + +/******************************************************************************* +* gqosSetPortDefaultTc +* +* DESCRIPTION: +* Sets the default traffic class for a specific port. +* +* INPUTS: +* port - logical port number +* trafClass - default traffic class of a port. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gcosSetPortDefaultTc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 trafClass +); + + +/******************************************************************************* +* gcosGetPortDefaultTc +* +* DESCRIPTION: +* Gets the default traffic class for a specific port. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* trafClass - default traffic class of a port. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gcosGetPortDefaultTc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U8 *trafClass +); + + +/******************************************************************************* +* gqosSetPrioMapRule +* +* DESCRIPTION: +* This routine sets priority mapping rule. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for user prio rule, GT_FALSE for otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetPrioMapRule +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + + +/******************************************************************************* +* gqosGetPrioMapRule +* +* DESCRIPTION: +* This routine get the priority mapping rule. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for user prio rule, GT_FALSE for otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetPrioMapRule +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gqosIpPrioMapEn +* +* DESCRIPTION: +* This routine enables the IP priority mapping. +* +* INPUTS: +* port - the logical port number. +* en - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosIpPrioMapEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gqosGetIpPrioMapEn +* +* DESCRIPTION: +* This routine return the IP priority mapping state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* en - GT_TRUE for user prio rule, GT_FALSE for otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetIpPrioMapEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + + + +/******************************************************************************* +* gqosUserPrioMapEn +* +* DESCRIPTION: +* This routine enables the user priority mapping. +* +* INPUTS: +* port - the logical port number. +* en - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosUserPrioMapEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gqosGetUserPrioMapEn +* +* DESCRIPTION: +* This routine return the user priority mapping state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* en - GT_TRUE for user prio rule, GT_FALSE for otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetUserPrioMapEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + + + +/******************************************************************************* +* gcosGetUserPrio2Tc +* +* DESCRIPTION: +* Gets the traffic class number for a specific 802.1p user priority. +* +* INPUTS: +* userPrior - user priority +* +* OUTPUTS: +* trClass - The Traffic Class the received frame is assigned. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* Table - UserPrio2Tc +* +*******************************************************************************/ +GT_STATUS gcosGetUserPrio2Tc +( + IN GT_QD_DEV *dev, + IN GT_U8 userPrior, + OUT GT_U8 *trClass +); + + +/******************************************************************************* +* gcosSetUserPrio2Tc +* +* DESCRIPTION: +* Sets the traffic class number for a specific 802.1p user priority. +* +* INPUTS: +* userPrior - user priority of a port. +* trClass - the Traffic Class the received frame is assigned. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* Table - UserPrio2Tc +* +*******************************************************************************/ +GT_STATUS gcosSetUserPrio2Tc +( + IN GT_QD_DEV *dev, + IN GT_U8 userPrior, + IN GT_U8 trClass +); + + +/******************************************************************************* +* gcosGetDscp2Tc +* +* DESCRIPTION: +* This routine retrieves the traffic class assigned for a specific +* IPv4 Dscp. +* +* INPUTS: +* dscp - the IPv4 frame dscp to query. +* +* OUTPUTS: +* trClass - The Traffic Class the received frame is assigned. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* Table - UserPrio2Tc +* +*******************************************************************************/ +GT_STATUS gcosGetDscp2Tc +( + IN GT_QD_DEV *dev, + IN GT_U8 dscp, + OUT GT_U8 *trClass +); + + +/******************************************************************************* +* gcosSetDscp2Tc +* +* DESCRIPTION: +* This routine sets the traffic class assigned for a specific +* IPv4 Dscp. +* +* INPUTS: +* dscp - the IPv4 frame dscp to map. +* trClass - the Traffic Class the received frame is assigned. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* Table - UserPrio2Tc +* +*******************************************************************************/ +GT_STATUS gcosSetDscp2Tc +( + IN GT_QD_DEV *dev, + IN GT_U8 dscp, + IN GT_U8 trClass +); + + +/******************************************************************************* +* qdLoadDriver +* +* DESCRIPTION: +* QuarterDeck Driver Initialization Routine. +* This is the first routine that needs be called by system software. +* It takes sysCfg from system software, and retures a pointer (*dev) +* to a data structure which includes infomation related to this QuarterDeck +* device. This pointer (*dev) is then used for all the API functions. +* +* INPUTS: +* sysCfg - Holds system configuration parameters. +* +* OUTPUTS: +* dev - Holds general system information. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_ALREADY_EXIST - if device already started +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* qdUnloadDriver is provided when the driver is not to be used anymore. +* +*******************************************************************************/ +GT_STATUS qdLoadDriver +( + IN GT_SYS_CONFIG *sysCfg, + OUT GT_QD_DEV *dev +); + + +/******************************************************************************* +* qdUnloadDriver +* +* DESCRIPTION: +* This function unloads the QuaterDeck Driver. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* 1. This function should be called only after successful execution of +* qdLoadDriver(). +* +*******************************************************************************/ +GT_STATUS qdUnloadDriver +( + IN GT_QD_DEV* dev +); + + +/******************************************************************************* +* sysEnable +* +* DESCRIPTION: +* This function enables the system for full operation. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS sysEnable +( + IN GT_QD_DEV* dev +); + + +/******************************************************************************* +* gsysSwReset +* +* DESCRIPTION: +* This routine preforms switch software reset. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSwReset +( + IN GT_QD_DEV* dev +); + + +/******************************************************************************* +* gsysSetDiscardExcessive +* +* DESCRIPTION: +* This routine set the Discard Excessive state. +* +* INPUTS: +* en - GT_TRUE Discard is enabled, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetDiscardExcessive +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gsysGetDiscardExcessive +* +* DESCRIPTION: +* This routine get the Discard Excessive state. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE Discard is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetDiscardExcessive +( + IN GT_QD_DEV* dev, + IN GT_BOOL *en +); + + + +/******************************************************************************* +* gsysSetSchedulingMode +* +* DESCRIPTION: +* This routine set the Scheduling Mode. +* +* INPUTS: +* mode - GT_TRUE wrr, GT_FALSE strict. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetSchedulingMode +( + IN GT_QD_DEV* dev, + IN GT_BOOL mode +); + + + +/******************************************************************************* +* gsysGetSchedulingMode +* +* DESCRIPTION: +* This routine get the Scheduling Mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE wrr, GT_FALSE strict. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetSchedulingMode +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gsysSetMaxFrameSize +* +* DESCRIPTION: +* This routine Set the max frame size allowed. +* +* INPUTS: +* mode - GT_TRUE max size 1522, GT_FALSE max size 1535. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetMaxFrameSize +( + IN GT_QD_DEV* dev, + IN GT_BOOL mode +); + + + +/******************************************************************************* +* gsysGetMaxFrameSize +* +* DESCRIPTION: +* This routine Get the max frame size allowed. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE max size 1522, GT_FALSE max size 1535. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetMaxFrameSize +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +); + + + +/******************************************************************************* +* gsysReLoad +* +* DESCRIPTION: +* This routine cause to the switch to reload the EEPROM. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysReLoad +( + IN GT_QD_DEV* dev +); + + +/******************************************************************************* +* gsysSetWatchDog +* +* DESCRIPTION: +* This routine Set the the watch dog mode. +* +* INPUTS: +* en - GT_TRUE enables, GT_FALSE disable. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetWatchDog +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gsysGetWatchDog +* +* DESCRIPTION: +* This routine Get the the watch dog mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE enables, GT_FALSE disable. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetWatchDog +( + IN GT_QD_DEV* dev, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gsysSetDuplexPauseMac +* +* DESCRIPTION: +* This routine sets the full duplex pause src Mac Address. +* +* INPUTS: +* mac - The Mac address to be set. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetDuplexPauseMac +( + IN GT_QD_DEV* dev, + IN GT_ETHERADDR *mac +); + + +/******************************************************************************* +* gsysGetDuplexPauseMac +* +* DESCRIPTION: +* This routine Gets the full duplex pause src Mac Address. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mac - the Mac address. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetDuplexPauseMac +( + IN GT_QD_DEV* dev, + OUT GT_ETHERADDR *mac +); + + + +/******************************************************************************* +* gsysSetPerPortDuplexPauseMac +* +* DESCRIPTION: +* This routine sets whether the full duplex pause src Mac Address is per +* port or per device. +* +* INPUTS: +* en - GT_TURE per port mac, GT_FALSE global mac. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetPerPortDuplexPauseMac +( + IN GT_QD_DEV* dev, + IN GT_BOOL en +); + + + +/******************************************************************************* +* gsysGetPerPortDuplexPauseMac +* +* DESCRIPTION: +* This routine Gets whether the full duplex pause src Mac Address is per +* port or per device. +* +* INPUTS: +* en - GT_TURE per port mac, GT_FALSE global mac. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetPerPortDuplexPauseMac +( + IN GT_QD_DEV* dev, + IN GT_BOOL *en +); + + +/******************************************************************************* +* gsysReadMiiRegister +* +* DESCRIPTION: +* This routine reads QuarterDeck Registers. Since this routine is only for +* Diagnostic Purpose, no error checking will be performed. +* User has to know exactly which phy address(0 ~ 0x1F) will be read. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysReadMiiReg +( + IN GT_QD_DEV* dev, + IN GT_U32 phyAddr, + IN GT_U32 regAddr, + OUT GT_U32 *data +); + +/******************************************************************************* +* gsysWriteMiiRegister +* +* DESCRIPTION: +* This routine writes QuarterDeck Registers. Since this routine is only for +* Diagnostic Purpose, no error checking will be performed. +* User has to know exactly which phy address(0 ~ 0x1F) will be read. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* data - data to be written. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysWriteMiiReg +( + IN GT_QD_DEV* dev, + IN GT_U32 phyAddr, + IN GT_U32 regAddr, + IN GT_U16 data +); + +/******************************************************************************* +* gsysGetSW_Mode +* +* DESCRIPTION: +* This routine get the Switch mode. These two bits returen +* the current value of the SW_MODE[1:0] pins. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE Discard is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* This feature is for both clippership and fullsail +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetSW_Mode +( + IN GT_QD_DEV* dev, + IN GT_SW_MODE *mode +); + +/******************************************************************************* +* gsysGetInitReady +* +* DESCRIPTION: +* This routine get the InitReady bit. This bit is set to a one when the ATU, +* the Queue Controller and the Statistics Controller are done with their +* initialization and are ready to accept frames. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE: switch is ready, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* This feature is for both clippership and fullsail +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetInitReady +( + IN GT_QD_DEV* dev, + IN GT_BOOL *mode +); + + +/******************************************************************************* +* gstatsFlushAll +* +* DESCRIPTION: +* Flush All RMON counters for all ports. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsFlushAll +( + IN GT_QD_DEV* dev +); + +/******************************************************************************* +* gstatsFlushPort +* +* DESCRIPTION: +* Flush All RMON counters for a given port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsFlushPort +( + IN GT_QD_DEV* dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gstatsGetPortCounter +* +* DESCRIPTION: +* This routine gets a specific counter of the given port +* +* INPUTS: +* port - the logical port number. +* counter - the counter which will be read +* +* OUTPUTS: +* statsData - points to 32bit data storage for the MIB counter +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortCounter +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_STATS_COUNTERS counter, + OUT GT_U32 *statsData +); + +/******************************************************************************* +* gstatsGetPortAllCounters +* +* DESCRIPTION: +* This routine gets all RMON counters of the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* statsCounterSet - points to GT_STATS_COUNTER_SET for the MIB counters +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortAllCounters +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_STATS_COUNTER_SET *statsCounterSet +); + + +/******************************************************************************* +* grcSetLimitMode +* +* DESCRIPTION: +* This routine sets the port's rate control ingress limit mode. +* +* INPUTS: +* port - logical port number. +* mode - rate control ingress limit mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +*******************************************************************************/ +GT_STATUS grcSetLimitMode +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_RATE_LIMIT_MODE mode +); + +/******************************************************************************* +* grcGetLimitMode +* +* DESCRIPTION: +* This routine gets the port's rate control ingress limit mode. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* mode - rate control ingress limit mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetLimitMode +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_RATE_LIMIT_MODE *mode +); + +/******************************************************************************* +* grcSetPri3Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 3 frames. +* Priority 3 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 3 frame rate limit mode +* GT_FALSE: use the same rate as Pri2Rate +* GT_TRUE: use twice the rate as Pri2Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +*******************************************************************************/ +GT_STATUS grcSetPri3Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetPri3Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 3 frames. +* Priority 3 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 3 frame rate limit mode +* GT_FALSE: use the same rate as Pri2Rate +* GT_TRUE: use twice the rate as Pri2Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetPri3Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetPri2Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 2 frames. +* Priority 2 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 2 frame rate limit mode +* GT_FALSE: use the same rate as Pri1Rate +* GT_TRUE: use twice the rate as Pri1Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +*******************************************************************************/ +GT_STATUS grcSetPri2Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetPri2Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 2 frames. +* Priority 2 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 2 frame rate limit mode +* GT_FALSE: use the same rate as Pri1Rate +* GT_TRUE: use twice the rate as Pri1Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetPri2Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetPri1Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 1 frames. +* Priority 1 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 1 frame rate limit mode +* GT_FALSE: use the same rate as Pri0Rate +* GT_TRUE: use twice the rate as Pri0Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +*******************************************************************************/ +GT_STATUS grcSetPri1Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetPri1Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 1 frames. +* Priority 1 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 1 frame rate limit mode +* GT_FALSE: use the same rate as Pri0Rate +* GT_TRUE: use twice the rate as Pri0Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetPri1Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetPri0Rate +* +* DESCRIPTION: +* This routine sets the port's ingress data limit for priority 0 frames. +* +* INPUTS: +* port - logical port number. +* rate - ingress data rate limit for priority 0 frames. These frames +* will be discarded after the ingress rate selected is reached +* or exceeded. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcSetPri0Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_PRI0_RATE rate +); + +/******************************************************************************* +* grcGetPri0Rate +* +* DESCRIPTION: +* This routine gets the port's ingress data limit for priority 0 frames. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* rate - ingress data rate limit for priority 0 frames. These frames +* will be discarded after the ingress rate selected is reached +* or exceeded. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetPri0Rate +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_PRI0_RATE *rate +); + +/******************************************************************************* +* grcSetBytesCount +* +* DESCRIPTION: +* This routine sets the byets to count for limiting needs to be determined +* +* INPUTS: +* port - logical port number to set. +* limitMGMT - GT_TRUE: To limit and count MGMT frame bytes +* GT_FALSE: otherwise +* countIFG - GT_TRUE: To count IFG bytes +* GT_FALSE: otherwise +* countPre - GT_TRUE: To count Preamble bytes +* GT_FALSE: otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcSetBytesCount +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL limitMGMT, + IN GT_BOOL countIFG, + IN GT_BOOL countPre +); + +/******************************************************************************* +* grcGetBytesCount +* +* DESCRIPTION: +* This routine gets the byets to count for limiting needs to be determined +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* limitMGMT - GT_TRUE: To limit and count MGMT frame bytes +* GT_FALSE: otherwise +* countIFG - GT_TRUE: To count IFG bytes +* GT_FALSE: otherwise +* countPre - GT_TRUE: To count Preamble bytes +* GT_FALSE: otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS grcGetBytesCount +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL *limitMGMT, + IN GT_BOOL *countIFG, + IN GT_BOOL *countPre +); + +/******************************************************************************* +* grcSetEgressRate +* +* DESCRIPTION: +* This routine sets the port's egress data limit. +* +* +* INPUTS: +* port - logical port number. +* rateType - egress data rate limit (GT_ERATE_TYPE union type). +* union type is used to support multiple devices with the +* different formats of egress rate. +* GT_ERATE_TYPE has the following fields: +* definedRate - GT_EGRESS_RATE enum type should used for the +* following devices: +* 88E6218, 88E6318, 88E6063, 88E6083, 88E6181, 88E6183, +* 88E6093, 88E6095, 88E6185, 88E6108, 88E6065, 88E6061, +* and their variations +* kbRate - rate in kbps that should used for the following +* devices: +* 88E6097, 88E6096 with the GT_PIRL_ELIMIT_MODE of +* GT_PIRL_ELIMIT_LAYER1, +* GT_PIRL_ELIMIT_LAYER2, or +* GT_PIRL_ELIMIT_LAYER3 (see grcSetELimitMode) +* 64kbps ~ 1Mbps : increments of 64kbps, +* 1Mbps ~ 100Mbps : increments of 1Mbps, and +* 100Mbps ~ 1000Mbps: increments of 10Mbps +* Therefore, the valid values are: +* 64, 128, 192, 256, 320, 384,..., 960, +* 1000, 2000, 3000, 4000, ..., 100000, +* 110000, 120000, 130000, ..., 1000000. +* fRate - frame per second that should used for the following +* devices: +* 88E6097, 88E6096 with GT_PIRL_ELIMIT_MODE of +* GT_PIRL_ELIMIT_FRAME +* Valid values are between 7600 and 1488000 +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* GT_16M, GT_32M, GT_64M, GT_128M, and GT_256M in GT_EGRESS_RATE enum +* are supported only by Gigabit Ethernet Switch. +* +*******************************************************************************/ +GT_STATUS grcSetEgressRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ERATE_TYPE *rateType +); + +/******************************************************************************* +* grcGetEgressRate +* +* DESCRIPTION: +* This routine gets the port's egress data limit. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* rateType - egress data rate limit (GT_ERATE_TYPE union type). +* union type is used to support multiple devices with the +* different formats of egress rate. +* GT_ERATE_TYPE has the following fields: +* definedRate - GT_EGRESS_RATE enum type should used for the +* following devices: +* 88E6218, 88E6318, 88E6063, 88E6083, 88E6181, 88E6183, +* 88E6093, 88E6095, 88E6185, 88E6108, 88E6065, 88E6061, +* and their variations +* kbRate - rate in kbps that should used for the following +* devices: +* 88E6097, 88E6096 with the GT_PIRL_ELIMIT_MODE of +* GT_PIRL_ELIMIT_LAYER1, +* GT_PIRL_ELIMIT_LAYER2, or +* GT_PIRL_ELIMIT_LAYER3 (see grcSetELimitMode) +* 64kbps ~ 1Mbps : increments of 64kbps, +* 1Mbps ~ 100Mbps : increments of 1Mbps, and +* 100Mbps ~ 1000Mbps: increments of 10Mbps +* Therefore, the valid values are: +* 64, 128, 192, 256, 320, 384,..., 960, +* 1000, 2000, 3000, 4000, ..., 100000, +* 110000, 120000, 130000, ..., 1000000. +* fRate - frame per second that should used for the following +* devices: +* 88E6097, 88E6096 with GT_PIRL_ELIMIT_MODE of +* GT_PIRL_ELIMIT_FRAME +* Valid values are between 7600 and 1488000 +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* GT_16M, GT_32M, GT_64M, GT_128M, and GT_256M in GT_EGRESS_RATE enum +* are supported only by Gigabit Ethernet Switch. +* +*******************************************************************************/ +GT_STATUS grcGetEgressRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ERATE_TYPE *rateType +); + + +/******************************************************************************* +* gpavSetPAV +* +* DESCRIPTION: +* This routine sets the Port Association Vector +* +* INPUTS: +* port - logical port number. +* pav - Port Association Vector +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS gpavSetPAV +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_U16 pav +); + +/******************************************************************************* +* gpavGetPAV +* +* DESCRIPTION: +* This routine gets the Port Association Vector +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* pav - Port Association Vector +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS gpavGetPAV +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_U16 *pav +); + +/******************************************************************************* +* gpavSetIngressMonitor +* +* DESCRIPTION: +* This routine sets the Ingress Monitor bit in the PAV. +* +* INPUTS: +* port - the logical port number. +* mode - the ingress monitor bit in the PAV +* GT_FALSE: Ingress Monitor enabled +* GT_TRUE: Ingress Monitor disabled +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +*******************************************************************************/ +GT_STATUS gpavSetIngressMonitor +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gpavGetIngressMonitor +* +* DESCRIPTION: +* This routine gets the Ingress Monitor bit in the PAV. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the ingress monitor bit in the PAV +* GT_FALSE: Ingress Monitor enabled +* GT_TRUE: Ingress Monitor disabled +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +*******************************************************************************/ +GT_STATUS gpavGetIngressMonitor +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gvctGetCableStatus +* +* DESCRIPTION: +* This routine perform the virtual cable test for the requested port, +* and returns the the status per MDI pair. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* cableStatus - the port copper cable status. +* cableLen - the port copper cable length. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* Internal Gigabit Phys in 88E6165 family and 88E6351 family devices +* are not supported by this API. For those devices, gvctGetAdvCableDiag +* API can be used, instead. +* +*******************************************************************************/ +GT_STATUS gvctGetCableDiag +( + IN GT_QD_DEV* dev, + IN GT_LPORT port, + OUT GT_CABLE_STATUS *cableStatus +); + + +/******************************************************************************* +* gvctGet1000BTExtendedStatus +* +* DESCRIPTION: +* This routine retrieves extended cable status, such as Pair Poloarity, +* Pair Swap, and Pair Skew. Note that this routine will be success only +* if 1000Base-T Link is up. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* extendedStatus - the extended cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* Internal Gigabit Phys in 88E6165 family and 88E6351 family devices +* are not supported by this API. For those devices, gvctGetAdvExtendedStatus +* API can be used, instead. +* +*******************************************************************************/ +GT_STATUS gvctGet1000BTExtendedStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_1000BT_EXTENDED_STATUS *extendedStatus +); + + +/******************************************************************************* +* gtMemSet +* +* DESCRIPTION: +* Set a block of memory +* +* INPUTS: +* start - start address of memory block for setting +* simbol - character to store, converted to an unsigned char +* size - size of block to be set +* +* OUTPUTS: +* None +* +* RETURNS: +* Pointer to set memory block +* +* COMMENTS: +* None +* +*******************************************************************************/ +void * gtMemSet +( + IN void * start, + IN int symbol, + IN GT_U32 size +); + +/******************************************************************************* +* gtMemCpy +* +* DESCRIPTION: +* Copies 'size' characters from the object pointed to by 'source' into +* the object pointed to by 'destination'. If copying takes place between +* objects that overlap, the behavior is undefined. +* +* INPUTS: +* destination - destination of copy +* source - source of copy +* size - size of memory to copy +* +* OUTPUTS: +* None +* +* RETURNS: +* Pointer to destination +* +* COMMENTS: +* None +* +*******************************************************************************/ +void * gtMemCpy +( + IN void * destination, + IN const void * source, + IN GT_U32 size +); + + +/******************************************************************************* +* gtMemCmp +* +* DESCRIPTION: +* Compares given memories. +* +* INPUTS: +* src1 - source 1 +* src2 - source 2 +* size - size of memory to copy +* +* OUTPUTS: +* None +* +* RETURNS: +* 0, if equal. +* negative number, if src1 < src2. +* positive number, if src1 > src2. +* +* COMMENTS: +* None +* +*******************************************************************************/ +int gtMemCmp +( + IN char src1[], + IN char src2[], + IN GT_U32 size +); + +/******************************************************************************* +* gtStrlen +* +* DESCRIPTION: +* Determine the length of a string +* INPUTS: +* source - string +* +* OUTPUTS: +* None +* +* RETURNS: +* size - number of characters in string, not including EOS. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_U32 gtStrlen +( + IN const void * source +); + +/******************************************************************************* +* gtDelay +* +* DESCRIPTION: +* Wait for the given uSec and return. +* Current Switch devices with Gigabit Ethernet Support require 250 uSec +* of delay time for PPU to be disabled. +* Since this function is System and/or OS dependent, it should be provided +* by each DSDT user. +* +* INPUTS: +* delayTime - delay in uSec. +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +void gtDelay +( + IN const unsigned int delayTime +); + + +/******************************************************************************* +* gtVersion +* +* DESCRIPTION: +* This function returns the version of the QuarterDeck SW suite. +* +* INPUTS: +* None. +* +* OUTPUTS: +* version - QuarterDeck software version. +* +* RETURNS: +* GT_OK on success, +* GT_BAD_PARAM on bad parameters, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gtVersion +( + OUT GT_VERSION *version +); + + +/* Prototypes added for Gigabit Ethernet Switch Support */ + + +/* gtBrgFdb.c */ + +/******************************************************************************* +* gfdbMove +* +* DESCRIPTION: +* This routine moves all or unblocked addresses from a port to another. +* +* INPUTS: +* moveCmd - the move operation type. +* moveFrom - port where moving from +* moveTo - port where moving to +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbMove +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_U32 moveFrom, + IN GT_U32 moveTo +); + +/******************************************************************************* +* gfdbMoveInDB +* +* DESCRIPTION: +* This routine move all or unblocked addresses which are in the particular +* ATU Database (DBNum) from a port to another. +* +* INPUTS: +* moveCmd - the move operation type. +* DBNum - ATU MAC Address Database Number. +* moveFrom - port where moving from +* moveTo - port where moving to +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbMoveInDB +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_U32 DBNum, + IN GT_U32 moveFrom, + IN GT_U32 moveTo +); + +/* gtBrgStp.c */ + +/* gtBrgVlan.c */ + +/* gtBrgVtu.c */ + +/* gtEvents.c */ + +/******************************************************************************* +* gatuGetIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of ATU interrupt occured +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* GT_MEMEBER_VIOLATION, GT_MISS_VIOLATION, or GT_FULL_VIOLATION +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gatuGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_ATU_INT_STATUS *atuIntStatus +); + + +/* gtPhyCtrl.c */ + +/******************************************************************************* +* gprtSet1000TMasterMode +* +* DESCRIPTION: +* This routine set the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* mode - GT_1000T_MASTER_SLAVE structure +* autoConfig - GT_TRUE for auto, GT_FALSE for manual setup. +* masterPrefer - GT_TRUE if Master configuration is preferred. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSet1000TMasterMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_1000T_MASTER_SLAVE *mode +); + +/******************************************************************************* +* gprtGet1000TMasterMode +* +* DESCRIPTION: +* This routine set the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_1000T_MASTER_SLAVE structure +* autoConfig - GT_TRUE for auto, GT_FALSE for manual setup. +* masterPrefer - GT_TRUE if Master configuration is preferred. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGet1000TMasterMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_1000T_MASTER_SLAVE *mode +); + +/******************************************************************************* +* gprtGetPhyReg +* +* DESCRIPTION: +* This routine reads Phy Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + OUT GT_U16 *data +); + +/******************************************************************************* +* gprtSetPhyReg +* +* DESCRIPTION: +* This routine writes Phy Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + IN GT_U16 data +); + + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtSetDropOnLock +* +* DESCRIPTION: +* This routine set the Drop on Lock. When set to one, Ingress frames will +* be discarded if their SA field is not in the ATU's address database. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Unknown SA drop or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDropOnLock +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetDropOnLock +* +* DESCRIPTION: +* This routine gets DropOnLock mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: DropOnLock enabled, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDropOnLock +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetDoubleTag +* +* DESCRIPTION: +* This routine set the Ingress Double Tag Mode. When set to one, +* ingressing frames are examined to see if they contain an 802.3ac tag. +* If they do, the tag is removed and then the frame is processed from +* there (i.e., removed tag is ignored). Essentially, untagged frames +* remain untagged, single tagged frames become untagged and double tagged +* frames become single tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for DoulbeTag mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDoubleTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetDoubleTag +* +* DESCRIPTION: +* This routine gets DoubleTag mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: DoubleTag enabled, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDoubleTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetInterswitchPort +* +* DESCRIPTION: +* This routine set Interswitch Port. When set to one, +* it indicates this port is a interswitch port used to communicated with +* CPU or to cascade with another switch device. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Interswitch port or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetInterswitchPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetInterswithPort +* +* DESCRIPTION: +* This routine gets InterswitchPort. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: This port is interswitch port, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetInterswitchPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetLearnDisable +* +* DESCRIPTION: +* This routine enables/disables automatic learning of new source MAC +* addresses on the given port ingress +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for disable or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetLearnDisable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + +/******************************************************************************* +* gprtGetLearnDisable +* +* DESCRIPTION: +* This routine gets LearnDisable setup +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: Learning disabled on the given port ingress frames, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetLearnDisable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetIgnoreFCS +* +* DESCRIPTION: +* This routine sets FCS Ignore mode. When this bit is set to a one, +* the last four bytes of frames received on this port are overwritten with +* a good CRC and the frames will be accepted by the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for ignore FCS or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIgnoreFCS +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetIgnoreFCS +* +* DESCRIPTION: +* This routine gets Ignore FCS setup +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: Ignore FCS on the given port's ingress frames, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIgnoreFCS +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetVTUPriOverride +* +* DESCRIPTION: +* VTU Priority Override. The following modes are supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetVTUPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PRI_OVERRIDE mode +); + +/******************************************************************************* +* gprtGetVTUPriOverride +* +* DESCRIPTION: +* VTU Priority Override. The following modes are supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetVTUPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +); + +/******************************************************************************* +* gprtSetSAPriOverride +* +* DESCRIPTION: +* SA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetSAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetSAPriOverride +* +* DESCRIPTION: +* SA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetSAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +); + +/******************************************************************************* +* gprtSetDAPriOverride +* +* DESCRIPTION: +* DA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetDAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PRI_OVERRIDE mode +); + +/******************************************************************************* +* gprtGetDAPriOverride +* +* DESCRIPTION: +* DA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetDAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +); + +/******************************************************************************* +* gprtSetCPUPort +* +* DESCRIPTION: +* This routine sets CPU Port number. When Snooping is enabled on this port +* or when this port is configured as an Interswitch Port and it receives a +* To_CPU frame, the switch needs to know what port on this device the frame +* should egress. +* +* INPUTS: +* port - the logical port number. +* cpuPort - CPU Port number or interswitch port where CPU Port is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetCPUPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LPORT cpuPort +); + +/******************************************************************************* +* gprtGetCPUPort +* +* DESCRIPTION: +* This routine gets CPU Logical Port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* cpuPort - CPU Port's logical number +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetCPUPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_LPORT *cpuLPort +); + +/******************************************************************************* +* gprtSetLockedPort +* +* DESCRIPTION: +* This routine sets LockedPort. When it's set to one, CPU directed +* learning for 802.1x MAC authentication is enabled on this port. In this +* mode, an ATU Miss Violation interrupt will occur when a new SA address +* is received in a frame on this port. Automatically SA learning and +* refreshing is disabled in this mode. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Locked Port, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetLockedPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetLockedPort +* +* DESCRIPTION: +* This routine gets Locked Port mode for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if LockedPort, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetLockedPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetIgnoreWrongData +* +* DESCRIPTION: +* This routine sets Ignore Wrong Data. If the frame's SA address is found +* in the database and if the entry is 'static' or if the port is 'locked' +* the source port's bit is checked to insure the SA has been assigned to +* this port. If the SA is NOT assigned to this port, it is considered an +* ATU Member Violation. If the IgnoreWrongData is set to GT_FALSE, an ATU +* Member Violation interrupt will be generated. If it's set to GT_TRUE, +* the ATU Member Violation error will be masked and ignored. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for IgnoreWrongData, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIgnoreWrongData +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + +/******************************************************************************* +* gprtGetIgnoreWrongData +* +* DESCRIPTION: +* This routine gets Ignore Wrong Data mode for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if IgnoreWrongData, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIgnoreWrongData +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/* gtPortRateCtrl.c */ + +/* gtPortRmon.c */ + +/******************************************************************************* +* gstatsGetPortCounter2 +* +* DESCRIPTION: +* This routine gets a specific counter of the given port +* +* INPUTS: +* port - the logical port number. +* counter - the counter which will be read +* +* OUTPUTS: +* statsData - points to 32bit data storage for the MIB counter +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* This function supports Gigabit Switch only +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortCounter2 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_STATS_COUNTERS2 counter, + OUT GT_U32 *statsData +); + + +/******************************************************************************* +* gstatsGetPortAllCounters2 +* +* DESCRIPTION: +* This routine gets all counters of the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* statsCounterSet - points to GT_STATS_COUNTER_SET for the MIB counters +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* This function supports Gigabit Switch only +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortAllCounters2 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_STATS_COUNTER_SET2 *statsCounterSet +); + +/******************************************************************************* +* gstatsGetHistogramMode +* +* DESCRIPTION: +* This routine gets the Histogram Counters Mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - Histogram Mode (GT_COUNT_RX_ONLY, GT_COUNT_TX_ONLY, +* and GT_COUNT_RX_TX) +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* This function supports Gigabit Switch only +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetHistogramMode +( + IN GT_QD_DEV *dev, + OUT GT_HISTOGRAM_MODE *mode +); + +/******************************************************************************* +* gstatsSetHistogramMode +* +* DESCRIPTION: +* This routine sets the Histogram Counters Mode. +* +* INPUTS: +* mode - Histogram Mode (GT_COUNT_RX_ONLY, GT_COUNT_TX_ONLY, +* and GT_COUNT_RX_TX) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsSetHistogramMode +( + IN GT_QD_DEV *dev, + IN GT_HISTOGRAM_MODE mode +); + + +/* gtPortStatus.c */ + +/******************************************************************************* +* gprtGetPauseEn +* +* DESCRIPTION: +* This routine retrives the link pause state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for enable or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* If set MAC Pause (for Full Duplex flow control) is implemented in the +* link partner and in MyPause +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPauseEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetHdFlow +* +* DESCRIPTION: +* This routine retrives the half duplex flow control value. +* If set, Half Duplex back pressure will be used on this port if this port +* is in a half duplex mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for enable or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetHdFlow +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetPHYDetect +* +* DESCRIPTION: +* This routine retrives the information regarding PHY detection. +* If set, An 802.3 PHY is attached to this port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if connected or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPHYDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtSetPHYDetect +* +* DESCRIPTION: +* This routine sets PHYDetect bit which make PPU change its polling. +* PPU's pool routine uses these bits to determine which port's to poll +* PHYs on for Link, Duplex, Speed, and Flow Control. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE or GT_FALSE +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* This function should not be called if gsysGetPPUState returns +* PPU_STATE_ACTIVE. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPHYDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gprtGetSpeedMode +* +* DESCRIPTION: +* This routine retrives the port speed. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PORT_SPEED_MODE type. +* (PORT_SPEED_1000_MBPS,PORT_SPEED_100_MBPS, or PORT_SPEED_10_MBPS) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSpeedMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_SPEED_MODE *speed +); + +/******************************************************************************* +* gprtGetHighErrorRate +* +* DESCRIPTION: +* This routine retrives the PCS High Error Rate. +* This routine returns GT_TRUE if the rate of invalid code groups seen by +* PCS has exceeded 10 to the power of -11. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE or GT_FALSE +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetHighErrorRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetTxPaused +* +* DESCRIPTION: +* This routine retrives Transmit Pause state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Rx MAC receives a PAUSE frame with none-zero Puase Time +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetTxPaused +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + +/******************************************************************************* +* gprtGetFlowCtrl +* +* DESCRIPTION: +* This routine retrives Flow control state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Rx MAC determines that no more data should be +* entering this port. +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetFlowCtrl +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetC_Duplex +* +* DESCRIPTION: +* This routine retrives Port 9's duplex configuration mode determined +* at reset. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if configured as Full duplex operation +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Return value is valid only if the given port is 9. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetC_Duplex +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetC_Mode +* +* DESCRIPTION: +* This routine retrives port's interface type configuration mode +* determined at reset. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - one of value in GT_PORT_CONFIG_MODE enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Return value is valid only if the given port is 9. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetC_Mode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_CONFIG_MODE *state +); + + +/* gtSysCtrl.c */ + +/******************************************************************************* +* gsysSetPPUEn +* +* DESCRIPTION: +* This routine enables/disables Phy Polling Unit. +* +* INPUTS: +* en - GT_TRUE to enable PPU, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetPPUEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetPPUEn +* +* DESCRIPTION: +* This routine get the PPU state. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if PPU is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetPPUEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetCascadePort +* +* DESCRIPTION: +* This routine sets Cascade Port number. +* In multichip systems frames coming from a CPU need to know when they +* have reached their destination chip. +* +* INPUTS: +* port - Cascade Port +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetCascadePort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetCascadePort +* +* DESCRIPTION: +* This routine gets Cascade Port number. +* In multichip systems frames coming from a CPU need to know when they +* have reached their destination chip. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - Cascade Port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetCascadePort +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetDeviceNumber +* +* DESCRIPTION: +* This routine sets Device Number. +* In multichip systems frames coming from a CPU need to know when they +* have reached their destination chip. From CPU frames whose Dev_Num +* fieldmatches these bits have reachedtheir destination chip and are sent +* out this chip using the port number indicated in the frame's Trg_Port +* field. +* +* INPUTS: +* devNum - Device Number (0 ~ 31) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetDeviceNumber +( + IN GT_QD_DEV *dev, + IN GT_U32 devNum +); + +/******************************************************************************* +* gsysGetDeviceNumber +* +* DESCRIPTION: +* This routine gets Device Number. +* +* INPUTS: +* None. +* +* OUTPUTS: +* devNum - Device Number (0 ~ 31) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetDeviceNumber +( + IN GT_QD_DEV *dev, + OUT GT_U32 *devNum +); + + +/* gtPCSCtrl.c */ + + +/******************************************************************************* +* gpcsGetCommaDet +* +* DESCRIPTION: +* This routine retrieves Comma Detection status in PCS +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Comma Detected or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetCommaDet +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsGetSyncOK +* +* DESCRIPTION: +* This routine retrieves SynOK bit. It is set to a one when the PCS has +* detected a few comma patterns and is synchronized with its peer PCS +* layer. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if synchronized or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetSyncOK +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsGetSyncFail +* +* DESCRIPTION: +* This routine retrieves SynFail bit. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if synchronizaion failed or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetSyncFail +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsGetAnBypassed +* +* DESCRIPTION: +* This routine retrieves Inband Auto-Negotiation bypass status. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if AN is bypassed or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetAnBypassed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsGetAnBypassMode +* +* DESCRIPTION: +* This routine retrieves Enable mode of Inband Auto-Negotiation bypass. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if AN bypass is enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetAnBypassMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gpcsSetAnBypassMode +* +* DESCRIPTION: +* This routine retrieves Enable mode of Inband Auto-Negotiation bypass. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable AN bypass mode or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetAnBypassMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gpcsGetPCSAnEn +* +* DESCRIPTION: +* This routine retrieves Enable mode of PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if PCS AN is enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSAnEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gpcsSetPCSAnEn +* +* DESCRIPTION: +* This routine sets Enable mode of PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable PCS AN mode or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetPCSAnEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gpcsSetRestartPCSAn +* +* DESCRIPTION: +* This routine restarts PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetRestartPCSAn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gpcsGetPCSAnDone +* +* DESCRIPTION: +* This routine retrieves completion information of PCS Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if PCS AN is done or never done +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSAnDone +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gpcsSetLinkValue +* +* DESCRIPTION: +* This routine sets Link's force value +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force link up, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetLinkValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetLinkValue +* +* DESCRIPTION: +* This routine retrieves Link Value which will be used for Forcing Link +* up or down. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Link Force value is one (link up) +* GT_FALSE otherwise (link down) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetLinkValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetForcedLink +* +* DESCRIPTION: +* This routine forces Link. If LinkValue is set to one, calling this +* routine with GT_TRUE will force Link to be up. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force link (up or down), GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetForcedLink +* +* DESCRIPTION: +* This routine retrieves Forced Link bit +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedLink bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetDpxValue +* +* DESCRIPTION: +* This routine sets Duplex's Forced value. This function needs to be +* called prior to gpcsSetForcedDpx. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force full duplex, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetDpxValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetDpxValue +* +* DESCRIPTION: +* This routine retrieves Duplex's Forced value +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Duplex's Forced value is set to Full duplex, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetDpxValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetForcedDpx +* +* DESCRIPTION: +* This routine forces duplex mode. If DpxValue is set to one, calling this +* routine with GT_TRUE will force duplex mode to be full duplex. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force duplex mode, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedDpx +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetForcedDpx +* +* DESCRIPTION: +* This routine retrieves Forced Duplex. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedDpx bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedDpx +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetForceSpeed +* +* DESCRIPTION: +* This routine forces speed. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PORT_FORCED_SPEED_MODE (10, 100, 1000, or No Speed Force) +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForceSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_FORCED_SPEED_MODE mode +); + +/******************************************************************************* +* gpcsGetForceSpeed +* +* DESCRIPTION: +* This routine retrieves Force Speed value +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_PORT_FORCED_SPEED_MODE (10, 100, 1000, or no force speed) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForceSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_FORCED_SPEED_MODE *mode +); + + + +/* gtQosMap.c */ + +/******************************************************************************* +* gqosGetTagRemap +* +* DESCRIPTION: +* Gets the remapped priority value for a specific 802.1p priority on a +* given port. +* +* INPUTS: +* port - the logical port number. +* pri - 802.1p priority +* +* OUTPUTS: +* remappedPri - remapped Priority +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetTagRemap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 pri, + OUT GT_U8 *remappedPri +); + +/******************************************************************************* +* gqosSetTagRemap +* +* DESCRIPTION: +* Sets the remapped priority value for a specific 802.1p priority on a +* given port. +* +* INPUTS: +* port - the logical port number. +* pri - 802.1p priority +* remappedPri - remapped Priority +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetTagRemap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 pri, + IN GT_U8 remappedPri +); + + +/* gtSysConfig.c */ + +/* gtSysStatus.c */ + +/******************************************************************************* +* gsysGetPPUState +* +* DESCRIPTION: +* This routine get the PPU State. These two bits return +* the current value of the PPU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_PPU_STATE +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetPPUState +( + IN GT_QD_DEV *dev, + OUT GT_PPU_STATE *mode +); + + +/* Prototypes added for 88E6093 */ + + +/* gtBrgFdb.c */ + +/******************************************************************************* +* gfdbGetLearn2All +* +* DESCRIPTION: +* When more than one Marvell device is used to form a single 'switch', it +* may be desirable for all devices in the 'switch' to learn any address this +* device learns. When this bit is set to a one all other devices in the +* 'switch' learn the same addresses this device learns. When this bit is +* cleared to a zero, only the devices that actually receive frames will learn +* from those frames. This mode typically supports more active MAC addresses +* at one time as each device in the switch does not need to learn addresses +* it may nerver use. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE if Learn2All is enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetLearn2All +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gfdbSetLearn2All +* +* DESCRIPTION: +* Enable or disable Learn2All mode. +* +* INPUTS: +* mode - GT_TRUE to set Learn2All, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetLearn2All +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +); + +/******************************************************************************* +* gfdbRemovePort +* +* DESCRIPTION: +* This routine deassociages all or unblocked addresses from a port. +* +* INPUTS: +* moveCmd - the move operation type. +* port - the logical port number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbRemovePort +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_LPORT port +); + +/******************************************************************************* +* gfdbRemovePortInDB +* +* DESCRIPTION: +* This routine deassociages all or unblocked addresses from a port in the +* particular ATU Database (DBNum). +* +* INPUTS: +* moveCmd - the move operation type. +* port - the logical port number. +* DBNum - ATU MAC Address Database Number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbRemovePortInDB +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_LPORT port, + IN GT_U32 DBNum +); + + + +/* gtBrgStp.c */ + +/* gtBrgVlan.c */ + +/* gtBrgVtu.c */ + +/* gtEvents.c */ + +/* gtPCSCtrl.c */ + +/******************************************************************************* +* gpcsGetPCSLink +* +* DESCRIPTION: +* This routine retrieves Link up status in PCS +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Comma Detected or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetFCValue +* +* DESCRIPTION: +* This routine sets Flow Control's force value +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force flow control enabled, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetFCValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetFCValue +* +* DESCRIPTION: +* This routine retrieves Flow Control Value which will be used for Forcing +* Flow Control enabled or disabled. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if FC Force value is one (flow control enabled) +* GT_FALSE otherwise (flow control disabled) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetFCValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gpcsSetForcedFC +* +* DESCRIPTION: +* This routine forces Flow Control. If FCValue is set to one, calling this +* routine with GT_TRUE will force Flow Control to be enabled. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force flow control (enable or disable), GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedFC +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + +/******************************************************************************* +* gpcsGetForcedFC +* +* DESCRIPTION: +* This routine retrieves Forced Flow Control bit +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedFC bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedFC +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + + + +/* gtPhyCtrl.c */ + +/******************************************************************************* +* gprtGetPagedPhyReg +* +* DESCRIPTION: +* This routine reads phy register of the given page +* +* INPUTS: +* port - port to be read +* regAddr - register offset to be read +* page - page number to be read +* +* OUTPUTS: +* data - value of the read register +* +* RETURNS: +* GT_OK - if read successed +* GT_FAIL - if read failed +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gprtGetPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U32 port, + IN GT_U32 regAddr, + IN GT_U32 page, + OUT GT_U16* data +); + +/******************************************************************************* +* gprtSetPagedPhyReg +* +* DESCRIPTION: +* This routine writes a value to phy register of the given page +* +* INPUTS: +* port - port to be read +* regAddr - register offset to be read +* page - page number to be read +* data - value of the read register +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - if read successed +* GT_FAIL - if read failed +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gprtSetPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U32 port, + IN GT_U32 regAddr, + IN GT_U32 page, + IN GT_U16 data +); + + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtSetUseCoreTag +* +* DESCRIPTION: +* This routine set the UseCoreTag bit in Port Control Register. +* When this bit is cleared to a zero, ingressing frames are considered +* Tagged if the 16-bits following the frame's Source Address is 0x8100. +* When this bit is set to a one, ingressing frames are considered Tagged +* if the 16-bits following the frame's Source Address is equal to the +* CoreTag register value. +* +* INPUTS: +* port - the logical port number. +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetUseCoreTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL force +); + +/******************************************************************************* +* gprtGetUseCoreTag +* +* DESCRIPTION: +* This routine get the Use Core Tag state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* force - GT_TRUE for using core tag register or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetUseCoreTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *force +); + +/******************************************************************************* +* gprtSetDiscardTagged +* +* DESCRIPTION: +* When this bit is set to a one, all non-MGMT frames that are processed as +* Tagged will be discarded as they enter this switch port. Priority only +* tagged frames (with a VID of 0x000) are considered tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to discard tagged frame, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardTagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetDiscardTagged +* +* DESCRIPTION: +* This routine gets DiscardTagged bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DiscardTagged bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardTagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetDiscardUntagged +* +* DESCRIPTION: +* When this bit is set to a one, all non-MGMT frames that are processed as +* Untagged will be discarded as they enter this switch port. Priority only +* tagged frames (with a VID of 0x000) are considered tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to discard untagged frame, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardUntagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetDiscardUntagged +* +* DESCRIPTION: +* This routine gets DiscardUntagged bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DiscardUntagged bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardUntagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetMapDA +* +* DESCRIPTION: +* When this bit is set to a one, normal switch operation will occur where a +* frame's DA address is used to direct the frame out the correct port. +* When this be is cleared to a zero, the frame will be sent out the port(s) +* defined by ForwardUnknown bits or the DefaultForward bits even if the DA +* is ound in the address database. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to use MapDA, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetMapDA +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetMapDA +* +* DESCRIPTION: +* This routine gets MapDA bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if MapDA bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetMapDA +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetDefaultForward +* +* DESCRIPTION: +* When this bit is set to a one, normal switch operation will occurs and +* multicast frames with unknown DA addresses are allowed to egress out this +* port (assuming the VLAN settings allow the frame to egress this port too). +* When this be is cleared to a zero, multicast frames with unknown DA +* addresses will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to use DefaultForward, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDefaultForward +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetDefaultForward +* +* DESCRIPTION: +* This routine gets DefaultForward bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DefaultForward bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDefaultForward +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetEgressMonitorSource +* +* DESCRIPTION: +* When this be is cleared to a zero, normal network switching occurs. +* When this bit is set to a one, any frame that egresses out this port will +* also be sent to the EgressMonitorDest Port +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to set EgressMonitorSource, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetEgressMonitorSource +* +* DESCRIPTION: +* This routine gets EgressMonitorSource bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if EgressMonitorSource bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetIngressMonitorSource +* +* DESCRIPTION: +* When this be is cleared to a zero, normal network switching occurs. +* When this bit is set to a one, any frame that egresses out this port will +* also be sent to the EgressMonitorDest Port +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to set EgressMonitorSource, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIngressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetIngressMonitorSource +* +* DESCRIPTION: +* This routine gets IngressMonitorSource bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if IngressMonitorSource bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIngressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/* gtPortPAV.c */ + +/* gtPortRateCtrl.c */ + +/* gtPortRmon.c */ + +/******************************************************************************* +* gstatsGetPortCounter3 +* +* DESCRIPTION: +* This routine gets a specific counter of the given port +* +* INPUTS: +* port - the logical port number. +* counter - the counter which will be read +* +* OUTPUTS: +* statsData - points to 32bit data storage for the MIB counter +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* This function supports Gigabit Switch only +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortCounter3 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_STATS_COUNTERS3 counter, + OUT GT_U32 *statsData +); + +/******************************************************************************* +* gstatsGetPortAllCounters3 +* +* DESCRIPTION: +* This routine gets all counters of the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* statsCounterSet - points to GT_STATS_COUNTER_SET for the MIB counters +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* This function supports Gigabit Switch only +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstatsGetPortAllCounters3 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_STATS_COUNTER_SET3 *statsCounterSet +); + + +/* gtPortStat.c */ + +/******************************************************************************* +* gprtGetPortCtr2 +* +* DESCRIPTION: +* This routine gets the port InDiscards, InFiltered, and OutFiltered counters. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* ctr - the counters value. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPortCtr2 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_STAT2 *ctr +); + +/* gtPortStatus.c */ + +/******************************************************************************* +* gprtGetMGMII +* +* DESCRIPTION: +* SERDES Interface mode. When this bit is cleared to a zero and a PHY is +* detected connected to this port, the SERDES interface between this port +* and the PHY will be SGMII. When this bit is set toa one and a PHY is +* detected connected to this port, the SERDES interface between this port +* and the PHY will be MGMII. When no PHY is detected on this port and the +* SERDES interface is being used, it will be configured in 1000Base-X mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE or GT_FALSE +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetMGMII +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtSetMGMII +* +* DESCRIPTION: +* SERDES Interface mode. When this bit is cleared to a zero and a PHY is +* detected connected to this port, the SERDES interface between this port +* and the PHY will be SGMII. When this bit is set toa one and a PHY is +* detected connected to this port, the SERDES interface between this port +* and the PHY will be MGMII. When no PHY is detected on this port and the +* SERDES interface is being used, it will be configured in 1000Base-X mode. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE or GT_FALSE +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetMGMII +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +); + + +/* gtQosMap.c */ + +/* gtSysCtrl.c */ + +/******************************************************************************* +* gsysSetCoreTagType +* +* DESCRIPTION: +* This routine sets Ether Core Tag Type. +* This Ether Type is added to frames that egress the switch as Double Tagged +* frames. It is also the Ether Type expected during Ingress to determine if +* a frame is Tagged or not on ports configured as UseCoreTag mode. +* +* INPUTS: +* etherType - Core Tag Type (2 bytes) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetCoreTagType +( + IN GT_QD_DEV *dev, + IN GT_U16 etherType +); + +/******************************************************************************* +* gsysGetCoreTagType +* +* DESCRIPTION: +* This routine gets CoreTagType +* +* INPUTS: +* None. +* +* OUTPUTS: +* etherType - Core Tag Type (2 bytes) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetCoreTagType +( + IN GT_QD_DEV *dev, + OUT GT_U16 *etherType +); + +/******************************************************************************* +* gsysSetIngressMonitorDest +* +* DESCRIPTION: +* This routine sets Ingress Monitor Destination Port. Frames that are +* targeted toward an Ingress Monitor Destination go out the port number +* indicated in these bits. This includes frames received on a Marvell Tag port +* with the Ingress Monitor type, and frames received on a Network port that +* is enabled to be the Ingress Monitor Source Port. +* If the Ingress Monitor Destination Port resides in this device these bits +* should point to the Network port where these frames are to egress. If the +* Ingress Monitor Destination Port resides in another device these bits +* should point to the Marvell Tag port in this device that is used to get +* to the device that contains the Ingress Monitor Destination Port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetIngressMonitorDest +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetIngressMonitorDest +* +* DESCRIPTION: +* This routine gets Ingress Monitor Destination Port. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetIngressMonitorDest +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetEgressMonitorDest +* +* DESCRIPTION: +* This routine sets Egress Monitor Destination Port. Frames that are +* targeted toward an Egress Monitor Destination go out the port number +* indicated in these bits. This includes frames received on a Marvell Tag port +* with the Egress Monitor type, and frames transmitted on a Network port that +* is enabled to be the Egress Monitor Source Port. +* If the Egress Monitor Destination Port resides in this device these bits +* should point to the Network port where these frames are to egress. If the +* Egress Monitor Destination Port resides in another device these bits +* should point to the Marvell Tag port in this device that is used to get +* to the device that contains the Egress Monitor Destination Port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetEgressMonitorDest +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetEgressMonitorDest +* +* DESCRIPTION: +* This routine gets Egress Monitor Destination Port. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetEgressMonitorDest +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + + +/* gtSysConfig.c */ + +/* gtSysStatus.c */ + + +/* functions added on rev 2.2 */ + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtSetMessagePort +* +* DESCRIPTION: +* When the Learn2All bit is set to one, learning message frames are +* generated. These frames will be sent out all ports whose Message Port is +* set to one. +* If this feature is used, it is recommended that all Marvell Tag ports, +* except for the CPU's port, have their MessagePort bit set to one. +* Ports that are not Marvell Tag ports should not have their Message Port +* bit set to one. +* +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to make this port a Message Port. GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetMessagePort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetMessagePort +* +* DESCRIPTION: +* When the Learn2All bit is set to one, learning message frames are +* generated. These frames will be sent out all ports whose Message Port is +* set to one. +* If this feature is used, it is recommended that all Marvell Tag ports, +* except for the CPU's port, have their MessagePort bit set to one. +* Ports that are not Marvell Tag ports should not have their Message Port +* bit set to one. +* +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to make this port a Message Port. GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetMessagePort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/******************************************************************************* +* gprtSetTrunkPort +* +* DESCRIPTION: +* This function enables/disables and sets the trunk ID. +* +* INPUTS: +* port - the logical port number. +* en - GT_TRUE to make the port be a member of a trunk with the given trunkId. +* GT_FALSE, otherwise. +* trunkId - valid ID is 0 ~ 15. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkId is neither valid nor INVALID_TRUNK_ID +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetTrunkPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en, + IN GT_U32 trunkId +); + + +/******************************************************************************* +* gprtGetTrunkPort +* +* DESCRIPTION: +* This function returns trunk state of the port. +* When trunk is disabled, trunkId field won't have valid value. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* en - GT_TRUE, if the port is a member of a trunk, +* GT_FALSE, otherwise. +* trunkId - 0 ~ 15, valid only if en is GT_TRUE +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetTrunkPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en, + OUT GT_U32 *trunkId +); + + + + +/******************************************************************************* +* gprtGetGlobal2Reg +* +* DESCRIPTION: +* This routine reads Switch Global 2 Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + OUT GT_U16 *data +); + +/******************************************************************************* +* gprtSetGlobal2Reg +* +* DESCRIPTION: +* This routine writes Switch Global2 Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + IN GT_U16 data +); + +/* gtSysCtrl.c */ +/******************************************************************************* +* gsysSetARPDest +* +* DESCRIPTION: +* This routine sets ARP Monitor Destination Port. Tagged or untagged +* frames that ingress Network ports with the Broadcast Destination Address +* and with an Ethertype of 0x0806 are mirrored to this port. The ARPDest +* should point to the port that directs these frames to the switch's CPU +* that will process ARPs. This target port should be a Marvell Tag port so +* that frames will egress with a To_CPU Marvell Tag with a CPU Code of ARP. +* To_CPU Marvell Tag frames with a CPU Code off ARP that ingress a Marvell +* Tag port will be sent to the port number definded in ARPDest. +* +* If ARPDest = 0xF, ARP Monitoring is disabled and ingressing To_CPU ARP +* frames will be discarded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetARPDest +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetARPDest +* +* DESCRIPTION: +* This routine gets ARP Monitor Destination Port. Tagged or untagged +* frames that ingress Network ports with the Broadcast Destination Address +* and with an Ethertype of 0x0806 are mirrored to this port. The ARPDest +* should point to the port that directs these frames to the switch's CPU +* that will process ARPs. This target port should be a Marvell Tag port so +* that frames will egress with a To_CPU Marvell Tag with a CPU Code of ARP. +* To_CPU Marvell Tag frames with a CPU Code off ARP that ingress a Marvell +* Tag port will be sent to the port number definded in ARPDest. +* +* If ARPDest = 0xF, ARP Monitoring is disabled and ingressing To_CPU ARP +* frames will be discarded. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetARPDest +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetRsvd2CpuEnables +* +* DESCRIPTION: +* Reserved DA Enables. When the function, gsysSetRsvd2Cpu, is called with +* en = GT_TRUE, the 16 reserved multicast DA addresses, whose bit in this +* enBits(or register) are also set to a one, are treated as MGMT frames. +* All the reserved DA's take the form 01:80:C2:00:00:0x. When x = 0x0, +* bit 0 of this register is tested. When x = 0x2, bit 2 of this field is +* tested and so on. +* If the tested bit in this register is cleared to a zero, the frame will +* be treated as a normal (non-MGMT) frame. +* +* INPUTS: +* enBits - bit vector of enabled Reserved Multicast. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetRsvd2CpuEnables +( + IN GT_QD_DEV *dev, + IN GT_U16 enBits +); + +/******************************************************************************* +* gsysGetRsvd2CpuEnables +* +* DESCRIPTION: +* Reserved DA Enables. When the function, gsysSetRsvd2Cpu, is called with +* en = GT_TRUE, the 16 reserved multicast DA addresses, whose bit in this +* enBits(or register) are also set to a one, are treated as MGMT frames. +* All the reserved DA's take the form 01:80:C2:00:00:0x. When x = 0x0, +* bit 0 of this register is tested. When x = 0x2, bit 2 of this field is +* tested and so on. +* If the tested bit in this register is cleared to a zero, the frame will +* be treated as a normal (non-MGMT) frame. +* +* INPUTS: +* None. +* +* OUTPUTS: +* enBits - bit vector of enabled Reserved Multicast. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetRsvd2CpuEnables +( + IN GT_QD_DEV *dev, + OUT GT_U16 *enBits +); + +/******************************************************************************* +* gsysSetRsvd2Cpu +* +* DESCRIPTION: +* When the Rsvd2Cpu is set to a one(GT_TRUE), frames with a Destination +* Address in the range 01:80:C2:00:00:0x, regardless of their VLAN +* membership, will be considered MGMT frames and sent to the port's CPU +* Port as long as the associated Rsvd2CpuEnable bit (gsysSetRsvd2CpuEnable +* function) for the frames's DA is also set to a one. +* +* INPUTS: +* en - GT_TRUE if Rsvd2Cpu is set. GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetRsvd2Cpu +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRsvd2Cpu +* +* DESCRIPTION: +* When the Rsvd2Cpu is set to a one(GT_TRUE), frames with a Destination +* Address in the range 01:80:C2:00:00:0x, regardless of their VLAN +* membership, will be considered MGMT frames and sent to the port's CPU +* Port as long as the associated Rsvd2CpuEnable bit (gsysSetRsvd2CpuEnable +* function) for the frames's DA is also set to a one. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if Rsvd2Cpu is set. GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetRsvd2Cpu +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetMGMTPri +* +* DESCRIPTION: +* These bits are used as the PRI[2:0] bits on Rsvd2CPU MGMT frames. +* +* INPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - If pri is not less than 8. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetMGMTPri +( + IN GT_QD_DEV *dev, + IN GT_U16 pri +); + +/******************************************************************************* +* gsysGetMGMTPri +* +* DESCRIPTION: +* These bits are used as the PRI[2:0] bits on Rsvd2CPU MGMT frames. +* +* INPUTS: +* None. +* +* OUTPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetMGMTPri +( + IN GT_QD_DEV *dev, + OUT GT_U16 *pri +); + +/******************************************************************************* +* gsysSetUseDoubleTagData +* +* DESCRIPTION: +* This bit is used to determine if Double Tag data that is removed from a +* Double Tag frame is used or ignored when making switching decisions on +* the frame. +* +* INPUTS: +* en - GT_TRUE to use removed tag data, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetUseDoubleTagData +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetUseDoubleTagData +* +* DESCRIPTION: +* This bit is used to determine if Double Tag data that is removed from a +* Double Tag frame is used or ignored when making switching decisions on +* the frame. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if removed tag data is used, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetUseDoubleTagData +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetPreventLoops +* +* DESCRIPTION: +* When a Marvell Tag port receives a Forward Marvell Tag whose Src_Dev +* field equals this device's Device Number, the following action will be +* taken depending upon the value of this bit. +* GT_TRUE (1) - The frame will be discarded. +* GT_FALSE(0) - The frame will be prevented from going out its original +* source port as defined by the frame's Src_Port field. +* +* INPUTS: +* en - GT_TRUE to discard the frame as described above, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetPreventLoops +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetPreventLoops +* +* DESCRIPTION: +* When a Marvell Tag port receives a Forward Marvell Tag whose Src_Dev +* field equals this device's Device Number, the following action will be +* taken depending upon the value of this bit. +* GT_TRUE (1) - The frame will be discarded. +* GT_FALSE(0) - The frame will be prevented from going out its original +* source port as defined by the frame's Src_Port field. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to discard the frame as described above, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetPreventLoops +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetFlowControlMessage +* +* DESCRIPTION: +* When this bit is set to one, Marvell Tag Flow Control messages will be +* generated when an output queue becomes congested and received Marvell Tag +* Flow Control messages will pause MACs inside this device. When this bit +* is cleared to a zero, Marvell Tag Flow Control messages will not be +* generated and any received will be ignored at the target MAC. +* +* INPUTS: +* en - GT_TRUE to use Marvell Tag Flow Control message, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetFlowControlMessage +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetFlowControlMessage +* +* DESCRIPTION: +* When this bit is set to one, Marvell Tag Flow Control messages will be +* generated when an output queue becomes congested and received Marvell Tag +* Flow Control messages will pause MACs inside this device. When this bit +* is cleared to a zero, Marvell Tag Flow Control messages will not be +* generated and any received will be ignored at the target MAC. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to use Marvell Tag Flow Control message, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetFlowControlMessage +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetForceFlowControlPri +* +* DESCRIPTION: +* When this bit is set to a one the PRI[2:0] bits of generated Marvell Tag +* Flow Control frames will be set to the value of the FC Pri bits (set by +* gsysSetFCPri function call). When this bit is cleared to a zero, generated +* Marvell Tag Flow Control frames will retain the PRI[2:0] bits from the +* frames that caused the congestion. This bit will have no effect if the +* FlowControlMessage bit(gsysSetFlowControlMessage function call) is +* cleared to a zero. +* +* INPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetForceFlowControlPri +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetForceFlowControlPri +* +* DESCRIPTION: +* When this bit is set to a one the PRI[2:0] bits of generated Marvell Tag +* Flow Control frames will be set to the value of the FC Pri bits (set by +* gsysSetFCPri function call). When this bit is cleared to a zero, generated +* Marvell Tag Flow Control frames will retain the PRI[2:0] bits from the +* frames that caused the congestion. This bit will have no effect if the +* FlowControlMessage bit(gsysSetFlowControlMessage function call) is +* cleared to a zero. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetForceFlowControlPri +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetFCPri +* +* DESCRIPTION: +* These bits are used as the PRI[2:0] bits on generated Marvell Tag Flow +* Control frames if the ForceFlowControlPri bit(gsysSetForceFlowControlPri) +* is set to a one. +* +* INPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - If pri is not less than 8. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetFCPri +( + IN GT_QD_DEV *dev, + IN GT_U16 pri +); + +/******************************************************************************* +* gsysGetFCPri +* +* DESCRIPTION: +* These bits are used as the PRI[2:0] bits on generated Marvell Tag Flow +* Control frames if the ForceFlowControlPri bit(gsysSetForceFlowControlPri) +* is set to a one. +* +* INPUTS: +* None. +* +* OUTPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetFCPri +( + IN GT_QD_DEV *dev, + OUT GT_U16 *pri +); + +/******************************************************************************* +* gsysSetFlowCtrlDelay +* +* DESCRIPTION: +* This function sets Flow control delay time for 10Mbps, 100Mbps, and +* 1000Mbps. +* +* INPUTS: +* sp - PORT_SPEED_10_MBPS, PORT_SPEED_100_MBPS, or PORT_SPEED_1000_MBPS +* delayTime - actual delay time will be (this value x 2.048uS). +* the value cannot exceed 0x1FFF (or 8191 in decimal). +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if sp is not valid or delayTime is > 0x1FFF. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetFlowCtrlDelay +( + IN GT_QD_DEV *dev, + IN GT_PORT_SPEED_MODE sp, + IN GT_U32 delayTime +); + +/******************************************************************************* +* gsysGetFlowCtrlDelay +* +* DESCRIPTION: +* This function retrieves Flow control delay time for 10Mbps, 100Mbps, and +* 1000Mbps. +* +* INPUTS: +* sp - PORT_SPEED_10_MBPS, PORT_SPEED_100_MBPS, or PORT_SPEED_1000_MBPS +* +* OUTPUTS: +* delayTime - actual delay time will be (this value x 2.048uS). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if sp is not valid or delayTime is > 0x1FFF. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetFlowCtrlDelay +( + IN GT_QD_DEV *dev, + IN GT_PORT_SPEED_MODE sp, + OUT GT_U32 *delayTime +); + +/******************************************************************************* +* gsysSetDevRoutingTable +* +* DESCRIPTION: +* This function sets Device to Port mapping (which device is connected to +* which port of this device). +* +* INPUTS: +* devNum - target device number. +* portNum - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if devNum >= 32 or port >= total number of ports. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetDevRoutingTable +( + IN GT_QD_DEV *dev, + IN GT_U32 devNum, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetDevRoutingTable +* +* DESCRIPTION: +* This function gets Device to Port mapping (which device is connected to +* which port of this device). +* +* INPUTS: +* devNum - target device number. +* +* OUTPUTS: +* portNum - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if devNum >= 32 +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetDevRoutingTable +( + IN GT_QD_DEV *dev, + IN GT_U32 devNum, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetTrunkMaskTable +* +* DESCRIPTION: +* This function sets Trunk mask vector table for load balancing. +* This vector will be AND'ed with where the frame was originally egressed to. +* To insure all trunks are load balanced correctly, the data in this table +* needs to be correctly configured. +* +* INPUTS: +* trunkNum - one of the eight Trunk mask vectors. +* trunkMask - Trunk Mask bits. Bit 0 controls trunk masking for port 0, +* bit 1 for port 1 , etc. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkNum > 0x7 or trunMask > 0x7FF (or port vector). +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetTrunkMaskTable +( + IN GT_QD_DEV *dev, + IN GT_U32 trunkNum, + IN GT_U32 trunkMask +); + +/******************************************************************************* +* gsysGetTrunkMaskTable +* +* DESCRIPTION: +* This function sets Trunk mask vector table for load balancing. +* This vector will be AND'ed with where the frame was originally egressed to. +* To insure all trunks are load balanced correctly, the data in this table +* needs to be correctly configured. +* +* INPUTS: +* trunkNum - one of the eight Trunk mask vectors. +* +* OUTPUTS: +* trunkMask - Trunk Mask bits. Bit 0 controls trunk masking for port 0, +* bit 1 for port 1 , etc. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkNum > 0x7. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetTrunkMaskTable +( + IN GT_QD_DEV *dev, + IN GT_U32 trunkNum, + OUT GT_U32 *trunkMask +); + +/******************************************************************************* +* gsysSetHashTrunk +* +* DESCRIPTION: +* Hash DA & SA for TrunkMask selection. Trunk load balancing is accomplished +* by using the frame's DA and SA fields to access one of eight Trunk Masks. +* When this bit is set to a one, the hashed computed for address table +* lookups is used for the TrunkMask selection. When this bit is cleared to +* a zero the lower 3 bits of the frame's DA and SA are XOR'ed together to +* select the TrunkMask to use. +* +* INPUTS: +* en - GT_TRUE to use lookup table, GT_FALSE to use XOR. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetHashTrunk +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetHashTrunk +* +* DESCRIPTION: +* Hash DA & SA for TrunkMask selection. Trunk load balancing is accomplished +* by using the frame's DA and SA fields to access one of eight Trunk Masks. +* When this bit is set to a one, the hashed computed for address table +* lookups is used for the TrunkMask selection. When this bit is cleared to +* a zero the lower 3 bits of the frame's DA and SA are XOR'ed together to +* select the TrunkMask to use. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to use lookup table, GT_FALSE to use XOR. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetHashTrunk +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetTrunkRouting +* +* DESCRIPTION: +* This function sets routing information for the given Trunk ID. +* +* INPUTS: +* trunkId - Trunk ID. +* trunkRoute - Trunk route bits. Bit 0 controls trunk routing for port 0, +* bit 1 for port 1 , etc. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkId > 0xF or trunkRoute > 0x7FF(or port vector). +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysSetTrunkRouting +( + IN GT_QD_DEV *dev, + IN GT_U32 trunkId, + IN GT_U32 trunkRoute +); + +/******************************************************************************* +* gsysGetTrunkRouting +* +* DESCRIPTION: +* This function retrieves routing information for the given Trunk ID. +* +* INPUTS: +* trunkId - Trunk ID. +* +* OUTPUTS: +* trunkRoute - Trunk route bits. Bit 0 controls trunk routing for port 0, +* bit 1 for port 1 , etc. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkId > 0xF. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetTrunkRouting +( + IN GT_QD_DEV *dev, + IN GT_U32 trunkId, + OUT GT_U32 *trunkRoute +); + + + +/* Prototype added for 88E6095 Rev 1 or Rev 2 */ + +/* gtPortCtrl.c */ +/******************************************************************************* +* gprtGetDiscardBCastMode +* +* DESCRIPTION: +* This routine gets the Discard Broadcast Mode. If the mode is enabled, +* all the broadcast frames to the given port will be discarded. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* en - GT_TRUE, if enabled, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardBCastMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gprtSetDiscardBCastMode +* +* DESCRIPTION: +* This routine sets the Discard Broadcast mode. +* If the mode is enabled, all the broadcast frames to the given port will +* be discarded. +* +* INPUTS: +* port - logical port number +* en - GT_TRUE, to enable the mode, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardBCastMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + +/******************************************************************************* +* gprtGetFCOnRateLimitMode +* +* DESCRIPTION: +* This routine returns mode that tells if ingress rate limiting uses Flow +* Control. When this mode is enabled and the port receives frames over the +* limit, Ingress Rate Limiting will be performed by stalling the +* link partner using flow control, instead of discarding frames. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* en - GT_TRUE, if the mode is enabled, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetFCOnRateLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gprtSetFCOnRateLimitMode +* +* DESCRIPTION: +* This routine sets the mode that tells if ingress rate limiting uses Flow +* Control. When this mode is enabled and the port receives frames over the +* limit, Ingress Rate Limiting will be performed by stalling the +* link partner using flow control, instead of discarding frames. +* +* INPUTS: +* port - logical port number +* en - GT_TRUE, to enable the mode, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetFCOnRateLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + +/* gtPortRateCtrl.c */ + +/******************************************************************************* +* grcSetBurstRate +* +* DESCRIPTION: +* This routine sets the port's ingress data limit based on burst size. +* +* INPUTS: +* port - logical port number. +* bsize - burst size. +* rate - ingress data rate limit. These frames will be discarded after +* the ingress rate selected is reached or exceeded. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* Minimum rate for Burst Size 24K byte is 128Kbps +* Minimum rate for Burst Size 48K byte is 256Kbps +* Minimum rate for Burst Size 96K byte is 512Kbps +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* If the device supports both priority based Rate Limiting and burst size +* based Rate limiting, user has to manually change the mode to burst size +* based Rate limiting by calling gsysSetRateLimitMode. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetBurstRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BURST_SIZE bsize, + IN GT_BURST_RATE rate +); + +/******************************************************************************* +* grcGetBurstRate +* +* DESCRIPTION: +* This routine retrieves the port's ingress data limit based on burst size. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* bsize - burst size. +* rate - ingress data rate limit. These frames will be discarded after +* the ingress rate selected is reached or exceeded. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetBurstRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BURST_SIZE *bsize, + OUT GT_BURST_RATE *rate +); + + +/******************************************************************************* +* grcSetTCPBurstRate +* +* DESCRIPTION: +* This routine sets the port's TCP/IP ingress data limit based on burst size. +* +* INPUTS: +* port - logical port number. +* rate - ingress data rate limit for TCP/IP packets. These frames will +* be discarded after the ingress rate selected is reached or exceeded. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* Valid rate is GT_BURST_NO_LIMIT, or between +* 64Kbps and 1500Kbps. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* If the device supports both priority based Rate Limiting and burst size +* based Rate limiting, user has to manually change the mode to burst size +* based Rate limiting by calling gsysSetRateLimitMode. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetTCPBurstRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BURST_RATE rate +); + + +/******************************************************************************* +* grcGetTCPBurstRate +* +* DESCRIPTION: +* This routine sets the port's TCP/IP ingress data limit based on burst size. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* rate - ingress data rate limit for TCP/IP packets. These frames will +* be discarded after the ingress rate selected is reached or exceeded. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_VALUE - register value is not known +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* If the device supports both priority based Rate Limiting and burst size +* based Rate limiting, user has to manually change the mode to burst size +* based Rate limiting by calling gsysSetRateLimitMode. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetTCPBurstRate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BURST_RATE *rate +); + + +/* gtSysCtrl.c */ +/******************************************************************************* +* gsysSetRateLimitMode +* +* DESCRIPTION: +* Ingress Rate Limiting can be either Priority based or Burst Size based. +* This routine sets which mode to use. +* +* INPUTS: +* mode - either GT_RATE_PRI_BASE or GT_RATE_BURST_BASE +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid mode is used. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRateLimitMode +( + IN GT_QD_DEV *dev, + IN GT_INGRESS_RATE_MODE mode +); + +/******************************************************************************* +* gsysGetRateLimitMode +* +* DESCRIPTION: +* Ingress Rate Limiting can be either Priority based or Burst Size based. +* This routine gets which mode is being used. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - either GT_RATE_PRI_BASE or GT_RATE_BURST_BASE +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRateLimitMode +( + IN GT_QD_DEV *dev, + OUT GT_INGRESS_RATE_MODE *mode +); + +/******************************************************************************* +* gsysSetAgeInt +* +* DESCRIPTION: +* Enable/Disable Age Refresh Interrupt. If CPU Directed Learning is being +* used (gprtSetLockedPort), it may be desirable to know when an address is +* still being used before it totally ages out of the switch. This can be +* accomplished by enabling Age Refresh Interrupt (or ATU Age Violation Int). +* An ATU Age Violation looks identical to and reported the same as an ATU +* Miss Violation. The only difference is when this reported. Normal ATU Miss +* Violation only occur if a new SA arrives at a LockedPort. The Age version +* of the ATU Miss Violation occurs if an SA arrives at a LockedPort, where +* the address is contained in the ATU's database, but where its EntryState +* is less than 0x4 (i.e., it has aged more than 1/2 way). +* GT_ATU_PROB Interrupt should be enabled for this interrupt to occur. +* Refer to eventSetActive routine to enable GT_ATU_PROB. +* +* +* INPUTS: +* en - GT_TRUE, to enable, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetAgeInt +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetAgeInt +* +* DESCRIPTION: +* Get state of Age Refresh Interrupt mode. If CPU Directed Learning is being +* used (gprtSetLockedPort), it may be desirable to know when an address is +* still being used before it totally ages out of the switch. This can be +* accomplished by enabling Age Refresh Interrupt (or ATU Age Violation Int). +* An ATU Age Violation looks identical to and reported the same as an ATU +* Miss Violation. The only difference is when this reported. Normal ATU Miss +* Violation only occur if a new SA arrives at a LockedPort. The Age version +* of the ATU Miss Violation occurs if an SA arrives at a LockedPort, where +* the address is contained in the ATU's database, but where its EntryState +* is less than 0x4 (i.e., it has aged more than 1/2 way). +* GT_ATU_PROB Interrupt should be enabled for this interrupt to occur. +* Refer to eventSetActive routine to enable GT_ATU_PROB. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE, if enabled, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetAgeInt +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + + +/* For Zephyr */ + +/* gtPhyCtrl.c */ +/******************************************************************************* +* gprtGetPhyLinkStatus +* +* DESCRIPTION: +* This routine retrieves the Link status. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* linkStatus - GT_FALSE if link is not established, +* GT_TRUE if link is established. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyLinkStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL *linkStatus +); + + +/******************************************************************************* +* gprtSetPktGenEnable +* +* DESCRIPTION: +* This routine enables or disables Packet Generator. +* Link should be established first prior to enabling the packet generator, +* and generator will generate packets at the speed of the established link. +* When enables packet generator, the following information should be +* provided: +* Payload Type: either Random or 5AA55AA5 +* Packet Length: either 64 or 1514 bytes +* Error Packet: either Error packet or normal packet +* +* INPUTS: +* port - The logical port number +* en - GT_TRUE to enable, GT_FALSE to disable +* pktInfo - packet information(GT_PG structure pointer), if en is GT_TRUE. +* ignored, if en is GT_FALSE +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPktGenEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en, + IN GT_PG *pktInfo +); + +/******************************************************************************* +* gprtGetSerdesMode +* +* DESCRIPTION: +* This routine reads Serdes Interface Mode. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* mode - Serdes Interface Mode +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSerdesMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SERDES_MODE *mode +); + +/******************************************************************************* +* gprtSetSerdesMode +* +* DESCRIPTION: +* This routine sets Serdes Interface Mode. +* +* INPUTS: +* port - logical port number +* mode - Serdes Interface Mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetSerdesMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SERDES_MODE mode +); + + +/* gtSysCtrl.c */ + +/******************************************************************************* +* gsysSetForceSnoopPri +* +* DESCRIPTION: +* Force Snooping Priority. The priority on IGMP or MLD Snoop frames are +* set to the SnoopPri value (gsysSetSnoopPri API) when Force Snooping +* Priority is enabled. When it's disabled, the priority on these frames +* is not modified. +* +* INPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetForceSnoopPri +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetForceSnoopPri +* +* DESCRIPTION: +* Force Snooping Priority. The priority on IGMP or MLD Snoop frames are +* set to the SnoopPri value (gsysSetSnoopPri API) when Force Snooping +* Priority is enabled. When it's disabled, the priority on these frames +* is not modified. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetForceSnoopPri +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gsysSetSnoopPri +* +* DESCRIPTION: +* Snoop Priority. When ForceSnoopPri (gsysSetForceSnoopPri API) is enabled, +* this priority is used as the egressing frame's PRI[2:0] bits on generated +* Marvell Tag To_CPU Snoop frames and higher 2 bits of the priority are +* used as the internal Queue Priority to use on IGMP/MLD snoop frames. +* +* INPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - If pri is not less than 8. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetSnoopPri +( + IN GT_QD_DEV *dev, + IN GT_U16 pri +); + + +/******************************************************************************* +* gsysGetSnoopPri +* +* DESCRIPTION: +* Snoop Priority. When ForceSnoopPri (gsysSetForceSnoopPri API) is enabled, +* this priority is used as the egressing frame's PRI[2:0] bits on generated +* Marvell Tag To_CPU Snoop frames and higher 2 bits of the priority are +* used as the internal Queue Priority to use on IGMP/MLD snoop frames. +* +* INPUTS: +* None. +* +* OUTPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetSnoopPri +( + IN GT_QD_DEV *dev, + OUT GT_U16 *pri +); + + +/******************************************************************************* +* gsysSetForceARPPri +* +* DESCRIPTION: +* Force ARP Priority. The priority on ARP frames are set to the ARPPri +* value (gsysSetARPPri API) when Force ARP Priority is enabled. When it's +* disabled, the priority on these frames is not modified. +* +* INPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetForceARPPri +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetForceARPPri +* +* DESCRIPTION: +* Force ARP Priority. The priority on ARP frames are set to the ARPPri +* value (gsysSetARPPri API) when Force ARP Priority is enabled. When it's +* disabled, the priority on these frames is not modified. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to use defined PRI bits, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetForceARPPri +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gsysSetARPPri +* +* DESCRIPTION: +* ARP Priority. When ForceARPPri (gsysSetForceARPPri API) is enabled, +* this priority is used as the egressing frame's PRI[2:0] bits on generated +* Marvell Tag To_CPU ARP frames and higher 2 bits of the priority are +* used as the internal Queue Priority to use on ARP frames. +* +* INPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - If pri is not less than 8. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetARPPri +( + IN GT_QD_DEV *dev, + IN GT_U16 pri +); + + +/******************************************************************************* +* gsysGetARPPri +* +* DESCRIPTION: +* ARP Priority. When ForceARPPri (gsysSetForceARPPri API) is enabled, +* this priority is used as the egressing frame's PRI[2:0] bits on generated +* Marvell Tag To_CPU ARP frames and higher 2 bits of the priority are +* used as the internal Queue Priority to use on ARP frames. +* +* INPUTS: +* None. +* +* OUTPUTS: +* pri - PRI[2:0] bits (should be less than 8) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetARPPri +( + IN GT_QD_DEV *dev, + OUT GT_U16 *pri +); + + +/* added for 88E6065 */ + +/* gtBrgVlan.c */ + +/******************************************************************** +* gvlnSetForceMap +* +* DESCRIPTION: +* This routine enables/disables Force Map feature. +* When Force Map feature is enabled, all received frames will be +* considered MGMT and they are mapped to the port or ports defined +* in the VLAN Table overriding the mapping from the address database. +* +* INPUTS: +* port - logical port number to set. +* mode - GT_TRUE, to enable force map feature +* GT_FAULSE, otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gvlnSetForceMap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + +/******************************************************************** +* gvlnGetForceMap +* +* DESCRIPTION: +* This routine checks if Force Map feature is enabled. +* When Force Map feature is enabled, all received frames will be +* considered MGMT and they are mapped to the port or ports defined +* in the VLAN Table overriding the mapping from the address database. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* mode - GT_TRUE, to enable force map feature +* GT_FAULSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gvlnGetForceMap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/* gtEvents.c */ + +/******************************************************************************* +* geventSetAgeIntEn +* +* DESCRIPTION: +* This routine enables/disables Age Interrupt for a port. +* When it's enabled, ATU Age Violation interrupts from this port are enabled. +* An Age Violation will occur anytime a port is Locked(gprtSetLockedPort) +* and the ingressing frame's SA is contained in the ATU as a non-Static +* entry with a EntryState less than 0x4. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetAgeIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* geventGetAgeIntEn +* +* DESCRIPTION: +* This routine gets Age Interrupt Enable for the port. +* When it's enabled, ATU Age Violation interrupts from this port are enabled. +* An Age Violation will occur anytime a port is Locked(gprtSetLockedPort) +* and the ingressing frame's SA is contained in the ATU as a non-Static +* entry with a EntryState less than 0x4. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetAgeIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/* gtPIRL.c */ + +/******************************************************************************* +* gpirlActivate +* +* DESCRIPTION: +* This routine activates Ingress Rate Limiting for the given ports by +* initializing a resource bucket, assigning ports, and configuring +* Bucket Parameters. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* portVec - the list of ports that share the bucket. +* pirlData - PIRL resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlActivate +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec, + IN GT_PIRL_DATA *pirlData +); + +/******************************************************************************* +* gpirlDeactivate +* +* DESCRIPTION: +* This routine deactivates Ingress Rate Limiting for the given bucket. +* It simply removes every ports from the Ingress Rate Resource. +* It is assumed that gpirlActivate has been successfully called with +* the irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be deactivated +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlDeactivate +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit +); + +/******************************************************************************* +* gpirlUpdateParam +* +* DESCRIPTION: +* This routine updates IRL Parameter. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11) +* pirlData - PIRL resource parameters +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlUpdateParam +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_PIRL_DATA *pirlData +); + +/******************************************************************************* +* gpirlReadParam +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlReadParam +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_PIRL_DATA *pirlData +); + +/******************************************************************************* +* gpirlUpdatePortVec +* +* DESCRIPTION: +* This routine updates port list that share the bucket. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* portVec - the list of ports that share the bucket. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlUpdatePortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec +); + +/******************************************************************************* +* gpirlReadPortVec +* +* DESCRIPTION: +* This routine retrieves port list that share the bucket. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* +* OUTPUTS: +* portVec - the list of ports that share the bucket. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlReadPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_U32 *portVec +); + +/******************************************************************************* +* grcGetPirlFcMode +* +* DESCRIPTION: +* This routine gets Port Ingress Rate Limit Flow Control mode. +* When EBSLimitAction is programmed to generate a flow control message, +* the deassertion of flow control is controlled by this mode. +* GT_PIRL_FC_DEASSERT_EMPTY: +* De-assert when the ingress rate resource has become empty +* GT_PIRL_FC_DEASSERT_CBS_LIMIT +* De-assert when the ingress rate resource has enough room as +* specified by the CBSLimit. +* Please refer to GT_PIRL_RESOURCE structure for EBSLimitAction and +* CBSLimit. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* mode - GT_PIRL_FC_DEASSERT enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcGetPirlFcMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PIRL_FC_DEASSERT *mode +); + +/******************************************************************************* +* gpirlGetIngressRateResource +* +* DESCRIPTION: +* This routine gets Ingress Rate Limiting Resources assigned to the port. +* This vector is used to attach specific counter resources to the physical +* port. And the same counter resource can be attached to more than one port. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* resVec - resource vector (bit 0 for irl unit 0, bit 1 for irl unit 1, etc.) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirlGetIngressRateResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *resVec +); + + + +/* gtPortStatus.c */ + +/******************************************************************************* +* gprtGetPxMode +* +* DESCRIPTION: +* This routine retrives 4 bits of Px_MODE Configuration value. +* If speed and duplex modes are forced, the returned mode value would be +* different from the configuration pin values. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - Px_MODE configuration value +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPxMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *mode +); + +/******************************************************************************* +* gprtGetMiiInterface +* +* DESCRIPTION: +* This routine retrives Mii Interface Mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Mii Interface is enabled, +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetMiiInterface +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetFdFlowDis +* +* DESCRIPTION: +* This routine retrives the read time value of the Full Duplex Flow Disable. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Full Duplex Flow Disable. +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetFdFlowDis +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetHdFlowDis +* +* DESCRIPTION: +* This routine retrives the read time value of the Half Duplex Flow Disable. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Half Duplex Flow Disable. +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetHdFlowDis +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +); + +/******************************************************************************* +* gprtGetOutQSize +* +* DESCRIPTION: +* This routine gets egress queue size counter value. +* This counter reflects the current number of Egress buffers switched to +* this port. This is the total number of buffers across all four priority +* queues. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* count - egress queue size counter value +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetOutQSize +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *count +); + + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtSetSAFiltering +* +* DESCRIPTION: +* This routine set the Source Address(SA) fitering method. +* GT_SA_FILTERING_DISABLE : +* no frame will be filtered. +* GT_SA_DROP_ON_LOCK : +* discard if SA field is not in the ATU's address database. +* GT_SA_DROP_ON_UNLOC : +* discard if SA field is in the ATU's address database as Static +* entry with a PortVec of all zeros. +* GT_SA_DROP_TO_CPU : +* Ingressing frames will be mapped to the CPU Port if their SA +* field is in the ATU's address database as Static entry with a +* PortVec of all zeros. Otherwise, the frames will be discarded +* if their SA field is not in the ATU's address database or if this +* port's bit is not set in the PortVec bits for the frame's SA. +* +* INPUTS: +* port - the logical port number. +* mode - GT_SA_FILTERING structure +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtSetSAFiltering +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SA_FILTERING mode +); + +/******************************************************************************* +* gprtGetSAFiltering +* +* DESCRIPTION: +* This routine gets the Source Address(SA) fitering method. +* GT_SA_FILTERING_DISABLE : +* no frame will be filtered. +* GT_SA_DROP_ON_LOCK : +* discard if SA field is not in the ATU's address database. +* GT_SA_DROP_ON_UNLOC : +* discard if SA field is in the ATU's address database as Static +* entry with a PortVec of all zeros. +* GT_SA_DROP_TO_CPU : +* Ingressing frames will be mapped to the CPU Port if their SA +* field is in the ATU's address database as Static entry with a +* PortVec of all zeros. Otherwise, the frames will be discarded +* if their SA field is not in the ATU's address database or if this +* port's bit is not set in the PortVec bits for the frame's SA. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_SA_FILTERING structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtGetSAFiltering +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_SA_FILTERING *mode +); + + +/******************************************************************************* +* gprtSetARPtoCPU +* +* DESCRIPTION: +* When ARPtoCPU is set to GT_TRUE, ARP frames are mapped to the CPU port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE, to map ARP frames to CPU Port, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtSetARPtoCPU +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + + +/******************************************************************************* +* gprtGetARPtoCPU +* +* DESCRIPTION: +* When ARPtoCPU is set to GT_TRUE, ARP frames are mapped to the CPU port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE, to map ARP frames to CPU Port, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtGetARPtoCPU +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetEgressFlood +* +* DESCRIPTION: +* This routine set Egress Flooding Mode. +* Frames with unknown DA (Destination Address that is not in ATU database) +* generally flood out all the ports. This mode can be used to prevent +* those frames from egressing this port as follows: +* GT_BLOCK_EGRESS_UNKNOWN +* do not egress frame with unknown DA (both unicast and multicast) +* GT_BLOCK_EGRESS_UNKNOWN_MULTICAST +* do not egress frame with unknown multicast DA +* GT_BLOCK_EGRESS_UNKNOWN_UNICAST +* do not egress frame with unknown unicast DA +* GT_BLOCK_EGRESS_NONE +* egress all frames with unknown DA +* +* INPUTS: +* port - the logical port number. +* mode - GT_EGRESS_FLOOD structure +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressFlood +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EGRESS_FLOOD mode +); + +/******************************************************************************* +* gprtGetEgressFlood +* +* DESCRIPTION: +* This routine gets Egress Flooding Mode. +* Frames with unknown DA (Destination Address that is not in ATU database) +* generally flood out all the ports. This mode can be used to prevent +* those frames from egressing this port as follows: +* GT_BLOCK_EGRESS_UNKNOWN +* do not egress frame with unknown DA (both unicast and multicast) +* GT_BLOCK_EGRESS_UNKNOWN_MULTICAST +* do not egress frame with unknown multicast DA +* GT_BLOCK_EGRESS_UNKNOWN_UNICAST +* do not egress frame with unknown unicast DA +* GT_BLOCK_EGRESS_NONE +* egress all frames with unknown DA +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_EGRESS_FLOOD structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressFlood +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EGRESS_FLOOD *mode +); + +/******************************************************************************* +* gprtSetPortSched +* +* DESCRIPTION: +* This routine sets Port Scheduling Mode. +* When usePortSched is enablied, this mode is used to select the Queue +* controller's scheduling on the port as follows: +* GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling +* GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme +* +* INPUTS: +* port - the logical port number +* mode - GT_PORT_SCHED_MODE enum type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPortSched +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_SCHED_MODE mode +); + +/******************************************************************************* +* gprtGetPortSched +* +* DESCRIPTION: +* This routine gets Port Scheduling Mode. +* When usePortSched is enablied, this mode is used to select the Queue +* controller's scheduling on the port as follows: +* GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling +* GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_PORT_SCHED_MODE enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPortSched +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_SCHED_MODE *mode +); + + +/******************************************************************************* +* gprtSetProviderTag +* +* DESCRIPTION: +* This routine sets Provider Tag which indicates the provider tag (Ether +* Type) value that needs to be matched to in ingress to determine if a +* frame is Provider tagged or not. +* +* INPUTS: +* port - the logical port number +* tag - Provider Tag (Ether Type) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetProviderTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 tag +); + +/******************************************************************************* +* gprtGetProviderTag +* +* DESCRIPTION: +* This routine gets Provider Tag which indicates the provider tag (Ether +* Type) value that needs to be matched to in ingress to determine if a +* frame is Provider tagged or not. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* tag - Provider Tag (Ether Type) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetProviderTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *tag +); + + + +/* gtPortRateCtrl.c */ + +/******************************************************************************* +* grcSetVidNrlEn +* +* DESCRIPTION: +* This routine enables/disables VID None Rate Limit (NRL). +* When VID NRL is enabled and the determined VID of a frame results in a VID +* whose VIDNonRateLimit in the VTU Table is set to GT_TURE, then the frame +* will not be ingress nor egress rate limited. +* +* INPUTS: +* port - logical port number. +* mode - GT_TRUE to enable VID None Rate Limit +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcSetVidNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetVidNrlEn +* +* DESCRIPTION: +* This routine gets VID None Rate Limit (NRL) mode. +* When VID NRL is enabled and the determined VID of a frame results in a VID +* whose VIDNonRateLimit in the VTU Table is set to GT_TURE, then the frame +* will not be ingress nor egress rate limited. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable VID None Rate Limit +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcGetVidNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetSaNrlEn +* +* DESCRIPTION: +* This routine enables/disables SA None Rate Limit (NRL). +* When SA NRL is enabled and the source address of a frame results in a ATU +* hit where the SA's MAC address returns an EntryState that indicates Non +* Rate Limited, then the frame will not be ingress nor egress rate limited. +* +* INPUTS: +* port - logical port number. +* mode - GT_TRUE to enable SA None Rate Limit +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcSetSaNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetSaNrlEn +* +* DESCRIPTION: +* This routine gets SA None Rate Limit (NRL) mode. +* When SA NRL is enabled and the source address of a frame results in a ATU +* hit where the SA's MAC address returns an EntryState that indicates Non +* Rate Limited, then the frame will not be ingress nor egress rate limited. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable SA None Rate Limit +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcGetSaNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetDaNrlEn +* +* DESCRIPTION: +* This routine enables/disables DA None Rate Limit (NRL). +* When DA NRL is enabled and the destination address of a frame results in +* a ATU hit where the DA's MAC address returns an EntryState that indicates +* Non Rate Limited, then the frame will not be ingress nor egress rate +* limited. +* +* INPUTS: +* port - logical port number. +* mode - GT_TRUE to enable DA None Rate Limit +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcSetDaNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* grcGetDaNrlEn +* +* DESCRIPTION: +* This routine gets SA None Rate Limit (NRL) mode. +* When DA NRL is enabled and the destination address of a frame results in +* a ATU hit where the DA's MAC address returns an EntryState that indicates +* Non Rate Limited, then the frame will not be ingress nor egress rate +* limited. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable DA None Rate Limit +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcGetDaNrlEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* grcSetELimitMode +* +* DESCRIPTION: +* This routine sets Egress Rate Limit counting mode. +* The supported modes are as follows: +* GT_PIRL_ELIMIT_FRAME - +* Count the number of frames +* GT_PIRL_ELIMIT_LAYER1 - +* Count all Layer 1 bytes: +* Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes) +* GT_PIRL_ELIMIT_LAYER2 - +* Count all Layer 2 bytes: Frame's DA to CRC +* GT_PIRL_ELIMIT_LAYER1 - +* Count all Layer 1 bytes: +* Frame's DA to CRC - 18 - 4 (if frame is tagged) +* +* INPUTS: +* port - logical port number +* mode - GT_PIRL_ELIMIT_MODE enum type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* GT_PIRL_ELIMIT_FRAME mode is supported by only a few devices. +* Please refer to the device datasheet for details. +* +*******************************************************************************/ +GT_STATUS grcSetELimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PIRL_ELIMIT_MODE mode +); + +/******************************************************************************* +* grcGetELimitMode +* +* DESCRIPTION: +* This routine gets Egress Rate Limit counting mode. +* The supported modes are as follows: +* GT_PIRL_ELIMIT_FRAME - +* Count the number of frames +* GT_PIRL_ELIMIT_LAYER1 - +* Count all Layer 1 bytes: +* Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes) +* GT_PIRL_ELIMIT_LAYER2 - +* Count all Layer 2 bytes: Frame's DA to CRC +* GT_PIRL_ELIMIT_LAYER1 - +* Count all Layer 1 bytes: +* Frame's DA to CRC - 18 - 4 (if frame is tagged) +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* mode - GT_PIRL_ELIMIT_MODE enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* GT_PIRL_ELIMIT_FRAME mode is supported by only a few devices. +* Please refer to the device datasheet for details. +* +*******************************************************************************/ +GT_STATUS grcGetELimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PIRL_ELIMIT_MODE *mode +); + +/******************************************************************************* +* grcSetRsvdNrlEn +* +* DESCRIPTION: +* This routine sets Reserved Non Rate Limit. +* When this feature is enabled, frames that match the requirements of the +* Rsvd2Cpu bit below will also be considered to be ingress and egress non +* rate limited. +* +* INPUTS: +* en - GT_TRUE to enable Reserved Non Rate Limit, +* GT_FALSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS grcSetRsvdNrlEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* grcGetRsvdNrlEn +* +* DESCRIPTION: +* This routine gets Reserved Non Rate Limit. +* When this feature is enabled, frames that match the requirements of the +* Rsvd2Cpu bit below will also be considered to be ingress and egress non +* rate limited. +* +* INPUTS: +* en - GT_TRUE to enable Reserved Non Rate Limit, +* GT_FALSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS grcGetRsvdNrlEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + + +/* gtPortRmon.c */ + +/******************************************************************************* +* gstatsGetRealtimePortCounter +* +* DESCRIPTION: +* This routine gets a specific realtime counter of the given port +* +* INPUTS: +* port - the logical port number. +* counter - the counter which will be read +* +* OUTPUTS: +* statsData - points to 32bit data storage for the MIB counter +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstatsGetRealtimePortCounter +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_STATS_COUNTERS3 counter, + OUT GT_U32 *statsData +); + + +/* gtQosMap.c */ + +/******************************************************************************* +* gqosSetVIDFPriOverride +* +* DESCRIPTION: +* This routine sets VID Frame Priority Override. When this feature is enabled, +* VID Frame priority overrides can occur on this port. +* VID Frame priority override occurs when the determined VID of a frame +* results in a VTU entry whose useVIDFPri override field is set to GT_TRUE. +* When this occurs the VIDFPri value assigned to the frame's VID (in the +* VTU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new VIDFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for VID Frame Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetVIDFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetVIDFPriOverride +* +* DESCRIPTION: +* This routine gets VID Frame Priority Override. When this feature is enabled, +* VID Frame priority overrides can occur on this port. +* VID Frame priority override occurs when the determined VID of a frame +* results in a VTU entry whose useVIDFPri override field is set to GT_TRUE. +* When this occurs the VIDFPri value assigned to the frame's VID (in the +* VTU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new VIDFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for VID Frame Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetVIDFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetSAFPriOverride +* +* DESCRIPTION: +* This routine sets Source Address(SA) Frame Priority Override. +* When this feature is enabled, SA Frame priority overrides can occur on +* this port. +* SA ATU Frame priority override occurs when the determined source address +* of a frame results in an ATU hit where the SA's MAC address entry contains +* the useATUFPri field set to GT_TRUE. +* When this occurs the ATUFPri value assigned to the frame's SA (in the +* ATU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new ATUFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for SA Frame Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetSAFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetSAFPriOverride +* +* DESCRIPTION: +* This routine gets Source Address(SA) Frame Priority Override. +* When this feature is enabled, SA Frame priority overrides can occur on +* this port. +* SA ATU Frame priority override occurs when the determined source address +* of a frame results in an ATU hit where the SA's MAC address entry contains +* the useATUFPri field set to GT_TRUE. +* When this occurs the ATUFPri value assigned to the frame's SA (in the +* ATU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new ATUFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for SA Frame Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetSAFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetDAFPriOverride +* +* DESCRIPTION: +* This routine sets Destination Address(DA) Frame Priority Override. +* When this feature is enabled, DA Frame priority overrides can occur on +* this port. +* DA ATU Frame priority override occurs when the determined destination address +* of a frame results in an ATU hit where the DA's MAC address entry contains +* the useATUFPri field set to GT_TRUE. +* When this occurs the ATUFPri value assigned to the frame's DA (in the +* ATU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new ATUFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for DA Frame Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetDAFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetDAFPriOverride +* +* DESCRIPTION: +* This routine gets Destination Address(DA) Frame Priority Override. +* When this feature is enabled, DA Frame priority overrides can occur on +* this port. +* DA ATU Frame priority override occurs when the determined destination address +* of a frame results in an ATU hit where the DA's MAC address entry contains +* the useATUFPri field set to GT_TRUE. +* When this occurs the ATUFPri value assigned to the frame's DA (in the +* ATU Table) is used to overwrite the frame's previously determined frame +* priority. If the frame egresses tagged the priority in the frame will be +* this new ATUFPri value. This function does not affect the egress queue +* priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for DA Frame Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetDAFPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetVIDQPriOverride +* +* DESCRIPTION: +* This routine sets VID Queue Priority Override. When this feature is enabled, +* VID Queue priority overrides can occur on this port. +* VID Queue priority override occurs when the determined VID of a frame +* results in a VTU entry whose useVIDQPri override field is set to GT_TRUE. +* When this occurs the VIDQPri value assigned to the frame's VID (in the +* VTU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new VIDQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for VID Queue Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetVIDQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetVIDQPriOverride +* +* DESCRIPTION: +* This routine gets VID Queue Priority Override. When this feature is enabled, +* VID Queue priority overrides can occur on this port. +* VID Queue priority override occurs when the determined VID of a frame +* results in a VTU entry whose useVIDQPri override field is set to GT_TRUE. +* When this occurs the VIDQPri value assigned to the frame's VID (in the +* VTU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new VIDQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for VID Queue Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetVIDQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetSAQPriOverride +* +* DESCRIPTION: +* This routine sets Source Address(SA) Queue Priority Override. +* When this feature is enabled, SA Queue priority overrides can occur on +* this port. +* SA ATU Queue priority override occurs when the determined source address +* of a frame results in an ATU hit where the SA's MAC address entry contains +* the useATUQPri field set to GT_TRUE. +* When this occurs the ATUQPri value assigned to the frame's SA (in the +* ATU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new ATUQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for SA Queue Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetSAQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetSAQPriOverride +* +* DESCRIPTION: +* This routine gets Source Address(SA) Queue Priority Override. +* When this feature is enabled, SA Queue priority overrides can occur on +* this port. +* SA ATU Queue priority override occurs when the determined source address +* of a frame results in an ATU hit where the SA's MAC address entry contains +* the useATUQPri field set to GT_TRUE. +* When this occurs the ATUQPri value assigned to the frame's SA (in the +* ATU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new ATUQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for SA Queue Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetSAQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetDAQPriOverride +* +* DESCRIPTION: +* This routine sets Destination Address(DA) Queue Priority Override. +* When this feature is enabled, DA Queue priority overrides can occur on +* this port. +* DA ATU Queue priority override occurs when the determined destination address +* of a frame results in an ATU hit where the DA's MAC address entry contains +* the useATUQPri field set to GT_TRUE. +* When this occurs the ATUQPri value assigned to the frame's DA (in the +* ATU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new ATUQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for DA Queue Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetDAQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetDAQPriOverride +* +* DESCRIPTION: +* This routine sets Destination Address(DA) Queue Priority Override. +* When this feature is enabled, DA Queue priority overrides can occur on +* this port. +* DA ATU Queue priority override occurs when the determined destination address +* of a frame results in an ATU hit where the DA's MAC address entry contains +* the useATUQPri field set to GT_TRUE. +* When this occurs the ATUQPri value assigned to the frame's DA (in the +* ATU Table) is used to overwrite the frame's previously determined queue +* priority. If the frame egresses tagged the priority in the frame will not +* be modified by this new ATUQPri value. This function affects the egress +* queue priority (QPri) the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for DA Queue Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetDAQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gqosSetARPQPriOverride +* +* DESCRIPTION: +* This routine sets ARP Queue Priority Override. +* When this feature is enabled, ARP Queue priority overrides can occur on +* this port. +* ARP Queue priority override occurs for all ARP frames. +* When this occurs, the frame's previously determined egress queue priority +* will be overwritten with ArpQPri. +* If the frame egresses tagged the priority in the frame will not +* be modified. When used, the two bits of the ArpQPri priority determine the +* egress queue the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for ARP Queue Priority Override, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosSetARPQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gqosGetARPQPriOverride +* +* DESCRIPTION: +* This routine sets ARP Queue Priority Override. +* When this feature is enabled, ARP Queue priority overrides can occur on +* this port. +* ARP Queue priority override occurs for all ARP frames. +* When this occurs, the frame's previously determined egress queue priority +* will be overwritten with ArpQPri. +* If the frame egresses tagged the priority in the frame will not +* be modified. When used, the two bits of the ArpQPri priority determine the +* egress queue the frame is switched into. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for ARP Queue Priority Override, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gqosGetARPQPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + + +/******************************************************************************* +* gqosSetQPriValue +* +* DESCRIPTION: +* This routine sets Queue priority value to used when forced. +* When ForceQPri is enabled (gqosSetForceQPri), all frames entering this port +* are mapped to the priority queue defined in this value, unless a VTU, SA, +* DA or ARP priority override occurs. The Frame's priority (FPri) is not +* effected by this value. +* +* INPUTS: +* port - the logical port number. +* pri - Queue priority value +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if pri > 3 +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosSetQPriValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 pri +); + +/******************************************************************************* +* gqosGetQPriValue +* +* DESCRIPTION: +* This routine gets Queue priority value to used when forced. +* When ForceQPri is enabled (gqosSetForceQPri), all frames entering this port +* are mapped to the priority queue defined in this value, unless a VTU, SA, +* DA or ARP priority override occurs. The Frame's priority (FPri) is not +* effected by this value. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* pri - Queue priority value +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosGetQPriValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U8 *pri +); + +/******************************************************************************* +* gqosSetForceQPri +* +* DESCRIPTION: +* This routine enables/disables forcing Queue priority. +* When ForceQPri is disabled, normal priority queue mapping is used on all +* ingressing frames entering this port. When it's enabled, all frames +* entering this port are mapped to the QPriValue (gqosSetQPriValue), unless +* a VTU, SA, DA or ARP priority override occurs. The frame's priorty (FPri) +* is not effected by this feature. +* +* INPUTS: +* port - the logical port number. +* en - GT_TRUE, to force Queue Priority, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosSetForceQPri +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + +/******************************************************************************* +* gqosGetForceQPri +* +* DESCRIPTION: +* This routine checks if forcing Queue priority is enabled. +* When ForceQPri is disabled, normal priority queue mapping is used on all +* ingressing frames entering this port. When it's enabled, all frames +* entering this port are mapped to the QPriValue (gqosSetQPriValue), unless +* a VTU, SA, DA or ARP priority override occurs. The frame's priorty (FPri) +* is not effected by this feature. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* en - GT_TRUE, to force Queue Priority, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosGetForceQPri +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gqosSetDefFPri +* +* DESCRIPTION: +* This routine sets the default frame priority (0 ~ 7). +* This priority is used as the default frame priority (FPri) to use when +* no other priority information is available. +* +* INPUTS: +* port - the logical port number +* pri - default frame priority +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if pri > 7 +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosSetDefFPri +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 pri +); + +/******************************************************************************* +* gqosGetDefFPri +* +* DESCRIPTION: +* This routine gets the default frame priority (0 ~ 7). +* This priority is used as the default frame priority (FPri) to use when +* no other priority information is available. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* pri - default frame priority +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gqosGetDefFPri +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U8 *pri +); + + +/******************************************************************************* +* gqosSetArpQPri +* +* DESCRIPTION: +* This routine sets ARP queue Priority to use for ARP QPri Overridden +* frames. When a ARP frame is received on a por tthat has its ARP +* QPriOVerride is enabled, the QPri assigned to the frame comes from +* this value +* +* INPUTS: +* pri - ARP Queue Priority (0 ~ 3) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if pri > 3 +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gqosSetArpQPri +( + IN GT_QD_DEV *dev, + IN GT_U8 pri +); + + +/******************************************************************************* +* gqosGetArpQPri +* +* DESCRIPTION: +* This routine gets ARP queue Priority to use for ARP QPri Overridden +* frames. When a ARP frame is received on a por tthat has its ARP +* QPriOVerride is enabled, the QPri assigned to the frame comes from +* this value +* +* INPUTS: +* None. +* +* OUTPUTS: +* pri - ARP Queue Priority (0 ~ 3) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gqosGetArpQPri +( + IN GT_QD_DEV *dev, + OUT GT_U8 *pri +); + + +/* gtSysCtrl.c */ + +/******************************************************************************* +* gsysSetUsePortSchedule +* +* DESCRIPTION: +* This routine sets per port scheduling mode +* +* INPUTS: +* en - GT_TRUE enables per port scheduling, +* GT_FALSE disable. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetUsePortSchedule +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetUsePortSchedule +* +* DESCRIPTION: +* This routine gets per port scheduling mode +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE enables per port scheduling, +* GT_FALSE disable. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetUsePortSchedule +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetOldHader +* +* DESCRIPTION: +* This routine sets Egress Old Header. +* When this feature is enabled and frames are egressed with a Marvell Header, +* the format of the Header is slightly modified to be backwards compatible +* with previous devices that used the original Header. Specifically, bit 3 +* of the Header's 2nd octet is cleared to a zero such that only FPri[2:1] +* is available in the Header. +* +* INPUTS: +* en - GT_TRUE to enable Old Header Mode, +* GT_FALSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetOldHader +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetOldHader +* +* DESCRIPTION: +* This routine gets Egress Old Header. +* When this feature is enabled and frames are egressed with a Marvell Header, +* the format of the Header is slightly modified to be backwards compatible +* with previous devices that used the original Header. Specifically, bit 3 +* of the Header's 2nd octet is cleared to a zero such that only FPri[2:1] +* is available in the Header. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to enable Old Header Mode, +* GT_FALSE to disable +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetOldHader +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetRecursiveStrippingDisable +* +* DESCRIPTION: +* This routine determines if recursive tag stripping feature needs to be +* disabled. +* +* INPUTS: +* en - GT_TRUE to disable Recursive Tag Stripping, +* GT_FALSE to enable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRecursiveStrippingDisable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRecursiveStrippingDisable +* +* DESCRIPTION: +* This routine checks if recursive tag stripping feature is disabled. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE, if Recursive Tag Stripping is disabled, +* GT_FALSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRecursiveStrippingDisable +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetCPUPort +* +* DESCRIPTION: +* This routine sets CPU Port where Rsvd2Cpu frames and IGMP/MLD Snooped +* frames are destined. +* +* INPUTS: +* cpuPort - CPU Port +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetCPUPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT cpuPort +); + +/******************************************************************************* +* gsysGetCPUPort +* +* DESCRIPTION: +* This routine gets CPU Port where Rsvd2Cpu frames and IGMP/MLD Snooped +* frames are destined. +* +* INPUTS: +* cpuPort - CPU Port +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetCPUPort +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *cpuPort +); + + + +/* gtSysStatus.c */ + +/******************************************************************************* +* gsysGetFreeQSize +* +* DESCRIPTION: +* This routine gets Free Queue Counter. This counter reflects the +* current number of unalllocated buffers available for all the ports. +* +* INPUTS: +* None. +* +* OUTPUTS: +* count - Free Queue Counter +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gsysGetFreeQSize +( + IN GT_QD_DEV *dev, + OUT GT_U16 *count +); + +/******************************************************************************* + New APIs in DSDT 2.6 +*******************************************************************************/ + +/* gtBrgFdb.c */ + +/******************************************************************************* +* gfdbSetPortAtuLearnLimit +* +* DESCRIPTION: +* Port's auto learning limit. When the limit is non-zero value, the number +* of MAC addresses that can be learned on this port are limited to the value +* specified in this API. When the learn limit has been reached any frame +* that ingresses this port with a source MAC address not already in the +* address database that is associated with this port will be discarded. +* Normal auto-learning will resume on the port as soon as the number of +* active unicast MAC addresses associated to this port is less than the +* learn limit. +* CPU directed ATU Load, Purge, or Move will not have any effect on the +* learn limit. +* This feature is disabled when the limit is zero. +* The following care is needed when enabling this feature: +* 1) disable learning on the ports +* 2) flush all non-static addresses in the ATU +* 3) define the desired limit for the ports +* 4) re-enable learing on the ports +* +* INPUTS: +* port - logical port number +* limit - auto learning limit ( 0 ~ 255 ) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetPortAtuLearnLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 limit +); + + +/******************************************************************************* +* gfdbGetPortAtuLearnCnt +* +* DESCRIPTION: +* Read the current number of active unicast MAC addresses associated with +* the given port. This counter (LearnCnt) is held at zero if learn limit +* (gfdbSetPortAtuLearnLimit API) is set to zero. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* count - current auto learning count +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetPortAtuLearnCnt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 *count +); + +/******************************************************************************* +* gfdbGetAtuAllCount +* +* DESCRIPTION: +* Counts all entries in the Address Translation Unit. +* +* INPUTS: +* None. +* +* OUTPUTS: +* count - number of valid entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuAllCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *count +); + +/******************************************************************************* +* gfdbGetAtuAllCountInDBNum +* +* DESCRIPTION: +* Counts all entries in the defined FID (or DBNum). +* +* INPUTS: +* dbNum - DBNum of FID +* +* OUTPUTS: +* count - number of valid entries in FID (or DBNum). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuAllCountInDBNum +( + IN GT_QD_DEV *dev, + IN GT_U32 dbNum, + OUT GT_U32 *count +); + +/******************************************************************************* +* gfdbGetAtuDynamicCountInDBNum +* +* DESCRIPTION: +* Counts all non-static entries in the defined FID (or DBNum). +* +* INPUTS: +* dbNum - DBNum or FID +* +* OUTPUTS: +* count - number of valid non-static entries in FID (or DBNum). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuDynamicCountInDBNum +( + IN GT_QD_DEV *dev, + IN GT_U32 dbNum, + OUT GT_U32 *count +); + + +/* gtBrgStu.c */ + +/******************************************************************************* +* gstuGetEntryCount +* +* DESCRIPTION: +* Gets the current number of valid entries in the STU table +* +* INPUTS: +* None. +* +* OUTPUTS: +* numEntries - number of STU entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gstuGetEntryCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numEntries +); + +/******************************************************************************* +* gstuGetEntryFirst +* +* DESCRIPTION: +* Gets first lexicographic entry from the STU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* stuEntry - find the first valid STU entry. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - table is empty. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuGetEntryFirst +( + IN GT_QD_DEV *dev, + OUT GT_STU_ENTRY *stuEntry +); + +/******************************************************************************* +* gstuGetEntryNext +* +* DESCRIPTION: +* Gets next lexicographic STU entry from the specified SID. +* +* INPUTS: +* stuEntry - the SID to start the search. +* +* OUTPUTS: +* stuEntry - next STU entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuGetEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_STU_ENTRY *stuEntry +); + +/******************************************************************************* +* gstuFindSidEntry +* +* DESCRIPTION: +* Find STU entry for a specific SID, it will return the entry, if found, +* along with its associated data +* +* INPUTS: +* stuEntry - contains the SID to searche for +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* stuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no such entry. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuFindSidEntry +( + IN GT_QD_DEV *dev, + INOUT GT_STU_ENTRY *stuEntry, + OUT GT_BOOL *found +); + +/******************************************************************************* +* gstuAddEntry +* +* DESCRIPTION: +* Creates or update the entry in STU table based on user input. +* +* INPUTS: +* stuEntry - stu entry to insert to the STU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gstuAddEntry +( + IN GT_QD_DEV *dev, + IN GT_STU_ENTRY *stuEntry +); + +/******************************************************************************* +* gstuDelEntry +* +* DESCRIPTION: +* Deletes STU entry specified by user. +* +* INPUTS: +* stuEntry - the STU entry to be deleted +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuDelEntry +( + IN GT_QD_DEV *dev, + IN GT_STU_ENTRY *stuEntry +); + + +/* gtCCPVT.c */ + +/******************************************************************************* +* gpvtInitialize +* +* DESCRIPTION: +* This routine initializes the PVT Table to all one's (initial state) +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtInitialize +( + IN GT_QD_DEV *dev +); + +/******************************************************************************* +* gpvtWritePVTData +* +* DESCRIPTION: +* This routine write Cross Chip Port Vlan Data. +* Cross chip Port VLAN Data used as a bit mask to limit where cross chip +* frames can egress (in chip Port VLANs are masked using gvlnSetPortVlanPorts +* API). Cross chip frames are Forward frames that ingress a DSA or Ether +* Type DSA port (see gprtSetFrameMode API). Bit 0 is a mask for port 0, +* bit 1 for port 1, etc. When a port's mask bit is one, frames are allowed +* to egress that port on this device. When a port's mask bit is zero, +* frames are not allowed to egress that port on this device. +* +* The Cross Chip Port VLAN Table is accessed by ingressing frames based +* upon the original source port of the frame using the Forward frame's DSA tag +* fields Src_Dev, Src_Port/Src_Trunk and Src_Is_Trunk. The 1 entry of the 512 +* that is accessed by the frame is: +* If 5 Bit Port (in Global 2, offset 0x1D) = 0: +* If Src_Is_Trunk = 0 Src_Dev[4:0], Src_Port[3:0]119 +* If Src_Is_Trunk = 1 Device Number (global offset 0x1C), Src_Trunk[3:0] +* If 5 Bit Port (in Global 2, offset 0x1D) = 1: +* If Src_Is_Trunk = 0 Src_Dev[3:0], Src_Port[4:0]120 +* If Src_Is_Trunk = 1 Device Number[3:0], Src_Trunk[4:0] +* +* Cross chip port VLANs with Trunks are supported in the table where this +* device's entries would be stored (defined by this device's Device Number). +* This portion of the table is available for Trunk entries because this device's +* port VLAN mappings to ports inside this device are masked by the port's +* VLAN Table (see gvlnSetPortVlanPorts API). +* +* +* INPUTS: +* pvtPointer - pointer to the desired entry of PVT (0 ~ 511) +* pvtData - Cross Chip Port Vlan Data +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtWritePVTData +( + IN GT_QD_DEV *dev, + IN GT_U32 pvtPointer, + IN GT_U32 pvtData +); + +/******************************************************************************* +* gpvtReadPVTData +* +* DESCRIPTION: +* This routine reads Cross Chip Port Vlan Data. +* Cross chip Port VLAN Data used as a bit mask to limit where cross chip +* frames can egress (in chip Port VLANs are masked using gvlnSetPortVlanPorts +* API). Cross chip frames are Forward frames that ingress a DSA or Ether +* Type DSA port (see gprtSetFrameMode API). Bit 0 is a mask for port 0, +* bit 1 for port 1, etc. When a port's mask bit is one, frames are allowed +* to egress that port on this device. When a port's mask bit is zero, +* frames are not allowed to egress that port on this device. +* +* The Cross Chip Port VLAN Table is accessed by ingressing frames based +* upon the original source port of the frame using the Forward frame's DSA tag +* fields Src_Dev, Src_Port/Src_Trunk and Src_Is_Trunk. The 1 entry of the 512 +* that is accessed by the frame is: +* If 5 Bit Port (in Global 2, offset 0x1D) = 0: +* If Src_Is_Trunk = 0 Src_Dev[4:0], Src_Port[3:0]119 +* If Src_Is_Trunk = 1 Device Number (global offset 0x1C), Src_Trunk[3:0] +* If 5 Bit Port (in Global 2, offset 0x1D) = 1: +* If Src_Is_Trunk = 0 Src_Dev[3:0], Src_Port[4:0]120 +* If Src_Is_Trunk = 1 Device Number[3:0], Src_Trunk[4:0] +* +* Cross chip port VLANs with Trunks are supported in the table where this +* device's entries would be stored (defined by this device's Device Number). +* This portion of the table is available for Trunk entries because this device's +* port VLAN mappings to ports inside this device are masked by the port's +* VLAN Table (see gvlnSetPortVlanPorts API). +* +* +* INPUTS: +* pvtPointer - pointer to the desired entry of PVT (0 ~ 511) +* +* OUTPUTS: +* pvtData - Cross Chip Port Vlan Data +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtReadPVTData +( + IN GT_QD_DEV *dev, + IN GT_U32 pvtPointer, + OUT GT_U32 *pvtData +); + + +/* gtEvents.c */ + +/******************************************************************************* +* geventGetDevIntStatus +* +* DESCRIPTION: +* Check to see which device interrupts (WatchDog, JamLimit, Duplex Mismatch, and +* SERDES Link Int) have occurred. +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_DEV_INT_WATCHDOG, +* GT_DEV_INT_JAMLIMIT, +* GT_DEV_INT_DUPLEX_MISMATCH, +* GT_DEV_INT_SERDES_LINK +* port - logical port where GT_DEV_INT_DUPLEX_MISMATCH occurred. +* valid only if GT_DEV_INT_DUPLEX_MISMATCH is set in intType. +* linkInt - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt is +* asserted. It's in vector format, Bit 10 is for port 10, +* Bit 9 is for port 9, etc. +* valid only if GT_DEV_INT_SERDES_LINK bit is set in intType. +* These bits are only valid of the port that is in 1000Base-X mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetDevIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_DEV_INT_STATUS *devIntStatus +); + +/******************************************************************************* +* geventSetAgeOutIntEn +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Out Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetAgeOutIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* geventGetAgeOutIntEn +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_TRUE, if Age Out Interrupt is enabled +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetAgeOutIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* geventSetOverLimitInt +* +* DESCRIPTION: +* This routine enables/disables Over Limit Interrupt for a port. +* If it's enabled, an ATU Miss violation will be generated when port auto +* learn reached the limit(refer to gfdbGetPortAtuLimitReached API). +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Over Limit Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetOverLimitInt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* geventGetOverLimitInt +* +* DESCRIPTION: +* This routine enables/disables Over Limit Interrupt for a port. +* If it's enabled, an ATU Miss violation will be generated when port auto +* learn reached the limit(refer to gfdbSetPortAtuLearnLimit API). +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_TRUE to enable Over Limit Interrupt, +* GT_FALUSE to disable +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetOverLimitInt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* geventGetPortAtuLimitReached +* +* DESCRIPTION: +* This routine checks if learn limit has been reached. +* When it reached, the port can no longer auto learn any more MAC addresses +* because the address learn limit set on this port has been reached. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* limit - GT_TRUE, if limit has been reached +* GT_FALSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* +*******************************************************************************/ +GT_STATUS geventGetPortAtuLimitReached +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL *limit +); + +/******************************************************************************* +* eventSetDevInt +* +* DESCRIPTION: +* Device Interrupt. +* The following device interrupts are supported: +* GT_DEV_INT_WATCHDOG - +* WatchDog event interrupt (WatchDog event can be configured with +* gwdSetEvent API) +* GT_DEV_INT_JAMLIMIT - +* any of the ports detect an Ingress Jam Limit violation +* (see gprtSetPauseLimitIn API) +* GT_DEV_INT_DUPLEX_MISMATCH - +* any of the ports detect a duplex mismatch (i.e., the local port is +* in half duplex mode while the link partner is in full duplex mode) +* GT_DEV_INT_SERDES_LINK - +* SERDES link chage interrupt. +* An interrupt occurs when a SERDES port changes link status +* (link up or link down) +* +* If any of the above events is enabled, GT_DEVICE_INT interrupt will +* be asserted by the enabled event when GT_DEV_INT is enabled with +* eventSetActive API. +* +* INPUTS: +* devInt - GT_DEV_INT +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS eventSetDevInt +( + IN GT_QD_DEV *dev, + IN GT_DEV_EVENT *devInt +); + +/******************************************************************************* +* gwdSetEvent +* +* DESCRIPTION: +* Watch Dog Event. +* The following Watch Dog events are supported: +* GT_WD_QC - Queue Controller Watch Dog enable. +* When enabled, the QC's watch dog circuit checks for link +* list errors and any errors found in the QC. +* GT_WD_EGRESS - Egress Watch Dog enable. +* When enabled, each port's egress circuit checks for problems +* between the port and the Queue Controller. +* GT_WD_FORCE - Force a Watch Dog event. +* +* If any of the above events is enabled, GT_DEVICE_INT interrupt will +* be asserted by the enabled WatchDog event when GT_DEV_INT_WATCHDOG is +* enabled with eventSetDevActive API and GT_DEV_INT is enabled with +* eventSetActive API. +* +* INPUTS: +* wdEvent - Watch Dog Events +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetEvent +( + IN GT_QD_DEV *dev, + IN GT_U32 wdEvent +); + +/******************************************************************************* +* gwdSetSWResetOnWD +* +* DESCRIPTION: +* SWReset on Watch Dog Event. +* When this feature is enabled, any enabled watch dog event (gwdSetEvent API) +* will automatically reset the switch core's datapath just as if gsysSwReset +* API is called. +* +* The Watch Dog History (gwdGetHistory API) won't be cleared by this +* automatic SWReset. This allows the user to know if any watch dog event +* ever occurred even if the swich is configured to automatically recover +* from a watch dog. +* +* When this feature is disabled, enabled watch dog events will not cause a +* SWReset. +* +* INPUTS: +* en - GT_TRUE to enable SWReset on WD +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetSWResetOnWD +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gwdGetSWResetOnWD +* +* DESCRIPTION: +* SWReset on Watch Dog Event. +* When this feature is enabled, any enabled watch dog event (gwdSetEvent API) +* will automatically reset the switch core's datapath just as if gsysSwReset +* API is called. +* +* The Watch Dog History (gwdGetHistory API) won't be cleared by this +* automatic SWReset. This allows the user to know if any watch dog event +* ever occurred even if the swich is configured to automatically recover +* from a watch dog. +* +* When this feature is disabled, enabled watch dog events will not cause a +* SWReset. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE, if SWReset on WD is enabled +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetSWResetOnWD +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gwdGetHistory +* +* DESCRIPTION: +* This routine retrieves Watch Dog history. They are +* +* wdEvent - +* When it's set to GT_TRUE, some enabled Watch Dog event occurred. +* The following events are possible: +* QC WatchDog Event (GT_WD_QC) +* Egress WatchDog Event (GT_WD_EGRESS) +* Forced WatchDog Event (GT_WD_FORCE) +* egressEvent - +* If any port's egress logic detects an egress watch dog issue, +* this field is set to GT_TRUE, regardless of the enabling GT_WD_EGRESS +* event. +* +* INPUTS: +* None. +* +* OUTPUTS: +* history - GT_WD_EVENT_HISTORY structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetHistory +( + IN GT_QD_DEV *dev, + OUT GT_WD_EVENT_HISTORY *history +); + + +/* gtPIRL2.c */ + +/******************************************************************************* +* gpirl2WriteResource +* +* DESCRIPTION: +* This routine writes resource bucket parameters to the given resource +* of the port. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* pirlData - PIRL resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2WriteResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + IN GT_PIRL2_DATA *pirlData +); + +/******************************************************************************* +* gpirl2ReadResource +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2ReadResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + OUT GT_PIRL2_DATA *pirlData +); + +/******************************************************************************* +* gpirl2DisableResource +* +* DESCRIPTION: +* This routine disables Ingress Rate Limiting for the given bucket. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2DisableResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes +); + + +/* gtPolicy.c */ + +/******************************************************************************* +* gprtSetPolicy +* +* DESCRIPTION: +* This routine sets the Policy for ports. +* Supported Policies are defined as GT_FRAME_POLICY as follows: +* FRAME_POLICY_NONE - normal frame switching +* FRAME_POLICY_MIRROR - mirror (copy) frame to MirrorDest port +* FRAME_POLICY_TRAP - trap(re-direct) frame to the CPUDest port +* FRAME_POLICY_DISCARD - discard(filter) the frame +* Supported Policy types are defined as GT_POLICY_TYPE: +* POLICY_TYPE_DA - DA Policy Mapping +* DA Policy Mapping occurs when the DA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_SA - SA Policy Mapping +* SA Policy Mapping occurs when the SA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_VTU - VTU Policy Mapping +* VTU Policy Mapping occurs when the VID of a frame is contained in +* the VTU database with the VidPolicy is enabled. +* POLICY_TYPE_ETYPE - EtherType Policy Mapping +* EType Policy Mapping occurs when the EtherType of a frame matches +* the PortEType (see gprtSetPortEType API) +* POLICY_TYPE_PPPoE - PPPoE Policy Mapping +* PPPoE Policy Mapping occurs when the EtherType of a frame matches 0x8863 +* POLICY_TYPE_VBAS - VBAS Policy Mapping +* VBAS Policy Mapping occurs when the EtherType of a frame matches 0x8200 +* POLICY_TYPE_OPT82 - DHCP Option 82 Policy Mapping +* DHCP Option 82 Policy Mapping occurs when the ingressing frame is an +* IPv4 UDP with a UDP Destination port = 0x0043 or 0x0044, or an +* IPv6 UDP with a UDP Destination port = 0x0223 or 0x0222 +* POLICY_TYPE_UDP - UDP Policy Mapping +* UDP Policy Mapping occurs when the ingressing frame is +* a Broadcast IPv4 UDP or a Multicast IPv6 UDP. +* +* INPUTS: +* port - logical port number. +* type - policy type (GT_POLICY_TYPE) +* policy - policy (GT_FRAME_POLICY) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_POLICY_TYPE type, + IN GT_FRAME_POLICY policy +); + +/******************************************************************************* +* gprtGetPolicy +* +* DESCRIPTION: +* This routine gets the Policy of the given policy type. +* Supported Policies are defined as GT_FRAME_POLICY as follows: +* FRAME_POLICY_NONE - normal frame switching +* FRAME_POLICY_MIRROR - mirror (copy) frame to MirrorDest port +* FRAME_POLICY_TRAP - trap(re-direct) frame to the CPUDest port +* FRAME_POLICY_DISCARD - discard(filter) the frame +* Supported Policy types are defined as GT_POLICY_TYPE: +* POLICY_TYPE_DA - DA Policy Mapping +* DA Policy Mapping occurs when the DA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_SA - SA Policy Mapping +* SA Policy Mapping occurs when the SA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_VTU - VTU Policy Mapping +* VTU Policy Mapping occurs when the VID of a frame is contained in +* the VTU database with the VidPolicy is enabled. +* POLICY_TYPE_ETYPE - EtherType Policy Mapping +* EType Policy Mapping occurs when the EtherType of a frame matches +* the PortEType (see gprtSetPortEType API) +* POLICY_TYPE_PPPoE - PPPoE Policy Mapping +* PPPoE Policy Mapping occurs when the EtherType of a frame matches 0x8863 +* POLICY_TYPE_VBAS - VBAS Policy Mapping +* VBAS Policy Mapping occurs when the EtherType of a frame matches 0x8200 +* POLICY_TYPE_OPT82 - DHCP Option 82 Policy Mapping +* DHCP Option 82 Policy Mapping occurs when the ingressing frame is an +* IPv4 UDP with a UDP Destination port = 0x0043 or 0x0044, or an +* IPv6 UDP with a UDP Destination port = 0x0223 or 0x0222 +* POLICY_TYPE_UDP - UDP Policy Mapping +* UDP Policy Mapping occurs when the ingressing frame is +* a Broadcast IPv4 UDP or a Multicast IPv6 UDP. +* +* INPUTS: +* port - logical port number. +* type - policy type (GT_POLICY_TYPE) +* +* OUTPUTS: +* policy - policy (GT_FRAME_POLICY) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_POLICY_TYPE type, + OUT GT_FRAME_POLICY *policy +); + + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtSetPauseLimitOut +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be transmitted +* from this port. When full duplex Flow Control is enabled on this port, +* these bits are used to limit the number of Pause refresh frames that can +* be generated from this port to keep this port's link partner from sending +* any data. +* Setting this value to 0 will allow continuous Pause frame refreshes to +* egress this port as long as this port remains congested. +* Setting this value to 1 will allow 1 Pause frame to egress from this port +* for each congestion situation. +* Setting this value to 2 will allow 2 Pause frames to egress from this port +* for each congestion situation, etc. +* +* INPUTS: +* port - the logical port number +* limit - the max number of Pause refresh frames for each congestion situation +* ( 0 ~ 0xFF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPauseLimitOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 limit +); + +/******************************************************************************* +* gprtGetPauseLimitOut +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be transmitted +* from this port. When full duplex Flow Control is enabled on this port, +* these bits are used to limit the number of Pause refresh frames that can +* be generated from this port to keep this port's link partner from sending +* any data. +* Setting this value to 0 will allow continuous Pause frame refreshes to +* egress this port as long as this port remains congested. +* Setting this value to 1 will allow 1 Pause frame to egress from this port +* for each congestion situation. +* Setting this value to 2 will allow 2 Pause frames to egress from this port +* for each congestion situation, etc. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* limit - the max number of Pause refresh frames for each congestion situation +* ( 0 ~ 0xFF) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPauseLimitOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *limit +); + +/******************************************************************************* +* gprtSetPauseLimitIn +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be received +* on this port. When a port has flow Control enabled, this value can be +* used to limit how long this port can be Paused off to prevent a port stall +* through jamming. +* When this value is in the range of 0x01 to 0xFF, and a frame is ready to +* be transmitted out this port, but it cannot be transmitted due to the port +* being jammed, this limit mechanism starts. The limit mechanism starts +* counting new Pause refresh frames or counts of 16 consecutive collisions. +* If the counter reaches the value set through this API, the following event +* will occur: +* 1) Port's ForceFC is enabled, +* 2) Port's FCValue is cleared to a zero, and +* 3) Jam Limit Interrupt is asserted. +* This effectively disables Flow Control on the port once the Pause timer +* expires. If a frame gets transmitted out this port before the counter +* reaches this limit, then this limit mechanism counter resets back to zero. +* +* Setting this value to 0 will allow continuous jamming to be received on +* this port without the Port's ForceFC and FCValue getting modified. +* +* The modification of Port's ForceFC and FCValue is the only indication that +* the limit was reached on this port. +* +* INPUTS: +* port - the logical port number +* limit - the max number of continuous Pause refresh frames for each trasmition +* ( 0 ~ 0xFF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPauseLimitIn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 limit +); + +/******************************************************************************* +* gprtGetPauseLimitIn +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be received +* on this port. When a port has flow Control enabled, this value can be +* used to limit how long this port can be Paused off to prevent a port stall +* through jamming. +* When this value is in the range of 0x01 to 0xFF, and a frame is ready to +* be transmitted out this port, but it cannot be transmitted due to the port +* being jammed, this limit mechanism starts. The limit mechanism starts +* counting new Pause refresh frames or counts of 16 consecutive collisions. +* If the counter reaches the value set through this API, the following event +* will occur: +* 1) Port's ForceFC is enabled, +* 2) Port's FCValue is cleared to a zero, and +* 3) Jam Limit Interrupt is asserted. +* This effectively disables Flow Control on the port once the Pause timer +* expires. If a frame gets transmitted out this port before the counter +* reaches this limit, then this limit mechanism counter resets back to zero. +* +* Setting this value to 0 will allow continuous jamming to be received on +* this port without the Port's ForceFC and FCValue getting modified. +* +* The modification of Port's ForceFC and FCValue is the only indication that +* the limit was reached on this port. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* limit - the max number of continuous Pause refresh frames for each trasmition +* ( 0 ~ 0xFF) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPauseLimitIn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *limit +); + +/******************************************************************************* +* gprtSetFrameMode +* +* DESCRIPTION: +* Frmae Mode is used to define the expected Ingress and the generated Egress +* tagging frame format for this port as follows: +* GT_FRAME_MODE_NORMAL - +* Normal Network mode uses industry standard IEEE 802.3ac Tagged or +* Untagged frames. Tagged frames use an Ether Type of 0x8100. +* GT_FRAME_MODE_DSA - +* DSA mode uses a Marvell defined tagged frame format for +* Chip-to-Chip and Chip-to-CPU connections. +* GT_FRAME_MODE_PROVIDER - +* Provider mode uses user definable Ether Types per port +* (see gprtSetPortEType/gprtGetPortEType API). +* GT_FRAME_MODE_ETHER_TYPE_DSA - +* Ether Type DSA mode uses standard Marvell DSA Tagged frame info +* flowing a user definable Ether Type. This mode allows the mixture +* of Normal Network frames with DSA Tagged frames and is useful to +* be used on ports that connect to a CPU. +* +* INPUTS: +* port - the logical port number +* mode - GT_FRAME_MODE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is unknown +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetFrameMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_FRAME_MODE mode +); + +/******************************************************************************* +* gprtGetFrameMode +* +* DESCRIPTION: +* Frmae Mode is used to define the expected Ingress and the generated Egress +* tagging frame format for this port as follows: +* GT_FRAME_MODE_NORMAL - +* Normal Network mode uses industry standard IEEE 802.3ac Tagged or +* Untagged frames. Tagged frames use an Ether Type of 0x8100. +* GT_FRAME_MODE_DSA - +* DSA mode uses a Marvell defined tagged frame format for +* Chip-to-Chip and Chip-to-CPU connections. +* GT_FRAME_MODE_PROVIDER - +* Provider mode uses user definable Ether Types per port +* (see gprtSetPortEType/gprtGetPortEType API). +* GT_FRAME_MODE_ETHER_TYPE_DSA - +* Ether Type DSA mode uses standard Marvell DSA Tagged frame info +* flowing a user definable Ether Type. This mode allows the mixture +* of Normal Network frames with DSA Tagged frames and is useful to +* be used on ports that connect to a CPU. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_FRAME_MODE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetFrameMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_FRAME_MODE *mode +); + +/******************************************************************************* +* gprtSetHoldAt1 +* +* DESCRIPTION: +* Hold Aging ATU Entries at an Entry State value of 1. When this feature +* is set to GT_TRUE, ATU entries associated with this port will age down +* to an Entry State of 0x1, but will not go to 0x0 (0x0 would purge the +* entry) +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to hold aging ATU entry with Entry State of 1, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetHoldAt1 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetHoldAt1 +* +* DESCRIPTION: +* Hold Aging ATU Entries at an Entry State value of 1. When this feature +* is set to GT_TRUE, ATU entries associated with this port will age down +* to an Entry State of 0x1, but will not go to 0x0 (0x0 would purge the +* entry) +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to hold aging ATU entry with Entry State of 1, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetHoldAt1 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetRefreshLocked +* +* DESCRIPTION: +* Auto Refresh known addresses when port is Locked. Already known addresses +* will be auto refreshed when this feature is enabled. When this feature +* is disabled, auto refreshing will not occur on Locked ports. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable Auto Refresh known addresses on locked port +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetRefreshLocked +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +); + +/******************************************************************************* +* gprtGetRefreshLocked +* +* DESCRIPTION: +* Auto Refresh known addresses when port is Locked. Already known addresses +* will be auto refreshed when this feature is enabled. When this feature +* is disabled, auto refreshing will not occur on Locked ports. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable Auto Refresh known addresses on locked port +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetRefreshLocked +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gprtSetPortEType +* +* DESCRIPTION: +* This routine sets the port's special Ether Type. This Ether Type is used +* for Policy (see gprtSetPolicy API) and FrameMode (see gprtSetFrameMode API). +* +* INPUTS: +* port - the logical port number +* etype - port's special ether type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPortEType +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ETYPE etype +); + +/******************************************************************************* +* gprtGetPortEType +* +* DESCRIPTION: +* This routine retrieves the port's special Ether Type. This Ether Type is used +* for Policy (see gprtSetPolicy API) and FrameMode (see gprtSetFrameMode API). +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* etype - port's special ether type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPortEType +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ETYPE *etype +); + + +/* gtPortRateCtr.c */ + +/******************************************************************************* +* grcSetFrameOverhead +* +* DESCRIPTION: +* Egress rate frame overhead adjustment. +* This field is used to adjust the number of bytes that need to be added to a +* frame's IFG on a per frame basis. +* +* The egress rate limiter multiplies the value programmed in this field by four +* for computing the frame byte offset adjustment value (i.e., the amount the +* IPG is increased for every frame). This adjustment, if enabled, is made to +* every egressing frame's IPG and it is made in addition to any other IPG +* adjustments due to other Egress Rate Control settings. +* +* The egress overhead adjustment can add the following number of byte times +* to each frame's IPG: 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, +* 56 and 60. +* +* Example: +* If FrameOverhead = 11, the egress rate limiter would increase the IPG +* between every frame by an additional 44 bytes. +* +* Note: When the Count Mode (port offset 0x0A) is in Frame based egress rate +* shaping mode, these Frame Overhead bits must be 0x0. +* +* INPUTS: +* port - logical port number. +* overhead - Frame overhead (0 ~ 15) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcSetFrameOverhead +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_32 overhead +); + +/******************************************************************************* +* grcGetFrameOverhead +* +* DESCRIPTION: +* Egress rate frame overhead adjustment. +* This field is used to adjust the number of bytes that need to be added to a +* frame's IFG on a per frame basis. +* +* The egress rate limiter multiplies the value programmed in this field by four +* for computing the frame byte offset adjustment value (i.e., the amount the +* IPG is increased for every frame). This adjustment, if enabled, is made to +* every egressing frame's IPG and it is made in addition to any other IPG +* adjustments due to other Egress Rate Control settings. +* +* The egress overhead adjustment can add the following number of byte times +* to each frame's IPG: 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, +* 56 and 60. +* +* Example: +* If FrameOverhead = 11, the egress rate limiter would increase the IPG +* between every frame by an additional 44 bytes. +* +* Note: When the Count Mode (port offset 0x0A) is in Frame based egress rate +* shaping mode, these Frame Overhead bits must be 0x0. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* overhead - Frame overhead (0 ~ 15) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +*******************************************************************************/ +GT_STATUS grcGetFrameOverhead +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_32 *overhead +); + + +/* gtPortStatus.c */ + +/******************************************************************************* +* gprtGetBufHigh +* +* DESCRIPTION: +* Output from QC telling the MAC that it should perform Flow Control. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* bufHigh - GT_TRUE, if Flow control required +* GT_FALSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetBufHigh +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *bufHigh +); + +/******************************************************************************* +* gprtGetFcEn +* +* DESCRIPTION: +* Input into the QC telling it that Flow Control is enabled on this port. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* fcEn - GT_TRUE, if Flow control is enabled +* GT_FALSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetFcEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *fcEn +); + +/******************************************************************************* +* gprtGetRsvSize +* +* DESCRIPTION: +* This routine gets Ingress reserved queue size counter. +* This counter reflects the current number of reserved ingress buffers +* assigned to this port. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* count - reserved ingress queue size counter value +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetRsvSize +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *count +); + + +/* gtPriTable.c */ + +/******************************************************************************* +* gsysSetQPriOverrideTable +* +* DESCRIPTION: +* Queue Priority Override. +* When a frame enters a port, its type is determined and the type is used +* to access the Queue Priority Table. If the type's qPriEn (in GT_QPRI_TBL_ENTRY +* structure) is enabled, then the frame's Queue Priority will be overridden +* with the value written in qPriority (in GT_QPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* entry - Q Priority Override Table entry (GT_QPRI_TBL_ENTRY) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetQPriOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + IN GT_QPRI_TBL_ENTRY *entry +); + +/******************************************************************************* +* gsysGetQPriOverrideTable +* +* DESCRIPTION: +* Queue Priority Override. +* When a frame enters a port, its type is determined and the type is used +* to access the Queue Priority Table. If the type's qPriEn (in GT_QPRI_TBL_ENTRY +* structure) is enabled, then the frame's Queue Priority will be overridden +* with the value written in qPriority (in GT_QPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* +* OUTPUTS: +* entry - Q Priority Override Table entry (GT_QPRI_TBL_ENTRY) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetQPriOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + OUT GT_QPRI_TBL_ENTRY *entry +); + + +/* gtSysCtrl.c */ + +/******************************************************************************* +* gsysSetCPUDest +* +* DESCRIPTION: +* This routine sets CPU Destination Port. CPU Destination port indicates the +* port number on this device where the CPU is connected (either directly or +* indirectly through another Marvell switch device). +* +* Many modes of frame processing need to know where the CPU is located. +* These modes are: +* 1. When IGMP/MLD frame is received and Snooping is enabled +* 2. When the port is configured as a DSA port and it receives a To_CPU frame +* 3. When a Rsvd2CPU frame enters the port +* 4. When the port's SA Filtering mode is Drop to CPU +* 5. When any of the port's Policy Options trap the frame to the CPU +* 6. When the ingressing frame is an ARP and ARP mirroring is enabled in the +* device +* +* In all cases, except for ARP, the frames that meet the enabled criteria +* are mapped to the CPU Destination port, overriding where the frame would +* normally go. In the case of ARP, the frame will be mapped normally and it +* will also get copied to this port. +* Frames that filtered or discarded will not be mapped to the CPU Destination +* port with the exception of the Rsvd2CPU and DSA Tag cases. +* +* If CPUDest = 0xF, the remapped frames will be discarded, no ARP mirroring +* will occur and ingressing To_CPU frames will be discarded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetCPUDest +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetCPUDest +* +* DESCRIPTION: +* This routine gets CPU Destination Port. CPU Destination port indicates the +* port number on this device where the CPU is connected (either directly or +* indirectly through another Marvell switch device). +* +* Many modes of frame processing need to know where the CPU is located. +* These modes are: +* 1. When IGMP/MLD frame is received and Snooping is enabled +* 2. When the port is configured as a DSA port and it receives a To_CPU frame +* 3. When a Rsvd2CPU frame enters the port +* 4. When the port's SA Filtering mode is Drop to CPU +* 5. When any of the port's Policy Options trap the frame to the CPU +* 6. When the ingressing frame is an ARP and ARP mirroring is enabled in the +* device +* +* In all cases, except for ARP, the frames that meet the enabled criteria +* are mapped to the CPU Destination port, overriding where the frame would +* normally go. In the case of ARP, the frame will be mapped normally and it +* will also get copied to this port. +* Frames that filtered or discarded will not be mapped to the CPU Destination +* port with the exception of the Rsvd2CPU and DSA Tag cases. +* +* If CPUDest = 0xF, the remapped frames will be discarded, no ARP mirroring +* will occur and ingressing To_CPU frames will be discarded. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetCPUDest +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetMirrorDest +* +* DESCRIPTION: +* This routine sets Mirror Destination Port. Frames that ingress a port +* that trigger a policy mirror are mapped (copied) to this port as long as +* the frame is not filtered or discarded. +* The Mirror Destination port should point to the port that directs these +* frames to the CPU that will process these frames. This target port should +* be a DSA Tag port so the frames will egress with a To_CPU DSA Tag with a +* CPU Code of Policy Mirror. +* To_CPU DSA Tag frames with a CPU Code of Policy Mirror that ingress a DSA +* Tag port will be sent to the port number defined in MirrorDest. +* +* If MirrorDest = 0xF, Policy Mirroring is disabled and ingressing To_CPU +* Policy Mirror frames will be discarded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetMirrorDest +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetMirrorDest +* +* DESCRIPTION: +* This routine gets Mirror Destination Port. Frames that ingress a port +* that trigger a policy mirror are mapped (copied) to this port as long as +* the frame is not filtered or discarded. +* The Mirror Destination port should point to the port that directs these +* frames to the CPU that will process these frames. This target port should +* be a DSA Tag port so the frames will egress with a To_CPU DSA Tag with a +* CPU Code of Policy Mirror. +* To_CPU DSA Tag frames with a CPU Code of Policy Mirror that ingress a DSA +* Tag port will be sent to the port number defined in MirrorDest. +* +* If MirrorDest = 0xF, Policy Mirroring is disabled and ingressing To_CPU +* Policy Mirror frames will be discarded. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - the logical port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetMirrorDest +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetRMPort +* +* DESCRIPTION: +* Remote Management feature is enabled only on one port. Since not all ports +* can be enabled for Remote Management feature, please refer to the device +* datasheet for detailed information. +* For example, 88E6097 device allows logical port 9 or 10, and 88E6047 +* device allows logical port 4 and 5. +* +* INPUTS: +* port - Remote Management Port +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unallowable port +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRMPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +); + +/******************************************************************************* +* gsysGetRMPort +* +* DESCRIPTION: +* Remote Management feature is enabled only on one port. Since not all ports +* can be enabled for Remote Management feature, please refer to the device +* datasheet for detailed information. +* For example, 88E6097 device allows logical port 9 or 10, and 88E6047 +* device allows logical port 4 and 5. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - Remote Management Port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRMPort +( + IN GT_QD_DEV *dev, + OUT GT_LPORT *port +); + +/******************************************************************************* +* gsysSetRMDACheck +* +* DESCRIPTION: +* Check the DA on Remote Management frames. +* When DA Check is enabled, the DA of Remote Management frames must be +* contained in this device's address database (ATU) as a Static entry +* (either unicast or multicast). If the DA of the frame is not contained +* in this device's address database, the frame will be not be processed as +* a Frame-to-Regter frame. +* When DA Check is disabled, the DA of Remote Management frames is not +* validated before processing the frame. +* +* INPUTS: +* en - GT_TRUE to enable DA Check, +* GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRMDACheck +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRMDACheck +* +* DESCRIPTION: +* Check the DA on Remote Management frames. +* When DA Check is enabled, the DA of Remote Management frames must be +* contained in this device's address database (ATU) as a Static entry +* (either unicast or multicast). If the DA of the frame is not contained +* in this device's address database, the frame will be not be processed as +* a Frame-to-Regter frame. +* When DA Check is disabled, the DA of Remote Management frames is not +* validated before processing the frame. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if DA Check is enabled, +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRMDACheck +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetRMEnable +* +* DESCRIPTION: +* Enable or disable Remote Management feature. This feature can be enabled +* only on one port (see gsysSetRMPort API). +* +* INPUTS: +* en - GT_TRUE to enable Remote Management feature, +* GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRMEnable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRMEnable +* +* DESCRIPTION: +* Enable or disable Remote Management feature. This feature can be enabled +* only on one port (see gsysSetRMPort API). +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if Remote Management feature is enabled, +* GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRMEnable +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetRsvd2CpuEnables2X +* +* DESCRIPTION: +* Reserved DA Enables for the form of 01:80:C2:00:00:2x. +* When the Rsvd2Cpu(gsysSetRsvd2Cpu) is set to a one, the 16 reserved +* multicast DA addresses, whose bit in this register are also set to a one, +* are treadted as MGMT frames. All the reserved DA's take the form +* 01:80:C2:00:00:2x. When x = 0x0, bit 0 of this register is tested. +* When x = 0x2, bit 2 of this field is tested and so on. +* If the tested bit in this register is cleared to a zero, the frame will +* be treated as a normal (non-MGMT) frame. +* +* INPUTS: +* enBits - bit vector of enabled Reserved Multicast. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRsvd2CpuEnables2X +( + IN GT_QD_DEV *dev, + IN GT_U16 enBits +); + +/******************************************************************************* +* gsysGetRsvd2CpuEnables2X +* +* DESCRIPTION: +* Reserved DA Enables for the form of 01:80:C2:00:00:2x. +* When the Rsvd2Cpu(gsysSetRsvd2Cpu) is set to a one, the 16 reserved +* multicast DA addresses, whose bit in this register are also set to a one, +* are treadted as MGMT frames. All the reserved DA's take the form +* 01:80:C2:00:00:2x. When x = 0x0, bit 0 of this register is tested. +* When x = 0x2, bit 2 of this field is tested and so on. +* If the tested bit in this register is cleared to a zero, the frame will +* be treated as a normal (non-MGMT) frame. +* +* INPUTS: +* None. +* +* OUTPUTS: +* enBits - bit vector of enabled Reserved Multicast. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRsvd2CpuEnables2X +( + IN GT_QD_DEV *dev, + OUT GT_U16 *enBits +); + +/******************************************************************************* +* gsysSetFloodBC +* +* DESCRIPTION: +* Flood Broadcast. +* When Flood Broadcast is enabled, frames with the Broadcast destination +* address will flood out all the ports regardless of the setting of the +* port's Egress Floods mode (see gprtSetEgressFlood API). VLAN rules and +* other switch policy still applies to these Broadcast frames. +* When this feature is disabled, frames with the Broadcast destination +* address are considered Multicast frames and will be affected by port's +* Egress Floods mode. +* +* INPUTS: +* en - GT_TRUE to enable Flood Broadcast, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetFloodBC +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetFloodBC +* +* DESCRIPTION: +* Flood Broadcast. +* When Flood Broadcast is enabled, frames with the Broadcast destination +* address will flood out all the ports regardless of the setting of the +* port's Egress Floods mode (see gprtSetEgressFlood API). VLAN rules and +* other switch policy still applies to these Broadcast frames. +* When this feature is disabled, frames with the Broadcast destination +* address are considered Multicast frames and will be affected by port's +* Egress Floods mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if Flood Broadcast is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetFloodBC +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetRemove1PTag +* +* DESCRIPTION: +* Remove One Provider Tag. +* When this feature is enabled and a port is configured as a Provider Port +* (see gprtSetFrameMode API), recursive Provider Tag stripping will NOT be +* performed. Only the first Provider Tag found on the frame will be +* extracted and removed. Its extracted data will be used for switching. +* When it's disabled and a port is configured as a Provider Port, recursive +* Provider Tag stripping will be performed. The first Provider Tag's data +* will be extracted and used for switching, and then all subsequent Provider +* Tags found in the frame will also be removed. This will only occur if the +* port's PortEType (see gprtSetPortEType API) is not 0x8100. +* +* INPUTS: +* en - GT_TRUE to enable Remove One Provider Tag, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRemove1PTag +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetRemove1PTag +* +* DESCRIPTION: +* Remove One Provider Tag. +* When this feature is enabled and a port is configured as a Provider Port +* (see gprtSetFrameMode API), recursive Provider Tag stripping will NOT be +* performed. Only the first Provider Tag found on the frame will be +* extracted and removed. Its extracted data will be used for switching. +* When it's disabled and a port is configured as a Provider Port, recursive +* Provider Tag stripping will be performed. The first Provider Tag's data +* will be extracted and used for switching, and then all subsequent Provider +* Tags found in the frame will also be removed. This will only occur if the +* port's PortEType (see gprtSetPortEType API) is not 0x8100. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if Remove One Provider Tag is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRemove1PTag +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetTagFlowControl +* +* DESCRIPTION: +* Use and generate source port Flow Control status for Cross-Chip Flow +* Control. +* When this feature is enabled, bit 17 of the DSA Tag Forward frames is +* defined to be Src_FC and it is added to these frames when generated and +* it is inspected on these frames when received. The QC will use the Src_FC +* bit on DSA ports instead of the DSA port's Flow Control mode bit for the +* QC Flow Control algorithm. +* When it is disabled, bit 17 of the DSA Tag Forward frames is defined to +* be Reserved and it will be zero on these frames when generated and it +* will not be used on these frames when received (this is a backwards +* compatibility mode). +* +* INPUTS: +* en - GT_TRUE to enable Tag Flow Control, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetTagFlowControl +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetTagFlowControl +* +* DESCRIPTION: +* Use and generate source port Flow Control status for Cross-Chip Flow +* Control. +* When this feature is enabled, bit 17 of the DSA Tag Forward frames is +* defined to be Src_FC and it is added to these frames when generated and +* it is inspected on these frames when received. The QC will use the Src_FC +* bit on DSA ports instead of the DSA port's Flow Control mode bit for the +* QC Flow Control algorithm. +* When it is disabled, bit 17 of the DSA Tag Forward frames is defined to +* be Reserved and it will be zero on these frames when generated and it +* will not be used on these frames when received (this is a backwards +* compatibility mode). +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if Tag Flow Control is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetTagFlowControl +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetAlwaysUseVTU +* +* DESCRIPTION: +* Always use VTU. +* When this feature is enabled, VTU hit data will be used to map frames +* even if 802.1Q is Disabled on the port. +* When it's disabled, data will be ignored when mapping frames on ports +* where 802.1Q is Disabled. +* +* INPUTS: +* en - GT_TRUE to use VTU always, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetAlwaysUseVTU +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetAlwaysUseVTU +* +* DESCRIPTION: +* Always use VTU. +* When this feature is enabled, VTU hit data will be used to map frames +* even if 802.1Q is Disabled on the port. +* When it's disabled, data will be ignored when mapping frames on ports +* where 802.1Q is Disabled. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if VTU is always used, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetAlwaysUseVTU +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetQVlansOnly +* +* DESCRIPTION: +* 802.1Q VLANs Only. +* When this feature is disabled, the egress mapping of the frame is +* limited by the frame's VID (using the MemberTag data found in the VTU) +* together with the port based VLANs (using the source port's PortVLANTable, +* gvlnSetPortVlanPorts API). The two methods are always used together in +* this mode. +* When this feature is enabled, the egress mapping of the frame is limitied +* by the frame's VID only, if the VID was found in the VTU. If the frame's +* VID was not found in the VTU the egress mapping of the frame is limited +* by the source port's PortVLANTable only. The two methods are never +* used together in this mode. +* +* INPUTS: +* en - GT_TRUE to use 802.1Q Vlan Only feature, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetQVlansOnly +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetQVlansOnly +* +* DESCRIPTION: +* 802.1Q VLANs Only. +* When this feature is disabled, the egress mapping of the frame is +* limited by the frame's VID (using the MemberTag data found in the VTU) +* together with the port based VLANs (using the source port's PortVLANTable, +* gvlnSetPortVlanPorts API). The two methods are always used together in +* this mode. +* When this feature is enabled, the egress mapping of the frame is limitied +* by the frame's VID only, if the VID was found in the VTU. If the frame's +* VID was not found in the VTU the egress mapping of the frame is limited +* by the source port's PortVLANTable only. The two methods are never +* used together in this mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if 802.1Q Vlan Only feature is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetQVlansOnly +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSet5BitPort +* +* DESCRIPTION: +* Use 5 bits for Port data in the Port VLAN Table (PVT). +* When this feature is enabled, the 9 bits used to access the PVT memory is: +* Addr[8:5] = Source Device[3:0] or Device Number[3:0] +* Addr[4:0] = Source Port/Trunk[4:0] +* When it's disabled, the 9 bits used to access the PVT memory is: +* Addr[8:4] = Source Device[4:0] or Device Number[4:0] +* Addr[3:0] = Source Port/Trunk[3:0] +* +* INPUTS: +* en - GT_TRUE to use 5 bit as a Source port in PVT, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSet5BitPort +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGet5BitPort +* +* DESCRIPTION: +* Use 5 bits for Port data in the Port VLAN Table (PVT). +* When this feature is enabled, the 9 bits used to access the PVT memory is: +* Addr[8:5] = Source Device[3:0] or Device Number[3:0] +* Addr[4:0] = Source Port/Trunk[4:0] +* When it's disabled, the 9 bits used to access the PVT memory is: +* Addr[8:4] = Source Device[4:0] or Device Number[4:0] +* Addr[3:0] = Source Port/Trunk[3:0] +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if 5 bit is used as a Source Port in PVT, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGet5BitPort +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gsysSetSDETPolarity +* +* DESCRIPTION: +* SDET (Signal Detect) Polarity select bits for each port. +* Bit 10 is for Port 10, bit 9 is for Port 9, etc. SDET is used to help +* determine link on fiber ports. This bit affects the active level of a +* port's SDET pins as follows: +* 0 = SDET is active low. A low level on the port's SDET pin is +* required for link to occur. +* 1 = SDET is active high. A high level on the port’s SDET pin is +* required for link to occur. +* SDET is used when the port is configured as a fiber port. In all other +* port modes the SDET pins are ignored and these bits have no effect. +* +* INPUTS: +* sdetVec - SDET Polarity for each port in Vector format +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if sdetVec is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetSDETPolarity +( + IN GT_QD_DEV *dev, + IN GT_U32 sdetVec +); + +/******************************************************************************* +* gsysSetSDETPolarity +* +* DESCRIPTION: +* SDET (Signal Detect) Polarity select bits for each port. +* Bit 10 is for Port 10, bit 9 is for Port 9, etc. SDET is used to help +* determine link on fiber ports. This bit affects the active level of a +* port's SDET pins as follows: +* 0 = SDET is active low. A low level on the port's SDET pin is +* required for link to occur. +* 1 = SDET is active high. A high level on the port’s SDET pin is +* required for link to occur. +* SDET is used when the port is configured as a fiber port. In all other +* port modes the SDET pins are ignored and these bits have no effect. +* +* INPUTS: +* None. +* +* OUTPUTS: +* sdetVec - SDET Polarity for each port in Vector format +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetSDETPolarity +( + IN GT_QD_DEV *dev, + OUT GT_U32 *sdetVec +); + + +/* gtBrgVlan.c for 2.6 release */ + +/******************************************************************************* +* gvlnSetNoEgrPolicy +* +* DESCRIPTION: +* No Egress Policy. When this bit is set to a one Egress 802.1Q Secure and +* Check discards are not performed. This mode allowsa non-802.1Q enabled +* port to send a frame to an 802.1Q enabled port that is configured in the +* Secure or Check 802.1Q mode. In this situation the frames will egress +* even if the VID assigned to the frame is not found in the VTU. +* +* INPUTS: +* mode - no egress policy mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gvlnSetNoEgrPolicy +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +); + + +/******************************************************************************* +* gvlnGetNoEgrPolicy +* +* DESCRIPTION: +* No Egress Policy. When this bit is set to a one Egress 802.1Q Secure and +* Check discards are not performed. This mode allowsa non-802.1Q enabled +* port to send a frame to an 802.1Q enabled port that is configured in the +* Secure or Check 802.1Q mode. In this situation the frames will egress +* even if the VID assigned to the frame is not found in the VTU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - no egress policy mode +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gvlnGetNoEgrPolicy +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gwdSetRMUTimeOut +* +* DESCRIPTION: +* Remote Management Timeout. When this bit is set to a one the Remote +* Management Unit(RMU) will timeout on Wait on Bit commands. If the bit that +* is being tested has not gone to the specified value after 1 sec. has elapsed +* the Wait on Bit command will be terminated and the Response frame will be +* sent without any further processing. +* +* When this bit is cleared to a zero the Wait on Bit command will wait +* until the bit that is being tested has changed to the specified value. +* +* INPUTS: +* en - GT_TRUE to enable RMU Timeout +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetRMUTimeOut +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gwdGetRMUTimeOut +* +* DESCRIPTION: +* Remote Management Timeout. When this bit is set to a one the Remote +* Management Unit(RMU) will timeout on Wait on Bit commands. If the bit that +* is being tested has not gone to the specified value after 1 sec. has elapsed +* the Wait on Bit command will be terminated and the Response frame will be +* sent without any further processing. +* +* When this bit is cleared to a zero the Wait on Bit command will wait +* until the bit that is being tested has changed to the specified value. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to enable RMU Timeout +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetRMUTimeOut +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gwdGetEgressWDEvent +* +* DESCRIPTION: +* If any port's egress logic detects an egress watch dog issue, this bit +* will be set to a one, regardless of the setting of the GT_WD_EGRESS in +* gwdSetEvent function. +* +* INPUTS: +* None. +* +* OUTPUTS: +* event - GT_TRUE, if egress logic has detected any egress watch dog issue +* GT_FALUSE, otherwise +* +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetEgressWDEvent +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *event +); + + +/******************************************************************************* +* gsysSetQoSWeight +* +* DESCRIPTION: +* Programmable Round Robin Weights. +* Each port has 4 output Queues. Queue 3 has the highest priority and +* Queue 0 has the lowest priority. When a scheduling mode of port is +* configured as Weighted Round Robin queuing mode, the access sequece of the +* Queue is 3,2,3,1,3,2,3,0,3,2,3,1,3,2,3 by default. +* This sequence can be configured with this API. +* +* INPUTS: +* weight - access sequence of the queue +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetQoSWeight +( + IN GT_QD_DEV *dev, + IN GT_QoS_WEIGHT *weight +); + +/******************************************************************************* +* gsysGetQoSWeight +* +* DESCRIPTION: +* Programmable Round Robin Weights. +* Each port has 4 output Queues. Queue 3 has the highest priority and +* Queue 0 has the lowest priority. When a scheduling mode of port is +* configured as Weighted Round Robin queuing mode, the access sequece of the +* Queue is 3,2,3,1,3,2,3,0,3,2,3,1,3,2,3 by default. +* This routine retrieves the access sequence of the Queue. +* +* INPUTS: +* None. +* +* OUTPUTS: +* weight - access sequence of the queue +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetQoSWeight +( + IN GT_QD_DEV *dev, + OUT GT_QoS_WEIGHT *weight +); + + +/* + * gtPortCtrl.c +*/ + +/******************************************************************************* +* gsysSetJumboMode +* +* DESCRIPTION: +* This routine Set the max frame size allowed to be received and transmitted +* from or to a given port. +* +* INPUTS: +* port - the logical port number +* mode - GT_JUMBO_MODE (1522, 2048, or 10240) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gsysSetJumboMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_JUMBO_MODE mode +); + +/******************************************************************************* +* gsysGetJumboMode +* +* DESCRIPTION: +* This routine gets the max frame size allowed to be received and transmitted +* from or to a given port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_JUMBO_MODE (1522, 2048, or 10240) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gsysGetJumboMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_JUMBO_MODE *mode +); + +/* + * gtPhyCtrl.c +*/ +/******************************************************************************* +* gprtGetEnergyDetect +* +* DESCRIPTION: +* Energy Detect power down mode enables or disables the PHY to wake up on +* its own by detecting activity on the CAT 5 cable. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* mode - GT_EDETECT_MODE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetEnergyDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EDETECT_MODE *mode +); + +/******************************************************************************* +* gprtSetEnergyDetect +* +* DESCRIPTION: +* Energy Detect power down mode enables or disables the PHY to wake up on +* its own by detecting activity on the CAT 5 cable. +* +* INPUTS: +* port - The logical port number +* mode - GT_EDETECT_MODE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtSetEnergyDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EDETECT_MODE mode +); + + +/* + * gtSysCtrl.c +*/ + +/******************************************************************************* +* gsysSetRMUMode +* +* DESCRIPTION: +* Set Rmote Management Unit Mode: disable, enable on port 4 or 5, or enable +* on port 9 or 10. Devices, such as 88E6097, support RMU on port 9 and 10, +* while other devices, such as 88E6165, support RMU on port 4 and 5. So, +* please refer to the device datasheet for detail. +* When RMU is enabled and this device receives a Remote Management Request +* frame directed to this device, the frame will be processed and a Remote +* Management Response frame will be generated and sent out. +* +* Note: enabling RMU has no effect if the Remote Management port is in half +* duplex mode. The port's FrameMode must be DSA or EtherType DSA as well. +* +* INPUTS: +* rmu - GT_RMU structure +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameter +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetRMUMode +( + IN GT_QD_DEV *dev, + IN GT_RMU *rmu +); + +/******************************************************************************* +* gsysGetRMUMode +* +* DESCRIPTION: +* Get Rmote Management Unit Mode: disable, enable on port 4 or 5, or enable +* on port 9 or 10. Devices, such as 88E6097, support RMU on port 9 and 10, +* while other devices, such as 88E6165, support RMU on port 4 and 5. So, +* please refer to the device datasheet for detail. +* When RMU is enabled and this device receives a Remote Management Request +* frame directed to this device, the frame will be processed and a Remote +* Management Response frame will be generated and sent out. +* +* Note: enabling RMU has no effect if the Remote Management port is in half +* duplex mode. The port's FrameMode must be DSA or EtherType DSA as well. +* +* INPUTS: +* None. +* +* OUTPUTS: +* rmu - GT_RMU structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetRMUMode +( + IN GT_QD_DEV *dev, + OUT GT_RMU *rmu +); + +/******************************************************************************* +* gsysPort2Lport +* +* DESCRIPTION: +* This routine converts physical port number to logical port number. +* +* INPUTS: +* port - physical port number +* +* OUTPUTS: +* lport - logical port number +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysPort2Lport +( + IN GT_QD_DEV *dev, + IN GT_U32 port, + OUT GT_LPORT *lport +); + +/******************************************************************************* +* gsysLport2Port +* +* DESCRIPTION: +* This routine converts logical port number to physical port number. +* +* INPUTS: +* lport - logical port number +* +* OUTPUTS: +* port - physical port number +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysLport2Port +( + IN GT_QD_DEV *dev, + IN GT_LPORT lport, + OUT GT_U32 *port +); + +/******************************************************************************* +* gsysPortvec2Lportvec +* +* DESCRIPTION: +* This routine converts physical port vector to logical port vector. +* +* INPUTS: +* portvec - physical port vector +* +* OUTPUTS: +* lportvec - logical port vector +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysPortvec2Lportvec +( + IN GT_QD_DEV *dev, + IN GT_U32 portvec, + OUT GT_U32 *lportvec +); + +/******************************************************************************* +* gsysLportvec2Portvec +* +* DESCRIPTION: +* This routine converts logical port vector to physical port vector. +* +* INPUTS: +* lportvec - logical port vector +* +* OUTPUTS: +* portvec - physical port vector +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysLportvec2Portvec +( + IN GT_QD_DEV *dev, + IN GT_U32 lportvec, + OUT GT_U32 *portvec +); + + +/* + * gtPIRL.c + */ + +/******************************************************************************* +* gpirlSetCurTimeUpInt +* +* DESCRIPTION: +* This function sets the current time update interval. +* Please contact FAE for detailed information. +* +* INPUTS: +* upInt - updata interval (0 ~ 7) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirlSetCurTimeUpInt +( + IN GT_QD_DEV *dev, + IN GT_U32 upInt +); + + +/* + * gtPIRL2.c + */ + +/******************************************************************************* +* gpirl2SetCurTimeUpInt +* +* DESCRIPTION: +* This function sets the current time update interval. +* Please contact FAE for detailed information. +* +* INPUTS: +* upInt - updata interval (0 ~ 7) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirl2SetCurTimeUpInt +( + IN GT_QD_DEV *dev, + IN GT_U32 upInt +); + + +/* + * gtPTP.c + */ + +/******************************************************************************* +* gptpSetConfig +* +* DESCRIPTION: +* This routine writes PTP configuration parameters. +* +* INPUTS: +* ptpData - PTP configuration parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetConfig +( + IN GT_QD_DEV *dev, + IN GT_PTP_CONFIG *ptpData +); + +/******************************************************************************* +* gptpGetConfig +* +* DESCRIPTION: +* This routine reads PTP configuration parameters. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ptpData - PTP configuration parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetConfig +( + IN GT_QD_DEV *dev, + OUT GT_PTP_CONFIG *ptpData +); + +/******************************************************************************* +* gptpSetGlobalConfig +* +* DESCRIPTION: +* This routine writes PTP global configuration parameters. +* +* INPUTS: +* ptpData - PTP global configuration parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetGlobalConfig +( + IN GT_QD_DEV *dev, + IN GT_PTP_GLOBAL_CONFIG *ptpData +); + +/******************************************************************************* +* gptpGetGlobalConfig +* +* DESCRIPTION: +* This routine reads PTP global configuration parameters. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ptpData - PTP global configuration parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetGlobalConfig +( + IN GT_QD_DEV *dev, + OUT GT_PTP_GLOBAL_CONFIG *ptpData +); + +/******************************************************************************* +* gptpSetPortConfig +* +* DESCRIPTION: +* This routine writes PTP port configuration parameters. +* +* INPUTS: +* ptpData - PTP port configuration parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetPortConfig +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PTP_PORT_CONFIG *ptpData +); + +/******************************************************************************* +* gptpGetPortConfig +* +* DESCRIPTION: +* This routine reads PTP configuration parameters for a port. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ptpData - PTP port configuration parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetPortConfig +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PTP_PORT_CONFIG *ptpData +); + +/******************************************************************************* +* gptpSetPTPEn +* +* DESCRIPTION: +* This routine enables or disables PTP. +* +* INPUTS: +* en - GT_TRUE to enable PTP, GT_FALSE to disable PTP +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetPTPEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gptpGetPTPEn +* +* DESCRIPTION: +* This routine checks if PTP is enabled. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetPTPEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gptpSetPortPTPEn +* +* DESCRIPTION: +* This routine enables or disables PTP on a port. +* +* INPUTS: +* en - GT_TRUE to enable PTP, GT_FALSE to disable PTP +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetPortPTPEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + +/******************************************************************************* +* gptpGetPortPTPEn +* +* DESCRIPTION: +* This routine checks if PTP is enabled on a port. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetPortPTPEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gptpGetPTPInt +* +* DESCRIPTION: +* This routine gets PTP interrupt status for each port. +* The PTP Interrupt bit gets set for a given port when an incoming PTP +* frame is time stamped and PTPArrIntEn for that port is set to 0x1. +* Similary PTP Interrupt bit gets set for a given port when an outgoing +* PTP frame is time stamped and PTPDepIntEn for that port is set to 0x1. +* This bit gets cleared upon software reading and clearing the corresponding +* time counter valid bits that are valid for that port. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ptpInt - interrupt status for each port (bit 0 for port 0, bit 1 for port 1, etc.) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetPTPInt +( + IN GT_QD_DEV *dev, + OUT GT_U32 *ptpInt +); + +/******************************************************************************* +* gptpGetPTPGlobalTime +* +* DESCRIPTION: +* This routine gets the global timer value that is running off of the free +* running switch core clock. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ptpTime - PTP global time +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetPTPGlobalTime +( + IN GT_QD_DEV *dev, + OUT GT_U32 *ptpTime +); + +/******************************************************************************* +* gptpGetTimeStamped +* +* DESCRIPTION: +* This routine retrieves the PTP port status that includes time stamp value +* and sequce Id that are captured by PTP logic for a PTP frame that needs +* to be time stamped. +* +* INPUTS: +* port - logical port number. +* timeToRead - Arr0, Arr1, or Dep time (GT_PTP_TIME enum type) +* +* OUTPUTS: +* ptpStatus - PTP port status +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetTimeStamped +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PTP_TIME timeToRead, + OUT GT_PTP_TS_STATUS *ptpStatus +); + +/******************************************************************************* +* gptpResetTimeStamp +* +* DESCRIPTION: +* This routine resets PTP Time valid bit so that PTP logic can time stamp +* a next PTP frame that needs to be time stamped. +* +* INPUTS: +* port - logical port number. +* timeToReset - Arr0, Arr1, or Dep time (GT_PTP_TIME enum type) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpResetTimeStamp +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PTP_TIME timeToReset +); + +/******************************************************************************* +* gptpGetReg +* +* DESCRIPTION: +* This routine reads PTP register. +* +* INPUTS: +* port - logical port number. +* regOffset - register to read +* +* OUTPUTS: +* data - register data +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regOffset, + OUT GT_U32 *data +); + +/******************************************************************************* +* gptpSetReg +* +* DESCRIPTION: +* This routine writes data to PTP register. +* +* INPUTS: +* port - logical port number +* regOffset - register to be written +* data - data to be written +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regOffset, + IN GT_U32 data +); + + +#ifdef CONFIG_AVB_FPGA + +/******************************************************************************* +* gptpSetFPGAIntStatus +* +* DESCRIPTION: +* This routine sets interrupt status of PTP logic. +* +* INPUTS: +* intStatus - PTP Int Status +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetFPGAIntStatus +( + IN GT_QD_DEV *dev, + IN GT_U32 intStatus +); + + +/******************************************************************************* +* gptpGetFPGAIntStatus +* +* DESCRIPTION: +* This routine gets interrupt status of PTP logic. +* +* INPUTS: +* None. +* +* OUTPUTS: +* intStatus - PTP Int Status +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetFPGAIntStatus +( + IN GT_QD_DEV *dev, + IN GT_U32 *intStatus +); + + +/******************************************************************************* +* gptpSetFPGAIntEn +* +* DESCRIPTION: +* This routine enables PTP interrupt. +* +* INPUTS: +* intEn - enable/disable PTP interrupt (1 to enable, 0 to disable) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetFPGAIntEn +( + IN GT_QD_DEV *dev, + IN GT_U32 intEn +); + +/******************************************************************************* +* gptpGetClockSource +* +* DESCRIPTION: +* This routine gets PTP Clock source mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* clkSrc - PTP clock source (A/D Device or FPGA) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetClockSource +( + IN GT_QD_DEV *dev, + OUT GT_PTP_CLOCK_SRC *clkSrc +); + +/******************************************************************************* +* gptpSetClockSource +* +* DESCRIPTION: +* This routine sets PTP Clock source mode. +* +* INPUTS: +* clkSrc - PTP clock source (A/D Device or FPGA) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetClockSource +( + IN GT_QD_DEV *dev, + IN GT_PTP_CLOCK_SRC clkSrc +); + +/******************************************************************************* +* gptpGetP9Mode +* +* DESCRIPTION: +* This routine gets Port 9 Mode. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - Port 9 mode (GT_PTP_P9_MODE enum type) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetP9Mode +( + IN GT_QD_DEV *dev, + OUT GT_PTP_P9_MODE *mode +); + +/******************************************************************************* +* gptpSetP9Mode +* +* DESCRIPTION: +* This routine sets Port 9 Mode. +* +* INPUTS: +* mode - Port 9 mode (GT_PTP_P9_MODE enum type) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetP9Mode +( + IN GT_QD_DEV *dev, + IN GT_PTP_P9_MODE mode +); + +/******************************************************************************* +* gptpReset +* +* DESCRIPTION: +* This routine performs software reset for PTP logic. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpReset +( + IN GT_QD_DEV *dev +); + + +/******************************************************************************* +* gptpGetCycleAdjustEn +* +* DESCRIPTION: +* This routine checks if PTP Duty Cycle Adjustment is enabled. +* +* INPUTS: +* None. +* +* OUTPUTS: +* adjEn - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetCycleAdjustEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *adjEn +); + + +/******************************************************************************* +* gptpSetCycleAdjustEn +* +* DESCRIPTION: +* This routine enables/disables PTP Duty Cycle Adjustment. +* +* INPUTS: +* adjEn - GT_TRUE to enable, GT_FALSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetCycleAdjustEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL adjEn +); + + +/******************************************************************************* +* gptpGetCycleAdjust +* +* DESCRIPTION: +* This routine gets clock duty cycle adjustment value. +* +* INPUTS: +* None. +* +* OUTPUTS: +* adj - adjustment value (GT_PTP_CLOCK_ADJUSTMENT structure) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpGetCycleAdjust +( + IN GT_QD_DEV *dev, + OUT GT_PTP_CLOCK_ADJUSTMENT *adj +); + +/******************************************************************************* +* gptpSetCycleAdjust +* +* DESCRIPTION: +* This routine sets clock duty cycle adjustment value. +* +* INPUTS: +* adj - adjustment value (GT_PTP_CLOCK_ADJUSTMENT structure) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gptpSetCycleAdjust +( + IN GT_QD_DEV *dev, + IN GT_PTP_CLOCK_ADJUSTMENT *adj +); + +/******************************************************************************* +* gptpGetPLLEn +* +* DESCRIPTION: +* This routine checks if PLL is enabled. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* freqSel - PLL Frequency Selection (default 0x3 - 22.368MHz) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PLL Frequence selection is based on the Clock Recovery PLL device. +* IDT MK1575-01 is the default PLL device. +* +*******************************************************************************/ +GT_STATUS gptpGetPLLEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en, + OUT GT_U32 *freqSel +); + +/******************************************************************************* +* gptpSetPLLEn +* +* DESCRIPTION: +* This routine enables/disables PLL device. +* +* INPUTS: +* en - GT_TRUE to enable, GT_FALSE to disable +* freqSel - PLL Frequency Selection (default 0x3 - 22.368MHz) +* Meaningful only when enabling PLL device +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PLL Frequence selection is based on the Clock Recovery PLL device. +* IDT MK1575-01 is the default PLL device. +* +*******************************************************************************/ +GT_STATUS gptpSetPLLEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL en, + IN GT_U32 freqSel +); +#endif + +/* Amber APIs */ + +/* gtBrgFdb.c */ + +/******************************************************************************* +* gfdbGetMacAvb +* +* DESCRIPTION: +* ATU MAC entry in AVB mode. +* When enabled, ATU entries operate in AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_AVB_ENTRY, and +* GT_UC_STATIC_AVB_ENTRY +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_AVB_ENTRY, and +* GT_MC_PRIO_STATIC_AVB_ENTRY +* +* When disabled, ATU entries operate in non-AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_NRL, and +* GT_UC_STATIC_NRL +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_UNLIMITED_RATE, and +* GT_MC_PRIO_STATIC_UNLIMITED_RATE +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE if MacAvb is enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* +*******************************************************************************/ +GT_STATUS gfdbGetMacAvb +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +); + +/******************************************************************************* +* gfdbSetMacAvb +* +* DESCRIPTION: +* ATU MAC entry in AVB mode. +* When enabled, ATU entries operate in AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_AVB_ENTRY, and +* GT_UC_STATIC_AVB_ENTRY +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_AVB_ENTRY, and +* GT_MC_PRIO_STATIC_AVB_ENTRY +* +* When disabled, ATU entries operate in non-AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_NRL, and +* GT_UC_STATIC_NRL +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_UNLIMITED_RATE, and +* GT_MC_PRIO_STATIC_UNLIMITED_RATE +* +* INPUTS: +* mode - GT_TRUE to enable MacAvb, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gfdbSetMacAvb +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +); + +/******************************************************************************* +* gfdbGetPortAtuLearnLimit +* +* DESCRIPTION: +* Port's auto learning limit. When the limit is non-zero value, the number +* of MAC addresses that can be learned on this port are limited to the value +* specified in this API. When the learn limit has been reached any frame +* that ingresses this port with a source MAC address not already in the +* address database that is associated with this port will be discarded. +* Normal auto-learning will resume on the port as soon as the number of +* active unicast MAC addresses associated to this port is less than the +* learn limit. +* CPU directed ATU Load, Purge, or Move will not have any effect on the +* learn limit. +* This feature is disabled when the limit is zero. +* The following care is needed when enabling this feature: +* 1) dsable learning on the ports +* 2) flush all non-static addresses in the ATU +* 3) define the desired limit for the ports +* 4) re-enable learing on the ports +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* limit - auto learning limit ( 0 ~ 255 ) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gfdbGetPortAtuLearnLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *limit +); + +/* gtPCSCtrl.c */ + +/******************************************************************************* +* gpcsGetRGMIITimingDelay +* +* DESCRIPTION: +* RGMII receive/transmit Timing Control. This api adds delay to RXCLK for +* IND inputs and GTXCLK for OUTD outputs when port is in RGMII mode. +* Change to this bit are disruptive to normal operation. Hence any changes +* to this register must be done only while the port's link is down. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* rxmode - GT_FALSE for default setup, GT_TRUE for adding delay to rxclk +* txmode - GT_FALSE for default setup, GT_TRUE for adding delay to txclk +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpcsGetRGMIITimingDelay +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *rxmode, + OUT GT_BOOL *txmode +); + +/******************************************************************************* +* gpcsSetRGMIITimingDelay +* +* DESCRIPTION: +* RGMII receive/transmit Timing Control. This api adds delay to RXCLK for +* IND inputs and GTXCLK for OUTD outputs when port is in RGMII mode. +* Change to this bit are disruptive to normal operation. Hence any changes +* to this register must be done only while the port's link is down. +* +* INPUTS: +* port - the logical port number. +* rxmode - GT_FALSE for default setup, GT_TRUE for adding delay to rxclk +* txmode - GT_FALSE for default setup, GT_TRUE for adding delay to txclk +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpcsSetRGMIITimingDelay +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL rxmode, + IN GT_BOOL txmode +); + + +/* gtPortLed.c */ + +/******************************************************************************* +* gprtSetLED +* +* DESCRIPTION: +* This API allows to configure 4 LED sections, Pulse stretch, Blink rate, +* and special controls. +* +* INPUTS: +* port - the logical port number +* cfg - GT_LED_CFG value +* value - value to be configured +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gprtSetLED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value +); + + +/******************************************************************************* +* gprtGetLED +* +* DESCRIPTION: +* This API allows to retrieve 4 LED sections, Pulse stretch, Blink rate, +* and special controls. +* +* INPUTS: +* port - the logical port number +* cfg - GT_LED_CFG value +* +* OUTPUTS: +* value - configured value +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gprtGetLED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + OUT GT_U32 *value +); + + + + + +/* gtPortStatus.c */ + +/******************************************************************************* +* gprtGetQSizePerQPri +* +* DESCRIPTION: +* This routine gets egress queue size for port's each QPri (0 ~ 3). +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* counts - egress queue size per QPri (should be 4 * 16bytes) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetQSizePerQPri +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *counts +); + + +/* gtSysCtrl.c */ + + +/******************************************************************************* +* gsysGetARPwoBC +* +* DESCRIPTION: +* ARP detection without Broadcast checking. When enabled the switch core +* does not check for a Btoadcast MAC address as part of the ARP frame +* detection. It only checkes the Ether Type (0x0806). +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_BAD_PARAM - on bad parameter +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetARPwoBC +( + IN GT_QD_DEV *dev, + IN GT_BOOL *en +); + +/******************************************************************************* +* gsysSetARPwoBC +* +* DESCRIPTION: +* ARP detection without Broadcast checking. When enabled the switch core +* does not check for a Btoadcast MAC address as part of the ARP frame +* detection. It only checkes the Ether Type (0x0806). +* +* INPUTS: +* en - GT_TRUE to enable, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetARPwoBC +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + + +/******************************************************************************* +* gsysGetCLK125En +* +* DESCRIPTION: +* Clock 125MHz Enable. +* When this feature is enabled, the CLK125 pin has a free running 125 MHz +* clock output. +* When it's disabled, the CLK125 pin will be in tri-state. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if 125MHz clock is enabled, GT_FALSE otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetCLK125En +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gsysSetCLK125En +* +* DESCRIPTION: +* Clock 125MHz Enable. +* When this feature is enabled, the CLK125 pin has a free running 125 MHz +* clock output. +* When it's disabled, the CLK125 pin will be in tri-state. +* +* INPUTS: +* en - GT_TRUE to enable 125 MHz clock, GT_FALSE otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysSetCLK125En +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + + +/* gtPriTable.c */ + +/******************************************************************************* +* gsysSetFPriOverrideTable +* +* DESCRIPTION: +* Frame Priority Override. +* When a frame enters a port, its type is determined and the type is used +* to access the Frame Priority Table. If the type's fPriEn (in GT_FPRI_TBL_ENTRY +* structure) is enabled, then the frame's Frame Priority will be overridden +* with the value written in fPriority (in GT_FPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* FTYPE_PPPoE_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an Ether Type 0x8863 +* (i.e., PPPoE frames). Not used on DSA Control frames. +* FTYPE_IP_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether +* Type. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* entry - Frame Priority Override Table entry (GT_FPRI_TBL_ENTRY) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetFPriOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + IN GT_FPRI_TBL_ENTRY *entry +); + + +/******************************************************************************* +* gsysGetFPriOverrideTable +* +* DESCRIPTION: +* Frame Priority Override. +* When a frame enters a port, its type is determined and the type is used +* to access the Frame Priority Table. If the type's fPriEn (in GT_FPRI_TBL_ENTRY +* structure) is enabled, then the frame's Frame Priority will be overridden +* with the value written in fPriority (in GT_FPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* FTYPE_PPPoE_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an Ether Type 0x8863 +* (i.e., PPPoE frames). Not used on DSA Control frames. +* FTYPE_IP_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether +* Type. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* +* OUTPUTS: +* entry - Frame Priority Override Table entry (GT_FPRI_TBL_ENTRY) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetFPriOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + OUT GT_FPRI_TBL_ENTRY *entry +); + + +/******************************************************************************* +* gsysSetQPriAvbOverrideTable +* +* DESCRIPTION: +* Queue Priority Override for AVB enabled ports or AvbOverride enabled ports. +* When a frame enters a AVB port, its type is determined and the type is used +* to access the Queue Priority Table. If the type's qPriEn (in GT_QPRI_TBL_ENTRY +* structure) is enabled, then the frame's Queue Priority will be overridden +* with the value written in qPriority (in GT_QPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* FTYPE_PPPoE_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an Ether Type 0x8863 +* (i.e., PPPoE frames). Not used on DSA Control frames. +* FTYPE_IP_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether +* Type. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* entry - Q Priority Override Table entry (GT_QPRI_TBL_ENTRY) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetQPriAvbOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + IN GT_QPRI_TBL_ENTRY *entry +); + + +/******************************************************************************* +* gsysGetQPriAvbOverrideTable +* +* DESCRIPTION: +* Queue Priority Override for AVB enabled ports or AvbOverride enabled ports. +* When a frame enters a AVB port, its type is determined and the type is used +* to access the Queue Priority Table. If the type's qPriEn (in GT_QPRI_TBL_ENTRY +* structure) is enabled, then the frame's Queue Priority will be overridden +* with the value written in qPriority (in GT_QPRI_TBL_ENTRY structure). +* Frame Types supported are: +* FTYPE_DSA_TO_CPU_BPDU - +* Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT). +* Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_F2R - +* Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register +* Reply). Not used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_IGMP - +* Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap) +* and on non-DSA Control frames that are IGMP or MLD trapped +* FTYPE_DSA_TO_CPU_TRAP - +* Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and +* on non-DSA Control frames that are Policy Trapped +* FTYPE_DSA_TO_CPU_ARP - +* Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and +* on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API). +* FTYPE_DSA_TO_CPU_MIRROR - +* Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and +* on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API). +* FTYPE_DSA_TO_CPU_RESERVED - +* Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not +* used on non-DSA Control frames. +* FTYPE_DSA_TO_CPU_UCAST_MGMT - +* Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast +* MGMT). Not used on non-DSA Control frames. +* FTYPE_DSA_FROM_CPU - +* Used on DSA From_CPU frames. Not used on non-DSA Control frame +* FTYPE_DSA_CROSS_CHIP_FC - +* Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow +* Control). Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_EGRESS_MON - +* Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx). +* Not used on non-DSA Control frames. +* FTYPE_DSA_CROSS_CHIP_INGRESS_MON - +* Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx). +* Not used on non-DSA Control frames. +* FTYPE_PORT_ETYPE_MATCH - +* Used on normal network ports (see gprtSetFrameMode API) +* on frames whose Ethertype matches the port's PortEType register. +* Not used on non-DSA Control frames. +* FTYPE_BCAST_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain a Broadcast +* destination address. Not used on DSA Control frames. +* FTYPE_PPPoE_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an Ether Type 0x8863 +* (i.e., PPPoE frames). Not used on DSA Control frames. +* FTYPE_IP_NON_DSA_CONTROL - +* Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether +* Type. Not used on DSA Control frames. +* +* INPUTS: +* fType - frame type (GT_PRI_OVERRIDE_FTYPE) +* +* OUTPUTS: +* entry - Q Priority Override Table entry (GT_QPRI_TBL_ENTRY) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on unknown frame type +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetQPriAvbOverrideTable +( + IN GT_QD_DEV *dev, + IN GT_PRI_OVERRIDE_FTYPE fType, + OUT GT_QPRI_TBL_ENTRY *entry +); + + +/* gtPortCtrl.c */ + +/******************************************************************************* +* gprtGet200Base +* +* DESCRIPTION: +* 200 Base mode. This bit can be used to change the port's Px_GTXCLK +* frequency to 50MHz to support 200 BASE mode as follows: +* 0 = 25MHz Px_GTXCLK +* 1 = 50MHz Px_GTXCLK +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - 0 for 100Mbps, 1 for 200Mbps +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* C_Mode should be set to 0x2 in order for this API to work +* +*******************************************************************************/ +GT_STATUS gprtGet200Base +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *mode +); + + +/******************************************************************************* +* gprtSet200Base +* +* DESCRIPTION: +* 200 Base mode. This bit can be used to change the port's Px_GTXCLK +* frequency to 50MHz to support 200 BASE mode as follows: +* 0 = 25MHz Px_GTXCLK +* 1 = 50MHz Px_GTXCLK +* +* INPUTS: +* port - the logical port number. +* mode - 0 for 100Mbps, 1 for 200Mbps +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* C_Mode should be set to 0x2 in order for this API to work +* +*******************************************************************************/ +GT_STATUS gprtSet200Base +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 mode +); + + +/* gtPIRL2.c */ + +/******************************************************************************* +* gpirl2WriteTSMResource +* +* DESCRIPTION: +* This routine writes rate resource bucket parameters in Time Slot Metering +* mode to the given resource of the port. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 1). +* pirlData - PIRL TSM resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Only Resource 0 and 1 can be supported for TSM Mode. +* +*******************************************************************************/ +GT_STATUS gpirl2WriteTSMResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + IN GT_PIRL2_TSM_DATA *pirlData +); + + +/******************************************************************************* +* gpirl2ReadTSMResource +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* Returned ingressRate would be rough number. Instead, customSetup will +* have the exact configured value. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 1). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Only Resource 0 and 1 can be supported for TSM Mode. +* +*******************************************************************************/ +GT_STATUS gpirl2ReadTSMResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + OUT GT_PIRL2_TSM_DATA *pirlData +); + + +/* gtPTP.c */ + +/******************************************************************************* +* gtaiSetEventConfig +* +* DESCRIPTION: +* This routine sets TAI Event Capture configuration parameters. +* +* INPUTS: +* eventData - TAI Event Capture configuration parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiSetEventConfig +( + IN GT_QD_DEV *dev, + IN GT_TAI_EVENT_CONFIG *eventData +); + + +/******************************************************************************* +* gtaiGetEventConfig +* +* DESCRIPTION: +* This routine gets TAI Event Capture configuration parameters. +* +* INPUTS: +* None. +* +* OUTPUTS: +* eventData - TAI Event Capture configuration parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetEventConfig +( + IN GT_QD_DEV *dev, + OUT GT_TAI_EVENT_CONFIG *eventData +); + +/******************************************************************************* +* gtaiGetEventStatus +* +* DESCRIPTION: +* This routine gets TAI Event Capture status. +* +* INPUTS: +* None. +* +* OUTPUTS: +* eventData - TAI Event Capture configuration parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetEventStatus +( + IN GT_QD_DEV *dev, + OUT GT_TAI_EVENT_STATUS *status +); + +/******************************************************************************* +* gtaiGetEventInt +* +* DESCRIPTION: +* This routine gets TAI Event Capture Interrupt status. +* +* INPUTS: +* None. +* +* OUTPUTS: +* intStatus - interrupt status for TAI Event capture +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetEventInt +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *intStatus +); + + +/******************************************************************************* +* gtaiGetTrigInt +* +* DESCRIPTION: +* This routine gets TAI Trigger Interrupt status. +* +* INPUTS: +* None. +* +* OUTPUTS: +* intStatus - interrupt status for TAI Trigger +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetTrigInt +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *intStatus +); + +/******************************************************************************* +* gtaiSetTrigConfig +* +* DESCRIPTION: +* This routine sets TAI Trigger configuration parameters. +* +* INPUTS: +* trigEn - enable/disable TAI Trigger. +* trigData - TAI Trigger configuration parameters (valid only if trigEn is GT_TRUE). +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiSetTrigConfig +( + IN GT_QD_DEV *dev, + IN GT_BOOL trigEn, + IN GT_TAI_TRIGGER_CONFIG *trigData +); + +/******************************************************************************* +* gtaiGetTrigConfig +* +* DESCRIPTION: +* This routine gets TAI Trigger configuration parameters. +* +* INPUTS: +* None. +* +* OUTPUTS: +* trigEn - enable/disable TAI Trigger. +* trigData - TAI Trigger configuration parameters (valid only if trigEn is GT_TRUE). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetTrigConfig +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *trigEn, + OUT GT_TAI_TRIGGER_CONFIG *trigData +); + +/******************************************************************************* +* gtaiGetTSClkPer +* +* DESCRIPTION: +* Time Stamping Clock Period in pico seconds. +* This routine specifies the clock period for the time stamping clock supplied +* to the PTP hardware logic. +* This is the clock that is used by the hardware logic to update the PTP +* Global Time Counter. +* +* INPUTS: +* None. +* +* OUTPUTS: +* clk - time stamping clock period +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetTSClkPer +( + IN GT_QD_DEV *dev, + OUT GT_U32 *clk +); + + +/******************************************************************************* +* gtaiSetTSClkPer +* +* DESCRIPTION: +* Time Stamping Clock Period in pico seconds. +* This routine specifies the clock period for the time stamping clock supplied +* to the PTP hardware logic. +* This is the clock that is used by the hardware logic to update the PTP +* Global Time Counter. +* +* INPUTS: +* clk - time stamping clock period +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiSetTSClkPer +( + IN GT_QD_DEV *dev, + IN GT_U32 clk +); + +/******************************************************************************* +* gtaiSetMultiPTPSync +* +* DESCRIPTION: +* This routine sets Multiple PTP device sync mode and sync time (TrigGenAmt). +* When enabled, the hardware logic detects a low to high transition on the +* EventRequest(GPIO) and transfers the sync time into the PTP Global Time +* register. The EventCapTime is also updated at that instant. +* +* INPUTS: +* multiEn - enable/disable Multiple PTP device sync mode +* syncTime - sync time (valid only if multiEn is GT_TRUE) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* When enabled, gtaiSetTrigConfig, gtaiSetEventConfig, gtaiSetTimeInc, +* and gtaiSetTimeDec APIs are not operational. +* +*******************************************************************************/ +GT_STATUS gtaiSetMultiPTPSync +( + IN GT_QD_DEV *dev, + IN GT_BOOL multiEn, + IN GT_32 syncTime +); + +/******************************************************************************* +* gtaiGetMultiPTPSync +* +* DESCRIPTION: +* This routine gets Multiple PTP device sync mode and sync time (TrigGenAmt). +* When enabled, the hardware logic detects a low to high transition on the +* EventRequest(GPIO) and transfers the sync time into the PTP Global Time +* register. The EventCapTime is also updated at that instant. +* +* INPUTS: +* None. +* +* OUTPUTS: +* multiEn - enable/disable Multiple PTP device sync mode +* syncTime - sync time (valid only if multiEn is GT_TRUE) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* When enabled, gtaiSetTrigConfig, gtaiSetEventConfig, gtaiSetTimeInc, +* and gtaiSetTimeDec APIs are not operational. +* +*******************************************************************************/ +GT_STATUS gtaiGetMultiPTPSync +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *multiEn, + OUT GT_32 *syncTime +); + +/******************************************************************************* +* gtaiGetTimeIncDec +* +* DESCRIPTION: +* This routine retrieves Time increment/decrement setup. +* This amount specifies the number of units of PTP Global Time that need to be +* incremented or decremented. This is used for adjusting the PTP Global Time +* counter value by a certain amount. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* inc - GT_TRUE if increment, GT_FALSE if decrement +* amount - increment/decrement amount +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiGetTimeIncDec +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en, + OUT GT_BOOL *inc, + OUT GT_U32 *amount +); + +/******************************************************************************* +* gtaiSetTimeInc +* +* DESCRIPTION: +* This routine enables time increment by the specifed time increment amount. +* The amount specifies the number of units of PTP Global Time that need to be +* incremented. This is used for adjusting the PTP Global Time counter value by +* a certain amount. +* Increment occurs just once. +* +* INPUTS: +* amount - time increment amount (0 ~ 0xFF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiSetTimeInc +( + IN GT_QD_DEV *dev, + IN GT_U32 amount +); + +/******************************************************************************* +* gtaiSetTimeDec +* +* DESCRIPTION: +* This routine enables time decrement by the specifed time decrement amount. +* The amount specifies the number of units of PTP Global Time that need to be +* decremented. This is used for adjusting the PTP Global Time counter value by +* a certain amount. +* Decrement occurs just once. +* +* INPUTS: +* amount - time decrement amount (0 ~ 0x7FF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gtaiSetTimeDec +( + IN GT_QD_DEV *dev, + IN GT_U32 amount +); + + +/******************************************************************************* +* gavbGetPriority +* +* DESCRIPTION: +* Priority overwrite. +* Supported priority type is defined as GT_AVB_PRI_TYPE. +* Priority is either 3 bits or 2 bits depending on priority type. +* GT_AVB_HI_FPRI - priority is 0 ~ 7 +* GT_AVB_HI_QPRI - priority is 0 ~ 3 +* GT_AVB_LO_FPRI - priority is 0 ~ 7 +* GT_AVB_LO_QPRI - priority is 0 ~ 3 +* GT_LEGACY_HI_FPRI - priority is 0 ~ 7 +* GT_LEGACY_HI_QPRI - priority is 0 ~ 3 +* GT_LEGACY_LO_FPRI - priority is 0 ~ 7 +* GT_LEGACY_LO_QPRI - priority is 0 ~ 3 +* +* INPUTS: +* priType - GT_AVB_PRI_TYPE +* +* OUTPUTS: +* pri - priority +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetPriority +( + IN GT_QD_DEV *dev, + IN GT_AVB_PRI_TYPE priType, + OUT GT_U32 *pri +); + +/******************************************************************************* +* gavbSetPriority +* +* DESCRIPTION: +* Priority overwrite. +* Supported priority type is defined as GT_AVB_PRI_TYPE. +* Priority is either 3 bits or 2 bits depending on priority type. +* GT_AVB_HI_FPRI - priority is 0 ~ 7 +* GT_AVB_HI_QPRI - priority is 0 ~ 3 +* GT_AVB_LO_FPRI - priority is 0 ~ 7 +* GT_AVB_LO_QPRI - priority is 0 ~ 3 +* GT_LEGACY_HI_FPRI - priority is 0 ~ 7 +* GT_LEGACY_HI_QPRI - priority is 0 ~ 3 +* GT_LEGACY_LO_FPRI - priority is 0 ~ 7 +* GT_LEGACY_LO_QPRI - priority is 0 ~ 3 +* +* INPUTS: +* priType - GT_AVB_PRI_TYPE +* pri - priority +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetPriority +( + IN GT_QD_DEV *dev, + IN GT_AVB_PRI_TYPE priType, + IN GT_U32 pri +); + +/******************************************************************************* +* gavbGetAVBHiLimit +* +* DESCRIPTION: +* AVB Hi Frame Limit. +* When these bits are zero, normal frame processing occurs. +* When it's non-zero, they are used to define the maximum frame size allowed +* for AVB frames that can be placed into the GT_AVB_HI_QPRI queue. Frames +* that are over this size limit are filtered. The only exception to this +* is non-AVB frames that get their QPriAvb assigned by the Priority Override +* Table +* +* INPUTS: +* None. +* +* OUTPUTS: +* limit - Hi Frame Limit +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAVBHiLimit +( + IN GT_QD_DEV *dev, + OUT GT_U32 *limit +); + +/******************************************************************************* +* gavbSetAVBHiLimit +* +* DESCRIPTION: +* AVB Hi Frame Limit. +* When these bits are zero, normal frame processing occurs. +* When it's non-zero, they are used to define the maximum frame size allowed +* for AVB frames that can be placed into the GT_AVB_HI_QPRI queue. Frames +* that are over this size limit are filtered. The only exception to this +* is non-AVB frames that get their QPriAvb assigned by the Priority Override +* Table +* +* INPUTS: +* limit - Hi Frame Limit +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAVBHiLimit +( + IN GT_QD_DEV *dev, + IN GT_U32 limit +); + +/******************************************************************************* +* gavbGetPtpExtClk +* +* DESCRIPTION: +* PTP external clock select. +* When this bit is cleared to a zero, the PTP core gets its clock from +* an internal 125MHz clock based on the device's XTAL_IN input. +* When this bit is set to a one, the PTP core gets its clock from the device's +* PTP_EXTCLK pin. +* +* INPUTS: +* None. +* +* OUTPUTS: +* extClk - GT_TRUE if external clock is selected, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetPtpExtClk +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *extClk +); + +/******************************************************************************* +* gavbSetPtpExtClk +* +* DESCRIPTION: +* PTP external clock select. +* When this bit is cleared to a zero, the PTP core gets its clock from +* an internal 125MHz clock based on the device's XTAL_IN input. +* When this bit is set to a one, the PTP core gets its clock from the device's +* PTP_EXTCLK pin. +* +* INPUTS: +* extClk - GT_TRUE if external clock is selected, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetPtpExtClk +( + IN GT_QD_DEV *dev, + IN GT_BOOL extClk +); + +/******************************************************************************* +* gavbGetRecClkSel +* +* DESCRIPTION: +* Synchronous Ethernet Recovered Clock Select. +* This field indicate the internal PHY number whose recovered clock will +* be presented on the SE_RCLK0 or SE_RCLK1 pin depending on the recClk selection. +* +* INPUTS: +* recClk - GT_AVB_RECOVERED_CLOCK type +* +* OUTPUTS: +* clkSel - recovered clock selection +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetRecClkSel +( + IN GT_QD_DEV *dev, + IN GT_AVB_RECOVERED_CLOCK recClk, + OUT GT_U32 *clkSel +); + + +/******************************************************************************* +* gavbSetRecClkSel +* +* DESCRIPTION: +* Synchronous Ethernet Recovered Clock Select. +* This field indicate the internal PHY number whose recovered clock will +* be presented on the SE_RCLK0 or SE_RCLK1 pin depending on the recClk selection. +* +* INPUTS: +* recClk - GT_AVB_RECOVERED_CLOCK type +* clkSel - recovered clock selection (should be less than 8) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetRecClkSel +( + IN GT_QD_DEV *dev, + IN GT_AVB_RECOVERED_CLOCK recClk, + IN GT_U32 clkSel +); + +/******************************************************************************* +* gavbGetAvbOuiBytes +* +* DESCRIPTION: +* AVB OUI Limit Filter bytes(0 ~ 2). +* When all three of the AvbOui Bytes are zero, normal frame processing occurs. +* When any of the three AvbOui Bytes are non-zero, all AVB frames must have a +* destination address whose 1st three bytes of the DA match these three +* AvbOui Bytes or the frame will be filtered. +* +* INPUTS: +* None. +* +* OUTPUTS: +* ouiBytes - 3 bytes of OUI field in Ethernet address format +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAvbOuiBytes +( + IN GT_QD_DEV *dev, + OUT GT_U8 *obiBytes +); + +/******************************************************************************* +* gavbSetAvbOuiBytes +* +* DESCRIPTION: +* AVB OUI Limit Filter bytes(0 ~ 2). +* When all three of the AvbOui Bytes are zero, normal frame processing occurs. +* When any of the three AvbOui Bytes are non-zero, all AVB frames must have a +* destination address whose 1st three bytes of the DA match these three +* AvbOui Bytes or the frame will be filtered. +* +* INPUTS: +* ouiBytes - 3 bytes of OUI field in Ethernet address format +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAvbOuiBytes +( + IN GT_QD_DEV *dev, + IN GT_U8 *obiBytes +); + +/******************************************************************************* +* gavbGetAvbMode +* +* DESCRIPTION: +* Port's AVB Mode. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_AVB_MODE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAvbMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_AVB_MODE *mode +); + +/******************************************************************************* +* gavbSetAvbMode +* +* DESCRIPTION: +* Port's AVB Mode. +* +* INPUTS: +* port - the logical port number +* mode - GT_AVB_MODE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAvbMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_AVB_MODE mode +); + +/******************************************************************************* +* gavbGetAvbOverride +* +* DESCRIPTION: +* AVB Override. +* When disabled, normal frame processing occurs. +* When enabled, the egress portion of this port is considered AVB even if +* the ingress portion is not. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAvbOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gavbSetAvbOverride +* +* DESCRIPTION: +* AVB Override. +* When disabled, normal frame processing occurs. +* When enabled, the egress portion of this port is considered AVB even if +* the ingress portion is not. +* +* INPUTS: +* port - the logical port number +* en - GT_TRUE to enable, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAvbOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + +/******************************************************************************* +* gavbGetFilterBadAvb +* +* DESCRIPTION: +* Filter Bad AVB frames. +* When disabled, normal frame processing occurs. +* When enabled, frames that are considered Bad AVB frames are filtered. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetFilterBadAvb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gavbSetFilterBadAvb +* +* DESCRIPTION: +* Filter Bad AVB frames. +* When disabled, normal frame processing occurs. +* When enabled, frames that are considered Bad AVB frames are filtered. +* +* INPUTS: +* port - the logical port number +* en - GT_TRUE to enable, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetFilterBadAvb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + +/******************************************************************************* +* gavbGetAvbTunnel +* +* DESCRIPTION: +* AVB Tunnel. +* When disabled, normal frame processing occurs. +* When enabled, the port based VLAN Table masking, 802.1Q VLAN membership +* masking and the Trunk Masking is bypassed for any frame entering this port +* that is considered AVB by DA. This includes unicast as well as multicast +* frame +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* en - GT_TRUE if enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAvbTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + + +/******************************************************************************* +* gavbSetAvbTunnel +* +* DESCRIPTION: +* AVB Tunnel. +* When disabled, normal frame processing occurs. +* When enabled, the port based VLAN Table masking, 802.1Q VLAN membership +* masking and the Trunk Masking is bypassed for any frame entering this port +* that is considered AVB by DA. This includes unicast as well as multicast +* frame +* +* INPUTS: +* port - the logical port number +* en - GT_TRUE to enable, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAvbTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + + +/******************************************************************************* +* gavbGetAvbFramePolicy +* +* DESCRIPTION: +* AVB Hi or Lo frame policy mapping. +* Supported policies are defined in GT_AVB_FRAME_POLICY. +* +* INPUTS: +* port - the logical port number +* fType - GT_AVB_FRAME_TYPE +* +* OUTPUTS: +* policy - GT_AVB_FRAME_POLICY +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbGetAvbFramePolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_AVB_FRAME_TYPE fType, + OUT GT_AVB_FRAME_POLICY *policy +); + + +/******************************************************************************* +* gavbSetAvbFramePolicy +* +* DESCRIPTION: +* AVB Hi or Lo frame policy mapping. +* Supported policies are defined in GT_AVB_FRAME_POLICY. +* +* INPUTS: +* port - the logical port number +* fType - GT_AVB_FRAME_TYPE +* policy - GT_AVB_FRAME_POLICY +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gavbSetAvbFramePolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_AVB_FRAME_TYPE fType, + IN GT_AVB_FRAME_POLICY policy +); + +/* Amber QAV API */ +/*******************************************************************************/ +/* Amber QAV API */ +/******************************************************************************* +* gqavSetPortQpriXQTSToken +* +* DESCRIPTION: +* This routine set Priority Queue 0-3 time slot tokens on a port. +* The setting value is number of tokens that need to be subtracted at each +* QTS interval boundary. +* +* INPUTS: +* port - the logical port number +* queue - 0 - 3 +* qtsToken - number of tokens. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gqavSetPortQpriXQTSToken +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 queue, + IN GT_U16 qtsToken +); + +/******************************************************************************* +* gqavGetPortQpriXQTSToken +* +* DESCRIPTION: +* This routine get Priority Queue 0-3 time slot tokens on a port. +* The setting value is number of tokens that need to be subtracted at each +* QTS interval boundary. +* +* INPUTS: +* port - the logical port number +* queue - 0 - 3 +* +* OUTPUTS: +* qtsToken - number of tokens +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gqavGetPortQpriXQTSToken +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 queue, + OUT GT_U16 *qtsToken +); + +/******************************************************************************* +* gqavSetPortQpriXBurstBytes +* +* DESCRIPTION: +* This routine set Priority Queue 0-3 Burst Bytes on a port. +* This value specifies the number of credits in bytes that can be +* accumulated when the queue is blocked from sending out a frame due to +* higher priority queue frames being sent out. +* +* INPUTS: +* port - the logical port number +* queue - 0 - 3 +* burst - number of credits in bytes . +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetPortQpriXBurstBytes +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 queue, + IN GT_U16 burst +); + +/******************************************************************************* +* gqavGetPortQpriXBurstBytes +* +* DESCRIPTION: +* This routine get Priority Queue 0-3 Burst Bytes on a port. +* This value specifies the number of credits in bytes that can be +* accumulated when the queue is blocked from sending out a frame due to +* higher priority queue frames being sent out. +* +* INPUTS: +* port - the logical port number +* queue - 0 - 3 +* +* OUTPUTS: +* burst - number of credits in bytes . +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetPortQpriXBurstBytes +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U8 queue, + OUT GT_U16 *burst +); + +/******************************************************************************* +* gqavSetPortQavEnable +* +* DESCRIPTION: +* This routine set QAV enable status on a port. +* +* INPUTS: +* port - the logical port number +* en - GT_TRUE: QAV enable, GT_FALSE: QAV disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetPortQavEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +); + +/******************************************************************************* +* gqavGetPortQavEnable +* +* DESCRIPTION: +* This routine get QAV enable status on a port. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* en - GT_TRUE: QAV enable, GT_FALSE: QAV disable +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetPortQavEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +); + +/*******************************************************************************/ +/* QAV Global registers processing */ +/******************************************************************************* +* gqavSetGlobalAdminMGMT +* +* DESCRIPTION: +* This routine set to accept Admit Management Frames always. +* +* INPUTS: +* en - GT_TRUE to set MGMT frame accepted always, +* GT_FALSE do not set MGMT frame accepted always +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalAdminMGMT +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gqavGetGlobalAdminMGMT +* +* DESCRIPTION: +* This routine get setting of Admit Management Frames always. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to set MGMT frame accepted always, +* GT_FALSE do not set MGMT frame accepted always +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalAdminMGMT +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gqavSetGlobalIsoPtrThreshold +* +* DESCRIPTION: +* This routine set Global Isochronous Queue Pointer Threshold. +* This field indicates the total number of isochronous pointers +* that are reserved for isochronous streams. The value is expected to be +* computed in SRP software and programmed into hardware based on the total +* aggregate isochronous streams configured to go through this device.. +* +* INPUTS: +* isoPtrs - total number of isochronous pointers +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoPtrThreshold +( + IN GT_QD_DEV *dev, + IN GT_U16 isoPtrs +); + +/******************************************************************************* +* gqavGetGlobalIsoPtrThreshold +* +* DESCRIPTION: +* This routine get Global Isochronous Queue Pointer Threshold. +* This field indicates the total number of isochronous pointers +* that are reserved for isochronous streams. The value is expected to be +* computed in SRP software and programmed into hardware based on the total +* aggregate isochronous streams configured to go through this device.. +* +* INPUTS: +* None. +* +* OUTPUTS: +* isoPtrs - total number of isochronous pointers +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoPtrThreshold +( + IN GT_QD_DEV *dev, + OUT GT_U16 *isoPtrs +); + +/******************************************************************************* +* gqavSetGlobalDisQSD4MGMT +* +* DESCRIPTION: +* This routine set Disable Queue Scheduler Delays for Management frames.. +* +* INPUTS: +* en - GT_TRUE, it indicates to the Queue Controller to disable applying Queue +* Scheduler Delays and the corresponding rate regulator does not account +* for MGMT frames through this queue. +* GT_FALSE, the MGMT frames follow similar rate regulation and delay +* regulation envelope as specified for the isochronous queue that the +* MGMT frames are sharing with. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalDisQSD4MGMT +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gqavGetGlobalDisQSD4MGMT +* +* DESCRIPTION: +* This routine Get Disable Queue Scheduler Delays for Management frames.. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE, it indicates to the Queue Controller to disable applying Queue +* Scheduler Delays and the corresponding rate regulator does not account +* for MGMT frames through this queue. +* GT_FALSE, the MGMT frames follow similar rate regulation and delay +* regulation envelope as specified for the isochronous queue that the +* MGMT frames are sharing with. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalDisQSD4MGMT +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gqavSetGlobalInterrupt +* +* DESCRIPTION: +* This routine set QAV interrupt enable, +* The QAV interrypts include: +* [GT_QAV_INT_ENABLE_ENQ_LMT_BIT] # EnQ Limit Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_DEL_BIT] # Iso Delay Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_DIS_BIT] # Iso Discard Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT] # Iso Packet Memory Exceeded +* Interrupt Enable +* +* INPUTS: +* intEn - [GT_QAV_INT_ENABLE_ENQ_LMT_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_DEL_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_DIS_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalInterrupt +( + IN GT_QD_DEV *dev, + IN GT_U16 intEn +); + +/******************************************************************************* +* gqavGetGlobalInterrupt +* +* DESCRIPTION: +* This routine get QAV interrupt status and enable status, +* The QAV interrypt status include: +* [GT_QAV_INT_STATUS_ENQ_LMT_BIT] # Enqueue Delay Limit exceeded +* [GT_QAV_INT_STATUS_ISO_DEL_BIT] # Iso Delay Interrupt Status +* [GT_QAV_INT_STATUS_ISO_DIS_BIT] # Iso Discard Interrupt Status +* [GT_QAV_INT_STATUS_ISO_LIMIT_EX_BIT] # Iso Packet Memory Exceeded +* Interrupt Status +* The QAV interrypt enable status include: +* [GT_QAV_INT_ENABLE_ENQ_LMT_BIT] # EnQ Limit Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_DEL_BIT] # Iso Delay Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_DIS_BIT] # Iso Discard Interrupt Enable +* [GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT] # Iso Packet Memory Exceeded +* Interrupt Enable +* +* INPUTS: +* None. +* +* OUTPUTS: +* intEnSt - [GT_QAV_INT_STATUS_ENQ_LMT_BIT] OR +* [GT_QAV_INT_STATUS_ISO_DEL_BIT] OR +* [GT_QAV_INT_STATUS_ISO_DIS_BIT] OR +* [GT_QAV_INT_STATUS_ISO_LIMIT_EX_BIT] OR +* [GT_QAV_INT_ENABLE_ENQ_LMT_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_DEL_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_DIS_BIT] OR +* [GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalInterrupt +( + IN GT_QD_DEV *dev, + OUT GT_U16 *intEnSt +); + +/******************************************************************************* +* gqavGetGlobalIsoInterruptPort +* +* DESCRIPTION: +* This routine get Isochronous interrupt port. +* This field indicates the port number for IsoDisInt or IsoLimitExInt +* bits. Only one such interrupt condition can be detected by hardware at one +* time. Once an interrupt bit has been set along with the IsoIntPort, the +* software would have to come and clear the bits before hardware records +* another interrupt event. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - port number for IsoDisInt or IsoLimitExInt bits. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoInterruptPort +( + IN GT_QD_DEV *dev, + OUT GT_U8 *port +); + +/******************************************************************************* +* gqavSetGlobalIsoDelayLmt +* +* DESCRIPTION: +* This routine set Isochronous queue delay Limit +* This field represents a per-port isochronous delay limit that +* will be checked by the queue controller logic to ensure no isochronous +* packets suffer more than this delay w.r.t to their eligibility time slot. +* This represents the number of Queue Time Slots. The interval for the QTS +* can be configured using the register in Qav Global Configuration, Offset 0x2. +* +* INPUTS: +* limit - per-port isochronous delay limit. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoDelayLmt +( + IN GT_QD_DEV *dev, + IN GT_U8 limit +); + +/******************************************************************************* +* gqavGetGlobalIsoDelayLmt +* +* DESCRIPTION: +* This routine get Isochronous queue delay Limit +* This field represents a per-port isochronous delay limit that +* will be checked by the queue controller logic to ensure no isochronous +* packets suffer more than this delay w.r.t to their eligibility time slot. +* This represents the number of Queue Time Slots. The interval for the QTS +* can be configured using the register in Qav Global Configuration, Offset 0x2. +* +* INPUTS: +* None. +* +* OUTPUTS: +* limit - per-port isochronous delay limit. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoDelayLmt +( + IN GT_QD_DEV *dev, + OUT GT_U8 *limit +); + +/******************************************************************************* +* gqavSetGlobalIsoMonEn +* +* DESCRIPTION: +* This routine set Isochronous monitor enable +* Set GT_TRUE: this bit enables the statistics gathering capabilities stated +* in PTP Global Status Registers Offset 0xD, 0xE and 0xF. Once enabled, the +* software is expected to program the IsoMonPort (PTP Global Status Offset +* 0xD) indicating which port of the device does the software wants to monitor. +* Upon setting this bit, the hardware collects IsoHiDisCtr, IsoLoDisCtr and +* IsoSchMissCtr values for the port indicated by IsoMonPort till this bit is +* set to a zero. +* Set GT_FALSE: this bit disables the statistics gathering capabilities. +* +* INPUTS: +* en - GT_TRUE / GT_FALSE. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoMonEn +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gqavGetGlobalIsoMonEn +* +* DESCRIPTION: +* This routine get Isochronous monitor enable +* Set GT_TRUE: this bit enables the statistics gathering capabilities stated +* in PTP Global Status Registers Offset 0xD, 0xE and 0xF. Once enabled, the +* software is expected to program the IsoMonPort (PTP Global Status Offset +* 0xD) indicating which port of the device does the software wants to monitor. +* Upon setting this bit, the hardware collects IsoHiDisCtr, IsoLoDisCtr and +* IsoSchMissCtr values for the port indicated by IsoMonPort till this bit is +* set to a zero. +* Set GT_FALSE: this bit disables the statistics gathering capabilities. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE / GT_FALSE. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoMonEn +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +); + +/******************************************************************************* +* gqavSetGlobalIsoMonPort +* +* DESCRIPTION: +* This routine set Isochronous monitoring port. +* This field is updated by software along with Iso Mon En bit +* (Qav Global Status, offset 0xD) and it indicates the port number that +* the software wants the hardware to start monitoring i.e., start updating +* IsoHiDisCtr, IsoLoDisCtr and IsoSchMissCtr. The queue controller clears +* the above stats when IsoMonPort is changed.. +* +* INPUTS: +* port - port number . +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoMonPort +( + IN GT_QD_DEV *dev, + IN GT_U16 port +); + +/******************************************************************************* +* gqavGetGlobalIsoMonPort +* +* DESCRIPTION: +* This routine get Isochronous monitoring port. +* This field is updated by software along with Iso Mon En bit +* (Qav Global Status, offset 0xD) and it indicates the port number that +* the software wants the hardware to start monitoring i.e., start updating +* IsoHiDisCtr, IsoLoDisCtr and IsoSchMissCtr. The queue controller clears +* the above stats when IsoMonPort is changed.. +* +* INPUTS: +* None. +* +* OUTPUTS: +* port - port number. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoMonPort +( + IN GT_QD_DEV *dev, + OUT GT_U16 *port +); + +/******************************************************************************* +* gqavSetGlobalIsoHiDisCtr +* +* DESCRIPTION: +* This routine set Isochronous hi queue discard counter. +* This field is updated by hardware when instructed to do so by +* enabling the IsoMonEn bit in Qav Global Status Register Offset 0xD. +* This is an upcounter of number of isochronous hi packets discarded +* by Queue Controller. +* +* INPUTS: +* disCtr - upcounter of number of isochronous hi packets discarded +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoHiDisCtr +( + IN GT_QD_DEV *dev, + IN GT_U8 disCtr +); + +/******************************************************************************* +* gqavGetGlobalIsoHiDisCtr +* +* DESCRIPTION: +* This routine get Isochronous hi queue discard counter. +* This field is updated by hardware when instructed to do so by +* enabling the IsoMonEn bit in Qav Global Status Register Offset 0xD. +* This is an upcounter of number of isochronous hi packets discarded +* by Queue Controller. +* +* INPUTS: +* None. +* +* OUTPUTS: +* disCtr - upcounter of number of isochronous hi packets discarded +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoHiDisCtr +( + IN GT_QD_DEV *dev, + OUT GT_U8 *disCtr +); + +/******************************************************************************* +* gqavSetGlobalIsoLoDisCtr +* +* DESCRIPTION: +* This routine set Isochronous Lo queue discard counter. +* This field is updated by hardware when instructed to do so by +* enabling the IsoMonEn bit in Qav Global Status Register Offset 0xD. +* This is an upcounter of number of isochronous lo packets discarded +* by Queue Controller. +* +* INPUTS: +* disCtr - upcounter of number of isochronous lo packets discarded +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavSetGlobalIsoLoDisCtr +( + IN GT_QD_DEV *dev, + IN GT_U8 disCtr +); + +/******************************************************************************* +* gqavGetGlobalIsoLoDisCtr +* +* DESCRIPTION: +* This routine set Isochronous Lo queue discard counter. +* This field is updated by hardware when instructed to do so by +* enabling the IsoMonEn bit in Qav Global Status Register Offset 0xD. +* This is an upcounter of number of isochronous lo packets discarded +* by Queue Controller. +* +* INPUTS: +* None. +* +* OUTPUTS: +* disCtr - upcounter of number of isochronous lo packets discarded +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gqavGetGlobalIsoLoDisCtr +( + IN GT_QD_DEV *dev, + OUT GT_U8 *disCtr +); + +/******************************************************************************* +* gsysSetUseIpMappingTable +* +* DESCRIPTION: +* This API set to use IP Frame Priorities from this table. +* Set GT_TRUE: The IP_FPRI data in this table is used as the frame’s +* initial IP_FPRI use Ip Mappingg table priorities. +* Set GT_FALSE: The IP_FPRI data in this table is ignored. Instead the +* frame’s initial IP_FPRI is generated by using the frame’s IP_QPRI +* as the IP_FPRI’s upper two bits, and the IP_FPRI’s lowest bit comes +* from bit 0 of the frame’s source port’s Default PRI (Port offset 0x07). +* +* INPUTS: +* en - [GT_TRUE] / [GT_FALSE] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetUseIpMappingTable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +); + +/******************************************************************************* +* gsysGetUseIpMappingTable +* +* DESCRIPTION: +* This API get to use IP Frame Priorities from this table. +* Set GT_TRUE: The IP_FPRI data in this table is used as the frame’s +* initial IP_FPRI use Ip Mappingg table priorities. +* Set GT_FALSE: The IP_FPRI data in this table is ignored. Instead the +* frame’s initial IP_FPRI is generated by using the frame’s IP_QPRI +* as the IP_FPRI’s upper two bits, and the IP_FPRI’s lowest bit comes +* from bit 0 of the frame’s source port’s Default PRI (Port offset 0x07). +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - [GT_TRUE] / [GT_FALSE] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetUseIpMappingTable +( + IN GT_QD_DEV *dev, + IN GT_BOOL *en +); + +/******************************************************************************* +* gsysSetIpMappingPrio +* +* DESCRIPTION: +* Set IPv4 and IPv6 Frame Priority Mapping, and +* IPv4 and IPv6 Queue Priority Mapping. +* The ipFpri value is used as the frames initial FPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri (Port offset 0x04) +* is configured to use IP FPri’s. +* The ipQpri value is used as the frame’s initial QPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri and TagIfBoth +* registers (Port offset 0x04) are configured to use IP QPri’s. +* +* INPUTS: +* point - Pointer to the Ip Mapping Table. +* 0 - 0x3f; +* ipFpri - The value is 0 - 7 +* ipQpri - The value is 0 - 3. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetIpMappingPrio +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + IN GT_U8 ipFpri, + IN GT_U8 ipQpri +); + +/******************************************************************************* +* gsysGetIpMappingPrio +* +* DESCRIPTION: +* Get IPv4 and IPv6 Frame Priority Mapping, and +* IPv4 and IPv6 Queue Priority Mapping. +* The ipFpri value is used as the frames initial FPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri (Port offset 0x04) +* is configured to use IP FPri’s. +* The ipQpri value is used as the frame’s initial QPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri and TagIfBoth +* registers (Port offset 0x04) are configured to use IP QPri’s. +* +* INPUTS: +* point - Pointer to the Ip Mapping Table. +* 0 - 0x3f; +* +* OUTPUTS: +* ipFpri - The value is 0 - 7 +* ipQpri - The value is 0 - 3. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gsysGetIpMappingPrio +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + OUT GT_U8 *ipFpri, + OUT GT_U8 *ipQpri +); + +/******************************************************************************* +* gsysReadEeprom +* +* DESCRIPTION: +* Read EEPROM from EEPROM’s address where the EEOp is performed. +* +* INPUTS: +* addr - EEPROM Address. +* +* OUTPUTS: +* data - Data that was read back from the EEPROM. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysReadEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr, + OUT GT_U8 *data +); + +/******************************************************************************* +* gsysWriteEeprom +* +* DESCRIPTION: +* Write EEPROM at the EEPROM’s address where the EEOp is performed. +* +* INPUTS: +* addr - EEPROM Address. +* data - Data to be written to the EEPROM +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysWriteEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr, + IN GT_U8 data +); + +/******************************************************************************* +* gsysRestartEeprom +* +* DESCRIPTION: +* Restart Register Loader execution at the EEPROM’s address where the EEOp +* is performed +* +* INPUTS: +* addr - EEPROM Address. . +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysRestartEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr +); + +/******************************************************************************* +* gsysHaltEeprom +* +* DESCRIPTION: +* Halt (stop executing the EEPROM if its not already stopped) +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysHaltEeprom +( + IN GT_QD_DEV *dev +); + +/******************************************************************************* +* gsysGetStEeprom +* +* DESCRIPTION: +* Get EEPROM status. They are Register Loader Running status and EEPROM +* Write Enable status +* runSt is GT_TRUE: Register Loader Running, whenever the register loader +* is busy executing the instructions contained in the EEPROM. +* writeEn is GT_TRUE: EEPROM Write Enable, that indicates that writing to +* the EEPROM is possible. +* writeEn is GT_FALSE: the Write EEPROM EEOp above will not do anything. +* This reflects the value of the EE_WE configuration pin after Reset. +* +* INPUTS: +* None. +* +* OUTPUTS: +* runSt - [GT_TRUE] / [GT_FALSE) +* writeEn - [GT_TRUE] / [GT_FALSE) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetStEeprom +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *writeEn, + OUT GT_BOOL *runSt +); + +/******************************************************************************* +* gsysSetScratchMiscCtrl +* +* DESCRIPTION: +* Set Scratch and Misc control data to the Scratch and Misc Control register. +* The register of Scratch and Misc control are. +* Scratch Byte 0 +* Scratch Byte 1 +* GPIO Configuration +* Reserved for future use +* GPIO Direction +* GPIO Data +* CONFIG Data 0 +* CONFIG Data 1 +* CONFIG Data 2 +* CONFIG Data 3 +* SyncE & TAICLK125’s Drive +* P5’s & CLK125’s Clock Drive +* P6’s Clock Drive +* EEPROM Pad drive +* +* INPUTS: +* point - Pointer to the Scratch and Misc. Control register. +* data - Scratch and Misc. Control data written to the register +* pointed to by the point above. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetScratchMiscCtrl +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + IN GT_U8 data +); + +/******************************************************************************* +* gsysGetScratchMiscCtrl +* +* DESCRIPTION: +* Get Scratch and Misc control data from the Scratch and Misc Control register. +* The register of Scratch and Misc control are. +* Scratch Byte 0 +* Scratch Byte 1 +* GPIO Configuration +* Reserved for future use +* GPIO Direction +* GPIO Data +* CONFIG Data 0 +* CONFIG Data 1 +* CONFIG Data 2 +* CONFIG Data 3 +* SyncE & TAICLK125’s Drive +* P5’s & CLK125’s Clock Drive +* P6’s Clock Drive +* EEPROM Pad drive + +* +* INPUTS: +* point - Pointer to the Scratch and Misc. Control register. +* +* OUTPUTS: +* data - Scratch and Misc. Control data read from the register +* pointed to by the point above. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetScratchMiscCtrl +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + OUT GT_U8 *data +); + +/******************************************************************************* +* gsysSetScratchBits +* +* DESCRIPTION: +* Set bits to the Scratch and Misc Control register . +* These bits are 100% available to software for whatever purpose desired. +* These bits do not connect to any hardware function. +* +* INPUTS: +* scritch - written bits. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetScratchBits +( + IN GT_QD_DEV *dev, + IN GT_U16 scratch +); + +/******************************************************************************* +* gsysGetScratchBits +* +* DESCRIPTION: +* Get bits from the Scratch and Misc Control register . +* These bits are 100% available to software for whatever purpose desired. +* These bits do not connect to any hardware function. +* +* INPUTS: +* None. +* +* OUTPUTS: +* scritch - read bits. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetScratchBits +( + IN GT_QD_DEV *dev, + OUT GT_U16 *scratch +); + +/******************************************************************************* +* gsysSetGpioConfigMod +* +* DESCRIPTION: +* Set bits to the Scratch and Misc Control register +* to configure GPIO mode. +* The bits are shared General Purpose Input Output mode Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* mode - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioConfigMod +( + IN GT_QD_DEV *dev, + IN GT_U32 mode +); + +/******************************************************************************* +* gsysGetGpioConfigMod +* +* DESCRIPTION: +* Get mode from the Scratch and Misc Control register . +* The bits are shared General Purpose Input Output mode Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioConfigMod +( + IN GT_QD_DEV *dev, + IN GT_U32 *mode +); + +/******************************************************************************* +* gsysSetGpioDirection +* +* DESCRIPTION: +* Set Gpio direction to the Scratch and Misc Control register . +* The bits are used to control the direction of GPIO[6:0]. +* When a GPIO’s bit is set to a one that GPIO will become an input. When a +* GPIO’s bit is cleared to a zero that GPIO will become an output +* General Purpose Input Output direction bits are: +* Bit 6 - GT_GPIO_BIT_6 +* Bit 5 - GT_GPIO_BIT_5 +* Bit 4 - GT_GPIO_BIT_4 +* Bit 3 - GT_GPIO_BIT_3 +* Bit 2 - GT_GPIO_BIT_2 +* Bit 1 - GT_GPIO_BIT_1 +* Bit 0 - GT_GPIO_BIT_0 +* +* INPUTS: +* dir - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioDirection +( + IN GT_QD_DEV *dev, + IN GT_U32 dir +); + +/******************************************************************************* +* gsysGetGpioDirection +* +* DESCRIPTION: +* get Gpio direction from the Scratch and Misc Control register . +* The bits are used to control the direction of GPIO[6:0]. +* When a GPIO’s bit is set to a one that GPIO will become an input. When a +* GPIO’s bit is cleared to a zero that GPIO will become an output +* General Purpose Input Output direction bits are: +* Bit 6 - GT_GPIO_BIT_6 +* Bit 5 - GT_GPIO_BIT_5 +* Bit 4 - GT_GPIO_BIT_4 +* Bit 3 - GT_GPIO_BIT_3 +* Bit 2 - GT_GPIO_BIT_2 +* Bit 1 - GT_GPIO_BIT_1 +* Bit 0 - GT_GPIO_BIT_0 +* +* INPUTS: +* None. +* +* OUTPUTS: +* dir - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioDirection +( + IN GT_QD_DEV *dev, + OUT GT_U32 *dir +); + +/******************************************************************************* +* gsysSetGpioData +* +* DESCRIPTION: +* Set Gpio data to the Scratch and Misc Control register . +* When a GPIO’s bit is set to be an input, data written to this bit will go +* to a holding register but will not appear on the pin nor in this register. +* Reads of this register will return the actual, real-time, data that is +* appearing on the GPIO’s pin. +* When a GPIO’s bit is set to be an output, data written to this bit will go +* to a holding register and will appear on the GPIO’s pin. Reads of this register +* will return the actual, real-time, data that is appearing on the GPIO’s pin +* (which in this case should be the data written, but if its isn’t that would +* be an indication of a conflict). +* When a pin’s direction changes from input to output, the data last written +* to the holding register appears on the GPIO’s pin +* General Purpose Input Output data bits are: +* Bit 6 - GT_GPIO_BIT_6 +* Bit 5 - GT_GPIO_BIT_5 +* Bit 4 - GT_GPIO_BIT_4 +* Bit 3 - GT_GPIO_BIT_3 +* Bit 2 - GT_GPIO_BIT_2 +* Bit 1 - GT_GPIO_BIT_1 +* Bit 0 - GT_GPIO_BIT_0 +* +* INPUTS: +* data - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioData +( + IN GT_QD_DEV *dev, + IN GT_U32 data +); + +/******************************************************************************* +* gsysGetGpioData +* +* DESCRIPTION: +* get Gpio data to the Scratch and Misc Control register . +* When a GPIO’s bit is set to be an input, data written to this bit will go +* to a holding register but will not appear on the pin nor in this register. +* Reads of this register will return the actual, real-time, data that is +* appearing on the GPIO’s pin. +* When a GPIO’s bit is set to be an output, data written to this bit will go +* to a holding register and will appear on the GPIO’s pin. Reads of this register +* will return the actual, real-time, data that is appearing on the GPIO’s pin +* (which in this case should be the data written, but if its isn’t that would +* be an indication of a conflict). +* When a pin’s direction changes from input to output, the data last written +* to the holding register appears on the GPIO’s pin +* General Purpose Input Output data bits are: +* Bit 6 - GT_GPIO_BIT_6 +* Bit 5 - GT_GPIO_BIT_5 +* Bit 4 - GT_GPIO_BIT_4 +* Bit 3 - GT_GPIO_BIT_3 +* Bit 2 - GT_GPIO_BIT_2 +* Bit 1 - GT_GPIO_BIT_1 +* Bit 0 - GT_GPIO_BIT_0 +* +* INPUTS: +* None. +* +* OUTPUTS: +* data - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioData +( + IN GT_QD_DEV *dev, + IN GT_U32 *data +); + +/******************************************************************************* +* gsysGetConfigData +* +* DESCRIPTION: +* Get Reset Configuration Pin Data 0-3. +* These registers return the values observed after a hardware Reset on the +* listed CONFIG data listed below. +* Config data 0: +* Bit Config Pin's Primary Name +* 0 USER[0] P6_OUTD[5] +* 1 USER[1] P6_OUTD[6] +* 2 USER[2] P6_OUTD[7] +* 3 ADDR[0] P5_OUTD[0] +* 4 ADDR[1] P5_OUTD[5] +* 5 ADDR[2] P5_OUTD[6] +* 6 ADDR]3] P5_OUTD[7] +* 7 ADDR[4] P5_OUTD[1] +* Config data 1: +* 0 LED_SEL[0] P1_LED +* 1 LED_SEL[1] P2_LED +* 2 4COL P3_LED +* 3 NormCx P4_LED +* 4 Jumbo P0_LED +* 5 EE_WE EE_CS/C2_LED +* 6 FD_FLOW EE_CLK/C1_LED +* 7 HD_FLOW EE_DIN/C0_LED +* Config data 2: +* 0 P5_MODE[0] P5_OUTD[2] +* 1 P5_MODE[1] P5_OUTD[3] +* 2 P5_MODE[2] P5_OUTD[4] +* 3 Reserved for future use +* 4 P6_MODE[0] P6_OUTD[2] +* 5 P6_MODE[1] P6_OUTD[3] +* 6 P6_MODE[2] P6_OUTD[4] +* 7 Reserved for future use +* Config data 3: +* 0 RMU_MODE[0] P6_OUTD[0] +* 1 RMU_MODE[1] P6_OUTD[1] +* 2 S_VDDOS[0] PTP_TRIG +* 3 CLK125EN CLK125 +* 4 P5_VDDOS[0] P5_GTXCLK +* 5 P5_VDDOS[1] P5_OUTEN +* 6 P6_VDDOS[0] P5_GTXCLK +* 7 P6_VDDOS[1] P6_OUTEN +* INPUTS: +* None. +* +* OUTPUTS: +* cfgDat - GT_CONFIG_DTTA +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetConfigData +( + IN GT_QD_DEV *dev, + OUT GT_CONFIG_DATA *cfgData +); + +/******************************************************************************* +* gsysSetSyncETai +* +* DESCRIPTION: +* Set SyncE and Tai to the Scratch and Misc. Control register . +* +* INPUTS: +* zpr - ZPR for SyncE and TAI +* znr - ZNR for SyncE and TAI +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetSyncETai +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +); + +/******************************************************************************* +* gsysGetSyncETai +* +* DESCRIPTION: +* Get SyncE and Tai from the Scratch and Misc Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for SyncE and TAI +* znr - ZNR for SyncE and TAI* +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetSyncETai +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +); + +/******************************************************************************* +* gsysSetP6_Clock +* +* DESCRIPTION: +* Set P6_clock to the Scratch and Misc Control register . +* +* INPUTS: +* zpr - ZPR for P6_Clock +* znr - ZNR for P6_Clock +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetP6_Clock +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +); + +/******************************************************************************* +* gsysGetP6_Clock +* +* DESCRIPTION: +* Get P6_clock from the Scratch and Misc Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for P6_Clock +* znr - ZNR for P6_Clock +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetP6_Clock +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +); + +/******************************************************************************* +* gsysSetP5_Clock +* +* DESCRIPTION: +* Set P5_clock to the Scratch and Misc Control register . +* +* INPUTS: +* zpr - ZPR for P5_Clock +* znr - ZNR for P5_Clock +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetP5_Clock +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +); + +/******************************************************************************* +* gsysGetP5_Clock +* +* DESCRIPTION: +* Get P5_clock from the Scratch and Misc Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for P5_Clock +* znr - ZNR for P5_Clock +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetP5_Clock +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +); + +/******************************************************************************* +* gsysSetEEPROM +* +* DESCRIPTION: +* Set EEPROM cycle to the Scratch and Misc Control register . +* +* INPUTS: +* dsm - DSM for EEPROM cycle +* zpr - ZPR for EEPROM cycle +* znr - ZNR for EEPROM cycle +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetEEPROM +( + IN GT_QD_DEV *dev, + IN GT_U8 dsm, + IN GT_U8 zpr, + IN GT_U8 znr +); + +/******************************************************************************* +* gsysGetEEPROM +* +* DESCRIPTION: +* Get EEPROM cycle to the Scratch and Misc Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* dsm - DSM for EEPROM cycle +* zpr - ZPR for EEPROM cycle +* znr - ZNR for EEPROM cycle +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetEEPROM +( + IN GT_QD_DEV *dev, + OUT GT_U8 *dsm, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +); + + +/* gtAdvVct.c */ + +/******************************************************************************* +* gvctGetAdvCableDiag +* +* DESCRIPTION: +* This routine perform the advanced virtual cable test for the requested +* port and returns the the status per MDI pair. +* +* INPUTS: +* port - logical port number. +* mode - advance VCT mode (either First Peak or Maximum Peak) +* +* OUTPUTS: +* cableStatus - the port copper cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Internal Gigabit Phys in 88E6165 family and 88E6351 family devices +* are supporting this API. +* +*******************************************************************************/ +GT_STATUS gvctGetAdvCableDiag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ADV_VCT_MODE mode, + OUT GT_ADV_CABLE_STATUS *cableStatus +); + +/******************************************************************************* +* gvctGetAdvExtendedStatus +* +* DESCRIPTION: +* This routine retrieves extended cable status, such as Pair Poloarity, +* Pair Swap, and Pair Skew. Note that this routine will be success only +* if 1000Base-T Link is up. +* DSP based cable length is also provided. +* +* INPUTS: +* dev - pointer to GT driver structure returned from mdLoadDriver +* port - logical port number. +* +* OUTPUTS: +* extendedStatus - the extended cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Supporting Device list: +* 88E1111, 88E1112, 88E1141~6, 88E1149, and Internal Gigabit Phys +* in 88E6165 family and 88E6351 family devices +* +*******************************************************************************/ +GT_STATUS gvctGetAdvExtendedStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ADV_EXTENDED_STATUS *extendedStatus +); + +#ifdef __cplusplus +} +#endif + +#endif /* __msApi_h */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiTypes.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiTypes.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiTypes.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiTypes.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,105 @@ +/* + * Copyright 2002, Marvell International Ltd. + * + * THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC. + * NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT + * OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE + * DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. + * THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS, IMPLIED + * OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. + */ + +/* + * FILENAME: $Workfile: mv_types.h $ + * REVISION: $Revision: 3 $ + * LAST UPDATE: $Modtime: 12/24/02 5:37p $ + * + * DESCRIPTION: + * This file defines common data types used on Host and NetGX sides. + */ + + +#ifndef MV_TYPES_H +#define MV_TYPES_H + + +/* general */ + +#undef IN +#define IN +#undef OUT +#define OUT +#undef INOUT +#define INOUT + + +#ifndef NULL +#define NULL ((void*)0) +#endif + +typedef void GT_VOID; +typedef char GT_8; +typedef short GT_16; +typedef long GT_32; + +typedef unsigned char GT_U8; +typedef unsigned short GT_U16; +typedef unsigned long GT_U32; +typedef unsigned int GT_UINT; + +typedef union { + GT_U8 c[8]; + GT_U16 s[4]; + GT_U32 l[2]; +} GT_U64; + + +typedef enum { + GT_FALSE = 0, + GT_TRUE = 1 +} GT_BOOL; + +typedef void (*GT_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef unsigned int (*GT_INTFUNCPTR) (void); /* ptr to function returning int */ + + +/* module state */ +typedef enum { + GT_STATE_NONE = 0, /* Uninitialized */ + GT_STATE_IDLE, /* Initialized, but not started (or stopped) */ + GT_STATE_ACTIVE /* Started */ +} GT_STATE; + + +#define GT_ETHERNET_HEADER_SIZE (6) + +typedef struct +{ + GT_U8 arEther[GT_ETHERNET_HEADER_SIZE]; +}GT_ETHERADDR; + +/* This macro checks for a multicast mac address */ +#define GT_IS_MULTICAST_MAC(mac) ((mac.arEther[0] & 0x1) == 1) + + +/* This macro checks for an broadcast mac address */ +#define GT_IS_BROADCAST_MAC(mac) (((mac).arEther[0] == 0xFF) && ((mac).arEther[1] == 0xFF) && ((mac).arEther[2] == 0xFF) && ((mac).arEther[3] == 0xFF) && ((mac).arEther[4] == 0xFF) && ((mac).arEther[5] == 0xFF)) + + +/* status / error codes */ +typedef int GT_STATUS; + +#define GT_ERROR (-1) +#define GT_OK (0x00) /* Operation succeeded */ +#define GT_FAIL (0x01) /* Operation failed */ +#define GT_BAD_VALUE (0x02) /* Illegal value (general) */ +#define GT_BAD_PARAM (0x04) /* Illegal parameter in function called */ +#define GT_NOT_FOUND (0x0B) /* Item not found */ +#define GT_NO_MORE (0x0C) /* No more items found */ +#define GT_NO_SUCH (0x0D) /* No such item */ +#define GT_TIMEOUT (0x0E) /* Time Out */ +#define GT_NOT_SUPPORTED (0x10) /* This request is not support */ +#define GT_ALREADY_EXIST (0x1B) /* Tried to create existing item */ +#define GT_BAD_CPU_PORT (0x20) /* Input CPU Port is not valid physical port number */ + +#endif /* MV_TYPES_H */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiWince.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiWince.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/Include/msApiWince.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/Include/msApiWince.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,556 @@ +#include + +/******************************************************************************** +* msApiWince.h +* +* DESCRIPTION: +* Wince Application need to include only this header file. +* +* DEPENDENCIES: None +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __msApiFunc_h +#define __msApiFunc_h + +#include "msApiDefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef GT_STATUS (*FGT_PRT_ATUSIZE)(ATU_SIZE); +typedef GT_STATUS (*FGT_PRT_U32_U32)(GT_U32*,GT_U32*); +typedef GT_STATUS (*FGT_VALUE_U32)(GT_U32); +typedef GT_STATUS (*FGT_PTR_U32)(GT_U32*); +typedef GT_STATUS (*FGT_PTR_U16)(GT_U16*); +typedef GT_STATUS (*FGT_PTR_U32_U32_U32)(GT_U32,GT_U32,GT_U32*); +typedef GT_STATUS (*FGT_PTR_ATUENTRY)(GT_ATU_ENTRY*); +typedef GT_STATUS (*FGT_PTR_ATUENTRY_BOOL)(GT_ATU_ENTRY*, GT_BOOL*); +typedef GT_STATUS (*FGT_VALUE_FLUSHCMD)(GT_FLUSH_CMD); +typedef GT_STATUS (*FGT_PTR_ETHERADDR)(GT_ETHERADDR*); +typedef GT_STATUS (*FGT_PTR_BOOL)(GT_BOOL*); +typedef GT_STATUS (*FGT_VALUE_BOOL)(GT_BOOL); +typedef GT_STATUS (*FGT_VALUE_PORT_STPSTATE)(GT_LPORT,GT_PORT_STP_STATE); +typedef GT_STATUS (*FGT_PTR_PORT_STPSTATE)(GT_LPORT,GT_PORT_STP_STATE*); +typedef GT_STATUS (*FGT_VALUE_PORT_EGRESSMODE)(GT_LPORT,GT_EGRESS_MODE); +typedef GT_STATUS (*FGT_PTR_PORT_EGRESSMODE)(GT_LPORT,GT_EGRESS_MODE*); +typedef GT_STATUS (*FGT_VALUE_PORT_BOOL)(GT_LPORT,GT_BOOL); +typedef GT_STATUS (*FGT_PTR_PORT_BOOL)(GT_LPORT,GT_BOOL*); +typedef GT_STATUS (*FGT_VALUE_PORT_PORTS_U8)(GT_LPORT,GT_LPORT*,GT_U8); +typedef GT_STATUS (*FGT_PTR_PORT_PORTS_U8)(GT_LPORT,GT_LPORT*,GT_U8*); +typedef GT_STATUS (*FGT_VALUE_PORT_U16)(GT_LPORT,GT_U16); +typedef GT_STATUS (*FGT_PTR_PORT_U16)(GT_LPORT,GT_U16*); +typedef GT_STATUS (*FGT_VALUE_PORT_AUTOMODE)(GT_LPORT,GT_PHY_AUTO_MODE); + +typedef GT_STATUS (*FGT_VALUE_PORT)(GT_LPORT); +typedef GT_STATUS (*FGT_VALUE_U8)(GT_U8); +typedef GT_STATUS (*FGT_PTR_U8)(GT_U8*); +typedef GT_STATUS (*FGT_VALUE_PORT_U8)(GT_LPORT,GT_U8); +typedef GT_STATUS (*FGT_PTR_PORT_U8)(GT_LPORT,GT_U8*); +typedef GT_STATUS (*FGT_VALUE_PORT_INGRESSMODE)(GT_LPORT,GT_INGRESS_MODE); +typedef GT_STATUS (*FGT_PTR_PORT_INGRESSMODE)(GT_LPORT,GT_INGRESS_MODE*); +typedef GT_STATUS (*FGT_VALUE_PORT_MCRATE)(GT_LPORT,GT_MC_RATE); +typedef GT_STATUS (*FGT_PTR_PORT_MCRATE)(GT_LPORT,GT_MC_RATE*); +typedef GT_STATUS (*FGT_VALUE_CTRMODE)(GT_CTR_MODE); +typedef GT_STATUS (*FGT_PTR_CTRMODE)(GT_CTR_MODE*); +typedef GT_STATUS (*FGT_VOID)(void); +typedef GT_STATUS (*FGT_PTR_PORT_PORTSTAT)(GT_LPORT,GT_PORT_STAT*); +typedef GT_STATUS (*FGT_VALUE_U8_U8)(GT_U8,GT_U8); +typedef GT_STATUS (*FGT_PTR_U8_U8)(GT_U8,GT_U8*); +typedef GT_STATUS (*FGT_PTR_CONFIG_INFO)(GT_SYS_CONFIG*,GT_SYS_INFO*); +typedef GT_STATUS (*FGT_PTR_VERSION)(GT_VERSION*); +typedef GT_STATUS (*FGT_PTR_REGISTER)(BSP_FUNCTIONS*); +typedef GT_STATUS (*FGT_PTR_INT_HANDLER)(FGT_INT_HANDLER*); + +typedef GT_STATUS (*FGT_PTR_U32_U32_U16)(GT_U32,GT_U32,GT_U16); + + +extern FGT_PRT_ATUSIZE gfdbSetAtuSize; +extern FGT_PRT_U32_U32 gfdbGetAgingTimeRange; +extern FGT_VALUE_U32 gfdbSetAgingTimeout; +extern FGT_PTR_U32 gfdbGetAtuDynamicCount; +extern FGT_PTR_ATUENTRY gfdbGetAtuEntryFirst; +extern FGT_PTR_ATUENTRY gfdbGetAtuEntryNext; +extern FGT_PTR_ATUENTRY_BOOL gfdbFindAtuMacEntry; +extern FGT_VALUE_FLUSHCMD gfdbFlush; +extern FGT_PTR_ATUENTRY gfdbAddMacEntry; //liane +extern FGT_PTR_ETHERADDR gfdbDelMacEntry; +extern FGT_VALUE_BOOL gfdbLearnEnable; +extern FGT_VALUE_BOOL gstpSetMode; +extern FGT_VALUE_PORT_STPSTATE gstpSetPortState; +extern FGT_PTR_PORT_STPSTATE gstpGetPortState; +extern FGT_VALUE_PORT_EGRESSMODE gprtSetEgressMode; +extern FGT_PTR_PORT_EGRESSMODE gprtGetEgressMode; +extern FGT_VALUE_PORT_BOOL gprtSetVlanTunnel; +extern FGT_PTR_PORT_BOOL gprtGetVlanTunnel; +extern FGT_VALUE_PORT_PORTS_U8 gvlnSetPortVlanPorts; +extern FGT_PTR_PORT_PORTS_U8 gvlnGetPortVlanPorts; +extern FGT_VALUE_PORT_BOOL gvlnSetPortUserPriLsb; +extern FGT_PTR_PORT_BOOL gvlnGetPortUserPriLsb; +extern FGT_VALUE_PORT_U16 gvlnSetPortVid; +extern FGT_PTR_PORT_U16 gvlnGetPortVid; +extern FGT_VALUE_U32 eventSetActive; +extern FGT_PTR_U16 eventGetIntStatus; +extern FGT_VALUE_PORT gprtPhyReset; +extern FGT_VALUE_PORT_BOOL gprtSetPortLoopback; +extern FGT_VALUE_PORT_BOOL gprtSetPortSpeed; +extern FGT_VALUE_PORT_BOOL gprtPortAutoNegEnable; +extern FGT_VALUE_PORT_BOOL gprtPortPowerDown; +extern FGT_VALUE_PORT gprtPortRestartAutoNeg; +extern FGT_VALUE_PORT_BOOL gprtSetPortDuplexMode; +extern FGT_VALUE_PORT_AUTOMODE gprtSetPortAutoMode; +extern FGT_VALUE_PORT_BOOL gprtSetPause; +extern FGT_VALUE_PORT_U16 gprtPhyIntEnable; +extern FGT_PTR_PORT_U16 gprtGetPhyIntStatus; +extern FGT_PTR_U16 gprtGetPhyIntPortSummary; +extern FGT_VALUE_PORT_BOOL gprtSetForceFc; +extern FGT_PTR_PORT_BOOL gprtGetForceFc; +extern FGT_VALUE_PORT_BOOL gprtSetTrailerMode; +extern FGT_PTR_PORT_BOOL gprtGetTrailerMode; +extern FGT_VALUE_PORT_INGRESSMODE gprtSetIngressMode; +extern FGT_PTR_PORT_INGRESSMODE gprtGetIngressMode; +extern FGT_VALUE_PORT_MCRATE gprtSetMcRateLimit; +extern FGT_PTR_PORT_MCRATE gprtGetMcRateLimit; +extern FGT_VALUE_CTRMODE gprtSetCtrMode; +extern FGT_VOID gprtClearAllCtr; +extern FGT_PTR_PORT_PORTSTAT gprtGetPortCtr; +extern FGT_PTR_PORT_BOOL gprtGetPartnerLinkPause; +extern FGT_PTR_PORT_BOOL gprtGetSelfLinkPause; +extern FGT_PTR_PORT_BOOL gprtGetResolve; +extern FGT_PTR_PORT_BOOL gprtGetLinkState; +extern FGT_PTR_PORT_BOOL gprtGetPortMode; +extern FGT_PTR_PORT_BOOL gprtGetPhyMode; +extern FGT_PTR_PORT_BOOL gprtGetDuplex; +extern FGT_PTR_PORT_BOOL gprtGetSpeed; +extern FGT_VALUE_PORT_U8 gcosSetPortDefaultTc; +extern FGT_VALUE_PORT_BOOL gqosSetPrioMapRule; +extern FGT_PTR_PORT_BOOL gqosGetPrioMapRule; +extern FGT_VALUE_PORT_BOOL gqosIpPrioMapEn; +extern FGT_PTR_PORT_BOOL gqosGetIpPrioMapEn; +extern FGT_VALUE_PORT_BOOL gqosUserPrioMapEn; +extern FGT_PTR_PORT_BOOL gqosGetUserPrioMapEn; +extern FGT_PTR_U8_U8 gcosGetUserPrio2Tc; +extern FGT_VALUE_U8_U8 gcosSetUserPrio2Tc; +extern FGT_PTR_U8_U8 gcosGetDscp2Tc; +extern FGT_VALUE_U8_U8 gcosSetDscp2Tc; +extern FGT_PTR_CONFIG_INFO sysConfig; +extern FGT_VOID sysEnable; +extern FGT_VOID gsysSwReset; +extern FGT_VALUE_BOOL gsysSetDiscardExcessive; +extern FGT_PTR_BOOL gsysGetDiscardExcessive; +extern FGT_VALUE_BOOL gsysSetSchedulingMode; +extern FGT_PTR_BOOL gsysGetSchedulingMode; +extern FGT_VALUE_BOOL gsysSetMaxFrameSize; +extern FGT_PTR_BOOL gsysGetMaxFrameSize; +extern FGT_VOID gsysReLoad; +extern FGT_VALUE_BOOL gsysSetWatchDog; +extern FGT_PTR_BOOL gsysGetWatchDog; +extern FGT_PTR_ETHERADDR gsysSetDuplexPauseMac; +extern FGT_PTR_ETHERADDR gsysGetDuplexPauseMac; +extern FGT_VALUE_BOOL gsysSetPerPortDuplexPauseMac; +extern FGT_PTR_BOOL gsysGetPerPortDuplexPauseMac; +extern FGT_PTR_U32_U32_U32 gsysReadMiiReg; +extern FGT_PTR_VERSION gtVersion; +extern FGT_PTR_REGISTER gtRegister; + +extern FGT_PTR_U32_U32_U16 gsysWriteMiiReg; + +/* + * This function will get the all the MS APIs and assign to local function pointers. + */ +int qdGetMSApiFunc(); + +GT_U32 gtStrlen +( + IN const void * source +); + +//***************************************************************************** +// I O C T L S +//***************************************************************************** +#include "windev.h" + +typedef struct _GT_IOCTL_PARAM +{ + union + { + GT_LPORT portList[8]; + GT_LPORT port; + GT_U8 u8Data; + GT_U16 u16Data; + GT_U32 u32Data; + GT_BOOL boolData; + + GT_CTR_MODE ctrMode; + GT_PORT_STP_STATE stpState; + GT_EGRESS_MODE egressMode; + GT_INGRESS_MODE ingressMode; + GT_MC_RATE mcRate; + GT_PORT_STAT portStat; + ATU_SIZE atuSize; + GT_FLUSH_CMD flushCmd; + + GT_ATU_ENTRY atuEntry; + GT_ETHERADDR etherAddr; + GT_SYS_CONFIG sysConfig; + GT_SYS_INFO sysInfo; + + } FirstParam; + + union + { + GT_LPORT port; + GT_LPORT portList[8]; + GT_U8 u8Data; + GT_U16 u16Data; + GT_U32 u32Data; + GT_BOOL boolData; + GT_PORT_STP_STATE stpState; + GT_EGRESS_MODE egressMode; + GT_INGRESS_MODE ingressMode; + GT_MC_RATE mcRate; + + GT_PORT_STAT portStat; + + GT_PHY_AUTO_MODE phyAutoMode; + + } SecondParam; + + union + { + GT_U8 u8Data; + GT_U16 u16Data; + GT_U32 u32Data; + + } ThirdParam; + +} GT_IOCTL_PARAM, *PGT_IOCTL_PARAM; + +#define GET_FUNC_FROM_CTL_CODE(_ioctl) ((_ioctl>>2) & 0xFFF) + +/* + Microsoft allows for us to use 0x800 ~ 0xFFF + So, our program is using 6 bits for function group, + and 6 bits for each function. +*/ +#define SUB_FUNC_MASK 0xFC0 +#define SYS_CFG_FUNC_MASK (1 << 6) | 0x800 +#define SYS_CTRL_FUNC_MASK (2 << 6) | 0x800 +#define FDB_FUNC_MASK (3 << 6) | 0x800 +#define VLAN_FUNC_MASK (4 << 6) | 0x800 +#define STP_FUNC_MASK (5 << 6) | 0x800 +#define PORT_CTRL_FUNC_MASK (6 << 6) | 0x800 +#define PORT_STATUS_FUNC_MASK (7 << 6) | 0x800 +#define PORT_STATS_FUNC_MASK (8 << 6) | 0x800 +#define QOS_FUNC_MASK (9 << 6) | 0x800 +#define PHY_CTRL_FUNC_MASK (10 << 6) | 0x800 +#define SYS_EVENT_FUNC_MASK (11 << 6) | 0x800 +#define PHY_INT_FUNC_MASK (12 << 6) | 0x800 + +/* + Functions for SYS Configuration +*/ +#define IOCTL_sysConfig \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CFG_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysReadMiiReg \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CFG_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysWriteMiiReg \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CFG_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gtVersion \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CFG_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for ATU +*/ +#define IOCTL_gfdbSetAtuSize \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbGetAgingTimeRange \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbSetAgingTimeout \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbGetAtuDynamicCount \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbGetAtuEntryFirst \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbGetAtuEntryNext \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbFindAtuMacEntry \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbFlush \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbAddMacEntry \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 8, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbDelMacEntry \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 9, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gfdbLearnEnable \ + CTL_CODE(FILE_DEVICE_NETWORK , FDB_FUNC_MASK + 10, METHOD_BUFFERED, FILE_ANY_ACCESS) + + +/* + Functions for STP +*/ +#define IOCTL_gstpSetMode \ + CTL_CODE(FILE_DEVICE_NETWORK , STP_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gstpSetPortState \ + CTL_CODE(FILE_DEVICE_NETWORK , STP_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gstpGetPortState \ + CTL_CODE(FILE_DEVICE_NETWORK , STP_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for VLAN +*/ +#define IOCTL_gprtSetEgressMode \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetEgressMode \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetVlanTunnel \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetVlanTunnel \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnSetPortVlanPorts \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnGetPortVlanPorts \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnSetPortUserPriLsb \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnGetPortUserPriLsb \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnSetPortVid \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 8, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gvlnGetPortVid \ + CTL_CODE(FILE_DEVICE_NETWORK , VLAN_FUNC_MASK + 9, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for System Event +*/ +#define IOCTL_eventSetActive \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_EVENT_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_eventGetIntStatus \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_EVENT_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for Phy Control +*/ +#define IOCTL_gprtPhyReset \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetPortLoopback \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetPortSpeed \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtPortAutoNegEnable \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtPortPowerDown \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtPortRestartAutoNeg \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetPortDuplexMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetPortAutoMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetPause \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_CTRL_FUNC_MASK + 8, METHOD_BUFFERED, FILE_ANY_ACCESS) + + +/* + Functions for Phy Interrupt +*/ +#define IOCTL_gprtPhyIntEnable \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_INT_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetPhyIntStatus \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_INT_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetPhyIntPortSummary \ + CTL_CODE(FILE_DEVICE_NETWORK , PHY_INT_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for Port Control +*/ +#define IOCTL_gprtSetForceFc \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetForceFc \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetTrailerMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetTrailerMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetIngressMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetIngressMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtSetMcRateLimit \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetMcRateLimit \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_CTRL_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + + +/* + Functions for Port Statistics +*/ +#define IOCTL_gprtSetCtrMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATS_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtClearAllCtr \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATS_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetPortCtr \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATS_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for Port Status +*/ +#define IOCTL_gprtGetPartnerLinkPause \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetSelfLinkPause \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetResolve \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetLinkState \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetPortMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetPhyMode \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetDuplex \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gprtGetSpeed \ + CTL_CODE(FILE_DEVICE_NETWORK , PORT_STATUS_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +/* + Functions for QoS Mapping +*/ +#define IOCTL_gcosSetPortDefaultTc \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosSetPrioMapRule \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosGetPrioMapRule \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosIpPrioMapEn \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosGetIpPrioMapEn \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosUserPrioMapEn \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gqosGetUserPrioMapEn \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gcosGetUserPrio2Tc \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gcosSetUserPrio2Tc \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 8, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gcosGetDscp2Tc \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 9, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gcosSetDscp2Tc \ + CTL_CODE(FILE_DEVICE_NETWORK , QOS_FUNC_MASK + 10, METHOD_BUFFERED, FILE_ANY_ACCESS) + + +/* + Functions for Sys Control +*/ +#define IOCTL_gsysSwReset \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 0, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetDiscardExcessive \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 1, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetDiscardExcessive \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 2, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetSchedulingMode \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 3, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetSchedulingMode \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 4, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetMaxFrameSize \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 5, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetMaxFrameSize \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 6, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysReLoad \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 7, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetWatchDog \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 8, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetWatchDog \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 9, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetDuplexPauseMac \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 10, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetDuplexPauseMac \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 11, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysSetPerPortDuplexPauseMac \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 12, METHOD_BUFFERED, FILE_ANY_ACCESS) + +#define IOCTL_gsysGetPerPortDuplexPauseMac \ + CTL_CODE(FILE_DEVICE_NETWORK , SYS_CTRL_FUNC_MASK + 13, METHOD_BUFFERED, FILE_ANY_ACCESS) + + +#ifdef __cplusplus +} +#endif + +#endif diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/mvCompVer.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/mvCompVer.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/mvCompVer.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/mvCompVer.txt 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/README u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/README --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/README 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/README 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,393 @@ + + DSDT Release version 2.8b + ========================== + +Table of Content: +----------------- +1) Release History +2) Source Code Organization +3) General Introduction +4) HOW TO - Build qdDrv.o for vxWorks +5) HOW TO - Build qdDrv.lib for WinCE +6) HOW TO - Build qdDrv.o for Linux +7) Changes +8) New APIs + + +1) Release History +------------------ +DSDT2.8b.zip - Oct. 2009 Added GPL and BSD license options to copyright header. + +DSDT2.8a.zip - Mar. 2009. Bug fixes. + 1. Bug fixes for SERDES interface configuration. + 2. VCT fixes for 88E616x, 88E617x, 88E635x internal PHYs. + 3. Auto Scan issues on 88E617x, 88E635x family. + 4. msgIdStartBit in GT_PTP_CONFIG is obsolete. + 5. TRUNK ATU entries for 88E616x, 88E617x, 88E635x are configured properly. + 6. Port mapping macros with GT_USE_SIMPLE_PORT_MAPPING are casted properly. + 7. Deleted to support 6095 family for Ingress Rate Limit with Flow control. + 8. Deleted unused definition in GT_QPRI_TBL_ENTRY. + 9. Device definition for GT_88E6124, GT_88E6325, GT_88E6371 has been corrected to + GT_88E6125, GT_88E6321, GT_88E6350, respectively. + +DSDT2.8.zip - Nov. 2008. added support for 88E6351 family (88E6351,88E6175,88E6124) + 1. New APIs are added to support new devices. + +DSDT2.7a.zip - March. 2008. + 1. Fixed known bugs. + 2. Enhanced some of the APIs. + +DSDT2.7.zip - May. 2007. added support for 88E6165 family (88E6123,88E6125,88E6140,88E6161) + 1. New APIs are added to support new devices. + 2. Bug fix + GT_PIRL2_DATA structure includes GT_PIRL_COUNT_MODE enum type, + which should be GT_PIRL2_COUNT_MODE. + 88E6083 support Static Management frame. + gprtSetForwardUnknown deals with wrong bit. + 3. Removed Diag program that make user confused with missing files. + +DSDT2.6b.zip - Jan. 2007. + 1. Bug Fixes + 2. PIRL Rate Limiting Parameter update + +DSDT2.6a.zip - Nov. 2006. added support for 88E6045. + +DSDT2.6.zip - Jul. 2006. added support for 88E6097, 88E6096, 88E6046, 88E6047, and 88E6085. + 1. New APIs are added to support new devices. + 2. Bug fixes those were in 2.6 preliminary release. + +DSDT2.6pre.zip - Apr. 2006. added preliminary support for 88E6097. + 1. New features are added. + 2. Some parameters in the existing APIs are modified to support extended feature. + +DSDT2.5b.zip - Jan. 2006. + 1. added gtDelay function after disabling PPU + Since delay function is system/OS dependent, it is required that DSDT user + fill up the gtDelay function based its platform parameters. + gtDelay function is located in src\msApi\gtUtils.c + 2. Unused GT_STATUS definitions are removed. + +DSDT2.5a.zip - Jan. 2006, added support for 88E6122 and 88E6121 and new feature that bypasses + initial device setup, and bug fixes in the previous release. + 1. Bypass initial configuration when loading driver. + 2. Bug fixes: + 1) synchronization issues. + 2) port vector of 0xFF was treated as an invalid vector. + +DSDT2.5.zip - Nov. 2005, added support for 88E6065, 88E6035, 88E6055, 88E6061, and 88E6031, + and bug fixes in the previous release. + 1. New APIs are added to support new devices. + 2. Bug fixes: + 1) gfdbGetAtuEntryNext API returns GT_NO_SUCH when Entry's MAC is Broadcast address. + 2) entryState in GT_ATU_ENTRY follows the definition. + 3) gsysSetTrunkMaskTable API does not overwrite HashTrunk value anymore. + 4) 10/100 FastEthernet Phy Reset occurs along with Speed, Duplex modification. + + +DSDT2.4a.zip - Oct. 2005, added support for 88E6131 and a bug fix. + 1. gprtPortPowerDown(gtPhyCtrl.c) didn't work due to reset - reset is not called after PowerDown bit change. + +DSDT2.4.zip - Aug. 2005, bug fixes and modifications + 1. gprtSetPktGenEnable(gtPhyCtrl.c) didn't work with Serdes Device - resolved. + 2. gprtSetPortAutoMode(gtPhyCtrl.c) dropped 1000Mbps Half duplex mode - resolved. + 3. gprtGetPhyLinkStatus(gtPhyCtrl.c) returned LinkOn when there is no phy connected - resolved. + 4. gprtSetPortDuplexMode(gtPhyCtrl.c) reset 1000M Speed - resolved. + 5. gfdbSetAtuSize(gtBrgFdb.c), now, returns GT_NOT_SUPPORT if ATU size of the device + is not configurable. + 6. gprtSetPortLoopback(gtPhyCtrl.c) treats Fast Ethernet Phy and Gigabit Ethernet Phy + differently. + 7. GT_GET_SERDES_PORT, now, does the error checking. + 8. IS_CONFIGURABLE_PHY reads PHY ID and returns the ID + +DSDT2.4pre.zip - July. 2005, added support for 88E6108 + 1. New features are added. + 2. Arguments in gprtSetPause and gprtSetPortSpeed are modified to support + 1000M Phys. + 3. Driver functions are added to support Marvell Alask Phys and to be + expanded easily for the future Phys. + +DSDT2.3c.zip - May. 2005, + 1. New features in Rev1 or Rev2 of 88E6095 are added + 2. gfdbGetAgingTimeout, and gfdbGetLearnEnable are added + 3. Bug fixes in grcSetEgressRate and grcSetPri0Rate + 4. Resetting TrunkID, when gprtSetTrunkPort is called to disable Trunk, is applied + only to Rev0 of 88E6095 and 88E6185 + +DSDT2.3b.zip - Mar. 2005, + 1. gstpSetMode function does not modify Port State any more, since STP module + sets the port state. gstpSetMode sets the switch so that it can receive + BPDU packets. + 2. gtLoadDriver clears Rsvd2Cpu and Rsvd2CpuEn bits. + 3. TrunkID will be reset when gprtSetTrunkPort is called to disable Trunk. + 4. "Check PPU Status in order to verify PPU disabled" is applied to gtVct.c + +DSDT2.3a.zip - Jan. 2005, added support for 88E6152, 88E6155, 88E6182, and 88E6092 + devices, removed non-existing devices, and bug fix in 2.3 release. + Fix : + Check PPU Status in order to verify PPU disabled. + +DSDT2.3.zip - Nov. 2004, support for 88E6185 and bug fixes in 2.3 preliminary release. + Fixes : + 1) Provide some delay after disabling PPU. + 2) VCT runs after disabling PPU. + +DSDT2.3pre.zip - Nov. 2004, added preliminary support for 88E6185. + +DSDT2.2a.zip - Nov. 2004, added semaphore support for MII Access with multi address mode. + +DSDT2.2.zip - Oct. 2004, support for 88E6095 and bug fixes in 2.2 preliminary release. + +DSDT2.2pre.zip - Sep. 2004, added preliminary support for 88E6095 and work-around for VCT + based on VCT Application Note. + +DSDT2.1a.zip - Apr. 2004, support 88E6093 and bug fixes. + Device Driver Package name has been changed from QDDriver to DSDT(Datacom + Same Driver Technology). + Bug Fixes : + 1) DBNum was not correctly handled while getting entry from VTU Table. + 2) Member Tag in VTU entry was not defined correctly for 88E6183 family. + 3) Correction of 88E6183 RMON Counter Structure and Enum. + 4) ATU Interrupt Handling routine + +qdDriver2.1-pre.zip - Apr. 2004, added preliminary support for 88E6093 and bug fixes. + Bug Fixes : + 1) DBNum was not incorrectly handled while getting entry from + VTU Table. + 2) Member Tag in VTU entry was not defined correctly for 88E6183 family. + +qdDriver2.0a.zip - Dec. 2003, provides functions, which can read/write + Switch Port Registers and Switch Global Registers: + gprtGetSwitchReg, + gprtSetSwitchReg, + gprtGetGlobalReg, and + gprtSetGlobalReg + +qdDriver2.0.zip - July. 2003, supports Multi Address Mode for upcoming device. + AUTO_SCAN_MODE, MANUAL_MODE, and MULTI_ADDR_MODE are added + to find a QD Family device. + Supports Sapphire (10 port Gigabit switch). + +qdDriver1.4a.zip - Apr. 2003, bug fixes. + Bug fixes on portVec in GT_ATU_ENTRY structure, which supported only + total of 8 ports (defined as GT_U8). It's now defined as GT_U32. + utils.c and testApi.c in Diag directory also modified to support + the switch with more than 8 ports. + +qdDriver1.4.zip - Apr. 2003, added support for Ocatne (6083). + Removed NO-OPs, which created when DBG_PRINT is undefined. + Bug fixes on gprtSetIGMPSnoop and gprtGetIGMPSnoop functions, + and GT_PRI0_RATE enum type. + +qdDriver1.3h.zip - Feb. 2003, added support for Extended Cable Status, + such as Impediance mismatch, Pair Skew, Pair Swap and Pair Polarity. + Bug fixes on FFox-EG and FFox-XP device ID. + +qdDriver1.3g.zip - Dec. 2002, added preliminary support for Octane (6083) + +qdDriver1.3.zip - Oct. 2002, added support for ClipperShip (6063) + This driver works with all released devices, including + 6051, 6052, 6021, and 6063 + +qdDriver1.2.zip - Aug. 2002, added support for FullSail (6021) + +qdDriver1.1.zip - June, 2002 OS independent QuarterDeck Driver Release + Based on 1.0 release, but removed OS dependency. The driver + is designed to work with any OS without code changes. + +qdDriver1.0.zip - Feb. 2002, Initial QuaterDeck Driver Release + Based on vxWorks OS, support 6051/6052 + + +2) Source Code Organization +-------------------------- + 2.1) src + DSDT Driver Suite Source Code. + + 2.2) Include directory + DSDT Driver Suite Header files and Prototype files + + 2.3) Library + Object files for DSDT driver Suite + + 2.4) Sample + Sample Code that shows how to use MSAPIs, e.g., init DSDT, setup VLAN for Home Gateway, etc. + + * The DSDT Driver Suite Source Code is OS independent, and fully supported by Marvell. + * The Sample Codes are tested under vxworks, and is provided for reference only. + + +3) General Introduction +----------------------- + +The DSDT driver suite is standalone program, which is independent of both OS and Platform. +As such, applications of MSAPIs need to register platform specific functions. +This is done by calling qdLoadDriver function. This function returns a pointer (*dev), +which contains the device and platform information. It will then be used for each MSAPI call. + +msApiInit.c file in Diag directory and Sample\Initialization directory demonstrate +how you can register those functions. + +msApiInit.c + qdStart is the main function to initialize DSDT Driver and does the + followings: + a) register the platform specific functions. + 1.1 and 1.2 below are required. 1.3 to 1.6 is optional. + 1.1) readMii - BSP specific MII read function + 1.2) writeMii - BSP specific MII write function + 1.3) semCreate - OS specific semaphore create function. + 1.4) semDelete - OS specific semaphore delete function. + 1.5) semTake - OS specific semaphore take function. + 1.6) semGive - OS specific semaphore give function. + + Notes) The given example will use DB-88E6218 BSP as an example. + + b) Initialize BSP provided routine (if required). + + c) Calls qdLoadDriver routine. + 1.1) Input (GT_SYS_CONFIG) - CPU Port Number (Board Specific) and Port Mode + (either 1 for Forwarding mode or 0 for Hardware default mode) + 1.2) Output (GT_QD_DEV) - Contains all device (QD) and platform specific info. + It will be used for all API calls. + + d) Calls sysEnable (for future use.) + + +4) HOW TO - Build qdDrv.o for vxWorks +------------------------------------- + +1. Extract the given ZIP file into c:\DSDT_2.x directory + You may change the directory name to your choice, and change the environment variable below accordingly. +2. Edit setenv.bat file in c:\DSDT_2.x\tools +3. Modify the following variables according to your setup. +set USER_BASE=C:\DSDT_2.x +set PROJ_NAME=qdDrv +set WIND_BASE=C:\Tornado +set TARGETCPU=MIPS ;ARM for ARM Cpu +set WIND_HOST_TYPE=x86-win32 +4. run "setenv" +5. Change directory to c:\DSDT_2.x\src +6. run "make" +7. qdDrv.o and qdDrv.map will be created in c:\DSDT_2.x\Library. + + +5) HOW TO - Build qdDrv.lib for WinCE +------------------------------------- + +1. Extract the given ZIP file into c:\DSDT_2.x directory(directory can be changed) +2. Edit setenv.bat file in c:\DSDT_2.x\tools +3. Modify the following variables according to your setup. +set USER_BASE=C:\DSDT_2.x +set PROJ_NAME=qdDrv +set TARGETCPU=x86 ;MIPSIV for MIPS IV +set WCEROOT=C:\WINCE400 + +4. run "setenv WINCE" +5. Change directory to c:\DSDT_2.x\src +6. run "make" +7. qdDrv.lib will be created in c:\DSDT_2.x\Library. + + +6) HOW TO - Build qdDrv.o for Linux +----------------------------------- + +1. Extract the given ZIP file into $HOME/DSDT_2.x directory(directory can be changed) + in Linux system (verified with RedHat 7.3) +2. Edit setenv file in $HOME/DSDT_2.x/tools +3. Modify the following variables according to your setup. + declare -x USER_BASE=$HOME/DSDT_2.x + declare -x PROJ_NAME=qdDrv +4. run "source setenv" +5. Change directory to $HOME/DSDT_2.x/src +6. run "make" +7. qdDrv.o and qdDrv.map will be created in $HOME/DSDT_2.x/Library. + + +7) Changes +----------- +1. SERDES interface configuration + 1) APIs in gtPhyCtrl.c can be used for SERDES interface. + 2) When SERDES interface is accessed, physical SMI address should be used + instead of logical number. This is due to the logical address confliction + between external phys and SERDES. + e.g.) To change the Speed for the first SERDES port (SMI address 0xC) + the following API can be used: + gprtSetPortSpeed(sw_dev, 0xC, PHY_SPEED_1000_MBPS); + +2. VCT for 88E616x, 88E617x, 88E635x + 1) New APIs added as defined the following section + +3. Supports Auto Scan mode for 88E617x, 88E635x devices +4. msgIdStartBit in GT_PTP_CONFIG is obsolete. +5. TRUNK ATU entries for 88E616x, 88E617x, 88E635x are configured properly. +6. Port mapping macros with GT_USE_SIMPLE_PORT_MAPPING are casted properly. +7. Deleted to support 6095 family for Ingress Rate Limit with Flow control. +8. Deleted unused definition in GT_QPRI_TBL_ENTRY. +9. Device definition for GT_88E6124, GT_88E6325, GT_88E6371 has been corrected to + GT_88E6125, GT_88E6321, GT_88E6350, respectively. + + +8) New APIs +----------- + +1. gtAdvVct.c + + 1.1) gvctGetAdvCableDiag + + DESCRIPTION + This routine perform the advanced virtual cable test (TDR) for the requested + port and returns the the status per MDI pair. + DSP based cable length is not provided. Please refer to the API, + gvctGetAdvExtendedStatus, for DSP. + + SYNOPSIS + GT_STATUS gvctGetAdvCableDiag + ( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ADV_VCT_MODE mode, + OUT GT_ADV_CABLE_STATUS *cableStatus + ) + + ARGUMENTS + INPUTS: + port - logical port number. + mode - advance VCT mode (either First Peak or Maximum Peak) + + OUTPUTS: + cableStatus - the copper cable status. + + RETURNS + GT_OK - on success + GT_FAIL - on error + GT_NOT_SUPPORTED - if current device does not support this feature. + + + 1.2) gvctGetAdvExtendedStatus + + DESCRIPTION + This routine retrieves extended cable status, such as Pair Poloarity, + Pair Swap, and Pair Skew. Note that this routine will be success only + if 1000Base-T Link is up. + DSP based cable length is also provided. + + SYNOPSIS + GT_STATUS gvctGetAdvExtendedStatus + ( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ADV_EXTENDED_STATUS *extendedStatus + ) + + + ARGUMENTS + INPUTS: + port - logical port number. + + OUTPUTS: + extendedStatus - the extended cable status. + + RETURNS + GT_OK - on success + GT_FAIL - on error + GT_NOT_SUPPORTED - if current device does not support this feature. + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/802_1q.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/802_1q.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/802_1q.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/802_1q.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,332 @@ +#include +/******************************************************************************* +* 802_1q.c +* +* DESCRIPTION: +* There are three 802.1Q modes (GT_SECURE, GT_CHECK, and GT_FALLBACK). +* In GT_SECURE mode, the VID for the given frame must be contained in +* the VTU, and the Ingress port must be a member of the VLAN or the +* frame will be discarded. +* In GT_CHECK mode, the VID for the given frame must be contained in +* the VTU or the frame will be discarded (the frame will not be +* discarded if the Ingress port is not a memeber of the VLAN). +* In GT_FALLBACK mode, Frames are not discarded if their VID's are not +* contained in the VTU. If the frame's VID is contained in the VTU, the +* frame is allowed to exit only those ports that are members of the +* frame's VLAN; otherwise the switch 'falls back' into Port Based VLAN +* mode for the frame (88E6021 Spec. section 3.5.2.1). +* +* Egress Tagging for a member port of a Vlan has the following three +* choices: +* 1) Unmodified, +* 2) Untagged, and +* 3) Tagged +* +* This sample shows how to utilize 802.1Q feature in the device. +* For more information, please refer to 88E6021 Spec. section 3.5.2.3 +* +* DEPENDENCIES: +* 88E6021 and 88E6063 are supporting this feature. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + + +/***************************************************************************** +* sample802_1qSetup +* +* DESCRIPTION: +* This routine will show how to configure the switch device so that it +* can be a Home Gateway. This example assumes that all the frames are not +* VLAN-Tagged. +* 1) to clear VLAN ID Table, +* 2) to enable 802.1Q in SECURE mode for each port except CPU port, +* 3) to enable 802.1Q in FALL BACK mode for the CPU port. +* 4) to add VLAN ID 1 with member port 0 and CPU port +* (untagged egress), +* 5) to add VLAN ID 2 with member the rest of the ports and CPU port +* (untagged egress), +* 6) to configure the default vid of each port: +* Port 0 have PVID 1, CPU port has PVID 3, and the rest ports have PVID 2. +* Note: CPU port's PVID should be unknown VID, so that QuarterDeck can use +* VlanTable (header info) for TX. +* +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* WARNING!! +* If you create just two VLAN for this setup, Trailer mode or Header mode +* for the CPU port has to be enabled and Ethernet driver which connects to +* CPU port should understand VLAN-TAGGING, Trailer mode, or Header mode. +* +*******************************************************************************/ +GT_STATUS sample802_1qSetup(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_DOT1Q_MODE mode; + GT_VTU_ENTRY vtuEntry; + GT_U16 vid; + GT_LPORT port; + int i; + + /* + * 1) Clear VLAN ID Table + */ + if((status = gvtuFlush(dev)) != GT_OK) + { + MSG_PRINT(("gvtuFlush returned fail.\n")); + return status; + } + + /* + * 2) Enable 802.1Q for each port as GT_SECURE mode except CPU port. + */ + mode = GT_SECURE; + for(i=0; inumOfPorts; i++) + { + port = i; + if (port == dev->cpuPortNum) + continue; + + if((status = gvlnSetPortVlanDot1qMode(dev,port, mode)) != GT_OK) + { + MSG_PRINT(("gvlnSetPortVlanDot1qMode return Failed\n")); + return status; + } + } + + /* + * 3) Enable 802.1Q for CPU port as GT_FALLBACK mode + */ + if((status = gvlnSetPortVlanDot1qMode(dev, dev->cpuPortNum, GT_FALLBACK)) != GT_OK) + { + MSG_PRINT(("gvlnSetPortVlanDot1qMode return Failed\n")); + return status; + } + + /* + * 4) Add VLAN ID 1 with Port 0 and CPU Port as members of the Vlan. + */ + gtMemSet(&vtuEntry,0,sizeof(GT_VTU_ENTRY)); + vtuEntry.DBNum = 0; + vtuEntry.vid = 1; + for(i=0; inumOfPorts; i++) + { + port = i; + if((i==0) || (port == dev->cpuPortNum)) + vtuEntry.vtuData.memberTagP[port] = MEMBER_EGRESS_UNTAGGED; + else + vtuEntry.vtuData.memberTagP[port] = NOT_A_MEMBER; + } + + if((status = gvtuAddEntry(dev,&vtuEntry)) != GT_OK) + { + MSG_PRINT(("gvtuAddEntry returned fail.\n")); + return status; + } + + /* + * 5) Add VLAN ID 2 with the rest of the Ports and CPU Port as members of + * the Vlan. + */ + gtMemSet(&vtuEntry,0,sizeof(GT_VTU_ENTRY)); + vtuEntry.DBNum = 0; + vtuEntry.vid = 2; + for(i=0; inumOfPorts; i++) + { + port = i; + if(i == 0) + vtuEntry.vtuData.memberTagP[port] = NOT_A_MEMBER; + else + vtuEntry.vtuData.memberTagP[port] = MEMBER_EGRESS_UNTAGGED; + } + + if((status = gvtuAddEntry(dev,&vtuEntry)) != GT_OK) + { + MSG_PRINT(("gvtuAddEntry returned fail.\n")); + return status; + } + + + /* + * 6) Configure the default vid for each port. + * Port 0 has PVID 1, CPU port has PVID 3, and the rest ports have PVID 2. + */ + for(i=0; inumOfPorts; i++) + { + port = i; + if(i==0) + vid = 1; + else if(port == dev->cpuPortNum) + vid = 3; + else + vid = 2; + + if((status = gvlnSetPortVid(dev,port,vid)) != GT_OK) + { + MSG_PRINT(("gvlnSetPortVid returned fail.\n")); + return status; + } + } + + return GT_OK; + +} + + +/***************************************************************************** +* sampleAdmitOnlyTaggedFrame +* +* DESCRIPTION: +* This routine will show how to configure a port to accept only vlan +* tagged frames. +* This routine assumes that 802.1Q has been enabled for the given port. +* +* INPUTS: +* port - logical port to be configured. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Some device support Discard Untagged feature. If so, gprtSetDiscardUntagged +* function will do the work. +* +*******************************************************************************/ +GT_STATUS sampleAdmitOnlyTaggedFrame(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_VTU_ENTRY vtuEntry; + int i; + + /* + * 0) If device support gprtSetDiscardUntagged, call the function. + */ + status = gprtSetDiscardUntagged(dev, port, GT_TRUE); + switch (status) + { + case GT_OK: + MSG_PRINT(("Done.\n")); + return status; + case GT_NOT_SUPPORTED: + MSG_PRINT(("Try other method.\n")); + break; + default: + MSG_PRINT(("Failure accessing device.\n")); + return status; + } + + + /* + * 1) Add VLAN ID 0xFFF with the given port as a member. + */ + gtMemSet(&vtuEntry,0,sizeof(GT_VTU_ENTRY)); + vtuEntry.DBNum = 0; + vtuEntry.vid = 0xFFF; + for(i=0; inumOfPorts; i++) + { + vtuEntry.vtuData.memberTagP[i] = NOT_A_MEMBER; + } + vtuEntry.vtuData.memberTagP[port] = MEMBER_EGRESS_TAGGED; + + if((status = gvtuAddEntry(dev,&vtuEntry)) != GT_OK) + { + MSG_PRINT(("gvtuAddEntry returned fail.\n")); + return status; + } + + /* + * 2) Configure the default vid for the given port with VID 0xFFF + */ + if((status = gvlnSetPortVid(dev,port,0xFFF)) != GT_OK) + { + MSG_PRINT(("gvlnSetPortVid returned fail.\n")); + return status; + } + + return GT_OK; + +} + + +/***************************************************************************** +* sampleDisplayVIDTable +* +* DESCRIPTION: +* This routine will show how to enumerate each vid entry in the VTU table +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS sampleDisplayVIDTable(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_VTU_ENTRY vtuEntry; + GT_LPORT port; + int portIndex; + + gtMemSet(&vtuEntry,0,sizeof(GT_VTU_ENTRY)); + vtuEntry.vid = 0xfff; + if((status = gvtuGetEntryFirst(dev,&vtuEntry)) != GT_OK) + { + MSG_PRINT(("gvtuGetEntryCount returned fail.\n")); + return status; + } + + MSG_PRINT(("DBNum:%i, VID:%i \n",vtuEntry.DBNum,vtuEntry.vid)); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + MSG_PRINT(("Tag%i:%#x ",port,vtuEntry.vtuData.memberTagP[port])); + } + + MSG_PRINT(("\n")); + + while(1) + { + if((status = gvtuGetEntryNext(dev,&vtuEntry)) != GT_OK) + { + break; + } + + MSG_PRINT(("DBNum:%i, VID:%i \n",vtuEntry.DBNum,vtuEntry.vid)); + + for(portIndex=0; portIndexnumOfPorts; portIndex++) + { + port = portIndex; + + MSG_PRINT(("Tag%i:%#x ",port,vtuEntry.vtuData.memberTagP[port])); + } + + MSG_PRINT(("\n")); + + } + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/802.1Q/readme.txt 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,53 @@ +======================================================================== + 802.1Q Feature +======================================================================== + +There are three 802.1Q modes (GT_SECURE, GT_CHECK, and GT_FALLBACK). +In GT_SECURE mode, the VID for the given frame must be contained in +the VTU, and the Ingress port must be a member of the VLAN or the +frame will be discarded. +In GT_CHECK mode, the VID for the given frame must be contained in +the VTU or the frame will be discarded (the frame will not be +discarded if the Ingress port is not a memeber of the VLAN). +In GT_FALLBACK mode, Frames are not discarded if their VID's are not +contained in the VTU. If the frame's VID is contained in the VTU, the +frame is allowed to exit only those ports that are members of the +frame's VLAN; otherwise the switch 'falls back' into Port Based VLAN +mode for the frame (88E6021 Spec. section 3.5.2.1). + +Egress Tagging for a member port of a Vlan has the following three +choices: +1) Unmodified, +2) Untagged, and +3) Tagged + +This sample shows how to utilize 802.1Q feature in the device. +For more information, please refer to 88E6021 Spec. section 3.5.2.3. + +802_1q.c + sample802_1qSetup + This routine will show + 1) how to enable 802.1Q feature for each port, + 2) how to clear VLAN ID (VTU) Table, + 3) how to enable 802.1Q in SECURE mode for each port, + 4) how to add VLAN ID 1 with member port 0 and CPU port + (unmodified egress), + 5) how to add VLAN ID 2 with member the rest of the ports and CPU port + (untagged egress), + 6) how to configure the default vid of each port: + Port 0 and CPU port have PVID 1 and the rest ports have PVID 2. + + sampleAdmitOnlyTaggedFrame + This routine will show how to configure a port to accept only vlan + tagged frames. + This routine assumes that 802.1Q has been enabled for the given port. + + sampleDisplayVIDTable + This routine will show how to enumerate each vid entry in the VTU table + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/CableTest/advCableTest.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/CableTest/advCableTest.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/CableTest/advCableTest.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/CableTest/advCableTest.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,202 @@ +#include +/******************************************************************************** +* testApi.c +* +* DESCRIPTION: +* API test functions +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +GT_STATUS advVctTest(GT_QD_DEV *dev, GT_LPORT port); +GT_STATUS getAdvExtendedStatus(GT_QD_DEV *dev, GT_LPORT port); + +void displayAdvVCTResult +( + GT_ADV_CABLE_STATUS *cableStatus, + int channel +) +{ + int i; + + switch(cableStatus->cableStatus[channel]) + { + case GT_ADV_VCT_FAIL: + MSG_PRINT(("Advanced Cable Test Failed\n")); + break; + case GT_ADV_VCT_NORMAL: + MSG_PRINT(("Cable Test Passed. No problem found.\n")); + break; + case GT_ADV_VCT_IMP_GREATER_THAN_115: + MSG_PRINT(("Cable Test Passed. Impedance is greater than 115 Ohms.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableStatus->u[channel].dist2fault)); + break; + case GT_ADV_VCT_IMP_LESS_THAN_85: + MSG_PRINT(("Cable Test Passed. Impedance is less than 85 Ohms.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableStatus->u[channel].dist2fault)); + break; + case GT_ADV_VCT_OPEN: + MSG_PRINT(("Cable Test Passed. Open Cable.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableStatus->u[channel].dist2fault)); + break; + case GT_ADV_VCT_SHORT: + MSG_PRINT(("Cable Test Passed. Shorted Cable.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableStatus->u[channel].dist2fault)); + break; + case GT_ADV_VCT_CROSS_PAIR_SHORT: + MSG_PRINT(("Cable Test Passed.\n")); + for(i=0; iu[channel].crossShort.channel[i] == GT_TRUE) + { + MSG_PRINT(("\tCross pair short with channel %i.\n",i)); + MSG_PRINT(("\tApproximatly %i meters from the tested port.\n", + cableStatus->u[channel].crossShort.dist2fault[i])); + } + } + break; + default: + MSG_PRINT(("Unknown Test Result.\n")); + break; + } +} + +/* Advanced VCT (TDR) */ +GT_STATUS advVctTest(GT_QD_DEV *dev, GT_LPORT port) +{ + GT_STATUS status; + int i, j; + GT_ADV_VCT_MODE mode; + GT_ADV_CABLE_STATUS advCableStatus; + + GT_ADV_VCT_MOD mod[2] = { + GT_ADV_VCT_FIRST_PEAK, + GT_ADV_VCT_MAX_PEAK + }; + + char modeStr[2][32] = { + "(Adv VCT First PEAK)", + "(Adv VCT MAX PEAK)" + }; + + if (dev == 0) + { + MSG_PRINT(("GT driver is not initialized\n")); + return GT_FAIL; + } + + for (j=0; j<2; j++) + { + mode.mode=mod[j]; + mode.transChanSel=GT_ADV_VCT_TCS_NO_CROSSPAIR; + mode.sampleAvg = 0; + mode.peakDetHyst =0; + + /* + * Start and get Cable Test Result + */ + status = GT_OK; + if((status = gvctGetAdvCableDiag(dev,port, + mode,&advCableStatus)) != GT_OK) + { + MSG_PRINT(("gvctGetAdvCableDiag return Failed\n")); + return status; + } + + MSG_PRINT(("\nCable Test Result %s for Port %i\n", modeStr[j], (int)port)); + + for(i=0; i +/******************************************************************************** +* cableTest.c +* +* DESCRIPTION: +* This sample shows how to run Virtual Cable Test and how to use the +* test result. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + +void sampleDisplayCableTestResult +( + GT_TEST_STATUS *cableStatus, + GT_CABLE_LEN *cableLen +) +{ + switch(*cableStatus) + { + case GT_TEST_FAIL: + MSG_PRINT(("Cable Test Failed\n")); + break; + case GT_NORMAL_CABLE: + MSG_PRINT(("Cable Test Passed. No problem found.\n")); + switch(cableLen->normCableLen) + { + case GT_LESS_THAN_50M: + MSG_PRINT(("Cable Length is less than 50M.\n")); + break; + case GT_50M_80M: + MSG_PRINT(("Cable Length is between 50M and 80M.\n")); + break; + case GT_80M_110M: + MSG_PRINT(("Cable Length is between 80M and 110M.\n")); + break; + case GT_110M_140M: + MSG_PRINT(("Cable Length is between 110M and 140M.\n")); + break; + case GT_MORE_THAN_140: + MSG_PRINT(("Cable Length is over 140M.\n")); + break; + default: + MSG_PRINT(("Cable Length is unknown.\n")); + break; + } + break; + case GT_IMPEDANCE_MISMATCH: + MSG_PRINT(("Cable Test Passed. Cable has Impedance Mismatch .\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + case GT_OPEN_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is open.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + case GT_SHORT_CABLE: + MSG_PRINT(("Cable Test Passed. Cable is short.\n")); + MSG_PRINT(("Approximatly %i meters from the tested port.\n",cableLen->errCableLen)); + break; + default: + MSG_PRINT(("Unknown Test Result.\n")); + break; + } +} + + +GT_STATUS sampleCableTest(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + GT_CABLE_STATUS cableStatus; + int i; + + /* + * Start and get Cable Test Result + */ + if((status = gvctGetCableDiag(dev,port, &cableStatus)) != GT_OK) + { + MSG_PRINT(("gvctGetCableDiag return Failed\n")); + return status; + } + + MSG_PRINT(("Cable Test Result for Port %i\n",port)); + + if(cableStatus.phyType == PHY_100M) + { + MSG_PRINT(("RX PAIR :\n")); + sampleDisplayCableTestResult(&cableStatus.cableStatus[MDI_RX_PAIR], + &cableStatus.cableLen[MDI_RX_PAIR]); + MSG_PRINT(("TX PAIR :\n")); + sampleDisplayCableTestResult(&cableStatus.cableStatus[MDI_TX_PAIR], + &cableStatus.cableLen[MDI_TX_PAIR]); + } + else /* phyType must be PHY_1000M */ + { + for(i=0; i +/******************************************************************************** +* crossChipTrunk.c +* +* DESCRIPTION: +* This sample shows how to setup the Cross Chip TRUNK +* +* DEPENDENCIES: +* Please check the device's spec. if the device supports this feature. +* At the moment this sample was written, 88E6095 was the only device support +* this feature. +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + +#define N_OF_QD_DEVICES 2 +#define MAX_PORT_IN_TRUNK 4 + +/* qdMultiDev is defined in sample/MultiDevice/msApiInit.c */ +extern GT_QD_DEV *qdMultiDev[N_OF_QD_DEVICES]; + +typedef struct _TRUNK_SET { + GT_U32 devIndex; + GT_U32 port; +} TRUNK_SET; + +typedef struct _TRUNK_MEMBER { + GT_U32 trunkId; + GT_U32 nTrunkPort; + TRUNK_SET trunkSet[MAX_PORT_IN_TRUNK]; +} TRUNK_MEMBER; + +GT_STATUS sampleCrossChipTrunk(GT_QD_DEV *dev[], TRUNK_MEMBER* tm); + +/* + Setup Trunk with the following member ports: + Port 0,1,2 of Device 0, and + Port 0 of Device 1, + where Device 0 is the first Switch Device Structure in qdMultiDev array + and Device 1 is the second Switch Device Structure in qdMultiDev array. +*/ +GT_STATUS crossChipTrunkSetup() +{ + TRUNK_MEMBER tm; + + tm.trunkId = 1; + tm.nTrunkPort = 4; + tm.trunkSet[0].devIndex = 0; + tm.trunkSet[0].port = 0; + tm.trunkSet[1].devIndex = 0; + tm.trunkSet[1].port = 1; + tm.trunkSet[2].devIndex = 0; + tm.trunkSet[2].port = 2; + tm.trunkSet[3].devIndex = 1; + tm.trunkSet[3].port = 0; + + return sampleCrossChipTrunk(qdMultiDev, &tm); +} + +GT_STATUS sampleCrossChipTrunk(GT_QD_DEV *dev[], TRUNK_MEMBER* tm) +{ + GT_STATUS status; + int i,j,index; + GT_U32 mask, trunkId; + TRUNK_SET* ts; + GT_U32 portVec[N_OF_QD_DEVICES]; + GT_U32 casecadeVec = 0xC0; /* Port 6 and 7. ToDo : get this value from user or device */ + + /* + * Enable Trunk for each member of the Trunk and set the Trunk ID (1). + */ + + printf("Setting TRUNK\n"); + printf("Trunk ID : %i\n",(unsigned int)tm->trunkId); + printf("N Ports : %i\n",(unsigned int)tm->nTrunkPort); + printf("1st Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[0].devIndex,(unsigned int)tm->trunkSet[0].port); + printf("2nd Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[1].devIndex,(unsigned int)tm->trunkSet[1].port); + printf("3rd Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[2].devIndex,(unsigned int)tm->trunkSet[2].port); + printf("4th Port : Dev %i, Port %i\n", + (unsigned int)tm->trunkSet[3].devIndex,(unsigned int)tm->trunkSet[3].port); + + trunkId = tm->trunkId; + + for(i=0; inTrunkPort; i++) + { + ts = &tm->trunkSet[i]; + + if(ts->devIndex >= N_OF_QD_DEVICES) + { + printf("Device %i is supported. Max Device Number is %i\n",(unsigned int)ts->devIndex,N_OF_QD_DEVICES-1); + return GT_FAIL; + } + + if((dev[ts->devIndex] == NULL) || (!dev[ts->devIndex]->devEnabled)) + { + printf("Device %i is not initialized\n",(unsigned int)ts->devIndex); + return GT_FAIL; + } + + /* enabled trunk on the given port */ + if((status = gprtSetTrunkPort(dev[ts->devIndex],ts->port,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + portVec[ts->devIndex] |= (1 << ts->port); + } + + /* + * Set Trunk Route Table for the given Trunk ID. + */ + printf("Setting TRUNK Routing Table\n"); + for(i=0; idevEnabled)) + { + printf("Device %i is not initialized\n",i); + break; + } + + if((status = gsysSetTrunkRouting(dev[i],trunkId,portVec[i]|casecadeVec)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + } + + /* + * Set Trunk Mask Table for load balancing. + */ + printf("Setting TRUNK Mask for Load Balancing\n"); + for(i=0; i<8; i++) + { + /* choose a port to be used for the given addr combo index */ + index = i % tm->nTrunkPort; + ts = &tm->trunkSet[index]; + + for(j=0; jdevEnabled)) + { + printf("Device %i is not initialized\n",j); + continue; + } + + if(portVec[j] == 0) + continue; + + if((status = gsysGetTrunkMaskTable(dev[j],i,&mask)) != GT_OK) + { + MSG_PRINT(("gsysGetTrunkMaskTable return Failed\n")); + return status; + } + + mask &= ~portVec[j]; + + if(ts->devIndex == j) + mask |= (1 << ts->port); + + if((status = gsysSetTrunkMaskTable(dev[j],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + } + } + + return GT_OK; +} + + + +/* + Assumption 1: Device ID, Cascading Port, CPU Port, and Interswitch Port are + already set properly. For more information, please refer to the + sample/MultiDevice/msApiInit.c + + Assumption 2: Port 0,1,2 of Device 0 and Port 0 of Device 1 are member of a + trunk with Trunk ID 1. +*/ + +GT_STATUS sampleFixedCrossChipTrunk(GT_QD_DEV *dev[]) +{ + GT_STATUS status; + int i; + GT_U32 mask, trunkBit, trunkId; + + /* + * Enable Trunk for each member of the Trunk and set the Trunk ID (1). + */ + + trunkId = 1; + + if((dev[0] == NULL) || (!dev[0]->devEnabled)) + { + printf("Device 0 is not initialized\n"); + return GT_FAIL; + } + if((dev[1] == NULL) || (!dev[1]->devEnabled)) + { + printf("Device 1 is not initialized\n"); + return GT_FAIL; + } + + /* setup for Device 0 port 0 */ + if((status = gprtSetTrunkPort(dev[0],0,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 0 port 1 */ + if((status = gprtSetTrunkPort(dev[0],1,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 0 port 2 */ + if((status = gprtSetTrunkPort(dev[0],2,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + /* setup for Device 1 port 0 */ + if((status = gprtSetTrunkPort(dev[1],0,GT_TRUE,trunkId)) != GT_OK) + { + MSG_PRINT(("gprtSetTrunkPort return Failed\n")); + return status; + } + + + /* + * Set Trunk Route Table for the given Trunk ID. + */ + + /* setup for Device 0, trunk ID 1 : port 0,1,2, and 9 (cascading port, assumption1) */ + if((status = gsysSetTrunkRouting(dev[0],trunkId,0x7|0x200)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + + /* setup for Device 1, trunk ID 1 : port 0, and 8 (cascading port, assumption1) */ + if((status = gsysSetTrunkRouting(dev[1],trunkId,0x1|0x100)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkRouting return Failed\n")); + return status; + } + + + /* + * Set Trunk Mask Table for load balancing. + */ + + /* + Trunk Mask Table for Device 0: + + 10 9 8 7 6 5 4 3 2 1 0 + TrunkMask[0] 1 1 1 1 1 1 1 1 0 0 1 + TrunkMask[1] 1 1 1 1 1 1 1 1 0 1 0 + TrunkMask[2] 1 1 1 1 1 1 1 1 1 0 0 + TrunkMask[3] 1 1 1 1 1 1 1 1 0 0 0 + TrunkMask[4] 1 1 1 1 1 1 1 1 0 0 1 + TrunkMask[5] 1 1 1 1 1 1 1 1 0 1 0 + TrunkMask[6] 1 1 1 1 1 1 1 1 1 0 0 + TrunkMask[7] 1 1 1 1 1 1 1 1 0 0 0 + + + Trunk Mask Table for Device 1: + + 10 9 8 7 6 5 4 3 2 1 0 + TrunkMask[0] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[1] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[2] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[3] 1 1 1 1 1 1 1 1 1 1 1 + TrunkMask[4] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[5] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[6] 1 1 1 1 1 1 1 1 1 1 0 + TrunkMask[7] 1 1 1 1 1 1 1 1 1 1 1 + + */ + + /* setup for Device 0 */ + for(i=0; i<8; i++) + { + if((i%4) == 3) + { + trunkBit = 0; + } + else + { + trunkBit = 1 << (i%4); + } + + mask = 0x7F8 | trunkBit; + + if((status = gsysSetTrunkMaskTable(dev[0],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + + } + + /* setup for Device 1 */ + for(i=0; i<8; i++) + { + if((i%4) == 3) + { + trunkBit = 1; + } + else + { + trunkBit = 0; + } + + mask = 0x7FE | trunkBit; + + if((status = gsysSetTrunkMaskTable(dev[1],i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + + } + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/CrossChipTrunk/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/CrossChipTrunk/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/CrossChipTrunk/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/CrossChipTrunk/readme.txt 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,19 @@ +======================================================================== + Setup for Cross Chip Trunk +======================================================================== + +This sample shows how to setup the Cross Chip Trunk with the following +assumptions. + Assumption 1: Device ID, Cascading Port, CPU Port, and Interswitch Port are + already set properly. For more information, please refer to the + sample/MultiDevice/msApiInit.c + + Assumption 2: Port 0,1,2 of Device 0 and Port 0 of Device 1 are member of a + trunk with Trunk ID, 1. + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/flowCtrl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/flowCtrl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/flowCtrl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/flowCtrl.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,55 @@ +#include +/******************************************************************************** +* flowCtrl.c +* +* DESCRIPTION: +* Sample program which will show how to Enable or Disable Flow Control of +* the given Port of the QuaterDeck. +* +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + +/* + * Enable or Disable Flow Control of the given port. + * Input - port : port to be programmed. + * enalble : either Enable or Disable. +*/ +GT_STATUS sampleSetFlowControl(GT_QD_DEV *dev, GT_LPORT port, GT_BOOL enable) +{ + GT_STATUS status; + + /* + * Program Phy's Pause bit in AutoNegotiation Advertisement Register. + */ + if((status = gprtSetPause(dev,port,enable)) != GT_OK) + { + MSG_PRINT(("gprtSetForceFC return Failed\n")); + return status; + } + + /* + * Restart AutoNegotiation of the given Port's phy + */ + if((status = gprtPortRestartAutoNeg(dev,port)) != GT_OK) + { + MSG_PRINT(("gprtSetForceFC return Failed\n")); + return status; + } + + /* + * Program Port's Flow Control. + */ + if((status = gprtSetForceFc(dev,port,enable)) != GT_OK) + { + MSG_PRINT(("gprtSetForceFC return Failed\n")); + return status; + } + + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/FlowControl/readme.txt 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,17 @@ +======================================================================== + Flow Contorl Enable or Disable +======================================================================== + +Flow Control Setup requires multiple of DSDT API calls which can be +examined in this sample. + +flowCtrl.c + sampleSetFlowControl can be used to enable or disable flow control + of the given port + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Header/header.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Header/header.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Header/header.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Header/header.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,45 @@ +#include +/******************************************************************************** +* header.c +* +* DESCRIPTION: +* This sample shows how to enable/disable CPU port's ingress and egress +* Header mode. For more information about Header mode, please refer to +* 88E6063 Data Book. Header mode sould be handled by Ethernet Device/Driver +* as well, since 88E6063, with header mode enabled, sends out a packet with +* header, which cannot be recognized by regular Ethernet device/driver, +* and expects header for every received packet. +* +* DEPENDENCIES: +* 88E6051, 88E6052, and 88E6021 are not supporting this feature. +* +* FILE REVISION NUMBER: +* +* COMMENTS: +* WARNING!! +* When Header mode for the CPU port is enabled, Ethernet Device/Driver +* which connects to the CPU port should understand Header Format. +* If Ethernet Device does not know about Header mode, then user may set +* the device to Promiscuous mode in order to receive packets from QD's CPU +* port. After that, it is Ethernet Device Driver's responsibility to handle +* Header properly. +*******************************************************************************/ + +#include "msSample.h" + +GT_STATUS sampleHeaderEnable(GT_QD_DEV *dev,GT_BOOL en) +{ + GT_STATUS status; + + /* + * Enable/Disable Header mode + */ + if((status = gprtSetHeaderMode(dev,dev->cpuPortNum, en)) != GT_OK) + { + MSG_PRINT(("gprtSetHeaderMode return Failed\n")); + return status; + } + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Header/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Header/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Header/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Header/readme.txt 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,26 @@ +======================================================================== + CPU Header Mode Enable or Disable +======================================================================== + +This sample shows how to enable/disable header mode for CPU port. +For more information about header mode, please refer to 88E6063 Spec. +section 3.5.10 and section 3.7.5. + +Notes: +When Header mode for the CPU port is enabled, Ethernet Device/Driver +which is directly connected to the CPU port should understand Header Format. +If Ethernet Device does not know about Header mode, then user may set +the device to Promiscuous mode in order to receive packets from switch's CPU +port. After that, it is Ethernet Device Driver's responsibility to handle +Header properly. + +header.c + sampleHeaderEnable can be used to enable or disable CPU port's + header mode + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Include/msSample.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Include/msSample.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Include/msSample.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Include/msSample.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,147 @@ +#include +/******************************************************************************** +* msSample.h +* +* DESCRIPTION: +* Types definitions for Sample program +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __pfTesth +#define __pfTesth + +#ifdef _VXWORKS +#include "vxWorks.h" +#include "logLib.h" +#endif +#include "stdio.h" +#include "stdarg.h" +#include "stdlib.h" +#include "time.h" +#include "string.h" + +#include "msApi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef GT_U32 (*GT_API_VOID) (GT_QD_DEV*); +typedef int (*GT_CMP_FUNC) (void*, int, int); + +typedef GT_STATUS (*GT_API_SET_BOOL) (GT_QD_DEV*, GT_BOOL); +typedef GT_STATUS (*GT_API_GET_BOOL) (GT_QD_DEV*, GT_BOOL*); + +typedef GT_STATUS (*GT_API_MAC_ADDR) (GT_QD_DEV*, GT_ETHERADDR*); + +typedef GT_STATUS (*GT_API_SET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL); +typedef GT_STATUS (*GT_API_GET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL*); + +typedef GT_STATUS (*GT_API_SET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16); +typedef GT_STATUS (*GT_API_GET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16*); + +typedef GT_STATUS (*GT_API_SET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32); +typedef GT_STATUS (*GT_API_GET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32*); + +typedef GT_STATUS (*GT_API_SET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8); +typedef GT_STATUS (*GT_API_GET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8*); + +typedef struct _TEST_API +{ + union + { + GT_API_SET_BOOL bool; + GT_API_MAC_ADDR mac; + GT_API_SET_PORT_BOOL port_bool; + GT_API_SET_PORT_U8 port_u8; + GT_API_SET_PORT_U16 port_u16; + GT_API_SET_PORT_U32 port_u32; + } setFunc; + + union + { + GT_API_GET_BOOL bool; + GT_API_MAC_ADDR mac; + GT_API_GET_PORT_BOOL port_bool; + GT_API_GET_PORT_U8 port_u8; + GT_API_GET_PORT_U16 port_u16; + GT_API_GET_PORT_U32 port_u32; + } getFunc; + +}TEST_API; + +typedef struct _TEST_STRUCT +{ + char strTest[16]; + GT_API_VOID testFunc; + GT_U32 testResults; +} TEST_STRUCT; + +#define MSG_PRINT(x) testPrint x + +#define TEST_MAC_ENTRIES 32 +typedef struct _TEST_ATU_ENTRY +{ + GT_ATU_ENTRY atuEntry[TEST_MAC_ENTRIES]; +}TEST_ATU_ENTRY; + +typedef struct _ATU_ENTRY_INFO +{ + GT_ATU_ENTRY atuEntry; + GT_U16 hash; + GT_U16 bucket; +} ATU_ENTRY_INFO; + +extern GT_SYS_CONFIG pfTestSysCfg; +extern ATU_ENTRY_INFO *gAtuEntry; +extern GT_QD_DEV *dev; + +GT_STATUS qdStart(int,int,int); +GT_STATUS qdSimSetPhyInt(unsigned int portNumber, unsigned short u16Data); +GT_STATUS qdSimSetGlobalInt(unsigned short u16Data); + +GT_STATUS testAll(GT_QD_DEV*); +void testPrint(char* format, ...); + +extern FGT_INT_HANDLER qdIntHandler; + +int vtuEntryCmpFunc(void* buf, int a, int b); +int atuEntryCmpFunc(void* buf, int a, int b); +GT_STATUS gtSort(int list[], GT_CMP_FUNC cmpFunc, void* buf, GT_U32 len); +GT_U16 createATUList(GT_QD_DEV *dev, TEST_ATU_ENTRY atuEntry[], GT_U16 entrySize, GT_U16 dbNumSize, + GT_U16 sameMacsInEachDb, GT_U16 bSize); +GT_STATUS testFillUpAtu(GT_QD_DEV *dev, ATU_ENTRY_INFO *atuEntry, GT_U8 atuSize, + GT_U8 dbNum, GT_U16 first2Bytes, GT_ATU_UC_STATE state); +GT_U16 runQDHash(GT_U8* eaddr, GT_U16 dbNum, int bSize, GT_U16* pHash, + GT_U16* preBucket, GT_U16* posBucket); +GT_STATUS testDisplayATUList(); + +#undef USE_SEMAPHORE + +#ifdef USE_SEMAPHORE +GT_SEM osSemCreate(GT_SEM_BEGIN_STATE state); +GT_STATUS osSemDelete(GT_SEM smid); +GT_STATUS osSemWait(GT_SEM smid, GT_U32 timeOut); +GT_STATUS osSemSignal(GT_SEM smid); +#endif + +GT_BOOL gtBspReadMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value); +GT_BOOL gtBspWriteMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int value); +void gtBspMiiInit(); + +GT_BOOL qdSimRead (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL qdSimWrite (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int value); +void qdSimInit(); + +#ifdef __cplusplus +} +#endif + +#endif /* __pfTesth */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Include/qdSimRegs.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Include/qdSimRegs.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Include/qdSimRegs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Include/qdSimRegs.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,131 @@ +#include + +/******************************************************************************** +* gtSimRegs.h +* +* DESCRIPTION: +* This file includes the declaration of the struct to hold the addresses +* of switch (global & per-port). +* +* DEPENDENCIES: +* QuarterDeck register MAP. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __qdSimRegsh +#define __qdSimRegsh + +/* QuarterDeck Per Port Registers */ +#define QD_REG_PORT_STATUS 0x0 +#define QD_REG_SWITCH_ID 0x3 +#define QD_REG_PORT_CONTROL 0x4 +#define QD_REG_PORT_VLAN_MAP 0x6 +#define QD_REG_PVID 0x7 +#define QD_REG_RATE_CTRL 0xA +#define QD_REG_PAV 0xB +#define QD_REG_RXCOUNTER 0x10 +#define QD_REG_TXCOUNTER 0x11 +#define QD_REG_Q_COUNTER 0x1B + +/* QuarterDeck Global Registers */ +#define QD_REG_GLOBAL_STATUS 0x0 +#define QD_REG_MACADDR_01 0x1 +#define QD_REG_MACADDR_23 0x2 +#define QD_REG_MACADDR_45 0x3 +#define QD_REG_GLOBAL_CONTROL 0x4 + +/* the following VTU entries are added for Fullsail and Clippership */ +#define QD_REG_VTU_OPERATION 0x5 +#define QD_REG_VTU_VID_REG 0x6 +#define QD_REG_VTU_DATA1_REG 0x7 +#define QD_REG_VTU_DATA2_REG 0x8 +#define QD_REG_VTU_DATA3_REG 0x9 +#define QD_REG_STATS_OPERATION 0x1D +#define QD_REG_STATS_COUNTER3_2 0x1E +#define QD_REG_STATS_COUNTER1_0 0x1F + +#define QD_REG_ATU_CONTROL 0xA +#define QD_REG_ATU_OPERATION 0xB +#define QD_REG_ATU_DATA_REG 0xC +#define QD_REG_ATU_MAC_BASE 0xD +#define QD_REG_ATU_MAC_01 0xD +#define QD_REG_ATU_MAC_23 0xE +#define QD_REG_ATU_MAC_45 0xF +#define QD_REG_IP_PRI_BASE 0x10 +#define QD_REG_IP_PRI_REG0 0x10 +#define QD_REG_IP_PRI_REG1 0x11 +#define QD_REG_IP_PRI_REG2 0x12 +#define QD_REG_IP_PRI_REG3 0x13 +#define QD_REG_IP_PRI_REG4 0x14 +#define QD_REG_IP_PRI_REG5 0x15 +#define QD_REG_IP_PRI_REG6 0x16 +#define QD_REG_IP_PRI_REG7 0x17 +#define QD_REG_IEEE_PRI 0x18 + +/* Definition for QD_REG_PORT_STATUS */ +#define QD_PORT_STATUS_DUPLEX 0x200 + +/* Definitions for MIB Counter */ +#define GT_STATS_NO_OP 0x0 +#define GT_STATS_FLUSH_ALL 0x1 +#define GT_STATS_FLUSH_PORT 0x2 +#define GT_STATS_READ_COUNTER 0x4 +#define GT_STATS_CAPTURE_PORT 0x5 + +#define QD_PHY_CONTROL_REG 0 +#define QD_PHY_AUTONEGO_AD_REG 4 +#define QD_PHY_NEXTPAGE_TX_REG 7 +#define QD_PHY_SPEC_CONTROL_REG 16 +#define QD_PHY_INT_ENABLE_REG 18 +#define QD_PHY_INT_STATUS_REG 19 +#define QD_PHY_INT_PORT_SUMMARY_REG 20 + +/* Bit Definition for QD_PHY_CONTROL_REG */ +#define QD_PHY_RESET 0x8000 +#define QD_PHY_LOOPBACK 0x4000 +#define QD_PHY_SPEED 0x2000 +#define QD_PHY_AUTONEGO 0x1000 +#define QD_PHY_POWER 0x800 +#define QD_PHY_ISOLATE 0x400 +#define QD_PHY_RESTART_AUTONEGO 0x200 +#define QD_PHY_DUPLEX 0x100 + +#define QD_PHY_POWER_BIT 11 +#define QD_PHY_RESTART_AUTONEGO_BIT 9 + +/* Bit Definition for QD_PHY_AUTONEGO_AD_REG */ +#define QD_PHY_NEXTPAGE 0x8000 +#define QD_PHY_REMOTEFAULT 0x4000 +#define QD_PHY_PAUSE 0x400 +#define QD_PHY_100_FULL 0x100 +#define QD_PHY_100_HALF 0x80 +#define QD_PHY_10_FULL 0x40 +#define QD_PHY_10_HALF 0x20 + +#define QD_PHY_MODE_AUTO_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF | QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_100_AUTO (QD_PHY_100_FULL | QD_PHY_100_HALF) +#define QD_PHY_MODE_10_AUTO (QD_PHY_10_FULL | QD_PHY_10_HALF) +#define QD_PHY_MODE_AUTO_FULL (QD_PHY_100_FULL | QD_PHY_10_FULL) +#define QD_PHY_MODE_AUTO_HALF (QD_PHY_100_HALF | QD_PHY_10_HALF) + +#define QD_PHY_MODE_100_FULL QD_PHY_100_FULL +#define QD_PHY_MODE_100_HALF QD_PHY_100_HALF +#define QD_PHY_MODE_10_FULL QD_PHY_10_FULL +#define QD_PHY_MODE_10_HALF QD_PHY_10_HALF + +/* Bit definition for QD_PHY_INT_ENABLE_REG */ +#define QD_PHY_INT_SPEED_CHANGED 0x4000 +#define QD_PHY_INT_DUPLEX_CHANGED 0x2000 +#define QD_PHY_INT_PAGE_RECEIVED 0x1000 +#define QD_PHY_INT_AUTO_NEG_COMPLETED 0x800 +#define QD_PHY_INT_LINK_STATUS_CHANGED 0x400 +#define QD_PHY_INT_SYMBOL_ERROR 0x200 +#define QD_PHY_INT_FALSE_CARRIER 0x100 +#define QD_PHY_INT_FIFO_FLOW 0x80 +#define QD_PHY_INT_CROSSOVER_CHANGED 0x40 +#define QD_PHY_INT_POLARITY_CHANGED 0x2 +#define QD_PHY_INT_JABBER 0x1 + +#endif /* __qdSimRegsh */ diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/ev96122mii.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/ev96122mii.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/ev96122mii.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/ev96122mii.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,213 @@ +#include +/******************************************************************************** +* ev96122mii.c +* +* DESCRIPTION: +* SMI access routines for EV-96122 board +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include + +/* + * For each platform, all we need is + * 1) Assigning functions into + * fgtReadMii : to read MII registers, and + * fgtWriteMii : to write MII registers. + * + * 2) Register Interrupt (Not Defined Yet.) +*/ + +/* + * EV-96122 Specific Definition +*/ + +#define SMI_OP_CODE_BIT_READ 1 +#define SMI_OP_CODE_BIT_WRITE 0 +#define SMI_BUSY 1<<28 +#define READ_VALID 1<<27 + +#ifdef FIREFOX +#define ETHER_SMI_REG 0x10 +#define internalRegBaseAddr 0x80008000 +#define NONE_CACHEABLE 0x00000000 +#define CACHEABLE 0x00000000 +#define SMI_RX_TIMEOUT 1000 +#else +#define ETHER_SMI_REG 0x080810 +#define internalRegBaseAddr 0x14000000 +#define NONE_CACHEABLE 0xa0000000 +#define CACHEABLE 0x80000000 +#define SMI_RX_TIMEOUT 10000000 +#endif + +typedef unsigned int SMI_REG; + +#ifdef LE /* Little Endian */ +#define SHORT_SWAP(X) (X) +#define WORD_SWAP(X) (X) +#define LONG_SWAP(X) ((l64)(X)) + +#else /* Big Endian */ +#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) + +#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ + (((X)&0xff00)<<8)+ \ + (((X)&0xff0000)>>8)+ \ + (((X)&0xff000000)>>24) + +#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ + (((X)&0xff00ULL)<<40)+ \ + (((X)&0xff0000ULL)<<24)+ \ + (((X)&0xff000000ULL)<<8)+ \ + (((X)&0xff00000000ULL)>>8)+ \ + (((X)&0xff0000000000ULL)>>24)+ \ + (((X)&0xff000000000000ULL)>>40)+ \ + (((X)&0xff00000000000000ULL)>>56)) + +#endif + +#define GT_REG_READ(offset, pData) \ +*pData = ( (volatile unsigned int)*((unsigned int *) \ + (NONE_CACHEABLE | internalRegBaseAddr | (offset))) ); \ +*pData = WORD_SWAP(*pData) + +#define GT_REG_WRITE(offset, data) \ +(volatile unsigned int)*((unsigned int *)(NONE_CACHEABLE | \ + internalRegBaseAddr | (offset))) = WORD_SWAP(data) + +typedef enum _bool{false,true} bool; + +/***************************************************************************** +* +* bool etherReadMIIReg (unsigned int portNumber , unsigned int MIIReg, +* unsigned int* value) +* +* Description +* This function will access the MII registers and will read the value of +* the MII register , and will retrieve the value in the pointer. +* Inputs +* portNumber - one of the 2 possiable Ethernet ports (0-1). +* MIIReg - the MII register offset. +* Outputs +* value - pointer to unsigned int which will receive the value. +* Returns Value +* true if success. +* false if fail to make the assignment. +* Error types (and exceptions if exist) +*/ + +GT_BOOL gtBspReadMii (GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value) +{ +SMI_REG smiReg; +unsigned int phyAddr; +unsigned int timeOut = 10; /* in 100MS units */ +int i; + +/* first check that it is not busy */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(smiReg & SMI_BUSY) + { + for(i = 0 ; i < SMI_RX_TIMEOUT ; i++); + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (smiReg & SMI_BUSY); + } +/* not busy */ + + phyAddr = portNumber; + + smiReg = (phyAddr << 16) | (SMI_OP_CODE_BIT_READ << 26) | (MIIReg << 21) | + SMI_OP_CODE_BIT_READ<<26; + + GT_REG_WRITE (ETHER_SMI_REG,*((unsigned int*)&smiReg)); + timeOut = 10; /* initialize the time out var again */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(!(smiReg & READ_VALID)) + { + i=0; + while(i < SMI_RX_TIMEOUT) + { + i++; + } + { + } + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (!(smiReg & READ_VALID)); + } + *value = (unsigned int)(smiReg & 0xffff); + + return true; + + +} + +/***************************************************************************** +* +* bool etherWriteMIIReg (unsigned int portNumber , unsigned int MIIReg, +* unsigned int value) +* +* Description +* This function will access the MII registers and will write the value +* to the MII register. +* Inputs +* portNumber - one of the 2 possiable Ethernet ports (0-1). +* MIIReg - the MII register offset. +* value -the value that will be written. +* Outputs +* Returns Value +* true if success. +* false if fail to make the assignment. +* Error types (and exceptions if exist) +*/ + +GT_BOOL gtBspWriteMii (GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int value) +{ +SMI_REG smiReg; +unsigned int phyAddr; +unsigned int timeOut = 10; /* in 100MS units */ +int i; + +/* first check that it is not busy */ + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(smiReg & SMI_BUSY) + { + for(i = 0 ; i < SMI_RX_TIMEOUT ; i++); + do { + GT_REG_READ (ETHER_SMI_REG,(unsigned int*)&smiReg); + if(timeOut-- < 1 ) { + return false; + } + } while (smiReg & SMI_BUSY); + } +/* not busy */ + + phyAddr = portNumber; + + smiReg = 0; /* make sure no garbage value in reserved bits */ + smiReg = smiReg | (phyAddr << 16) | (SMI_OP_CODE_BIT_WRITE << 26) | + (MIIReg << 21) | (value & 0xffff); + + GT_REG_WRITE (ETHER_SMI_REG,*((unsigned int*)&smiReg)); + + return(true); +} + + +void gtBspMiiInit(GT_QD_DEV* dev) +{ + return; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msApiInit.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msApiInit.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msApiInit.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msApiInit.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,115 @@ +#include +/******************************************************************************** +* msApiInit.c +* +* DESCRIPTION: +* MS API initialization routine +* +* DEPENDENCIES: Platform +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" +/* +#define MULTI_ADDR_MODE +#define MANUAL_MODE +*/ + +GT_SYS_CONFIG cfg; +GT_QD_DEV diagDev; +GT_QD_DEV *dev=&diagDev; + + +/* + * Initialize the QuarterDeck. This should be done in BSP driver init routine. + * Since BSP is not combined with QuarterDeck driver, we are doing here. +*/ + +GT_STATUS qdStart(int cpuPort, int useQdSim, int devId) /* devId is used for simulator only */ +{ +GT_STATUS status; + + /* + * Register all the required functions to QuarterDeck Driver. + */ + memset((char*)&cfg,0,sizeof(GT_SYS_CONFIG)); + memset((char*)&diagDev,0,sizeof(GT_QD_DEV)); + + if(useQdSim == 0) /* use EV-96122 */ + { + cfg.BSPFunctions.readMii = gtBspReadMii; + cfg.BSPFunctions.writeMii = gtBspWriteMii; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + gtBspMiiInit(dev); + } + else /* use QuaterDeck Simulator (No QD Device Required.) */ + { + cfg.BSPFunctions.readMii = qdSimRead; + cfg.BSPFunctions.writeMii = qdSimWrite; +#ifdef USE_SEMAPHORE + cfg.BSPFunctions.semCreate = osSemCreate; + cfg.BSPFunctions.semDelete = osSemDelete; + cfg.BSPFunctions.semTake = osSemWait; + cfg.BSPFunctions.semGive = osSemSignal; +#else + cfg.BSPFunctions.semCreate = NULL; + cfg.BSPFunctions.semDelete = NULL; + cfg.BSPFunctions.semTake = NULL; + cfg.BSPFunctions.semGive = NULL; +#endif + + qdSimInit(devId,0); + } + + cfg.initPorts = GT_TRUE; /* Set switch ports to Forwarding mode. If GT_FALSE, use Default Setting. */ + cfg.cpuPortNum = cpuPort; +#ifdef MANUAL_MODE /* not defined. this is only for sample */ + /* user may want to use this mode when there are two QD switchs on the same MII bus. */ + cfg.mode.scanMode = SMI_MANUAL_MODE; /* Use QD located at manually defined base addr */ + cfg.mode.baseAddr = 0x10; /* valid value in this case is either 0 or 0x10 */ +#else +#ifdef MULTI_ADDR_MODE + cfg.mode.scanMode = SMI_MULTI_ADDR_MODE; /* find a QD in indirect access mode */ + cfg.mode.baseAddr = 1; /* this is the phyAddr used by QD family device. + Valid value are 1 ~ 31.*/ +#else + cfg.mode.scanMode = SMI_AUTO_SCAN_MODE; /* Scan 0 or 0x10 base address to find the QD */ + cfg.mode.baseAddr = 0; +#endif +#endif + if((status=qdLoadDriver(&cfg, dev)) != GT_OK) + { + MSG_PRINT(("qdLoadDriver return Failed\n")); + return status; + } + + MSG_PRINT(("Device ID : 0x%x\n",dev->deviceId)); + MSG_PRINT(("Base Reg Addr : 0x%x\n",dev->baseRegAddr)); + MSG_PRINT(("No of Ports : %d\n",dev->numOfPorts)); + MSG_PRINT(("CPU Ports : %d\n",dev->cpuPortNum)); + + /* + * start the QuarterDeck + */ + if((status=sysEnable(dev)) != GT_OK) + { + MSG_PRINT(("sysConfig return Failed\n")); + return status; + } + + MSG_PRINT(("QuarterDeck has been started.\n")); + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msSample.h u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msSample.h --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msSample.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/msSample.h 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,147 @@ +#include +/******************************************************************************** +* msSample.h +* +* DESCRIPTION: +* Types definitions for Sample program +* +* DEPENDENCIES: Platform. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifndef __pfTesth +#define __pfTesth + +#ifdef _VXWORKS +#include "vxWorks.h" +#include "logLib.h" +#endif +#include "stdio.h" +#include "stdarg.h" +#include "stdlib.h" +#include "time.h" +#include "string.h" + +#include "msApi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef GT_U32 (*GT_API_VOID) (GT_QD_DEV*); +typedef int (*GT_CMP_FUNC) (void*, int, int); + +typedef GT_STATUS (*GT_API_SET_BOOL) (GT_QD_DEV*, GT_BOOL); +typedef GT_STATUS (*GT_API_GET_BOOL) (GT_QD_DEV*, GT_BOOL*); + +typedef GT_STATUS (*GT_API_MAC_ADDR) (GT_QD_DEV*, GT_ETHERADDR*); + +typedef GT_STATUS (*GT_API_SET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL); +typedef GT_STATUS (*GT_API_GET_PORT_BOOL) (GT_QD_DEV*, GT_LPORT,GT_BOOL*); + +typedef GT_STATUS (*GT_API_SET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16); +typedef GT_STATUS (*GT_API_GET_PORT_U16) (GT_QD_DEV*, GT_LPORT,GT_U16*); + +typedef GT_STATUS (*GT_API_SET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32); +typedef GT_STATUS (*GT_API_GET_PORT_U32) (GT_QD_DEV*, GT_LPORT,GT_U32*); + +typedef GT_STATUS (*GT_API_SET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8); +typedef GT_STATUS (*GT_API_GET_PORT_U8) (GT_QD_DEV*, GT_LPORT,GT_U8*); + +typedef struct _TEST_API +{ + union + { + GT_API_SET_BOOL bool; + GT_API_MAC_ADDR mac; + GT_API_SET_PORT_BOOL port_bool; + GT_API_SET_PORT_U8 port_u8; + GT_API_SET_PORT_U16 port_u16; + GT_API_SET_PORT_U32 port_u32; + } setFunc; + + union + { + GT_API_GET_BOOL bool; + GT_API_MAC_ADDR mac; + GT_API_GET_PORT_BOOL port_bool; + GT_API_GET_PORT_U8 port_u8; + GT_API_GET_PORT_U16 port_u16; + GT_API_GET_PORT_U32 port_u32; + } getFunc; + +}TEST_API; + +typedef struct _TEST_STRUCT +{ + char strTest[16]; + GT_API_VOID testFunc; + GT_U32 testResults; +} TEST_STRUCT; + +#define MSG_PRINT(x) testPrint x + +#define TEST_MAC_ENTRIES 32 +typedef struct _TEST_ATU_ENTRY +{ + GT_ATU_ENTRY atuEntry[TEST_MAC_ENTRIES]; +}TEST_ATU_ENTRY; + +typedef struct _ATU_ENTRY_INFO +{ + GT_ATU_ENTRY atuEntry; + GT_U16 hash; + GT_U16 bucket; +} ATU_ENTRY_INFO; + +extern GT_SYS_CONFIG pfTestSysCfg; +extern ATU_ENTRY_INFO *gAtuEntry; +extern GT_QD_DEV *dev; + +GT_STATUS qdStart(int,int,int); +GT_STATUS qdSimSetPhyInt(unsigned int portNumber, unsigned short u16Data); +GT_STATUS qdSimSetGlobalInt(unsigned short u16Data); + +GT_STATUS testAll(GT_QD_DEV*); +void testPrint(char* format, ...); + +extern FGT_INT_HANDLER qdIntHandler; + +int vtuEntryCmpFunc(void* buf, int a, int b); +int atuEntryCmpFunc(void* buf, int a, int b); +GT_STATUS gtSort(int list[], GT_CMP_FUNC cmpFunc, void* buf, GT_U32 len); +GT_U16 createATUList(GT_QD_DEV *dev, TEST_ATU_ENTRY atuEntry[], GT_U16 entrySize, GT_U16 dbNumSize, + GT_U16 sameMacsInEachDb, GT_U16 bSize); +GT_STATUS testFillUpAtu(GT_QD_DEV *dev, ATU_ENTRY_INFO *atuEntry, GT_U8 atuSize, + GT_U8 dbNum, GT_U16 first2Bytes, GT_ATU_UC_STATE state); +GT_U16 runQDHash(GT_U8* eaddr, GT_U16 dbNum, int bSize, GT_U16* pHash, + GT_U16* preBucket, GT_U16* posBucket); +GT_STATUS testDisplayATUList(); + +#undef USE_SEMAPHORE + +#ifdef USE_SEMAPHORE +GT_SEM osSemCreate(GT_SEM_BEGIN_STATE state); +GT_STATUS osSemDelete(GT_SEM smid); +GT_STATUS osSemWait(GT_SEM smid, GT_U32 timeOut); +GT_STATUS osSemSignal(GT_SEM smid); +#endif + +GT_BOOL gtBspReadMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int* value); +GT_BOOL gtBspWriteMii ( GT_QD_DEV* dev, unsigned int portNumber , unsigned int MIIReg, + unsigned int value); +void gtBspMiiInit(); + +GT_BOOL qdSimRead (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL qdSimWrite (GT_QD_DEV* dev,unsigned int portNumber , unsigned int miiReg, unsigned int value); +void qdSimInit(); + +#ifdef __cplusplus +} +#endif + +#endif /* __pfTesth */ + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/osSem.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/osSem.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/osSem.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/osSem.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,233 @@ +#include +/******************************************************************************** +* osSem.c +* +* DESCRIPTION: +* Semaphore related routines +* +* DEPENDENCIES: +* OS Dependent. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#ifdef _VXWORKS +#include "vxWorks.h" +#include "semLib.h" +#include "errnoLib.h" +#include "objLib.h" + +int sysClkRateGet(void); + +#elif defined(WIN32) +#include "windows.h" +#include "wdm.h" +#elif defined(LINUX) +#include "/usr/include/semaphore.h" +typedef sem_t semaphore ; +#endif + +#include + +GT_SEM osSemCreate( GT_SEM_BEGIN_STATE state); +GT_STATUS osSemDelete(GT_SEM smid); +GT_STATUS osSemWait( GT_SEM smid, GT_U32 timeOut); +GT_STATUS osSemSignal(GT_SEM smid); + +/******************************************************************************* +* osSemCreate +* +* DESCRIPTION: +* Create semaphore. +* +* INPUTS: +* name - semaphore Name +* init - init value of semaphore counter +* count - max counter (must be >= 1) +* +* OUTPUTS: +* smid - semaphore Id +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_SEM osSemCreate(GT_SEM_BEGIN_STATE state) +{ +#ifdef _VXWORKS +#if 0 + return (GT_SEM)semBCreate(SEM_Q_FIFO, state); +#else + GT_SEM semid; + semid =(GT_SEM)semBCreate(SEM_Q_FIFO, state); + return semid; +#endif + +#elif defined(WIN32) + return (GT_SEM)CreateSemaphore(NULL, state, 1, NULL); +#elif defined(LINUX) + semaphore lxSem; + + sem_init(&lxSem, state, 1); + return lxSem; +#else + return 1; +#endif + return GT_OK; +} + +/******************************************************************************* +* osSemDelete +* +* DESCRIPTION: +* Delete semaphore. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemDelete(GT_SEM smid) +{ +#ifdef _VXWORKS + STATUS rc; + + rc = semDelete((SEM_ID) smid); + if (rc != OK) + return GT_FAIL; + +#elif defined(WIN32) + if (CloseHandle((HANDLE)smid) == 0) + return GT_FAIL; + +#elif defined(LINUX) + sem_destroy((semaphore*) smid); +#else + return GT_OK; +#endif + + return GT_OK; +} + +/******************************************************************************* +* osSemWait +* +* DESCRIPTION: +* Wait on semaphore. +* +* INPUTS: +* smid - semaphore Id +* timeOut - time out in miliseconds or 0 to wait forever +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* OS_TIMEOUT - on time out +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemWait(GT_SEM smid, GT_U32 timeOut) +{ +#ifdef _VXWORKS + STATUS rc; + + if (timeOut == 0) + rc = semTake ((SEM_ID) smid, WAIT_FOREVER); + else + { + int num, delay; + + num = sysClkRateGet(); + delay = (num * timeOut) / 1000; + if (delay < 1) + rc = semTake ((SEM_ID) smid, 1); + else + rc = semTake ((SEM_ID) smid, delay); + } + + if (rc != OK) + { + if (errno == S_objLib_OBJ_TIMEOUT) + return GT_TIMEOUT; + else + return GT_FAIL; + } + +#elif defined(WIN32) + DWORD rc; + + rc = WaitForSingleObject((HANDLE)smid, timeOut); + + if (rc == WAIT_ABANDONED) + return GT_FAIL; + if (rc == WAIT_TIMEOUT) + return GT_TIMEOUT; + +#elif defined(LINUX) + sem_wait((semaphore*) smid) ; +#else + return GT_OK; + +#endif + + return GT_OK; +} + +/******************************************************************************* +* osSemSignal +* +* DESCRIPTION: +* Signal a semaphore. +* +* INPUTS: +* smid - semaphore Id +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS osSemSignal(GT_SEM smid) +{ +#ifdef _VXWORKS + STATUS rc; + rc = semGive ((SEM_ID) smid); + if (rc != OK) + return GT_FAIL; + +#elif defined(WIN32) + if(ReleaseSemaphore((HANDLE) smid, 1, NULL) == 0) + return GT_FAIL; + +#elif defined(LINUX) + sem_post((semaphore*) smid) ; +#else + return GT_OK; +#endif + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/qdSim.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/qdSim.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Initialization/qdSim.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Initialization/qdSim.c 2011-04-04 13:57:35.065597424 -0400 @@ -0,0 +1,2004 @@ +#include +/******************************************************************************** +* qdSim.c +* +* DESCRIPTION: +* Simulate QuaterDeck Device(88E6052)'s register map. When QuareterDeck API +* try to read/write a bit or bits into QuaterDeck, the simulator will redirect to +* its own memory place and performing the function very close to QuaterDeck. +* For example, +* 1) user can set/reset a certain bit of QuarterDeck registers(Phy,Port,and General registers). +* 2) user can access ATU (flush, load, purge, etc. with max MAC addresses of 32) +* 3) user can manually generate an Interrupt and test the Interrupt routine. +* 4) when user read a register, it will clear a certain register if it's a Self Clear register. +* 5) when user write a register, it will return ERROR if it's read only register. +* +* +* DEPENDENCIES: QuaterDeck (88E6052) Register MAP. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include +#include + +#define IS_BROADCAST_ADDR(_addr) \ + (((_addr)[0] == 0xFF) && ((_addr)[1] == 0xFF) && \ + ((_addr)[2] == 0xFF) && ((_addr)[3] == 0xFF) && \ + ((_addr)[4] == 0xFF) && ((_addr)[5] == 0xFF)) + +#define IS_GLOBAL_REG(_port) ((int)(_port) == qdSimDev.qdSimGlobalRegBase) +#define IS_PORT_REG(_port) (((int)(_port) >= qdSimDev.qdSimPortBase) && ((int)(_port) < qdSimDev.qdSimPortBase + qdSimDev.qdSimNumOfPorts)) +#define IS_PHY_REG(_port) (((int)(_port) >= qdSimDev.qdSimPhyBase) && ((int)(_port) < qdSimDev.qdSimPhyBase + qdSimDev.qdSimNumOfPhys)) + +typedef struct _QD_SIM_DEV +{ + int qdSimUsed; + unsigned int qdSimDevId; + int qdSimNumOfPorts; + int qdSimPortBase; + int qdSimNumOfPhys; + int qdSimPhyBase; + int qdSimGlobalRegBase; + int qdSimPortStatsClear[10]; + int qdSimStatsCapturedPort; + int vtuSize; + int atuSize; +} QD_SIM_DEV; + +static QD_SIM_DEV qdSimDev = {0}; + +void qdSimRegsInit(); +GT_BOOL qdSimRead (GT_QD_DEV *dev, unsigned int portNumber , unsigned int miiReg, unsigned int* value); +GT_BOOL qdSimWrite(GT_QD_DEV *dev, unsigned int portNumber , unsigned int miiReg, unsigned int value); + +/* + * This Array will simulate the QuarterDeck Registers. + * To use it, qdSimRegs has to be initialized with its default values and + * Call qdSimRead and qdSimWrite functions. +*/ +#define MAX_SMI_ADDRESS 0x20 +#define MAX_REG_ADDRESS 0x20 +#define MAX_ATU_ADDRESS 0x800 +#define MAX_QD_VTU_ENTRIES 0x40 + +GT_U16 qdSimRegs[MAX_SMI_ADDRESS][MAX_REG_ADDRESS]; + +typedef struct _QDSIM_ATU_ENTRY +{ + GT_U16 atuData; + GT_U16 DBNum; + GT_U8 atuMac[6]; +} QDSIM_ATU_ENTRY; + +/* + Since QuarterDeck Simulator supports only fixed size of atu entry, + we are going with array list not dynamic linked list. +*/ +typedef struct _QDSIM_ATU_NODE +{ + QDSIM_ATU_ENTRY atuEntry; + GT_U32 nextEntry; +} QDSIM_ATU_NODE; + +typedef struct _QDSIM_ATU_LIST +{ + int atuSize; + GT_U32 head; +} QDSIM_ATU_LIST; + +QDSIM_ATU_NODE ATUNode[MAX_ATU_ADDRESS]; +QDSIM_ATU_LIST ATUList; + +typedef struct _QDSIM_VTU_ENTRY +{ + GT_U16 DBNum; + GT_U16 memberTag[10]; + GT_U16 vid; +} QDSIM_VTU_ENTRY; + +/* + Since QuarterDeck Simulator supports only fixed size of atu entry, + we are going with array list not dynamic linked list. +*/ +typedef struct _QDSIM_VTU_NODE +{ + QDSIM_VTU_ENTRY vtuEntry; + GT_U32 nextEntry; +} QDSIM_VTU_NODE; + +typedef struct _QDSIM_VTU_LIST +{ + int vtuSize; + GT_U32 head; +} QDSIM_VTU_LIST; + +QDSIM_VTU_NODE VTUNode[MAX_QD_VTU_ENTRIES]; +QDSIM_VTU_LIST VTUList; + +/******************************************************************************* +* qdMemSet +* +* DESCRIPTION: +* Set a block of memory +* +* INPUTS: +* start - start address of memory block for setting +* simbol - character to store, converted to an unsigned char +* size - size of block to be set +* +* OUTPUTS: +* None +* +* RETURNS: +* Pointer to set memory block +* +* COMMENTS: +* None +* +*******************************************************************************/ +void * qdMemSet +( + IN void * start, + IN int symbol, + IN GT_U32 size +) +{ + GT_U32 i; + char* buf; + + buf = (char*)start; + + for(i=0; i src2. +* +* COMMENTS: +* None +* +*******************************************************************************/ +int qdMemCmp +( + IN char src1[], + IN char src2[], + IN GT_U32 size +) +{ + GT_U32 i; + int value; + + for(i=0; iatuMac)) + { + if(ATUList.atuSize != 0) + { + if (ATUNode[node].atuEntry.DBNum == entry->DBNum) + return node; + else + { + for(i=0; iDBNum) + return node; + node = ATUNode[node].nextEntry; + } + } + + } + return MAX_ATU_ADDRESS; + } + + for(i=0; iatuMac) > 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + break; + } + node = ATUNode[node].nextEntry; + } + + if (i == ATUList.atuSize) + return MAX_ATU_ADDRESS; + + return node; +} + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimATUAdd(QDSIM_ATU_ENTRY* entry) +{ + int i, freeNode, preNode, node; + + preNode = node = ATUList.head; + + if (ATUList.atuSize >= MAX_ATU_ADDRESS) + return GT_FALSE; + + /* find a free entry from our global memory. */ + for(i=0; iatuMac) >= 0) + break; + preNode = node; + node = ATUNode[node].nextEntry; + } + + /* if the same Mac address is in the list and dbnum is identical, then just update and return. */ + if (i != ATUList.atuSize) + if(cmpEtherMac(ATUNode[node].atuEntry.atuMac,entry->atuMac) == 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + { + ATUNode[node].atuEntry.atuData = entry->atuData; + return GT_TRUE; + } + } + + qdMemCpy(ATUNode[freeNode].atuEntry.atuMac, entry->atuMac, 6); + ATUNode[freeNode].atuEntry.atuData = entry->atuData; + ATUNode[freeNode].atuEntry.DBNum = entry->DBNum; + + /* Add it to head */ + if (i == 0) + { + ATUNode[freeNode].nextEntry = ATUList.head; + ATUList.head = freeNode; + } + /* Add it to tail */ + else if (i == ATUList.atuSize) + { + ATUNode[preNode].nextEntry = freeNode; + ATUNode[freeNode].nextEntry = ATUList.head; + } + /* Add it in the middle of the list */ + else + { + ATUNode[freeNode].nextEntry = ATUNode[preNode].nextEntry; + ATUNode[preNode].nextEntry = freeNode; + } + ATUList.atuSize++; + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimATUDel(QDSIM_ATU_ENTRY* entry) +{ + int i, preNode, node; + + preNode = node = ATUList.head; + + /* find the entry */ + for(i=0; iatuMac) == 0) + { + if(ATUNode[node].atuEntry.DBNum == entry->DBNum) + break; + } + preNode = node; + node = ATUNode[node].nextEntry; + } + + if (i == ATUList.atuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Delete it from head */ + if (i == 0) + { + ATUList.head = ATUNode[node].nextEntry; + } + /* Delete it in the middle of the list */ + else if (i != ATUList.atuSize-1) + { + ATUNode[preNode].nextEntry = ATUNode[node].nextEntry; + } + ATUList.atuSize--; + ATUNode[node].nextEntry = MAX_ATU_ADDRESS; + + return GT_TRUE; +} + + +GT_BOOL qdSimATUFlushUnlockedEntry() +{ + int i; + + for (i=0; iatuData = qdSimRegs[qdSimDev.qdSimGlobalRegBase][12]; + entry->atuMac[0] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] >> 8) & 0xFF; + entry->atuMac[1] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] & 0xFF; + entry->atuMac[2] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] >> 8) & 0xFF; + entry->atuMac[3] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] & 0xFF; + entry->atuMac[4] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] >> 8) & 0xFF; + entry->atuMac[5] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] & 0xFF; + entry->DBNum = qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] & 0xF; + return; +} + +void qdSimSetATUInfo(QDSIM_ATU_ENTRY* entry) +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][12] = entry->atuData; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] = (entry->atuMac[0]<<8) | entry->atuMac[1]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] = (entry->atuMac[2]<<8) | entry->atuMac[3]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] = (entry->atuMac[4]<<8) | entry->atuMac[5]; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (entry->DBNum & 0xF); + + return; +} + +void qdSimReSetATUInfo() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][12] = 0; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][13] = 0xFFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][14] = 0xFFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][15] = 0xFFFF; + + return; +} + +GT_BOOL qdSimATUOperation(unsigned int value) +{ + QDSIM_ATU_ENTRY entry; + int index; + + switch((value & 0x7000) >> 12) + { + case 1: + /* Flush ALL */ + qdSimATUInit(); + break; + case 2: + /* Flush all unlocked entries */ + return qdSimATUFlushUnlockedEntry(); + case 3: + /* Load or Purge entry */ + qdSimGetATUInfo(&entry); + if(entry.atuData & 0xF) + return qdSimATUAdd(&entry); + else + return qdSimATUDel(&entry); + break; + case 4: + /* Get Next Entry */ + qdSimGetATUInfo(&entry); + index = qdSimATUFindNext(&entry); + if (index == MAX_ATU_ADDRESS) + { + qdSimReSetATUInfo(); + return GT_TRUE; + } + else + { + qdSimSetATUInfo(&ATUNode[index].atuEntry); + return GT_TRUE; + } + break; + case 5: + /* Flush ALL in a DBNum */ + return qdSimATUFlushInDB(value & 0xF); + break; + case 6: + /* Flush all unlocked entries */ + return qdSimATUFlushUnlockedInDB(value & 0xF); + default: + break; + } + return GT_TRUE; +} + +/* + VTU Related Routines +*/ + +/* + entry index, if found. + MAX_QD_VTU_ENTRIES, otherwise. +*/ +int qdSimVTUFindNext(QDSIM_VTU_ENTRY* entry) +{ + int i; + int node = VTUList.head; + + if (entry->vid == 0xFFF) + { + if(VTUList.vtuSize != 0) + return node; + else + return MAX_QD_VTU_ENTRIES; + } + + for(i=0; i entry->vid) + break; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + return MAX_QD_VTU_ENTRIES; + + return node; +} + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUAdd(QDSIM_VTU_ENTRY* entry) +{ + int i, freeNode, preNode, node; + + preNode = node = VTUList.head; + + if (VTUList.vtuSize >= qdSimDev.vtuSize) + return GT_FALSE; + + /* find a free entry from our global memory. */ + for(i=0; i= entry->vid) + break; + preNode = node; + node = VTUNode[node].nextEntry; + } + + /* if the same vid is in the list, then just update and return. */ + if (i != VTUList.vtuSize) + if(VTUNode[node].vtuEntry.vid == entry->vid) + { + qdMemCpy(&VTUNode[node].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + return GT_TRUE; + } + + qdMemCpy(&VTUNode[freeNode].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + + /* Add it to head */ + if (i == 0) + { + VTUNode[freeNode].nextEntry = VTUList.head; + VTUList.head = freeNode; + } + /* Add it to tail */ + else if (i == VTUList.vtuSize) + { + VTUNode[preNode].nextEntry = freeNode; + VTUNode[freeNode].nextEntry = VTUList.head; + } + /* Add it in the middle of the list */ + else + { + VTUNode[freeNode].nextEntry = VTUNode[preNode].nextEntry; + VTUNode[preNode].nextEntry = freeNode; + } + VTUList.vtuSize++; + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUDel(QDSIM_VTU_ENTRY* entry) +{ + int i, preNode, node; + + preNode = node = VTUList.head; + + /* find the entry */ + for(i=0; ivid) + break; + preNode = node; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Delete it from head */ + if (i == 0) + { + VTUList.head = VTUNode[node].nextEntry; + } + /* Delete it in the middle of the list */ + else if (i != VTUList.vtuSize-1) + { + VTUNode[preNode].nextEntry = VTUNode[node].nextEntry; + } + VTUList.vtuSize--; + VTUNode[node].nextEntry = MAX_QD_VTU_ENTRIES; + + return GT_TRUE; +} + + +/* + Return 1, if added successfully. + Return 0, otherwise. +*/ +GT_BOOL qdSimVTUUpdate(QDSIM_VTU_ENTRY* entry) +{ + int i; + int node = VTUList.head; + + /* find the entry */ + for(i=0; ivid) + break; + node = VTUNode[node].nextEntry; + } + + if (i == VTUList.vtuSize) + { + /* cannot find the given entry to be deleted. */ + return GT_FALSE; + } + + /* Update the found entry */ + qdMemCpy(&VTUNode[node].vtuEntry, entry, sizeof(QDSIM_VTU_ENTRY)); + + return GT_TRUE; +} + +void qdSimVTUInit() +{ + int i; + + qdMemSet((char*)VTUNode, 0, sizeof(VTUNode)); + + /* MAX_ATU_ADDRESS means entry i is free, otherwise, it's not free */ + for (i=0; iDBNum = qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] & 0xF; + entry->vid = qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] & 0x1FFF; + entry->memberTag[0] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] & 0x3; + entry->memberTag[1] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 4) & 0x3; + entry->memberTag[2] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 8) & 0x3; + entry->memberTag[3] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] >> 12) & 0x3; + entry->memberTag[4] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] & 0x3; + entry->memberTag[5] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 4) & 0x3; + entry->memberTag[6] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 8) & 0x3; + entry->memberTag[7] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] >> 12) & 0x3; + entry->memberTag[8] = qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] & 0x3; + entry->memberTag[9] = (qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] >> 4) & 0x3; + + return; +} + +void qdSimSetVTUInfo(QDSIM_VTU_ENTRY* entry) +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= entry->DBNum; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = (entry->vid & 0xFFF) | 0x1000; + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = entry->memberTag[0] | + (entry->memberTag[1] << 4) | + (entry->memberTag[2] << 8) | + (entry->memberTag[3] << 12); + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = entry->memberTag[4] | + (entry->memberTag[5] << 4) | + (entry->memberTag[6] << 8) | + (entry->memberTag[7] << 12); + + qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] = entry->memberTag[8] | + (entry->memberTag[9] << 4); + + return; +} + +void qdSimReSetVTUInfo() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0xFFF; + + return; +} + +void qdSimVTUGetViolation() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xFFF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= 1; /* assume port 1 causes the violation */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 1; /* assume vid 1 causes the violation */ +} + +void qdSimVTUResetBusy() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0x8000; + + return; +} + +GT_BOOL qdSimVTUOperation(unsigned int value) +{ + QDSIM_VTU_ENTRY entry; + int index; + + if(!(value & 0x8000)) + return GT_FALSE; + + qdSimVTUResetBusy(); + + switch((value & 0x7000) >> 12) + { + case 1: + /* Flush ALL */ + qdSimVTUInit(); + break; + case 3: + /* Load or Purge entry */ + qdSimGetVTUInfo(&entry); + if(entry.vid & 0x1000) + { + entry.vid &= ~0x1000; + return qdSimVTUAdd(&entry); + } + else + return qdSimVTUDel(&entry); + break; + case 4: + /* Get Next Entry */ + qdSimGetVTUInfo(&entry); + entry.vid &= ~0x1000; + index = qdSimVTUFindNext(&entry); + if (index == MAX_QD_VTU_ENTRIES) + { + qdSimReSetVTUInfo(); + return GT_TRUE; + } + else + { + qdSimSetVTUInfo(&VTUNode[index].vtuEntry); + return GT_TRUE; + } + break; + case 7: + qdSimVTUGetViolation(); + break; + default: + break; + } + return GT_TRUE; +} + +void qdSimStatsInit() +{ + int i; + + for(i=0; i> 12) + { + case 1: + /* Flush ALL */ + for(i=0; i= (unsigned int)qdSimDev.qdSimNumOfPorts) + return GT_FALSE; + qdSimDev.qdSimPortStatsClear[value & 0x3F] = 1; + break; + case 4: + /* Read a counter */ + if(qdSimDev.qdSimPortStatsClear[qdSimDev.qdSimStatsCapturedPort] == 1) + { + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; + } + else + { + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = qdSimDev.qdSimStatsCapturedPort; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = value & 0x3F; + } + break; + case 5: + if ((value & 0x3F) >= (unsigned int)qdSimDev.qdSimNumOfPorts) + return GT_FALSE; + qdSimDev.qdSimStatsCapturedPort = value & 0x3F; + break; + default: + return GT_FALSE; + } + return GT_TRUE; +} + +#define QD_PHY_CONTROL_RW (QD_PHY_RESET|QD_PHY_LOOPBACK|QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_POWER|QD_PHY_RESTART_AUTONEGO|QD_PHY_DUPLEX) +#define QD_PHY_CONTROL_RO (~QD_PHY_CONTROL_RW) + +GT_BOOL qdSimPhyControl(unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + + /* reset all the Read Only bits. */ + value &= QD_PHY_CONTROL_RW; + + /* If powerDown is set, add Reset and Restart Auto bits. */ + if(value & QD_PHY_POWER) + { + value |= (QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + + /* If Power Down was set, clear Reset and Restart Auto bits. */ + if(qdSimRegs[portNumber][miiReg] & QD_PHY_POWER) + { + value &= ~(QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + + /* If Reset or Restart Auto set, replace with current value and clear Reset/Restart Auto. */ + if (value & (QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO)) + { + value &= ~(QD_PHY_RESET|QD_PHY_RESTART_AUTONEGO); + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; + } + else + { + value &= ~(QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_DUPLEX); + qdSimRegs[portNumber][miiReg] &= (QD_PHY_SPEED|QD_PHY_AUTONEGO|QD_PHY_DUPLEX); + qdSimRegs[portNumber][miiReg] |= (GT_U16)value; + return GT_TRUE; + } + + return GT_TRUE; +} + +void qdSimRegsInit_6021() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit_6063() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit_6083() +{ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] = 0; /* VTU Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][6] = 0; /* VTU VID Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][7] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][8] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][9] = 0; /* VTU Data Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][29] = 0; /* Stats Operation Register */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][30] = 0; /* Stats Counter Register Bytes 3,2 */ + qdSimRegs[qdSimDev.qdSimGlobalRegBase][31] = 0; /* Stats Counter Register Bytes 1,0 */ +} + +void qdSimRegsInit() +{ + int i; + + qdMemSet(qdSimRegs, 0xff, sizeof(qdSimRegs)); + + /* + PHY Registers Setup + */ + for(i=0; i= MAX_SMI_ADDRESS) + portNumber -= MAX_SMI_ADDRESS; + + if ((portNumber >= MAX_SMI_ADDRESS) || (miiReg >= MAX_REG_ADDRESS)) + return GT_FALSE; + + switch(qdSimDev.qdSimDevId) + { + case GT_88E6051: + case GT_88E6052: + return qdSimRead_6052(portNumber, miiReg, value); + case GT_88E6021: + return qdSimRead_6021(portNumber, miiReg, value); + case GT_88E6063: + case GT_FF_HG: + case GT_FF_EG: + case GT_FH_VPN: + return qdSimRead_6063(portNumber, miiReg, value); + case GT_88E6083: + return qdSimRead_6083(portNumber, miiReg, value); + default: + break; + } + + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6052 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6021 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 9) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + break; + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6063 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 12) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + +GT_BOOL qdSimWrite_6083 (unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + GT_BOOL status; + + if (IS_GLOBAL_REG(portNumber)) /* Global register */ + { + switch(miiReg) + { + case QD_REG_GLOBAL_STATUS: + /* readonly register */ + return GT_FALSE; + case QD_REG_MACADDR_01: + case QD_REG_MACADDR_23: + case QD_REG_MACADDR_45: + break; + case QD_REG_VTU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][5] |= (value & 0xF); + status = qdSimVTUOperation(value); + return status; + case QD_REG_VTU_VID_REG: + case QD_REG_VTU_DATA1_REG: + case QD_REG_VTU_DATA2_REG: + case QD_REG_VTU_DATA3_REG: + break; + case QD_REG_GLOBAL_CONTROL: + if(value & 0x200) + { + /* Reload EEPROM values */ + qdSimRegsInit(); + qdSimRegs[portNumber][QD_REG_GLOBAL_STATUS] |= 0x1; + return GT_TRUE; + } + break; + case QD_REG_ATU_CONTROL: + value &= ~0x8000; + break; + case QD_REG_ATU_OPERATION: + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] &= ~0xF; + qdSimRegs[qdSimDev.qdSimGlobalRegBase][11] |= (value & 0xF); + status = qdSimATUOperation(value); + return status; + case QD_REG_ATU_DATA_REG: + case QD_REG_ATU_MAC_01: + case QD_REG_ATU_MAC_23: + case QD_REG_ATU_MAC_45: + case QD_REG_IP_PRI_REG0: + case QD_REG_IP_PRI_REG1: + case QD_REG_IP_PRI_REG2: + case QD_REG_IP_PRI_REG3: + case QD_REG_IP_PRI_REG4: + case QD_REG_IP_PRI_REG5: + case QD_REG_IP_PRI_REG6: + case QD_REG_IP_PRI_REG7: + case QD_REG_IEEE_PRI: + break; + case QD_REG_STATS_OPERATION: + status = qdSimStatsOperation(value); + return status; + case QD_REG_STATS_COUNTER3_2: + case QD_REG_STATS_COUNTER1_0: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PORT_REG(portNumber)) /* Port registers */ + { + switch(miiReg) + { + case QD_REG_PORT_STATUS: + if(portNumber > 12) + { + qdSimRegs[portNumber][miiReg] &= ~QD_PORT_STATUS_DUPLEX; + qdSimRegs[portNumber][miiReg] |= (value & QD_PORT_STATUS_DUPLEX); + return GT_TRUE; + } + case QD_REG_SWITCH_ID: + /* readonly registers */ + return GT_FALSE; + case QD_REG_PORT_CONTROL: + case QD_REG_PORT_VLAN_MAP: + case QD_REG_PVID: + case QD_REG_RATE_CTRL: + case QD_REG_PAV: + break; + case QD_REG_RXCOUNTER: + case QD_REG_TXCOUNTER: + /* readonly registers */ + return GT_FALSE; + case QD_REG_Q_COUNTER: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else if(IS_PHY_REG(portNumber)) /* phy registers */ + { + switch(miiReg) + { + case QD_PHY_CONTROL_REG: + return qdSimPhyControl(portNumber,miiReg,value); + case QD_PHY_INT_ENABLE_REG: + case QD_PHY_AUTONEGO_AD_REG: + case QD_PHY_NEXTPAGE_TX_REG: + case QD_PHY_SPEC_CONTROL_REG: + break; + case QD_PHY_INT_STATUS_REG: + case QD_PHY_INT_PORT_SUMMARY_REG: + return GT_FALSE; + default: + return GT_FALSE; + } + } + else + return GT_FALSE; + + qdSimRegs[portNumber][miiReg] = (GT_U16)value; + return GT_TRUE; +} + + +GT_BOOL qdSimWrite (GT_QD_DEV *dev,unsigned int portNumber , unsigned int miiReg, unsigned int value) +{ + if (portNumber >= MAX_SMI_ADDRESS) + portNumber -= MAX_SMI_ADDRESS; + + if ((portNumber >= MAX_SMI_ADDRESS) || (miiReg >= MAX_REG_ADDRESS)) + return GT_FALSE; + + switch(qdSimDev.qdSimDevId) + { + case GT_88E6051: + case GT_88E6052: + return qdSimWrite_6052(portNumber, miiReg, value); + case GT_88E6021: + return qdSimWrite_6021(portNumber, miiReg, value); + case GT_88E6063: + case GT_FF_HG: + case GT_FF_EG: + case GT_FH_VPN: + return qdSimWrite_6063(portNumber, miiReg, value); + case GT_88E6083: + return qdSimWrite_6083(portNumber, miiReg, value); + + default: + break; + } + + return GT_TRUE; +} + +GT_STATUS qdSimSetPhyInt(unsigned int portNumber, unsigned short u16Data) +{ + if(!qdSimDev.qdSimUsed) + return GT_FAIL; + + qdSimRegs[portNumber][QD_PHY_INT_STATUS_REG] = u16Data; + if(u16Data) + qdSimRegs[0][QD_PHY_INT_PORT_SUMMARY_REG] |= (1< +/******************************************************************************** +* qdInt.c +* +* DESCRIPTION: +* This sample shows how to call QuarterDeck Interrupt handler when QD INT +* raised, and how to take care each Interrupt Cause. +* +* DEPENDENCIES: NONE. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + + +/* + * To enable quarterDeck interrupt, you need to call eventSetActive() and + * gprtPhyIntEnable(), as following sample routine. + * sampleQDIntEnable will enable all interrupt causes. + * For Port, GT_ATU_FULL, GT_ATU_DONE, GT_PHY_INTERRUPT, and GT_EE_INTERRUPT + * are enabled. + * + * In this sample, GT_SPEED_CHANGED, GT_DUPLEX_CHANGED, and + * GT_LINK_STATUS_CHANGED are enabled for ports 0 ~ 2. +*/ +GT_STATUS sampleQDIntEnable(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + GT_U16 data; + + /* + * Enable QuarterDeck interrupt for ATUFull, ATUDone, PHYInt, and EEInt. + * If writing 0 into eventSetActive(), all port interrupt will be disabled. + */ + data = GT_STATS_DONE|GT_VTU_PROB|GT_VTU_DONE| + GT_ATU_FULL|GT_ATU_DONE|GT_PHY_INTERRUPT|GT_EE_INTERRUPT; + if((status = eventSetActive(dev,data)) != GT_OK) + { + MSG_PRINT(("eventSetActive returned fail.\n")); + return status; + } + + /* + * Enable Phy interrupt for every possible interrupt cause. + * If writing 0 into gprtPhyIntEnable(), all port interrupt will be disabled. + */ + data = GT_SPEED_CHANGED|GT_DUPLEX_CHANGED|GT_LINK_STATUS_CHANGED; + + for(port=0; port<3; port++) + { + if((status = gprtPhyIntEnable(dev,port,data)) != GT_OK) + { + MSG_PRINT(("gprtPhyIntEnable returned fail.\n")); + return status; + } + } + + return GT_OK; +} + +/* + * Disable QuarterDeck Interrupt. +*/ +GT_STATUS sampleQDIntDisable(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + + /* + * Writing 0 into eventSetActive(), all port interrupt will be disabled. + */ + if((status = eventSetActive(dev,0)) != GT_OK) + { + MSG_PRINT(("eventSetActive returned fail.\n")); + return status; + } + + /* + * Writing 0 into gprtPhyIntEnable(), all port interrupt will be disabled. + */ + for(port=0; port<3; port++) + { + if((status = gprtPhyIntEnable(dev,port,0)) != GT_OK) + { + MSG_PRINT(("gprtPhyIntEnable returned fail.\n")); + return status; + } + } + return GT_OK; +} + + +/* + * Assume that the following function, sampleQDIntVector(), is registered + * when BSP calls intConnect for QD Interrupt. + * This sample will show how to deal with QuarterDeck Interrupt. +*/ +GT_STATUS sampleQDIntVector(GT_QD_DEV *dev) +{ + GT_U16 intCause, phyIntCause; + GT_U16 portVec; + GT_LPORT port; + GT_VTU_INT_STATUS vtuInt; + GT_ATU_INT_STATUS atuInt; + + /* + * Disable QuarterDeck Interrupt in System Level. + * ToDo... + */ + + /* + * Check if QD generated the interrupt. + */ + if(eventGetIntStatus(dev,&intCause) != GT_TRUE) + { + /* QD didn't generate the interrupt. */ + return GT_FAIL; + } + + /* + * QD generated interrupt with the reason in intCause. + */ + + if(intCause & GT_STATS_DONE) + { + /* + * Statistics Done Interrupt + * ToDo... + */ + + } + if(intCause & GT_VTU_DONE) + { + /* + * VTU Done Interrupt + * ToDo... + */ + + } + + if(intCause & GT_VTU_PROB) + { + /* + * Vlan Table Problem/Violation. + * Need to read the cause. + */ + do { + if(gvtuGetIntStatus(dev,&vtuInt) != GT_OK) + { + /* failed to retrieve VTU Interrupt cause */ + break; + } + + if(vtuInt.vtuIntCause & GT_VTU_FULL_VIOLATION) + { + /* + * Vlan Table is Full + * ToDo... + */ + } + + if(vtuInt.vtuIntCause & GT_MEMBER_VIOLATION) + { + /* + * Member Violation + * ToDo... + */ + } + + if(vtuInt.vtuIntCause & GT_MISS_VIOLATION) + { + /* + * Miss Violation + * ToDo... + */ + } + } while(vtuInt.vtuIntCause != 0); + } + + if(intCause & GT_ATU_PROB) + { + /* + * ATU cannot load or learn a new mapping due to all the available + * locations for an address being locked. + * ToDo... + */ + do { + if(gatuGetIntStatus(dev,&atuInt) != GT_OK) + { + /* failed to retrieve VTU Interrupt cause */ + break; + } + + if(atuInt.atuIntCause & GT_FULL_VIOLATION) + { + /* + * Table is Full + * ToDo... + */ + } + + if(atuInt.atuIntCause & GT_MEMBER_VIOLATION) + { + /* + * Member Violation + * ToDo... + */ + } + + if(atuInt.atuIntCause & GT_MISS_VIOLATION) + { + /* + * Miss Violation + * ToDo... + */ + } + } while(atuInt.atuIntCause != 0); + + } + + if(intCause & GT_ATU_DONE) + { + /* + * There is a transitions from a one to a zero on ATUBusy bit + * (Refer to ATU Operation Register.) + * ToDo... + */ + + } + + if(intCause & GT_PHY_INTERRUPT) + { + /* + * At least one of the Phy generated interrupt. + * We need to read Phy Interrupt Summary and go through each phy + * based on the summary. + */ + + if(gprtGetPhyIntPortSummary(dev,&portVec) != GT_OK) + { + return GT_FAIL; + } + + port = 0; + while(portVec) + { + if(portVec & 0x01) + { + /* + * Call gprtGetPhyIntStatus to get intCause + */ + if(gprtGetPhyIntStatus(dev,port,&phyIntCause) != GT_OK) + { + /* + * Something wrong with the system. Need to do the + * necessary work. + * ToDo... + */ + } + + if(phyIntCause & GT_SPEED_CHANGED) + { + /* + * Speed has been changed. + * ToDo... + */ + } + + if(phyIntCause & GT_DUPLEX_CHANGED) + { + /* + * Duplex mode has been changed. + * ToDo... + */ + } + + if(phyIntCause & GT_PAGE_RECEIVED) + { + /* + * Page received. + * ToDo... + */ + + } + + if(phyIntCause & GT_AUTO_NEG_COMPLETED) + { + /* + * AutoNegotiation completed. + * ToDo... + */ + + } + + if(phyIntCause & GT_LINK_STATUS_CHANGED) + { + /* + * Link Status changed. + * ToDo... + */ + + } + + if(phyIntCause & GT_SYMBOL_ERROR) + { + /* + * Symbol error + * ToDo... + */ + + } + + if(phyIntCause & GT_FALSE_CARRIER) + { + /* + * False Carrier. + * ToDo... + */ + + } + + if(phyIntCause & GT_FIFO_FLOW) + { + /* + * Fifo Overflow/underflow error + * ToDo... + */ + + } + + if(phyIntCause & GT_CROSSOVER_CHANGED) + { + /* + * MDI/MDIX crossover changed. + * ToDo... + */ + + } + + if(phyIntCause & GT_POLARITY_CHANGED) + { + /* + * Polarity changed. + * ToDo... + */ + + } + + if(phyIntCause & GT_JABBER) + { + /* + * Jabber + * ToDo... + */ + + } + } + + portVec >>= 1; + port++; + } + } + + if(intCause & GT_EE_INTERRUPT) + { + /* + * EEPROM is done loading registers. + * ToDo... + */ + + } + + + /* + * Now, all the QuarterDeck related interrupt have been cleared, + * so it's OK to enable QuarterDeck Interrupt in System Level. + * ToDo... + */ + + return GT_OK; + +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Interrupt/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Interrupt/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Interrupt/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Interrupt/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,20 @@ +======================================================================== + QuaterDeck Interrupt Handler called by BSP Interrupt Vector +======================================================================== + +This sample shows how to enable/disable QuaterDeck Interrupt, and how to +handle each Interrupt. + +qdInt.c + sampleQDIntEnable() will enable all the interrupt supported by + QuaterDeck. + sampleQDIntDisable() will disable QuarterDeck Interrupt. + sampleQDIntVector() will show how BSP interrupt service routine can + deal with QuarterDeck Interrupt. + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/loadBalance.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/loadBalance.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/loadBalance.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/loadBalance.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,57 @@ +#include +/******************************************************************************** +* loadBalance.c +* +* DESCRIPTION: +* This sample shows how to setup load balance among Trunk ports. +* In this sample, port 0,1,2, and 3 will be in the Trunk group. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + + +/* + The following sample sets Trunk Mask Table as follows: + + 10 9 8 7 6 5 4 3 2 1 0 + TrunkMask[0] 1 1 1 1 1 1 1 0 0 0 1 + TrunkMask[1] 1 1 1 1 1 1 1 0 0 1 0 + TrunkMask[2] 1 1 1 1 1 1 1 0 1 0 0 + TrunkMask[3] 1 1 1 1 1 1 1 1 0 0 0 + TrunkMask[4] 1 1 1 1 1 1 1 0 0 0 1 + TrunkMask[5] 1 1 1 1 1 1 1 0 0 1 0 + TrunkMask[6] 1 1 1 1 1 1 1 0 1 0 0 + TrunkMask[7] 1 1 1 1 1 1 1 1 0 0 0 +*/ + +GT_STATUS sampleLoadBalance(GT_QD_DEV *dev) +{ + GT_STATUS status; + int i; + GT_U32 mask, baseMask; + + baseMask = 0xFFF0; /* clear bits for port 0 ~ 3 */ + + /* + * Set the trunk mask table for load balancing. + */ + for(i=0; i<8; i++) + { + mask = baseMask | (1 << (i%4)); + + if((status = gsysSetTrunkMaskTable(dev,i,mask)) != GT_OK) + { + MSG_PRINT(("gsysSetTrunkMaskTable return Failed\n")); + return status; + } + } + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/LoadBalance/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,16 @@ +======================================================================== + Setup for Load Balancing +======================================================================== + +This sample shows how to setup Trunk Mask Table for load balancing. +For more information about load balancing, please refer to 88E6095 Spec. + +loadBalance.c + sampleLoadBalance demonstrates how to setup Trunk Mask Table. + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/macAddr.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/macAddr.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/macAddr.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/macAddr.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,223 @@ +#include +/******************************************************************************** +* macAddr.c +* +* DESCRIPTION: +* This sample will demonstrate how to add/delete a static MAC Address +* into/from the QuaterDeck MAC Address Data Base. +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +/* + * Add the CPU MAC address into the QuaterDeck MAC Address database. + * Input - None +*/ +GT_STATUS sampleAddCPUMac(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY macEntry; + + /* + * Assume that Ethernet address for the CPU MAC is + * 00-50-43-00-01-02. + */ + macEntry.macAddr.arEther[0] = 0x00; + macEntry.macAddr.arEther[1] = 0x50; + macEntry.macAddr.arEther[2] = 0x43; + macEntry.macAddr.arEther[3] = 0x00; + macEntry.macAddr.arEther[4] = 0x01; + macEntry.macAddr.arEther[5] = 0x02; + + macEntry.portVec = 1 << dev->cpuPortNum; /* CPU Port number. 7bits are used for portVector. */ + + macEntry.prio = 0; /* Priority (2bits). When these bits are used they override + any other priority determined by the frame's data. This value is + meaningful only if the device does not support extended priority + information such as MAC Queue Priority and MAC Frame Priority */ + + macEntry.exPrio.macQPri = 0; /* If device doesnot support MAC Queue Priority override, + this field is ignored. */ + macEntry.exPrio.macFPri = 0; /* If device doesnot support MAC Frame Priority override, + this field is ignored. */ + macEntry.exPrio.useMacFPri = 0; /* If device doesnot support MAC Frame Priority override, + this field is ignored. */ + + macEntry.entryState.ucEntryState = GT_UC_STATIC; + /* This address is locked and will not be aged out. + Refer to GT_ATU_UC_STATE in msApiDefs.h for other option. */ + + /* + * Add the MAC Address. + */ + if((status = gfdbAddMacEntry(dev,&macEntry)) != GT_OK) + { + MSG_PRINT(("gfdbAddMacEntry returned fail.\n")); + return status; + } + + return GT_OK; +} + + +/* + * Delete the CPU MAC address from the QuaterDeck MAC Address database. + * Input - None +*/ +GT_STATUS sampleDelCPUMac(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY macEntry; + + /* + * Assume that Ethernet address for the CPU MAC is + * 00-50-43-00-01-02. + */ + macEntry.macAddr.arEther[0] = 0x00; + macEntry.macAddr.arEther[1] = 0x50; + macEntry.macAddr.arEther[2] = 0x43; + macEntry.macAddr.arEther[3] = 0x00; + macEntry.macAddr.arEther[4] = 0x01; + macEntry.macAddr.arEther[5] = 0x02; + + /* + * Delete the CPU MAC Address. + */ + if((status = gfdbDelMacEntry(dev,&macEntry.macAddr)) != GT_OK) + { + MSG_PRINT(("gfdbDelMacEntry returned fail.\n")); + return status; + } + + return GT_OK; +} + + +/* + * Add a multicast MAC address into the QuaterDeck MAC Address database, + * where address is 01-00-18-1a-00-00 and frames with this destination has + * to be forwarding to Port 1, Port 2 and Port 4 (port starts from Port 0) + * Input - None +*/ +GT_STATUS sampleAddMulticastAddr(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY macEntry; + + /* + * Assume that we want to add the following multicast address + * 01-50-43-00-01-02. + */ + macEntry.macAddr.arEther[0] = 0x01; + macEntry.macAddr.arEther[1] = 0x50; + macEntry.macAddr.arEther[2] = 0x43; + macEntry.macAddr.arEther[3] = 0x00; + macEntry.macAddr.arEther[4] = 0x01; + macEntry.macAddr.arEther[5] = 0x02; + + /* + * Assume that a packet needs to be forwarded to the second Port (port 1), + * the third Port (port 2) and cpu Port, if the frame has destination of + * 01-00-18-1a-00-00. + */ + macEntry.portVec = (1<<1) | /* the second port */ + (1<<2) | /* the third port */ + (1<cpuPortNum); + + macEntry.prio = 0; /* Priority (2bits). When these bits are used they override + any other priority determined by the frame's data. This value is + meaningful only if the device does not support extended priority + information such as MAC Queue Priority and MAC Frame Priority */ + + macEntry.exPrio.macQPri = 0; /* If device doesnot support MAC Queue Priority override, + this field is ignored. */ + macEntry.exPrio.macFPri = 0; /* If device doesnot support MAC Frame Priority override, + this field is ignored. */ + macEntry.exPrio.useMacFPri = 0; /* If device doesnot support MAC Frame Priority override, + this field is ignored. */ + + macEntry.entryState.ucEntryState = GT_MC_STATIC; + /* This address is locked and will not be aged out. + Refer to GT_ATU_MC_STATE in msApiDefs.h for other option.*/ + + /* + * Add the MAC Address. + */ + if((status = gfdbAddMacEntry(dev,&macEntry)) != GT_OK) + { + MSG_PRINT(("gfdbAddMacEntry returned fail.\n")); + return status; + } + + return GT_OK; +} + + +/* + * Delete the Multicast MAC address of 01-00-18-1a-00-00. + * Input - None +*/ +GT_STATUS sampleDelMulticastAddr(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY macEntry; + + /* + * Assume that Ethernet address for the CPU MAC is + * 01-50-43-00-01-02. + */ + macEntry.macAddr.arEther[0] = 0x01; + macEntry.macAddr.arEther[1] = 0x50; + macEntry.macAddr.arEther[2] = 0x43; + macEntry.macAddr.arEther[3] = 0x00; + macEntry.macAddr.arEther[4] = 0x01; + macEntry.macAddr.arEther[5] = 0x02; + + /* + * Delete the given Multicast Address. + */ + if((status = gfdbDelMacEntry(dev,&macEntry.macAddr)) != GT_OK) + { + MSG_PRINT(("gfdbDelMacEntry returned fail.\n")); + return status; + } + + return GT_OK; +} + + +/* + * This sample function will show how to display all the MAC address + * in the ATU. +*/ +GT_STATUS sampleShowMacEntry(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_ATU_ENTRY tmpMacEntry; + + MSG_PRINT(("ATU List:\n")); + memset(&tmpMacEntry,0,sizeof(GT_ATU_ENTRY)); + + while(1) + { + /* Get the sorted list of MAC Table. */ + if((status = gfdbGetAtuEntryNext(dev,&tmpMacEntry)) != GT_OK) + { + return status; + } + + MSG_PRINT(("(%02x-%02x-%02x-%02x-%02x-%02x) PortVec %#x\n", + tmpMacEntry.macAddr.arEther[0], + tmpMacEntry.macAddr.arEther[1], + tmpMacEntry.macAddr.arEther[2], + tmpMacEntry.macAddr.arEther[3], + tmpMacEntry.macAddr.arEther[4], + tmpMacEntry.macAddr.arEther[5], + tmpMacEntry.portVec)); + } + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MACAddress/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,21 @@ +======================================================================== + MAC Address ADD/DELETE Sample +======================================================================== + +This sample will demonstrate how to add/delete a static MAC Address +into/from the QuaterDeck MAC Address Data Base and how to enumerate +all the MAC addresses in the Data Base. + +macAddr.c + sampleAddCPUMac : show how to add CPU Mac address into the QuterDeck + Database. + sampleDelCPUMac : show how to delete CPU Mac address from the database. + sampleAddMulticastAddr : show how to add a multicast address into + the QuaterDeck Database. + sampleDelMulticastAddr : show how to delete a multicast address. + sampleShowMacEntry : show how to get all the Mac addresses in the database. + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/makefile u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/makefile --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/makefile 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,53 @@ +# makefile - build main object file +# +# modification history +# -------------------- +# 04-15-02,mj created +# +####################################################################### + +DEMONAME = sample +WORK_TO_DO = $(DEMONAME).o + +exe : $(WORK_TO_DO) + +# Include common variable definitions +include $(TOOL_DIR)\make.defs + +.PHONY : exe + +QDLIB = $(LIB_DIR)/$(PROJ_NAME).o + +OBJDIRS = $(subst /,\,$(dir $(QDLIB))) + +CSOURCES = FlowControl/flowCtrl.c Initialization/osSem.c Initialization/ev96122mii.c \ + Initialization/qdSim.c Initialization/msApiInit.c \ + MACAddress/macAddr.c QoSSetup/qos.c VlanSetup/hgVlan.c Interrupt/qdInt.c \ + Trailer/trailer.c RMON/rmon.c 802.1Q/802_1q.c Header/header.c \ + CableTest/cableTest.c CableTest/advCableTest.c PortMonitor/portMonitor.c MultiDevice/msApiInit.c \ + CrossChipTrunk/crossChipTrunk.c MinimizeCPUTraffic\minimizeCPUTraffic.c \ + PktGen/phyPktGenSample.c PIRL/pirl.c PIRL/pirl2.c ptp/ptp.c + +EXTRA_INCLUDE = -I./Include -I./Initialization +COBJECTS = $(CSOURCES:.c=.o) +AOBJECTS = $(ASOURCES:.s=.o) +ifeq ($(OBJECTS),) +OBJECTS = $(COBJECTS) $(AOBJECTS) +endif + +OBJECTS_MS= $(subst /,\,$(OBJECTS)) + +$(DEMONAME).o : $(OBJECTS) $(QDLIB) + $(LD) $(LDFLAGS) -Map $(DEMONAME).map -o $(DEMONAME).o $(OBJECTS) $(QDLIB) + +$(OBJECTS) : %.o : %.c +.c.o : + $(CC) $(CFLAGS) $(EXTRA_DEFINE) $(EXTRA_INCLUDE) $(ADDED_CFLAGS) -c $< -o $@ + +.PHONY : clean +clean : + @for %x in ($(OBJECTS_MS)) do \ + $(RM) %x + $(RM) $(DEMONAME).* + +#end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/minimizeCPUTraffic.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/minimizeCPUTraffic.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/minimizeCPUTraffic.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/minimizeCPUTraffic.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,186 @@ +#include +/******************************************************************************** +* minizeCPUTraffic.c +* +* DESCRIPTION: +* This sample shows how to setup the CPU port not to be a member of any +* VLAN, while it still be a manager of a switch. +* +* DEPENDENCIES: +* Please check the device's spec. if the device supports this feature. +* At the moment this sample was written, 88E6095 was the only device support +* this feature. +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + +/* + For the devices that support gsysSetARPDest API: + + 0) Remove CPU port from VLAN Member Table. + (this sample deals with Port Based Vlan only.) + 1) Mirror ARPs to the CPU with To_CPU Marvell Tag + 2) Convert unicast frames directed to the CPU into To_CPU Marvell Tag + Assumption : Device ID, Cascading Port, CPU Port, and Interswitch Port are + already set properly. For more information, please refer to the + sample/MultiDevice/msApiInit.c +*/ + +GT_STATUS sampleMinimizeCPUTraffic1(GT_QD_DEV *dev, GT_U8* macAddr) +{ + GT_STATUS status; + int i; + GT_LPORT memPorts[16], cpuPort; + GT_U8 memPortsLen, index; + GT_ATU_ENTRY macEntry; + + cpuPort = (GT_LPORT)dev->cpuPortNum; + + /* + * Remove CPU port from VLAN Member Table. + */ + for(i=0; inumOfPorts; i++) + { + if((status = gvlnGetPortVlanPorts(dev,(GT_LPORT)i,memPorts,&memPortsLen)) != GT_OK) + { + MSG_PRINT(("gvlnGetPortVlanPorts return Failed\n")); + return status; + } + + for(index=0; indexcpuPortNum; + macEntry.prio = 0; /* Priority (2bits). When these bits are used they override + any other priority determined by the frame's data */ + macEntry.entryState.ucEntryState = GT_UC_TO_CPU_STATIC; + macEntry.DBNum = 0; + macEntry.trunkMember = GT_FALSE; + + if((status = gfdbAddMacEntry(dev,&macEntry)) != GT_OK) + { + MSG_PRINT(("gfdbAddMacEntry return Failed\n")); + return status; + } + + + return GT_OK; +} + + +/* + For the devices that support gprtSetARPtoCPU API: + + 1) Enable ARP to CPU feature fore each port. + 2) Set Egress Flood Mode to be Block Unknown DA on CPU Port. + 3) Add CPU Port's MAC into address table. + 4) Remove Broadcast address from address table. +*/ + +GT_STATUS sampleMinimizeCPUTraffic2(GT_QD_DEV *dev, GT_U8* macAddr) +{ + GT_STATUS status; + int i; + GT_LPORT cpuPort; + GT_ATU_ENTRY macEntry; + + cpuPort = (GT_LPORT)dev->cpuPortNum; + + /* + * Remove CPU port from VLAN Member Table. + */ + for(i=0; inumOfPorts; i++) + { + if (i == cpuPort) + continue; + + if((status = gprtSetARPtoCPU(dev,i,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetARPtoCPU return Failed\n")); + return status; + } + } + + /* + * Set Egress Flood Mode to be Block Unknown DA on CPU Port. + */ + if((status = gprtSetEgressFlood(dev,cpuPort,GT_BLOCK_EGRESS_UNKNOWN)) != GT_OK) + { + MSG_PRINT(("gprtSetEgressFlood return Failed\n")); + return status; + } + + + /* + * Add CPU's MAC into address table. + * This sample assumes that DBNum is not used. If DBNum is used, + * the macEntry has to be added for each DBNum used. + */ + memset(&macEntry,0,sizeof(GT_ATU_ENTRY)); + memcpy(macEntry.macAddr.arEther,macAddr,6); + macEntry.portVec = 1 << dev->cpuPortNum; + macEntry.prio = 0; /* Priority (2bits). When these bits are used they override + any other priority determined by the frame's data */ + macEntry.entryState.ucEntryState = GT_UC_STATIC; + macEntry.DBNum = 0; + macEntry.trunkMember = GT_FALSE; + + if((status = gfdbAddMacEntry(dev,&macEntry)) != GT_OK) + { + MSG_PRINT(("gfdbAddMacEntry return Failed\n")); + return status; + } + + /* + * Delete BroadCast Entry from address table if exists. + * This sample assumes that DBNum is not used. If DBNum is used, + * the macEntry has to be added for each DBNum used. + */ + memset(&macEntry,0,sizeof(GT_ATU_ENTRY)); + memset(macEntry.macAddr.arEther,0xFF,6); + gfdbDelAtuEntry(dev,&macEntry); + + return GT_OK; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MinimizeCPUTraffic/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,29 @@ +======================================================================== + Setup for CPU Port which is not a member of any VLAN +======================================================================== + +Previous SOHO switch devices were low port count and/or used for Routers. +In this environment, the CPU must be a member of all VLANs, so it can +route the frames from one VLAN to another. +In a high port count managed switch, the CPU is not a router but the +manager of the switch. In this environment, the CPU doesn't want to be a +member of any VLAN. If it is, it can get saturated with non-management +frames preventing it from receiving the important management frames. + +In order to support the feature, the following has to be provided: + +1. For the devices that support gsysSetARPDest API: + 0) Remove CPU port from VLAN Member Table. + 1) Mirror ARPs to the CPU with To_CPU Marvell Tag. + 2) Convert unicast frames directed to the CPU into To_CPU Marvell Tag. + +2. For the devices that support gprtSetARPtoCPU API: + 0) Remove CPU port from VLAN Member Table. + 1) Enable ARP to CPU for each port. + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MultiDevice/msApiInit.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MultiDevice/msApiInit.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/MultiDevice/msApiInit.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/MultiDevice/msApiInit.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,272 @@ +#include +/******************************************************************************** +* msApiInit.c +* +* DESCRIPTION: +* MS API initialization routine for devices supporting Multi Address Mode, +* such as 88E6183. Following setup will be used for this sample code. +* +* ------------------ +* |CPU Ethernet Dev| +* ------------------ +* | +* | +* | 8--------------9 8--------------9 8-------------- +* |----| QD Device 0|------| QD Device 1|-----| QD Device 2| +* -------------- -------------- -------------- +* 0 1 2 ... 7 0 1 2 ... 7 0 1 2 ... 7 +* +* +* Ethernet port of CPU is connected to port 8 of Device 0, +* port 9 of Device 0 is connected to port 8 of Device 1, and +* port 9 of Device 1 is connected to port 8 of Device 2. +* +* Device 0 uses Phy Address 1, +* Device 1 uses Phy Address 2, and +* Device 2 uses Phy Address 3 +* Notes: Phy Address 0 cannot be used in a Multi Chip Address Mode. +* +* Each Switch Device has to be configured to Multi Chip Address Mode. +* For detailed information for Multi Chip Address Mode configuration, +* please refer to your device's Datasheet. +* +* DEPENDENCIES: Platform +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +/* +#define MULTI_ADDR_MODE +#define MANUAL_MODE +*/ + +#define MULTI_ADDR_MODE +#define N_OF_QD_DEVICES 3 /* number of 88E6183 devices connected */ + +#define DEVICE0_ID 10 +#define DEVICE1_ID DEVICE0_ID + 1 +#define DEVICE2_ID DEVICE0_ID + 2 + +#define DEVICE0_PHY_ADDR 1 +#define DEVICE1_PHY_ADDR DEVICE0_PHY_ADDR + 1 +#define DEVICE2_PHY_ADDR DEVICE0_PHY_ADDR + 2 + +#define S_CPU_DEVICE DEVICE0_ID + +#define DEVICE0_CPU_PORT 8 +#define DEVICE0_CASCADE_PORT 9 +#define DEVICE1_CPU_PORT 8 +#define DEVICE1_CASCADE_PORT 9 +#define DEVICE2_CPU_PORT 8 +#define DEVICE2_CASCADE_PORT 9 + +GT_QD_DEV *qdMultiDev[N_OF_QD_DEVICES] = {0,}; + +/* + * Initialize each Switch Devices. This should be done in BSP driver init routine. + * Since BSP is not combined with QuarterDeck driver, we are doing here. + * This routine will setup Switch Devices according to the above description. +*/ + +GT_STATUS qdMultiDevStart() +{ + GT_STATUS status = GT_FAIL; + GT_SYS_CONFIG cfg; + int cpuPort; + int cascadePort; + int i,j; + + memset((char*)&cfg,0,sizeof(GT_SYS_CONFIG)); + + /* + * Create QD Device Structure for each device. + */ + for(i=0; ideviceId)); + MSG_PRINT(("Base Reg Addr : 0x%x\n",qdMultiDev[i]->baseRegAddr)); + MSG_PRINT(("No of Ports : %d\n",qdMultiDev[i]->numOfPorts)); + MSG_PRINT(("CPU Ports : %d\n",qdMultiDev[i]->cpuPortNum)); + + /* + * start the QuarterDeck + */ + if((status=sysEnable(qdMultiDev[i])) != GT_OK) + { + MSG_PRINT(("sysConfig return Failed\n")); + goto errorExit; + } + } + + /* + Now, we need to configure Cascading information for each devices. + 1. Set Interswitch port mode for port 8 and 9 for device 0,1,and 2, + so that switch device can expect Marvell Tag from frames + ingressing/egressing this port. + 2. Set CPU Port information (for To_CPU frame) for each port of device. + 3. Set Cascading Port information (for From_CPU fram) for each device. + 4. Set Device ID (if required) + Note: DeviceID is hardware configurable. + */ + for(i=0; inumOfPorts; j++) + { + if((i == cpuPort) || (i == cascadePort)) + { + if((status=gprtSetInterswitchPort(qdMultiDev[i],j,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gprtSetInterswitchPort returned %i (port %i, mode TRUE)\n",status,j)); + goto errorExit; + } + } + else + { + if((status=gprtSetInterswitchPort(qdMultiDev[i],j,GT_FALSE)) != GT_OK) + { + MSG_PRINT(("gprtSetInterswitchPort returned %i (port %i, mode FALSE)\n",status,j)); + goto errorExit; + } + } + + if((status=gprtSetCPUPort(qdMultiDev[i],j,cpuPort)) != GT_OK) + { + MSG_PRINT(("gprtSetCPUPort returned %i\n",status)); + goto errorExit; + } + } + + /* + 3. Set Cascading Port information (for From_CPU fram) for each device. + */ + if((status=gsysSetCascadePort(qdMultiDev[i],cascadePort)) != GT_OK) + { + MSG_PRINT(("gsysSetCascadePort returned %i\n",status)); + goto errorExit; + } + + /* + 4. Set Device ID (if required) + */ + if((status=gsysSetDeviceNumber(qdMultiDev[i],DEVICE0_ID+i)) != GT_OK) + { + MSG_PRINT(("gsysSetDeviceNumber returned %i\n",status)); + goto errorExit; + } + + } + + MSG_PRINT(("QuarterDeck has been started.\n")); + + return GT_OK; + +errorExit: + + for(i=0; i +/******************************************************************************** +* pirl2.c +* +* DESCRIPTION: +* Setup PIRL buckets for 88E6097 device family +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + + +/* + * This setup function configures the resource 0 of Port 0 of Marvell SOHO + * Switch Device with capability of PIRL to be : + * + * 1) Ingress Rate : 128Kbps (128K bit per sec) + * 2) Custom setup for Ingress Rate : disabled + * 3) Discarded frame : Do not account discarded frame due to queue congestion + * 4) Filtered frame : Account filtered frame + * 5) Mgmt frame : Exclude management frame from rate limiting calculation + * 6) SA found in ATU : Exclude from ingress rate limiting calculation if the SA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * 7) DA found in ATU : Include to ingress rate limiting calculation even though the DA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * 8) Sampling Mode : Disable the mode + * 9) Action Mode : Follow Limit action when there are not enough tokens to accept the + * entire imcoming frame. + * 10) Limit action : Drop packets when the incoming rate exceeds the limit + * 11) Rate type : Rate is based on Traffic type + * 12) Traffic type : ARP, MGMT, Multicast, Broadcast, and Unicast frames are + * tracked as part of the rate resource calculation. + * 13) Byte counted : Account only Layer 3 bytes (IP header and payload) + * +*/ + +GT_STATUS samplePIRL2Setup(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_PIRL2_DATA pirlData; + GT_U32 irlRes; + GT_LPORT port; + + /* change Current Timer Update Interval */ + status = gpirl2SetCurTimeUpInt(dev,4); + switch (status) + { + case GT_OK: + break; + case GT_NOT_SUPPORTED: + MSG_PRINT(("Device is not supporting PIRL.\n")); + return status; + default: + MSG_PRINT(("Failure to configure device.\n")); + return status; + } + + port = 0; + irlRes = 0; + + pirlData.ingressRate = 128; + + pirlData.customSetup.isValid = GT_FALSE; + + pirlData.accountQConf = GT_FALSE; + pirlData.accountFiltered = GT_TRUE; + + pirlData.mgmtNrlEn = GT_TRUE; + pirlData.saNrlEn = GT_TRUE; + pirlData.daNrlEn = GT_FALSE; + pirlData.samplingMode = GT_FALSE; + pirlData.actionMode = PIRL_ACTION_USE_LIMIT_ACTION; + + pirlData.ebsLimitAction = ESB_LIMIT_ACTION_DROP; + pirlData.bktRateType = BUCKET_TYPE_TRAFFIC_BASED; + pirlData.bktTypeMask = BUCKET_TRAFFIC_BROADCAST | + BUCKET_TRAFFIC_MULTICAST | + BUCKET_TRAFFIC_UNICAST | + BUCKET_TRAFFIC_MGMT_FRAME| + BUCKET_TRAFFIC_ARP; + + pirlData.priORpt = GT_TRUE; + pirlData.priMask = 0; + + pirlData.byteTobeCounted = GT_PIRL2_COUNT_ALL_LAYER3; + + status = gpirl2WriteResource(dev,port,irlRes,&pirlData); + + switch (status) + { + case GT_OK: + MSG_PRINT(("PIRL2 writing completed.\n")); + break; + case GT_BAD_PARAM: + MSG_PRINT(("Invalid parameters are given.\n")); + break; + case GT_NOT_SUPPORTED: + MSG_PRINT(("Device is not supporting PIRL2.\n")); + break; + default: + MSG_PRINT(("Failure to configure device.\n")); + break; + } + + return status; +} + + + +/* + * This setup function shows how to configure Ingress Rate of 128Kbps with the + * custom data information. + * it configures the resource 0 of Port 0 of Marvell SOHO Switch Device with + * capability of PIRL to be : + * + * 1) Custom setup for Ingress Rate : Enabled + * 2) Custom EBS Limit : 0xFFFFFF + * 3) Custom CBS Limit : 0x200000 + * 4) Custom Bucket Increament : 0x3D + * 5) Custom Bucket Rate Factor : 2 + * 6) Discarded frame : Do not account discarded frame due to queue congestion + * 7) Filtered frame : Account filtered frame + * 8) Mgmt frame : Exclude management frame from rate limiting calculation + * 9) SA found in ATU : Exclude from ingress rate limiting calculation if the SA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * 10) DA found in ATU : Include to ingress rate limiting calculation even though the DA of the + * frame is in ATU with EntryState that indicates Non Rate Limited. + * 11) Sampling Mode : Disable the mode + * 12) Action Mode : Follow Limit action when there are not enough tokens to accept the + * entire imcoming frame. + * 13) Limit action : Drop packets when the incoming rate exceeds the limit + * 14) Rate type : Rate is based on Traffic type + * 15) Traffic type : ARP, MGMT, Multicast, Broadcast, and Unicast frames are + * tracked as part of the rate resource calculation. + * 16) Byte counted : Account only Layer 3 bytes (IP header and payload) + * +*/ + +GT_STATUS samplePIRL2CustomSetup(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_PIRL2_DATA pirlData; + GT_U32 irlRes; + GT_LPORT port; + + port = 0; + irlRes = 0; + + pirlData.customSetup.isValid = GT_TRUE; + pirlData.customSetup.ebsLimit = 0xFFFFFF; + pirlData.customSetup.cbsLimit = 0x200000; + pirlData.customSetup.bktIncrement = 0x3D; + pirlData.customSetup.bktRateFactor = 2; + + pirlData.accountQConf = GT_FALSE; + pirlData.accountFiltered = GT_TRUE; + + pirlData.mgmtNrlEn = GT_TRUE; + pirlData.saNrlEn = GT_TRUE; + pirlData.daNrlEn = GT_FALSE; + pirlData.samplingMode = GT_FALSE; + pirlData.actionMode = PIRL_ACTION_USE_LIMIT_ACTION; + + pirlData.ebsLimitAction = ESB_LIMIT_ACTION_DROP; + pirlData.bktRateType = BUCKET_TYPE_TRAFFIC_BASED; + pirlData.bktTypeMask = BUCKET_TRAFFIC_BROADCAST | + BUCKET_TRAFFIC_MULTICAST | + BUCKET_TRAFFIC_UNICAST | + BUCKET_TRAFFIC_MGMT_FRAME| + BUCKET_TRAFFIC_ARP; + + pirlData.priORpt = GT_TRUE; + pirlData.priMask = 0; + + pirlData.byteTobeCounted = GT_PIRL2_COUNT_ALL_LAYER3; + + status = gpirl2WriteResource(dev,port,irlRes,&pirlData); + + switch (status) + { + case GT_OK: + MSG_PRINT(("PIRL2 writing completed.\n")); + break; + case GT_BAD_PARAM: + MSG_PRINT(("Invalid parameters are given.\n")); + break; + case GT_NOT_SUPPORTED: + MSG_PRINT(("Device is not supporting PIRL2.\n")); + break; + default: + MSG_PRINT(("Failure to configure device.\n")); + break; + } + + return status; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PIRL/pirl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PIRL/pirl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PIRL/pirl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PIRL/pirl.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,93 @@ +#include +/******************************************************************************** +* pirl.c +* +* DESCRIPTION: +* Setup PIRL buckets +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + + +/* + * This setup function configures the Port 0 of Marvell SOHO Switch Device with + * capability of PIRL to be : + * + * 1) Ingress Rate : 128Kbps (128K bit per sec) + * 2) Discarded frame : Do not account discarded frame due to queue congestion + * 3) Filtered frame : Account filtered frame + * 4) Limit action : Drop packets when the incoming rate exceeds the limit + * 5) Rate type : Rate is based on Traffic type + * 6) Traffic type : ARP, MGMT, Multicast, Broadcast, and Unicast frames are + * tracked as part of the rate resource calculation. + * 7) Byte counted : Account only Layer 3 bytes (IP header and payload) + * + * Notes: This sample uses IRL Unit 0. The available number of IRL Units are + * various depending on the device. Please refer to the datasheet for detailed + * information. + * + * Notes: Port 0 will be blocked while programming PIRL. +*/ + +GT_STATUS samplePIRLSetup(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_PIRL_DATA pirlData; + GT_U32 irlUnit; + GT_LPORT port; + + /* change Current Timer Update Interval */ + status = gpirlSetCurTimeUpInt(dev,4); + switch (status) + { + case GT_OK: + break; + case GT_NOT_SUPPORTED: + MSG_PRINT(("Device is not supporting PIRL.\n")); + return status; + default: + MSG_PRINT(("Failure to configure device.\n")); + return status; + } + + irlUnit = 0; + port = 0; + + pirlData.ingressRate = 128; + pirlData.accountQConf = GT_FALSE; + pirlData.accountFiltered = GT_TRUE; + pirlData.ebsLimitAction = ESB_LIMIT_ACTION_DROP; + pirlData.bktRateType = BUCKET_TYPE_TRAFFIC_BASED; + pirlData.bktTypeMask = BUCKET_TRAFFIC_BROADCAST | + BUCKET_TRAFFIC_MULTICAST | + BUCKET_TRAFFIC_UNICAST | + BUCKET_TRAFFIC_MGMT_FRAME| + BUCKET_TRAFFIC_ARP; + + pirlData.byteTobeCounted = GT_PIRL_COUNT_ALL_LAYER3; + + status = gpirlActivate(dev,irlUnit,(1< +/******************************************************************************** +* phyPktGenSample.c +* +* DESCRIPTION: +* Packet Generator setup sample (startPktGenerator and stopPktGenerator). +* +* DEPENDENCIES: +* Please check the phy device's spec. if the device supports this feature. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + + +/* + * Start Packet Generator. + * Input: + * pktload - enum GT_PG_PAYLOAD (GT_PG_PAYLOAD_RANDOM or GT_PG_PAYLOAD_5AA5) + * length - enum GT_PG_LENGTH (GT_PG_LENGTH_64 or GT_PG_LENGTH_1514) + * tx - enum GT_PG_TX (GT_PG_TX_NORMAL or GT_PG_TX_ERROR) +*/ +GT_STATUS startPktGenerator +( + GT_QD_DEV *dev, + GT_LPORT port, + GT_PG_PAYLOAD payload, + GT_PG_LENGTH length, + GT_PG_TX tx +) +{ + GT_STATUS status; + GT_PG pktInfo; + + if (dev == 0) + { + MSG_PRINT(("GT driver is not initialized\n")); + return GT_FAIL; + } + + MSG_PRINT(("Start Packet Generator for port %i\n",(int)port)); + + pktInfo.payload = payload; /* Pseudo-random, 5AA55AA5... */ + pktInfo.length = length; /* 64 bytes, 1514 bytes */ + pktInfo.tx = tx; /* normal packet, error packet */ + + /* + * Start Packet Generator + */ + if((status = gprtSetPktGenEnable(dev,port,GT_TRUE,&pktInfo)) != GT_OK) + { + MSG_PRINT(("mdDiagSetPktGenEnable return Failed\n")); + return status; + } + + return GT_OK; +} + + +/* + * Stop Packet Generator. + */ +GT_STATUS stopPktGenerator(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + + if (dev == 0) + { + MSG_PRINT(("GT driver is not initialized\n")); + return GT_FAIL; + } + + MSG_PRINT(("Stopping Packet Generator for port %i\n",(int)port)); + + /* + * Start Packet Generator + */ + if((status = gprtSetPktGenEnable(dev,port,GT_FALSE,NULL)) != GT_OK) + { + MSG_PRINT(("mdDiagSetPktGenEnable return Failed\n")); + return status; + } + + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PktGen/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PktGen/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PktGen/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PktGen/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,20 @@ + + Sample for Packet Generator +======================================================= + +This sample shows how to start/stop Packet Generator. + +Main Functions: + startPktGenerator - start Packet Generator + stopPktGenerator - stop Packet Generator + +Used APIs: + gprtSetPktGenEnable + + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PortMonitor/portMonitor.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PortMonitor/portMonitor.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PortMonitor/portMonitor.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PortMonitor/portMonitor.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,108 @@ +#include +/******************************************************************************** +* portMonitor.c +* +* DESCRIPTION: +* This sample shows how to monitor a certain port. Port monitoring is +* supported by the ClipperShip device with Egress only monitoring or +* Egress and Ingress monitoring. +* +* DEPENDENCIES: +* Only ClipperShip Family supports this feature. +* +* FILE REVISION NUMBER: +* +* COMMENTS: +*******************************************************************************/ + +#include "msSample.h" + +/* + * Enable EgressMonitoring for the monitoredPort. + * With this setup, monitoringPort will receive every packet + * which egressed from monitoredPort. +*/ +GT_STATUS sampleEgressMonitor(GT_QD_DEV *dev,GT_LPORT monitoredPort, GT_LPORT monitoringPort) +{ + GT_STATUS status; + GT_U16 pav; + + /* + * Enable EgressMonitoring for the monitoredPort. + */ + pav = (1< +/******************************************************************************** +* ptp.c +* +* DESCRIPTION: +* Setup PTP for 88E6165 device family. +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + + +/* + * PTP Init routine + * + * 1) Setup each port to forward PTP frame to CPU port + * 2) Enable PTP Interrupt (assumes that no other interrupt is used, but PTP) + * 3) Configure PTP + * 4) Enable PTP + * + * Notes: This sample uses the following configuration + * 1) Enables only PTP interrupt + * 2) Assumes PTP Ethernet Type is 0x88F7 + * 3) Time Stamp is enabled only for Message ID 0, 2, and 3 + * 4) Message ID 0 and 2 use Arr0 pointer and ID 3 uses Arr1 pointer + * 5) PTP interrtups are enabled on Port 0 ~ 5 + * + * Notes: Forwarding PTP fram to CPU port is based on Ether Type DSA Tag (8 bytes). + * Therefore, Ethernet device driver, that actually rx/tx the PTP frame, + * should expect/insert Ether Type DSA Tag. +*/ + +STATUS samplePTPInit(GT_QD_DEV *dev) +{ + GT_PTP_CONFIG ptpCfg; + GT_LPORT port; + GT_STATUS status; + + + /* + * 1) Setup each port to forward PTP frame to CPU port + */ + + /* setup EtypeType and Policy */ + for(port=0; portnumOfPorts; port++) + { + if ((status = gprtSetPortEType(dev, port, (GT_ETYPE)0x88F7)) != GT_OK) + { + MSG_PRINT(("gprtSetPortEType returned not OK\n")); + return status; + } + + if (port == dev->cpuPortNum) + continue; + + if ((status = gprtSetPolicy(dev, port, POLICY_TYPE_ETYPE, FRAME_POLICY_TRAP)) != GT_OK) + { + MSG_PRINT(("gprtSetPolicy returned not OK\n")); + return status; + } + } + + /* setup Frame Mode for CPU port */ + if ((status = gprtSetFrameMode(dev, dev->cpuPortNum, GT_FRAME_MODE_ETHER_TYPE_DSA)) != GT_OK) + { + MSG_PRINT(("gprtSetFrameMode return failed\n")); + return status; + } + + /* + * 2) Enable PTP Interrupt + */ + eventSetActive(dev, GT_AVB_INT); + + + /* + * 3) Configure PTP + */ + ptpCfg.ptpEType = 0x88F7; + ptpCfg.msgIdTSEn = 0xd; /* id 0, 2, and 3 */ + ptpCfg.tsArrPtr = 0x8; /* id 0 and 2 for ARR0, id 3 for ARR1 */ + + /* Transport specific bits present in PTP Common Header */ + ptpCfg.transSpec = 1; + + /* starting bit location for the Message ID field in the PTP Common Header */ + ptpCfg.msgIdStartBit = 4; + + ptpCfg.ptpArrIntEn = 0x3F; + ptpCfg.ptpDepIntEn = 0x3F; + ptpCfg.disTSOverwrite = 0; + + + if ((status = gptpSetConfig(dev, &ptpCfg)) != GT_OK) + { + MSG_PRINT(("gptpSetConfig return failed\n")); + return status; + } + if ((status = gptpSetPTPEn(dev, GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gptpSetPTPEn return failed\n")); + return status; + } + + return GT_OK; +} + + +/* + * PTP Interrupt Handler + * + * 1) for each port that causes PTP interrup, do the followings + * 2) check Arrival 0 Time Stamp + * 3) check Arrival 1 Time Stamp + * 4) check Departure Time Stamp +*/ + +STATUS samplePTPIntHandler(GT_QD_DEV *dev) +{ + GT_U32 int_ports, i, int_status; + GT_STATUS status; + GT_PTP_TS_STATUS ptpStatus; + + /* disable AVB Interrupt */ + eventSetActive(dev, 0); + + /* read interrupt cause */ + eventGetIntStatus(dev,(GT_U16*)&int_status); + if ((int_status & GT_AVB_INT) == 0) + { + /* it's not PTP interrupt */ + return GT_FAIL; + } + + /* read AVB Int status */ + if((status = gptpGetPTPInt(dev, &int_ports)) != GT_OK) + { + MSG_PRINT(("gptpGetPTPInt return failed\n")); + goto ret_int; + } + + /* for each port, get the timestamp information if necessary */ + i = 0; + while(int_ports) + { + if(!(int_ports & 0x1)) + { + i++; + int_ports >>= 1; + continue; + } + + /* check Arrival0 Time Stamp */ + if((status = gptpGetTimeStamped(dev, i, PTP_ARR0_TIME, &ptpStatus)) != GT_OK) + { + MSG_PRINT(("gptpGetTimeStamped return failed\n")); + goto ret_int; + } + + if (ptpStatus.isValid == GT_TRUE) + { + switch(ptpStatus.status) + { + case PTP_INT_NORMAL: + /* To Do: No error condition occurred. So store the time stamp and seqId */ + break; + + case PTP_INT_OVERWRITE: + /* To Do: PTP Logic received several PTP frames and only the last one is valid */ + break; + + case PTP_INT_DROP: + /* To Do: PTP Logic received several PTP frames and only the first one is valid */ + break; + + default: + MSG_PRINT(("unknown ptp status %i\n", ptpStatus.status)); + status = GT_FAIL; + goto ret_int; + + } + + if((status = gptpResetTimeStamp(dev, i, PTP_ARR0_TIME)) != GT_OK) + { + MSG_PRINT(("gptpResetTimeStamp return failed\n")); + goto ret_int; + } + } + + /* check Arrival1 Time Stamp */ + if((status = gptpGetTimeStamped(dev, i, PTP_ARR1_TIME, &ptpStatus)) != GT_OK) + { + MSG_PRINT(("gptpGetTimeStamped return failed\n")); + goto ret_int; + } + + if (ptpStatus.isValid == GT_TRUE) + { + switch(ptpStatus.status) + { + case PTP_INT_NORMAL: + /* To Do: No error condition occurred. So store the time stamp and seqId */ + break; + + case PTP_INT_OVERWRITE: + /* To Do: PTP Logic received several PTP frames and only the last one is valid */ + break; + + case PTP_INT_DROP: + /* To Do: PTP Logic received several PTP frames and only the first one is valid */ + break; + + default: + MSG_PRINT(("unknown ptp status %i\n", ptpStatus.status)); + status = GT_FAIL; + goto ret_int; + } + + if((status = gptpResetTimeStamp(dev, i, PTP_ARR1_TIME)) != GT_OK) + { + MSG_PRINT(("gptpResetTimeStamp return failed\n")); + goto ret_int; + } + + } + + /* check Departure Time Stamp */ + if((status = gptpGetTimeStamped(dev, i, PTP_DEP_TIME, &ptpStatus)) != GT_OK) + { + MSG_PRINT(("gptpGetTimeStamped return failed\n")); + goto ret_int; + } + + if (ptpStatus.isValid == GT_TRUE) + { + switch(ptpStatus.status) + { + case PTP_INT_NORMAL: + /* To Do: No error condition occurred. So store the time stamp and seqId */ + break; + + case PTP_INT_OVERWRITE: + /* To Do: PTP Logic received several PTP frames and only the last one is valid */ + break; + + case PTP_INT_DROP: + /* To Do: PTP Logic received several PTP frames and only the first one is valid */ + break; + + default: + MSG_PRINT(("unknown ptp status %i\n", ptpStatus.status)); + status = GT_FAIL; + goto ret_int; + } + + if((status = gptpResetTimeStamp(dev, i, PTP_DEP_TIME)) != GT_OK) + { + MSG_PRINT(("gptpResetTimeStamp return failed\n")); + goto ret_int; + } + + } + + int_ports >>= 1; + + } + +ret_int: + eventSetActive(dev, GT_AVB_INT); + + return status; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PTP/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PTP/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/PTP/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/PTP/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,17 @@ +================================================================== + PTP (Precise Time Protocol) Setup +================================================================== + +88E6165 device family Switch Devices support PTP. + +This sample shows how to use PTP APIs. + + + + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/qos.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/qos.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/qos.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/qos.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,196 @@ +#include +/******************************************************************************** +* qos.c +* +* DESCRIPTION: +* Sample program which will show how to setup the Priority Queue for QoS +* +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +/* + * sampleQoS will enable using both IEEE 802.3ac Tag and IPv4/IPv6 Traffic + * Class field and IEEE 802.3ac has a higher priority than IPv4/IPv6. + * The following is the QoS mapping programmed by sampleQos: + * 1) IEEE 802.3ac Tag (Priority 0 ~ 7, 3 bits) + * Priority 1~3 is using QuarterDeck Queue 0. + * Priority 0,4 is using QuarterDeck Queue 1. + * Priority 6,7 is using QuarterDeck Queue 2. + * Priority 5 is using QuarterDeck Queue 3. + * 2) IPv4/IPv6 (Priority 0 ~ 63, 6 bits) + * Priority 0~7 is using QuaterDeck Queue 0. + * Priority 8~31 is using QuaterDeck Queue 1. + * Priority 32~55 is using QuaterDeck Queue 2. + * Priority 56~63 is using QuaterDeck Queue 3. + * 3) Each port's default priority is set to 1. +*/ +GT_STATUS sampleQos(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_U8 priority; + GT_LPORT port; + + for(port=0; port<7; port++) + { + /* + * Use IEEE Tag + */ + if((status = gqosUserPrioMapEn(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gqosUserPrioMapEn return Failed\n")); + return status; + } + + /* + * Use IPv4/IPv6 priority fields (use IP) + */ + if((status = gqosIpPrioMapEn(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gqosIpPrioMapEn return Failed\n")); + return status; + } + + /* + * IEEE Tag has higher priority than IP priority fields + */ + if((status = gqosSetPrioMapRule(dev,port,GT_TRUE)) != GT_OK) + { + MSG_PRINT(("gqosSetPrioMapRule return Failed\n")); + return status; + } + } + + /* + * IEEE 802.3ac Tag (Priority 0 ~ 7, 3 bits) + * Priority 1~3 is using QuarterDeck Queue 0. + * Priority 0,4 is using QuarterDeck Queue 1. + * Priority 6,7 is using QuarterDeck Queue 2. + * Priority 5 is using QuarterDeck Queue 3. + */ + + /* Priority 0 is using QuarterDeck Queue 1. */ + if((status = gcosSetUserPrio2Tc(dev,0,1)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 1 is using QuarterDeck Queue 0. */ + if((status = gcosSetUserPrio2Tc(dev,1,0)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 2 is using QuarterDeck Queue 0. */ + if((status = gcosSetUserPrio2Tc(dev,2,0)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 3 is using QuarterDeck Queue 0. */ + if((status = gcosSetUserPrio2Tc(dev,3,0)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 4 is using QuarterDeck Queue 1. */ + if((status = gcosSetUserPrio2Tc(dev,4,1)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 5 is using QuarterDeck Queue 3. */ + if((status = gcosSetUserPrio2Tc(dev,5,3)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 6 is using QuarterDeck Queue 2. */ + if((status = gcosSetUserPrio2Tc(dev,6,2)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + /* Priority 7 is using QuarterDeck Queue 2. */ + if((status = gcosSetUserPrio2Tc(dev,7,2)) != GT_OK) + { + MSG_PRINT(("gcosSetUserPrio2Tc returned fail.\n")); + return status; + } + + + /* + * IPv4/IPv6 (Priority 0 ~ 63, 6 bits) + * Priority 0~7 is using QuaterDeck Queue 0. + * Priority 8~31 is using QuaterDeck Queue 1. + * Priority 32~55 is using QuaterDeck Queue 2. + * Priority 56~63 is using QuaterDeck Queue 3. + */ + + /* Priority 0~7 is using QuaterDeck Queue 0. */ + for(priority=0; priority<8; priority++) + { + if((status = gcosSetDscp2Tc(dev,priority,0)) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned fail.\n")); + return status; + } + } + + /* Priority 8~31 is using QuaterDeck Queue 1. */ + for(priority=8; priority<32; priority++) + { + if((status = gcosSetDscp2Tc(dev,priority,1)) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned fail.\n")); + return status; + } + } + + /* Priority 32~55 is using QuaterDeck Queue 2. */ + for(priority=32; priority<56; priority++) + { + if((status = gcosSetDscp2Tc(dev,priority,2)) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned fail.\n")); + return status; + } + } + + /* Priority 56~63 is using QuaterDeck Queue 3. */ + for(priority=56; priority<64; priority++) + { + if((status = gcosSetDscp2Tc(dev,priority,3)) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned fail.\n")); + return status; + } + } + + /* + * Each port's default priority is set to 1. + */ + for(port=0; port<7; port++) + { + if((status = gcosSetPortDefaultTc(dev,port,1)) != GT_OK) + { + MSG_PRINT(("gcosSetDscp2Tc returned fail.\n")); + return status; + } + } + + return GT_OK; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/QoSSetup/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,41 @@ +======================================================================== + Priority Queue Setup for QoS +======================================================================== + +QuarterDeck Device has 4 Priority Queues to support QoS. The priority of +a frame is determined by (in priority order): + 1) The CPU's Trailer if enabled on the port. + 2) The DA address in the frame if the frame's DA address is in the address + database with a priority defined. + 3) The IEEE 802.3ac Tag containing IEEE 802.1p priority information + if enabled on the port. + 4) The IPv4 Type of Service (TOS)/DiffServ field or IPv6 Traffic Class + field if enabled on the port. + 5) The Port's default priority defined in DefPri. + +This sample program will deal with the above 3) ~ 5) cases. + +qos.c + sampleQoS will enable using both IEEE 802.3ac Tag and IPv4/IPv6 Traffic + Class field and IEEE 802.3ac has a higher priority than IPv4/IPv6. + The following is the QoS mapping programmed by sampleQos: + 1) IEEE 802.3ac Tag (Priority 0 ~ 7, 3 bits) + Priority 1~3 is using QuarterDeck Queue 0. + Priority 0,4 is using QuarterDeck Queue 1. + Priority 6,7 is using QuarterDeck Queue 2. + Priority 5 is using QuarterDeck Queue 3. + 2) IPv4/IPv6 (Priority 0 ~ 63, 6 bits) + Priority 0~7 is using QuaterDeck Queue 0. + Priority 8~31 is using QuaterDeck Queue 1. + Priority 32~55 is using QuaterDeck Queue 2. + Priority 56~63 is using QuaterDeck Queue 3. + 3) Each port's default priority is set to 1. + + + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/README u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/README --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/README 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/README 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,2 @@ +This directory includes sample code that demonstrats how to use the API of +the DSDT Suite. There is a readme.txt file in each of the subdirectories. diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/RMON/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/RMON/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/RMON/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/RMON/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,32 @@ +======================================================================== + RMON Counters +======================================================================== + +This sample shows how to read/clear RMON counter in the device. +Please notes that there are three groups of RMON counters in Marvell SOHO Switchs. +Each group has different set of counters. Therefore it is necessary to find out +which group the switch device belongs to. + +Group for GT_STATS_COUNTERS : 88E6021, 88E6063, and 88E6083 +Group for GT_STATS_COUNTERS2 : 88E6183 +Group for GT_STATS_COUNTERS3 : 88E6093, 88E6095, 88E6185, and 88E6065 + +rmon.c + sampleClearRMONCounter + shows how to reset RMON counter for the given port + + sampleGetRMONCounter + shows how to read RMON counter for each port + this routine is for the devices that use GT_STATS_COUNTERS. + + sampleGetRMONCounter2 + shows how to read RMON counter for each port + this routine is for the devices that use GT_STATS_COUNTERS2. + + sampleGetRMONCounter3 + shows how to read RMON counter for each port + this routine is for the devices that use GT_STATS_COUNTERS3. + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/RMON/rmon.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/RMON/rmon.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/RMON/rmon.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/RMON/rmon.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,238 @@ +#include +/******************************************************************************** +* rmon.c +* +* DESCRIPTION: +* This sample shows how to read/clear RMON counter in the device +* +* DEPENDENCIES: NONE. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + + +/* + * This sample is for every device that support RMON counter. +*/ +GT_STATUS sampleClearRMONCounter(GT_QD_DEV *dev,GT_LPORT port) +{ + GT_STATUS status; + + if((status = gstatsFlushPort(dev,port)) != GT_OK) + { + MSG_PRINT(("gstatsFlushPort returned fail (%#x).\n",status)); + return status; + } + + return GT_OK; +} + +/* + * This sample is for 88E6021, 88E6063, and 88E6083. +*/ +void sampleDisplayCounter(GT_STATS_COUNTER_SET *statsCounter) +{ + MSG_PRINT(("InUnicasts %08i ", statsCounter->InUnicasts)); + MSG_PRINT(("InBroadcasts %08i \n", statsCounter->InBroadcasts)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("InFCSErr %08i ", statsCounter->InFCSErr)); + MSG_PRINT(("AlignErr %08i \n", statsCounter->AlignErr)); + MSG_PRINT(("InGoodOctets %08i ", statsCounter->InGoodOctets)); + MSG_PRINT(("InBadOctets %08i \n", statsCounter->InBadOctets)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("In64Octets %08i ", statsCounter->In64Octets)); + MSG_PRINT(("In127Octets %08i \n", statsCounter->In127Octets)); + MSG_PRINT(("In255Octets %08i ", statsCounter->In255Octets)); + MSG_PRINT(("In511Octets %08i \n", statsCounter->In511Octets)); + MSG_PRINT(("In1023Octets %08i ", statsCounter->In1023Octets)); + MSG_PRINT(("InMaxOctets %08i \n", statsCounter->InMaxOctets)); + MSG_PRINT(("Jabber %08i ", statsCounter->Jabber)); + MSG_PRINT(("Oversize %08i \n", statsCounter->Oversize)); + MSG_PRINT(("InDiscards %08i ", statsCounter->InDiscards)); + MSG_PRINT(("Filtered %08i \n", statsCounter->Filtered)); + MSG_PRINT(("OutUnicasts %08i ", statsCounter->OutUnicasts)); + MSG_PRINT(("OutBroadcasts %08i \n", statsCounter->OutBroadcasts)); + MSG_PRINT(("OutPause %08i ", statsCounter->OutPause)); + MSG_PRINT(("OutMulticasts %08i \n", statsCounter->OutMulticasts)); + MSG_PRINT(("OutFCSErr %08i ", statsCounter->OutFCSErr)); + MSG_PRINT(("OutGoodOctets %08i \n", statsCounter->OutGoodOctets)); + MSG_PRINT(("Out64Octets %08i ", statsCounter->Out64Octets)); + MSG_PRINT(("Out127Octets %08i \n", statsCounter->Out127Octets)); + MSG_PRINT(("Out255Octets %08i ", statsCounter->Out255Octets)); + MSG_PRINT(("Out511Octets %08i \n", statsCounter->Out511Octets)); + MSG_PRINT(("Out1023Octets %08i ", statsCounter->Out1023Octets)); + MSG_PRINT(("OutMaxOctets %08i \n", statsCounter->OutMaxOctets)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); + MSG_PRINT(("Excessive %08i ", statsCounter->Excessive)); + MSG_PRINT(("Multiple %08i \n", statsCounter->Multiple)); + MSG_PRINT(("Single %08i ", statsCounter->Single)); + MSG_PRINT(("Deferred %08i \n", statsCounter->Deferred)); + MSG_PRINT(("OutDiscards %08i \n", statsCounter->OutDiscards)); +} + +/* + * This sample is for 88E6021, 88E6063, and 88E6083. +*/ +GT_STATUS sampleGetRMONCounter(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + GT_STATS_COUNTER_SET statsCounterSet; + + for(port=0; portnumOfPorts; port++) + { + MSG_PRINT(("Port %i :\n",port)); + + if((status = gstatsGetPortAllCounters(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters returned fail (%#x).\n",status)); + return status; + } + + sampleDisplayCounter(&statsCounterSet); + + } + + return GT_OK; +} + + +/* + * This sample is for 88E6183 +*/ +void sampleDisplayCounter2(GT_STATS_COUNTER_SET2 *statsCounter) +{ + MSG_PRINT(("InGoodOctetsHi %08i ", statsCounter->InGoodOctetsHi)); + MSG_PRINT(("InGoodOctetsLo %08i \n", statsCounter->InGoodOctetsLo)); + MSG_PRINT(("InBadOctets %08i ", statsCounter->InBadOctets)); + MSG_PRINT(("OutDiscards %08i \n", statsCounter->OutDiscards)); + MSG_PRINT(("InGoodFrames %08i ", statsCounter->InGoodFrames)); + MSG_PRINT(("InBadFrames %08i \n", statsCounter->InBadFrames)); + MSG_PRINT(("InBroadcasts %08i ", statsCounter->InBroadcasts)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("64Octets %08i ", statsCounter->Octets64)); + MSG_PRINT(("127Octets %08i \n", statsCounter->Octets127)); + MSG_PRINT(("255Octets %08i ", statsCounter->Octets255)); + MSG_PRINT(("511Octets %08i \n", statsCounter->Octets511)); + MSG_PRINT(("1023Octets %08i ", statsCounter->Octets1023)); + MSG_PRINT(("MaxOctets %08i \n", statsCounter->OctetsMax)); + MSG_PRINT(("OutOctetsHi %08i ", statsCounter->OutOctetsHi)); + MSG_PRINT(("OutOctetsLo %08i \n", statsCounter->OutOctetsLo)); + MSG_PRINT(("OutFrames %08i ", statsCounter->OutFrames)); + MSG_PRINT(("Excessive %08i \n", statsCounter->Excessive)); + MSG_PRINT(("OutMulticasts %08i ", statsCounter->OutMulticasts)); + MSG_PRINT(("OutBroadcasts %08i ", statsCounter->OutBroadcasts)); + MSG_PRINT(("InBadMACCtrl %08i ", statsCounter->InBadMACCtrl)); + MSG_PRINT(("OutPause %08i \n", statsCounter->OutPause)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("InDiscards %08i \n", statsCounter->InDiscards)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("Oversize %08i ", statsCounter->Oversize)); + MSG_PRINT(("Jabber %08i \n", statsCounter->Jabber)); + MSG_PRINT(("MACRcvErr %08i ", statsCounter->MACRcvErr)); + MSG_PRINT(("InFCSErr %08i \n", statsCounter->InFCSErr)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); +} + +/* + * This sample is for 88E6183 +*/ +GT_STATUS sampleGetRMONCounter2(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + GT_STATS_COUNTER_SET2 statsCounterSet; + + for(port=0; portnumOfPorts; port++) + { + MSG_PRINT(("Port %i :\n",port)); + + if((status = gstatsGetPortAllCounters2(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters2 returned fail (%#x).\n",status)); + return status; + } + + sampleDisplayCounter2(&statsCounterSet); + + } + + return GT_OK; +} + + + +/* + * This sample is for 88E6093, 88E6095, 88E6185, and 88E6065 +*/ +void sampleDisplayCounter3(GT_STATS_COUNTER_SET3 *statsCounter) +{ + MSG_PRINT(("InGoodOctetsLo %08i ", statsCounter->InGoodOctetsLo)); + MSG_PRINT(("InGoodOctetsHi %08i \n", statsCounter->InGoodOctetsHi)); + MSG_PRINT(("InBadOctets %08i ", statsCounter->InBadOctets)); + MSG_PRINT(("OutFCSErr %08i \n", statsCounter->OutFCSErr)); + MSG_PRINT(("InUnicasts %08i ", statsCounter->InUnicasts)); + MSG_PRINT(("Deferred %08i \n", statsCounter->Deferred)); + MSG_PRINT(("InBroadcasts %08i ", statsCounter->InBroadcasts)); + MSG_PRINT(("InMulticasts %08i \n", statsCounter->InMulticasts)); + MSG_PRINT(("64Octets %08i ", statsCounter->Octets64)); + MSG_PRINT(("127Octets %08i \n", statsCounter->Octets127)); + MSG_PRINT(("255Octets %08i ", statsCounter->Octets255)); + MSG_PRINT(("511Octets %08i \n", statsCounter->Octets511)); + MSG_PRINT(("1023Octets %08i ", statsCounter->Octets1023)); + MSG_PRINT(("MaxOctets %08i \n", statsCounter->OctetsMax)); + MSG_PRINT(("OutOctetsLo %08i ", statsCounter->OutOctetsLo)); + MSG_PRINT(("OutOctetsHi %08i \n", statsCounter->OutOctetsHi)); + MSG_PRINT(("OutUnicasts %08i ", statsCounter->OutUnicasts)); + MSG_PRINT(("Excessive %08i \n", statsCounter->Excessive)); + MSG_PRINT(("OutMulticasts %08i ", statsCounter->OutMulticasts)); + MSG_PRINT(("OutBroadcasts %08i \n", statsCounter->OutBroadcasts)); + MSG_PRINT(("Single %08i ", statsCounter->Single)); + MSG_PRINT(("OutPause %08i \n", statsCounter->OutPause)); + MSG_PRINT(("InPause %08i ", statsCounter->InPause)); + MSG_PRINT(("Multiple %08i \n", statsCounter->Multiple)); + MSG_PRINT(("Undersize %08i ", statsCounter->Undersize)); + MSG_PRINT(("Fragments %08i \n", statsCounter->Fragments)); + MSG_PRINT(("Oversize %08i ", statsCounter->Oversize)); + MSG_PRINT(("Jabber %08i \n", statsCounter->Jabber)); + MSG_PRINT(("InMACRcvErr %08i ", statsCounter->InMACRcvErr)); + MSG_PRINT(("InFCSErr %08i \n", statsCounter->InFCSErr)); + MSG_PRINT(("Collisions %08i ", statsCounter->Collisions)); + MSG_PRINT(("Late %08i \n", statsCounter->Late)); +} + + +/* + * This sample is for 88E6093, 88E6095, 88E6185, and 88E6065 +*/ +GT_STATUS sampleGetRMONCounter3(GT_QD_DEV *dev) +{ + GT_STATUS status; + GT_LPORT port; + GT_STATS_COUNTER_SET3 statsCounterSet; + + for(port=0; portnumOfPorts; port++) + { + MSG_PRINT(("Port %i :\n",port)); + + if((status = gstatsGetPortAllCounters3(dev,port,&statsCounterSet)) != GT_OK) + { + MSG_PRINT(("gstatsGetPortAllCounters3 returned fail (%#x).\n",status)); + return status; + } + + sampleDisplayCounter3(&statsCounterSet); + + } + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Trailer/readme.txt u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Trailer/readme.txt --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Trailer/readme.txt 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Trailer/readme.txt 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,19 @@ +======================================================================== + CPU Trailer Mode Enable or Disable +======================================================================== + +This sample shows how to enable/disable CPU port's ingress trailer mode +and engress trailer mode. +For more information about trailer mode, please refer to 88E6052 Spec. +section 3.5.5 and section 3.7.3 + +trailer.c + sampleCPUTrailerEnable can be used to enable or disable CPU port's + trailer mode + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Trailer/trailer.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Trailer/trailer.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/Trailer/trailer.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/Trailer/trailer.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,50 @@ +#include +/******************************************************************************** +* trailer.c +* +* DESCRIPTION: +* This sample shows how to enable/disable CPU port's ingress and egress +* Trailer mode. +* +* DEPENDENCIES: NONE. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ + +#include "msSample.h" + +GT_STATUS sampleCPUTrailerEnable(GT_QD_DEV *dev, GT_BOOL en) +{ + GT_STATUS status; + GT_INGRESS_MODE inMode; + + if (en) /* Enable Trailer Mode */ + { + inMode = GT_TRAILER_INGRESS; + } + else + { + inMode = GT_UNMODIFY_INGRESS; + } + + /* + * Enable CPU's Ingress Trailer + */ + if((status = gprtSetIngressMode(dev,dev->cpuPortNum, inMode)) != GT_OK) + { + MSG_PRINT(("gprtSetIngressMode return Failed\n")); + return status; + } + + /* + * Enable CPU's Egress Trailer + */ + if((status = gprtSetTrailerMode(dev,dev->cpuPortNum, en)) != GT_OK) + { + MSG_PRINT(("gprtSetTrailerMode return Failed\n")); + return status; + } + + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/VlanSetup/hgVlan.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/VlanSetup/hgVlan.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/sample/VlanSetup/hgVlan.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/sample/VlanSetup/hgVlan.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,135 @@ +#include +/******************************************************************************** +* hgVlan.c +* +* DESCRIPTION: +* Setup the VLAN table of QuaterDeck so that it can be used as a Home +* Gateway. +* +* +* DEPENDENCIES: None. +* +* FILE REVISION NUMBER: +* +*******************************************************************************/ +#include "msSample.h" + +static GT_STATUS sampleHomeGatewayVlan(GT_QD_DEV *dev, + GT_LPORT numOfPorts, + GT_LPORT cpuPort); + +/* + * Get the required parameter from QuarterDeck driver. + * Notes: This routine should be called after QuarterDeck Driver has been initialized. + * (Refer to Initialization Sample) +*/ + +GT_STATUS sampleVlanSetup(GT_QD_DEV *dev) +{ + sampleHomeGatewayVlan(dev,dev->numOfPorts, dev->cpuPortNum); + + return GT_OK; +} + + +/* + * WAN Port (Port 0) and CPU Port (Port 5) are in VLAN 1 and + * all ports (including CPU Port) except WAN Port are in VLAN 2. + * 1) Set PVID for each port. (CPU port has PVID 2, which is the same as LAN) + * 2) Set Port Based VLAN Map for each port. (CPU port's VLAN Map is set for all LAN ports) + * Notes: + * 1) Trailer Mode + * When Ethernet Device, which is directly connected to CPU port, sends out a packet + * to WAN, DPV in Trailer Tag should have WAN port bit set (bit 0 in this case), and + * to LAN, Trailer Tag should be set to 0. + * Restriction : Only one group of VLAN can have multiple ports. + * 2) Header Mode + * When Ethernet Device, which is directly connected to CPU port, sends out a packet + * to WAN, VlanTable in Header Tag should have WAN ports bits set (bit 0 in this case), and + * to LAN, VlanTable in Header Tag should have LAN ports bits set (bit 1~4 and 6 in this case) +*/ +static GT_STATUS sampleHomeGatewayVlan(GT_QD_DEV *dev,GT_LPORT numOfPorts, GT_LPORT cpuPort) +{ + GT_STATUS status; + GT_LPORT index,port,portToSet; + GT_LPORT portList[MAX_SWITCH_PORTS]; + + /* + * set PVID for each port. + * the first port(port 0, WAN) has default VID 2 and all others has 1. + */ + + if((status = gvlnSetPortVid(dev,0,2)) != GT_OK) + { + MSG_PRINT(("gprtSetPortVid returned fail.\n")); + return status; + } + + for (port=1; port +/******************************************************************************** +* gtDrvConfig.h +* +* DESCRIPTION: +* Includes driver level configuration and initialization function. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 8 $ +* +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include "boardEnv/mvBoardEnvLib.h" + +/******************************************************************************* +* lport2port +* +* DESCRIPTION: +* This function converts logical port number to physical port number +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_U8 lport2port +( + IN GT_U16 portVec, + IN GT_LPORT port +) +{ + GT_U8 hwPort, tmpPort; + + tmpPort = hwPort = 0; + + while (portVec) + { + if(portVec & 0x1) + { + if((GT_LPORT)tmpPort == port) + break; + tmpPort++; + } + hwPort++; + portVec >>= 1; + } + + if (!portVec) + hwPort = GT_INVALID_PORT; + + return hwPort; +} + +/******************************************************************************* +* port2lport +* +* DESCRIPTION: +* This function converts physical port number to logical port number +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_LPORT port2lport +( + IN GT_U16 portVec, + IN GT_U8 hwPort +) +{ + GT_U8 tmpPort,port; + + port = 0; + + if (hwPort == GT_INVALID_PORT) + return (GT_LPORT)hwPort; + + if (!GT_IS_PORT_SET(portVec, hwPort)) + return (GT_LPORT)GT_INVALID_PORT; + + for (tmpPort = 0; tmpPort <= hwPort; tmpPort++) + { + if(portVec & 0x1) + { + port++; + } + portVec >>= 1; + } + + return (GT_LPORT)port-1; +} + +/******************************************************************************* +* lportvec2portvec +* +* DESCRIPTION: +* This function converts logical port vector to physical port vector +* +* INPUTS: +* portVec - physical port list in vector +* lVec - logical port vector +* OUTPUTS: +* None. +* RETURNS: +* physical port vector +* +* COMMENTS: +* +*******************************************************************************/ +GT_U32 lportvec2portvec +( + IN GT_U16 portVec, + IN GT_U32 lVec +) +{ + GT_U32 pVec, vec; + + pVec = 0; + vec = 1; + + while (portVec) + { + if(portVec & 0x1) + { + if(lVec & 0x1) + { + pVec |= vec; + } + lVec >>= 1; + } + + vec <<= 1; + portVec >>= 1; + } + + if(lVec) + return GT_INVALID_PORT_VEC; + + return pVec; +} + +/******************************************************************************* +* portvec2lportvec +* +* DESCRIPTION: +* This function converts physical port vector to logical port vector +* +* INPUTS: +* portVec - physical port list in vector +* pVec - physical port vector +* OUTPUTS: +* None. +* RETURNS: +* logical port vector +* +* COMMENTS: +* +*******************************************************************************/ +GT_U32 portvec2lportvec +( + IN GT_U16 portVec, + IN GT_U32 pVec +) +{ + GT_U32 lVec, vec; + + lVec = 0; + vec = 1; + + while (portVec) + { + if(portVec & 0x1) + { + if(pVec & 0x1) + { + lVec |= vec; + } + vec <<= 1; + } + + pVec >>= 1; + portVec >>= 1; + } + + return lVec; +} + +/******************************************************************************* +* lport2phy +* +* DESCRIPTION: +* This function converts logical port number to physical phy number. +* +* INPUTS: +* portVec - physical port list in vector +* port - logical port number +* OUTPUTS: +* None. +* RETURNS: +* physical port number +* +* COMMENTS: +* +*******************************************************************************/ +GT_U8 lport2phy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +) +{ + GT_U8 hwPort; + + /* check if it's for SERDES */ + if(dev->validSerdesVec & (1<accessMode == SMI_AUTO_SCAN_MODE) + { + /* Initialize the MII / SMI interface, search for the device */ + if((deviceId = miiSmiIfInit(dev,&highSmiDevAddr)) == 0) + { + return GT_FAIL; + } + + dev->baseRegAddr = (highSmiDevAddr)?0x10:0; + } + else + { + if((deviceId = miiSmiManualIfInit(dev,(GT_U32)dev->baseRegAddr)) == 0) + { + return GT_FAIL; + } + } + + /* Init the device's config struct. */ + dev->deviceId = deviceId >> 4; + dev->revision = (GT_U8)deviceId & 0xF; + +#ifdef CONFIG_ARCH_FEROCEON_KW + if(mvBoardIdGet() == RD_88F6281A_ID) { + /* Enable RGMII delay on Tx and Rx for CPU port */ + miiSmiIfWriteRegister(dev, 0x14,0x1a, 0x81e7); + miiSmiIfReadRegister(dev, 0x15,0x1a,&tmp); + miiSmiIfWriteRegister(dev, 0x15,0x1a,0x18); + miiSmiIfWriteRegister(dev, 0x14,0x1a,0xc1e7); + + /* swap MDI signals for PHYs 0,1,2,3,4 on RD_88F6281A_ID */ + for(phy = 0; phy < 5; phy++) { + miiSmiIfWriteRegister(dev, 0x1c,0x19,0xf); + miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9414 + (phy*0x20))); + miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp); /* used for delay */ + /* testing - read phy register #20 + miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9814+ (phy*0x20))); + miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp); + DBG_INFO(("phy-%d reg20 = 0x%x\n",phy,tmp)); + */ + } + } +#endif + + return GT_OK; +} + + +/******************************************************************************* +* driverEnable +* +* DESCRIPTION: +* This function enables the switch for full operation, after the driver +* Config function was called. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverEnable +( + IN GT_QD_DEV *dev +) +{ + GT_UNUSED_PARAM(dev); + return GT_OK; +} + + +GT_STATUS driverGetSerdesPort(GT_QD_DEV *dev, GT_U8* hwPort) +{ + switch(dev->deviceId) + { + case GT_88E6122: + if ((*hwPort<3) || (*hwPort>6)) + { + *hwPort = GT_INVALID_PORT; + } + else + { + *hwPort += 9; + } + break; + case GT_88E6131: + case GT_88E6108: + if ((*hwPort<4) || (*hwPort>7)) + { + *hwPort = GT_INVALID_PORT; + } + else + { + *hwPort += 8; + } + break; + case GT_88E6123: + case GT_88E6140: + case GT_88E6161: + case GT_88E6165: + if ((*hwPort<4) || (*hwPort>5)) + { + *hwPort = GT_INVALID_PORT; + } + else + { + *hwPort += 8; + } + break; + default: + *hwPort = GT_INVALID_PORT; + break; + } + return GT_OK; +} + +/******************************************************************************* +* driverFindPhyID +* +* DESCRIPTION: +* This function get Phy ID from Phy register 2 and 3. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* phyId - Phy ID +* +* RETURNS: +* GT_OK - if found Marvell Phy, +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static GT_STATUS driverFindPhyID +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + OUT GT_U32 *phyID +) +{ + GT_U16 ouiMsb, ouiLsb; + GT_STATUS status; + + if((status= hwReadPhyReg(dev,hwPort,2,&ouiMsb)) != GT_OK) + { + DBG_INFO(("Not able to read Phy Register.\n")); + return status; + } + + if((status= hwReadPhyReg(dev,hwPort,3,&ouiLsb)) != GT_OK) + { + DBG_INFO(("Not able to read Phy Register.\n")); + return status; + } + + if(ouiMsb != MARVELL_OUI_MSb) + return GT_FAIL; + + *phyID = (GT_U32)ouiLsb; + + return GT_OK; +} + + +/******************************************************************************* +* driverIsPhyAttached +* +* DESCRIPTION: +* This function verifies Marvell Phy. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* 1 - if Marvell Phy exists +* 0 - otherwise +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U32 driverIsPhyAttached +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort +) +{ + GT_U32 phyId; + + if(hwPort > dev->maxPhyNum) + return 0; + + if(driverFindPhyID(dev,hwPort,&phyId) != GT_OK) + { + DBG_INFO(("cannot find Marvell Phy.\n")); + return 0; + } + + return 1; +} + +/******************************************************************************* +* driverGetPhyID +* +* DESCRIPTION: +* This function reads and returns Phy ID (register 3) of Marvell Phy. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* phyId - if Marvell Phy exists +* GT_INVALID_PORT - otherwise +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_U32 driverGetPhyID +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort +) +{ + GT_U32 phyId; + + if(hwPort > dev->maxPhyNum) + return GT_INVALID_PHY; + + if(driverFindPhyID(dev,hwPort,&phyId) != GT_OK) + { + DBG_INFO(("cannot find Marvell Phy.\n")); + return GT_INVALID_PHY; + } + + return phyId; +} + +/******************************************************************************* +* driverPagedAccessStart +* +* DESCRIPTION: +* This function stores page register and Auto Reg Selection mode if needed. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* pageType - type of the page registers +* +* OUTPUTS: +* autoOn - GT_TRUE if Auto Reg Selection enabled, GT_FALSE otherwise. +* pageReg - Page Register Data +* +* RETURNS: +* GT_OK - if success +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverPagedAccessStart +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_U8 pageType, + OUT GT_BOOL *autoOn, + OUT GT_U16 *pageReg +) +{ + GT_U16 data; + GT_STATUS status; + + switch(pageType) + { + case GT_PHY_PAGE_WRITE_BACK: + break; + case GT_PHY_PAGE_DIS_AUTO1: /* 88E1111 Type */ + if((status= hwGetPhyRegField(dev,hwPort,27,9,1,&data)) != GT_OK) + { + DBG_INFO(("Not able to read Phy Register.\n")); + return status; + } + + data ^= 0x1; /* toggle bit 0 */ + BIT_2_BOOL(data, *autoOn); + + if (*autoOn) /* Auto On */ + { + if((status= hwSetPhyRegField(dev,hwPort,27,9,1,data)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Register.\n")); + return status; + } + } + + break; + case GT_PHY_PAGE_DIS_AUTO2: /* 88E1112 Type */ + if((status= hwGetPhyRegField(dev,hwPort,22,15,1,&data)) != GT_OK) + { + DBG_INFO(("Not able to read Phy Register.\n")); + return status; + } + + BIT_2_BOOL(data, *autoOn); + data ^= 0x1; /* toggle bit 0 */ + + if (*autoOn) /* Auto On */ + { + if((status= hwSetPhyRegField(dev,hwPort,22,15,1,data)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Register.\n")); + return status; + } + } + + break; + + case GT_PHY_NO_PAGE: + default: + /* Nothing to do */ + return GT_OK; + } + + + if((status= hwGetPhyRegField(dev,hwPort,22,0,8,pageReg)) != GT_OK) + { + DBG_INFO(("Not able to read Phy Register.\n")); + return status; + } + + return GT_OK; +} + + +/******************************************************************************* +* driverPagedAccessStop +* +* DESCRIPTION: +* This function restores page register and Auto Reg Selection mode if needed. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* pageType - type of the page registers +* autoOn - GT_TRUE if Auto Reg Selection enabled, GT_FALSE otherwise. +* pageReg - Page Register Data +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - if success +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverPagedAccessStop +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_U8 pageType, + IN GT_BOOL autoOn, + IN GT_U16 pageReg +) +{ + GT_U16 data; + GT_STATUS status; + + switch(pageType) + { + case GT_PHY_PAGE_WRITE_BACK: + break; + case GT_PHY_PAGE_DIS_AUTO1: /* 88E1111 Type */ + if (autoOn) /* Auto On */ + { + data = 0; + if((status= hwSetPhyRegField(dev,hwPort,27,9,1,data)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Register.\n")); + return status; + } + } + + break; + case GT_PHY_PAGE_DIS_AUTO2: /* 88E1112 Type */ + if (autoOn) /* Auto On */ + { + data = 1; + if((status= hwSetPhyRegField(dev,hwPort,22,15,1,data)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Register.\n")); + return status; + } + } + + break; + + case GT_PHY_NO_PAGE: + default: + /* Nothing to do */ + return GT_OK; + } + + + if((status= hwSetPhyRegField(dev,hwPort,22,0,8,pageReg)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Register.\n")); + return status; + } + + return GT_OK; +} + + +/******************************************************************************* +* driverFindPhyInformation +* +* DESCRIPTION: +* This function gets information of Phy connected to the given port. +* PhyInfo structure should have valid Phy ID. +* +* INPUTS: +* hwPort - port number where the Phy is connected +* +* OUTPUTS: +* phyId - Phy ID +* +* RETURNS: +* GT_OK - if found Marvell Phy, +* GT_FAIL - othrwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS driverFindPhyInformation +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + OUT GT_PHY_INFO *phyInfo +) +{ + GT_U32 phyId; + GT_U16 data; + + phyId = phyInfo->phyId; + + switch (phyId & PHY_MODEL_MASK) + { + case DEV_E3082: + phyInfo->anyPage = 0xFFFFFFFF; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_MAC_IF_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_COPPER; + phyInfo->vctType = GT_PHY_VCT_TYPE1; + phyInfo->exStatusType = 0; + if ((phyId & PHY_REV_MASK) < 9) + phyInfo->dteType = GT_PHY_DTE_TYPE1; /* need workaround */ + else + phyInfo->dteType = GT_PHY_DTE_TYPE5; + + phyInfo->pktGenType = 0; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_NO_PAGE; + break; + + case DEV_E104X: + phyInfo->anyPage = 0xFFFFFFFF; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_EXTERNAL_LOOP; + + phyInfo->dteType = 0; + if ((phyId & PHY_REV_MASK) < 3) + phyInfo->flag &= ~GT_PHY_VCT_CAPABLE; /* VCT is not supported */ + else if ((phyId & PHY_REV_MASK) == 3) + phyInfo->vctType = GT_PHY_VCT_TYPE3; /* Need workaround */ + else + phyInfo->vctType = GT_PHY_VCT_TYPE2; + phyInfo->exStatusType = 0; + + phyInfo->pktGenType = 0; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_NO_PAGE; + + break; + + case DEV_E1111: + phyInfo->anyPage = 0xFFF1FE0C; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_GIGABIT|GT_PHY_RESTRICTED_PAGE; + + phyInfo->vctType = GT_PHY_VCT_TYPE2; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE1; + if ((phyId & PHY_REV_MASK) < 2) + phyInfo->dteType = GT_PHY_DTE_TYPE3; /* Need workaround */ + else + phyInfo->dteType = GT_PHY_DTE_TYPE2; + + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE1; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_DIS_AUTO1; + break; + + case DEV_E1112: + phyInfo->anyPage = 0x1BC0780C; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT|GT_PHY_RESTRICTED_PAGE| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + + phyInfo->vctType = GT_PHY_VCT_TYPE4; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE2; + phyInfo->dteType = GT_PHY_DTE_TYPE4; + + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_DIS_AUTO2; + break; + + case DEV_E114X: + phyInfo->anyPage = 0x2FF1FE0C; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_GIGABIT|GT_PHY_RESTRICTED_PAGE; + + phyInfo->vctType = GT_PHY_VCT_TYPE2; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE1; + if ((phyId & PHY_REV_MASK) < 4) + phyInfo->dteType = GT_PHY_DTE_TYPE3; /* Need workaround */ + else + phyInfo->dteType = GT_PHY_DTE_TYPE2; + + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE1; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_DIS_AUTO1; + + break; + + case DEV_E1149: + phyInfo->anyPage = 0x2040FFFF; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + phyInfo->vctType = GT_PHY_VCT_TYPE4; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE3; + phyInfo->dteType = GT_PHY_DTE_TYPE4; + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK; + break; + + case DEV_G15LV: + if (IS_IN_DEV_GROUP(dev,DEV_88E6108)) + { + phyInfo->anyPage = 0x2040FFFF; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + phyInfo->vctType = GT_PHY_VCT_TYPE4; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE3; + phyInfo->dteType = GT_PHY_DTE_TYPE4; + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK; + } + else /* 88E6165 family */ + { + phyInfo->anyPage = 0x2040FFFF; + phyInfo->flag = GT_PHY_ADV_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + phyInfo->vctType = GT_PHY_ADV_VCT_TYPE2; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE6; + phyInfo->dteType = GT_PHY_DTE_TYPE4; + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK; + } + break; + + case DEV_EC010: + phyInfo->anyPage = 0x2040780C; + phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT|GT_PHY_RESTRICTED_PAGE| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP; + phyInfo->vctType = GT_PHY_VCT_TYPE2; + phyInfo->exStatusType = 0; + phyInfo->dteType = GT_PHY_DTE_TYPE3; /* Need workaround */ + phyInfo->pktGenType = 0; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK; + break; + + case DEV_S15LV: + phyInfo->anyPage = 0xFFFFFFFF; + phyInfo->flag = GT_PHY_SERDES_CORE|GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + phyInfo->vctType = 0; + phyInfo->exStatusType = 0; + phyInfo->dteType = 0; + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE3; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE3; + phyInfo->lineLoopType = GT_PHY_LINE_LB_TYPE4; + phyInfo->exLoopType = 0; + phyInfo->pageType = GT_PHY_NO_PAGE; + break; + + case DEV_G65G: + phyInfo->anyPage = 0x2040FFFF; + phyInfo->flag = GT_PHY_ADV_VCT_CAPABLE|GT_PHY_DTE_CAPABLE| + GT_PHY_EX_CABLE_STATUS| + GT_PHY_GIGABIT| + GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP| + GT_PHY_PKT_GENERATOR; + phyInfo->vctType = GT_PHY_ADV_VCT_TYPE2; + phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE6; + phyInfo->dteType = GT_PHY_DTE_TYPE4; + phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2; + phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1; + phyInfo->lineLoopType = 0; + phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0; + phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK; + break; + + default: + return GT_FAIL; + } + + if (phyInfo->flag & GT_PHY_GIGABIT) + { + if(hwGetPhyRegField(dev,hwPort,15,12,4,&data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,15)); + return GT_FAIL; + } + + if(data & QD_GIGPHY_1000X_CAP) + phyInfo->flag |= GT_PHY_FIBER; + + if(data & QD_GIGPHY_1000T_CAP) + { + phyInfo->flag |= GT_PHY_COPPER; + } + else + { + phyInfo->flag &= ~(GT_PHY_VCT_CAPABLE|GT_PHY_EX_CABLE_STATUS|GT_PHY_DTE_CAPABLE|GT_PHY_ADV_VCT_CAPABLE); + } + } + + return GT_OK; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/gtDrvEvents.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/gtDrvEvents.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/gtDrvEvents.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/gtDrvEvents.c 2011-04-04 13:57:35.075596941 -0400 @@ -0,0 +1,95 @@ +#include +/******************************************************************************** +* gtDrvEvents.c +* +* DESCRIPTION: +* This file includes function declarations for QuarterDeck interrupts +* configuration and handling. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 1 $ +* +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* drvEventsInit +* +* DESCRIPTION: +* This function initializes the driver's interrupt handling mechanism. +* +* INPUTS: +* intVecNum - The interrupt vector the switch is connected to. +* isrFunc - A pointer to the Interrupt Service Routine to be +* connected to the given interrupt vector. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success, +* GT_FAIL - otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS drvEventsInit +( + IN GT_QD_DEV *dev, + IN GT_U32 intVecNum, + IN GT_VOIDFUNCPTR isrFunc +) +{ + GT_UNUSED_PARAM(dev); + GT_UNUSED_PARAM(intVecNum); + GT_UNUSED_PARAM(isrFunc); +#if 0 + return osInterruptConnect(intVecNum,isrFunc,0); +#endif + return GT_OK; +} + + + +/******************************************************************************* +* eventQdSr +* +* DESCRIPTION: +* QuarterDeck interrupt service routine. +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* None. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_BOOL eventQdSr +( + IN GT_QD_DEV* dev, + OUT GT_U16* intCause +) +{ + GT_STATUS retVal; /* Function calls return value. */ + + retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,0,4,intCause); + + if(retVal != GT_OK) + return GT_FALSE; + + return (*intCause)?GT_TRUE:GT_FALSE; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/gtHwCntl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/gtHwCntl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/gtHwCntl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/gtHwCntl.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,2474 @@ +#include +/******************************************************************************** +* gtHwCntl.c +* +* DESCRIPTION: +* Functions declarations for Hw accessing quarterDeck phy, internal and +* global registers. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +* +*******************************************************************************/ + +#include +#include +#include +#include + + +static GT_STATUS hwReadPPU(GT_QD_DEV *dev, GT_U16 *data); +static GT_STATUS hwWritePPU(GT_QD_DEV *dev, GT_U16 data); +static GT_STATUS coreReadPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + OUT GT_U16 *data +); +static GT_STATUS coreWritePhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +); +static GT_STATUS coreReadPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + OUT GT_U16 *data +); +static GT_STATUS coreWritePagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + IN GT_U16 data +); + +static GT_STATUS phyRegReadPPUEn (GT_QD_DEV* dev, unsigned int phyAddr , unsigned int regAddr, + GT_U16* value); +static GT_STATUS phyRegWritePPUEn (GT_QD_DEV* dev, unsigned int phyAddr , unsigned int regAddr, + GT_U16 value); +static GT_STATUS phyReadGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +); +static GT_STATUS phyWriteGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +); + + +/******************************************************************************* +* portToSmiMapping +* +* DESCRIPTION: +* This function mapps port to smi address +* +* INPUTS: +* dev - device context +* portNum - Port number to read the register for. +* accessType - type of register (Phy, Port, or Global) +* +* OUTPUTS: +* None. +* +* RETURNS: +* smiAddr - smi address. +* +*******************************************************************************/ +GT_U8 portToSmiMapping +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U32 accessType +) +{ + GT_U8 smiAddr; + + if(IS_IN_DEV_GROUP(dev,DEV_8PORT_SWITCH)) + { + switch(accessType) + { + case PHY_ACCESS: + if (dev->validPhyVec & (1<validPortVec & (1<baseRegAddr; + switch(accessType) + { + case PHY_ACCESS: + if (dev->validPhyVec & (1<validPortVec & (1<multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreReadPhyReg(dev, portNum, regAddr, data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwWritePhyReg +* +* DESCRIPTION: +* This function writes to a switch's port phy register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreWritePhyReg(dev, portNum, regAddr, data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwGetPhyRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port phy register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +) +{ + GT_U16 mask; /* Bits mask to be read */ + GT_U16 tmpData; + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreReadPhyReg(dev, portNum, regAddr, &tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + if (retVal != GT_OK) + return retVal; + + CALC_MASK(fieldOffset,fieldLength,mask); + + tmpData = (tmpData & mask) >> fieldOffset; + *data = tmpData; + + DBG_INFO(("Read from phy(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data)); + + return retVal; +} + + +/******************************************************************************* +* hwSetPhyRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port phy register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +) +{ + GT_U16 mask; + GT_U16 tmpData; + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreReadPhyReg(dev, portNum, regAddr, &tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= ((data << fieldOffset) & mask); + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset, + fieldLength,data)); + + retVal = coreWritePhyReg(dev, portNum, regAddr, tmpData); + + gtSemGive(dev,dev->multiAddrSem); + return retVal; +} + + +/******************************************************************************* +* hwReadPagedPhyReg +* +* DESCRIPTION: +* This function reads a switch's port phy register in page mode. +* +* INPUTS: +* portNum - Port number to read the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* anyPage - Any Page register vector +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + OUT GT_U16 *data +) +{ + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreReadPagedPhyReg(dev,portNum,pageNum,regAddr,anyPage,data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwWritePagedPhyReg +* +* DESCRIPTION: +* This function writes to a switch's port phy register in page mode. +* +* INPUTS: +* portNum - Port number to write the register for. +* pageNum - Page number of the register to be written. +* regAddr - The register's address. +* anyPage - Any Page register vector +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + IN GT_U16 data +) +{ + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreWritePagedPhyReg(dev,portNum,pageNum,regAddr,anyPage,data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwGetPagedPhyRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port phy register +* in page mode. +* +* INPUTS: +* portNum - Port number to read the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* anyPage - Any Page register vector +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPagedPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U32 anyPage, + OUT GT_U16 *data +) +{ + GT_U16 mask; /* Bits mask to be read */ + GT_U16 tmpData; + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = coreReadPagedPhyReg(dev,portNum,pageNum,regAddr,anyPage,&tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + if(retVal != GT_OK) + { + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + tmpData = (tmpData & mask) >> fieldOffset; + *data = tmpData; + + DBG_INFO(("Read from phy(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data)); + + return GT_OK; +} + + +/******************************************************************************* +* hwSetPagedPhyRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port phy register +* in page mode +* +* INPUTS: +* portNum - Port number to write the register for. +* pageNum - Page number of the register to be read. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* anyPage - Any Page register vector +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPagedPhyRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U32 anyPage, + IN GT_U16 data +) +{ + GT_U16 mask; + GT_U16 tmpData; + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + if((retVal=coreReadPagedPhyReg(dev,portNum,pageNum,regAddr,anyPage,&tmpData)) != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= ((data << fieldOffset) & mask); + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset, + fieldLength,data)); + retVal = coreWritePagedPhyReg(dev,portNum,pageNum,regAddr,anyPage,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwPhyReset +* +* DESCRIPTION: +* This function performs softreset and waits until reset completion. +* +* INPUTS: +* portNum - Port number to write the register for. +* u16Data - data should be written into Phy control register. +* if this value is 0xFF, normal operation occcurs (read, +* update, and write back.) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS hwPhyReset +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U16 u16Data +) +{ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U32 retryCount; + GT_BOOL pd = GT_FALSE; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + if((retVal=coreReadPhyReg(dev,portNum,0,&tmpData)) + != GT_OK) + { + DBG_INFO(("Reading Register failed\n")); + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + if (tmpData & 0x800) + { + pd = GT_TRUE; + } + + if (u16Data != 0xFF) + { + tmpData = u16Data; + } + + /* Set the desired bits to 0. */ + if (pd) + { + tmpData |= 0x800; + } + else + { + tmpData |= 0x8000; + } + + if((retVal=coreWritePhyReg(dev,portNum,0,tmpData)) + != GT_OK) + { + DBG_INFO(("Writing to register failed\n")); + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + if (pd) + { + gtSemGive(dev,dev->multiAddrSem); + return GT_OK; + } + + for (retryCount = 0x1000; retryCount > 0; retryCount--) + { + if((retVal=coreReadPhyReg(dev,portNum,0,&tmpData)) != GT_OK) + { + DBG_INFO(("Reading register failed\n")); + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + if ((tmpData & 0x8000) == 0) + break; + } + + gtSemGive(dev,dev->multiAddrSem); + + if (retryCount == 0) + { + DBG_INFO(("Reset bit is not cleared\n")); + return GT_FAIL; + } + + return GT_OK; +} + +/****************************************************************************/ +/* Per port registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadPortReg +* +* DESCRIPTION: +* This function reads a switch's port register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadPortReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PORT_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + DBG_INFO(("Read from port(%d) register: phyAddr 0x%x, regAddr 0x%x, ", + portNum,phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",*data)); + return retVal; +} + + +/******************************************************************************* +* hwWritePortReg +* +* DESCRIPTION: +* This function writes to a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWritePortReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PORT_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + DBG_INFO(("Write to port(%d) register: phyAddr 0x%x, regAddr 0x%x, ", + portNum,phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",data)); + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwGetPortRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's port register. +* +* INPUTS: +* portNum - Port number to read the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetPortRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +) +{ + GT_U16 mask; /* Bits mask to be read */ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PORT_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + if (retVal != GT_OK) + return retVal; + + CALC_MASK(fieldOffset,fieldLength,mask); + + tmpData = (tmpData & mask) >> fieldOffset; + *data = tmpData; + DBG_INFO(("Read from port(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data)); + + return GT_OK; +} + + +/******************************************************************************* +* hwSetPortRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetPortRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +) +{ + GT_U16 mask; + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PORT_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= ((data << fieldOffset) & mask); + DBG_INFO(("Write to port(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset, + fieldLength,data)); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwSetPortRegBits +* +* DESCRIPTION: +* This function writes to specified bits in a switch's port register. +* +* INPUTS: +* portNum - Port number to write the register for. +* regAddr - The register's address. +* mask - The bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. When Data is 0x1002 and mask is 0xF00F, 0001b is written to bit[31:24] +* and 0010b is written to bit[3:0] +* +*******************************************************************************/ +GT_STATUS hwSetPortRegBits +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 mask, + IN GT_U16 data +) +{ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PORT_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= (data & mask); + DBG_INFO(("Write to port(%d) register: regAddr 0x%x, ", + portNum,regAddr)); + DBG_INFO(("mask %d, data 0x%x.\n",mask,data)); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + + +/****************************************************************************/ +/* Global registers related functions. */ +/****************************************************************************/ + +/******************************************************************************* +* hwReadGlobalReg +* +* DESCRIPTION: +* This function reads a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + DBG_INFO(("read from global register: phyAddr 0x%x, regAddr 0x%x, ", + phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",*data)); + return retVal; +} + + +/******************************************************************************* +* hwWriteGlobalReg +* +* DESCRIPTION: +* This function writes to a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + + DBG_INFO(("Write to global register: phyAddr 0x%x, regAddr 0x%x, ", + phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",data)); + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwGetGlobalRegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetGlobalRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +) +{ + GT_U16 mask; /* Bits mask to be read */ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + if(retVal != GT_OK) + { + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + tmpData = (tmpData & mask) >> fieldOffset; + *data = tmpData; + DBG_INFO(("Read from global register: regAddr 0x%x, ", + regAddr)); + DBG_INFO(("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data)); + + return GT_OK; +} + + +/******************************************************************************* +* hwSetGlobalRegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's global register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetGlobalRegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +) +{ + GT_U16 mask; + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= ((data << fieldOffset) & mask); + + DBG_INFO(("Write to global register: regAddr 0x%x, ", + regAddr)); + DBG_INFO(("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset, + fieldLength,data)); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + +/******************************************************************************* +* hwReadGlobal2Reg +* +* DESCRIPTION: +* This function reads a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + DBG_INFO(("read from global 2 register: phyAddr 0x%x, regAddr 0x%x, ", + phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",*data)); + return retVal; +} + + +/******************************************************************************* +* hwWriteGlobal2Reg +* +* DESCRIPTION: +* This function writes to a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* data - The data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + DBG_INFO(("Write to global 2 register: phyAddr 0x%x, regAddr 0x%x, ", + phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",data)); + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwGetGlobal2RegField +* +* DESCRIPTION: +* This function reads a specified field from a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to read. +* +* OUTPUTS: +* data - The read register field. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwGetGlobal2RegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + OUT GT_U16 *data +) +{ + GT_U16 mask; /* Bits mask to be read */ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + if(retVal != GT_OK) + return retVal; + + CALC_MASK(fieldOffset,fieldLength,mask); + tmpData = (tmpData & mask) >> fieldOffset; + *data = tmpData; + DBG_INFO(("Read from global 2 register: regAddr 0x%x, ", + regAddr)); + DBG_INFO(("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data)); + + return GT_OK; +} + + +/******************************************************************************* +* hwSetGlobal2RegField +* +* DESCRIPTION: +* This function writes to specified field in a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* fieldOffset - The field start bit index. (0 - 15) +* fieldLength - Number of bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. The sum of fieldOffset & fieldLength parameters must be smaller- +* equal to 16. +* +*******************************************************************************/ +GT_STATUS hwSetGlobal2RegField +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U8 fieldOffset, + IN GT_U8 fieldLength, + IN GT_U16 data +) +{ + GT_U16 mask; + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + CALC_MASK(fieldOffset,fieldLength,mask); + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= ((data << fieldOffset) & mask); + + DBG_INFO(("Write to global 2 register: regAddr 0x%x, ", + regAddr)); + DBG_INFO(("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset, + fieldLength,data)); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + +/******************************************************************************* +* hwSetGlobal2RegBits +* +* DESCRIPTION: +* This function writes to specified bits in a switch's global 2 register. +* +* INPUTS: +* regAddr - The register's address. +* mask - The bits to write. +* data - Data to be written. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. When Data is 0x1002 and mask is 0xF00F, 0001b is written to bit[31:24] +* and 0010b is written to bit[3:0] +* +*******************************************************************************/ +GT_STATUS hwSetGlobal2RegBits +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 mask, + IN GT_U16 data +) +{ + GT_U16 tmpData; + GT_STATUS retVal; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,&tmpData); + + if(retVal != GT_OK) + { + gtSemGive(dev,dev->multiAddrSem); + return retVal; + } + + /* Set the desired bits to 0. */ + tmpData &= ~mask; + /* Set the given data into the above reset bits. */ + tmpData |= (data & mask); + + DBG_INFO(("Write to global 2 register: regAddr 0x%x, ", + regAddr)); + DBG_INFO(("mask %d, data 0x%x.\n",mask,data)); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,tmpData); + + gtSemGive(dev,dev->multiAddrSem); + + return retVal; +} + + +/******************************************************************************* +* hwReadMiiReg +* +* DESCRIPTION: +* This function reads a switch register. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwReadMiiReg +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + DBG_INFO(("Read from phy(0x%x) register: regAddr 0x%x, data 0x%x.\n", + phyAddr,regAddr,*data)); + + return retVal; +} + + +/******************************************************************************* +* hwWriteMiiReg +* +* DESCRIPTION: +* This function writes a switch register. +* +* INPUTS: +* phyAddr - Phy Address to read the register for.( 0 ~ 0x1F ) +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS hwWriteMiiReg +( + IN GT_QD_DEV *dev, + IN GT_U8 phyAddr, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_STATUS retVal; + + gtSemTake(dev,dev->multiAddrSem,OS_WAIT_FOREVER); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + + gtSemGive(dev,dev->multiAddrSem); + + DBG_INFO(("Write to phy(0x%x) register: regAddr 0x%x, data 0x%x.\n", + phyAddr,regAddr,data)); + + return retVal; +} + + +/******************************************************************************* +* hwReadPPU +* +* DESCRIPTION: +* This function reads PPU bit in Global Register +* +* INPUTS: +* None. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* This function can be used to access PHY register connected to Gigabit +* Switch. +* Semaphore should be acquired before this function get called. +* +*******************************************************************************/ +static GT_STATUS hwReadPPU +( + IN GT_QD_DEV *dev, + OUT GT_U16 *data +) +{ + GT_STATUS retVal; + GT_U16 tmpData; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + retVal = miiSmiIfReadRegister(dev,phyAddr,4,&tmpData); + + if(retVal != GT_OK) + { + return retVal; + } + + *data = (tmpData >> 14) & 0x1; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* hwWritePPU +* +* DESCRIPTION: +* This function writes PPU bit in Global Register +* +* INPUTS: +* data - The value to write into PPU bit +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, or +* GT_FAIL otherwise. +* +* COMMENTS: +* This function can be used to access PHY register connected to Gigabit +* Switch. +* Semaphore should be acquired before this function get called. +* +*******************************************************************************/ +static GT_STATUS hwWritePPU +( + IN GT_QD_DEV *dev, + IN GT_U16 data +) +{ + GT_STATUS retVal; + GT_U16 tmpData; + GT_U8 phyAddr; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + retVal = miiSmiIfReadRegister(dev,phyAddr,4,&tmpData); + + if(retVal != GT_OK) + { + return retVal; + } + + if (data) + tmpData |= (0x1 << 14); + else + tmpData &= ~(0x1 << 14); + + retVal = miiSmiIfWriteRegister(dev,phyAddr,4,tmpData); + + if(retVal != GT_OK) + { + return retVal; + } + + /* busy wait - till PPU is actually disabled */ + if (data == 0) /* disable PPU */ + { + gtDelay(250); + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +static GT_STATUS coreReadPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal, retPPU; + GT_U16 orgPPU = 0; + GT_BOOL usePPU = GT_FALSE; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PHY_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + if(IS_IN_DEV_GROUP(dev,DEV_PPU_READ_ONLY)) + { + if((IS_IN_DEV_GROUP(dev,DEV_PPU_SERDES_ACCESS_RES)) && (dev->validSerdesVec && (1<revision != 0) + usePPU = GT_TRUE; + } + else + { + usePPU = GT_TRUE; + } + } + + /* Disable PPU so that External Phy can be accessible */ + if (!usePPU) + { + if((retPPU=hwWritePPU(dev, 0)) != GT_OK) + { + return retPPU; + } + } + } + } + + if (usePPU) + { + retVal = phyRegReadPPUEn (dev,phyAddr,regAddr,data); + } + else + { + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + } + + DBG_INFO(("Read from phy(%d) register: phyAddr 0x%x, regAddr 0x%x, ", + portNum,phyAddr,regAddr)); + + if(orgPPU && (!usePPU)) + { + if((retPPU=hwWritePPU(dev, orgPPU)) != GT_OK) + { + return retPPU; + } + } + + return retVal; +} + + +static GT_STATUS coreWritePhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal, retPPU; + GT_U16 orgPPU = 0; + GT_BOOL usePPU = GT_FALSE; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PHY_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + if(IS_IN_DEV_GROUP(dev,DEV_PPU_READ_ONLY)) + { + if((IS_IN_DEV_GROUP(dev,DEV_PPU_SERDES_ACCESS_RES)) && (dev->validSerdesVec && (1<revision != 0) + usePPU = GT_TRUE; + } + else + { + usePPU = GT_TRUE; + } + } + + /* Disable PPU so that External Phy can be accessible */ + if (!usePPU) + { + if((retPPU=hwWritePPU(dev, 0)) != GT_OK) + { + return retPPU; + } + } + } + } + + DBG_INFO(("Write to phy(%d) register: phyAddr 0x%x, regAddr 0x%x, ", + portNum,phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",data)); + + if (usePPU) + { + retVal = phyRegWritePPUEn (dev,phyAddr,regAddr,data); + } + else + { + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + } + + if(orgPPU && (!usePPU)) + { + if((retPPU=hwWritePPU(dev, orgPPU)) != GT_OK) + { + return retPPU; + } + } + + return retVal; +} + + +static GT_STATUS coreReadPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr,pageAddr; + GT_STATUS retVal, retPPU; + GT_U16 orgPPU, tmpData, orgPage; + GT_BOOL usePPU = GT_FALSE; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PHY_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + orgPPU = 0; + + if(IS_IN_DEV_GROUP(dev,DEV_PPU_READ_ONLY)) + { + if((IS_IN_DEV_GROUP(dev,DEV_PPU_SERDES_ACCESS_RES)) && (dev->validSerdesVec && (1<revision != 0) + usePPU = GT_TRUE; + } + else + { + usePPU = GT_TRUE; + } + } + + /* Disable PPU so that External Phy can be accessible */ + if (!usePPU) + { + if((retPPU=hwWritePPU(dev, 0)) != GT_OK) + { + return retPPU; + } + } + } + } + + if(anyPage & (1 << regAddr)) + { + if (usePPU) + { + retVal = phyRegReadPPUEn (dev,phyAddr,regAddr,data); + } + else + { + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + } + DBG_INFO(("Read from phy(%d) register: smiAddr 0x%x, pageNum 0x%x, regAddr 0x%x\n", + portNum,phyAddr,pageNum,regAddr)); + } + else + { + pageAddr = GT_GET_PAGE_ADDR(regAddr); + + if (usePPU) + { + retVal = phyRegReadPPUEn (dev,phyAddr,regAddr,&orgPage); + } + else + { + retVal = miiSmiIfReadRegister(dev,phyAddr,pageAddr,&orgPage); + } + + if (retVal != GT_OK) + { + DBG_INFO(("Reading page register failed\n")); + return retVal; + } + + if(pageAddr == 22) + tmpData = orgPage & 0xFF00; + else + tmpData = orgPage & 0xFFC0; + tmpData |= pageNum; + + if (usePPU) + { + if((retVal = phyRegWritePPUEn(dev,phyAddr,pageAddr,tmpData)) == GT_OK) + { + retVal = phyRegReadPPUEn (dev,phyAddr,regAddr,data); + + DBG_INFO(("Read from phy(%d) register: smiAddr 0x%x, pageNum 0x%x, regAddr 0x%x\n", + portNum,phyAddr,pageNum,regAddr)); + } + } + else + { + if((retVal = miiSmiIfWriteRegister(dev,phyAddr,pageAddr,tmpData)) == GT_OK) + { + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + DBG_INFO(("Read from phy(%d) register: smiAddr 0x%x, pageNum 0x%x, regAddr 0x%x\n", + portNum,phyAddr,pageNum,regAddr)); + } + } + } + + if(orgPPU && (!usePPU)) + { + if((retPPU=hwWritePPU(dev, orgPPU)) != GT_OK) + { + return retPPU; + } + } + + return retVal; + +} + + +static GT_STATUS coreWritePagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U8 portNum, + IN GT_U8 pageNum, + IN GT_U8 regAddr, + IN GT_U32 anyPage, + IN GT_U16 data +) +{ + GT_U8 phyAddr,pageAddr; + GT_STATUS retVal, retPPU; + GT_U16 orgPPU, tmpData, orgPage; + GT_BOOL usePPU = GT_FALSE; + + phyAddr = CALC_SMI_DEV_ADDR(dev, portNum, PHY_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + orgPPU = 0; + + if(IS_IN_DEV_GROUP(dev,DEV_PPU_READ_ONLY)) + { + if((IS_IN_DEV_GROUP(dev,DEV_PPU_SERDES_ACCESS_RES)) && (dev->validSerdesVec && (1<revision != 0) + usePPU = GT_TRUE; + } + else + { + usePPU = GT_TRUE; + } + } + + /* Disable PPU so that External Phy can be accessible */ + if (!usePPU) + { + if((retPPU=hwWritePPU(dev, 0)) != GT_OK) + { + return retPPU; + } + } + } + } + + DBG_INFO(("Write to phy(%d) register: smiAddr 0x%x, pageNum 0x%x, regAddr 0x%x\n", + portNum,phyAddr,pageNum,regAddr)); + DBG_INFO(("data 0x%x.\n",data)); + + if(anyPage & (1 << regAddr)) + { + if (usePPU) + { + retVal = phyRegWritePPUEn (dev,phyAddr,regAddr,data); + } + else + { + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + } + } + else + { + pageAddr = GT_GET_PAGE_ADDR(regAddr); + + if (usePPU) + { + retVal = phyRegReadPPUEn (dev,phyAddr,regAddr,&orgPage); + } + else + { + retVal = miiSmiIfReadRegister(dev,phyAddr,pageAddr,&orgPage); + } + + if (retVal != GT_OK) + { + DBG_INFO(("Reading page register failed\n")); + return retVal; + } + + if(pageAddr == 22) + tmpData = orgPage & 0xFF00; + else + tmpData = orgPage & 0xFFC0; + tmpData |= pageNum; + + if (usePPU) + { + if((retVal = phyRegWritePPUEn(dev,phyAddr,pageAddr,tmpData)) == GT_OK) + { + retVal = phyRegWritePPUEn(dev,phyAddr,regAddr,data); + } + } + else + { + if((retVal = miiSmiIfWriteRegister(dev,phyAddr,pageAddr,tmpData)) == GT_OK) + { + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + } + } + } + + if(orgPPU && (!usePPU)) + { + if((retPPU=hwWritePPU(dev, orgPPU)) != GT_OK) + { + return retPPU; + } + } + + return retVal; +} + + +/***************************************************************************** +* phyRegReadPPUEn +* +* DESCRIPTION: +* This function reads phy register data when PPU is enabled. +* +* INPUTS: +* phyAddr - The PHY address to be read. +* regAddr - The register address to read. +* value - The storage where register date to be saved. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_TRUE - on success +* GT_FALSE - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static GT_STATUS phyRegReadPPUEn (GT_QD_DEV* dev, unsigned int phyAddr , unsigned int regAddr, + unsigned short* value) +{ + volatile unsigned int timeOut; /* in 100MS units */ + volatile int i; + GT_U16 smiReg; + + DBG_INFO(("Read Phy register while PPU Enabled\n")); + + /* first check that it is not busy */ + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + DBG_INFO(("Reading Phy register Failed\n")); + return GT_FAIL; + } + timeOut = QD_SMI_ACCESS_LOOP; /* initialize the loop count */ + + if(smiReg & QD_SMI_BUSY) + { + for(i = 0 ; i < QD_SMI_TIMEOUT ; i++); + do + { + if(timeOut-- < 1 ) + { + DBG_INFO(("Reading Phy register Timed Out\n")); + return GT_FAIL; + } + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + DBG_INFO(("Reading Phy register Failed\n")); + return GT_FAIL; + } + } while (smiReg & QD_SMI_BUSY); + } + + smiReg = QD_SMI_BUSY | (phyAddr << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_READ << QD_SMI_OP_BIT) | + (regAddr << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT); + + if(phyWriteGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, smiReg) != GT_OK) + { + return GT_FAIL; + } + timeOut = QD_SMI_ACCESS_LOOP; /* initialize the loop count */ + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + return GT_FAIL; + } + + if(smiReg & QD_SMI_BUSY) + { + for(i = 0 ; i < QD_SMI_TIMEOUT ; i++); + do + { + if(timeOut-- < 1 ) + { + DBG_INFO(("Reading Phy register Timed Out\n")); + return GT_FALSE; + } + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + DBG_INFO(("Reading Phy register Failed\n")); + return GT_FAIL; + } + } while (smiReg & QD_SMI_BUSY); + } + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_DATA, &smiReg) != GT_OK) + { + DBG_INFO(("Reading Phy register Failed\n")); + return GT_FAIL; + } + *value = (unsigned short)smiReg; + + return GT_OK; +} + +/***************************************************************************** +* phyRegWritePPUEn +* +* DESCRIPTION: +* This function writes data to a phy register when PPU is enabled. +* +* INPUTS: +* phyAddr - The PHY address to be read. +* regAddr - The register address to read. +* value - The data to be written into the register. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_TRUE - on success +* GT_FALSE - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ + +static GT_STATUS phyRegWritePPUEn (GT_QD_DEV* dev, unsigned int phyAddr , unsigned int regAddr, + unsigned short value) +{ + volatile unsigned int timeOut; /* in 100MS units */ + volatile int i; + GT_U16 smiReg; + + DBG_INFO(("Writing Phy register while PPU Enabled\n")); + + /* first check that it is not busy */ + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + DBG_INFO(("Reading Phy register Failed\n")); + return GT_FAIL; + } + timeOut = QD_SMI_ACCESS_LOOP; /* initialize the loop count */ + + if(smiReg & QD_SMI_BUSY) + { + for(i = 0 ; i < QD_SMI_TIMEOUT ; i++); + do + { + if(timeOut-- < 1 ) + { + DBG_INFO(("Writing Phy register Timed Out\n")); + return GT_FALSE; + } + if(phyReadGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, &smiReg) != GT_OK) + { + DBG_INFO(("Writing Phy register Failed\n")); + return GT_FAIL; + } + } while (smiReg & QD_SMI_BUSY); + } + + if(phyWriteGlobal2Reg(dev,QD_REG_SMI_PHY_DATA, value) != GT_OK) + { + DBG_INFO(("Writing Phy Data register Failed\n")); + return GT_FAIL; + } + smiReg = QD_SMI_BUSY | (phyAddr << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_WRITE << QD_SMI_OP_BIT) | + (regAddr << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT); + + if(phyWriteGlobal2Reg(dev,QD_REG_SMI_PHY_CMD, smiReg) != GT_OK) + { + DBG_INFO(("Writing Phy Command register Failed\n")); + return GT_FAIL; + } + + return GT_OK; +} + + +static GT_STATUS phyReadGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + OUT GT_U16 *data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + retVal = miiSmiIfReadRegister(dev,phyAddr,regAddr,data); + + DBG_INFO(("read from global 2 register: phyAddr 0x%x, regAddr 0x%x, ", + phyAddr,regAddr)); + DBG_INFO(("data 0x%x.\n",*data)); + return retVal; +} + + +static GT_STATUS phyWriteGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U8 regAddr, + IN GT_U16 data +) +{ + GT_U8 phyAddr; + GT_STATUS retVal; + + phyAddr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS); + if (phyAddr == 0xFF) + { + return GT_BAD_PARAM; + } + + retVal = miiSmiIfWriteRegister(dev,phyAddr,regAddr,data); + + return retVal; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/makefile u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/makefile --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/driver/makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/driver/makefile 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,32 @@ +# Source files in this directory +CSOURCES = gtDrvConfig.c gtDrvEvents.c gtHwCntl.c +ASOURCES = + +# Include common variable definitions +ifeq ($(OS_RUN),VXWORKS) +include $(TOOL_DIR)\make.defs +endif +ifeq ($(OS_RUN),WIN32) +include $(TOOL_DIR)\makewce.defs +endif +ifeq ($(OS_RUN),LINUX) +include $(TOOL_DIR)/makelnx.defs +endif + +# Add in extra stuffs +EXTRA_INCLUDE += +EXTRA_DEFINE += +ADDED_CFLAGS += + +# Include common build rules +ifeq ($(OS_RUN),VXWORKS) +include $(TOOL_DIR)\make.rules +endif +ifeq ($(OS_RUN),WIN32) +include $(TOOL_DIR)\makewce.rules +endif +ifeq ($(OS_RUN),LINUX) +include $(TOOL_DIR)/makelnx.rules +endif + +# end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/makefile u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/makefile --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/makefile 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,96 @@ +# makefile - build main object file +# +# modification history +# -------------------- +# 04-15-02,mj created +# +####################################################################### + +TARGET = $(PROJ_NAME) + +ifeq ($(OS_RUN),VXWORKS) +WORK_TO_DO = $(PROJ_NAME).o + +# Include common variable definitions +include $(TOOL_DIR)\make.defs +endif + +ifeq ($(OS_RUN),LINUX) +WORK_TO_DO = $(PROJ_NAME).o + +# Include common variable definitions +include $(TOOL_DIR)/makelnx.defs +endif + +exe : $(WORK_TO_DO) + +.PHONY : exe + +vpath %.o $(OBJDIR) +vpath %.lib $(OBJDIR) + +MAINDRV_PATH = $(SRC_BASE_PATH) + +OBJECTS_LIST = $(MAINDRV_PATH)/driver/$(OBJDIR)/driver.o \ + $(MAINDRV_PATH)/msapi/$(OBJDIR)/msapi.o \ + $(MAINDRV_PATH)/platform/$(OBJDIR)/platform.o + +OBJECTS = $(OBJECTS_LIST) + +OBJDIRS = $(subst /,\,$(dir $(OBJECTS))) +LIBDIRS = $(subst /,\,$(LIB_DIR)) + +OBJDIRS_/ = $(subst \,/,$(OBJDIRS)) +LIBDIRS_/ = $(subst \,/,$(LIBDIRS)) + +ifeq ($(OS_RUN),VXWORKS) +$(PROJ_NAME).o : $(OBJECTS) $(MAD_OBJ) + @ $(ECHO) '------------' + @ $(ECHO) 'Building $@' + $(LD) $(LDFLAGS) -Map $(LIB_DIR)/$(PROJ_NAME).map -o $(LIB_DIR)/$(PROJ_NAME).o $(OBJECTS) $(MAD_OBJ) + +$(OBJECTS) : FORCE + @($(CD) $(subst /,\,$(dir $(@D)))) && $(MAKE) + +$(MAD_OBJ) : FORCE + $(MAKE) -C $(MAD_ROOT)/src + +endif + +ifeq ($(OS_RUN),LINUX) +$(PROJ_NAME).o : $(OBJECTS) $(MAD_OBJ) + @ $(ECHO) '------------' + @ $(ECHO) 'Building $@' + $(LD) $(LDFLAGS) -Map $(LIB_DIR)/$(PROJ_NAME).map -o $(LIB_DIR)/$(PROJ_NAME).o $(OBJECTS) $(MAD_OBJ) + +$(OBJECTS) : FORCE + @cd $(dir $(@D)); $(MAKE) + +$(MAD_OBJ) : FORCE + $(MAKE) -C $(MAD_ROOT)/src + +endif + +FORCE : + +.PHONY : clean +ifeq ($(OS_RUN),VXWORKS) +clean : + @for %x in ($(OBJDIRS)) do \ + @($(CD) %x..) && $(MAKE) clean + - ($(CD) $(LIBDIRS)) && $(RM) $(PROJ_NAME).o + - ($(CD) $(LIBDIRS)) && $(RM) $(PROJ_NAME).map + @if exist $(MAD_ROOT) $(MAKE) -C $(MAD_ROOT)/src clean +endif + +ifeq ($(OS_RUN),LINUX) +clean : + @for i in $(OBJDIRS_/); do \ + cd $$i..; $(MAKE) clean; \ + done + @cd $(LIBDIRS_/); $(RM) $(PROJ_NAME).o + @cd $(LIBDIRS_/); $(RM) $(PROJ_NAME).map + @if exist $(MAD_ROOT) $(MAKE) -C $(MAD_ROOT)/src clean +endif + +#end of file diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtAdvVct.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtAdvVct.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtAdvVct.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtAdvVct.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,1855 @@ +#include +/******************************************************************************* +* gtAdvVct.c +* +* DESCRIPTION: +* API for Marvell Virtual Cable Tester. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 1 $ +*******************************************************************************/ +#include +#include +#include +#include +#include +#include + +#define GT_LOOKUP_TABLE_ENTRY 128 /* 73 */ + +#define GT_ADV_VCT_ACCEPTABLE_SHORT_CABLE 11 + +static GT_U8 tbl_1181[GT_LOOKUP_TABLE_ENTRY] = + { 2, 4, 8, 14, 18, 20, 25, 30, 33, 36, + 39, 42, 46, 48, 51, 54, 57, 59, 62, 64, + 66, 69, 71, 73, 75, 77, 80, 81, 83, 85, + 87, 88, 90, 93, 95, 97, 98,100,101,103, + 104,106,106,107,109,110,111,113,114,115, + 116,118,119,120,121,122,124,125,126,127, + 128,129,130,131,132,133,134,135,136,137, + 138,139,140}; + +static GT_U8 tbl_1111[GT_LOOKUP_TABLE_ENTRY] = + { 0, 2, 4, 5, 6, 9, 13, 17, 20, 23, + 27, 30, 33, 35, 38, 41, 43, 46, 48, 51, + 53, 55, 58, 60, 62, 64, 66, 68, 70, 72, + 73, 75, 77, 79, 80, 82, 84, 85, 87, 88, + 90, 91, 93, 94, 96, 97, 98,100,101,102, + 104,105,106,107,109,110,111,112,113,114, + 116,117,118,119,120,121,122,123,124,125, + 126,127,128,129,130,131,132,133,134,134}; + +static GT_U8 tbl_1112[GT_LOOKUP_TABLE_ENTRY] = /* from 17*/ + { 0, 4, 8, 11, 14, 18, 21, 24, 28, 31, + 34, 37, 39, 42, 44, 47, 49, 52, 54, 56, + 58, 60, 62, 64, 66, 68, 70, 72, 74, 75, + 77, 79, 80, 82, 83, 85, 87, 88, 89, 91, + 92, 94, 95, 96, 98, 99,100,101,103,104, + 105,106,107,108,109,111,112,113,114,115, + 116,117,118,119,120,121,122,123,124,124, + 125,126,127,128,129,130,131,131,132,133, + 134,135,135,136,137,138,139,139,140,141, + 142,142,143,144,144,145,146,147,147,148}; + +static GT_U8 tbl_1116[GT_LOOKUP_TABLE_ENTRY] = /* from 16*/ + { 2, 4, 8, 14, 18, 20, 25, 30, 33, 36, + 39, 42, 46, 48, 51, 54, 57, 59, 62, 64, + 66, 69, 71, 73, 75, 77, 80, 81, 83, 85, + 87, 88, 90, 93, 95, 97, 98, 100, 101, 103, + 104,106,106,107,109,110,111,113,114,115, + 116,118,119,120,121,122,124,125,126,127, + 128,129,130,131,132,133,134,135,136,137, + 138,139,140}; + +static GT_U8 tbl_1240[GT_LOOKUP_TABLE_ENTRY] = + { 1, 2, 5, 10, 13, 15, 18, 22, 26, 30, + 33, 35, 38, 40, 43, 45, 48, 51, 53, 55, + 58, 60, 63, 65, 68, 69, 70, 71, 73, 75, + 77, 79, 80, 81, 82, 83, 85, 87, 88, 90, + 91, 92, 93, 95, 97, 98,100,101,102,103, + 105,106,107,108,109,110,111,112,113,114, + 115,116,117,118,119,120,121,122,123,124, + 125,126,127,128,129,130}; + + +/******************************************************************************* +* getDetailedAdvVCTResult +* +* DESCRIPTION: +* This routine differenciate Open/Short from Impedance mismatch. +* +* INPUTS: +* amp - amplitude +* len - distance to fault +* vctResult - test result +* (Impedance mismatch, either > 115 ohms, or < 85 ohms) +* +* OUTPUTS: +* +* RETURNS: +* GT_ADV_VCT_STATUS +* +* COMMENTS: +* This routine assumes test result is not normal nor cross pair short. +* +*******************************************************************************/ +static +GT_ADV_VCT_STATUS getDetailedAdvVCTResult +( + IN GT_U32 devType, + IN GT_U32 amp, + IN GT_U32 len, + IN GT_ADV_VCT_STATUS result +) +{ + GT_ADV_VCT_STATUS vctResult; + GT_BOOL update = GT_FALSE; + + DBG_INFO(("getDetailedAdvVCTResult Called.\n")); + + if (devType == GT_PHY_ADV_VCT_TYPE2) + { + if(len < 10) + { + if(amp > 54) /* 90 x 0.6 */ + update = GT_TRUE; + } + else if(len < 50) + { + if(amp > 42) /* 70 x 0.6 */ + update = GT_TRUE; + } + else if(len < 110) + { + if(amp > 30) /* 50 x 0.6 */ + update = GT_TRUE; + } + else if(len < 140) + { + if(amp > 24) /* 40 x 0.6 */ + update = GT_TRUE; + } + else + { + if(amp > 18) /* 30 x 0.6 */ + update = GT_TRUE; + } + } + else + { + if(len < 10) + { + if(amp > 90) + update = GT_TRUE; + } + else if(len < 50) + { + if(amp > 70) + update = GT_TRUE; + } + else if(len < 110) + { + if(amp > 50) + update = GT_TRUE; + } + else if(len < 140) + { + if(amp > 40) + update = GT_TRUE; + } + else + { + if(amp > 30) + update = GT_TRUE; + } + } + + + switch (result) + { + case GT_ADV_VCT_IMP_GREATER_THAN_115: + if(update) + vctResult = GT_ADV_VCT_OPEN; + else + vctResult = result; + break; + case GT_ADV_VCT_IMP_LESS_THAN_85: + if(update) + vctResult = GT_ADV_VCT_SHORT; + else + vctResult = result; + break; + default: + vctResult = result; + break; + } + + return vctResult; +} + +/******************************************************************************* +* analizeAdvVCTResult +* +* DESCRIPTION: +* This routine analize the Advanced VCT result. +* +* INPUTS: +* channel - channel number where test was run +* crossChannelReg - register values after the test is completed +* mode - use formula for normal cable case +* +* OUTPUTS: +* cableStatus - analized test result. +* +* RETURNS: +* -1, or distance to fault +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_16 analizeAdvVCTNoCrosspairResult +( + IN GT_U32 devType, + IN int channel, + IN GT_U16 *crossChannelReg, + IN GT_BOOL isShort, + OUT GT_ADV_CABLE_STATUS *cableStatus +) +{ + int len; + GT_16 dist2fault; + GT_ADV_VCT_STATUS vctResult = GT_ADV_VCT_NORMAL; + + DBG_INFO(("analizeAdvVCTNoCrosspairResult Called.\n")); + DBG_INFO(("analizeAdvVCTNoCrosspairResult chan %d reg data %x\n", channel, crossChannelReg[channel])); + + dist2fault = -1; + + /* check if test is failed */ + if(IS_VCT_FAILED(crossChannelReg[channel])) + { + cableStatus->cableStatus[channel] = GT_ADV_VCT_FAIL; + return dist2fault; + } + + /* Check if fault detected */ + if(IS_ZERO_AMPLITUDE(crossChannelReg[channel])) + { + cableStatus->cableStatus[channel] = GT_ADV_VCT_NORMAL; + return dist2fault; + } + + /* find out test result by reading Amplitude */ + if(IS_POSITIVE_AMPLITUDE(crossChannelReg[channel])) + { + vctResult = GT_ADV_VCT_IMP_GREATER_THAN_115; + } + else + { + vctResult = GT_ADV_VCT_IMP_LESS_THAN_85; + } + + /* + * now, calculate the distance for GT_ADV_VCT_IMP_GREATER_THAN_115 and + * GT_ADV_VCT_IMP_LESS_THAN_85 + */ + switch (vctResult) + { + case GT_ADV_VCT_IMP_GREATER_THAN_115: + case GT_ADV_VCT_IMP_LESS_THAN_85: + if(!isShort) + { + len = (int)GT_ADV_VCT_CALC(crossChannelReg[channel] & 0xFF); + } + else + { + len = (int)GT_ADV_VCT_CALC_SHORT(crossChannelReg[channel] & 0xFF); + } + DBG_INFO(("@@@@ no cross len %d\n", len)); + + if (len < 0) + len = 0; + cableStatus->u[channel].dist2fault = (GT_16)len; + vctResult = getDetailedAdvVCTResult( + devType, + GET_AMPLITUDE(crossChannelReg[channel]), + len, + vctResult); + dist2fault = (GT_16)len; + break; + default: + break; + } + + cableStatus->cableStatus[channel] = vctResult; + + return dist2fault; +} + + +static +GT_16 analizeAdvVCTResult +( + IN GT_U32 devType, + IN int channel, + IN GT_U16 *crossChannelReg, + IN GT_BOOL isShort, + OUT GT_ADV_CABLE_STATUS *cableStatus +) +{ + int i, len; + GT_16 dist2fault; + GT_ADV_VCT_STATUS vctResult = GT_ADV_VCT_NORMAL; + + DBG_INFO(("analizeAdvVCTResult(Crosspair) chan %d reg data %x\n", channel, crossChannelReg[channel])); + DBG_INFO(("analizeAdvVCTResult Called.\n")); + + dist2fault = -1; + + /* check if test is failed */ + for (i=0; icableStatus[channel] = GT_ADV_VCT_FAIL; + return dist2fault; + } + } + + /* find out test result by reading Amplitude */ + for (i=0; icableStatus[channel] = GT_ADV_VCT_CROSS_PAIR_SHORT; + for (i=0; iu[channel].crossShort.channel[i] = GT_FALSE; + cableStatus->u[channel].crossShort.dist2fault[i] = 0; + continue; + } + + cableStatus->u[channel].crossShort.channel[i] = GT_TRUE; + if(!isShort) + len = (int)GT_ADV_VCT_CALC(crossChannelReg[i] & 0xFF); + else + len = (int)GT_ADV_VCT_CALC_SHORT(crossChannelReg[i] & 0xFF); + DBG_INFO(("@@@@ len %d\n", len)); + + if (len < 0) + len = 0; + cableStatus->u[channel].crossShort.dist2fault[i] = (GT_16)len; + dist2fault = (GT_16)len; + } + + return dist2fault; + } + + /* + * now, calculate the distance for GT_ADV_VCT_IMP_GREATER_THAN_115 and + * GT_ADV_VCT_IMP_LESS_THAN_85 + */ + switch (vctResult) + { + case GT_ADV_VCT_IMP_GREATER_THAN_115: + case GT_ADV_VCT_IMP_LESS_THAN_85: + if(isShort) + len = (int)GT_ADV_VCT_CALC(crossChannelReg[channel] & 0xFF); + else + len = (int)GT_ADV_VCT_CALC_SHORT(crossChannelReg[channel] & 0xFF); + if (len < 0) + len = 0; + cableStatus->u[channel].dist2fault = (GT_16)len; + vctResult = getDetailedAdvVCTResult( + devType, + GET_AMPLITUDE(crossChannelReg[channel]), + len, + vctResult); + dist2fault = (GT_16)len; + break; + default: + break; + } + + cableStatus->cableStatus[channel] = vctResult; + + return dist2fault; +} + + +/******************************************************************************* +* runAdvCableTest_1181 +* +* DESCRIPTION: +* This routine performs the advanced virtual cable test for the PHY with +* multiple page mode and returns the the status per MDIP/N. +* +* INPUTS: +* port - logical port number. +* mode - GT_TRUE, if short cable detect is required +* GT_FALSE, otherwise +* +* OUTPUTS: +* cableStatus - the port copper cable status. +* tooShort - if known distance to fault is too short +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_STATUS runAdvCableTest_1181 +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_BOOL mode, + OUT GT_ADV_CABLE_STATUS *cableStatus, + OUT GT_BOOL *tooShort +) +{ + GT_STATUS retVal; + GT_U16 u16Data; + GT_U16 crossChannelReg[GT_MDI_PAIR_NUM]; + int i,j; + GT_16 dist2fault; + + VCT_REGISTER regList[GT_MDI_PAIR_NUM][GT_MDI_PAIR_NUM] = { + {{8,16},{8,17},{8,18},{8,19}}, /* channel 0 */ + {{8,24},{8,25},{8,26},{8,27}}, /* channel 1 */ + {{9,16},{9,17},{9,18},{9,19}}, /* channel 2 */ + {{9,24},{9,25},{9,26},{9,27}} /* channel 3 */ + }; + + DBG_INFO(("runAdvCableTest_1181 Called.\n")); + + if (mode) + *tooShort = GT_FALSE; + + /* + * start Advanced Virtual Cable Tester + */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,8,QD_REG_ADV_VCT_CONTROL_8,15,1,phyInfo->anyPage,1)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + /* + * loop until test completion and result is valid + */ + do + { + if((retVal = hwReadPagedPhyReg( + dev,hwPort,8,QD_REG_ADV_VCT_CONTROL_8,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + } while(u16Data & 0x8000); + + DBG_INFO(("Page 8 of Reg20 after test : %0#x.\n", u16Data)); + + for (i=0; ianyPage, + &crossChannelReg[j])) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + } + + /* + * analyze the test result for RX Pair + */ + dist2fault = analizeAdvVCTResult(phyInfo->vctType, i, crossChannelReg, mode, cableStatus); + + if(mode) + { + if ((dist2fault>=0) && (dist2faultanyPage,u16Data)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + if (flag) + { + /* save original Pulse Width */ + if((retVal = hwGetPagedPhyRegField( + dev,hwPort,9,23,10,2,phyInfo->anyPage,&orgPulse)) != GT_OK) + { + DBG_INFO(("Reading paged phy reg failed.\n")); + return retVal; + } + + /* set the Pulse Width with default value */ + if (orgPulse != 0) + { + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,9,23,10,2,phyInfo->anyPage,0)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + } + } + + if((retVal=runAdvCableTest_1181(dev,hwPort,phyInfo,flag,cableStatus,&tooShort)) != GT_OK) + { + DBG_INFO(("Running advanced VCT failed.\n")); + return retVal; + } + + if (flag) + { + if(tooShort) + { + /* set the Pulse Width with minimum width */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,9,23,10,2,phyInfo->anyPage,3)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + /* run the Adv VCT again */ + if((retVal=runAdvCableTest_1181(dev,hwPort,phyInfo,GT_FALSE,cableStatus,&tooShort)) != GT_OK) + { + DBG_INFO(("Running advanced VCT failed.\n")); + return retVal; + } + + } + + /* set the Pulse Width back to the original value */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,9,23,10,2,phyInfo->anyPage,orgPulse)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + } + + return GT_OK; +} + + +static +GT_STATUS runAdvCableTest_1116_set +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_32 channel, + IN GT_ADV_VCT_TRANS_CHAN_SEL crosspair +) +{ + GT_STATUS retVal; + + DBG_INFO(("runAdvCableTest_1116_set Called.\n")); + + /* + * start Advanced Virtual Cable Tester + */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,5,QD_REG_ADV_VCT_CONTROL_5,15,1,phyInfo->anyPage,1)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + return GT_OK; +} + +static +GT_STATUS runAdvCableTest_1116_check +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo +) +{ + GT_STATUS retVal; + GT_U16 u16Data; + + /* + * loop until test completion and result is valid + */ + do { + if((retVal = hwReadPagedPhyReg( + dev,hwPort,5,QD_REG_ADV_VCT_CONTROL_5,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + } while (u16Data & 0x8000); + + return GT_OK; +} + +static +GT_STATUS runAdvCableTest_1116_get +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_ADV_VCT_TRANS_CHAN_SEL crosspair, + IN GT_32 channel, + OUT GT_ADV_CABLE_STATUS *cableStatus, + OUT GT_BOOL *tooShort +) +{ + GT_STATUS retVal; + GT_U16 u16Data; + GT_U16 crossChannelReg[GT_MDI_PAIR_NUM]; + int j; + GT_16 dist2fault; + GT_BOOL mode; + GT_BOOL localTooShort[GT_MDI_PAIR_NUM]; + + VCT_REGISTER regList[GT_MDI_PAIR_NUM] = { {5,16},{5,17},{5,18},{5,19} }; + + mode = GT_TRUE; + + DBG_INFO(("runAdvCableTest_1116_get Called.\n")); + + if ((retVal = hwReadPagedPhyReg( + dev,hwPort,5,QD_REG_ADV_VCT_CONTROL_5,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + + DBG_INFO(("Page 5 of Reg23 after test : %0#x.\n", u16Data)); + + /* + * read the test result for the cross pair against selected MDI Pair + */ + for (j=0; janyPage, + &crossChannelReg[j])) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + DBG_INFO(("@@@@@ reg channel %d is %x \n", j, crossChannelReg[j])); + } + + /* + * analyze the test result for RX Pair + */ + for (j=0; jvctType, j, crossChannelReg, mode&(*tooShort), cableStatus); + else + dist2fault = analizeAdvVCTNoCrosspairResult(phyInfo->vctType, j, crossChannelReg, mode&(*tooShort), cableStatus); + + localTooShort[j]=GT_FALSE; + if((mode)&&(*tooShort==GT_FALSE)) + { + if ((dist2fault>=0) && (dist2faultanyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading paged phy reg failed.\n")); + return retVal; + } + + u16Data |= ((mode.mode<<6) | (mode.transChanSel<<11)); + if (mode.peakDetHyst) u16Data |= (mode.peakDetHyst); + if (mode.sampleAvg) u16Data |= (mode.sampleAvg<<8) ; + + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,5,QD_REG_ADV_VCT_CONTROL_5,0,13,phyInfo->anyPage,u16Data)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + if (flag) + { + /* save original Pulse Width */ + if((retVal = hwGetPagedPhyRegField(dev,hwPort,5,28,10,2,phyInfo->anyPage,&orgPulse)) != GT_OK) + { + DBG_INFO(("Reading paged phy reg failed.\n")); + return retVal; + } + + /* set the Pulse Width with default value */ + if (orgPulse != 0) + { + if((retVal = hwSetPagedPhyRegField(dev,hwPort,5,28,10,2,phyInfo->anyPage,0)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + } + tooShort=GT_FALSE; + } + + if((retVal=runAdvCableTest_1116(dev,hwPort,phyInfo,flag,crosspair, + cableStatus,&tooShort)) != GT_OK) + { + DBG_INFO(("Running advanced VCT failed.\n")); + return retVal; + } + + if (flag) + { + if(tooShort) + { + /* set the Pulse Width with minimum width */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,5,28,10,2,phyInfo->anyPage,3)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + /* run the Adv VCT again */ + if((retVal=runAdvCableTest_1116(dev,hwPort,phyInfo,GT_FALSE,crosspair, + cableStatus,&tooShort)) != GT_OK) + { + DBG_INFO(("Running advanced VCT failed.\n")); + return retVal; + } + + } + + /* set the Pulse Width back to the original value */ + if((retVal = hwSetPagedPhyRegField( + dev,hwPort,5,28,10,2,phyInfo->anyPage,orgPulse)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + } + + return GT_OK; +} + + +/******************************************************************************* +* gvctGetAdvCableStatus +* +* DESCRIPTION: +* This routine perform the advanced virtual cable test for the requested +* port and returns the the status per MDI pair. +* +* INPUTS: +* port - logical port number. +* mode - advance VCT mode (either First Peak or Maximum Peak) +* +* OUTPUTS: +* cableStatus - the port copper cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Internal Gigabit Phys in 88E6165 family and 88E6351 family devices +* are supporting this API. +* +*******************************************************************************/ +GT_STATUS gvctGetAdvCableDiag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ADV_VCT_MODE mode, + OUT GT_ADV_CABLE_STATUS *cableStatus +) +{ + GT_STATUS status; + GT_U8 hwPort; + GT_U16 u16Data, org0; + GT_BOOL ppuEn; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn, autoNeg; + GT_U16 pageReg; + int i; + + DBG_INFO(("gvctGetCableDiag Called.\n")); + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* check if the port supports VCT */ + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_ADV_VCT_CAPABLE)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* Need to disable PPUEn for safe. */ + if(gsysGetPPUEn(dev,&ppuEn) != GT_OK) + { + ppuEn = GT_FALSE; + } + + if(ppuEn != GT_FALSE) + { + if((status= gsysSetPPUEn(dev,GT_FALSE)) != GT_OK) + { + DBG_INFO(("Not able to disable PPUEn.\n")); + gtSemGive(dev,dev->phyRegsSem); + return status; + } + gtDelay(250); + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* + * If Fiber is used, simply return with test fail. + */ + if(phyInfo.flag & GT_PHY_FIBER) + { + if((status= hwReadPagedPhyReg(dev,hwPort,1,17,phyInfo.anyPage,&u16Data)) != GT_OK) + { + return status; + } + + if(u16Data & 0x400) + { + for (i=0; icableStatus[i] = GT_ADV_VCT_FAIL; + } + return GT_OK; + } + } + + /* + * Check the link + */ + if((status= hwReadPagedPhyReg(dev,hwPort,0,17,phyInfo.anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Not able to reset the Phy.\n")); + return status; + } + + autoNeg = GT_FALSE; + org0 = 0; + if (!(u16Data & 0x400)) + { + /* link is down, so disable auto-neg if enabled */ + if((status= hwReadPagedPhyReg(dev,hwPort,0,0,phyInfo.anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Not able to reset the Phy.\n")); + return status; + } + + org0 = u16Data; + + if (u16Data & 0x1000) + { + u16Data = 0x140; + + /* link is down, so disable auto-neg if enabled */ + if((status= hwWritePagedPhyReg(dev,hwPort,0,0,phyInfo.anyPage,u16Data)) != GT_OK) + { + DBG_INFO(("Not able to reset the Phy.\n")); + return status; + } + + if((status= hwPhyReset(dev,hwPort,0xFF)) != GT_OK) + { + DBG_INFO(("Not able to reset the Phy.\n")); + return status; + } + autoNeg = GT_TRUE; + } + } + + switch(phyInfo.vctType) + { + case GT_PHY_ADV_VCT_TYPE1: + status = getAdvCableStatus_1181(dev,hwPort,&phyInfo,mode,cableStatus); + break; + case GT_PHY_ADV_VCT_TYPE2: + status = getAdvCableStatus_1116(dev,hwPort,&phyInfo,mode,cableStatus); + break; + default: + status = GT_FAIL; + break; + } + + if (autoNeg) + { + if((status= hwPhyReset(dev,hwPort,org0)) != GT_OK) + { + DBG_INFO(("Not able to reset the Phy.\n")); + goto cableDiagCleanup; + return status; + } + } + +cableDiagCleanup: + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(ppuEn != GT_FALSE) + { + if(gsysSetPPUEn(dev,ppuEn) != GT_OK) + { + DBG_INFO(("Not able to enable PPUEn.\n")); + status = GT_FAIL; + } + } + + gtSemGive(dev,dev->phyRegsSem); + return status; +} + + +/******************************************************************************* +* dspLookup +* +* DESCRIPTION: +* This routine returns cable length (meters) by reading DSP Lookup table. +* +* INPUTS: +* regValue - register 21 +* +* OUTPUTS: +* cableLen - cable length (unit of meters). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_STATUS dspLookup +( + IN GT_PHY_INFO *phyInfo, + IN GT_U16 regValue, + OUT GT_32 *cableLen +) +{ + GT_U16 startEntry,tableEntry; + GT_U8* tbl; + switch(phyInfo->exStatusType) + { + case GT_PHY_EX_STATUS_TYPE1: /* 88E1111/88E1141/E1145 */ + startEntry = 18-1; + tableEntry = 80; + tbl = tbl_1111; + break; + + case GT_PHY_EX_STATUS_TYPE2: /* 88E1112 */ + startEntry = 17; + tableEntry = 100; + tbl = tbl_1112; + break; + + case GT_PHY_EX_STATUS_TYPE3: /* 88E1149 has no reference constans*/ + startEntry = 16; + tableEntry = 73; + tbl = tbl_1181; + break; + + case GT_PHY_EX_STATUS_TYPE4: /* 88E1181 */ + startEntry = 16; + tableEntry = 73; + tbl = tbl_1181; + break; + + case GT_PHY_EX_STATUS_TYPE5: /* 88E1116 88E1121 */ + startEntry = 16; + tableEntry = 73; + tbl = tbl_1116; + break; + + case GT_PHY_EX_STATUS_TYPE6: /* 88E6165 Internal Phy */ + if ((phyInfo->phyId & PHY_MODEL_MASK) == DEV_G65G) + startEntry = 18; + else + startEntry = 21; + tableEntry = 76; + tbl = tbl_1240; + break; + + default: + return GT_NOT_SUPPORTED; + } + + if (tbl == NULL) + { + *cableLen = -1; + return GT_OK; + } + + if (regValue < startEntry) + { + *cableLen = 0; + return GT_OK; + } + + if (regValue >= (tableEntry+startEntry-1)) + { + regValue = tableEntry-1; + } + else + { + regValue -= startEntry; + } + + *cableLen = (GT_32)tbl[regValue]; + return GT_OK; +} + +/******************************************************************************* +* getDSPDistance_1111 +* +* DESCRIPTION: +* This routine returns cable length (meters) from DSP method. +* This routine is for the 88E1111 like devices. +* +* INPUTS: +* mdi - pair of each MDI (0..3). +* +* OUTPUTS: +* cableLen - cable length (unit of meters). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_STATUS getDSPDistance_1111 +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_U32 mdi, + OUT GT_32 *cableLen +) +{ + GT_U16 data, pageNum; + GT_STATUS retVal; + + DBG_INFO(("getDSPDistance Called.\n")); + + pageNum = 0x8754 + (GT_U16)((mdi << 12)&0xf000); + + if((retVal = hwReadPagedPhyReg(dev,hwPort,(GT_U8)pageNum,31,phyInfo->anyPage,&data)) != GT_OK) + { + DBG_INFO(("Reading length of MDI pair failed.\n")); + return retVal; + } + + return dspLookup(phyInfo,data,cableLen); +} + + +/******************************************************************************* +* getDSPDistance_1181 +* +* DESCRIPTION: +* This routine returns cable length (meters) from DSP method. +* This routine is for the 88E1181 like devices. +* +* INPUTS: +* mdi - pair of each MDI (0..3). +* +* OUTPUTS: +* cableLen - cable length (unit of meters). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_STATUS getDSPDistance_1181 +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_U32 mdi, + OUT GT_32 *cableLen +) +{ + GT_U16 data, retryCount; + GT_STATUS retVal; + + DBG_INFO(("getDSPDistance Called.\n")); + + /* Set the required bits for Cable length register */ + if((retVal = hwWritePagedPhyReg(dev,hwPort,0xff,19,phyInfo->anyPage,(GT_U16)(0x1018+(0xff&mdi)))) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + retryCount = 1000; + + do + { + if(retryCount == 0) + { + DBG_INFO(("Ready bit of Cable length resiter is not set.\n")); + return GT_FAIL; + } + + /* Check the ready bit of Cable length register */ + if((retVal = hwGetPagedPhyRegField(dev,hwPort,0xff,19,15,1,phyInfo->anyPage,&data)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + retryCount--; + + } while(!data); + + /* read length of MDI pair */ + if((retVal = hwReadPagedPhyReg(dev,hwPort,0xff,21,phyInfo->anyPage,&data)) != GT_OK) + { + DBG_INFO(("Reading length of MDI pair failed.\n")); + return retVal; + } + + return dspLookup(phyInfo,data,cableLen); +} + + +/******************************************************************************* +* getDSPDistance_1240 +* +* DESCRIPTION: +* This routine returns cable length (meters) from DSP method. +* This routine is for the 88E1181 like devices. +* +* INPUTS: +* mdi - pair of each MDI (0..3). +* +* OUTPUTS: +* cableLen - cable length (unit of meters). +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static +GT_STATUS getDSPDistance_1240 +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_U32 mdi, + OUT GT_32 *cableLen +) +{ + GT_U16 data, retryCount; + GT_STATUS retVal; + + DBG_INFO(("getDSPDistance Called.\n")); + + /* Set the required bits for Cable length register */ + if((retVal = hwWritePagedPhyReg(dev,hwPort,0xff,16,phyInfo->anyPage,(GT_U16)(0x1118+(0xff&mdi)))) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + retryCount = 1000; + + do + { + if(retryCount == 0) + { + DBG_INFO(("Ready bit of Cable length resiter is not set.\n")); + return GT_FAIL; + } + + /* Check the ready bit of Cable length register */ + if((retVal = hwGetPagedPhyRegField(dev,hwPort,0xff,16,15,1,phyInfo->anyPage,&data)) != GT_OK) + { + DBG_INFO(("Writing to paged phy reg failed.\n")); + return retVal; + } + + retryCount--; + + } while(!data); + + /* read length of MDI pair */ + if((retVal = hwReadPagedPhyReg(dev,hwPort,0xff,18,phyInfo->anyPage,&data)) != GT_OK) + { + DBG_INFO(("Reading length of MDI pair failed.\n")); + return retVal; + } + + return dspLookup(phyInfo,data,cableLen); +} + + + +/******************************************************************************* +* getExStatus_28 +* +* DESCRIPTION: +* This routine retrieves Pair Skew, Pair Swap, and Pair Polarity +* for 1000M phy with multiple page mode +* +* INPUTS: +* dev - device context. +* port - logical port number. +* +* OUTPUTS: +* extendedStatus - extended cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static GT_STATUS getExStatus_28 +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + OUT GT_ADV_EXTENDED_STATUS *extendedStatus +) +{ + GT_STATUS retVal; + GT_U16 u16Data, i; + + extendedStatus->isValid = GT_FALSE; + /* DSP based cable length */ + for (i=0; icableLen[i])) != GT_OK) + { + DBG_INFO(("getDSPDistance failed.\n")); + return retVal; + } + } + + + /* + * get data from 28_5 register for pair swap + */ + if((retVal = hwReadPagedPhyReg( + dev,hwPort,5,28,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + + /* if bit 6 is not set, it's not valid. */ + if (!(u16Data & 0x40)) + { + DBG_INFO(("Valid Bit is not set (%0#x).\n", u16Data)); + return GT_OK; + } + + extendedStatus->isValid = GT_TRUE; + + /* get Pair Polarity */ + for(i=0; i> i) & 0x1) + { + case 0: + extendedStatus->pairPolarity[i] = GT_POSITIVE; + break; + default: + extendedStatus->pairPolarity[i] = GT_NEGATIVE; + break; + } + } + + /* get Pair Swap for Channel A and B */ + if (u16Data & 0x10) + { + extendedStatus->pairSwap[0] = GT_CHANNEL_A; + extendedStatus->pairSwap[1] = GT_CHANNEL_B; + } + else + { + extendedStatus->pairSwap[0] = GT_CHANNEL_B; + extendedStatus->pairSwap[1] = GT_CHANNEL_A; + } + + /* get Pair Swap for Channel C and D */ + if (u16Data & 0x20) + { + extendedStatus->pairSwap[2] = GT_CHANNEL_C; + extendedStatus->pairSwap[3] = GT_CHANNEL_D; + } + else + { + extendedStatus->pairSwap[2] = GT_CHANNEL_D; + extendedStatus->pairSwap[3] = GT_CHANNEL_C; + } + + /* + * get data from 28_4 register for pair skew + */ + if((retVal = hwReadPagedPhyReg( + dev,hwPort,4,28,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + + /* get Pair Skew */ + for(i=0; ipairSkew[i] = ((u16Data >> i*4) & 0xF) * 8; + } + + return GT_OK; +} + + +/******************************************************************************* +* getExStatus +* +* DESCRIPTION: +* This routine retrieves Pair Skew, Pair Swap, and Pair Polarity +* for 1000M phy with multiple page mode +* +* INPUTS: +* dev - device context. +* port - logical port number. +* +* OUTPUTS: +* extendedStatus - extended cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static GT_STATUS getExStatus +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + OUT GT_ADV_EXTENDED_STATUS *extendedStatus +) +{ + GT_STATUS retVal; + GT_U16 u16Data, i; + + extendedStatus->isValid = GT_FALSE; + /* DSP based cable length */ + switch(phyInfo->exStatusType) + { + case GT_PHY_EX_STATUS_TYPE1: + case GT_PHY_EX_STATUS_TYPE2: + for (i=0; icableLen[i])) != GT_OK) + { + DBG_INFO(("getDSPDistance failed.\n")); + return retVal; + } + } + break; + case GT_PHY_EX_STATUS_TYPE3: + case GT_PHY_EX_STATUS_TYPE4: + case GT_PHY_EX_STATUS_TYPE5: + for (i=0; icableLen[i])) != GT_OK) + { + DBG_INFO(("getDSPDistance failed.\n")); + return retVal; + } + } + break; + + case GT_PHY_EX_STATUS_TYPE6: + for (i=0; icableLen[i])) != GT_OK) + { + DBG_INFO(("getDSPDistance failed.\n")); + return retVal; + } + } + break; + + default: + return GT_NOT_SUPPORTED; + } + + /* + * get data from 21_5 register for pair swap + */ + if((retVal = hwReadPagedPhyReg( + dev,hwPort,5,QD_REG_PAIR_SWAP_STATUS,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + + /* if bit 6 is not set, it's not valid. */ + if (!(u16Data & 0x40)) + { + DBG_INFO(("Valid Bit is not set (%0#x).\n", u16Data)); + return GT_OK; + } + + extendedStatus->isValid = GT_TRUE; + + /* get Pair Polarity */ + for(i=0; i> i) & 0x1) + { + case 0: + extendedStatus->pairPolarity[i] = GT_POSITIVE; + break; + default: + extendedStatus->pairPolarity[i] = GT_NEGATIVE; + break; + } + } + + /* get Pair Swap for Channel A and B */ + if (u16Data & 0x10) + { + extendedStatus->pairSwap[0] = GT_CHANNEL_A; + extendedStatus->pairSwap[1] = GT_CHANNEL_B; + } + else + { + extendedStatus->pairSwap[0] = GT_CHANNEL_B; + extendedStatus->pairSwap[1] = GT_CHANNEL_A; + } + + /* get Pair Swap for Channel C and D */ + if (u16Data & 0x20) + { + extendedStatus->pairSwap[2] = GT_CHANNEL_C; + extendedStatus->pairSwap[3] = GT_CHANNEL_D; + } + else + { + extendedStatus->pairSwap[2] = GT_CHANNEL_D; + extendedStatus->pairSwap[3] = GT_CHANNEL_C; + } + + /* + * get data from 20_5 register for pair skew + */ + if((retVal = hwReadPagedPhyReg( + dev,hwPort,5,QD_REG_PAIR_SKEW_STATUS,phyInfo->anyPage,&u16Data)) != GT_OK) + { + DBG_INFO(("Reading from paged phy reg failed.\n")); + return retVal; + } + + /* get Pair Skew */ + for(i=0; ipairSkew[i] = ((u16Data >> i*4) & 0xF) * 8; + } + + + return GT_OK; +} + + +/******************************************************************************* +* gvctGetAdvExtendedStatus +* +* DESCRIPTION: +* This routine retrieves extended cable status, such as Pair Poloarity, +* Pair Swap, and Pair Skew. Note that this routine will be success only +* if 1000Base-T Link is up. +* Note: Since DSP based cable length in extended status is based on +* constants from test results. At present, only E1181, E1111, and +* E1112 are available. +* +* INPUTS: +* dev - pointer to GT driver structure returned from mdLoadDriver +* port - logical port number. +* +* OUTPUTS: +* extendedStatus - the extended cable status. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Supporting Device list: +* 88E1111, 88E1112, 88E1141~6, 88E1149, and Internal Gigabit Phys +* in 88E6165 family and 88E6351 family devices +* +*******************************************************************************/ +GT_STATUS gvctGetAdvExtendedStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ADV_EXTENDED_STATUS *extendedStatus +) +{ + GT_STATUS retVal; + GT_U8 hwPort; + GT_BOOL ppuEn; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gvctGetAdvExtendedStatus Called.\n")); + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* check if the port supports VCT */ + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_EX_CABLE_STATUS)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* Need to disable PPUEn for safe. */ + if(gsysGetPPUEn(dev,&ppuEn) != GT_OK) + { + ppuEn = GT_FALSE; + } + + if(ppuEn != GT_FALSE) + { + if((retVal = gsysSetPPUEn(dev,GT_FALSE)) != GT_OK) + { + DBG_INFO(("Not able to disable PPUEn.\n")); + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + gtDelay(250); + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + switch(phyInfo.exStatusType) + { + case GT_PHY_EX_STATUS_TYPE1: + if((retVal = getExStatus_28(dev,hwPort,&phyInfo,extendedStatus)) != GT_OK) + { + DBG_INFO(("Getting Extanded Cable Status failed.\n")); + break; + } + break; + + case GT_PHY_EX_STATUS_TYPE2: + case GT_PHY_EX_STATUS_TYPE3: + case GT_PHY_EX_STATUS_TYPE4: + case GT_PHY_EX_STATUS_TYPE5: + case GT_PHY_EX_STATUS_TYPE6: + if((retVal = getExStatus(dev,hwPort,&phyInfo,extendedStatus)) != GT_OK) + { + DBG_INFO(("Getting Extanded Cable Status failed.\n")); + break; + } + + break; + default: + retVal = GT_NOT_SUPPORTED; + } + + return retVal; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgFdb.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgFdb.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgFdb.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgFdb.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,3093 @@ +#include + +/******************************************************************************** +* gtBrgFdb.c +* +* DESCRIPTION: +* API definitions for Multiple Forwarding Databases +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 9 $ +*******************************************************************************/ + +#include +#include +#include +#include + + +/****************************************************************************/ +/* Forward function declaration. */ +/****************************************************************************/ +static GT_STATUS atuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_ATU_OPERATION atuOp, + INOUT GT_EXTRA_OP_DATA *opData, + INOUT GT_ATU_ENTRY *atuEntry +); + +static GT_STATUS atuStateAppToDev +( + IN GT_QD_DEV *dev, + IN GT_BOOL unicast, + IN GT_U32 state, + OUT GT_U32 *newOne +); + +static GT_STATUS atuStateDevToApp +( + IN GT_QD_DEV *dev, + IN GT_BOOL unicast, + IN GT_U32 state, + OUT GT_U32 *newOne +); + +static GT_STATUS atuGetStats +( + IN GT_QD_DEV *dev, + IN GT_ATU_STAT *atuStat, + OUT GT_U32 *count +); + + +/******************************************************************************* +* gfdbSetPortAtuLearnLimit +* +* DESCRIPTION: +* Port's auto learning limit. When the limit is non-zero value, the number +* of MAC addresses that can be learned on this port are limited to the value +* specified in this API. When the learn limit has been reached any frame +* that ingresses this port with a source MAC address not already in the +* address database that is associated with this port will be discarded. +* Normal auto-learning will resume on the port as soon as the number of +* active unicast MAC addresses associated to this port is less than the +* learn limit. +* CPU directed ATU Load, Purge, or Move will not have any effect on the +* learn limit. +* This feature is disabled when the limit is zero. +* The following care is needed when enabling this feature: +* 1) dsable learning on the ports +* 2) flush all non-static addresses in the ATU +* 3) define the desired limit for the ports +* 4) re-enable learing on the ports +* +* INPUTS: +* port - logical port number +* limit - auto learning limit ( 0 ~ 255 ) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetPortAtuLearnLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 limit +) +{ + GT_U16 data, mask; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gfdbSetPortAtuLearnLimit Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Check device if it has fixed ATU Size. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT)) + { + return GT_NOT_SUPPORTED; + } + + if (limit > 0xFF) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + mask = 0x80FF; + + if (IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT_READ)) + mask |= 0x1000; + + data = (GT_U16) limit; + + /* Set the learn limit bits. */ + retVal = hwSetPortRegBits(dev,hwPort, QD_REG_PORT_ATU_CONTROL, mask, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbGetPortAtuLearnLimit +* +* DESCRIPTION: +* Port's auto learning limit. When the limit is non-zero value, the number +* of MAC addresses that can be learned on this port are limited to the value +* specified in this API. When the learn limit has been reached any frame +* that ingresses this port with a source MAC address not already in the +* address database that is associated with this port will be discarded. +* Normal auto-learning will resume on the port as soon as the number of +* active unicast MAC addresses associated to this port is less than the +* learn limit. +* CPU directed ATU Load, Purge, or Move will not have any effect on the +* learn limit. +* This feature is disabled when the limit is zero. +* The following care is needed when enabling this feature: +* 1) dsable learning on the ports +* 2) flush all non-static addresses in the ATU +* 3) define the desired limit for the ports +* 4) re-enable learing on the ports +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* limit - auto learning limit ( 0 ~ 255 ) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gfdbGetPortAtuLearnLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *limit +) +{ + GT_U16 data, mask; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gfdbGetPortAtuLearnLimit Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Check device if it has fixed ATU Size. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT_READ)) + { + return GT_NOT_SUPPORTED; + } + + mask = 0x9000; + data = (GT_U16) 0x1000; + + /* Set the learn limit bits. */ + retVal = hwSetPortRegBits(dev,hwPort, QD_REG_PORT_ATU_CONTROL, mask, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + /* Get the ReadLearnLimit bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 0, 8, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *limit = (GT_U32)data; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gfdbGetPortAtuLearnCnt +* +* DESCRIPTION: +* Read the current number of active unicast MAC addresses associated with +* the given port. This counter (LearnCnt) is held at zero if learn limit +* (gfdbSetPortAtuLearnLimit API) is set to zero. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* count - current auto learning count +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetPortAtuLearnCnt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 *count +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gfdbGetPortAtuLearnCnt Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Check device if this feature is supported. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT)) + { + return GT_NOT_SUPPORTED; + } + + /* Get the ReadLearnCnt bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 15, 1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if(data == 0) + { + /* Set the ReadLearnCnt bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 15, 1, 1); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + + /* Get the LearnCnt bits. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 0, 8, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *count = (GT_U32)data; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbGetAtuAllCount +* +* DESCRIPTION: +* Counts all entries in the Address Translation Unit. +* +* INPUTS: +* None. +* +* OUTPUTS: +* count - number of valid entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuAllCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *count +) +{ + GT_U32 dbNum, maxDbNum, numOfEntries; + GT_STATUS retVal; + GT_ATU_ENTRY entry; + GT_ATU_STAT atuStat; + + DBG_INFO(("gfdbGetAtuAllCount Called.\n")); + + if(IS_IN_DEV_GROUP(dev,DEV_ATU_STATS)) + { + atuStat.op = GT_ATU_STATS_ALL; + return atuGetStats(dev,&atuStat,count); + } + + numOfEntries = 0; + + if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_FULL)) + maxDbNum = 16; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + maxDbNum = 64; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + maxDbNum = 256; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_4096)) + maxDbNum = 4096; + else + maxDbNum = 1; + + for(dbNum=0; dbNum. Please refer to the description of +* . +* +* INPUTS: +* None. +* +* OUTPUTS: +* timeout - aging time in seconds. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetAgingTimeout +( + IN GT_QD_DEV *dev, + OUT GT_U32 *timeout +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U16 timeBase; + + DBG_INFO(("gfdbGetAgingTimeout Called.\n")); + + if (IS_IN_DEV_GROUP(dev,DEV_ATU_15SEC_AGING)) + timeBase = 15; + else + timeBase = 16; + + /* Get the Time Out value. */ + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_CONTROL,4,8,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *timeout = data*timeBase; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbSetAgingTimeout +* +* DESCRIPTION: +* Sets the timeout period in seconds for aging out dynamically learned +* forwarding information. The standard recommends 300 sec. +* Supported aging timeout values are multiple of time-base, where time-base +* is either 15 or 16 seconds, depending on the Switch device. For example, +* 88E6063 uses time-base 16, and so supported aging timeouts are 0,16,32, +* 48,..., and 4080. If unsupported timeout value (bigger than 16) is used, +* the value will be rounded to the nearest supported value smaller than the +* given timeout. If the given timeout is less than 16, minimum timeout value +* 16 will be used instead. E.g.) 35 becomes 32 and 5 becomes 16. +* function can be used to find the time-base. +* +* INPUTS: +* timeout - aging time in seconds. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetAgingTimeout +( + IN GT_QD_DEV *dev, + IN GT_U32 timeout +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U16 timeBase; + + DBG_INFO(("gfdbSetAgingTimeout Called.\n")); + + if (IS_IN_DEV_GROUP(dev,DEV_ATU_15SEC_AGING)) + timeBase = 15; + else + timeBase = 16; + + if((timeout < timeBase) && (timeout != 0)) + { + data = 1; + } + else + { + data = (GT_U16)(timeout/timeBase); + if (data & 0xFF00) + data = 0xFF; + } + + /* Set the Time Out value. */ + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_CONTROL,4,8,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbGetLearn2All +* +* DESCRIPTION: +* When more than one Marvell device is used to form a single 'switch', it +* may be desirable for all devices in the 'switch' to learn any address this +* device learns. When this bit is set to a one all other devices in the +* 'switch' learn the same addresses this device learns. When this bit is +* cleared to a zero, only the devices that actually receive frames will learn +* from those frames. This mode typically supports more active MAC addresses +* at one time as each device in the switch does not need to learn addresses +* it may nerver use. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE if Learn2All is enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* +*******************************************************************************/ +GT_STATUS gfdbGetLearn2All +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetLearn2All Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the Learn2All. */ + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_CONTROL, 3, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gfdbSetLearn2All +* +* DESCRIPTION: +* Enable or disable Learn2All mode. +* +* INPUTS: +* mode - GT_TRUE to set Learn2All, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbSetLearn2All +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gprtSetLearn2All Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Learn2All. */ + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_CONTROL, 3, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gfdbGetMacAvb +* +* DESCRIPTION: +* ATU MAC entry in AVB mode. +* When enabled, ATU entries operate in AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_AVB_ENTRY, and +* GT_UC_STATIC_AVB_ENTRY +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_AVB_ENTRY, and +* GT_MC_PRIO_STATIC_AVB_ENTRY +* +* When disabled, ATU entries operate in non-AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_NRL, and +* GT_UC_STATIC_NRL +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_UNLIMITED_RATE, and +* GT_MC_PRIO_STATIC_UNLIMITED_RATE +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - GT_TRUE if MacAvb is enabled, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* +*******************************************************************************/ +GT_STATUS gfdbGetMacAvb +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gfdbGetMacAvb Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_MAC_AVB)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the bit. */ + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_CONTROL, 15, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gfdbSetMacAvb +* +* DESCRIPTION: +* ATU MAC entry in AVB mode. +* When enabled, ATU entries operate in AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_AVB_ENTRY, and +* GT_UC_STATIC_AVB_ENTRY +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_AVB_ENTRY, and +* GT_MC_PRIO_STATIC_AVB_ENTRY +* +* When disabled, ATU entries operate in non-AVB mode: +* +* GT_ATU_UC_STATE - support +* GT_UC_NO_PRI_STATIC_NRL, and +* GT_UC_STATIC_NRL +* +* GT_ATU_MC_STATE - support +* GT_MC_STATIC_UNLIMITED_RATE, and +* GT_MC_PRIO_STATIC_UNLIMITED_RATE +* +* INPUTS: +* mode - GT_TRUE to enable MacAvb, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gfdbSetMacAvb +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gprtSetMacAvb Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_MAC_AVB)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the bit */ + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_CONTROL, 15, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gfdbGetAtuDynamicCount +* +* DESCRIPTION: +* Gets the current number of dynamic unicast (non-static) entries in this +* Filtering Database. +* +* INPUTS: +* None. +* +* OUTPUTS: +* numDynEntries - number of dynamic entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - vlan does not exist. +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuDynamicCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numDynEntries +) +{ + GT_U32 dbNum, maxDbNum, numOfEntries, tmpState; + GT_STATUS retVal; + GT_ATU_ENTRY entry; + GT_ATU_UC_STATE state; + GT_ATU_STAT atuStat; + + DBG_INFO(("gfdbGetAtuDynamicCount Called.\n")); + + if(IS_IN_DEV_GROUP(dev,DEV_ATU_STATS)) + { + atuStat.op = GT_ATU_STATS_NON_STATIC; + return atuGetStats(dev,&atuStat,numDynEntries); + } + + numOfEntries = 0; + + if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_FULL)) + maxDbNum = 16; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + maxDbNum = 64; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + maxDbNum = 256; + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_4096)) + maxDbNum = 4096; + else + maxDbNum = 1; + + for(dbNum=0; dbNumDBNum; + + DBG_INFO(("DBNum : %i\n",entry.DBNum)); + + retVal = atuOperationPerform(dev,GET_NEXT_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (atuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + if(IS_BROADCAST_MAC(entry.macAddr)) + { + if(IS_IN_DEV_GROUP(dev,DEV_BROADCAST_INVALID)) + { + DBG_INFO(("Failed (Invalid Mac).\n")); + return GT_NO_SUCH; + } + else if(entry.entryState.ucEntryState == 0) + { + DBG_INFO(("Failed (Invalid Mac).\n")); + return GT_NO_SUCH; + } + } + + gtMemCpy(atuEntry->macAddr.arEther,entry.macAddr.arEther,6); + atuEntry->portVec = GT_PORTVEC_2_LPORTVEC(entry.portVec); + atuEntry->prio = entry.prio; + atuEntry->trunkMember = entry.trunkMember; + atuEntry->exPrio.useMacFPri = entry.exPrio.useMacFPri; + atuEntry->exPrio.macFPri = entry.exPrio.macFPri; + atuEntry->exPrio.macQPri = entry.exPrio.macQPri; + + if(IS_MULTICAST_MAC(entry.macAddr)) + { + if(dev->deviceId == GT_88E6051) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + atuStateDevToApp(dev,GT_FALSE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.mcEntryState); + } + else + { + atuStateDevToApp(dev,GT_TRUE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.ucEntryState); + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gfdbGetAtuEntryNext +* +* DESCRIPTION: +* Gets next lexicographic MAC address from the specified Mac Addr. +* +* INPUTS: +* atuEntry - the Mac Address to start the search. +* +* OUTPUTS: +* atuEntry - match Address translate unit entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* Search starts from atu.macAddr[xx:xx:xx:xx:xx:xx] specified by the +* user. +* +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbGetAtuEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_ATU_ENTRY *atuEntry +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + + DBG_INFO(("gfdbGetAtuEntryNext Called.\n")); + + if(IS_BROADCAST_MAC(atuEntry->macAddr)) + { + return GT_NO_SUCH; + } + + gtMemCpy(entry.macAddr.arEther,atuEntry->macAddr.arEther,6); + + entry.DBNum = atuEntry->DBNum; + DBG_INFO(("DBNum : %i\n",entry.DBNum)); + + retVal = atuOperationPerform(dev,GET_NEXT_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (atuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + if(IS_BROADCAST_MAC(entry.macAddr)) + { + if(IS_IN_DEV_GROUP(dev,DEV_BROADCAST_INVALID)) + { + DBG_INFO(("Failed (Invalid Mac).\n")); + return GT_NO_SUCH; + } + else if(entry.entryState.ucEntryState == 0) + { + DBG_INFO(("Failed (Invalid Mac).\n")); + return GT_NO_SUCH; + } + } + + gtMemCpy(atuEntry->macAddr.arEther,entry.macAddr.arEther,6); + atuEntry->portVec = GT_PORTVEC_2_LPORTVEC(entry.portVec); + atuEntry->prio = entry.prio; + atuEntry->trunkMember = entry.trunkMember; + atuEntry->exPrio.useMacFPri = entry.exPrio.useMacFPri; + atuEntry->exPrio.macFPri = entry.exPrio.macFPri; + atuEntry->exPrio.macQPri = entry.exPrio.macQPri; + + if(IS_MULTICAST_MAC(entry.macAddr)) + { + if(dev->deviceId == GT_88E6051) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + atuStateDevToApp(dev,GT_FALSE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.mcEntryState); + } + else + { + atuStateDevToApp(dev,GT_TRUE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.ucEntryState); + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gfdbFindAtuMacEntry +* +* DESCRIPTION: +* Find FDB entry for specific MAC address from the ATU. +* +* INPUTS: +* atuEntry - the Mac address to search. +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* atuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* GT_BAD_PARAM - on bad parameter +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbFindAtuMacEntry +( + IN GT_QD_DEV *dev, + INOUT GT_ATU_ENTRY *atuEntry, + OUT GT_BOOL *found +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + int i; + + DBG_INFO(("gfdbFindAtuMacEntry Called.\n")); + *found = GT_FALSE; + gtMemCpy(entry.macAddr.arEther,atuEntry->macAddr.arEther,6); + entry.DBNum = atuEntry->DBNum; + + /* Decrement 1 from mac address. */ + for(i=5; i >= 0; i--) + { + if(entry.macAddr.arEther[i] != 0) + { + entry.macAddr.arEther[i] -= 1; + break; + } + else + entry.macAddr.arEther[i] = 0xFF; + } + + /* Check if the given mac equals zero */ + if((i == -1) && IS_IN_DEV_GROUP(dev,DEV_BROADCAST_INVALID)) + { + DBG_INFO(("Address should not be all zeros.\n")); + return GT_BAD_PARAM; + } + + retVal = atuOperationPerform(dev,GET_NEXT_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if(IS_BROADCAST_MAC(entry.macAddr)) + { + if(IS_IN_DEV_GROUP(dev,DEV_BROADCAST_INVALID)) + { + DBG_INFO(("Failed (Broadcast addr is not valid).\n")); + return GT_NO_SUCH; + } + else if(entry.entryState.ucEntryState == 0) + { + DBG_INFO(("Failed (Invalid Mac).\n")); + return GT_NO_SUCH; + } + } + + if(gtMemCmp((char*)atuEntry->macAddr.arEther,(char*)entry.macAddr.arEther,ETHERNET_HEADER_SIZE)) + { + DBG_INFO(("Failed.\n")); + return GT_NO_SUCH; + } + + atuEntry->portVec = GT_PORTVEC_2_LPORTVEC(entry.portVec); + atuEntry->prio = entry.prio; + atuEntry->trunkMember = entry.trunkMember; + atuEntry->exPrio.useMacFPri = entry.exPrio.useMacFPri; + atuEntry->exPrio.macFPri = entry.exPrio.macFPri; + atuEntry->exPrio.macQPri = entry.exPrio.macQPri; + + if(IS_MULTICAST_MAC(entry.macAddr)) + { + if(dev->deviceId == GT_88E6051) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + atuStateDevToApp(dev,GT_FALSE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.mcEntryState); + } + else + { + atuStateDevToApp(dev,GT_TRUE,(GT_U32)entry.entryState.ucEntryState, + (GT_U32*)&atuEntry->entryState.ucEntryState); + } + + *found = GT_TRUE; + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gfdbFlush +* +* DESCRIPTION: +* This routine flush all or unblocked addresses from the MAC Address +* Table. +* +* INPUTS: +* flushCmd - the flush operation type. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbFlush +( + IN GT_QD_DEV *dev, + IN GT_FLUSH_CMD flushCmd +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + + DBG_INFO(("gfdbFlush Called.\n")); + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_STATIC_ADDR)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.DBNum = 0; + entry.entryState.ucEntryState = 0; + + if(flushCmd == GT_FLUSH_ALL) + retVal = atuOperationPerform(dev,FLUSH_ALL,NULL,&entry); + else + retVal = atuOperationPerform(dev,FLUSH_UNLOCKED,NULL,&entry); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbFlushInDB +* +* DESCRIPTION: +* This routine flush all or unblocked addresses from the particular +* ATU Database (DBNum). If multiple address databases are being used, this +* API can be used to flush entries in a particular DBNum database. +* +* INPUTS: +* flushCmd - the flush operation type. +* DBNum - ATU MAC Address Database Number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbFlushInDB +( + IN GT_QD_DEV *dev, + IN GT_FLUSH_CMD flushCmd, + IN GT_U32 DBNum +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + + DBG_INFO(("gfdbFlush Called.\n")); + DBG_INFO(("gfdbFush: dev=%x, dev->atuRegsSem=%d \n",dev, dev->atuRegsSem)); + + /* check if device supports this feature */ + if ((!IS_IN_DEV_GROUP(dev,DEV_DBNUM_FULL)) && + (!IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) && + (!IS_IN_DEV_GROUP(dev,DEV_DBNUM_4096)) && + (!IS_IN_DEV_GROUP(dev,DEV_DBNUM_256))) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.DBNum = (GT_U16)DBNum; + entry.entryState.ucEntryState = 0; + + if(flushCmd == GT_FLUSH_ALL) + retVal = atuOperationPerform(dev,FLUSH_ALL_IN_DB,NULL,&entry); + else + retVal = atuOperationPerform(dev,FLUSH_UNLOCKED_IN_DB,NULL,&entry); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbMove +* +* DESCRIPTION: +* This routine moves all or unblocked addresses from a port to another. +* +* INPUTS: +* moveCmd - the move operation type. +* moveFrom - port where moving from +* moveTo - port where moving to +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbMove +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_LPORT moveFrom, + IN GT_LPORT moveTo +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + GT_EXTRA_OP_DATA opData; + + DBG_INFO(("gfdbMove Called.\n")); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1W)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.DBNum = 0; + entry.entryState.ucEntryState = 0xF; + if (moveTo == 0xF) + opData.moveTo = moveTo; + else + opData.moveTo = (GT_U32)GT_LPORT_2_PORT(moveTo); + opData.moveFrom = (GT_U32)GT_LPORT_2_PORT(moveFrom); + + if((opData.moveTo == 0xFF) || (opData.moveFrom == 0xFF)) + return GT_BAD_PARAM; + + if(moveCmd == GT_MOVE_ALL) + retVal = atuOperationPerform(dev,FLUSH_ALL,&opData,&entry); + else + retVal = atuOperationPerform(dev,FLUSH_UNLOCKED,&opData,&entry); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbMoveInDB +* +* DESCRIPTION: +* This routine move all or unblocked addresses which are in the particular +* ATU Database (DBNum) from a port to another. +* +* INPUTS: +* moveCmd - the move operation type. +* DBNum - ATU MAC Address Database Number. +* moveFrom - port where moving from +* moveTo - port where moving to +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbMoveInDB +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_U32 DBNum, + IN GT_LPORT moveFrom, + IN GT_LPORT moveTo +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + GT_EXTRA_OP_DATA opData; + + DBG_INFO(("gfdbMoveInDB Called.\n")); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1W)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.DBNum = (GT_U16)DBNum; + entry.entryState.ucEntryState = 0xF; + + if (moveTo == 0xF) + opData.moveTo = moveTo; + else + opData.moveTo = (GT_U32)GT_LPORT_2_PORT(moveTo); + opData.moveFrom = (GT_U32)GT_LPORT_2_PORT(moveFrom); + + if((opData.moveTo == 0xFF) || (opData.moveFrom == 0xFF)) + return GT_BAD_PARAM; + + if(moveCmd == GT_MOVE_ALL) + retVal = atuOperationPerform(dev,FLUSH_ALL_IN_DB,&opData,&entry); + else + retVal = atuOperationPerform(dev,FLUSH_UNLOCKED_IN_DB,&opData,&entry); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbRemovePort +* +* DESCRIPTION: +* This routine deassociages all or unblocked addresses from a port. +* +* INPUTS: +* moveCmd - the move operation type. +* port - the logical port number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbRemovePort +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_LPORT port +) +{ + DBG_INFO(("gfdbRemovePort Called.\n")); + + /* Only 88E6093 Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_RM_PORTS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + return gfdbMove(dev,moveCmd,port,(GT_LPORT)0xF); +} + + +/******************************************************************************* +* gfdbRemovePortInDB +* +* DESCRIPTION: +* This routine deassociages all or unblocked addresses from a port in the +* particular ATU Database (DBNum). +* +* INPUTS: +* moveCmd - the move operation type. +* port - the logical port number. +* DBNum - ATU MAC Address Database Number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED- if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbRemovePortInDB +( + IN GT_QD_DEV *dev, + IN GT_MOVE_CMD moveCmd, + IN GT_LPORT port, + IN GT_U32 DBNum +) +{ + DBG_INFO(("gfdbRemovePortInDB Called.\n")); + + /* Only 88E6093 Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_RM_PORTS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + return gfdbMoveInDB(dev,moveCmd,DBNum,port,(GT_LPORT)0xF); +} + + +/******************************************************************************* +* gfdbAddMacEntry +* +* DESCRIPTION: +* Creates the new entry in MAC address table. +* +* INPUTS: +* macEntry - mac address entry to insert to the ATU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on invalid port vector +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbAddMacEntry +( + IN GT_QD_DEV *dev, + IN GT_ATU_ENTRY *macEntry +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + + DBG_INFO(("gfdbAddMacEntry Called.\n")); + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_STATIC_ADDR)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + gtMemCpy(entry.macAddr.arEther,macEntry->macAddr.arEther,6); + entry.DBNum = macEntry->DBNum; + entry.portVec = GT_LPORTVEC_2_PORTVEC(macEntry->portVec); + if(entry.portVec == GT_INVALID_PORT_VEC) + { + return GT_BAD_PARAM; + } + + if(IS_IN_DEV_GROUP(dev,DEV_ATU_EXT_PRI)) + { + if(IS_IN_DEV_GROUP(dev,DEV_FQPRI_IN_TABLE)) + { + entry.exPrio.useMacFPri = macEntry->exPrio.useMacFPri; + entry.exPrio.macFPri = macEntry->exPrio.macFPri; + entry.exPrio.macQPri = macEntry->exPrio.macQPri; + } + else + { + entry.exPrio.useMacFPri = 0; + entry.exPrio.macFPri = 0; + entry.exPrio.macQPri = macEntry->exPrio.macQPri; + } + entry.prio = 0; + } + else + { + entry.exPrio.useMacFPri = 0; + entry.exPrio.macFPri = 0; + entry.exPrio.macQPri = 0; + entry.prio = macEntry->prio; + } + + if (IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + entry.trunkMember = macEntry->trunkMember; + } + else + { + entry.trunkMember = GT_FALSE; + } + + if(IS_MULTICAST_MAC(entry.macAddr)) + { + atuStateAppToDev(dev,GT_FALSE,(GT_U32)macEntry->entryState.mcEntryState, + (GT_U32*)&entry.entryState.ucEntryState); + } + else + { + atuStateAppToDev(dev,GT_TRUE,(GT_U32)macEntry->entryState.ucEntryState, + (GT_U32*)&entry.entryState.ucEntryState); + } + + if (entry.entryState.ucEntryState == 0) + { + DBG_INFO(("Entry State should not be ZERO.\n")); + return GT_BAD_PARAM; + } + + retVal = atuOperationPerform(dev,LOAD_PURGE_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gfdbDelMacEntry +* +* DESCRIPTION: +* Deletes MAC address entry. If DBNum or FID is used, gfdbDelAtuEntry API +* would be the better choice to delete an entry in ATU. +* +* INPUTS: +* macAddress - mac address. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gfdbDelMacEntry +( + IN GT_QD_DEV *dev, + IN GT_ETHERADDR *macAddress +) +{ + GT_STATUS retVal; + GT_ATU_ENTRY entry; + + DBG_INFO(("gfdbDelMacEntry Called.\n")); + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_STATIC_ADDR)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + gtMemCpy(entry.macAddr.arEther,macAddress->arEther,6); + entry.DBNum = 0; + entry.prio = 0; + entry.portVec = 0; + entry.entryState.ucEntryState = 0; + entry.trunkMember = GT_FALSE; + entry.exPrio.useMacFPri = GT_FALSE; + entry.exPrio.macFPri = 0; + entry.exPrio.macQPri = 0; + + retVal = atuOperationPerform(dev,LOAD_PURGE_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbDelAtuEntry +* +* DESCRIPTION: +* Deletes ATU entry. +* +* INPUTS: +* atuEntry - the ATU entry to be deleted. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_RESOURCE - failed to allocate a t2c struct +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* DBNum in atuEntry - +* ATU MAC Address Database number. If multiple address +* databases are not being used, DBNum should be zero. +* If multiple address databases are being used, this value +* should be set to the desired address database number. +* +*******************************************************************************/ +GT_STATUS gfdbDelAtuEntry +( + IN GT_QD_DEV *dev, + IN GT_ATU_ENTRY *atuEntry +) +{ + GT_ATU_ENTRY entry; + GT_STATUS retVal; + + DBG_INFO(("gfdbDelMacEntry Called.\n")); + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_STATIC_ADDR)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + gtMemCpy(entry.macAddr.arEther,atuEntry->macAddr.arEther,6); + entry.DBNum = atuEntry->DBNum; + entry.prio = 0; + entry.portVec = 0; + entry.entryState.ucEntryState = 0; + entry.trunkMember = GT_FALSE; + entry.exPrio.useMacFPri = GT_FALSE; + entry.exPrio.macFPri = 0; + entry.exPrio.macQPri = 0; + + retVal = atuOperationPerform(dev,LOAD_PURGE_ENTRY,NULL,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gfdbLearnEnable +* +* DESCRIPTION: +* Enable/disable automatic learning of new source MAC addresses on port +* ingress. +* +* INPUTS: +* en - GT_TRUE for enable or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbLearnEnable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_LPORT port; + GT_BOOL mode; + + DBG_INFO(("gfdbLearnEnable Called.\n")); + BOOL_2_BIT(en,data); + data = 1 - data; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + mode = (en)?GT_FALSE:GT_TRUE; + + for (port=0; portnumOfPorts; port++) + { + retVal = gprtSetLearnDisable(dev,port,mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + } + else + { + /* Set the Learn Enable bit. */ + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_CONTROL,14,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gfdbGetLearnEnable +* +* DESCRIPTION: +* Get automatic learning status of new source MAC addresses on port ingress. +* +* INPUTS: +* None +* +* OUTPUTS: +* en - GT_TRUE if enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gfdbGetLearnEnable +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + DBG_INFO(("gfdbGetLearnEnable Called.\n")); + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + return GT_NOT_SUPPORTED; + } + else + { + /* Get the Learn Enable bit. */ + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_CONTROL,14,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + + data = 1 - data; + BOOL_2_BIT(data, *en); + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/****************************************************************************/ +/* Internal use functions. */ +/****************************************************************************/ + +/******************************************************************************* +* gatuGetViolation +* +* DESCRIPTION: +* Get ATU Violation data +* +* INPUTS: +* None. +* +* OUTPUTS: +* atuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gatuGetViolation +( + IN GT_QD_DEV *dev, + OUT GT_ATU_INT_STATUS *atuIntStatus +) +{ + GT_U16 intCause; + GT_STATUS retVal; + GT_ATU_ENTRY entry; + GT_EXTRA_OP_DATA opData; + GT_BOOL found, ageInt; + + DBG_INFO(("gatuGetViolation Called.\n")); + + /* check which Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,3,1,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read ATU OPERATION Register.\n")); + return retVal; + } + + if (!intCause) + { + /* No Violation occurred. */ + atuIntStatus->atuIntCause = 0; + return GT_OK; + } + + retVal = atuOperationPerform(dev,SERVICE_VIOLATIONS,&opData,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (atuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + gtMemCpy(atuIntStatus->macAddr.arEther,entry.macAddr.arEther,6); + + atuIntStatus->atuIntCause = (GT_U16)opData.intCause; + atuIntStatus->spid = entry.entryState.ucEntryState; + + if(atuIntStatus->spid != 0xF) + atuIntStatus->spid = (GT_U8)GT_PORT_2_LPORT(atuIntStatus->spid); + + if (IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + if (opData.intCause == GT_AGE_VIOLATION) + { + atuIntStatus->atuIntCause = GT_AGE_OUT_VIOLATION; + } + else if (opData.intCause == GT_MISS_VIOLATION) + { + /* check if it's AGE Violation */ + if((retVal = gsysGetAgeInt(dev, &ageInt)) != GT_OK) + return retVal; + + if(ageInt) + { + gfdbFindAtuMacEntry(dev, &entry, &found); + if ((found) && (entry.entryState.ucEntryState <= 4)) + atuIntStatus->atuIntCause = GT_AGE_VIOLATION; + } + + } + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* atuOperationPerform +* +* DESCRIPTION: +* This function is used by all ATU control functions, and is responsible +* to write the required operation into the ATU registers. +* +* INPUTS: +* atuOp - The ATU operation bits to be written into the ATU +* operation register. +* DBNum - ATU Database Number for CPU accesses +* entryPri - The EntryPri field in the ATU Data register. +* portVec - The portVec field in the ATU Data register. +* entryState - The EntryState field in the ATU Data register. +* atuMac - The Mac address to be written to the ATU Mac registers. +* +* OUTPUTS: +* entryPri - The EntryPri field in case the atuOp is GetNext. +* portVec - The portVec field in case the atuOp is GetNext. +* entryState - The EntryState field in case the atuOp is GetNext. +* atuMac - The returned Mac address in case the atuOp is GetNext. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* 1. if atuMac == NULL, nothing needs to be written to ATU Mac registers. +* +*******************************************************************************/ +static GT_STATUS atuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_ATU_OPERATION atuOp, + INOUT GT_EXTRA_OP_DATA *opData, + INOUT GT_ATU_ENTRY *entry +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U16 opcodeData; /* Data to be set into the */ + /* register. */ + GT_U8 i; + GT_U16 portMask; + + gtSemTake(dev,dev->atuRegsSem,OS_WAIT_FOREVER); + + portMask = (1 << dev->maxPorts) - 1; + + /* Wait until the ATU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + + opcodeData = 0; + + switch (atuOp) + { + case LOAD_PURGE_ENTRY: + if (IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY) || + IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + if (IS_IN_DEV_GROUP(dev,DEV_TRUNK) && entry->trunkMember) + { + /* portVec represents trunk ID */ + data = (GT_U16)( 0x8000 | (((entry->portVec) & 0xF) << 4) | + (((entry->entryState.ucEntryState) & 0xF)) ); + } + else + { + data = (GT_U16)( (((entry->portVec) & portMask) << 4) | + (((entry->entryState.ucEntryState) & 0xF)) ); + } + opcodeData |= (entry->prio & 0x7) << 8; + } + else if(IS_IN_DEV_GROUP(dev,DEV_ATU_EXT_PRI)) + { + data = (GT_U16)( (((entry->portVec) & portMask) << 4) | + (((entry->entryState.ucEntryState) & 0xF)) | + (((entry->exPrio.macQPri) & 0x3) << 14) ); + if(entry->exPrio.useMacFPri == GT_TRUE) + data |= ((1 << 13) | ((entry->exPrio.macFPri & 0x7) << 10)); + } + else + { + data = (GT_U16)( (((entry->prio) & 0x3) << 14) | + (((entry->portVec) & portMask) << 4) | + (((entry->entryState.ucEntryState) & 0xF)) ); + } + retVal = hwWriteGlobalReg(dev,QD_REG_ATU_DATA_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + /* pass thru */ + + case GET_NEXT_ENTRY: + for(i = 0; i < 3; i++) + { + data=(entry->macAddr.arEther[2*i] << 8)|(entry->macAddr.arEther[1 + 2*i]); + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_ATU_MAC_BASE+i),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + break; + + case FLUSH_ALL: + case FLUSH_UNLOCKED: + case FLUSH_ALL_IN_DB: + case FLUSH_UNLOCKED_IN_DB: + if (entry->entryState.ucEntryState == 0xF) + { + data = (GT_U16)(0xF | ((opData->moveFrom & 0xF) << 4) | ((opData->moveTo & 0xF) << 8)); + } + else + { + data = 0; + } + retVal = hwWriteGlobalReg(dev,QD_REG_ATU_DATA_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + break; + + case SERVICE_VIOLATIONS: + + break; + + default : + return GT_FAIL; + } + + /* Set DBNum */ + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_FID_REG,0,12,(GT_U16)(entry->DBNum & 0xFFF)); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + retVal = hwSetGlobalRegField(dev,QD_REG_ATU_CONTROL,12,4,(GT_U16)((entry->DBNum & 0xF0) >> 4)); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + opcodeData |= ((entry->DBNum & 0x30) << 4); /* Op Reg bit 9:8 */ + } + + /* Set the ATU Operation register in addtion to DBNum setup */ + + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + opcodeData |= ((1 << 15) | (atuOp << 12)); + else + opcodeData |= ((1 << 15) | (atuOp << 12) | (entry->DBNum & 0xF)); + + retVal = hwWriteGlobalReg(dev,QD_REG_ATU_OPERATION,opcodeData); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + + /* If the operation is to service violation operation wait for the response */ + if(atuOp == SERVICE_VIOLATIONS) + { + /* Wait until the VTU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + + /* get the Interrupt Cause */ + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,4,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + data &= 0x7; /* only 3 bits are valid for non age_out_int group */ + } + + switch (data) + { + case 8: /* Age Interrupt */ + opData->intCause = GT_AGE_VIOLATION; + break; + case 4: /* Member Violation */ + opData->intCause = GT_MEMBER_VIOLATION; + break; + case 2: /* Miss Violation */ + opData->intCause = GT_MISS_VIOLATION; + break; + case 1: /* Full Violation */ + opData->intCause = GT_FULL_VIOLATION; + break; + default: + opData->intCause = 0; + gtSemGive(dev,dev->atuRegsSem); + return GT_OK; + } + + /* get the DBNum that was involved in the violation */ + + entry->DBNum = 0; + + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_FID_REG,0,12,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->DBNum = (GT_U16)data; + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_CONTROL,12,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->DBNum = (GT_U16)data << 4; + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,8,2,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->DBNum = (GT_U16)data << 4; + } + + if(!IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,0,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + + entry->DBNum |= (GT_U8)(data & 0xF); + } + + /* get the Source Port ID that was involved in the violation */ + + retVal = hwReadGlobalReg(dev,QD_REG_ATU_DATA_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + + entry->entryState.ucEntryState = data & 0xF; + + /* Get the Mac address */ + for(i = 0; i < 3; i++) + { + retVal = hwReadGlobalReg(dev,(GT_U8)(QD_REG_ATU_MAC_BASE+i),&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->macAddr.arEther[2*i] = data >> 8; + entry->macAddr.arEther[1 + 2*i] = data & 0xFF; + } + + + } /* end of service violations */ + /* If the operation is a gen next operation wait for the response */ + if(atuOp == GET_NEXT_ENTRY) + { + entry->trunkMember = GT_FALSE; + entry->exPrio.useMacFPri = GT_FALSE; + entry->exPrio.macFPri = 0; + entry->exPrio.macQPri = 0; + + /* Wait until the ATU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + } + + /* Get the Mac address */ + for(i = 0; i < 3; i++) + { + retVal = hwReadGlobalReg(dev,(GT_U8)(QD_REG_ATU_MAC_BASE+i),&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->macAddr.arEther[2*i] = data >> 8; + entry->macAddr.arEther[1 + 2*i] = data & 0xFF; + } + + retVal = hwReadGlobalReg(dev,QD_REG_ATU_DATA_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + + /* Get the Atu data register fields */ + if(IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_TRUNK)) + { + if (IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + entry->trunkMember = (data & 0x8000)?GT_TRUE:GT_FALSE; + } + + entry->portVec = (data >> 4) & portMask; + entry->entryState.ucEntryState = data & 0xF; + retVal = hwGetGlobalRegField(dev,QD_REG_ATU_OPERATION,8,3,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->atuRegsSem); + return retVal; + } + entry->prio = (GT_U8)data; + } + else if(IS_IN_DEV_GROUP(dev,DEV_ATU_EXT_PRI)) + { + entry->prio = 0; + entry->portVec = (data >> 4) & portMask; + entry->entryState.ucEntryState = data & 0xF; + entry->exPrio.useMacFPri = (data & 0x2000)?GT_TRUE:GT_FALSE; + entry->exPrio.macFPri = (data >> 10) & 0x7; + entry->exPrio.macQPri = data >> 14; + } + else + { + entry->prio = data >> 14; + entry->portVec = (data >> 4) & portMask; + entry->entryState.ucEntryState = data & 0xF; + } + } + + gtSemGive(dev,dev->atuRegsSem); + return GT_OK; +} + +static GT_STATUS atuStateAppToDev +( + IN GT_QD_DEV *dev, + IN GT_BOOL unicast, + IN GT_U32 state, + OUT GT_U32 *newOne +) +{ + GT_U32 newState; + GT_STATUS retVal = GT_OK; + + if(unicast) + { + switch ((GT_ATU_UC_STATE)state) + { + case GT_UC_INVALID: + newState = state; + break; + + case GT_UC_DYNAMIC: + if (IS_IN_DEV_GROUP(dev,DEV_UC_7_DYNAMIC)) + { + newState = 7; + } + else + { + newState = 0xE; + } + break; + + case GT_UC_NO_PRI_TO_CPU_STATIC_NRL: + if (IS_IN_DEV_GROUP(dev,DEV_UC_NO_PRI_TO_CPU_STATIC_NRL)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_TO_CPU_STATIC_NRL: + if (IS_IN_DEV_GROUP(dev,DEV_UC_TO_CPU_STATIC_NRL)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_NO_PRI_STATIC_NRL: + if (IS_IN_DEV_GROUP(dev,DEV_UC_NO_PRI_STATIC_NRL)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_STATIC_NRL: + if (IS_IN_DEV_GROUP(dev,DEV_UC_STATIC_NRL)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_NO_PRI_TO_CPU_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_UC_NO_PRI_TO_CPU_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_TO_CPU_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_UC_TO_CPU_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_NO_PRI_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_UC_NO_PRI_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_UC_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_UC_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_UC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + default: + if (IS_IN_DEV_GROUP(dev,DEV_UC_7_DYNAMIC)) + { + newState = 7; + } + else + { + newState = 0xE; + } + retVal = GT_BAD_PARAM; + break; + + } + } + else + { + switch ((GT_ATU_UC_STATE)state) + { + case GT_MC_INVALID: + newState = state; + break; + + case GT_MC_MGM_STATIC_UNLIMITED_RATE: + if (IS_IN_DEV_GROUP(dev,DEV_MC_MGM_STATIC_UNLIMITED_RATE)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_STATIC_UNLIMITED_RATE: + if (IS_IN_DEV_GROUP(dev,DEV_MC_STATIC_UNLIMITED_RATE)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_MGM_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_MC_MGM_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_MC_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_PRIO_MGM_STATIC_UNLIMITED_RATE: + if (IS_IN_DEV_GROUP(dev,DEV_MC_PRIO_MGM_STATIC_UNLIMITED_RATE)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_PRIO_STATIC_UNLIMITED_RATE: + if (IS_IN_DEV_GROUP(dev,DEV_MC_PRIO_STATIC_UNLIMITED_RATE)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_PRIO_MGM_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_MC_PRIO_MGM_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + case GT_MC_PRIO_STATIC: + if (IS_IN_DEV_GROUP(dev,DEV_MC_PRIO_STATIC)) + { + newState = state; + } + else + { + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + } + break; + + default: + newState = (GT_U32)GT_MC_STATIC; + retVal = GT_BAD_PARAM; + break; + + } + } + + *newOne = newState; + return retVal; +} + +static GT_STATUS atuStateDevToApp +( + IN GT_QD_DEV *dev, + IN GT_BOOL unicast, + IN GT_U32 state, + OUT GT_U32 *newOne +) +{ + GT_U32 newState; + GT_STATUS retVal = GT_OK; + + if(unicast) + { + if (state == 0) + { + newState = (GT_U32)GT_UC_INVALID; + } + else if (state <= 7) + { + newState = (GT_U32)GT_UC_DYNAMIC; + } + else if ((state <= 0xE) && (!IS_IN_DEV_GROUP(dev,DEV_UC_7_DYNAMIC))) + { + newState = (GT_U32)GT_UC_DYNAMIC; + } + else + { + newState = state; + } + } + else + { + newState = state; + } + + *newOne = newState; + return retVal; +} + + +static GT_STATUS atuGetStats +( + IN GT_QD_DEV *dev, + IN GT_ATU_STAT *atuStat, + OUT GT_U32 *count +) +{ + GT_U32 numOfEntries, dbNum; + GT_ATU_ENTRY entry; + GT_U16 data,mode,bin; + GT_STATUS retVal; + + DBG_INFO(("atuGetStats Called.\n")); + + switch (atuStat->op) + { + case GT_ATU_STATS_ALL: + case GT_ATU_STATS_NON_STATIC: + dbNum = 0; + break; + case GT_ATU_STATS_ALL_FID: + case GT_ATU_STATS_NON_STATIC_FID: + dbNum = atuStat->DBNum; + break; + default: + return GT_FALSE; + } + + numOfEntries = 0; + mode = atuStat->op; + + for(bin=0; bin<4; bin++) + { + data = (bin << 14) | (mode << 12); + + retVal = hwWriteGlobal2Reg(dev, QD_REG_ATU_STATS, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + entry.DBNum = (GT_U16)dbNum; + gtMemSet(entry.macAddr.arEther,0,sizeof(GT_ETHERADDR)); + + retVal = atuOperationPerform(dev,GET_NEXT_ENTRY,NULL,&entry); + if(retVal == GT_FAIL) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + retVal = hwReadGlobal2Reg(dev, QD_REG_ATU_STATS, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + numOfEntries += (data & 0xFFF); + } + + *count = numOfEntries; + + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStp.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStp.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStp.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStp.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,333 @@ +#include + +/******************************************************************************** +* gtBrgStp.c +* +* DESCRIPTION: +* API definitions to handle port spanning tree state. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +*******************************************************************************/ + +#include +#include +#include + +static GT_STATUS enhancedBPDUSet(GT_QD_DEV *dev,GT_BOOL en) +{ + GT_STATUS retVal = GT_OK; /* Functions return value. */ + GT_U16 enBits; + + /* If disable, reset the BPDU bit(bit0) from Rsvd2CpuEnables register */ + if(en == GT_FALSE) + { + if((retVal = gsysGetRsvd2CpuEnables(dev,&enBits)) != GT_OK) + { + DBG_INFO(("gsysGetRsvd2CpuEnables failed.\n")); + return retVal; + } + enBits &= ~0x1; + + if((retVal = gsysSetRsvd2CpuEnables(dev,enBits)) != GT_OK) + { + DBG_INFO(("gsysSetRsvd2CpuEnables failed.\n")); + return retVal; + } + + return retVal; + } + + /* + If enable, + 1) Set MGMT Pri bits, + 2) Set BPDU bit(bit0) from Rsvd2CpuEnables register, + 3) Enable Rsvd2Cpu + */ + if((retVal = gsysSetMGMTPri(dev,7)) != GT_OK) + { + DBG_INFO(("gsysSetMGMTPri failed.\n")); + return retVal; + } + + if((retVal = gsysGetRsvd2CpuEnables(dev,&enBits)) != GT_OK) + { + DBG_INFO(("gsysGetRsvd2CpuEnables failed.\n")); + return retVal; + } + enBits |= 0x1; + if((retVal = gsysSetRsvd2CpuEnables(dev,enBits)) != GT_OK) + { + DBG_INFO(("gsysSetRsvd2CpuEnables failed.\n")); + return retVal; + } + + if((retVal = gsysSetRsvd2Cpu(dev,GT_TRUE)) != GT_OK) + { + DBG_INFO(("gsysSetRsvd2Cpu failed.\n")); + return retVal; + } + + return retVal; +} + + +/******************************************************************************* +* gstpSetMode +* +* DESCRIPTION: +* This routine Enable the Spanning tree. +* +* INPUTS: +* en - GT_TRUE for enable, GT_FALSE for disable. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* when enabled, this function sets all port to blocking state, and inserts +* the BPDU MAC into the ATU to be captured to CPU, on disable all port are +* being modified to be in forwarding state. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpSetMode +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +) +{ + GT_STATUS retVal = GT_OK; /* Functions return value. */ + GT_ATU_ENTRY atuEntry; /* The ATU entry data to be set */ + GT_U32 i, dbNum; + + DBG_INFO(("gstpSetMode Called.\n")); + if(dev->deviceId == GT_88E6051) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + if((en == GT_TRUE) && (dev->stpMode == 1)) + { + DBG_INFO(("OK.\n")); + return GT_OK; + } + + switch(dev->deviceId) + { + case GT_88E6051: + case GT_88E6052: + dbNum = 1; + break; + case GT_FF_HG: + case GT_FF_EG: + case GT_88E6021: + case GT_88E6060: + case GT_88E6031: + case GT_88E6061: + case GT_88E6063: + case GT_FH_VPN: + case GT_88E6083: + case GT_88E6153: + case GT_88E6181: + case GT_88E6183: + case GT_88E6093: + dbNum = 16; + break; + case GT_88E6035: + case GT_88E6055: + case GT_88E6065: + dbNum = 64; + break; + default: + if (!IS_IN_DEV_GROUP(dev,DEV_ENHANCED_MULTICAST)) + { + dbNum = 64; + } + else + { + dbNum = 0; + retVal = enhancedBPDUSet(dev,en); + } + break; + } + + for (i=0; icpuPortNum)); + if(IS_IN_DEV_GROUP(dev,DEV_ATU_EXT_PRI)) + { + if(IS_IN_DEV_GROUP(dev,DEV_FQPRI_IN_TABLE)) + { + atuEntry.exPrio.useMacFPri = GT_TRUE; + atuEntry.exPrio.macFPri = 7; + } + else + { + atuEntry.exPrio.useMacFPri = 0; + atuEntry.exPrio.macFPri = 0; + } + atuEntry.exPrio.macQPri = 3; + atuEntry.prio = 0; + } + else + { + atuEntry.prio = 3; + atuEntry.exPrio.useMacFPri = 0; + atuEntry.exPrio.macFPri = 0; + atuEntry.exPrio.macQPri = 0; + } + atuEntry.DBNum = (GT_U8)i; + atuEntry.entryState.mcEntryState = GT_MC_PRIO_MGM_STATIC; + + if(en == GT_TRUE) + { + retVal = gfdbAddMacEntry(dev,&atuEntry); + } + else + { + if(dev->stpMode == 0) + break; + retVal = gfdbDelAtuEntry(dev,&atuEntry); + } + + if (retVal != GT_OK) + break; + } + + if(retVal == GT_OK) + { + if(en == GT_TRUE) + dev->stpMode = 1; + else + dev->stpMode = 2; + DBG_INFO(("OK.\n")); + } + else + { + dev->stpMode = 0; + DBG_INFO(("Failed.\n")); + } + + + return retVal; +} + + + +/******************************************************************************* +* gstpSetPortState +* +* DESCRIPTION: +* This routine set the port state. +* +* INPUTS: +* port - the logical port number. +* state - the port state to set. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpSetPortState +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_STP_STATE state +) +{ + GT_U8 phyPort; /* Physical port */ + GT_U16 data; /* Data to write to register. */ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gstpSetPortState Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + data = state; + + /* Set the port state bits. */ + retVal= hwSetPortRegField(dev,phyPort, QD_REG_PORT_CONTROL,0,2,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gstpGetPortState +* +* DESCRIPTION: +* This routine returns the port state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - the current port state. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gstpGetPortState +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_STP_STATE *state +) +{ + GT_U8 phyPort; /* Physical port */ + GT_U16 data; /* Data read from register. */ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gstpGetPortState Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* Get the port state bits. */ + retVal = hwGetPortRegField(dev,phyPort, QD_REG_PORT_CONTROL,0,2,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *state = data & 0x3; + DBG_INFO(("OK.\n")); + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStu.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStu.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStu.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgStu.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,848 @@ +#include + +/******************************************************************************* +* gtBrgStu.c +* +* DESCRIPTION: +* API definitions for SID (VTU 802.1s Port State Information Database) +* Translation Unit. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: $ +*******************************************************************************/ + +#include +#include +#include +#include + +/****************************************************************************/ +/* Forward function declaration. */ +/****************************************************************************/ + +static GT_STATUS stuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_STU_OPERATION stuOp, + INOUT GT_U8 *valid, + INOUT GT_STU_ENTRY *stuEntry +); + +/******************************************************************************* +* gstuGetEntryCount +* +* DESCRIPTION: +* Gets the current number of valid entries in the STU table +* +* INPUTS: +* None. +* +* OUTPUTS: +* numEntries - number of STU entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gstuGetEntryCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numEntries +) +{ + GT_U8 valid; + GT_U32 numOfEntries; + GT_STATUS retVal; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuGetEntryCount Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.sid = 0; + numOfEntries = 0; + + while(1) + { + retVal = stuOperationPerform(dev,GET_NEXT_STU_ENTRY,&valid,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + if( entry.sid==0x3F ) + { + if (valid==1) numOfEntries++; + break; + } + + numOfEntries++; + } + + *numEntries = numOfEntries; + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gstuGetEntryFirst +* +* DESCRIPTION: +* Gets first lexicographic entry from the STU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* stuEntry - find the first valid STU entry. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - table is empty. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuGetEntryFirst +( + IN GT_QD_DEV *dev, + OUT GT_STU_ENTRY *stuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuGetEntryFirst Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + entry.sid = 0; + valid = 0; + + retVal = stuOperationPerform(dev,GET_NEXT_STU_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrieve the value from the operation */ + + if((entry.sid == 0x3F) && (valid == 0)) + return GT_NO_SUCH; + + stuEntry->sid = entry.sid; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + stuEntry->portState[lport]=entry.portState[port]; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gstuGetEntryNext +* +* DESCRIPTION: +* Gets next lexicographic STU entry from the specified SID. +* +* INPUTS: +* stuEntry - the SID to start the search. +* +* OUTPUTS: +* stuEntry - next STU entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gstuGetEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_STU_ENTRY *stuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuGetEntryNext Called.\n")); + + /* check if device supports this feature */ + + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if(stuEntry->sid >= 0x3F) + { + return GT_NO_SUCH; + } + else + { + entry.sid = stuEntry->sid; + } + valid = 0; + + retVal = stuOperationPerform(dev,GET_NEXT_STU_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrieve the value from the operation */ + + if((entry.sid == 0x3F) && (valid == 0)) + return GT_NO_SUCH; + + stuEntry->sid = entry.sid; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + stuEntry->portState[lport]=entry.portState[port]; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gstuFindSidEntry +* +* DESCRIPTION: +* Find STU entry for a specific SID, it will return the entry, if found, +* along with its associated data +* +* INPUTS: +* stuEntry - contains the SID to searche for +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* stuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no such entry. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Valid SID is 1 ~ 63. +* +*******************************************************************************/ +GT_STATUS gstuFindSidEntry +( + IN GT_QD_DEV *dev, + INOUT GT_STU_ENTRY *stuEntry, + OUT GT_BOOL *found +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuFindSidEntry Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if((stuEntry->sid == 0) || (stuEntry->sid > 0x3F)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + *found = GT_FALSE; + + /* Decrement 1 from sid */ + entry.sid = stuEntry->sid-1; + valid = 0; /* valid is not used as input in this operation */ + + retVal = stuOperationPerform(dev,GET_NEXT_STU_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrive the value from the operation */ + if ((entry.sid != stuEntry->sid) | (valid == 0)) + return GT_NO_SUCH; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + stuEntry->portState[lport]=entry.portState[port]; + } + + *found = GT_TRUE; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gstuAddEntry +* +* DESCRIPTION: +* Creates or update the entry in STU table based on user input. +* +* INPUTS: +* stuEntry - stu entry to insert to the STU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Valid SID is 1 ~ 63. +* +*******************************************************************************/ +GT_STATUS gstuAddEntry +( + IN GT_QD_DEV *dev, + IN GT_STU_ENTRY *stuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_STU_ENTRY tmpStuEntry; + GT_BOOL found; + int count = 50000; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuAddEntry Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if((stuEntry->sid == 0) || (stuEntry->sid > 0x3F)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + entry.sid = stuEntry->sid; + + valid = 1; /* for load operation */ + + for(port=0; portmaxPorts; port++) + { + lport = GT_PORT_2_LPORT(port); + if (lport == GT_INVALID_PORT) + entry.portState[port] = 0; + else + entry.portState[port] = stuEntry->portState[lport]; + } + + retVal = stuOperationPerform(dev,LOAD_PURGE_STU_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* verify that the given entry has been added */ + tmpStuEntry.sid = stuEntry->sid; + + if((retVal = gstuFindSidEntry(dev,&tmpStuEntry,&found)) != GT_OK) + { + while(count--); + if((retVal = gstuFindSidEntry(dev,&tmpStuEntry,&found)) != GT_OK) + { + DBG_INFO(("Added entry cannot be found\n")); + return retVal; + } + } + if(found == GT_FALSE) + { + DBG_INFO(("Added entry cannot be found\n")); + return GT_FAIL; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gstuDelEntry +* +* DESCRIPTION: +* Deletes STU entry specified by user. +* +* INPUTS: +* stuEntry - the STU entry to be deleted +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Valid SID is 1 ~ 63. +* +*******************************************************************************/ +GT_STATUS gstuDelEntry +( + IN GT_QD_DEV *dev, + IN GT_STU_ENTRY *stuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_STU_ENTRY entry; + + DBG_INFO(("gstuDelEntry Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if((stuEntry->sid == 0) || (stuEntry->sid > 0x3F)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + entry.sid = stuEntry->sid; + valid = 0; /* for delete operation */ + + retVal = stuOperationPerform(dev,LOAD_PURGE_STU_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/****************************************************************************/ +/* Internal use functions. */ +/****************************************************************************/ + +static GT_STATUS stuSetSTUData +( + IN GT_QD_DEV *dev, + IN GT_STU_ENTRY *entry +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data1,data2,data3; /* Data to be set into the */ + GT_U16 nStuData = 0; + + data1 = data2 = data3 = 0; + + switch (dev->maxPorts) + { + case 11: + data3 |= (entry->portState[10] & 3) << 10; + /* pass through */ + case 10: + data3 |= (entry->portState[9] & 3) << 6; + /* pass through */ + case 9: + data3 |= (entry->portState[8] & 3) << 2; + nStuData++; + + /* pass through */ + case 8: + data2 |= (entry->portState[7] & 3) << 14; + /* pass through */ + case 7: + data2 |= (entry->portState[6] & 3) << 10; + /* pass through */ + case 6: + data2 |= (entry->portState[5] & 3) << 6; + /* pass through */ + case 5: + data2 |= (entry->portState[4] & 3) << 2; + nStuData++; + + /* pass through */ + case 4: + data1 |= (entry->portState[3] & 3) << 14; + /* pass through */ + case 3: + data1 |= (entry->portState[2] & 3) << 10; + /* pass through */ + case 2: + data1 |= (entry->portState[1] & 3) << 6; + /* pass through */ + case 1: + data1 |= (entry->portState[0] & 3) << 2; + nStuData++; + break; + + default: + return GT_FAIL; + } + + switch(nStuData) + { + case 3: + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA3_REG,data3); + if(retVal != GT_OK) + { + return retVal; + } + /* pass through */ + case 2: + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA2_REG,data2); + if(retVal != GT_OK) + { + return retVal; + } + /* pass through */ + case 1: + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA1_REG,data1); + if(retVal != GT_OK) + { + return retVal; + } + break; + default: + return GT_FAIL; + } + + return retVal; +} + +static GT_STATUS stuGetSTUData +( + IN GT_QD_DEV *dev, + OUT GT_STU_ENTRY *entry +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data1,data2,data3; /* Data to be set into the */ + GT_U16 nStuData = 0; + + data1 = data2 = data3 = 0; + + gtMemSet((void*)entry->portState,0,sizeof(entry->portState)); + + switch (dev->maxPorts) + { + case 11: + case 10: + case 9: + nStuData = 3; + break; + + case 8: + case 7: + case 6: + case 5: + nStuData = 2; + break; + + case 4: + case 3: + case 2: + case 1: + nStuData = 1; + break; + + default: + return GT_FAIL; + } + + switch(nStuData) + { + case 3: + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA3_REG,&data3); + if(retVal != GT_OK) + { + return retVal; + } + /* pass through */ + case 2: + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA2_REG,&data2); + if(retVal != GT_OK) + { + return retVal; + } + /* pass through */ + case 1: + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA1_REG,&data1); + if(retVal != GT_OK) + { + return retVal; + } + break; + default: + return GT_FAIL; + } + + switch (dev->maxPorts) + { + case 11: + entry->portState[10] = (data3 >> 10) & 3 ; + /* pass through */ + case 10: + entry->portState[9] = (data3 >> 6) & 3 ; + /* pass through */ + case 9: + entry->portState[8] = (data3 >> 2) & 3 ; + /* pass through */ + case 8: + entry->portState[7] = (data2 >> 14) & 3 ; + /* pass through */ + case 7: + entry->portState[6] = (data2 >> 10) & 3 ; + /* pass through */ + case 6: + entry->portState[5] = (data2 >> 6) & 3 ; + /* pass through */ + case 5: + entry->portState[4] = (data2 >> 2) & 3 ; + /* pass through */ + case 4: + entry->portState[3] = (data1 >> 14) & 3 ; + /* pass through */ + case 3: + entry->portState[2] = (data1 >> 10) & 3 ; + /* pass through */ + case 2: + entry->portState[1] = (data1 >> 6) & 3 ; + /* pass through */ + case 1: + entry->portState[0] = (data1 >> 2) & 3 ; + break; + + default: + return GT_FAIL; + } + + return GT_OK; +} + + +/******************************************************************************* +* stuOperationPerform +* +* DESCRIPTION: +* This function is used by all STU control functions, and is responsible +* to write the required operation into the STU registers. +* +* INPUTS: +* stuOp - The STU operation bits to be written into the STU +* operation register. +* sid - sid +* valid - valid bit +* stuData - STU Data with port state information +* +* OUTPUTS: +* sid - sid +* valid - valid bit +* stuData - STU Data with port state information +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ + +static GT_STATUS stuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_STU_OPERATION stuOp, + INOUT GT_U8 *valid, + INOUT GT_STU_ENTRY *entry +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + + gtSemTake(dev,dev->vtuRegsSem,OS_WAIT_FOREVER); + + /* Wait until the VTU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /* Set the VTU data register if Load operation is required. */ + if (stuOp == LOAD_PURGE_STU_ENTRY) + { + if (*valid == 1) + { + /* set the Port State for all the ports */ + retVal = stuSetSTUData(dev,entry); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* Set the valid bit (QD_REG_VTU_VID_REG) */ + data= *valid << 12 ; + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_VTU_VID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + else + { + /* Clear the valid bit (QD_REG_VTU_VID_REG) */ + data= 0 ; + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_VTU_VID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + } + + /* Set the SID register (QD_REG_STU_SID_REG) */ + data= (entry->sid) & 0x3F; + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_STU_SID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* Start the STU Operation by defining the stuOp and VTUBusy */ + data = (1 << 15) | (stuOp << 12); + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_OPERATION,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* If the operation is a get next operation wait for the response */ + if(stuOp == GET_NEXT_STU_ENTRY) + { + /* Wait until the STU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /****************** get the valid bit *******************/ + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_VID_REG,12,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + *valid = (GT_U8)data; + + /****************** get the sid *******************/ + + retVal = hwReadGlobalReg(dev,QD_REG_STU_SID_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* the sid is bits 0-5 */ + entry->sid = data & 0x3F; + + if (*valid) + { + /* get the Port State for all the ports */ + retVal = stuGetSTUData(dev,entry); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + } /* entry is valid */ + + } /* end of get next entry */ + + gtSemGive(dev,dev->vtuRegsSem); + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVlan.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVlan.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVlan.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVlan.c 2011-04-04 13:57:35.085596463 -0400 @@ -0,0 +1,1289 @@ +#include + +/******************************************************************************** +* gtBrgVlan.c +* +* DESCRIPTION: +* API definitions to handle port-based vlan configuration. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* gprtSetEgressMode +* +* DESCRIPTION: +* This routine set the egress mode. +* +* INPUTS: +* port - the logical port number. +* mode - the egress mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EGRESS_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gprtSetEgressMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_TAGGING)) != GT_OK ) + return retVal; + + switch (mode) + { + case (GT_UNMODIFY_EGRESS): + data = 0; + break; + + case (GT_TAGGED_EGRESS): + data = 2; + break; + + case (GT_UNTAGGED_EGRESS): + data = 1; + break; + + case (GT_ADD_TAG): + if(!IS_IN_DEV_GROUP(dev,DEV_EGRESS_DOUBLE_TAGGING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + data = 3; + break; + default: + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL,12,2,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gprtGetEgressMode +* +* DESCRIPTION: +* This routine get the egress mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the egress mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EGRESS_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + if(mode == NULL) + return GT_BAD_PARAM; + + DBG_INFO(("gprtGetEgressMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL,12,2,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + switch (data) + { + case (0): + *mode = GT_UNMODIFY_EGRESS; + break; + + case (2): + *mode = GT_TAGGED_EGRESS; + break; + + case (1): + *mode = GT_UNTAGGED_EGRESS; + break; + + case (3): + *mode = GT_ADD_TAG; + break; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gprtSetVlanTunnel +* +* DESCRIPTION: +* This routine sets the vlan tunnel mode. +* +* INPUTS: +* port - the logical port number. +* mode - the vlan tunnel mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetVlanTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gprtSetVlanTunnel Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + BOOL_2_BIT(mode,data); + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL,7,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gprtGetVlanTunnel +* +* DESCRIPTION: +* This routine get the vlan tunnel mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the vlan tunnel mode.. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetVlanTunnel +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gprtGetVlanTunnel Called.\n")); + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL,7,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvlnSetPortVlanPorts +* +* DESCRIPTION: +* This routine sets the port VLAN group port membership list. +* +* INPUTS: +* port - logical port number to set. +* memPorts - array of logical ports in the same vlan. +* memPortsLen - number of members in memPorts array +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanPorts +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LPORT memPorts[], + IN GT_U8 memPortsLen +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + GT_U8 i; + + DBG_INFO(("gvlnSetPortVlanPorts Called.\n")); + if(memPorts == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + data = 0; + + if(memPortsLen > dev->numOfPorts) + { + DBG_INFO(("Failed (PortsLen Too Big).\n")); + return GT_BAD_PARAM; + } + + for(i = 0; i < memPortsLen; i++) + data |= (1 << GT_LPORT_2_PORT(memPorts[i])); + + /* numOfPorts = 3 for fullsail, = 10 for octane, = 7 for others */ + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,0,dev->maxPorts,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvlnGetPortVlanPorts +* +* DESCRIPTION: +* This routine gets the port VLAN group port membership list. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* memPorts - array of logical ports in the same vlan. +* memPortsLen - number of members in memPorts array +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanPorts +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_LPORT memPorts[], + OUT GT_U8 *memPortsLen +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + GT_U8 i; + + DBG_INFO(("gvlnGetPortVlanPorts Called.\n")); + if((memPorts == NULL) || (memPortsLen == NULL)) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + /* memPortsLen = 3 for fullsail, =7 for others */ + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,0,dev->maxPorts,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + i = 0; + for(phyPort = 0; phyPort < dev->maxPorts; phyPort++) + { + if(!GT_IS_PORT_SET(dev->validPortVec, phyPort)) + continue; + + if(((1 << phyPort) & data) != 0) + { + memPorts[i] = GT_PORT_2_LPORT(phyPort); + i++; + } + } + *memPortsLen = i; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gvlnSetPortUserPriLsb +* +* DESCRIPTION: +* This routine Set the user priority (VPT) LSB bit, to be added to the +* user priority on the egress. +* +* INPUTS: +* port - logical port number to set. +* userPriLsb - GT_TRUE for 1, GT_FALSE for 0. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortUserPriLsb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL userPriLsb +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnSetPortUserPriLsb Called.\n")); + + /* Gigabit Switch does not support this status. */ + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + phyPort = GT_LPORT_2_PORT(port); + BOOL_2_BIT(userPriLsb,data); + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PVID,13,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvlnGetPortUserPriLsb +* +* DESCRIPTION: +* This routine gets the user priority (VPT) LSB bit. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* userPriLsb - GT_TRUE for 1, GT_FALSE for 0. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortUserPriLsb +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *userPriLsb +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnGetPortUserPriLsb Called.\n")); + + /* Gigabit Switch does not support this status. */ + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if(userPriLsb == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PVID,13,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*userPriLsb); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gvlnSetPortVid +* +* DESCRIPTION: +* This routine Set the port default vlan id. +* +* INPUTS: +* port - logical port number to set. +* vid - the port vlan id. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVid +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 vid +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnSetPortVid Called.\n")); + phyPort = GT_LPORT_2_PORT(port); + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PVID,0,12, vid); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gvlnGetPortVid +* +* DESCRIPTION: +* This routine Get the port default vlan id. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* vid - the port vlan id. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVid +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *vid +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnGetPortVid Called.\n")); + if(vid == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PVID,0,12, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *vid = data; + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gvlnSetPortVlanDBNum +* +* DESCRIPTION: +* This routine sets the port's default VLAN database number (DBNum or +* FID, Forwarding Information Database). +* +* INPUTS: +* port - logical port number to set. +* DBNum - database number for this port (or FID) +* +* OUTPUTS: +* None. +* +* RETURNS:IN GT_INGRESS_MODE mode +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanDBNum +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 DBNum +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnSetPortVlanDBNum Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_4096)) + { + if(DBNum > 4095) + { + return GT_BAD_PARAM; + } + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL1,0,8,(GT_U16)((DBNum & 0xFF0) >> 4)); + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4,(GT_U16)(DBNum & 0x000F)); + } + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + if(DBNum > 255) + { + return GT_BAD_PARAM; + } + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL1,0,4,(GT_U16)((DBNum & 0xF0) >> 4)); + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4,(GT_U16)(DBNum & 0x0F)); + } + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + if(DBNum > 63) + { + return GT_BAD_PARAM; + } + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,6,2,(GT_U16)((DBNum & 0x30) >> 4)); + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4,(GT_U16)(DBNum & 0x0F)); + } + else + { + if(DBNum > 15) + { + return GT_BAD_PARAM; + } + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4,(GT_U16)(DBNum & 0x0F)); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvlnGetPortVlanDBNum +* +* DESCRIPTION: +* This routine gets the port's default VLAN database number (DBNum or +* FID, Forwarding Information Database). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* DBNum - database number for this port (or FID) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanDBNum +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *DBNum +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data,dataH; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnGetPortVlanDBNum Called.\n")); + + if(DBNum == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_4096)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL1,0,8, &dataH); + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4, &data); + } + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL1,0,4, &dataH); + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4, &data); + } + else if(IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,6,2, &dataH); + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4, &data); + } + else + { + dataH = 0; + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,12,4, &data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *DBNum = (GT_U32)(data | (dataH << 4)); + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************** +* gvlnSetPortVlanDot1qMode +* +* DESCRIPTION: +* This routine sets the IEEE 802.1q mode for this port (11:10) +* +* INPUTS: +* port - logical port number to set. +* mode - 802.1q mode for this port +* +* OUTPUTS: +* None. +* +* RETURNS:IN GT_INGRESS_MODE mode +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanDot1qMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_DOT1Q_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnSetPortVlanDot1qMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_802_1Q)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL2,10,2,(GT_U16)mode ); + } + else + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,10,2,(GT_U16)mode ); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvlnGetPortVlanDot1qMode +* +* DESCRIPTION: +* This routine gets the IEEE 802.1q mode for this (bit 11:10). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* mode - 802.1q mode for this port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanDot1qMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_DOT1Q_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gvlnGetPortVlanDot1qMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_802_1Q)) != GT_OK ) + return retVal; + + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_CONTROL2,10,2, &data); + } + else + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,10,2, &data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *mode = data; + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************** +* gvlnSetPortVlanForceDefaultVID +* +* DESCRIPTION: +* This routine sets the mode for forcing to use default VID +* +* INPUTS: +* port - logical port number to set. +* mode - GT_TRUE, force to use default VID +* GT_FAULSE, otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnSetPortVlanForceDefaultVID +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + GT_U16 data; /* Data to be set into the */ + + DBG_INFO(("gvlnSetPortForceDefaultVID Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_802_1Q)) != GT_OK ) + return retVal; + + BOOL_2_BIT(mode,data); + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PVID,12,1,data ); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvlnGetPortVlanForceDefaultVID +* +* DESCRIPTION: +* This routine gets the port mode for ForceDefaultVID (bit 12). +* +* INPUTS: +* port - logical port number to get. +* +* OUTPUTS: +* mode - ForceDefaultVID mode for this port +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvlnGetPortVlanForceDefaultVID +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + + DBG_INFO(("gvlnGetPortVlanDot1qMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_802_1Q)) != GT_OK ) + return retVal; + + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PVID,12,1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************** +* gvlnSetForceMap +* +* DESCRIPTION: +* This routine enables/disables Force Map feature. +* When Force Map feature is enabled, all received frames will be +* considered MGMT and they are mapped to the port or ports defined +* in the VLAN Table overriding the mapping from the address database. +* +* INPUTS: +* port - logical port number to set. +* mode - GT_TRUE, to enable force map feature +* GT_FAULSE, otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gvlnSetForceMap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + GT_U16 data; /* Data to be set into the reg */ + + DBG_INFO(("gvlnSetForceMap Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_MAP)) + { + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(mode,data); + + retVal = hwSetPortRegField(dev,phyPort, QD_REG_PORT_VLAN_MAP, 8, 1, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + + +/******************************************************************** +* gvlnGetForceMap +* +* DESCRIPTION: +* This routine checks if Force Map feature is enabled. +* When Force Map feature is enabled, all received frames will be +* considered MGMT and they are mapped to the port or ports defined +* in the VLAN Table overriding the mapping from the address database. +* +* INPUTS: +* port - logical port number to set. +* +* OUTPUTS: +* mode - GT_TRUE, to enable force map feature +* GT_FAULSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gvlnGetForceMap +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + GT_U16 data; /* Data to be set into the reg */ + + DBG_INFO(("gvlnGetForceMap Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_MAP)) + { + return GT_NOT_SUPPORTED; + } + + retVal = hwGetPortRegField(dev,phyPort, QD_REG_PORT_VLAN_MAP, 8, 1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data, *mode); + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + + +/******************************************************************************* +* gvlnSetNoEgrPolicy +* +* DESCRIPTION: +* No Egress Policy. When this bit is set to a one Egress 802.1Q Secure and +* Check discards are not performed. This mode allowsa non-802.1Q enabled +* port to send a frame to an 802.1Q enabled port that is configured in the +* Secure or Check 802.1Q mode. In this situation the frames will egress +* even if the VID assigned to the frame is not found in the VTU. +* +* INPUTS: +* mode - no egress policy mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gvlnSetNoEgrPolicy +( + IN GT_QD_DEV *dev, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + + DBG_INFO(("gvlnSetNoEgrPolicy Called.\n")); + + /* Check if Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_NO_EGRESS_POLICY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(mode,data); + + /* Set related register */ + retVal = hwSetGlobal2RegField(dev,QD_REG_SDET_POLARITY,13,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvlnGetNoEgrPolicy +* +* DESCRIPTION: +* No Egress Policy. When this bit is set to a one Egress 802.1Q Secure and +* Check discards are not performed. This mode allowsa non-802.1Q enabled +* port to send a frame to an 802.1Q enabled port that is configured in the +* Secure or Check 802.1Q mode. In this situation the frames will egress +* even if the VID assigned to the frame is not found in the VTU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - no egress policy mode +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gvlnGetNoEgrPolicy +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + + DBG_INFO(("gvlnGetNoEgrPolicy Called.\n")); + + /* Check if Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_NO_EGRESS_POLICY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get related register */ + retVal = hwGetGlobal2RegField(dev,QD_REG_SDET_POLARITY,13,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + + DBG_INFO(("OK.\n")); + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVtu.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVtu.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVtu.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtBrgVtu.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,1531 @@ +#include + +/******************************************************************************* +* gtBrgVtu.c +* +* DESCRIPTION: +* API definitions for Vlan Translation Unit for 802.1Q. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 9 $ +*******************************************************************************/ + +#include +#include +#include +#include + +/****************************************************************************/ +/* Forward function declaration. */ +/****************************************************************************/ +#define MEMBER_TAG_CONV_FOR_APP(_dev,_tag) memberTagConversionForApp(_dev,_tag) +#define MEMBER_TAG_CONV_FOR_DEV(_dev,_tag) memberTagConversionForDev(_dev,_tag) + +static GT_U8 memberTagConversionForApp +( + IN GT_QD_DEV *dev, + IN GT_U8 tag +) +{ + GT_U8 convTag; + + /* check if memberTag needs to be converted */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + return tag; + + switch(tag) + { + case 0: + convTag = MEMBER_EGRESS_UNMODIFIED; + break; + case 1: + convTag = MEMBER_EGRESS_UNTAGGED; + break; + case 2: + convTag = MEMBER_EGRESS_TAGGED; + break; + case 3: + convTag = NOT_A_MEMBER; + break; + default: + DBG_INFO(("Unknown Tag (%#x) from Device !!!.\n",tag)); + convTag = 0xFF; + break; + + } + + return convTag; +} + +static GT_U8 memberTagConversionForDev +( + IN GT_QD_DEV *dev, + IN GT_U8 tag +) +{ + GT_U8 convTag; + + /* check if memberTag needs to be converted */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + return tag; + + switch(tag) + { + case MEMBER_EGRESS_UNMODIFIED: + convTag = 0; + break; + case NOT_A_MEMBER: + convTag = 3; + break; + case MEMBER_EGRESS_UNTAGGED: + convTag = 1; + break; + case MEMBER_EGRESS_TAGGED: + convTag = 2; + break; + default: + DBG_INFO(("Unknown Tag (%#x) from App. !!!.\n",tag)); + convTag = 0xFF; + break; + + } + + return convTag; +} + +static GT_STATUS vtuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_VTU_OPERATION vtuOp, + INOUT GT_U8 *valid, + INOUT GT_VTU_ENTRY *vtuEntry +); + +/******************************************************************************* +* gvtuGetEntryCount +* +* DESCRIPTION: +* Gets the current number of valid entries in the VTU table +* +* INPUTS: +* None. +* +* OUTPUTS: +* numEntries - number of VTU entries. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - vlan does not exist. +* +* COMMENTS: +* None +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryCount +( + IN GT_QD_DEV *dev, + OUT GT_U32 *numEntries +) +{ + GT_U8 valid; + GT_U32 numOfEntries; + GT_STATUS retVal; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetEntryCount Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + entry.vid = 0xFFF; + entry.DBNum = 0; + + numOfEntries = 0; + while(1) + { + retVal = vtuOperationPerform(dev,GET_NEXT_ENTRY,&valid,&entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + if( entry.vid==0xFFF ) + { + if (valid==1) numOfEntries++; + break; + } + + numOfEntries++; + } + + *numEntries = numOfEntries; + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gvtuGetEntryFirst +* +* DESCRIPTION: +* Gets first lexicographic entry from the VTU. +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuEntry - match VTU entry. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - table is empty. +* +* COMMENTS: +* Search starts from vid of all one's +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryFirst +( + IN GT_QD_DEV *dev, + OUT GT_VTU_ENTRY *vtuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetEntryFirst Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + entry.vid = 0xFFF; + entry.DBNum = 0; + + retVal = vtuOperationPerform(dev,GET_NEXT_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrive the value from the operation */ + + if((entry.vid == 0xFFF) && (valid == 0)) + return GT_NO_SUCH; + + vtuEntry->DBNum = entry.DBNum; + vtuEntry->vid = entry.vid; + + vtuEntry->vidPriOverride = entry.vidPriOverride; + vtuEntry->vidPriority = entry.vidPriority; + + vtuEntry->vidPolicy = entry.vidPolicy; + vtuEntry->sid = entry.sid; + + vtuEntry->vidExInfo.useVIDFPri = entry.vidExInfo.useVIDFPri; + vtuEntry->vidExInfo.vidFPri = entry.vidExInfo.vidFPri; + vtuEntry->vidExInfo.useVIDQPri = entry.vidExInfo.useVIDQPri; + vtuEntry->vidExInfo.vidQPri = entry.vidExInfo.vidQPri; + vtuEntry->vidExInfo.vidNRateLimit = entry.vidExInfo.vidNRateLimit; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + vtuEntry->vtuData.memberTagP[lport]=MEMBER_TAG_CONV_FOR_APP(dev,entry.vtuData.memberTagP[port]); + vtuEntry->vtuData.portStateP[lport]=entry.vtuData.portStateP[port]; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gvtuGetEntryNext +* +* DESCRIPTION: +* Gets next lexicographic VTU entry from the specified VID. +* +* INPUTS: +* vtuEntry - the VID to start the search. +* +* OUTPUTS: +* vtuEntry - match VTU entry. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* Search starts from the VID specified by the user. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetEntryNext +( + IN GT_QD_DEV *dev, + INOUT GT_VTU_ENTRY *vtuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetEntryNext Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + entry.DBNum = vtuEntry->DBNum; + entry.vid = vtuEntry->vid; + valid = 0; + + retVal = vtuOperationPerform(dev,GET_NEXT_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrieve the value from the operation */ + + if((entry.vid == 0xFFF) && (valid == 0)) + return GT_NO_SUCH; + + vtuEntry->DBNum = entry.DBNum; + vtuEntry->vid = entry.vid; + + vtuEntry->vidPriOverride = entry.vidPriOverride; + vtuEntry->vidPriority = entry.vidPriority; + + vtuEntry->vidPolicy = entry.vidPolicy; + vtuEntry->sid = entry.sid; + + vtuEntry->vidExInfo.useVIDFPri = entry.vidExInfo.useVIDFPri; + vtuEntry->vidExInfo.vidFPri = entry.vidExInfo.vidFPri; + vtuEntry->vidExInfo.useVIDQPri = entry.vidExInfo.useVIDQPri; + vtuEntry->vidExInfo.vidQPri = entry.vidExInfo.vidQPri; + vtuEntry->vidExInfo.vidNRateLimit = entry.vidExInfo.vidNRateLimit; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + vtuEntry->vtuData.memberTagP[lport]=MEMBER_TAG_CONV_FOR_APP(dev,entry.vtuData.memberTagP[port]); + vtuEntry->vtuData.portStateP[lport]=entry.vtuData.portStateP[port]; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvtuFindVidEntry +* +* DESCRIPTION: +* Find VTU entry for a specific VID, it will return the entry, if found, +* along with its associated data +* +* INPUTS: +* vtuEntry - contains the VID to searche for +* +* OUTPUTS: +* found - GT_TRUE, if the appropriate entry exists. +* vtuEntry - the entry parameters. +* +* RETURNS: +* GT_OK - on success. +* GT_FAIL - on error or entry does not exist. +* GT_NO_SUCH - no more entries. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuFindVidEntry +( + IN GT_QD_DEV *dev, + INOUT GT_VTU_ENTRY *vtuEntry, + OUT GT_BOOL *found +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuFindVidEntry Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + *found = GT_FALSE; + + /* Decrement 1 from vid */ + entry.vid = vtuEntry->vid-1; + valid = 0; /* valid is not used as input in this operation */ + entry.DBNum = vtuEntry->DBNum; + + retVal = vtuOperationPerform(dev,GET_NEXT_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* retrive the value from the operation */ + + if( (entry.vid !=vtuEntry->vid) | (valid !=1) ) + { + DBG_INFO(("Failed.\n")); + return GT_NO_SUCH; + } + + vtuEntry->DBNum = entry.DBNum; + + vtuEntry->vidPriOverride = entry.vidPriOverride; + vtuEntry->vidPriority = entry.vidPriority; + + vtuEntry->vidPolicy = entry.vidPolicy; + vtuEntry->sid = entry.sid; + + vtuEntry->vidExInfo.useVIDFPri = entry.vidExInfo.useVIDFPri; + vtuEntry->vidExInfo.vidFPri = entry.vidExInfo.vidFPri; + vtuEntry->vidExInfo.useVIDQPri = entry.vidExInfo.useVIDQPri; + vtuEntry->vidExInfo.vidQPri = entry.vidExInfo.vidQPri; + vtuEntry->vidExInfo.vidNRateLimit = entry.vidExInfo.vidNRateLimit; + + for(lport=0; lportnumOfPorts; lport++) + { + port = GT_LPORT_2_PORT(lport); + vtuEntry->vtuData.memberTagP[lport]=MEMBER_TAG_CONV_FOR_APP(dev,entry.vtuData.memberTagP[port]); + vtuEntry->vtuData.portStateP[lport]=entry.vtuData.portStateP[port]; + } + + *found = GT_TRUE; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gvtuFlush +* +* DESCRIPTION: +* This routine removes all entries from VTU Table. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuFlush +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; + + DBG_INFO(("gvtuFlush Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + { + return retVal; + } + + retVal = vtuOperationPerform(dev,FLUSH_ALL,NULL,NULL); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvtuAddEntry +* +* DESCRIPTION: +* Creates the new entry in VTU table based on user input. +* +* INPUTS: +* vtuEntry - vtu entry to insert to the VTU. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_FULL - vtu table is full +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuAddEntry +( + IN GT_QD_DEV *dev, + IN GT_VTU_ENTRY *vtuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_U8 port; + GT_LPORT lport; + GT_VTU_ENTRY tmpVtuEntry; + GT_BOOL found; + int count = 5000; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuAddEntry Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + entry.DBNum = vtuEntry->DBNum; + entry.vid = vtuEntry->vid; + + if(IS_IN_DEV_GROUP(dev,DEV_VTU_EXT_INFO)) + { + entry.vidPriOverride = 0; + entry.vidPriority = 0; + + entry.vidPolicy = GT_FALSE; + entry.sid = 0; + + if(IS_IN_DEV_GROUP(dev,DEV_FQPRI_IN_TABLE)) + { + entry.vidExInfo.useVIDFPri = vtuEntry->vidExInfo.useVIDFPri; + entry.vidExInfo.vidFPri = vtuEntry->vidExInfo.vidFPri; + entry.vidExInfo.useVIDQPri = vtuEntry->vidExInfo.useVIDQPri; + entry.vidExInfo.vidQPri = vtuEntry->vidExInfo.vidQPri; + entry.vidExInfo.vidNRateLimit = vtuEntry->vidExInfo.vidNRateLimit; + } + else + { + entry.vidExInfo.useVIDFPri = 0; + entry.vidExInfo.vidFPri = 0; + entry.vidExInfo.useVIDQPri = 0; + entry.vidExInfo.vidQPri = 0; + entry.vidExInfo.vidNRateLimit = vtuEntry->vidExInfo.vidNRateLimit; + } + } + else + { + entry.vidPriOverride = vtuEntry->vidPriOverride; + entry.vidPriority = vtuEntry->vidPriority; + + if(IS_IN_DEV_GROUP(dev,DEV_POLICY)) + { + entry.vidPolicy = vtuEntry->vidPolicy; + } + else + { + entry.vidPolicy = GT_FALSE; + } + + if(IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + entry.sid = vtuEntry->sid; + } + else + { + entry.sid = 0; + } + + entry.vidExInfo.useVIDFPri = 0; + entry.vidExInfo.vidFPri = 0; + entry.vidExInfo.useVIDQPri = 0; + entry.vidExInfo.vidQPri = 0; + entry.vidExInfo.vidNRateLimit = 0; + } + + valid = 1; /* for load operation */ + + for(port=0; portmaxPorts; port++) + { + lport = GT_PORT_2_LPORT(port); + if(lport == GT_INVALID_PORT) + { + entry.vtuData.memberTagP[port] = MEMBER_TAG_CONV_FOR_DEV(dev,NOT_A_MEMBER); + entry.vtuData.portStateP[port] = 0; + } + else + { + entry.vtuData.memberTagP[port] = MEMBER_TAG_CONV_FOR_DEV(dev,vtuEntry->vtuData.memberTagP[lport]); + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + entry.vtuData.portStateP[port] = vtuEntry->vtuData.portStateP[lport]; + else + entry.vtuData.portStateP[port] = 0; + } + } + + retVal = vtuOperationPerform(dev,LOAD_PURGE_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* verify that the given entry has been added */ + tmpVtuEntry.vid = vtuEntry->vid; + tmpVtuEntry.DBNum = vtuEntry->DBNum; + + if((retVal = gvtuFindVidEntry(dev,&tmpVtuEntry,&found)) != GT_OK) + { + while(count--); + if((retVal = gvtuFindVidEntry(dev,&tmpVtuEntry,&found)) != GT_OK) + { + DBG_INFO(("Added entry cannot be found\n")); + return retVal; + } + } + if(found == GT_FALSE) + { + DBG_INFO(("Added entry cannot be found\n")); + return GT_FAIL; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvtuDelEntry +* +* DESCRIPTION: +* Deletes VTU entry specified by user. +* +* INPUTS: +* vtuEntry - the VTU entry to be deleted +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NO_SUCH - if specified address entry does not exist +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuDelEntry +( + IN GT_QD_DEV *dev, + IN GT_VTU_ENTRY *vtuEntry +) +{ + GT_U8 valid; + GT_STATUS retVal; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuDelEntry Called.\n")); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK) + return retVal; + + entry.DBNum = vtuEntry->DBNum; + entry.vid = vtuEntry->vid; + valid = 0; /* for delete operation */ + + retVal = vtuOperationPerform(dev,LOAD_PURGE_ENTRY,&valid, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/****************************************************************************/ +/* Internal use functions. */ +/****************************************************************************/ + +/******************************************************************************* +* gvtuGetViolation +* +* DESCRIPTION: +* Get VTU Violation data +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation +( + IN GT_QD_DEV *dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +) +{ + GT_U8 spid; + GT_U16 vid; + GT_U16 intCause; + GT_STATUS retVal; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetViolation Called.\n")); + + /* check which Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,4,3,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read VTU OPERATION Register.\n")); + return retVal; + } + + if (intCause == 0) + { + /* No Violation occurred. */ + vtuIntStatus->vtuIntCause = 0; + return GT_OK; + } + + entry.DBNum = 0; + + retVal = vtuOperationPerform(dev,SERVICE_VIOLATIONS,NULL, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + spid = entry.DBNum & 0xF; + vid = entry.vid; + + if(spid == 0xF) + { + vtuIntStatus->vtuIntCause = GT_VTU_FULL_VIOLATION; + vtuIntStatus->spid = spid; + vtuIntStatus->vid = 0; + } + else + { + vtuIntStatus->vtuIntCause = intCause & (GT_MEMBER_VIOLATION | GT_MISS_VIOLATION); + vtuIntStatus->spid = spid; + vtuIntStatus->vid = vid; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvtuGetViolation2 +* +* DESCRIPTION: +* Get VTU Violation data (for Gigabit Device) +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation2 +( + IN GT_QD_DEV *dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +) +{ + GT_U16 intCause; + GT_STATUS retVal; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetViolation2 Called.\n")); + + /* check if Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,5,1,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read VTU OPERATION Register.\n")); + return retVal; + } + + if (intCause == 0) + { + /* No Violation occurred. */ + vtuIntStatus->vtuIntCause = 0; + return GT_OK; + } + + entry.DBNum = 0; + + retVal = vtuOperationPerform(dev,SERVICE_VIOLATIONS,NULL, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* check which Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,5,2,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read VTU OPERATION Register.\n")); + return retVal; + } + + switch (intCause) + { + case 0: + /* No Violation occurred. */ + vtuIntStatus->vtuIntCause = 0; + return GT_OK; + case 1: + /* Miss Violation */ + vtuIntStatus->vtuIntCause = GT_MISS_VIOLATION; + break; + case 2: + /* Member Violation */ + vtuIntStatus->vtuIntCause = GT_MEMBER_VIOLATION; + break; + default : + return GT_FAIL; + } + + vtuIntStatus->spid = entry.DBNum & 0xF; + vtuIntStatus->vid = entry.vid; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gvtuGetViolation3 +* +* DESCRIPTION: +* Get VTU Violation data +* +* INPUTS: +* None. +* +* OUTPUTS: +* vtuIntStatus - interrupt cause, source portID, and vid. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORT - if current device does not support this feature. +* +* COMMENTS: +* This is an internal function. No user should call this function. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gvtuGetViolation3 +( + IN GT_QD_DEV *dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +) +{ + GT_U16 intCause; + GT_STATUS retVal; + GT_VTU_ENTRY entry; + + DBG_INFO(("gvtuGetViolation3 Called.\n")); + + /* check if Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,5,1,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read VTU OPERATION Register.\n")); + return retVal; + } + + if (intCause == 0) + { + /* No Violation occurred. */ + vtuIntStatus->vtuIntCause = 0; + return GT_OK; + } + + entry.DBNum = 0; + + retVal = vtuOperationPerform(dev,SERVICE_VIOLATIONS,NULL, &entry); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (vtuOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* check which Violation occurred */ + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,4,3,&intCause); + if(retVal != GT_OK) + { + DBG_INFO(("ERROR to read VTU OPERATION Register.\n")); + return retVal; + } + + vtuIntStatus->vtuIntCause = 0; + + if(intCause & 0x1) + { + vtuIntStatus->vtuIntCause |= GT_VTU_FULL_VIOLATION; + } + + if(intCause & 0x2) + { + vtuIntStatus->vtuIntCause |= GT_MISS_VIOLATION; + } + + if(intCause & 0x4) + { + vtuIntStatus->vtuIntCause |= GT_MEMBER_VIOLATION; + } + + vtuIntStatus->spid = entry.DBNum & 0xF; + vtuIntStatus->vid = entry.vid; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* vtuOperationPerform +* +* DESCRIPTION: +* This function is used by all VTU control functions, and is responsible +* to write the required operation into the VTU registers. +* +* INPUTS: +* vtuOp - The VTU operation bits to be written into the VTU +* operation register. +* DBNum - DBNum where the given vid belongs to +* vid - vlan id +* valid - valid bit +* vtuData - VTU Data with memberTag information +* +* OUTPUTS: +* DBNum - DBNum where the given vid belongs to +* vid - vlan id +* valid - valid bit +* vtuData - VTU Data with memberTag information +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ + +static GT_STATUS vtuOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_VTU_OPERATION vtuOp, + INOUT GT_U8 *valid, + INOUT GT_VTU_ENTRY *entry +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + + gtSemTake(dev,dev->vtuRegsSem,OS_WAIT_FOREVER); + + /* Wait until the VTU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /* Set the VTU data register */ + /* There is no need to setup data reg. on flush, get next, or service violation */ + if((vtuOp != FLUSH_ALL) && (vtuOp != GET_NEXT_ENTRY) && (vtuOp != SERVICE_VIOLATIONS)) + { + + /****************** VTU DATA 1 REG *******************/ + + /* get data and wirte to QD_REG_VTU_DATA1_REG (ports 0 to 3) */ + + data = (entry->vtuData.memberTagP[0] & 3) | + ((entry->vtuData.memberTagP[1] & 3)<<4) | + ((entry->vtuData.memberTagP[2] & 3)<<8); + + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[0] & 3)<<2) | + ((entry->vtuData.portStateP[1] & 3)<<6) | + ((entry->vtuData.portStateP[2] & 3)<<10); + + if(dev->maxPorts > 3) + { + data |= ((entry->vtuData.memberTagP[3] & 3)<<12) ; + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[3] & 3)<<14) ; + } + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA1_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /****************** VTU DATA 2 REG *******************/ + + /* get data and wirte to QD_REG_VTU_DATA2_REG (ports 4 to 7) */ + + if(dev->maxPorts > 4) + { + /* also need to set data register ports 4 to 6 */ + + data = (entry->vtuData.memberTagP[4] & 3) | + ((entry->vtuData.memberTagP[5] & 3) << 4); + + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[4] & 3) << 2) | + ((entry->vtuData.portStateP[5] & 3) << 6); + + if(dev->maxPorts > 6) + { + data |= ((entry->vtuData.memberTagP[6] & 3)<<8) ; + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[6] & 3)<<10) ; + } + + if(dev->maxPorts > 7) + { + data |= ((entry->vtuData.memberTagP[7] & 3)<<12) ; + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[7] & 3)<<14) ; + } + + if (IS_IN_DEV_GROUP(dev,DEV_VTU_EXT_INFO)) + { + if(entry->vidExInfo.useVIDFPri == GT_TRUE) + data |= ((1 << 15) | ((entry->vidExInfo.vidFPri & 0x7) << 12)); + if(entry->vidExInfo.useVIDQPri == GT_TRUE) + data |= ((1 << 11) | ((entry->vidExInfo.vidQPri & 0x3) << 9)); + if(entry->vidExInfo.vidNRateLimit == GT_TRUE) + data |= (1 << 8); + } + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA2_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + + /****************** VTU DATA 3 REG *******************/ + + /* get data and wirte to QD_REG_VTU_DATA3_REG (ports 8 to 10) */ + + if(dev->maxPorts > 7) + { + /* also need to set data register ports 8 to 9 */ + + data = (entry->vtuData.memberTagP[8] & 3) | + ((entry->vtuData.memberTagP[9] & 3) << 4); + + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= ((entry->vtuData.portStateP[8] & 3) << 2) | + ((entry->vtuData.portStateP[9] & 3) << 6); + + if(dev->maxPorts > 10) + { + data |= (entry->vtuData.memberTagP[10] & 3) << 8; + + if (IS_IN_DEV_GROUP(dev,DEV_802_1S)) + data |= (entry->vtuData.portStateP[10] & 3) << 10; + } + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + if(entry->vidPriOverride == GT_TRUE) + data |= ((1 << 15) | ((entry->vidPriority & 0x7) << 12)); + } + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA3_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + else if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + if(entry->vidPriOverride == GT_TRUE) + data = ((1 << 15) | ((entry->vidPriority & 0x7) << 12)); + else + data = 0; + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_DATA3_REG,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + } + + /* Set the VID register (QD_REG_VTU_VID_REG) */ + /* There is no need to setup VID reg. on flush and service violation */ + if((vtuOp != FLUSH_ALL) && (vtuOp != SERVICE_VIOLATIONS) ) + { + data= ( (entry->vid) & 0xFFF ) | ( (*valid) << 12 ); + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_VTU_VID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /* Set SID, FID, VIDPolicy, if it's Load operation */ + if((vtuOp == LOAD_PURGE_ENTRY) && (*valid == 1)) + { + if(IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + data= (entry->sid) & 0x3F; + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_STU_SID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + data = 0; + + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + if(IS_IN_DEV_GROUP(dev,DEV_POLICY)) + { + data= entry->vidPolicy << 12; + } + + data |= (entry->DBNum & 0xFFF); + + retVal = hwWriteGlobalReg(dev,(GT_U8)(QD_REG_VTU_FID_REG),data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + + } + + /* Start the VTU Operation by defining the DBNum, vtuOp and VTUBusy */ + /* + * Flush operation will skip the above two setup (for data and vid), and + * come to here directly + */ + + if(vtuOp == FLUSH_ALL) + data = (1 << 15) | (vtuOp << 12); + else + { + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + data = (1 << 15) | (vtuOp << 12); + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + /* Since DBNum is defined as GT_U8, it cannot be >= 256. */ + #if 0 + if(entry->DBNum >= 256) + { + gtSemGive(dev,dev->vtuRegsSem); + return GT_BAD_PARAM; + } + #endif + data = (1 << 15) | (vtuOp << 12) | ((entry->DBNum & 0xF0) << 4) | (entry->DBNum & 0x0F); + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + if(entry->DBNum >= 64) + { + gtSemGive(dev,dev->vtuRegsSem); + return GT_BAD_PARAM; + } + data = (1 << 15) | (vtuOp << 12) | ((entry->DBNum & 0x30) << 4) | (entry->DBNum & 0x0F); + } + else + { + if(entry->DBNum >= 16) + { + gtSemGive(dev,dev->vtuRegsSem); + return GT_BAD_PARAM; + } + data = (1 << 15) | (vtuOp << 12) | entry->DBNum; + } + } + + retVal = hwWriteGlobalReg(dev,QD_REG_VTU_OPERATION,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* only two operations need to go through the mess below to get some data + * after the operations - service violation and get next entry + */ + + /* If the operation is to service violation operation wait for the response */ + if(vtuOp == SERVICE_VIOLATIONS) + { + /* Wait until the VTU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /* get the Source Port ID that was involved in the violation */ + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,0,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + entry->DBNum = (GT_U8)(data & 0xF); + + /* get the VID that was involved in the violation */ + + retVal = hwReadGlobalReg(dev,QD_REG_VTU_VID_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* Get the vid - bits 0-11 */ + entry->vid = data & 0xFFF; + + + } /* end of service violations */ + + /* If the operation is a get next operation wait for the response */ + if(vtuOp == GET_NEXT_ENTRY) + { + entry->vidExInfo.useVIDFPri = GT_FALSE; + entry->vidExInfo.vidFPri = 0; + + entry->vidExInfo.useVIDQPri = GT_FALSE; + entry->vidExInfo.vidQPri = 0; + + entry->vidExInfo.vidNRateLimit = GT_FALSE; + + entry->sid = 0; + entry->vidPolicy = GT_FALSE; + + /* Wait until the VTU in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + } + + /****************** get the vid *******************/ + + retVal = hwReadGlobalReg(dev,QD_REG_VTU_VID_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* the vid is bits 0-11 */ + entry->vid = data & 0xFFF; + + /* the vid valid is bits 12 */ + *valid = (data >> 12) & 1; + + if (*valid == 0) + { + gtSemGive(dev,dev->vtuRegsSem); + return GT_OK; + } + + /****************** get the SID *******************/ + if(IS_IN_DEV_GROUP(dev,DEV_802_1S_STU)) + { + retVal = hwReadGlobalReg(dev,(GT_U8)(QD_REG_STU_SID_REG),&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + entry->sid = data & 0x3F; + } + + /****************** get the DBNum *******************/ + if(IS_IN_DEV_GROUP(dev,DEV_FID_REG)) + { + retVal = hwReadGlobalReg(dev,(GT_U8)(QD_REG_VTU_FID_REG),&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + if(IS_IN_DEV_GROUP(dev,DEV_POLICY)) + { + entry->vidPolicy = (data >> 12) & 0x1; + } + + entry->DBNum = data & 0xFFF; + + } + else + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,0,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + entry->DBNum = data & 0xF; + + if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_256)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,8,4,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + entry->DBNum |= ((data & 0xF) << 4); + } + else if (IS_IN_DEV_GROUP(dev,DEV_DBNUM_64)) + { + retVal = hwGetGlobalRegField(dev,QD_REG_VTU_OPERATION,8,2,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + entry->DBNum |= ((data & 0x3) << 4); + } + } + + + /****************** get the MemberTagP *******************/ + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA1_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + /* get data from data register for ports 0 to 2 */ + entry->vtuData.memberTagP[0] = data & 3 ; + entry->vtuData.memberTagP[1] = (data >> 4) & 3 ; + entry->vtuData.memberTagP[2] = (data >> 8) & 3 ; + entry->vtuData.portStateP[0] = (data >> 2) & 3 ; + entry->vtuData.portStateP[1] = (data >> 6) & 3 ; + entry->vtuData.portStateP[2] = (data >> 10) & 3 ; + + /****************** for the switch more than 3 ports *****************/ + + if(dev->maxPorts > 3) + { + /* fullsail has 3 ports, clippership has 7 prots */ + entry->vtuData.memberTagP[3] = (data >>12) & 3 ; + entry->vtuData.portStateP[3] = (data >>14) & 3 ; + + /* get data from data register for ports 4 to 6 */ + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA2_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + entry->vtuData.memberTagP[4] = data & 3 ; + entry->vtuData.memberTagP[5] = (data >> 4) & 3 ; + entry->vtuData.portStateP[4] = (data >> 2) & 3 ; + entry->vtuData.portStateP[5] = (data >> 6) & 3 ; + + if(dev->maxPorts > 6) + { + entry->vtuData.memberTagP[6] = (data >> 8) & 3 ; + entry->vtuData.portStateP[6] = (data >> 10) & 3 ; + } + + if (IS_IN_DEV_GROUP(dev,DEV_VTU_EXT_INFO)) + { + entry->vidPriOverride = 0; + entry->vidPriority = 0; + + entry->vidExInfo.useVIDFPri = (data & 0x8000)?GT_TRUE:GT_FALSE; + entry->vidExInfo.vidFPri = (data >> 12) & 0x7; + + entry->vidExInfo.useVIDQPri = (data & 0x0800)?GT_TRUE:GT_FALSE; + entry->vidExInfo.vidQPri = (data >> 9) & 0x3; + + entry->vidExInfo.vidNRateLimit = (data & 0x0100)?GT_TRUE:GT_FALSE; + } + } + /****************** upto 7 port switch *******************/ + + /****************** for the switch more than 7 ports *****************/ + + if(dev->maxPorts > 7) + { + /* fullsail has 3 ports, clippership has 7 prots */ + entry->vtuData.memberTagP[7] = (data >>12) & 3 ; + entry->vtuData.portStateP[7] = (data >>14) & 3 ; + + /* get data from data register for ports 4 to 6 */ + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA3_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + entry->vtuData.memberTagP[8] = data & 3 ; + entry->vtuData.memberTagP[9] = (data >> 4) & 3 ; + entry->vtuData.portStateP[8] = (data >> 2) & 3 ; + entry->vtuData.portStateP[9] = (data >> 6) & 3 ; + + if(dev->maxPorts > 10) + { + entry->vtuData.memberTagP[10] = (data >> 8) & 3 ; + entry->vtuData.portStateP[10] = (data >> 10) & 3 ; + } + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + if (data & 0x8000) + { + entry->vidPriOverride = GT_TRUE; + entry->vidPriority = (data >> 12) & 0x7; + } + else + { + entry->vidPriOverride = GT_FALSE; + entry->vidPriority = 0; + } + } + + } + else if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + /* get data from data register for ports 4 to 6 */ + retVal = hwReadGlobalReg(dev,QD_REG_VTU_DATA3_REG,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->vtuRegsSem); + return retVal; + } + + if (data & 0x8000) + { + entry->vidPriOverride = GT_TRUE; + entry->vidPriority = (data >> 12) & 0x7; + } + else + { + entry->vidPriOverride = GT_FALSE; + entry->vidPriority = 0; + } + } + + /****************** upto 11 ports switch *******************/ + + } /* end of get next entry */ + + gtSemGive(dev,dev->vtuRegsSem); + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtCCPVT.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtCCPVT.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtCCPVT.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtCCPVT.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,401 @@ +#include + +/******************************************************************************* +* gtCCPVT.c +* +* DESCRIPTION: +* API definitions for Cross Chip Port Vlan Data Table +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +*******************************************************************************/ + +#include +#include +#include +#include + +/****************************************************************************/ +/* Cross Chip Port Vlan operation function declaration. */ +/****************************************************************************/ +static GT_STATUS pvtOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PVT_OPERATION pvtOp, + INOUT GT_PVT_OP_DATA *opData +); + + +/******************************************************************************* +* gpvtInitialize +* +* DESCRIPTION: +* This routine initializes the PVT Table to all one's (initial state) +* +* INPUTS: +* None. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtInitialize +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; + GT_PVT_OPERATION op; + + DBG_INFO(("gpvtInitialize Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_CROSS_CHIP_PORT_VLAN)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Program Tuning register */ + op = PVT_INITIALIZE; + retVal = pvtOperationPerform(dev,op,NULL); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (pvtOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpvtWritePVTData +* +* DESCRIPTION: +* This routine write Cross Chip Port Vlan Data. +* Cross chip Port VLAN Data used as a bit mask to limit where cross chip +* frames can egress (in chip Port VLANs are masked using gvlnSetPortVlanPorts +* API). Cross chip frames are Forward frames that ingress a DSA or Ether +* Type DSA port (see gprtSetFrameMode API). Bit 0 is a mask for port 0, +* bit 1 for port 1, etc. When a port's mask bit is one, frames are allowed +* to egress that port on this device. When a port's mask bit is zero, +* frames are not allowed to egress that port on this device. +* +* The Cross Chip Port VLAN Table is accessed by ingressing frames based +* upon the original source port of the frame using the Forward frame's DSA tag +* fields Src_Dev, Src_Port/Src_Trunk and Src_Is_Trunk. The 1 entry of the 512 +* that is accessed by the frame is: +* If 5 Bit Port (in Global 2, offset 0x1D) = 0: +* If Src_Is_Trunk = 0 Src_Dev[4:0], Src_Port[3:0]119 +* If Src_Is_Trunk = 1 Device Number (global offset 0x1C), Src_Trunk[3:0] +* If 5 Bit Port (in Global 2, offset 0x1D) = 1: +* If Src_Is_Trunk = 0 Src_Dev[3:0], Src_Port[4:0]120 +* If Src_Is_Trunk = 1 Device Number[3:0], Src_Trunk[4:0] +* +* Cross chip port VLANs with Trunks are supported in the table where this +* device's entries would be stored (defined by this device's Device Number). +* This portion of the table is available for Trunk entries because this device's +* port VLAN mappings to ports inside this device are masked by the port's +* VLAN Table (see gvlnSetPortVlanPorts API). +* +* +* INPUTS: +* pvtPointer - pointer to the desired entry of PVT (0 ~ 511) +* pvtData - Cross Chip Port Vlan Data +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtWritePVTData +( + IN GT_QD_DEV *dev, + IN GT_U32 pvtPointer, + IN GT_U32 pvtData +) +{ + GT_STATUS retVal; + GT_PVT_OPERATION op; + GT_PVT_OP_DATA opData; + + DBG_INFO(("gpvtWritePVTData Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_CROSS_CHIP_PORT_VLAN)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given pointer is valid */ + if (pvtPointer > 0x1FF) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* check if the given pvtData is valid */ + if (pvtData >= (GT_U32)(1 << dev->maxPorts)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* Program Tuning register */ + op = PVT_WRITE; + opData.pvtAddr = pvtPointer; + + if((opData.pvtData = GT_LPORTVEC_2_PORTVEC(pvtData)) == GT_INVALID_PORT_VEC) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + + retVal = pvtOperationPerform(dev,op,&opData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (pvtOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpvtReadPVTData +* +* DESCRIPTION: +* This routine reads Cross Chip Port Vlan Data. +* Cross chip Port VLAN Data used as a bit mask to limit where cross chip +* frames can egress (in chip Port VLANs are masked using gvlnSetPortVlanPorts +* API). Cross chip frames are Forward frames that ingress a DSA or Ether +* Type DSA port (see gprtSetFrameMode API). Bit 0 is a mask for port 0, +* bit 1 for port 1, etc. When a port's mask bit is one, frames are allowed +* to egress that port on this device. When a port's mask bit is zero, +* frames are not allowed to egress that port on this device. +* +* The Cross Chip Port VLAN Table is accessed by ingressing frames based +* upon the original source port of the frame using the Forward frame's DSA tag +* fields Src_Dev, Src_Port/Src_Trunk and Src_Is_Trunk. The 1 entry of the 512 +* that is accessed by the frame is: +* If 5 Bit Port (in Global 2, offset 0x1D) = 0: +* If Src_Is_Trunk = 0 Src_Dev[4:0], Src_Port[3:0]119 +* If Src_Is_Trunk = 1 Device Number (global offset 0x1C), Src_Trunk[3:0] +* If 5 Bit Port (in Global 2, offset 0x1D) = 1: +* If Src_Is_Trunk = 0 Src_Dev[3:0], Src_Port[4:0]120 +* If Src_Is_Trunk = 1 Device Number[3:0], Src_Trunk[4:0] +* +* Cross chip port VLANs with Trunks are supported in the table where this +* device's entries would be stored (defined by this device's Device Number). +* This portion of the table is available for Trunk entries because this device's +* port VLAN mappings to ports inside this device are masked by the port's +* VLAN Table (see gvlnSetPortVlanPorts API). +* +* +* INPUTS: +* pvtPointer - pointer to the desired entry of PVT (0 ~ 511) +* +* OUTPUTS: +* pvtData - Cross Chip Port Vlan Data +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpvtReadPVTData +( + IN GT_QD_DEV *dev, + IN GT_U32 pvtPointer, + OUT GT_U32 *pvtData +) +{ + GT_STATUS retVal; + GT_PVT_OPERATION op; + GT_PVT_OP_DATA opData; + + DBG_INFO(("gpvtReadPVTData Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_CROSS_CHIP_PORT_VLAN)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given pointer is valid */ + if (pvtPointer > 0x1FF) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* Program Tuning register */ + op = PVT_READ; + opData.pvtAddr = pvtPointer; + retVal = pvtOperationPerform(dev,op,&opData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (pvtOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + opData.pvtData &= (1 << dev->maxPorts) - 1; + *pvtData = GT_PORTVEC_2_LPORTVEC(opData.pvtData); + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/****************************************************************************/ +/* Internal functions. */ +/****************************************************************************/ + + +/******************************************************************************* +* pvtOperationPerform +* +* DESCRIPTION: +* This function accesses PVT Table +* +* INPUTS: +* pvtOp - The pvt operation +* pvtData - address and data to be written into PVT +* +* OUTPUTS: +* pvtData - data read from PVT pointed by address +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pvtOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PVT_OPERATION pvtOp, + INOUT GT_PVT_OP_DATA *opData +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data; /* temporary Data storage */ + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* Wait until the pvt in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_PVT_ADDR,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } + + /* Set the PVT Operation register */ + switch (pvtOp) + { + case PVT_INITIALIZE: + data = (1 << 15) | (pvtOp << 12); + retVal = hwWriteGlobal2Reg(dev,QD_REG_PVT_ADDR,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + break; + + case PVT_WRITE: + data = (GT_U16)opData->pvtData; + retVal = hwWriteGlobal2Reg(dev,QD_REG_PVT_DATA,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + data = (GT_U16)((1 << 15) | (pvtOp << 12) | opData->pvtAddr); + retVal = hwWriteGlobal2Reg(dev,QD_REG_PVT_ADDR,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + break; + + case PVT_READ: + data = (GT_U16)((1 << 15) | (pvtOp << 12) | opData->pvtAddr); + retVal = hwWriteGlobal2Reg(dev,QD_REG_PVT_ADDR,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_PVT_ADDR,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } + + retVal = hwReadGlobal2Reg(dev,QD_REG_PVT_DATA,&data); + opData->pvtData = (GT_U32)data; + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + break; + + default: + + gtSemGive(dev,dev->tblRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->tblRegsSem); + return retVal; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtEvents.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtEvents.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtEvents.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtEvents.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,1489 @@ +#include + +/******************************************************************************** +* gtEvents.c +* +* DESCRIPTION: +* API definitions for system interrupt events handling. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 3 $ +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* eventSetActive +* +* DESCRIPTION: +* This routine enables/disables the receive of an hardware driven event. +* +* INPUTS: +* eventType - the event type. any combination of the folowing: +* GT_STATS_DONE, GT_VTU_PROB, GT_VTU_DONE, GT_ATU_FULL(or GT_ATU_PROB), +* GT_ATU_DONE, GT_PHY_INTERRUPT, GT_EE_INTERRUPT, GT_DEVICE_INT, +* and GT_AVB_INTERRUPT +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* Each switch device has its own set of event Types. Please refer to the +* device datasheet for the list of event types that the device supports. +* +*******************************************************************************/ +GT_STATUS eventSetActive +( + IN GT_QD_DEV *dev, + IN GT_U32 eventType +) +{ + GT_STATUS retVal; + GT_U16 data; + GT_U16 intMask; + GT_U8 len; + + DBG_INFO(("eventSetActive Called.\n")); + + data = (GT_U16) eventType; + len = 9; + + if ((IS_IN_DEV_GROUP(dev,DEV_EXTERNAL_PHY_ONLY)) || + (IS_IN_DEV_GROUP(dev,DEV_DEV_PHY_INTERRUPT))) + { + intMask = GT_NO_INTERNAL_PHY_INT_MASK; + } + else + { + intMask = GT_INT_MASK; + } + + if (!IS_IN_DEV_GROUP(dev,DEV_AVB_INTERRUPT)) + { + intMask &= ~GT_AVB_INT; + len = 8; + } + + if (!IS_IN_DEV_GROUP(dev,DEV_DEVICE_INTERRUPT)) + { + intMask &= ~GT_DEVICE_INT; + len = 7; + } + + + if(data & ~intMask) + { + DBG_INFO(("Invalid event type.\n")); + return GT_FAIL; + } + + /* Set the IntEn bit. */ + retVal = hwSetGlobalRegField(dev,QD_REG_GLOBAL_CONTROL,0,len,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* eventGetIntStatus +* +* DESCRIPTION: +* This routine reads an hardware driven event status. +* +* INPUTS: +* None. +* +* OUTPUTS: +* intCause - It provides the source of interrupt of the following: +* GT_STATS_DONE, GT_VTU_PROB, GT_VTU_DONE, GT_ATU_FULL, +* GT_ATU_DONE, GT_PHY_INTERRUPT, GT_EE_INTERRUPT, GT_DEVICE_INT, +* and GT_AVB_INTERRUPT +* For Gigabit Switch, GT_ATU_FULL is replaced with GT_ATU_PROB and +* if there is no internal phy, GT_PHY_INTERRUPT is not supported. +* +* RETURNS: +* GT_OK - read success. +* GT_FAIL - otherwise +* +* COMMENTS: +* Each switch device has its own set of event Types. Please refer to the +* device datasheet for the list of event types that the device supports. +* +*******************************************************************************/ +GT_STATUS eventGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_U16 *intCause +) +{ + GT_STATUS retVal; /* Function calls return value. */ + GT_U8 len; + + if (IS_IN_DEV_GROUP(dev,DEV_AVB_INTERRUPT)) + len = 9; + else if (IS_IN_DEV_GROUP(dev,DEV_DEVICE_INTERRUPT)) + len = 8; + else + len = 7; + + retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,0,len,intCause); + + return retVal; +} + + +/******************************************************************************* +* gvtuGetIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of VTU interrupt occured +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_MEMEBER_VIOLATION, +* GT_MISS_VIOLATION, +* GT_FULL_VIOLATION +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* FULL_VIOLATION is not supported by all switch devices. +* Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gvtuGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_VTU_INT_STATUS *vtuIntStatus +) +{ + GT_STATUS retVal; + + DBG_INFO(("gvtuGetIntStatus Called.\n")); + + /* check if device supports this feature */ + if((IS_VALID_API_CALL(dev,1, DEV_802_1Q)) != GT_OK ) + return GT_FAIL; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + retVal = gvtuGetViolation2(dev,vtuIntStatus); + } + else if (IS_IN_DEV_GROUP(dev,DEV_ENHANCED_FE_SWITCH)) + { + retVal = gvtuGetViolation3(dev,vtuIntStatus); + } + else + { + retVal = gvtuGetViolation(dev,vtuIntStatus); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gatuGetIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of ATU interrupt occured +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_AGE_OUT_VIOLATION, +* GT_AGE_VIOLATION, +* GT_MEMEBER_VIOLATION, +* GT_MISS_VIOLATION, +* GT_FULL_VIOLATION +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gatuGetIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_ATU_INT_STATUS *atuIntStatus +) +{ + GT_STATUS retVal; + + DBG_INFO(("gatuGetIntStatus Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gatuGetViolation(dev,atuIntStatus); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* geventGetDevIntStatus +* +* DESCRIPTION: +* Check to see which device interrupts (WatchDog, JamLimit, Duplex Mismatch, +* SERDES Link Int, and Phy Int) have occurred. +* +* INPUTS: +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_DEV_INT_WATCHDOG, +* GT_DEV_INT_JAMLIMIT, +* GT_DEV_INT_DUPLEX_MISMATCH, +* GT_DEV_INT_SERDES_LINK +* GT_DEV_INT_PHY +* port - logical port where GT_DEV_INT_DUPLEX_MISMATCH occurred. +* valid only if GT_DEV_INT_DUPLEX_MISMATCH is set in intType. +* linkInt - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt is +* asserted. It's in vector format, Bit 10 is for port 10, +* Bit 9 is for port 9, etc. +* valid only if GT_DEV_INT_SERDES_LINK bit is set in intType. +* These bits are only valid of the port that is in 1000Base-X mode. +* phyInt - port list where GT_DEV_INT_PHY interrupt is asserted. +* It's in vector format, Bit 0 is for port 0, Bit 1 is for port 1, etc. +* valid only if GT_DEV_INT_PHY bit is set in intType. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS geventGetDevIntStatus +( + IN GT_QD_DEV *dev, + OUT GT_DEV_INT_STATUS *devIntStatus +) +{ + GT_STATUS retVal; + GT_U16 data, hwPort; + + DBG_INFO(("geventGetDevIntStatus Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_DEVICE_INTERRUPT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + devIntStatus->devIntCause = 0; + + retVal = hwReadGlobal2Reg(dev,QD_REG_DEVINT_SOURCE,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + /* check SERDES Link Int and Phy Int, if applicable */ + if (IS_IN_DEV_GROUP(dev,DEV_DEVICE_INT_TYPE1)) + { + /* check SERDES Link Int */ + if (data & (0x7 << 8)) + { + devIntStatus->devIntCause |= GT_DEV_INT_SERDES_LINK; + devIntStatus->linkInt = GT_PORTVEC_2_LPORTVEC((data & (7<<8))); + } + } + else /* DEV_DEVICE_INT_TYPE2 */ + { + if (data & (0x3 << 11)) + { + devIntStatus->devIntCause |= GT_DEV_INT_SERDES_LINK; + devIntStatus->linkInt = GT_PORTVEC_2_LPORTVEC((data & (0x3 << 11)) >> 7); + } + + if (data & 0x1F) + { + devIntStatus->devIntCause |= GT_DEV_INT_PHY; + devIntStatus->phyInt = GT_PORTVEC_2_LPORTVEC((data & 0x1F)); + } + } + + if (data & QD_DEV_INT_DUPLEX_MISMATCH) + { + devIntStatus->devIntCause |= GT_DEV_INT_DUPLEX_MISMATCH; + + /* read port that causes the interrupt */ + retVal = hwGetGlobal2RegField(dev, QD_REG_WD_CONTROL, 12, 4, &hwPort); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + /* re-arm the interrupt event */ + retVal = hwSetGlobal2RegField(dev, QD_REG_WD_CONTROL, 12, 4, 0xF); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + devIntStatus->port = GT_PORT_2_LPORT((GT_U8)hwPort); + } + + if (data & QD_DEV_INT_WATCHDOG) + { + devIntStatus->devIntCause |= GT_DEV_INT_WATCHDOG; + } + + if (data & QD_DEV_INT_JAMLIMIT) + { + devIntStatus->devIntCause |= GT_DEV_INT_JAMLIMIT; + } + + return retVal; +} + + +/******************************************************************************* +* geventSetAgeIntEn +* +* DESCRIPTION: +* This routine enables/disables Age Interrupt for a port. +* When it's enabled, ATU Age Violation interrupts from this port are enabled. +* An Age Violation will occur anytime a port is Locked(gprtSetLockedPort) +* and the ingressing frame's SA is contained in the ATU as a non-Static +* entry with a EntryState less than 0x4. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetAgeIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventSetAgeIntEn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_BASED_AGE_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Age Interrupt Enable Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,11,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* geventGetAgeIntEn +* +* DESCRIPTION: +* This routine gets Age Interrupt Enable for the port. +* When it's enabled, ATU Age Violation interrupts from this port are enabled. +* An Age Violation will occur anytime a port is Locked(gprtSetLockedPort) +* and the ingressing frame's SA is contained in the ATU as a non-Static +* entry with a EntryState less than 0x4. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetAgeIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventGetAgeIntEn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_BASED_AGE_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Age Interrupt Enable Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,11,1,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *mode); + + return retVal; +} + + +/******************************************************************************* +* geventSetAgeOutIntEn +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Age Out Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetAgeOutIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventSetAgeOutIntEn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Age Out Interrupt Enable Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,14,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* geventGetAgeOutIntEn +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_TRUE, if Age Out Interrupt is enabled +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetAgeOutIntEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventGetAgeOutIntEn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Age Out Interrupt Enable Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,14,1,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *mode); + + return retVal; +} + + +/******************************************************************************* +* geventSetOverLimitInt +* +* DESCRIPTION: +* This routine enables/disables Over Limit Interrupt for a port. +* If it's enabled, an ATU Miss violation will be generated when port auto +* learn reached the limit(refer to gfdbGetPortAtuLimitReached API). +* +* INPUTS: +* port - the logical port number +* mode - GT_TRUE to enable Over Limit Interrupt, +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventSetOverLimitInt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventSetOverLimitInt Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Over Limit Interrupt Enable Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 13, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* geventGetOverLimitInt +* +* DESCRIPTION: +* This routine enables/disables Over Limit Interrupt for a port. +* If it's enabled, an ATU Miss violation will be generated when port auto +* learn reached the limit(refer to gfdbSetPortAtuLearnLimit API). +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_TRUE to enable Over Limit Interrupt, +* GT_FALUSE to disable +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS geventGetOverLimitInt +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventGetOverLimitInt Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Set Over Limit Interrupt Enable Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 13, 1, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *mode); + + return retVal; +} + +/******************************************************************************* +* geventGetPortAtuLimitReached +* +* DESCRIPTION: +* This routine checks if learn limit has been reached. +* When it reached, the port can no longer auto learn any more MAC addresses +* because the address learn limit set on this port has been reached. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* limit - GT_TRUE, if limit has been reached +* GT_FALSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* +*******************************************************************************/ +GT_STATUS geventGetPortAtuLimitReached +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL *limit +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("geventGetPortAtuLimitReached Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Check device if this feature is supported. */ + if (!IS_IN_DEV_GROUP(dev,DEV_ATU_LIMIT)) + { + return GT_NOT_SUPPORTED; + } + + /* Get the LimitReached bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ATU_CONTROL, 14, 1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data, *limit); + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* eventSetDevInt +* +* DESCRIPTION: +* Device Interrupt. +* The following device interrupts are supported: +* GT_DEV_INT_WATCHDOG - +* WatchDog event interrupt (WatchDog event can be configured with +* gwdSetEvent API) +* GT_DEV_INT_JAMLIMIT - +* any of the ports detect an Ingress Jam Limit violation +* (see gprtSetPauseLimitIn API) +* GT_DEV_INT_DUPLEX_MISMATCH - +* any of the ports detect a duplex mismatch (i.e., the local port is +* in half duplex mode while the link partner is in full duplex mode) +* GT_DEV_INT_SERDES_LINK - +* SERDES link change interrupt. +* An interrupt occurs when a SERDES port changes link status +* (link up or link down) +* GT_DEV_INT_PHY - Phy interrupt. +* +* If any of the above events is enabled, GT_DEVICE_INT interrupt will +* be asserted by the enabled event when GT_DEV_INT is enabled with +* eventSetActive API. +* +* INPUTS: +* devInt - GT_DEV_INT +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS eventSetDevInt +( + IN GT_QD_DEV *dev, + IN GT_DEV_EVENT *devInt +) +{ + GT_U16 data, event; + GT_U16 serdesMask, phyMask, mask; + GT_U32 pList; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("eventSetDevInt Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_DEVICE_INTERRUPT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + event = (GT_U16)devInt->event; + + if (IS_IN_DEV_GROUP(dev,DEV_DEVICE_INT_TYPE1)) + { + serdesMask = mask = 7 << 8; /* SERDES Port List */ + phyMask = 0; + } + else + { + serdesMask = mask = 3 << 11; /* SERDES Port List */ + mask |= 0x1F; /* Phy list */ + phyMask = 0x1F; + } + mask |= QD_DEV_INT_WATCHDOG | QD_DEV_INT_JAMLIMIT | QD_DEV_INT_DUPLEX_MISMATCH; + + data = 0; + + if (event & GT_DEV_INT_SERDES_LINK) + { + /* check for valid SERDES Port List */ + if (IS_IN_DEV_GROUP(dev,DEV_DEVICE_INT_TYPE1)) + { + pList = GT_LPORTVEC_2_PORTVEC(devInt->portList); + if ((GT_U16)pList & (~serdesMask)) + { + DBG_INFO(("GT_BAD_PARAM portList\n")); + return GT_BAD_PARAM; + } + data = (GT_U16)pList; + } + else + { + pList = GT_LPORTVEC_2_PORTVEC(devInt->portList); + pList <<= 7; + if ((GT_U16)pList & (~serdesMask)) + { + DBG_INFO(("GT_BAD_PARAM portList\n")); + return GT_BAD_PARAM; + } + data = (GT_U16)pList; + } + } + + if (event & GT_DEV_INT_PHY) + { + /* check for valid Phy List */ + if (IS_IN_DEV_GROUP(dev,DEV_DEVICE_INT_TYPE1)) + { + DBG_INFO(("GT_BAD_PARAM: PHY Int not supported.\n")); + return GT_BAD_PARAM; + } + else + { + pList = GT_LPORTVEC_2_PORTVEC(devInt->phyList); + if ((GT_U16)pList & (~phyMask)) + { + DBG_INFO(("GT_BAD_PARAM phyList\n")); + return GT_BAD_PARAM; + } + + data |= (GT_U16)pList; + } + } + + if (event & GT_DEV_INT_WATCHDOG) + { + data |= QD_DEV_INT_WATCHDOG; + } + + if (event & GT_DEV_INT_JAMLIMIT) + { + data |= QD_DEV_INT_JAMLIMIT; + } + + if (event & GT_DEV_INT_DUPLEX_MISMATCH) + { + data |= QD_DEV_INT_DUPLEX_MISMATCH; + } + + if (data & (~mask)) + { + DBG_INFO(("GT_BAD_PARAM portList\n")); + return GT_BAD_PARAM; + } + + if (data & GT_DEV_INT_DUPLEX_MISMATCH) + { + retVal = hwSetGlobal2RegField(dev, QD_REG_WD_CONTROL, 12, 4, 0xF); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + + /* Set the related bit. */ + retVal = hwSetGlobal2RegBits(dev,QD_REG_DEVINT_MASK, mask, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gwdSetEvent +* +* DESCRIPTION: +* Watch Dog Event. +* The following Watch Dog events are supported: +* GT_WD_QC - Queue Controller Watch Dog enable. +* When enabled, the QC's watch dog circuit checks for link +* list errors and any errors found in the QC. +* GT_WD_EGRESS - Egress Watch Dog enable. +* When enabled, each port's egress circuit checks for problems +* between the port and the Queue Controller. +* GT_WD_FORCE - Force a Watch Dog event. +* +* If any of the above events is enabled, GT_DEVICE_INT interrupt will +* be asserted by the enabled WatchDog event when GT_DEV_INT_WATCHDOG is +* enabled with eventSetDevActive API and GT_DEV_INT is enabled with +* eventSetActive API. +* +* INPUTS: +* wdEvent - Watch Dog Events +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetEvent +( + IN GT_QD_DEV *dev, + IN GT_U32 wdEvent +) +{ + GT_U16 data, mask; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdSetEvent Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + mask = (1 << 5) | (1 << 3) | (1 << 2); + data = 0; + + if (wdEvent & GT_WD_QC) + { + data |= (1 << 5); + } + + if (wdEvent & GT_WD_EGRESS) + { + data |= (1 << 3); + } + + if (wdEvent & GT_WD_FORCE) + { + data |= (1 << 2); + } + + /* Set the related bit. */ + retVal = hwSetGlobal2RegBits(dev,QD_REG_WD_CONTROL, mask, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gwdSetSWResetOnWD +* +* DESCRIPTION: +* SWReset on Watch Dog Event. +* When this feature is enabled, any enabled watch dog event (gwdSetEvent API) +* will automatically reset the switch core's datapath just as if gsysSwReset +* API is called. +* +* The Watch Dog History (gwdGetHistory API) won't be cleared by this +* automatic SWReset. This allows the user to know if any watch dog event +* ever occurred even if the swich is configured to automatically recover +* from a watch dog. +* +* When this feature is disabled, enabled watch dog events will not cause a +* SWReset. +* +* INPUTS: +* en - GT_TRUE to enable SWReset on WD +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetSWResetOnWD +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdSetSWResetOnWD Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(en,data); + + /* Set the related bit. */ + retVal = hwSetGlobal2RegField(dev,QD_REG_WD_CONTROL, 0, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gwdGetSWResetOnWD +* +* DESCRIPTION: +* SWReset on Watch Dog Event. +* When this feature is enabled, any enabled watch dog event (gwdSetEvent API) +* will automatically reset the switch core's datapath just as if gsysSwReset +* API is called. +* +* The Watch Dog History (gwdGetHistory API) won't be cleared by this +* automatic SWReset. This allows the user to know if any watch dog event +* ever occurred even if the swich is configured to automatically recover +* from a watch dog. +* +* When this feature is disabled, enabled watch dog events will not cause a +* SWReset. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE, if SWReset on WD is enabled +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetSWResetOnWD +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdSetSWResetOnWD Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the related bit. */ + retVal = hwGetGlobal2RegField(dev,QD_REG_WD_CONTROL, 0, 1, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *en); + + return retVal; +} + + +/******************************************************************************* +* gwdGetHistory +* +* DESCRIPTION: +* This routine retrieves Watch Dog history. They are +* +* wdEvent - +* When it's set to GT_TRUE, some enabled Watch Dog event occurred. +* The following events are possible: +* QC WatchDog Event (GT_WD_QC) +* Egress WatchDog Event (GT_WD_EGRESS) +* Forced WatchDog Event (GT_WD_FORCE) +* egressEvent - +* If any port's egress logic detects an egress watch dog issue, +* this field is set to GT_TRUE, regardless of the enabling GT_WD_EGRESS +* event. +* +* INPUTS: +* None. +* +* OUTPUTS: +* history - GT_WD_EVENT_HISTORY structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetHistory +( + IN GT_QD_DEV *dev, + OUT GT_WD_EVENT_HISTORY *history +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdSetSWResetOnWD Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the related bit. */ + retVal = hwReadGlobal2Reg(dev,QD_REG_WD_CONTROL,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if (data & (1 << 4)) + { + history->egressEvent = GT_TRUE; + } + else + { + history->egressEvent = GT_FALSE; + } + + if (data & (1 << 1)) + { + history->wdEvent = GT_TRUE; + } + else + { + history->wdEvent = GT_FALSE; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gwdSetRMUTimeOut +* +* DESCRIPTION: +* Remote Management Timeout. When this bit is set to a one the Remote +* Management Unit(RMU) will timeout on Wait on Bit commands. If the bit that +* is being tested has not gone to the specified value after 1 sec. has elapsed +* the Wait on Bit command will be terminated and the Response frame will be +* sent without any further processing. +* +* When this bit is cleared to a zero the Wait on Bit command will wait +* until the bit that is being tested has changed to the specified value. +* +* INPUTS: +* en - GT_TRUE to enable RMU Timeout +* GT_FALUSE to disable +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdSetRMUTimeOut +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdSetRMUTimeOut Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(en,data); + + /* Set the related bit. */ + retVal = hwSetGlobal2RegField(dev,QD_REG_WD_CONTROL, 6, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gwdGetRMUTimeOut +* +* DESCRIPTION: +* Remote Management Timeout. When this bit is set to a one the Remote +* Management Unit(RMU) will timeout on Wait on Bit commands. If the bit that +* is being tested has not gone to the specified value after 1 sec. has elapsed +* the Wait on Bit command will be terminated and the Response frame will be +* sent without any further processing. +* +* When this bit is cleared to a zero the Wait on Bit command will wait +* until the bit that is being tested has changed to the specified value. +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - GT_TRUE to enable RMU Timeout +* GT_FALUSE, otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetRMUTimeOut +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdGetRMUTimeOut Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the related bit. */ + retVal = hwGetGlobal2RegField(dev,QD_REG_WD_CONTROL, 6, 1, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *en); + + return retVal; +} + + +/******************************************************************************* +* gwdGetEgressWDEvent +* +* DESCRIPTION: +* If any port's egress logic detects an egress watch dog issue, this bit +* will be set to a one, regardless of the setting of the GT_WD_EGRESS in +* gwdSetEvent function. +* +* INPUTS: +* None. +* +* OUTPUTS: +* event - GT_TRUE, if egress logic has detected any egress watch dog issue +* GT_FALUSE, otherwise +* +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gwdGetEgressWDEvent +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *event +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gwdGetEgressWDEvent Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_WATCHDOG_EVENT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the related bit. */ + retVal = hwGetGlobal2RegField(dev,QD_REG_WD_CONTROL, 7, 1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *event); + + return retVal; +} + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtMisc.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtMisc.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtMisc.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtMisc.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,2027 @@ +#include + +/******************************************************************************* +* gtMisc.c +* +* DESCRIPTION: +* API definitions for Ip Mapping Table +* EEPROM access +* Scratch and Misc Control +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +*******************************************************************************/ + +#include +#include +#include +#include + + +/******************************************************************************* +* gsysSetUseIpMappingTable +* +* DESCRIPTION: +* This API set to use IP Frame Priorities from this table. +* Set GT_TRUE: The IP_FPRI data in this table is used as the frame’s +* initial IP_FPRI use Ip Mappingg table priorities. +* Set GT_FALSE: The IP_FPRI data in this table is ignored. Instead the +* frame’s initial IP_FPRI is generated by using the frame’s IP_QPRI +* as the IP_FPRI’s upper two bits, and the IP_FPRI’s lowest bit comes +* from bit 0 of the frame’s source port’s Default PRI (Port offset 0x07). +* +* INPUTS: +* en - [GT_TRUE] / [GT_FALSE] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetUseIpMappingTable +( + IN GT_QD_DEV *dev, + IN GT_BOOL en +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + + DBG_INFO(("gsysSetUseIpMappingTable Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_IP_MAPPING_TABLE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = (en==GT_TRUE)?1:0; + + retVal = hwSetGlobalRegField(dev,QD_REG_IP_MAPPING_TABLE,14,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + +/******************************************************************************* +* gsysGetUseIpMappingTable +* +* DESCRIPTION: +* This API get to use IP Frame Priorities from this table. +* Set GT_TRUE: The IP_FPRI data in this table is used as the frame’s +* initial IP_FPRI use Ip Mappingg table priorities. +* Set GT_FALSE: The IP_FPRI data in this table is ignored. Instead the +* frame’s initial IP_FPRI is generated by using the frame’s IP_QPRI +* as the IP_FPRI’s upper two bits, and the IP_FPRI’s lowest bit comes +* from bit 0 of the frame’s source port’s Default PRI (Port offset 0x07). +* +* INPUTS: +* None. +* +* OUTPUTS: +* en - [GT_TRUE] / [GT_FALSE] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetUseIpMappingTable +( + IN GT_QD_DEV *dev, + IN GT_BOOL *en +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + + DBG_INFO(("gsysGetUseIpMappingTable Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_IP_MAPPING_TABLE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + + retVal = hwGetGlobalRegField(dev,QD_REG_IP_MAPPING_TABLE,14,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *en= (data==1)?GT_TRUE:GT_FALSE; + + return GT_OK; +} + +/******************************************************************************* +* gsysSetIpMappingPrio +* +* DESCRIPTION: +* Set IPv4 and IPv6 Frame Priority Mapping, and +* IPv4 and IPv6 Queue Priority Mapping. +* The ipFpri value is used as the frames initial FPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri (Port offset 0x04) +* is configured to use IP FPri’s. +* The ipQpri value is used as the frame’s initial QPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri and TagIfBoth +* registers (Port offset 0x04) are configured to use IP QPri’s. +* +* INPUTS: +* point - Pointer to the Ip Mapping Table. +* 0 - 0x3f; +* ipFpri - The value is 0 - 7 +* ipQpri - The value is 0 - 3. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetIpMappingPrio +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + IN GT_U8 ipFpri, + IN GT_U8 ipQpri +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + + DBG_INFO(("gsysSetIpMappingPrio Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_IP_MAPPING_TABLE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((point>0x3f)||(ipFpri>7)||(ipQpri>3)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* Wait until the Scratch and Misc control is ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobalRegField(dev,QD_REG_IP_MAPPING_TABLE,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } + + data = (((ipFpri&7)<<4) | (ipQpri&3)); + data |= ((GT_U16)((1 << 15) | (point << 8))); + + retVal = hwWriteGlobalReg(dev, QD_REG_IP_MAPPING_TABLE, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + + + gtSemGive(dev,dev->tblRegsSem); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + +/******************************************************************************* +* gsysGetIpMappingPrio +* +* DESCRIPTION: +* get IPv4 and IPv6 Frame Priority Mapping, and +* IPv4 and IPv6 Queue Priority Mapping. +* The ipFpri value is used as the frames initial FPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri (Port offset 0x04) +* is configured to use IP FPri’s. +* The ipQpri value is used as the frame’s initial QPRI when the frame is +* an IPv4 or an IPv6 frame, and the port’s InitialPri and TagIfBoth +* registers (Port offset 0x04) are configured to use IP QPri’s. +* +* INPUTS: +* point - Pointer to the Ip Mapping Table. +* 0 - 0x3f; +* +* OUTPUTS: +* ipFpri - The value is 0 - 7 +* ipQpri - The value is 0 - 3. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetIpMappingPrio +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + OUT GT_U8 *ipFpri, + OUT GT_U8 *ipQpri +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + + DBG_INFO(("gsysGetIpMappingPrio Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_IP_MAPPING_TABLE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (point > 0x3f) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + do { + retVal = hwReadGlobalReg(dev, QD_REG_IP_MAPPING_TABLE, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } while (data&0x8000); + + + *ipFpri = (data >> 4) & 7; + *ipQpri = (data) & 3; + + gtSemGive(dev,dev->tblRegsSem); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + + +/******************************************************************************* +* eepromOperationPerform +* +* DESCRIPTION: +* This function accesses EEPROM Command Register and Data Register. +* The device supports the following EEPROM +* operations +* GT_EEPROM_NO_OP = No Operation +* GT_EEPROM_WRITE_DATA = Write EEPROM at Addr. +* GT_EEPROM_READ_DATA = Read EEPROM from Addr. +* GT_EEPROM_RESTART = Restart Register Loader execution at Addr +* (eepromData = don’t care in this case) +* GT_EEPROM_HALT = Halt (stop executing the EEPROM if its not already +* stopped) +* +* INPUTS: +* eepromOp - EEPROM Opcode. +* eepromData - Data to be written to the EEPROM +* +* OUTPUTS: +* eepromData - Data that was read back from the EEPROM. +* +Command register above. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* GT_BAD_PARAM - if input parameters are beyond range. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS eepromOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_EEPROM_OPERATION eepromOp, + INOUT GT_EEPROM_OP_DATA *opData +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data; /* temporary Data storage */ + DBG_INFO(("eepromOperationPerform Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_EEPROM)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (eepromOp>GT_EEPROM_HALT) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->eepromRegsSem,OS_WAIT_FOREVER); + + + /* Wait until the eeprom in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_EEPROM_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + } + + + /* Set the EEPROM Operation register */ + switch (eepromOp) + { + case GT_EEPROM_WRITE_DATA: + retVal = hwGetGlobal2RegField(dev,QD_REG_EEPROM_COMMAND,10,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + if (data==0) + { + gtSemGive(dev,dev->eepromRegsSem); + DBG_INFO(("EEPROM is not writablen")); + return GT_FAIL; + } + + retVal = hwGetGlobal2RegField(dev,QD_REG_EEPROM_COMMAND,11,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + if (data==1) + { + gtSemGive(dev,dev->eepromRegsSem); + DBG_INFO(("EEPROM Loader is running")); + return GT_FAIL; + } + + data = (GT_U16)opData->eepromData; + retVal = hwWriteGlobal2Reg(dev,QD_REG_EEPROM_DATA,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + + data = (GT_U16)((1 << 15) | (GT_EEPROM_WRITE_DATA << 12) | + (opData->eepromAddr & 0xFF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_EEPROM_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + break; + + case GT_EEPROM_READ_DATA: + retVal = hwGetGlobal2RegField(dev,QD_REG_EEPROM_COMMAND,11,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + if (data==1) + { + gtSemGive(dev,dev->eepromRegsSem); + DBG_INFO(("EEPROM Loader is running")); + return GT_FAIL; + } + + data = (GT_U16)((1 << 15) | (GT_EEPROM_READ_DATA << 12) | + (opData->eepromAddr & 0xFF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_EEPROM_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + + + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_EEPROM_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + } + + + retVal = hwReadGlobal2Reg(dev,QD_REG_EEPROM_DATA,&data); + opData->eepromData = (GT_U32)data; + + break; + + case GT_EEPROM_RESTART: + data = (GT_U16)((1 << 15) | (GT_EEPROM_RESTART << 12) | + (opData->eepromAddr & 0xFF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_EEPROM_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + + + break; + + case GT_EEPROM_HALT: + data = (GT_U16)((1 << 15) | (GT_EEPROM_HALT << 12) | + (opData->eepromAddr & 0xFF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_EEPROM_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->eepromRegsSem); + return retVal; + } + + break; + default: + gtSemGive(dev,dev->eepromRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->eepromRegsSem); + return GT_OK; +} + + +/******************************************************************************* +* gsysReadEeprom +* +* DESCRIPTION: +* Read EEPROM from EEPROM’s address where the EEOp is performed. +* +* INPUTS: +* addr - EEPROM Address. +* +* OUTPUTS: +* data - Data that was read back from the EEPROM. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysReadEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr, + OUT GT_U8 *data +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_EEPROM_OPERATION eepromOp; + GT_EEPROM_OP_DATA opData; + + eepromOp = GT_EEPROM_READ_DATA; + opData.eepromAddr = addr; + + retVal = eepromOperationPerform(dev,eepromOp,&opData); + if(retVal != GT_OK) + { + return retVal; + } + *data = (GT_U8)opData.eepromData; + return GT_OK; + +} + +/******************************************************************************* +* gsysWriteEeprom +* +* DESCRIPTION: +* Write EEPROM at the EEPROM’s address where the EEOp is performed. + +* +* INPUTS: +* addr - EEPROM Address. +* data - Data to be written to the EEPROM +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysWriteEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr, + IN GT_U8 data +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_EEPROM_OPERATION eepromOp; + GT_EEPROM_OP_DATA opData; + + eepromOp = GT_EEPROM_WRITE_DATA; + opData.eepromAddr = addr; + opData.eepromData = data; + + retVal = eepromOperationPerform(dev,eepromOp,&opData); + if(retVal != GT_OK) + { + return retVal; + } + return GT_OK; + +} + +/******************************************************************************* +* gsysRestartEeprom +* +* DESCRIPTION: +* Restart Register Loader execution at the EEPROM’s address where the EEOp +* is performed +* +* INPUTS: +* addr - EEPROM Address. . +* +* OUTPUTS: +* none +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysRestartEeprom +( + IN GT_QD_DEV *dev, + IN GT_U32 addr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_EEPROM_OPERATION eepromOp; + GT_EEPROM_OP_DATA opData; + + eepromOp = GT_EEPROM_RESTART; + opData.eepromAddr = addr; + + retVal = eepromOperationPerform(dev,eepromOp,&opData); + if(retVal != GT_OK) + { + return retVal; + } + return GT_OK; + +} + +/******************************************************************************* +* gsysHaltEeprom +* +* DESCRIPTION: +* Halt (stop executing the EEPROM if its not already stopped) + +* +* INPUTS: +* none . +* +* OUTPUTS: +* none +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysHaltEeprom +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_EEPROM_OPERATION eepromOp; + GT_EEPROM_OP_DATA opData; + + eepromOp = GT_EEPROM_HALT; + + retVal = eepromOperationPerform(dev,eepromOp, &opData); + if(retVal != GT_OK) + { + return retVal; + } + return GT_OK; + +} + +/******************************************************************************* +* gsysGetStEeprom +* +* DESCRIPTION: +* Get EEPROM status. They are Register Loader Running status and EEPROM +* Write Enable status +* runSt is GT_TRUE: Register Loader Running, whenever the register loader +* is busy executing the instructions contained in the EEPROM. +* writeEn is GT_TRUE: EEPROM Write Enable, that indicates that writing to +* the EEPROM is possible. +* writeEn is GT_FALSE: the Write EEPROM EEOp above will not do anything. +* This reflects the value of the EE_WE configuration pin after Reset. +* +* INPUTS: +* none . +* +* OUTPUTS: +* runSt - [GT_TRUE] / [GT_FALSE) +* writeEn - [GT_TRUE] / [GT_FALSE) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetStEeprom +( + IN GT_QD_DEV *dev, + OUT GT_BOOL *writeEn, + OUT GT_BOOL *runSt +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* temporary Data storage */ + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_EEPROM)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = hwReadGlobal2Reg(dev,QD_REG_EEPROM_COMMAND, &data); + if(retVal != GT_OK) + { + return retVal; + } + + + *runSt = (data>_EEPROM_OP_ST_RUNNING_MASK)?GT_TRUE:GT_FALSE; + *writeEn = (data>_EEPROM_OP_ST_WRITE_EN_MASK)?GT_TRUE:GT_FALSE; + + return GT_OK; + +} + +/******************************************************************************* +* gsysSetScratchMiscCtrl +* +* DESCRIPTION: +* Set Scratch and Misc control data to the Pointer to the Scratch and Misc. +* Control register. +* Scratch Byte 0 +* Scratch Byte 1 +* GPIO Configuration +* Reserved for future use +* GPIO Direction +* GPIO Data +* CONFIG Data 0 +* CONFIG Data 1 +* CONFIG Data 2 +* CONFIG Data 3 +* SyncE & TAICLK125’s Drive +* P5’s & CLK125’s Clock Drive +* P6’s Clock Drive +* EEPROM Pad drive +* +* INPUTS: +* point - Pointer to the Scratch and Misc. Control register. +* data - Scratch and Misc. Control data written to the register +* pointed to by the point above. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetScratchMiscCtrl +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + IN GT_U8 data +) +{ + GT_STATUS retVal; /* Functions return value. */ + IN GT_U16 tmpData; + + if (point > GT_SCRAT_MISC_REG_MAX) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + if ((point>0x7f)||(data>0xff)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* program QoS Weight Table, 4 sequences at a time */ + + /* Wait until the Scratch and Misc control is ready. */ + tmpData = 1; + while(tmpData == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_SCRATCH_MISC,15,1,&tmpData); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } + + tmpData = (GT_U16)((1 << 15) | (point << 8) | data); + + retVal = hwWriteGlobal2Reg(dev, QD_REG_SCRATCH_MISC, tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + + + gtSemGive(dev,dev->tblRegsSem); + + return retVal; + +} + + +/******************************************************************************* +* gsysGetScratchMiscCtrl +* +* DESCRIPTION: +* Get Scratch and Misc control data to the Pointer to the Scratch and Misc. +* Control register. +* Scratch Byte 0 +* Scratch Byte 1 +* GPIO Configuration +* Reserved for future use +* GPIO Direction +* GPIO Data +* CONFIG Data 0 +* CONFIG Data 1 +* CONFIG Data 2 +* CONFIG Data 3 +* SyncE & TAICLK125’s Drive +* P5’s & CLK125’s Clock Drive +* P6’s Clock Drive +* EEPROM Pad drive + +* +* INPUTS: +* point - Pointer to the Scratch and Misc. Control register. +* +* OUTPUTS: +* data - Scratch and Misc. Control data read from the register +* pointed to by the point above. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetScratchMiscCtrl +( + IN GT_QD_DEV *dev, + IN GT_U32 point, + OUT GT_U8 *data +) +{ + GT_STATUS retVal; /* Functions return value. */ + OUT GT_U16 tmpData; + + if (point > GT_SCRAT_MISC_REG_MAX) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + if (point>0x7f) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* program QoS Weight Table, 4 sequences at a time */ + + do { + retVal = hwReadGlobal2Reg(dev, QD_REG_SCRATCH_MISC, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + } while (tmpData&0x8000); + + *data = tmpData&0xff; + + gtSemGive(dev,dev->tblRegsSem); + + + return retVal; +} + + +/******************************************************************************* +* gsysSetScratchBits +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register bits. +* Scratch bits. These bits are 100% available to software for whatever +* purpose desired. These bits do not connect to any hardware function. +* +* INPUTS: +* scritch - written bits. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetScratchBits +( + IN GT_QD_DEV *dev, + IN GT_U16 scratch +) +{ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gsysSetScratchBits Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SCRAT_0, (GT_U8)(scratch&0xff)); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SCRAT_1, (GT_U8)((scratch>>8)&0xff)); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetScratchBits +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register bits. +* Scratch bits. These bits are 100% available to software for whatever +* purpose desired. These bits do not connect to any hardware function. +* +* INPUTS: +* None. +* +* OUTPUTS: +* scritch - read bits. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetScratchBits +( + IN GT_QD_DEV *dev, + OUT GT_U16 *scratch +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetScratchBits Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SCRAT_1, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + *scratch = data; + *scratch = *scratch<<8; + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SCRAT_0, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *scratch |= data; + + return GT_OK; + +} + +/******************************************************************************* +* gsysSetGpioConfigMod +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS + +* +* INPUTS: +* mode - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioConfigMod +( + IN GT_QD_DEV *dev, + IN GT_U32 mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gsysSetGpioConfigMod Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_CFG, (GT_U8)(mode&0x7f)); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetGpioConfigMod +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS + +* +* INPUTS: +* None. +* +* OUTPUTS: +* mode - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioConfigMod +( + IN GT_QD_DEV *dev, + IN GT_U32 *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetGpioConfigMod Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_CFG, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *mode = 0x7f&data; + + return GT_OK; + +} + +/******************************************************************************* +* gsysSetGpioDirection +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* dir - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioDirection +( + IN GT_QD_DEV *dev, + IN GT_U32 dir +) +{ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gsysSetGpioDirection Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_DIR, (GT_U8)(dir&0x7f)); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetGpioDirection +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* None. +* +* OUTPUTS: +* dir - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioDirection +( + IN GT_QD_DEV *dev, + OUT GT_U32 *dir +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetGpioDirection Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_DIR, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *dir = data; + + return GT_OK; + +} + + +/******************************************************************************* +* gsysSetGpioData +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* data - OR [GT_GPIO_BIT_x] +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetGpioData +( + IN GT_QD_DEV *dev, + IN GT_U32 data +) +{ + GT_STATUS retVal; /* Functions return value. */ + + DBG_INFO(("gsysSetGpioData Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_DAT, (GT_U8)(data&0x7f)); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetGpioData +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* General Purpose Input Output Bits: +* Bit 6 - GT_GPIO_BIT_6: 1:GPIO[6] 0:SE_RCLK1 +* Bit 5 - GT_GPIO_BIT_5: 1:GPIO[5] 0:SE_RCLK0 +* Now, folloing bits are read only. +* Bit 4 - GT_GPIO_BIT_4: 1:GPIO[4] 0: +* Bit 3 - GT_GPIO_BIT_3: 1:GPIO[3] 0: +* Bit 2 - GT_GPIO_BIT_2: 1:GPIO[2] 0: +* Bit 1 - GT_GPIO_BIT_1: 1:GPIO[1] 0:P6_COL +* Bit 0 - GT_GPIO_BIT_0: 1:GPIO[0] 0:P6_CRS +* +* INPUTS: +* None. +* +* OUTPUTS: +* data - OR [GT_GPIO_BIT_x] +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetGpioData +( + IN GT_QD_DEV *dev, + IN GT_U32 *data +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 tmpData; + + DBG_INFO(("gsysGetGpioData Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_GPIO_DAT, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *data = tmpData; + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetConfigData +* +* DESCRIPTION: +* Get Reset Configuration pin data 0-3. +* These registers return the values observed after a hardware Reset on the +* listed CONFIG data listed below. +* Config data 0: +* 0 USER[0] P6_OUTD[5] +* 1 USER[1] P6_OUTD[6] +* 2 USER[2] P6_OUTD[7] +* 3 ADDR[0] P5_OUTD[0] +* 4 ADDR[1] P5_OUTD[5] +* 5 ADDR[2] P5_OUTD[6] +* 6 ADDR]3] P5_OUTD[7] +* 7 ADDR[4] P5_OUTD[1] +* Config data 1: +* 0 LED_SEL[0] P1_LED +* 1 LED_SEL[1] P2_LED +* 2 4COL P3_LED +* 3 NormCx P4_LED +* 4 Jumbo P0_LED +* 5 EE_WE EE_CS/C2_LED +* 6 FD_FLOW EE_CLK/C1_LED +* 7 HD_FLOW EE_DIN/C0_LED +* Config data 2: +* 0 P5_MODE[0] P5_OUTD[2] +* 1 P5_MODE[1] P5_OUTD[3] +* 2 P5_MODE[2] P5_OUTD[4] +* 3 Reserved for future useP5_HALFDPX P5_OUTEN +* 4 P6_MODE[0] P6_OUTD[2] +* 5 P6_MODE[1] P6_OUTD[3] +* 6 P6_MODE[2] P6_OUTD[4] +* 7 Reserved for future useP6_HALFDPX P6_OUTEN +* Config data 2: +* 0 RMU_MODE[0] P6_OUTD[0] +* 1 RMU_MODE[1] P6_OUTD[1] +* 2 +* 3 +* 4 +* 5 +* 6 +* 7 + +* INPUTS: +* none. +* +* OUTPUTS: +* cfgDat - GT_CONFIG_DTTA +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetConfigData +( + IN GT_QD_DEV *dev, + OUT GT_CONFIG_DATA *cfgData +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 tmpData; + + DBG_INFO(("gsysGetConfigData Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_CFG_DAT0, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + cfgData->cfgData0.Byte = tmpData; + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_CFG_DAT1, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + cfgData->cfgData1.Byte = tmpData; + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_CFG_DAT2, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + cfgData->cfgData2.Byte = tmpData; + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_CFG_DAT3, &tmpData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + cfgData->cfgData3.Byte = tmpData; + + return GT_OK; + +} + + +/******************************************************************************* +* gsysSetSyncETai +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* +* INPUTS: +* zpr - ZPR for SyncE and TAI +* znr - ZNR for SyncE and TAI +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetSyncETai +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysSetSyncETai Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((zpr>0x7) || (znr>0x7)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + data = ((zpr&0x7)<<3) | (znr&0x7); + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SYNCE, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetSyncETai +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for SyncE and TAI +* znr - ZNR for SyncE and TAI* +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetSyncETai +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetSyncETai Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_SYNCE, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *zpr = 0x7 &(data>>3); + *znr = 0x7 &(data); + + return GT_OK; + +} + + +/******************************************************************************* +* gsysSetP6_Clock +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* +* INPUTS: +* zpr - ZPR for P6_Clock +* znr - ZNR for P6_Clock +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetP6_Clock +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysSetP6_Clock Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((zpr>0x7) || (znr>0x7)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + data = ((zpr&0x7)<<3) | (znr&0x7); + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_P6_CLK, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetP6_Clock +* +* Get the Scratch and Misc. Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for P6_Clock +* znr - ZNR for P6_Clock* +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetP6_Clock +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetP6_Clock Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_P6_CLK, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *zpr = 0x7 &(data>>3); + *znr = 0x7 &(data); + + return GT_OK; + +} + + + +/******************************************************************************* +* gsysSetP5_Clock +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* +* INPUTS: +* zpr - ZPR for P5_Clock +* znr - ZNR for P5_Clock +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetP5_Clock +( + IN GT_QD_DEV *dev, + IN GT_U8 zpr, + IN GT_U8 znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysSetP5_Clock Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((zpr>0x7) || (znr>0x7)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + data = ((zpr&0x7)<<3) | (znr&0x7); + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_P5_CLK, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetP5_Clock +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* zpr - ZPR for P5_Clock +* znr - ZNR for P5_Clock +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetP5_Clock +( + IN GT_QD_DEV *dev, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetP6_Clock Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_P5_CLK, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *zpr = 0x7 &(data>>3); + *znr = 0x7 &(data); + + return GT_OK; + +} + + + +/******************************************************************************* +* gsysSetEEPROM +* +* DESCRIPTION: +* Set the Scratch and Misc. Control register . +* +* INPUTS: +* dsm - DSM for EEPROM +* zpr - ZPR for EEPROM +* znr - ZNR for EEPROM +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if input parameters are beyond range. +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysSetEEPROM +( + IN GT_QD_DEV *dev, + IN GT_U8 dsm, + IN GT_U8 zpr, + IN GT_U8 znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysSetEEPROM Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((zpr>0x7) || (znr>0x7)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + data = ((dsm&0x3)<<6) | ((zpr&0x7)<<3) | (znr&0x7); + + retVal = gsysSetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_EEPROM, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; + +} + +/******************************************************************************* +* gsysGetEEPROM +* +* DESCRIPTION: +* Get the Scratch and Misc. Control register . +* +* INPUTS: +* None. +* +* OUTPUTS: +* dsm - DSM for EEPROM +* zpr - ZPR for EEPROM +* znr - ZNR for EEPROM +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gsysGetEEPROM +( + IN GT_QD_DEV *dev, + OUT GT_U8 *dsm, + OUT GT_U8 *zpr, + OUT GT_U8 *znr +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 data; + + DBG_INFO(("gsysGetEEPROM Called.\n")); + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_SCRATCH_MISC_CTRL)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = gsysGetScratchMiscCtrl(dev, GT_SCRAT_MISC_REG_EEPROM, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *dsm = 0x3 &(data>>6); + *zpr = 0x7 &(data>>3); + *znr = 0x7 &(data); + + return GT_OK; + +} + + + + + + + + + + + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPCSCtrl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPCSCtrl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPCSCtrl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPCSCtrl.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,1878 @@ +#include + +/******************************************************************************** +* gtPCSCtrl.c +* +* DESCRIPTION: +* API implementation for 1000BASE-X PCS block register access. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 3 $ +*******************************************************************************/ + +#include +#include +#include + + +/******************************************************************************* +* gpcsGetCommaDet +* +* DESCRIPTION: +* This routine retrieves Comma Detection status in PCS +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Comma Detected or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetCommaDet +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetCommaDet Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_PCS_LINK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the CommaDet bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,15,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetPCSLink +* +* DESCRIPTION: +* This routine retrieves Link up status in PCS +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE for Comma Detected or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetPCSLink Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS_LINK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the PCS Link bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,15,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetSyncOK +* +* DESCRIPTION: +* This routine retrieves SynOK bit. It is set to a one when the PCS has +* detected a few comma patterns and is synchronized with its peer PCS +* layer. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if synchronized or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetSyncOK +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetSyncOK Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the SyncOK bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,14,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsGetSyncFail +* +* DESCRIPTION: +* This routine retrieves SynFail bit. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if synchronizaion failed or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetSyncFail +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetSyncFail Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the SyncFail bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,13,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsGetAnBypassed +* +* DESCRIPTION: +* This routine retrieves Inband Auto-Negotiation bypass status. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if AN is bypassed or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetAnBypassed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetAnBypassed Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the AnBypassed bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,12,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetAnBypassMode +* +* DESCRIPTION: +* This routine retrieves Enable mode of Inband Auto-Negotiation bypass. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if AN bypass is enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetAnBypassMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetAnBypassMode Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the AnBypass bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,11,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsSetAnBypassMode +* +* DESCRIPTION: +* This routine retrieves Enable mode of Inband Auto-Negotiation bypass. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable AN bypass mode or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetAnBypassMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetAnBypassMode Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the AnBypass bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,11,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetPCSAnEn +* +* DESCRIPTION: +* This routine retrieves Enable mode of PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if PCS AN is enabled or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSAnEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetPCSAnEn Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + if (!IS_IN_DEV_GROUP(dev, DEV_INTERNAL_GPHY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((hwPort < 4) || (hwPort > 7)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Get the PCSAnEn bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,10,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsSetPCSAnEn +* +* DESCRIPTION: +* This routine sets Enable mode of PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable PCS AN mode or GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetPCSAnEn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetPCSAnEn Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + if (!IS_IN_DEV_GROUP(dev, DEV_INTERNAL_GPHY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if ((hwPort < 4) || (hwPort > 7)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Get the PCSAnEn bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,10,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsSetRestartPCSAn +* +* DESCRIPTION: +* This routine restarts PCS Inband Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetRestartPCSAn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetRestartPCSAn Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = 1; /* to set RestartPCSAn bit */ + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the RestartPCSAn bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,9,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetPCSAnDone +* +* DESCRIPTION: +* This routine retrieves completion information of PCS Auto-Negotiation. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if PCS AN is done or never done +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetPCSAnDone +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetPCSAnDone Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PCS)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given port supports PCS */ + if (!DOES_DEVPORT_SUPPORT_PCS(dev,hwPort)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the PCSAnDone bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,8,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetFCValue +* +* DESCRIPTION: +* This routine sets Flow Control's force value +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force flow control enabled, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetFCValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetFCValue Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Set the FCValue bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,7,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetFCValue +* +* DESCRIPTION: +* This routine retrieves Flow Control Value which will be used for Forcing +* Flow Control enabled or disabled. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if FC Force value is one (flow control enabled) +* GT_FALSE otherwise (flow control disabled) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetFCValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetFCValue Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the FCValue bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,7,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetForcedFC +* +* DESCRIPTION: +* This routine forces Flow Control. If FCValue is set to one, calling this +* routine with GT_TRUE will force Flow Control to be enabled. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force flow control (enable or disable), GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedFC +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetForcedFC Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedFC bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,6,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetForcedFC +* +* DESCRIPTION: +* This routine retrieves Forced Flow Control bit +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedFC bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedFC +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetForcedLink Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedLink bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,6,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + + +/******************************************************************************* +* gpcsSetLinkValue +* +* DESCRIPTION: +* This routine sets Link's force value +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force link up, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetLinkValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetLinkValue Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the LinkValue bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,5,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetLinkValue +* +* DESCRIPTION: +* This routine retrieves Link Value which will be used for Forcing Link +* up or down. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Link Force value is one (link up) +* GT_FALSE otherwise (link down) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetLinkValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetLinkValue Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the LinkValue bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,5,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetForcedLink +* +* DESCRIPTION: +* This routine forces Link. If LinkValue is set to one, calling this +* routine with GT_TRUE will force Link to be up. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force link (up or down), GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetForcedLink Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedLink bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,4,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetForcedLink +* +* DESCRIPTION: +* This routine retrieves Forced Link bit +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedLink bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedLink +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetForcedLink Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedLink bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,4,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetDpxValue +* +* DESCRIPTION: +* This routine sets Duplex's Forced value. This function needs to be +* called prior to gpcsSetForcedDpx. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force full duplex, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetDpxValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetDpxValue Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the DpxValue bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,3,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetDpxValue +* +* DESCRIPTION: +* This routine retrieves Duplex's Forced value +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if Duplex's Forced value is set to Full duplex, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetDpxValue +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetForcedLink Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the DpxValue bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,3,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetForcedDpx +* +* DESCRIPTION: +* This routine forces duplex mode. If DpxValue is set to one, calling this +* routine with GT_TRUE will force duplex mode to be full duplex. +* +* INPUTS: +* port - the logical port number. +* state - GT_TRUE to force duplex mode, GT_FALSE otherwise +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForcedDpx +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetForcedDpx Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedDpx bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,2,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetForcedDpx +* +* DESCRIPTION: +* This routine retrieves Forced Duplex. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_TRUE if ForcedDpx bit is one, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForcedDpx +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetForcedDpx Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForcedDpx bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,2,1,&data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *state); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsSetForceSpeed +* +* DESCRIPTION: +* This routine forces Speed. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PORT_FORCED_SPEED_MODE (10, 100, 1000, or no force speed) +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsSetForceSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_FORCED_SPEED_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetForceSpeed Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Set the Force Speed bits. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,0,2,(GT_U16)mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetForceSpeed +* +* DESCRIPTION: +* This routine retrieves Force Speed value +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* state - GT_PORT_FORCED_SPEED_MODE (10, 100, 1000, or no force speed) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpcsGetForceSpeed +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_FORCED_SPEED_MODE *mode +) +{ + GT_U16 data; /* Used to poll the SWReset bit */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetForceSpeed Called.\n")); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_FORCE_WITH_VALUE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the ForceSpeed bits. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,0,2,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *mode = data; + + /* return */ + return retVal; +} + + +/******************************************************************************* +* gpcsGetRGMIITimingDelay +* +* DESCRIPTION: +* RGMII receive/transmit Timing Control. This api adds delay to RXCLK for +* IND inputs and GTXCLK for OUTD outputs when port is in RGMII mode. +* Change to this bit are disruptive to normal operation. Hence any changes +* to this register must be done only while the port's link is down. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* rxmode - GT_FALSE for default setup, GT_TRUE for adding delay to rxclk +* txmode - GT_FALSE for default setup, GT_TRUE for adding delay to txclk +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpcsGetRGMIITimingDelay +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *rxmode, + OUT GT_BOOL *txmode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsGetRGMIITimingDelay Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_RGMII_TIMING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (hwPort < (dev->maxPorts - 2)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the register bit(s). */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,14,2,&data); + + *rxmode = (data & 0x2)?GT_TRUE:GT_FALSE; + *txmode = (data & 0x1)?GT_TRUE:GT_FALSE; + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + /* return */ + return retVal; +} + +/******************************************************************************* +* gpcsSetRGMIITimingDelay +* +* DESCRIPTION: +* RGMII receive/transmit Timing Control. This api adds delay to RXCLK for +* IND inputs and GTXCLK for OUTD outputs when port is in RGMII mode. +* Change to this bit are disruptive to normal operation. Hence any changes +* to this register must be done only while the port's link is down. +* +* INPUTS: +* port - the logical port number. +* rxmode - GT_FALSE for default setup, GT_TRUE for adding delay to rxclk +* txmode - GT_FALSE for default setup, GT_TRUE for adding delay to txclk +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpcsSetRGMIITimingDelay +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL rxmode, + IN GT_BOOL txmode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gpcsSetRGMIITimingDelay Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_RGMII_TIMING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (hwPort < (dev->maxPorts - 2)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = (rxmode) ? 2 : 0; + data |= (txmode) ? 1 : 0; + + /* Set the register bit(s). */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,14,2,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + /* return */ + return retVal; +} + + + + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyCtrl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyCtrl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyCtrl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyCtrl.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,3032 @@ +#include + +/******************************************************************************** +* gtPhyCtrl.h +* +* DESCRIPTION: +* API definitions for PHY control facility. +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 10 $ +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* + * This routine set Auto-Negotiation Ad Register for Fast Ethernet Phy +*/ +static +GT_STATUS feSetAutoMode +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_PHY_AUTO_MODE mode +) +{ + GT_U16 u16Data; + + GT_UNUSED_PARAM(phyInfo); + + DBG_INFO(("feSetAutoMode Called.\n")); + + if(hwReadPhyReg(dev,hwPort,QD_PHY_AUTONEGO_AD_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + return GT_FAIL; + } + + /* Mask out all auto mode related bits. */ + u16Data &= ~QD_PHY_MODE_AUTO_AUTO; + + switch(mode) + { + case SPEED_AUTO_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_AUTO_AUTO; + break; + case SPEED_100_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_100_AUTO; + break; + case SPEED_10_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_10_AUTO; + break; + case SPEED_AUTO_DUPLEX_FULL: + u16Data |= QD_PHY_MODE_AUTO_FULL; + break; + case SPEED_AUTO_DUPLEX_HALF: + u16Data |= QD_PHY_MODE_AUTO_HALF; + break; + case SPEED_100_DUPLEX_FULL: + u16Data |= QD_PHY_100_FULL; + break; + case SPEED_100_DUPLEX_HALF: + u16Data |= QD_PHY_100_HALF; + break; + case SPEED_10_DUPLEX_FULL: + u16Data |= QD_PHY_10_FULL; + break; + case SPEED_10_DUPLEX_HALF: + u16Data |= QD_PHY_10_HALF; + break; + default: + DBG_INFO(("Unknown Auto Mode (%d)\n",mode)); + return GT_BAD_PARAM; + } + + /* Write to Phy AutoNegotiation Advertisement Register. */ + if(hwWritePhyReg(dev,hwPort,QD_PHY_AUTONEGO_AD_REG,u16Data) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d,data:%#x).\n",hwPort,QD_PHY_AUTONEGO_AD_REG,u16Data)); + return GT_FAIL; + } + + return GT_OK; +} + +/* + * This routine set Auto-Negotiation Ad Register for Copper +*/ +static +GT_STATUS gigCopperSetAutoMode +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_PHY_AUTO_MODE mode +) +{ + GT_U16 u16Data,u16Data1; + + DBG_INFO(("gigCopperSetAutoMode Called.\n")); + + if(hwReadPagedPhyReg(dev,hwPort,0,QD_PHY_AUTONEGO_AD_REG,phyInfo->anyPage,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + return GT_FAIL; + } + + /* Mask out all auto mode related bits. */ + u16Data &= ~QD_PHY_MODE_AUTO_AUTO; + + if(hwReadPagedPhyReg(dev,hwPort,0,QD_PHY_AUTONEGO_1000AD_REG,phyInfo->anyPage,&u16Data1) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + return GT_FAIL; + } + + /* Mask out all auto mode related bits. */ + u16Data1 &= ~(QD_GIGPHY_1000T_FULL|QD_GIGPHY_1000T_HALF); + + switch(mode) + { + case SPEED_AUTO_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_AUTO_AUTO; + case SPEED_1000_DUPLEX_AUTO: + u16Data1 |= QD_GIGPHY_1000T_FULL|QD_GIGPHY_1000T_HALF; + break; + case SPEED_AUTO_DUPLEX_FULL: + u16Data |= QD_PHY_MODE_AUTO_FULL; + u16Data1 |= QD_GIGPHY_1000T_FULL; + break; + case SPEED_1000_DUPLEX_FULL: + u16Data1 |= QD_GIGPHY_1000T_FULL; + break; + case SPEED_1000_DUPLEX_HALF: + u16Data1 |= QD_GIGPHY_1000T_HALF; + break; + case SPEED_AUTO_DUPLEX_HALF: + u16Data |= QD_PHY_MODE_AUTO_HALF; + u16Data1 |= QD_GIGPHY_1000T_HALF; + break; + case SPEED_100_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_100_AUTO; + break; + case SPEED_10_DUPLEX_AUTO: + u16Data |= QD_PHY_MODE_10_AUTO; + break; + case SPEED_100_DUPLEX_FULL: + u16Data |= QD_PHY_100_FULL; + break; + case SPEED_100_DUPLEX_HALF: + u16Data |= QD_PHY_100_HALF; + break; + case SPEED_10_DUPLEX_FULL: + u16Data |= QD_PHY_10_FULL; + break; + case SPEED_10_DUPLEX_HALF: + u16Data |= QD_PHY_10_HALF; + break; + default: + DBG_INFO(("Unknown Auto Mode (%d)\n",mode)); + return GT_BAD_PARAM; + } + + /* Write to Phy AutoNegotiation Advertisement Register. */ + if(hwWritePagedPhyReg(dev,hwPort,0,QD_PHY_AUTONEGO_AD_REG,phyInfo->anyPage,u16Data) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d,data:%#x).\n",hwPort,QD_PHY_AUTONEGO_AD_REG,u16Data)); + return GT_FAIL; + } + + /* Write to Phy AutoNegotiation 1000B Advertisement Register. */ + if(hwWritePagedPhyReg(dev,hwPort,0,QD_PHY_AUTONEGO_1000AD_REG,phyInfo->anyPage,u16Data1) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + return GT_FAIL; + } + + return GT_OK; +} + +/* + * This routine set Auto-Negotiation Ad Register for Fiber +*/ +static +GT_STATUS gigFiberSetAutoMode +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_PHY_AUTO_MODE mode +) +{ + GT_U16 u16Data; + + DBG_INFO(("gigPhySetAutoMode Called.\n")); + + if(hwReadPagedPhyReg(dev,hwPort,1,QD_PHY_AUTONEGO_AD_REG,phyInfo->anyPage,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + return GT_FAIL; + } + + /* Mask out all auto mode related bits. */ + u16Data &= ~(QD_GIGPHY_1000X_FULL|QD_GIGPHY_1000X_HALF); + + switch(mode) + { + case SPEED_AUTO_DUPLEX_AUTO: + case SPEED_1000_DUPLEX_AUTO: + u16Data |= QD_GIGPHY_1000X_FULL|QD_GIGPHY_1000X_HALF; + break; + case SPEED_AUTO_DUPLEX_FULL: + case SPEED_1000_DUPLEX_FULL: + u16Data |= QD_GIGPHY_1000X_FULL; + break; + case SPEED_AUTO_DUPLEX_HALF: + case SPEED_1000_DUPLEX_HALF: + u16Data |= QD_GIGPHY_1000X_HALF; + break; + default: + DBG_INFO(("Unknown Auto Mode (%d)\n",mode)); + return GT_BAD_PARAM; + } + + /* Write to Phy AutoNegotiation Advertisement Register. */ + if(hwWritePagedPhyReg(dev,hwPort,1,QD_PHY_AUTONEGO_AD_REG,phyInfo->anyPage,u16Data) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d,data:%#x).\n",hwPort,QD_PHY_AUTONEGO_AD_REG,u16Data)); + return GT_FAIL; + } + + return GT_OK; +} + +/* + * This routine sets Auto Mode and Reset the phy +*/ +static +GT_STATUS phySetAutoMode +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort, + IN GT_PHY_INFO *phyInfo, + IN GT_PHY_AUTO_MODE mode +) +{ + GT_U16 u16Data; + GT_STATUS status; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("phySetAutoMode Called.\n")); + + if (!(phyInfo->flag & GT_PHY_GIGABIT)) + { + if((status=feSetAutoMode(dev,hwPort,phyInfo,mode)) != GT_OK) + { + return status; + } + + u16Data = QD_PHY_SPEED | QD_PHY_DUPLEX | QD_PHY_AUTONEGO; + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + /* soft reset */ + return hwPhyReset(dev,hwPort,u16Data); + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo->pageType,&autoOn,&pageReg) != GT_OK) + { + return GT_FAIL; + } + + if(phyInfo->flag & GT_PHY_COPPER) + { + if((status=gigCopperSetAutoMode(dev,hwPort,phyInfo,mode)) != GT_OK) + { + return status; + } + + u16Data = QD_PHY_AUTONEGO; + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + /* Write to Phy Control Register. */ + if(hwWritePagedPhyReg(dev,hwPort,0,QD_PHY_CONTROL_REG,phyInfo->anyPage,u16Data) != GT_OK) + return GT_FAIL; + } + else if(phyInfo->flag & GT_PHY_FIBER) + { + if((status=gigFiberSetAutoMode(dev,hwPort,phyInfo,mode)) != GT_OK) + { + return status; + } + u16Data = QD_PHY_AUTONEGO; + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + /* Write to Phy Control Register. */ + if(hwWritePagedPhyReg(dev,hwPort,1,QD_PHY_CONTROL_REG,phyInfo->anyPage,u16Data) != GT_OK) + return GT_FAIL; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo->pageType,autoOn,pageReg) != GT_OK) + { + return GT_FAIL; + } + + return hwPhyReset(dev,hwPort,0xFF); +} + + +/******************************************************************************* +* gprtPhyReset +* +* DESCRIPTION: +* This routine preforms PHY reset. +* After reset, phy will be in Autonegotiation mode. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* data sheet register 0.15 - Reset +* data sheet register 0.13 - Speed +* data sheet register 0.12 - Autonegotiation +* data sheet register 0.8 - Duplex Mode +*******************************************************************************/ + +GT_STATUS gprtPhyReset +( + IN GT_QD_DEV *dev, + IN GT_LPORT port +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_PHY_INFO phyInfo; + + DBG_INFO(("gprtPhyReset Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* set Auto Negotiation AD Register */ + retVal = phySetAutoMode(dev,hwPort,&phyInfo,SPEED_AUTO_DUPLEX_AUTO); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + gtSemGive(dev,dev->phyRegsSem); + + return retVal; +} + + +/******************************************************************************* +* gprtSetPortLoopback +* +* DESCRIPTION: +* Enable/Disable Internal Port Loopback. +* For 10/100 Fast Ethernet PHY, speed of Loopback is determined as follows: +* If Auto-Negotiation is enabled, this routine disables Auto-Negotiation and +* forces speed to be 10Mbps. +* If Auto-Negotiation is disabled, the forced speed is used. +* Disabling Loopback simply clears bit 14 of control register(0.14). Therefore, +* it is recommended to call gprtSetPortAutoMode for PHY configuration after +* Loopback test. +* For 10/100/1000 Gigagbit Ethernet PHY, speed of Loopback is determined as follows: +* If Auto-Negotiation is enabled and Link is active, the current speed is used. +* If Auto-Negotiation is disabled, the forced speed is used. +* All other cases, default MAC Interface speed is used. Please refer to the data +* sheet for the information of the default MAC Interface speed. +* +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* enable - If GT_TRUE, enable loopback mode +* If GT_FALSE, disable loopback mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.14 - Loop_back +* +*******************************************************************************/ + +GT_STATUS gprtSetPortLoopback +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL enable +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_PHY_INFO phyInfo; + + DBG_INFO(("gprtSetPortLoopback Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(hwReadPhyReg(dev,hwPort,QD_PHY_CONTROL_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_CONTROL_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* is this Fast Ethernet Phy? */ + if (!(phyInfo.flag & GT_PHY_GIGABIT)) + { + if(enable) + { + if(u16Data & QD_PHY_AUTONEGO) + { + /* disable Auto-Neg and force speed to be 10Mbps */ + u16Data = u16Data & QD_PHY_DUPLEX; + + if((retVal=hwPhyReset(dev,hwPort,u16Data)) != GT_OK) + { + DBG_INFO(("Softreset failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + } + } + } + + BOOL_2_BIT(enable,u16Data); + + /* Write to Phy Control Register. */ + retVal = hwSetPhyRegField(dev,hwPort,QD_PHY_CONTROL_REG,14,1,u16Data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSetPortSpeed +* +* DESCRIPTION: +* Sets speed for a specific logical port. This function will keep the duplex +* mode and loopback mode to the previous value, but disable others, such as +* Autonegotiation. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* speed - port speed. +* PHY_SPEED_10_MBPS for 10Mbps +* PHY_SPEED_100_MBPS for 100Mbps +* PHY_SPEED_1000_MBPS for 1000Mbps +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.13 - Speed Selection (LSB) +* data sheet register 0.6 - Speed Selection (MSB) +* +*******************************************************************************/ + +GT_STATUS gprtSetPortSpeed +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_PHY_SPEED speed +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_PHY_INFO phyInfo; + GT_STATUS retVal; + + DBG_INFO(("gprtSetPortSpeed Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(hwReadPhyReg(dev,hwPort,QD_PHY_CONTROL_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_CONTROL_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + switch(speed) + { + case PHY_SPEED_10_MBPS: + if ((phyInfo.flag & GT_PHY_GIGABIT) && !(phyInfo.flag & GT_PHY_COPPER)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_BAD_PARAM; + } + u16Data = u16Data & (QD_PHY_LOOPBACK | QD_PHY_DUPLEX); + break; + case PHY_SPEED_100_MBPS: + u16Data = (u16Data & (QD_PHY_LOOPBACK | QD_PHY_DUPLEX)) | QD_PHY_SPEED; + break; + case PHY_SPEED_1000_MBPS: + if (!(phyInfo.flag & GT_PHY_GIGABIT)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_BAD_PARAM; + } + u16Data = (u16Data & (QD_PHY_LOOPBACK | QD_PHY_DUPLEX)) | QD_PHY_SPEED_MSB; + break; + default: + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + retVal = hwPhyReset(dev,hwPort,u16Data); + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtPortAutoNegEnable +* +* DESCRIPTION: +* Enable/disable an Auto-Negotiation. +* This routine simply sets Auto Negotiation bit (bit 12) of Control +* Register and reset the phy. +* For Speed and Duplex selection, please use gprtSetPortAutoMode. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* state - GT_TRUE for enable Auto-Negotiation, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.12 - Auto-Negotiation Enable +* data sheet register 4.8, 4.7, 4.6, 4.5 - Auto-Negotiation Advertisement +* +*******************************************************************************/ +GT_STATUS gprtPortAutoNegEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL state +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal; + + DBG_INFO(("gprtPortAutoNegEnable Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(hwReadPhyReg(dev,hwPort,QD_PHY_CONTROL_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_CONTROL_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(state) + { + u16Data = (u16Data & (QD_PHY_SPEED | QD_PHY_DUPLEX)) | QD_PHY_AUTONEGO; + } + else + { + u16Data = u16Data & (QD_PHY_SPEED | QD_PHY_DUPLEX); + } + + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + retVal = hwPhyReset(dev,hwPort,u16Data); + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + +/******************************************************************************* +* gprtPortPowerDown +* +* DESCRIPTION: +* Enable/disable (power down) on specific logical port. +* Phy configuration remains unchanged after Power down. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* state - GT_TRUE: power down +* GT_FALSE: normal operation +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.11 - Power Down +* +*******************************************************************************/ + +GT_STATUS gprtPortPowerDown +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_BOOL state +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + + DBG_INFO(("gprtPortPowerDown Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + BOOL_2_BIT(state,u16Data); + + if((retVal=hwSetPhyRegField(dev,hwPort,QD_PHY_CONTROL_REG,11,1,u16Data)) != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + +/******************************************************************************* +* gprtPortRestartAutoNeg +* +* DESCRIPTION: +* Restart AutoNegotiation. If AutoNegotiation is not enabled, it'll enable +* it. Loopback and Power Down will be disabled by this routine. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.9 - Restart Auto-Negotiation +* +*******************************************************************************/ + +GT_STATUS gprtPortRestartAutoNeg +( +IN GT_QD_DEV *dev, +IN GT_LPORT port +) +{ + GT_STATUS retVal; + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + + DBG_INFO(("gprtPortRestartAutoNeg Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(hwReadPhyReg(dev,hwPort,QD_PHY_CONTROL_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_CONTROL_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + u16Data &= (QD_PHY_DUPLEX | QD_PHY_SPEED); + u16Data |= (QD_PHY_RESTART_AUTONEGO | QD_PHY_AUTONEGO); + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + /* Write to Phy Control Register. */ + retVal = hwWritePhyReg(dev,hwPort,QD_PHY_CONTROL_REG,u16Data); + gtSemGive(dev,dev->phyRegsSem); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtSetPortDuplexMode +* +* DESCRIPTION: +* Sets duplex mode for a specific logical port. This function will keep +* the speed and loopback mode to the previous value, but disable others, +* such as Autonegotiation. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* dMode - dulpex mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* data sheet register 0.8 - Duplex Mode +* +*******************************************************************************/ +GT_STATUS gprtSetPortDuplexMode +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_BOOL dMode +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal; + + DBG_INFO(("gprtSetPortDuplexMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(hwReadPhyReg(dev,hwPort,QD_PHY_CONTROL_REG,&u16Data) != GT_OK) + { + DBG_INFO(("Not able to read Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_CONTROL_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(dMode) + { + u16Data = (u16Data & (QD_PHY_LOOPBACK | QD_PHY_SPEED | QD_PHY_SPEED_MSB)) | QD_PHY_DUPLEX; + } + else + { + u16Data = u16Data & (QD_PHY_LOOPBACK | QD_PHY_SPEED | QD_PHY_SPEED_MSB); + } + + + DBG_INFO(("Write to phy(%d) register: regAddr 0x%x, data %#x", + hwPort,QD_PHY_CONTROL_REG,u16Data)); + + /* Write to Phy Control Register. */ + retVal = hwPhyReset(dev,hwPort,u16Data); + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSetPortAutoMode +* +* DESCRIPTION: +* This routine sets up the port with given Auto Mode. +* Supported mode is as follows: +* - Auto for both speed and duplex. +* - Auto for speed only and Full duplex. +* - Auto for speed only and Half duplex. +* - Auto for duplex only and speed 1000Mbps. +* - Auto for duplex only and speed 100Mbps. +* - Auto for duplex only and speed 10Mbps. +* - Speed 1000Mbps and Full duplex. +* - Speed 1000Mbps and Half duplex. +* - Speed 100Mbps and Full duplex. +* - Speed 100Mbps and Half duplex. +* - Speed 10Mbps and Full duplex. +* - Speed 10Mbps and Half duplex. +* +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* mode - Auto Mode to be written +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - on device without copper +* +* COMMENTS: +* data sheet register 4.8, 4.7, 4.6, and 4.5 Autonegotiation Advertisement +* data sheet register 4.6, 4.5 Autonegotiation Advertisement for 1000BX +* data sheet register 9.9, 9.8 Autonegotiation Advertisement for 1000BT +*******************************************************************************/ + +GT_STATUS gprtSetPortAutoMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PHY_AUTO_MODE mode +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_PHY_INFO phyInfo; + + DBG_INFO(("gprtSetPortAutoMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + retVal = GT_NOT_SUPPORTED; + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + retVal = phySetAutoMode(dev,hwPort,&phyInfo,mode); + + gtSemGive(dev,dev->phyRegsSem); + return retVal; + +} + + +/******************************************************************************* +* gprtSetPause +* +* DESCRIPTION: +* This routine will set the pause bit in Autonegotiation Advertisement +* Register. And restart the autonegotiation. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* state - GT_PHY_PAUSE_MODE enum value. +* GT_PHY_NO_PAUSE - disable pause +* GT_PHY_PAUSE - support pause +* GT_PHY_ASYMMETRIC_PAUSE - support asymmetric pause +* GT_PHY_BOTH_PAUSE - support both pause and asymmetric pause +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* COMMENTS: +* data sheet register 4.10 Autonegotiation Advertisement Register +*******************************************************************************/ + +GT_STATUS gprtSetPause +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_PHY_PAUSE_MODE state +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data,regStart; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + + DBG_INFO(("phySetPause Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + regStart = 10; + + if(state & GT_PHY_ASYMMETRIC_PAUSE) + { + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_GIGABIT)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_BAD_PARAM; + } + + if(!(phyInfo.flag & GT_PHY_COPPER)) + { + regStart = 7; + } + + } + + u16Data = state; + + /* Write to Phy AutoNegotiation Advertisement Register. */ + if((retVal=hwSetPhyRegField(dev,hwPort,QD_PHY_AUTONEGO_AD_REG,(GT_U8)regStart,2,u16Data)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d).\n",hwPort,QD_PHY_AUTONEGO_AD_REG)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* Restart Auto Negotiation */ + if((retVal=hwSetPhyRegField(dev,hwPort,QD_PHY_CONTROL_REG,9,1,1)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d,data:%#x).\n",hwPort,QD_PHY_AUTONEGO_AD_REG,u16Data)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +static +GT_STATUS dteWorkAround_Phy100M +( + IN GT_QD_DEV *dev, + IN GT_U8 hwPort +) +{ + GT_STATUS status = GT_OK; + GT_U32 threshold[] = {0x000B,0x0000,0x8780,0x0000,0x8F80,0x0000, + 0x9780,0x0000,0x9F80,0x0000,0xA780,0x0000, + 0xAF80,0x0000,0xB780,0x0000,0xBF80,0x0000, + 0xC780,0x0000,0xCF80,0x0000,0xD780,0x0000, + 0xDF80,0x0000,0xE780,0x0000,0xEF80,0x0000, + 0xF780,0x0000,0xFF80,0x0000}; + int i, thresholdSize; + + /* force r125 clock */ + if((status= hwWritePhyReg(dev,hwPort,0x1D,0x0003)) != GT_OK) + { + return status; + } + if((status= hwWritePhyReg(dev,hwPort,0x1E,0x807f)) != GT_OK) + { + return status; + } + + /* write thresholds */ + if((status= hwWritePhyReg(dev,hwPort,0x1D,0x000B)) != GT_OK) + { + return status; + } + + thresholdSize = sizeof(threshold)/sizeof(GT_U32); + + for(i=0; iphyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* check if the port supports DTE */ + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_DTE_CAPABLE)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + switch(phyInfo.dteType) + { + case GT_PHY_DTE_TYPE1: + /* FE Phy needs work-around */ + if((retVal = feSetDTE(dev,hwPort,state)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(state == GT_FALSE) + break; + + if((retVal = dteWorkAround_Phy100M(dev,hwPort)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + break; + case GT_PHY_DTE_TYPE3: + /* Gigabit Phy with work-around required */ + if((retVal = gigSetDTE(dev,hwPort,state)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(state == GT_FALSE) + break; + + if((retVal = dteWorkAround_Phy1000M(dev,hwPort)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + break; + + case GT_PHY_DTE_TYPE2: + /* no workaround required */ + if((retVal = gigSetDTE(dev,hwPort,state)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + break; + case GT_PHY_DTE_TYPE4: + /* no workaround required */ + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = gigMPSetDTE(dev,hwPort,state)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + break; + case GT_PHY_DTE_TYPE5: + /* FE Phy */ + if((retVal = feSetDTE(dev,hwPort,state)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + break; + + default: + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGetDTEDetectStatus +* +* DESCRIPTION: +* This routine gets DTE status. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* status - GT_TRUE, if link partner needs DTE power. +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtGetDTEDetectStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *state +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data,pageReg; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + + DBG_INFO(("gprtGetDTEStatus Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* check if the port supports DTE */ + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_DTE_CAPABLE)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + switch(phyInfo.dteType) + { + case GT_PHY_DTE_TYPE1: + /* FE Phy needs work-around */ + if((retVal = hwReadPhyReg(dev,hwPort,17,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + *state = (u16Data & 0x8000)?GT_TRUE:GT_FALSE; + + break; + case GT_PHY_DTE_TYPE2: + case GT_PHY_DTE_TYPE3: + if((retVal = hwReadPhyReg(dev,hwPort,27,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + *state = (u16Data & 0x10)?GT_TRUE:GT_FALSE; + + break; + case GT_PHY_DTE_TYPE4: + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = hwReadPagedPhyReg(dev,hwPort,0,17,phyInfo.anyPage,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + *state = (u16Data & 0x4)?GT_TRUE:GT_FALSE; + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + break; + default: + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSetDTEDetectDropWait +* +* DESCRIPTION: +* Once the PHY no longer detects that the link partner filter, the PHY +* will wait a period of time before clearing the power over Ethernet +* detection status bit. The wait time is 5 seconds multiplied by the +* given value. +* +* INPUTS: +* port - The logical port number +* waitTime - 0 ~ 15 (unit of 4 sec.) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtSetDTEDetectDropWait +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 waitTime +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtSetDTEDropWait Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + /* check if the port supports DTE */ + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_DTE_CAPABLE)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + switch(phyInfo.dteType) + { + case GT_PHY_DTE_TYPE1: + if((retVal = hwReadPhyReg(dev,hwPort,22,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data & ~(0xF<<12)) | ((waitTime & 0xF) << 12); + + if((retVal = hwWritePhyReg(dev,hwPort,22,u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + break; + case GT_PHY_DTE_TYPE2: + case GT_PHY_DTE_TYPE3: + if((retVal = hwReadPhyReg(dev,hwPort,27,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data & ~(0xF<<5)) | ((waitTime & 0xF) << 5); + + if((retVal = hwWritePhyReg(dev,hwPort,27,u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + break; + case GT_PHY_DTE_TYPE4: + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = hwReadPagedPhyReg(dev,hwPort,0,26,phyInfo.anyPage,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data & ~(0xF<<4)) | ((waitTime & 0xF) << 4); + if((retVal = hwWritePagedPhyReg(dev,hwPort,0,26,phyInfo.anyPage,u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + break; + default: + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGetDTEDetectDropWait +* +* DESCRIPTION: +* Once the PHY no longer detects that the link partner filter, the PHY +* will wait a period of time before clearing the power over Ethernet +* detection status bit. The wait time is 5 seconds multiplied by the +* returned value. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* waitTime - 0 ~ 15 (unit of 4 sec.) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtGetDTEDetectDropWait +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *waitTime +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtSetDTEDropWait Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_DTE_CAPABLE)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + switch(phyInfo.dteType) + { + case GT_PHY_DTE_TYPE1: + if((retVal = hwReadPhyReg(dev,hwPort,22,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data >> 12) & 0xF; + + break; + case GT_PHY_DTE_TYPE2: + case GT_PHY_DTE_TYPE3: + if((retVal = hwReadPhyReg(dev,hwPort,27,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data >> 5) & 0xF; + + break; + case GT_PHY_DTE_TYPE4: + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = hwReadPagedPhyReg(dev,hwPort,0,26,phyInfo.anyPage,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + u16Data = (u16Data >> 4) & 0xF; + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + break; + default: + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + *waitTime = u16Data; + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSetEnergyDetect +* +* DESCRIPTION: +* Energy Detect power down mode enables or disables the PHY to wake up on +* its own by detecting activity on the CAT 5 cable. +* +* INPUTS: +* port - The logical port number +* mode - GT_EDETECT_MODE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtSetEnergyDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EDETECT_MODE mode +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtSetEnergyDetect Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (phyInfo.flag & GT_PHY_SERDES_CORE) + { + DBG_INFO(("Not Supported.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + else if (phyInfo.flag & GT_PHY_GIGABIT) + { + /* check if the mode is valid */ + switch (mode) + { + case GT_EDETECT_OFF: + u16Data = 0; + break; + case GT_EDETECT_SENSE_PULSE: + u16Data = 3; + break; + case GT_EDETECT_SENSE: + u16Data = 2; + break; + default: + DBG_INFO(("Invalid paramerter.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_BAD_PARAM; + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = hwSetPagedPhyRegField(dev,hwPort,0,0x10,8,2,phyInfo.anyPage,u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if((retVal = hwPhyReset(dev,hwPort,0xFF)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + } + else /* it's a Fast Ethernet device */ + { + /* check if the mode is valid */ + switch (mode) + { + case GT_EDETECT_OFF: + u16Data = 0; + break; + case GT_EDETECT_SENSE_PULSE: + u16Data = 1; + break; + case GT_EDETECT_SENSE: + default: + DBG_INFO(("Invalid paramerter.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_BAD_PARAM; + } + + if((retVal = hwSetPhyRegField(dev,hwPort,0x10,14,1,u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGetEnergyDetect +* +* DESCRIPTION: +* Energy Detect power down mode enables or disables the PHY to wake up on +* its own by detecting activity on the CAT 5 cable. +* +* INPUTS: +* port - The logical port number +* +* OUTPUTS: +* mode - GT_EDETECT_MODE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ + +GT_STATUS gprtGetEnergyDetect +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EDETECT_MODE *mode +) +{ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_STATUS retVal = GT_OK; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtGetEnergyDetect Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (phyInfo.flag & GT_PHY_SERDES_CORE) + { + DBG_INFO(("Not Supported.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + else if (phyInfo.flag & GT_PHY_GIGABIT) + { + /* read the mode */ + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal = hwGetPagedPhyRegField(dev,hwPort,0,0x10,8,2,phyInfo.anyPage,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + switch (u16Data) + { + case 0: + case 1: + *mode = GT_EDETECT_OFF; + break; + case 2: + *mode = GT_EDETECT_SENSE; + break; + case 3: + *mode = GT_EDETECT_SENSE_PULSE; + break; + default: + DBG_INFO(("Unknown value (shouldn't happen).\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + } + else /* it's a Fast Ethernet device */ + { + /* read the mode */ + if((retVal = hwGetPhyRegField(dev,hwPort,0x10,14,1,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + switch (u16Data) + { + case 0: + *mode = GT_EDETECT_OFF; + break; + case 1: + *mode = GT_EDETECT_SENSE_PULSE; + break; + default: + DBG_INFO(("Unknown value (shouldn't happen).\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + } + + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSet1000TMasterMode +* +* DESCRIPTION: +* This routine sets the ports 1000Base-T Master mode and restart the Auto +* negotiation. +* +* INPUTS: +* port - the logical port number. +* mode - GT_1000T_MASTER_SLAVE structure +* autoConfig - GT_TRUE for auto, GT_FALSE for manual setup. +* masterPrefer - GT_TRUE if Master configuration is preferred. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSet1000TMasterMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_1000T_MASTER_SLAVE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtSet1000TMasterMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + return GT_NOT_SUPPORTED; + } + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_GIGABIT) || !(phyInfo.flag & GT_PHY_COPPER)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(mode->autoConfig == GT_TRUE) + { + if(mode->masterPrefer == GT_TRUE) + { + data = 0x1; + } + else + { + data = 0x0; + } + } + else + { + if(mode->masterPrefer == GT_TRUE) + { + data = 0x6; + } + else + { + data = 0x4; + } + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* Set the Master Mode. */ + retVal = hwSetPagedPhyRegField(dev,hwPort,0,9,10,3,phyInfo.anyPage,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + else + { + DBG_INFO(("OK.\n")); + } + + /* Restart Auto Negotiation */ + if((retVal=hwSetPhyRegField(dev,hwPort,QD_PHY_CONTROL_REG,9,1,1)) != GT_OK) + { + DBG_INFO(("Not able to write Phy Reg(port:%d,offset:%d,data:%#x).\n",hwPort,QD_PHY_CONTROL_REG,1)); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGet1000TMasterMode +* +* DESCRIPTION: +* This routine retrieves 1000Base-T Master Mode +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_1000T_MASTER_SLAVE structure +* autoConfig - GT_TRUE for auto, GT_FALSE for manual setup. +* masterPrefer - GT_TRUE if Master configuration is preferred. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGet1000TMasterMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_1000T_MASTER_SLAVE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtGet1000TMasterMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + return GT_NOT_SUPPORTED; + } + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (!(phyInfo.flag & GT_PHY_GIGABIT) || !(phyInfo.flag & GT_PHY_COPPER)) + { + DBG_INFO(("Not Supported\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + /* Set the Master Mode. */ + retVal = hwGetPagedPhyRegField(dev,hwPort,0,9,10,3,phyInfo.anyPage,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + else + { + DBG_INFO(("OK.\n")); + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(data & 0x4) /* Manual Mode */ + { + mode->autoConfig = GT_FALSE; + + if(data & 0x2) + { + mode->masterPrefer = GT_TRUE; + } + else + { + mode->masterPrefer = GT_FALSE; + } + } + else /* Auto Mode */ + { + mode->autoConfig = GT_TRUE; + + if(data & 0x1) + { + mode->masterPrefer = GT_TRUE; + } + else + { + mode->masterPrefer = GT_FALSE; + } + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + +/******************************************************************************* +* gprtGetPhyLinkStatus +* +* DESCRIPTION: +* This routine retrieves the Link status. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* +* OUTPUTS: +* linkStatus - GT_FALSE if link is not established, +* GT_TRUE if link is established. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyLinkStatus +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL *linkStatus +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 u16Data; + GT_PHY_INFO phyInfo; + + DBG_INFO(("gprtGetPhyLinkStatus Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if((retVal=hwGetPhyRegField(dev,hwPort,17,10,1,&u16Data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + BIT_2_BOOL(u16Data,*linkStatus); + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtSetPktGenEnable +* +* DESCRIPTION: +* This routine enables or disables Packet Generator. +* Link should be established first prior to enabling the packet generator, +* and generator will generate packets at the speed of the established link. +* When enables packet generator, the following information should be +* provided: +* Payload Type: either Random or 5AA55AA5 +* Packet Length: either 64 or 1514 bytes +* Error Packet: either Error packet or normal packet +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* en - GT_TRUE to enable, GT_FALSE to disable +* pktInfo - packet information(GT_PG structure pointer), if en is GT_TRUE. +* ignored, if en is GT_FALSE +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPktGenEnable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en, + IN GT_PG *pktInfo +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + GT_BOOL link; + GT_PHY_INFO phyInfo; + GT_U8 page,reg, offset, len; + GT_BOOL autoOn; + GT_U16 pageReg; + + DBG_INFO(("gprtSetPktGenEnable Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(!(phyInfo.flag & GT_PHY_PKT_GENERATOR)) + { + DBG_INFO(("Not Supported.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + switch (phyInfo.pktGenType) + { + case GT_PHY_PKTGEN_TYPE1: /* 30_18.5:2 */ + page = 18; + reg = 30; + offset = 2; + break; + case GT_PHY_PKTGEN_TYPE2: /* 16_6.3:0 */ + page = 6; + reg = 16; + offset = 0; + break; + case GT_PHY_PKTGEN_TYPE3: /* 25.3:0 */ + page = 0; + reg = 25; + offset = 0; + break; + default: + DBG_INFO(("Unknown PKTGEN Type.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (en) + { + if((retVal = gprtGetPhyLinkStatus(dev,port,&link)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if (link == GT_FALSE) + { + DBG_INFO(("Link should be on to run Packet Generator.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + data = 0x8; + + if (pktInfo->payload == GT_PG_PAYLOAD_5AA5) + data |= 0x4; + + if (pktInfo->length == GT_PG_LENGTH_1514) + data |= 0x2; + + if (pktInfo->tx == GT_PG_TX_ERROR) + data |= 0x1; + + len = 4; + } + else + { + data = 0; + len = 1; + offset += 3; + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if((retVal=hwSetPagedPhyRegField(dev,hwPort, + page,reg,offset,len,phyInfo.anyPage,data)) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return retVal; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGetSerdesMode +* +* DESCRIPTION: +* This routine reads Serdes Interface Mode. +* +* INPUTS: +* port - The physical SERDES device address +* (logical port number is also supported for backward comparibility) +* +* OUTPUTS: +* mode - Serdes Interface Mode +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* logical port number is supported only for the devices made production +* before 2009. (88E6131, 88E6122, 88E6108, 88E6161, and 88E6165) +* +*******************************************************************************/ +GT_STATUS gprtGetSerdesMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SERDES_MODE *mode +) +{ + GT_U16 u16Data; /* The register's read data. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetSerdesMode Called.\n")); + + if(!IS_IN_DEV_GROUP(dev,DEV_SERDES_CORE)) + { + return GT_NOT_SUPPORTED; + } + + /* check if input is logical port number */ + hwPort = GT_LPORT_2_PORT(port); + GT_GET_SERDES_PORT(dev,&hwPort); + + if(hwPort > dev->maxPhyNum) + { + /* check if input is physical serdes address */ + if(dev->validSerdesVec & (1<phyRegsSem,OS_WAIT_FOREVER); + + /* Get Phy Register. */ + if(hwGetPhyRegField(dev,hwPort,16,0,2,&u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + *mode = u16Data; + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + + +/******************************************************************************* +* gprtSetSerdesMode +* +* DESCRIPTION: +* This routine sets Serdes Interface Mode. +* +* INPUTS: +* port - The physical SERDES device address +* (logical port number is also supported for backward comparibility) +* mode - Serdes Interface Mode +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* logical port number is supported only for the devices made production +* before 2009. (88E6131, 88E6122, 88E6108, 88E6161, and 88E6165) +* +*******************************************************************************/ +GT_STATUS gprtSetSerdesMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SERDES_MODE mode +) +{ + GT_U16 u16Data; /* The register's read data. */ + GT_U8 hwPort; /* the physical port number */ + GT_STATUS retVal; + + DBG_INFO(("gprtSetSerdesMode Called.\n")); + + if(!IS_IN_DEV_GROUP(dev,DEV_SERDES_CORE)) + { + return GT_NOT_SUPPORTED; + } + + /* check if input is logical port number */ + hwPort = GT_LPORT_2_PORT(port); + GT_GET_SERDES_PORT(dev,&hwPort); + + if(hwPort > dev->maxPhyNum) + { + /* check if input is physical serdes address */ + if(dev->validSerdesVec & (1<phyRegsSem,OS_WAIT_FOREVER); + + u16Data = mode; + + /* Get Phy Register. */ + if(hwSetPhyRegField(dev,hwPort,16,0,2,u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + retVal = hwPhyReset(dev,hwPort,0xFF); + gtSemGive(dev,dev->phyRegsSem); + return retVal; +} + + +/******************************************************************************* +* gprtGetPhyReg +* +* DESCRIPTION: +* This routine reads Phy Registers. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + OUT GT_U16 *data +) +{ + GT_U16 u16Data; /* The register's read data. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPhyReg Called.\n")); + + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* Get Phy Register. */ + if(hwReadPhyReg(dev,hwPort,(GT_U8)regAddr,&u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + *data = u16Data; + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + +/******************************************************************************* +* gprtSetPhyReg +* +* DESCRIPTION: +* This routine writes Phy Registers. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPhyReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + IN GT_U16 data +) +{ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetPhyReg Called.\n")); + + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* Write to Phy Register */ + if(hwWritePhyReg(dev,hwPort,(GT_U8)regAddr,data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + + + +/******************************************************************************* +* gprtGetPagedPhyReg +* +* DESCRIPTION: +* This routine reads phy register of the given page +* +* INPUTS: +* port - logical port to be read +* regAddr - register offset to be read +* page - page number to be read +* +* OUTPUTS: +* data - value of the read register +* +* RETURNS: +* GT_OK - if read successed +* GT_FAIL - if read failed +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gprtGetPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U32 port, + IN GT_U32 regAddr, + IN GT_U32 page, + OUT GT_U16* data +) +{ + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + GT_U8 hwPort; + + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(hwReadPagedPhyReg(dev,hwPort,(GT_U8)page, + (GT_U8)regAddr,0,data) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + +/******************************************************************************* +* gprtSetPagedPhyReg +* +* DESCRIPTION: +* This routine writes a value to phy register of the given page +* +* INPUTS: +* port - logical port to be read +* regAddr - register offset to be read +* page - page number to be read +* data - value of the read register +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - if read successed +* GT_FAIL - if read failed +* +* COMMENTS: +* None. +* +*******************************************************************************/ +GT_STATUS gprtSetPagedPhyReg +( + IN GT_QD_DEV *dev, + IN GT_U32 port, + IN GT_U32 regAddr, + IN GT_U32 page, + IN GT_U16 data +) +{ + GT_PHY_INFO phyInfo; + GT_BOOL autoOn; + GT_U16 pageReg; + GT_U8 hwPort; + + hwPort = GT_LPORT_2_PHY(port); + + gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER); + + /* check if the port is configurable */ + if((phyInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_NOT_SUPPORTED; + } + + if(driverFindPhyInformation(dev,hwPort,&phyInfo) != GT_OK) + { + DBG_INFO(("Unknown PHY device.\n")); + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(driverPagedAccessStart(dev,hwPort,phyInfo.pageType,&autoOn,&pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(hwWritePagedPhyReg(dev,hwPort,(GT_U8)page, + (GT_U8)regAddr,0,data) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + if(driverPagedAccessStop(dev,hwPort,phyInfo.pageType,autoOn,pageReg) != GT_OK) + { + gtSemGive(dev,dev->phyRegsSem); + return GT_FAIL; + } + + gtSemGive(dev,dev->phyRegsSem); + return GT_OK; +} + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyInt.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyInt.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyInt.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPhyInt.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,279 @@ +#include + +/******************************************************************************** +* gtPhyInt.h +* +* DESCRIPTION: +* API definitions for PHY interrupt handling +* +* DEPENDENCIES: +* None. +* +* FILE REVISION NUMBER: +* $Revision: 10 $ +*******************************************************************************/ + +#include +#include +#include +#include + +/******************************************************************************* +* gprtPhyIntEnable +* +* DESCRIPTION: +* Enable/Disable one PHY Interrupt +* This register determines whether the INT# pin is asserted when an interrupt +* event occurs. When an interrupt occurs, the corresponding bit is set and +* remains set until register 19 is read via the SMI. When interrupt enable +* bits are not set in register 18, interrupt status bits in register 19 are +* still set when the corresponding interrupt events occur. However, the INT# +* is not asserted. +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* intType - the type of interrupt to enable/disable. any combination of +* GT_SPEED_CHANGED, +* GT_DUPLEX_CHANGED, +* GT_PAGE_RECEIVED, +* GT_AUTO_NEG_COMPLETED, +* GT_LINK_STATUS_CHANGED, +* GT_SYMBOL_ERROR, +* GT_FALSE_CARRIER, +* GT_FIFO_FLOW, +* GT_CROSSOVER_CHANGED, ( Copper only ) +* GT_DOWNSHIFT_DETECT, ( for 1000M Copper only ) +* GT_ENERGY_DETECT, ( for 1000M Copper only ) +* GT_POLARITY_CHANGED, and ( Copper only ) +* GT_JABBER (Copper only ) +* +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* For 88E6131, 88E6122, and 88E6108 devices, Serdes port can be accessed using +* logical port number. +* For 88E6161 and 88E6165 devices, Serdes port 5 (address 0xD) can be accessed +* using logical port number, but not port 4 (since port 4 could be an internal +* PHY.) +*******************************************************************************/ + + +GT_STATUS gprtPhyIntEnable +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +IN GT_U16 intType +) +{ + GT_STATUS retVal; + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtPhyIntEnable Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + + if((IS_IN_DEV_GROUP(dev,DEV_SERDES_CORE)) && (hwPort > 3)) + { + if(!(dev->validSerdesVec & (1 << hwPort))) + { + if(!((IS_IN_DEV_GROUP(dev,DEV_88E6165_FAMILY)) && (hwPort == 4))) + GT_GET_SERDES_PORT(dev,&hwPort); + } + if(hwPort >= dev->maxPhyNum) + { + return GT_NOT_SUPPORTED; + } + } + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + return GT_NOT_SUPPORTED; + } + + retVal = hwWritePhyReg(dev,hwPort, QD_PHY_INT_ENABLE_REG, intType); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; + +} + +/******************************************************************************* +* gprtGetPhyIntStatus +* +* DESCRIPTION: +* Check to see if a specific type of interrupt occured +* +* INPUTS: +* port - The logical port number, unless SERDES device is accessed +* The physical address, if SERDES device is accessed +* intType - the type of interrupt which causes an interrupt. +* any combination of +* GT_SPEED_CHANGED, +* GT_DUPLEX_CHANGED, +* GT_PAGE_RECEIVED, +* GT_AUTO_NEG_COMPLETED, +* GT_LINK_STATUS_CHANGED, +* GT_SYMBOL_ERROR, +* GT_FALSE_CARRIER, +* GT_FIFO_FLOW, +* GT_CROSSOVER_CHANGED, ( Copper only ) +* GT_DOWNSHIFT_DETECT, ( for 1000M Copper only ) +* GT_ENERGY_DETECT, ( for 1000M Copper only ) +* GT_POLARITY_CHANGED, and ( Copper only ) +* GT_JABBER (Copper only ) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* For 88E6131, 88E6122, and 88E6108 devices, Serdes port can be accessed using +* logical port number. +* For 88E6161 and 88E6165 devices, Serdes port 5 (address 0xD) can be accessed +* using logical port number, but not port 4 (since port 4 could be an internal +* PHY.) +* +*******************************************************************************/ + +GT_STATUS gprtGetPhyIntStatus +( +IN GT_QD_DEV *dev, +IN GT_LPORT port, +OUT GT_U16* intType +) +{ + GT_STATUS retVal; + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPhyIntStatus Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PHY(port); + if((IS_IN_DEV_GROUP(dev,DEV_SERDES_CORE)) && (hwPort > 3)) + { + if(!(dev->validSerdesVec & (1 << hwPort))) + { + if(!((IS_IN_DEV_GROUP(dev,DEV_88E6165_FAMILY)) && (hwPort == 4))) + GT_GET_SERDES_PORT(dev,&hwPort); + } + if(hwPort >= dev->maxPhyNum) + { + return GT_NOT_SUPPORTED; + } + } + + /* check if the port is configurable */ + if(!IS_CONFIGURABLE_PHY(dev,hwPort)) + { + return GT_NOT_SUPPORTED; + } + + retVal = hwReadPhyReg(dev,hwPort, QD_PHY_INT_STATUS_REG, intType); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtGetPhyIntPortSummary +* +* DESCRIPTION: +* Lists the ports that have active interrupts. It provides a quick way to +* isolate the interrupt so that the MAC or switch does not have to poll the +* interrupt status register (19) for all ports. Reading this register does not +* de-assert the INT# pin +* +* INPUTS: +* none +* +* OUTPUTS: +* GT_U8 *intPortMask - bit Mask with the bits set for the corresponding +* phys with active interrupt. E.g., the bit number 0 and 2 are set when +* port number 0 and 2 have active interrupt +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* 88E3081 data sheet register 20 +* For 88E6165, 88E6375 devices, geventGetDevIntStatus should be used instead. +* +*******************************************************************************/ + +GT_STATUS gprtGetPhyIntPortSummary +( +IN GT_QD_DEV *dev, +OUT GT_U16 *intPortMask +) +{ + GT_STATUS retVal; + GT_U8 hwPort; /* the physical port number */ + GT_U16 portVec; + + DBG_INFO(("gprtGetPhyIntPortSummary Called.\n")); + + /* translate LPORT 0 to hardware port */ + hwPort = GT_LPORT_2_PORT(0); + + *intPortMask=0; + + if (IS_IN_DEV_GROUP(dev,DEV_DEV_PHY_INTERRUPT)) + { + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_INTERNAL_GPHY)) + { + /* get the interrupt port summary from global register */ + retVal = hwGetGlobal2RegField(dev,QD_REG_PHYINT_SOURCE,0,dev->maxPorts,&portVec); + GT_GIG_PHY_INT_MASK(dev,portVec); + *intPortMask = (GT_U16)GT_PORTVEC_2_LPORTVEC(portVec); + } + else + { + /* get the interrupt port summary from phy */ + retVal = hwReadPhyReg(dev,hwPort, QD_PHY_INT_PORT_SUMMARY_REG, &portVec); + *intPortMask = (GT_U16)GT_PORTVEC_2_LPORTVEC(portVec); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; + +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPIRL2.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPIRL2.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPIRL2.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPIRL2.c 2011-04-04 13:57:35.095596260 -0400 @@ -0,0 +1,1682 @@ +#include + +/******************************************************************************* +* gtPIRL2.c +* +* DESCRIPTION: +* API definitions for Port based PIRL Resources +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +*******************************************************************************/ + +#include +#include +#include +#include + +/****************************************************************************/ +/* PIRL operation function declaration. */ +/****************************************************************************/ +static GT_STATUS pirl2OperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_OPERATION pirlOp, + INOUT GT_PIRL2_OP_DATA *opData +); + +static GT_STATUS pirl2Initialize +( + IN GT_QD_DEV *dev +); + +static GT_STATUS pirl2InitIRLResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes +); + +static GT_STATUS pirl2DisableIRLResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes +); + +static GT_STATUS pirl2DataToResource +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_DATA *pirlData, + OUT GT_PIRL2_RESOURCE *res +); + +static GT_STATUS pirl2ResourceToData +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_RESOURCE *res, + OUT GT_PIRL2_DATA *pirlData +); + +static GT_STATUS pirl2WriteResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + IN GT_PIRL2_RESOURCE *res +); + +static GT_STATUS pirl2ReadResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + OUT GT_PIRL2_RESOURCE *res +); + +static GT_STATUS pirl2WriteTSMResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + IN GT_PIRL2_TSM_RESOURCE *res +); + +static GT_STATUS pirl2ReadTSMResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + OUT GT_PIRL2_TSM_RESOURCE *res +); + +/******************************************************************************* +* gpirl2WriteResource +* +* DESCRIPTION: +* This routine writes resource bucket parameters to the given resource +* of the port. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* pirlData - PIRL resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2WriteResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + IN GT_PIRL2_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_PIRL2_RESOURCE pirlRes; + GT_U32 irlPort; /* the physical port number */ + GT_U32 maxRes; + + DBG_INFO(("gpirl2WriteResource Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL2_RESOURCE)) + { + maxRes = 2; + } + else + { + maxRes = 5; + } + + if (irlRes >= maxRes) + { + DBG_INFO(("GT_BAD_PARAM irlRes\n")); + return GT_BAD_PARAM; + } + + irlPort = (GT_U32)GT_LPORT_2_PORT(port); + if (irlPort == GT_INVALID_PORT) + { + DBG_INFO(("GT_BAD_PARAM port\n")); + return GT_BAD_PARAM; + } + + /* Initialize internal counters */ + retVal = pirl2InitIRLResource(dev,irlPort,irlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + /* Program the Ingress Rate Resource Parameters */ + retVal = pirl2DataToResource(dev,pirlData,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Data to PIRL Resource conversion failed.\n")); + return retVal; + } + + retVal = pirl2WriteResource(dev,irlPort,irlRes,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + +/******************************************************************************* +* gpirl2ReadResource +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2ReadResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + OUT GT_PIRL2_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_U32 irlPort; + GT_PIRL2_RESOURCE pirlRes; + GT_U32 maxRes; + + DBG_INFO(("gpirl2ReadResource Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL2_RESOURCE)) + { + maxRes = 2; + } + else + { + maxRes = 5; + } + + if (irlRes >= maxRes) + { + DBG_INFO(("GT_BAD_PARAM irlRes\n")); + return GT_BAD_PARAM; + } + + irlPort = (GT_U32)GT_LPORT_2_PORT(port); + if (irlPort == GT_INVALID_PORT) + { + DBG_INFO(("GT_BAD_PARAM port\n")); + return GT_BAD_PARAM; + } + + /* Read the Ingress Rate Resource Parameters */ + retVal = pirl2ReadResource(dev,irlPort,irlRes,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Read Resource failed.\n")); + return retVal; + } + + retVal = pirl2ResourceToData(dev,&pirlRes,pirlData); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Resource to PIRL Data conversion failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpirl2DisableResource +* +* DESCRIPTION: +* This routine disables Ingress Rate Limiting for the given bucket. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 4). +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2DisableResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes +) +{ + GT_STATUS retVal; + GT_U32 irlPort; + GT_U32 maxRes; + + DBG_INFO(("gpirl2Dectivate Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL2_RESOURCE)) + { + maxRes = 2; + } + else + { + maxRes = 5; + } + + if (irlRes >= maxRes) + { + DBG_INFO(("GT_BAD_PARAM irlRes\n")); + return GT_BAD_PARAM; + } + + irlPort = (GT_U32)GT_LPORT_2_PORT(port); + if (irlPort == GT_INVALID_PORT) + { + DBG_INFO(("GT_BAD_PARAM port\n")); + return GT_BAD_PARAM; + } + + /* disable irl resource */ + retVal = pirl2DisableIRLResource(dev, irlPort, irlRes); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gpirl2SetCurTimeUpInt +* +* DESCRIPTION: +* This function sets the current time update interval. +* Please contact FAE for detailed information. +* +* INPUTS: +* upInt - updata interval (0 ~ 7) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirl2SetCurTimeUpInt +( + IN GT_QD_DEV *dev, + IN GT_U32 upInt +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (upInt > 0x7) + return GT_BAD_PARAM; + + op = PIRL_READ_RESOURCE; + + opData.irlPort = 0xF; + opData.irlRes = 0; + opData.irlReg = 1; + opData.irlData = 0; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + op = PIRL_WRITE_RESOURCE; + opData.irlData = (opData.irlData & 0xFFF8) | (GT_U16)upInt; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + return GT_OK; +} + + +/******************************************************************************* +* gpirl2WriteTSMResource +* +* DESCRIPTION: +* This routine writes rate resource bucket parameters in Time Slot Metering +* mode to the given resource of the port. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 1). +* pirlData - PIRL TSM resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Only Resource 0 and 1 can be supported for TSM Mode. +* +*******************************************************************************/ +GT_STATUS gpirl2WriteTSMResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + IN GT_PIRL2_TSM_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_PIRL2_TSM_RESOURCE pirlRes; + GT_U32 irlPort; /* the physical port number */ + GT_U32 maxRes; + GT_U32 cbs, cts, i, rate; + + DBG_INFO(("gpirl2WriteTSMResource Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_TSM_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + maxRes = 2; + + if (irlRes >= maxRes) + { + DBG_INFO(("GT_BAD_PARAM irlRes\n")); + return GT_BAD_PARAM; + } + + irlPort = (GT_U32)GT_LPORT_2_PORT(port); + if (irlPort == GT_INVALID_PORT) + { + DBG_INFO(("GT_BAD_PARAM port\n")); + return GT_BAD_PARAM; + } + + /* Initialize internal counters */ + retVal = pirl2InitIRLResource(dev,irlPort,irlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + if (pirlData->customSetup.isValid == GT_TRUE) + { + pirlRes.cbsLimit = pirlData->customSetup.cbsLimit; + pirlRes.ctsIntv = pirlData->customSetup.ctsIntv; + pirlRes.ebsLimit = pirlData->customSetup.ebsLimit; + pirlRes.actionMode = pirlData->customSetup.actionMode; + } + else + { + /* convert ingressRate to cbsLimit and ctsIntv */ + cts = 1; + cbs = 0; + i = 3; + rate = pirlData->ingressRate; + while(cts < 16) + { + cbs = TSM_GET_CBS(rate, cts); + if ((cbs == 0) || (cbs <= 0xFFFF)) + break; + cts += i; + i = cts; + } + + if (cts > 16) + { + return GT_BAD_PARAM; + } + + switch (cts) + { + case 1: + pirlRes.ctsIntv = 3; + break; + case 4: + pirlRes.ctsIntv = 2; + break; + case 8: + pirlRes.ctsIntv = 1; + break; + case 16: + pirlRes.ctsIntv = 0; + break; + default: + return GT_FAIL; + } + + pirlRes.cbsLimit = cbs; + pirlRes.ebsLimit = 0xFFFF; + pirlRes.actionMode = 1; + } + + pirlRes.mgmtNrlEn = pirlData->mgmtNrlEn; + pirlRes.priMask = pirlData->priMask; + pirlRes.tsmMode = GT_TRUE; + + if (pirlData->tsmMode == GT_FALSE) + { + pirlRes.tsmMode = 0; + pirlRes.cbsLimit = 0; + pirlRes.ctsIntv = 0; + pirlRes.ebsLimit = 0; + pirlRes.actionMode = 0; + pirlRes.mgmtNrlEn = 0; + pirlRes.priMask = 0; + } + + retVal = pirl2WriteTSMResource(dev,irlPort,irlRes,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + +/******************************************************************************* +* gpirl2ReadTSMResource +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* Returned ingressRate would be rough number. Instead, customSetup will +* have the exact configured value. +* +* INPUTS: +* port - logical port number. +* irlRes - bucket to be used (0 ~ 1). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* Only Resource 0 and 1 can be supported for TSM Mode. +* +*******************************************************************************/ +GT_STATUS gpirl2ReadTSMResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 irlRes, + OUT GT_PIRL2_TSM_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_U32 irlPort; + GT_PIRL2_TSM_RESOURCE pirlRes; + GT_U32 maxRes, cbs, cts; + + DBG_INFO(("gpirl2ReadTSMResource Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_TSM_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + maxRes = 2; + + if (irlRes >= maxRes) + { + DBG_INFO(("GT_BAD_PARAM irlRes\n")); + return GT_BAD_PARAM; + } + + irlPort = (GT_U32)GT_LPORT_2_PORT(port); + if (irlPort == GT_INVALID_PORT) + { + DBG_INFO(("GT_BAD_PARAM port\n")); + return GT_BAD_PARAM; + } + + /* Read the Ingress Rate Resource Parameters */ + retVal = pirl2ReadTSMResource(dev,irlPort,irlRes,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Read Resource failed.\n")); + return retVal; + } + + if (pirlRes.tsmMode == 0) + { + /* TMS Mode is not enabled */ + pirlData->tsmMode = GT_FALSE; + pirlData->ingressRate = 0; + pirlData->mgmtNrlEn = 0; + pirlData->priMask = 0; + pirlData->customSetup.isValid = 0; + pirlData->customSetup.cbsLimit = 0; + pirlData->customSetup.ctsIntv = 0; + pirlData->customSetup.ebsLimit = 0; + pirlData->customSetup.actionMode = 0; + return GT_OK; + } + + cbs = pirlRes.cbsLimit; + switch (pirlRes.ctsIntv) + { + case 0: + cts = 16; + break; + case 1: + cts = 8; + break; + case 2: + cts = 4; + break; + case 3: + cts = 1; + break; + default: + return GT_FAIL; + } + + pirlData->ingressRate = TSM_GET_RATE(cbs,cts); + + pirlData->mgmtNrlEn = pirlRes.mgmtNrlEn; + pirlData->priMask = pirlRes.priMask; + + pirlData->customSetup.isValid = GT_TRUE; + pirlData->customSetup.cbsLimit = pirlRes.cbsLimit; + pirlData->customSetup.ctsIntv = pirlRes.ctsIntv; + pirlData->customSetup.ebsLimit = pirlRes.ebsLimit; + pirlData->customSetup.actionMode = pirlRes.actionMode; + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + + +/****************************************************************************/ +/* Internal functions. */ +/****************************************************************************/ + +/******************************************************************************* +* gpirl2Initialize +* +* DESCRIPTION: +* This routine initializes PIRL Resources. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirl2Initialize +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = pirl2Initialize(dev); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + + +/******************************************************************************* +* pirl2OperationPerform +* +* DESCRIPTION: +* This function accesses Ingress Rate Command Register and Data Register. +* +* INPUTS: +* pirlOp - The stats operation bits to be written into the stats +* operation register. +* +* OUTPUTS: +* pirlData - points to the data storage where the MIB counter will be saved. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirl2OperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_OPERATION pirlOp, + INOUT GT_PIRL2_OP_DATA *opData +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data; /* temporary Data storage */ + + gtSemTake(dev,dev->pirlRegsSem,OS_WAIT_FOREVER); + + /* Wait until the pirl in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + /* Set the PIRL Operation register */ + switch (pirlOp) + { + case PIRL_INIT_ALL_RESOURCE: + data = (1 << 15) | (PIRL_INIT_ALL_RESOURCE << 12); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + case PIRL_INIT_RESOURCE: + data = (GT_U16)((1 << 15) | (PIRL_INIT_RESOURCE << 12) | + (opData->irlPort << 8) | + (opData->irlRes << 5)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + + case PIRL_WRITE_RESOURCE: + data = (GT_U16)opData->irlData; + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_DATA,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + + data = (GT_U16)((1 << 15) | (PIRL_WRITE_RESOURCE << 12) | + (opData->irlPort << 8) | + (opData->irlRes << 5) | + (opData->irlReg & 0xF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + + case PIRL_READ_RESOURCE: + data = (GT_U16)((1 << 15) | (PIRL_READ_RESOURCE << 12) | + (opData->irlPort << 8) | + (opData->irlRes << 5) | + (opData->irlReg & 0xF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + retVal = hwReadGlobal2Reg(dev,QD_REG_INGRESS_RATE_DATA,&data); + opData->irlData = (GT_U32)data; + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + + default: + + gtSemGive(dev,dev->pirlRegsSem); + return GT_FAIL; + } + + /* Wait until the pirl in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + gtSemGive(dev,dev->pirlRegsSem); + return retVal; +} + +/* + * Initialize all PIRL resources to the inital state. +*/ +static GT_STATUS pirl2Initialize +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL2_OPERATION op; + + op = PIRL_INIT_ALL_RESOURCE; + + retVal = pirl2OperationPerform(dev, op, NULL); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + retVal = gpirl2SetCurTimeUpInt(dev,4); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + } + + return retVal; +} + +/* + * Initialize the selected PIRL resource to the inital state. + * This function initializes only the BSM structure for the IRL Unit. +*/ +static GT_STATUS pirl2InitIRLResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + + op = PIRL_INIT_RESOURCE; + opData.irlPort = irlPort; + opData.irlRes = irlRes; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + return retVal; +} + +/* + * Disable the selected PIRL resource. +*/ +static GT_STATUS pirl2DisableIRLResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + int i; + + op = PIRL_WRITE_RESOURCE; + + for(i=0; i<8; i++) + { + opData.irlPort = irlPort; + opData.irlRes = irlRes; + opData.irlReg = i; + opData.irlData = 0; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + } + + return GT_OK; +} + +/* + * convert PIRL Data structure to PIRL Resource structure. + * if PIRL Data is not valid, return GT_BAD_PARARM; +*/ +static GT_STATUS pirl2DataToResource +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_DATA *pirlData, + OUT GT_PIRL2_RESOURCE *res +) +{ + GT_U32 typeMask; + GT_U32 data; + + gtMemSet((void*)res,0,sizeof(GT_PIRL2_RESOURCE)); + + data = (GT_U32)(pirlData->accountQConf|pirlData->accountFiltered| + pirlData->mgmtNrlEn|pirlData->saNrlEn|pirlData->daNrlEn| + pirlData->samplingMode); + + if (data > 1) + { + DBG_INFO(("GT_BAD_PARAM (Boolean)\n")); + return GT_BAD_PARAM; + } + + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL2_RESOURCE)) + { + if (pirlData->samplingMode != GT_FALSE) + { + DBG_INFO(("GT_BAD_PARAM (sampling mode)\n")); + return GT_BAD_PARAM; + } + } + + res->accountQConf = pirlData->accountQConf; + res->accountFiltered = pirlData->accountFiltered; + res->mgmtNrlEn = pirlData->mgmtNrlEn; + res->saNrlEn = pirlData->saNrlEn; + res->daNrlEn = pirlData->daNrlEn; + res->samplingMode = pirlData->samplingMode; + + switch(pirlData->actionMode) + { + case PIRL_ACTION_ACCEPT: + case PIRL_ACTION_USE_LIMIT_ACTION: + res->actionMode = pirlData->actionMode; + break; + default: + DBG_INFO(("GT_BAD_PARAM actionMode\n")); + return GT_BAD_PARAM; + } + + switch(pirlData->ebsLimitAction) + { + case ESB_LIMIT_ACTION_DROP: + case ESB_LIMIT_ACTION_FC: + res->ebsLimitAction = pirlData->ebsLimitAction; + break; + default: + DBG_INFO(("GT_BAD_PARAM ebsLimitAction\n")); + return GT_BAD_PARAM; + } + + switch(pirlData->fcDeassertMode) + { + case GT_PIRL_FC_DEASSERT_EMPTY: + case GT_PIRL_FC_DEASSERT_CBS_LIMIT: + res->fcDeassertMode = pirlData->fcDeassertMode; + break; + default: + if(res->ebsLimitAction != ESB_LIMIT_ACTION_FC) + { + res->fcDeassertMode = GT_PIRL_FC_DEASSERT_EMPTY; + break; + } + DBG_INFO(("GT_BAD_PARAM fcDeassertMode\n")); + return GT_BAD_PARAM; + } + + if(pirlData->customSetup.isValid == GT_TRUE) + { + res->ebsLimit = pirlData->customSetup.ebsLimit; + res->cbsLimit = pirlData->customSetup.cbsLimit; + res->bktIncrement = pirlData->customSetup.bktIncrement; + res->bktRateFactor = pirlData->customSetup.bktRateFactor; + } + else + { + if(pirlData->ingressRate == 0) + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + + if(pirlData->ingressRate < 1000) /* less than 1Mbps */ + { + /* it should be divided by 64 */ + if(pirlData->ingressRate % 64) + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + res->bktRateFactor = pirlData->ingressRate/64; + } + else if(pirlData->ingressRate < 10000) /* less than or equal to 10Mbps */ + { + /* it should be divided by 1000 */ + if(pirlData->ingressRate % 1000) + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + res->bktRateFactor = pirlData->ingressRate/128 + ((pirlData->ingressRate % 128)?1:0); + } + else if(pirlData->ingressRate < 100000) /* less than or equal to 100Mbps */ + { + /* it should be divided by 1000 */ + if(pirlData->ingressRate % 1000) + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + res->bktRateFactor = pirlData->ingressRate/1000; + } + else if(pirlData->ingressRate <= 200000) /* less than or equal to 200Mbps */ + { + /* it should be divided by 10000 */ + if(pirlData->ingressRate % 10000) + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + res->bktRateFactor = pirlData->ingressRate/1000; + } + else + { + DBG_INFO(("GT_BAD_PARAM ingressRate(%i)\n",pirlData->ingressRate)); + return GT_BAD_PARAM; + } + + res->ebsLimit = RECOMMENDED_ESB_LIMIT(dev, pirlData->ingressRate); + res->cbsLimit = RECOMMENDED_CBS_LIMIT(dev, pirlData->ingressRate); + res->bktIncrement = RECOMMENDED_BUCKET_INCREMENT(dev, pirlData->ingressRate); + } + + switch(pirlData->bktRateType) + { + case BUCKET_TYPE_TRAFFIC_BASED: + res->bktRateType = pirlData->bktRateType; + + typeMask = 0x7FFF; + + if (pirlData->bktTypeMask > typeMask) + { + DBG_INFO(("GT_BAD_PARAM bktTypeMask(%#x)\n",pirlData->bktTypeMask)); + return GT_BAD_PARAM; + } + + res->bktTypeMask = pirlData->bktTypeMask; + + if (pirlData->bktTypeMask & BUCKET_TRAFFIC_ARP) + { + res->bktTypeMask &= ~BUCKET_TRAFFIC_ARP; + res->bktTypeMask |= 0x80; + } + + if (pirlData->priORpt > 1) + { + DBG_INFO(("GT_BAD_PARAM rpiORpt\n")); + return GT_BAD_PARAM; + } + + res->priORpt = pirlData->priORpt; + + if (pirlData->priMask >= (1 << 4)) + { + DBG_INFO(("GT_BAD_PARAM priMask(%#x)\n",pirlData->priMask)); + return GT_BAD_PARAM; + } + + res->priMask = pirlData->priMask; + + break; + + case BUCKET_TYPE_RATE_BASED: + res->bktRateType = pirlData->bktRateType; + res->bktTypeMask = pirlData->bktTypeMask; + res->priORpt = pirlData->priORpt; + res->priMask = pirlData->priMask; + break; + + default: + DBG_INFO(("GT_BAD_PARAM bktRateType(%#x)\n",pirlData->bktRateType)); + return GT_BAD_PARAM; + } + + switch(pirlData->byteTobeCounted) + { + case GT_PIRL2_COUNT_FRAME: + case GT_PIRL2_COUNT_ALL_LAYER1: + case GT_PIRL2_COUNT_ALL_LAYER2: + case GT_PIRL2_COUNT_ALL_LAYER3: + res->byteTobeCounted = pirlData->byteTobeCounted; + break; + default: + DBG_INFO(("GT_BAD_PARAM byteTobeCounted(%#x)\n",pirlData->byteTobeCounted)); + return GT_BAD_PARAM; + } + + return GT_OK; +} + +/* + * convert PIRL Resource structure to PIRL Data structure. +*/ +static GT_STATUS pirl2ResourceToData +( + IN GT_QD_DEV *dev, + IN GT_PIRL2_RESOURCE *res, + OUT GT_PIRL2_DATA *pirlData +) +{ + GT_U32 rate; + GT_U32 factor; + + pirlData->accountQConf = res->accountQConf; + pirlData->accountFiltered = res->accountFiltered; + pirlData->mgmtNrlEn = res->mgmtNrlEn; + pirlData->saNrlEn = res->saNrlEn; + pirlData->daNrlEn = res->daNrlEn; + pirlData->samplingMode = res->samplingMode; + pirlData->ebsLimitAction = res->ebsLimitAction; + pirlData->actionMode = res->actionMode; + pirlData->fcDeassertMode = res->fcDeassertMode; + + pirlData->customSetup.isValid = GT_FALSE; + + FACTOR_FROM_BUCKET_INCREMENT(dev,res->bktIncrement,factor); + + rate = res->bktRateFactor * factor; + if(factor == 128) + { + pirlData->ingressRate = rate - (rate % 1000); + } + else if (factor == 0) + { + pirlData->ingressRate = 0; + pirlData->customSetup.isValid = GT_TRUE; + pirlData->customSetup.ebsLimit = res->ebsLimit; + pirlData->customSetup.cbsLimit = res->cbsLimit; + pirlData->customSetup.bktIncrement = res->bktIncrement; + pirlData->customSetup.bktRateFactor = res->bktRateFactor; + } + else + { + pirlData->ingressRate = rate; + } + + pirlData->bktRateType = res->bktRateType; + pirlData->bktTypeMask = res->bktTypeMask; + + if (pirlData->bktTypeMask & 0x80) + { + res->bktTypeMask &= ~0x80; + res->bktTypeMask |= BUCKET_TRAFFIC_ARP; + } + + pirlData->priORpt = res->priORpt; + pirlData->priMask = res->priMask; + + pirlData->byteTobeCounted = res->byteTobeCounted; + + return GT_OK; +} + +/******************************************************************************* +* pirl2WriteResource +* +* DESCRIPTION: +* This function writes IRL Resource to BCM (Bucket Configuration Memory) +* +* INPUTS: +* irlPort - physical port number. +* irlRes - bucket to be used (0 ~ 4). +* res - IRL Resource data +* +* OUTPUTS: +* Nont. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirl2WriteResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + IN GT_PIRL2_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + int i; + + op = PIRL_WRITE_RESOURCE; + + /* reg0 data */ + data[0] = (GT_U16)((res->bktRateType << 15) | /* Bit[15] : Bucket Rate Type */ + (res->bktTypeMask << 0 )); /* Bit[14:0] : Traffic Type */ + + /* reg1 data */ + data[1] = (GT_U16)res->bktIncrement; /* Bit[11:0] : Bucket Increment */ + + /* reg2 data */ + data[2] = (GT_U16)res->bktRateFactor; /* Bit[15:0] : Bucket Rate Factor */ + + /* reg3 data */ + data[3] = (GT_U16)((res->cbsLimit & 0xFFF) << 4)| /* Bit[15:4] : CBS Limit[11:0] */ + (res->byteTobeCounted << 2); /* Bit[3:0] : Bytes to be counted */ + + /* reg4 data */ + data[4] = (GT_U16)(res->cbsLimit >> 12); /* Bit[11:0] : CBS Limit[23:12] */ + + /* reg5 data */ + data[5] = (GT_U16)(res->ebsLimit & 0xFFFF); /* Bit[15:0] : EBS Limit[15:0] */ + + /* reg6 data */ + data[6] = (GT_U16)((res->ebsLimit >> 16) | /* Bit[7:0] : EBS Limit[23:16] */ + (res->samplingMode << 11) | /* Bit[11] : Sampling Mode */ + (res->ebsLimitAction << 12) | /* Bit[12] : EBS Limit Action */ + (res->actionMode << 13) | /* Bit[13] : Action Mode */ + (res->fcDeassertMode << 14)); /* Bit[14] : Flow control mode */ + + /* reg7 data */ + data[7] = (GT_U16)((res->daNrlEn) | /* Bit[0] : DA Nrl En */ + (res->saNrlEn << 1) | /* Bit[1] : SA Nrl En */ + (res->mgmtNrlEn << 2) | /* Bit[2] : MGMT Nrl En */ + (res->priMask << 8) | /* Bit[11:8] : Priority Queue Mask */ + (res->priORpt << 12) | /* Bit[12] : Priority OR PacketType */ + (res->accountFiltered << 14)| /* Bit[14] : Account Filtered */ + (res->accountQConf << 15)); /* Bit[15] : Account QConf */ + + for(i=0; i<8; i++) + { + opData.irlPort = irlPort; + opData.irlRes = irlRes; + opData.irlReg = i; + opData.irlData = data[i]; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + } + + return GT_OK; +} + + +/******************************************************************************* +* pirl2ReadResource +* +* DESCRIPTION: +* This function reads IRL Resource from BCM (Bucket Configuration Memory) +* +* INPUTS: +* irlPort - physical port number. +* irlRes - bucket to be used (0 ~ 4). +* +* OUTPUTS: +* res - IRL Resource data +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirl2ReadResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + OUT GT_PIRL2_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + int i; + + op = PIRL_READ_RESOURCE; + + for(i=0; i<8; i++) + { + opData.irlPort = irlPort; + opData.irlRes = irlRes; + opData.irlReg = i; + opData.irlData = 0; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + data[i] = (GT_U16)opData.irlData; + } + + + /* reg0 data */ + res->bktRateType = (data[0] >> 15) & 0x1; + res->bktTypeMask = (data[0] >> 0) & 0x7FFF; + + /* reg1 data */ + res->bktIncrement = data[1] & 0xFFF; + + /* reg2 data */ + res->bktRateFactor = data[2] & 0xFFFF; + + /* reg3,4 data */ + res->byteTobeCounted = (data[3] >> 2) & 0x3; + res->cbsLimit = ((data[3] >> 4) & 0xFFF) | ((data[4] & 0xFFF) << 12); + + /* reg5,6 data */ + res->ebsLimit = data[5] | ((data[6] & 0xFF) << 16); + + /* reg6 data */ + res->samplingMode = (data[6] >> 11) & 0x1; + res->ebsLimitAction = (data[6] >> 12) & 0x1; + res->actionMode = (data[6] >> 13) & 0x1; + res->fcDeassertMode = (data[6] >> 14) & 0x1; + + /* reg7 data */ + res->daNrlEn = (data[7] >> 0) & 0x1; + res->saNrlEn = (data[7] >> 1) & 0x1; + res->mgmtNrlEn = (data[7] >> 2) & 0x1; + res->priMask = (data[7] >> 8) & 0xF; + res->priORpt = (data[7] >> 12) & 0x1; + res->accountFiltered = (data[7] >> 14) & 0x1; + res->accountQConf = (data[7] >> 15) & 0x1; + + return GT_OK; +} + + +/******************************************************************************* +* pirl2WriteTSMResource +* +* DESCRIPTION: +* This function writes IRL Resource to BCM (Bucket Configuration Memory) +* in Time Slot Metering Mode. +* +* INPUTS: +* irlPort - physical port number. +* irlRes - bucket to be used (0 ~ 1). +* res - IRL Resource data +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirl2WriteTSMResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + IN GT_PIRL2_TSM_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + int i; + + op = PIRL_WRITE_RESOURCE; + + /* reg0 data */ + data[0] = 0; + + /* reg1 data */ + data[1] = 0; + + /* reg2 data */ + data[2] = 0; + + /* reg3 data */ + data[3] = (GT_U16)(((res->cbsLimit & 0xFFF) << 4)| /* Bit[15:4] : CBS Limit[11:0] */ + (0x2 << 2)); /* Bit[3:0] : Bytes to be counted */ + + /* reg4 data */ + data[4] = (GT_U16)(res->cbsLimit >> 12); /* Bit[11:0] : CBS Limit[23:12] */ + + /* reg5 data */ + data[5] = (GT_U16)(res->ebsLimit & 0xFFFF); /* Bit[15:0] : EBS Limit[15:0] */ + + /* reg6 data */ + data[6] = (GT_U16)(res->actionMode << 13); /* Bit[13] : Action Mode */ + + /* reg7 data */ + data[7] = (GT_U16)((res->tsmMode << 7) | /* Bit[7] : TSM Mode */ + (res->mgmtNrlEn << 2) | /* Bit[2] : MGMT Nrl En */ + (res->priMask << 8) | /* Bit[11:8] : Priority Queue Mask */ + (res->ctsIntv << 4)); /* Bit[5:4] : Class Timer Slot Interval */ + + for(i=0; i<8; i++) + { + opData.irlPort = irlPort; + opData.irlRes = irlRes; + opData.irlReg = i; + opData.irlData = data[i]; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + } + + return GT_OK; +} + + +/******************************************************************************* +* pirl2ReadTSMResource +* +* DESCRIPTION: +* This function reads IRL Resource from BCM (Bucket Configuration Memory) +* in Time Slot Metering Mode. +* +* INPUTS: +* irlPort - physical port number. +* irlRes - bucket to be used (0 ~ 1). +* +* OUTPUTS: +* res - IRL Resource data +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirl2ReadTSMResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + OUT GT_PIRL2_TSM_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + int i; + + op = PIRL_READ_RESOURCE; + + for(i=0; i<8; i++) + { + opData.irlPort = irlPort; + opData.irlRes = irlRes; + opData.irlReg = i; + opData.irlData = 0; + + retVal = pirl2OperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + data[i] = (GT_U16)opData.irlData; + } + + res->tsmMode = data[7] & (1<<7); + + if(res->tsmMode == GT_FALSE) + { + /* TMS mode is not set */ + res->cbsLimit = 0; + res->ebsLimit = 0; + res->actionMode = 0; + res->mgmtNrlEn = 0; + res->priMask = 0; + res->ctsIntv = 0; + + return GT_OK; + } + + /* reg3,4 data */ + res->cbsLimit = ((data[3] >> 4) & 0xFFF) | ((data[4] & 0xF) << 12); + + /* reg5,6 data */ + res->ebsLimit = data[5]; + + /* reg6 data */ + res->actionMode = (data[6] >> 13) & 0x1; + + /* reg7 data */ + res->mgmtNrlEn = (data[7] >> 2) & 0x1; + res->priMask = (data[7] >> 8) & 0xF; + res->ctsIntv = (data[7] >> 4) & 0x3; + + return GT_OK; +} + +#define PIRL2_DEBUG +#ifdef PIRL2_DEBUG +/******************************************************************************* +* pirl2DumpResource +* +* DESCRIPTION: +* This function dumps IRL Resource register values. +* +* INPUTS: +* irlPort - physical port number. +* irlRes - bucket to be used (0 ~ 4). +* dataLen - data size. +* +* OUTPUTS: +* data - IRL Resource data +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS pirl2DumpResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlPort, + IN GT_U32 irlRes, + IN GT_U32 dataLen, + OUT GT_U16 *data +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL2_OPERATION op; + GT_PIRL2_OP_DATA opData; + GT_U32 i; + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL2_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + op = PIRL_READ_RESOURCE; + + for(i=0; i + +/******************************************************************************* +* gtPIRL.c +* +* DESCRIPTION: +* API definitions for PIRL Resources +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +*******************************************************************************/ + +#include +#include +#include +#include + +/****************************************************************************/ +/* STATS operation function declaration. */ +/****************************************************************************/ +static GT_STATUS pirlOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PIRL_OPERATION pirlOp, + INOUT GT_PIRL_OP_DATA *opData +); + +static GT_STATUS pirlInitialize +( + IN GT_QD_DEV *dev +); + +static GT_STATUS pirlInitIRLUnit +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit +); + +static GT_STATUS pirlDataToResource +( + IN GT_QD_DEV *dev, + IN GT_PIRL_DATA *pirlData, + OUT GT_PIRL_RESOURCE *res +); + +static GT_STATUS pirlResourceToData +( + IN GT_QD_DEV *dev, + IN GT_PIRL_RESOURCE *res, + OUT GT_PIRL_DATA *pirlData +); + +static GT_STATUS pirlWriteResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_PIRL_RESOURCE *res +); + +static GT_STATUS pirlReadResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_PIRL_RESOURCE *res +); + +static GT_STATUS pirlSetPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec +); + +static GT_STATUS pirlGetPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_U32 *portVec +); + +static GT_STATUS pirlSetFcMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PIRL_FC_DEASSERT mode +); + +/******************************************************************************* +* gpirlActivate +* +* DESCRIPTION: +* This routine activates Ingress Rate Limiting for the given ports by +* initializing a resource bucket, assigning ports, and configuring +* Bucket Parameters. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* portVec - the list of ports that share the bucket. +* pirlData - PIRL resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlActivate +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec, + IN GT_PIRL_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_PORT_STP_STATE pState[MAX_SWITCH_PORTS]; + GT_LPORT port; + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + GT_PIRL_RESOURCE pirlRes; + + DBG_INFO(("gpirlActivate Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM irlUnit\n")); + return GT_BAD_PARAM; + } + + /* check if the given portVec is valid */ + if ((!portVec) || (portVec >= (GT_U32)(1<numOfPorts))) + { + DBG_INFO(("GT_BAD_PARAM portVec\n")); + return GT_BAD_PARAM; + } + + /* set or reset port's ingress resource bit based on the portVec */ + retVal = pirlSetPortVec(dev, irlUnit, portVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + /* Disable ports that share the bucket */ + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = gstpGetPortState(dev, port, &pState[port]); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + retVal = gstpSetPortState(dev, port, GT_PORT_DISABLE); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + } + + /* Program Tuning register */ + op = PIRL_WRITE_RESOURCE; + opData.irlUnit = irlUnit; + opData.irlReg = 0xF; + opData.irlData = 0x7; + retVal = pirlOperationPerform(dev,op,&opData); + if(retVal != GT_OK) + { + DBG_INFO(("Failed (statsOperationPerform returned GT_FAIL).\n")); + return retVal; + } + + /* Program the Ingress Rate Resource Parameters */ + retVal = pirlDataToResource(dev,pirlData,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Data to PIRL Resource conversion failed.\n")); + return retVal; + } + + retVal = pirlWriteResource(dev,irlUnit,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + /* Initialize internal counters */ + retVal = pirlInitIRLUnit(dev,irlUnit); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + /* Program PirlFCMode for each port that shares Bucket */ + if (pirlRes.ebsLimitAction == ESB_LIMIT_ACTION_FC) + { + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = pirlSetFcMode(dev,port,pirlData->fcDeassertMode[port]); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL FC Mode set failed.\n")); + return retVal; + } + } + } + + /* Set the ports in their original state */ + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = gstpSetPortState(dev, port, pState[port]); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpirlDeactivate +* +* DESCRIPTION: +* This routine deactivates Ingress Rate Limiting for the given bucket. +* It simply removes every ports from the Ingress Rate Resource. +* It is assumed that gpirlActivate has been successfully called with +* the irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlDeactivate +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit +) +{ + GT_STATUS retVal; + + DBG_INFO(("gpirlDectivate Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* reset port's ingress resource bit */ + retVal = pirlSetPortVec(dev, irlUnit, 0); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gpirlUpdateParam +* +* DESCRIPTION: +* This routine updates IRL Parameter. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* pirlData - PIRL resource parameters. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlUpdateParam +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_PIRL_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_PORT_STP_STATE pState[MAX_SWITCH_PORTS]; + GT_LPORT port; + GT_PIRL_RESOURCE pirlRes; + GT_U32 portVec; + + DBG_INFO(("gpirlUpdateParam Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* get port list that share ingress resource */ + retVal = pirlGetPortVec(dev, irlUnit, &portVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + /* check if the given portVec is valid */ + if (!portVec) + { + DBG_INFO(("IRL Unit not Activated\n")); + return GT_FAIL; + } + + /* Disable ports that share the bucket */ + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = gstpGetPortState(dev, port, &pState[port]); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + retVal = gstpSetPortState(dev, port, GT_PORT_DISABLE); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + } + + /* Program the Ingress Rate Resource Parameters */ + retVal = pirlDataToResource(dev,pirlData,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Data to PIRL Resource conversion failed.\n")); + return retVal; + } + + retVal = pirlWriteResource(dev,irlUnit,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + /* Initialize internal counrters for the bucket */ + retVal = pirlInitIRLUnit(dev,irlUnit); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Write Resource failed.\n")); + return retVal; + } + + /* Program PirlFCMode for each port that shares Bucket */ + if (pirlRes.ebsLimitAction == ESB_LIMIT_ACTION_FC) + { + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = pirlSetFcMode(dev,port,pirlData->fcDeassertMode[port]); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL FC Mode set failed.\n")); + return retVal; + } + } + } + + /* Set the ports in their original state */ + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = gstpSetPortState(dev, port, pState[port]); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpirlReadParam +* +* DESCRIPTION: +* This routine retrieves IRL Parameter. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* +* OUTPUTS: +* pirlData - PIRL resource parameters. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlReadParam +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_PIRL_DATA *pirlData +) +{ + GT_STATUS retVal; + GT_LPORT port; + GT_PIRL_RESOURCE pirlRes; + GT_U32 portVec; + + DBG_INFO(("gpirlReadParam Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* get port list that share ingress resource */ + retVal = pirlGetPortVec(dev, irlUnit, &portVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + /* check if the given portVec is valid */ + if (!portVec) + { + DBG_INFO(("IRL Unit not Activated\n")); + return GT_FAIL; + } + + /* Read the Ingress Rate Resource Parameters */ + retVal = pirlReadResource(dev,irlUnit,&pirlRes); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Read Resource failed.\n")); + return retVal; + } + + retVal = pirlResourceToData(dev,&pirlRes,pirlData); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL Resource to PIRL Data conversion failed.\n")); + return retVal; + } + + /* Program PirlFCMode for each port that shares Bucket */ + if (pirlRes.ebsLimitAction == ESB_LIMIT_ACTION_FC) + { + for(port=0; portnumOfPorts; port++) + { + if(!GT_IS_PORT_SET(portVec,port)) + continue; + + retVal = grcGetPirlFcMode(dev,port,&pirlData->fcDeassertMode[port]); + if(retVal != GT_OK) + { + DBG_INFO(("PIRL FC Mode get failed.\n")); + return retVal; + } + } + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + + +/******************************************************************************* +* gpirlUpdatePortVec +* +* DESCRIPTION: +* This routine updates port list that share the bucket. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* portVec - the list of ports that share the bucket. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlUpdatePortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec +) +{ + GT_STATUS retVal; + GT_U32 tmpVec; + + DBG_INFO(("gpirlActivate Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* check if the given portVec is valid */ + if ((!portVec) || (portVec > (GT_U32)(1<numOfPorts))) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* get port list that share ingress resource */ + retVal = pirlGetPortVec(dev, irlUnit, &tmpVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + /* check if the given portVec is valid */ + if (!tmpVec) + { + DBG_INFO(("IRL Unit not Activated\n")); + return GT_FAIL; + } + + /* set or reset port's ingress resource bit based on the portVec */ + retVal = pirlSetPortVec(dev, irlUnit, portVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + +/******************************************************************************* +* gpirlReadPortVec +* +* DESCRIPTION: +* This routine retrieves port list that share the bucket. +* It is assumed that gpirlActivate has been successfully called with +* the given irlUnit before this function is called. +* +* INPUTS: +* irlUnit - bucket to be used (0 ~ 11). +* +* OUTPUTS: +* portVec - the list of ports that share the bucket. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlReadPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_U32 *portVec +) +{ + GT_STATUS retVal; + + DBG_INFO(("gpirlReadPortVec Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if the given bucket number is valid */ + if (!GT_IS_IRLUNIT_VALID(dev,irlUnit)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* get port list that share ingress resource */ + retVal = pirlGetPortVec(dev, irlUnit, portVec); + if(retVal != GT_OK) + { + DBG_INFO(("Getting Port State failed\n")); + return retVal; + } + + /* check if the given portVec is valid */ + if (!*portVec) + { + DBG_INFO(("IRL Unit not Activated\n")); + return GT_FAIL; + } + + DBG_INFO(("OK.\n")); + return GT_OK; + +} + + + +/******************************************************************************* +* grcGetPirlFcMode +* +* DESCRIPTION: +* This routine gets Port Ingress Rate Limit Flow Control mode. +* When EBSLimitAction is programmed to generate a flow control message, +* the deassertion of flow control is controlled by this mode. +* GT_PIRL_FC_DEASSERT_EMPTY: +* De-assert when the ingress rate resource has become empty +* GT_PIRL_FC_DEASSERT_CBS_LIMIT +* De-assert when the ingress rate resource has enough room as +* specified by the CBSLimit. +* Please refer to GT_PIRL_RESOURCE structure for EBSLimitAction and +* CBSLimit. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* mode - GT_PIRL_FC_DEASSERT enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS grcGetPirlFcMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PIRL_FC_DEASSERT *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* Physical port. */ + + DBG_INFO(("grcSetDaNrlEn Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the PirlFcMode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,12,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *mode = (GT_PIRL_FC_DEASSERT)data; + DBG_INFO(("OK.\n")); + + return GT_OK; +} + +/******************************************************************************* +* gpirlGetIngressRateResource +* +* DESCRIPTION: +* This routine gets Ingress Rate Limiting Resources assigned to the port. +* This vector is used to attach specific counter resources to the physical +* port. And the same counter resource can be attached to more than one port. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* resVec - resource vector (bit 11:0, since there is 12 resources) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirlGetIngressRateResource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *resVec +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* Physical port. */ + GT_U16 data; + + DBG_INFO(("grcGetIngressRateResource Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the resource vector. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,0,12,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *resVec = (GT_U32)data; + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + +/******************************************************************************* +* gpirlSetCurTimeUpInt +* +* DESCRIPTION: +* This function sets the current time update interval. +* Please contact FAE for detailed information. +* +* INPUTS: +* upInt - updata interval (0 ~ 7) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if invalid parameter is given +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gpirlSetCurTimeUpInt +( + IN GT_QD_DEV *dev, + IN GT_U32 upInt +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (upInt > 0x7) + return GT_BAD_PARAM; + + op = PIRL_READ_RESOURCE; + + opData.irlUnit = 0xF; + opData.irlReg = 1; + opData.irlData = 0; + + retVal = pirlOperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + op = PIRL_WRITE_RESOURCE; + opData.irlData = (opData.irlData & 0xFFF8) | (GT_U16)upInt; + + retVal = pirlOperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + return GT_OK; +} + +/****************************************************************************/ +/* Internal functions. */ +/****************************************************************************/ + +/******************************************************************************* +* gpirlInitialize +* +* DESCRIPTION: +* This routine initializes PIRL Resources. +* +* INPUTS: +* None +* +* OUTPUTS: +* None +* +* RETURNS: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gpirlInitialize +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; + GT_LPORT port; + GT_U8 hwPort; /* Physical port. */ + + /* reset port's ingress resource bit */ + for(port=0; portnumOfPorts; port++) + { + hwPort = GT_LPORT_2_PORT(port); + + /* Set the resource vector. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,0,12,0); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + + retVal = pirlInitialize(dev); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + + +/******************************************************************************* +* statsOperationPerform +* +* DESCRIPTION: +* This function accesses Ingress Rate Command Register and Data Register. +* +* INPUTS: +* pirlOp - The stats operation bits to be written into the stats +* operation register. +* port - port number +* counter - counter to be read if it's read operation +* +* OUTPUTS: +* pirlData - points to the data storage where the MIB counter will be saved. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlOperationPerform +( + IN GT_QD_DEV *dev, + IN GT_PIRL_OPERATION pirlOp, + INOUT GT_PIRL_OP_DATA *opData +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data; /* temporary Data storage */ + + gtSemTake(dev,dev->pirlRegsSem,OS_WAIT_FOREVER); + + /* Wait until the pirl in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + /* Set the PIRL Operation register */ + switch (pirlOp) + { + case PIRL_INIT_ALL_RESOURCE: + data = (1 << 15) | (PIRL_INIT_ALL_RESOURCE << 12); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + case PIRL_INIT_RESOURCE: + data = (GT_U16)((1 << 15) | (PIRL_INIT_RESOURCE << 12) | + ((opData->irlUnit&0xF)<< 4)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + + case PIRL_WRITE_RESOURCE: + data = (GT_U16)opData->irlData; + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_DATA,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + + data = (GT_U16)((1 << 15) | (PIRL_WRITE_RESOURCE << 12) | + ((opData->irlUnit&0xF) << 4) | (opData->irlReg & 0xF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + break; + + case PIRL_READ_RESOURCE: + data = (GT_U16)((1 << 15) | (PIRL_READ_RESOURCE << 12) | + ((opData->irlUnit&0xF) << 4) | (opData->irlReg & 0xF)); + retVal = hwWriteGlobal2Reg(dev,QD_REG_INGRESS_RATE_COMMAND,data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + retVal = hwReadGlobal2Reg(dev,QD_REG_INGRESS_RATE_DATA,&data); + opData->irlData = (GT_U32)data; + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + + default: + + gtSemGive(dev,dev->pirlRegsSem); + return GT_FAIL; + } + + /* Wait until the pirl in ready. */ + data = 1; + while(data == 1) + { + retVal = hwGetGlobal2RegField(dev,QD_REG_INGRESS_RATE_COMMAND,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->pirlRegsSem); + return retVal; + } + } + + gtSemGive(dev,dev->pirlRegsSem); + return retVal; +} + +/* + * Initialize all PIRL resources to the inital state. +*/ +static GT_STATUS pirlInitialize +( + IN GT_QD_DEV *dev +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL_OPERATION op; + + op = PIRL_INIT_ALL_RESOURCE; + + retVal = pirlOperationPerform(dev, op, NULL); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + retVal = gpirlSetCurTimeUpInt(dev,7); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + } + + return retVal; +} + +/* + * Initialize the selected PIRL resource to the inital state. + * This function initializes only the BSM structure for the IRL Unit. +*/ +static GT_STATUS pirlInitIRLUnit +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + + op = PIRL_INIT_RESOURCE; + opData.irlUnit = irlUnit; + + retVal = pirlOperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + return retVal; +} + +/* + * convert PIRL Data structure to PIRL Resource structure. + * if PIRL Data is not valid, return GT_BAD_PARARM; +*/ +static GT_STATUS pirlDataToResource +( + IN GT_QD_DEV *dev, + IN GT_PIRL_DATA *pirlData, + OUT GT_PIRL_RESOURCE *res +) +{ + GT_U16 typeMask; + + switch(pirlData->accountQConf) + { + case GT_FALSE: + case GT_TRUE: + res->accountQConf = pirlData->accountQConf; + break; + default: + return GT_BAD_PARAM; + } + + switch(pirlData->accountFiltered) + { + case GT_FALSE: + case GT_TRUE: + res->accountFiltered = pirlData->accountFiltered; + break; + default: + return GT_BAD_PARAM; + } + + switch(pirlData->ebsLimitAction) + { + case ESB_LIMIT_ACTION_DROP: + case ESB_LIMIT_ACTION_FC: + res->ebsLimitAction = pirlData->ebsLimitAction; + break; + default: + return GT_BAD_PARAM; + } + + if(pirlData->customSetup.isValid == GT_TRUE) + { + res->ebsLimit = pirlData->customSetup.ebsLimit; + res->cbsLimit = pirlData->customSetup.cbsLimit; + res->bktIncrement = pirlData->customSetup.bktIncrement; + res->bktRateFactor = pirlData->customSetup.bktRateFactor; + } + else + { + if(pirlData->ingressRate == 0) + return GT_BAD_PARAM; + + if(pirlData->ingressRate < 1000) /* less than 1Mbps */ + { + /* it should be divided by 64 */ + if(pirlData->ingressRate % 64) + return GT_BAD_PARAM; + res->bktRateFactor = pirlData->ingressRate/64; + } + else if(pirlData->ingressRate <= 100000) /* less than or equal to 100Mbps */ + { + /* it should be divided by 1000 */ + if(pirlData->ingressRate % 1000) + return GT_BAD_PARAM; + res->bktRateFactor = pirlData->ingressRate/64 + ((pirlData->ingressRate % 64)?1:0); + } + else if(pirlData->ingressRate <= 200000) /* less than or equal to 200Mbps */ + { + /* it should be divided by 10000 */ + if(pirlData->ingressRate % 10000) + return GT_BAD_PARAM; + res->bktRateFactor = pirlData->ingressRate/64 + ((pirlData->ingressRate % 64)?1:0); + } + else + return GT_BAD_PARAM; + + res->ebsLimit = RECOMMENDED_ESB_LIMIT(dev, pirlData->ingressRate); + res->cbsLimit = RECOMMENDED_CBS_LIMIT(dev, pirlData->ingressRate); + res->bktIncrement = RECOMMENDED_BUCKET_INCREMENT(dev, pirlData->ingressRate); + } + + switch(pirlData->bktRateType) + { + case BUCKET_TYPE_TRAFFIC_BASED: + res->bktRateType = pirlData->bktRateType; + + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL_RESOURCE)) + { + typeMask = 0xF; + } + else + { + typeMask = 0x7F; + } + + if (pirlData->bktTypeMask > typeMask) + { + return GT_BAD_PARAM; + } + else + { + res->bktTypeMask = pirlData->bktTypeMask; + } + + break; + + case BUCKET_TYPE_RATE_BASED: + if (IS_IN_DEV_GROUP(dev,DEV_RESTRICTED_PIRL_RESOURCE)) + return GT_BAD_PARAM; + res->bktRateType = pirlData->bktRateType; + res->bktTypeMask = 0; + break; + + default: + return GT_BAD_PARAM; + } + + switch(pirlData->byteTobeCounted) + { + case GT_PIRL_COUNT_ALL_LAYER1: + res->byteTobeCounted = 1; + break; + case GT_PIRL_COUNT_ALL_LAYER2: + res->byteTobeCounted = 2; + break; + case GT_PIRL_COUNT_ALL_LAYER3: + res->byteTobeCounted = 6; + break; + default: + return GT_BAD_PARAM; + } + + return GT_OK; +} + +/* + * convert PIRL Resource structure to PIRL Data structure. +*/ +static GT_STATUS pirlResourceToData +( + IN GT_QD_DEV *dev, + IN GT_PIRL_RESOURCE *res, + OUT GT_PIRL_DATA *pirlData +) +{ + GT_U32 rate; + GT_U32 factor; + + pirlData->accountQConf = res->accountQConf; + pirlData->accountFiltered = res->accountFiltered; + pirlData->ebsLimitAction = res->ebsLimitAction; + + pirlData->customSetup.isValid = GT_FALSE; + + FACTOR_FROM_BUCKET_INCREMENT(dev,res->bktIncrement,factor); + + rate = res->bktRateFactor * factor; + if(rate == 0) + { + pirlData->ingressRate = 0; + pirlData->customSetup.isValid = GT_TRUE; + pirlData->customSetup.ebsLimit = res->ebsLimit; + pirlData->customSetup.cbsLimit = res->cbsLimit; + pirlData->customSetup.bktIncrement = res->bktIncrement; + pirlData->customSetup.bktRateFactor = res->bktRateFactor; + } + else if(rate < 1000) + { + pirlData->ingressRate = rate; + } + else if(rate < 100000) + { + pirlData->ingressRate = rate - (rate % 1000); + } + else + { + pirlData->ingressRate = rate - (rate % 10000); + } + + pirlData->bktRateType = res->bktRateType; + pirlData->bktTypeMask = res->bktTypeMask; + + switch(res->byteTobeCounted) + { + case 1: + pirlData->byteTobeCounted = GT_PIRL_COUNT_ALL_LAYER1; + break; + case 2: + pirlData->byteTobeCounted = GT_PIRL_COUNT_ALL_LAYER2; + break; + case 6: + pirlData->byteTobeCounted = GT_PIRL_COUNT_ALL_LAYER3; + break; + default: + return GT_BAD_PARAM; + } + + return GT_OK; +} + +/******************************************************************************* +* pirlWriteResource +* +* DESCRIPTION: +* This function writes IRL Resource to BCM (Bucket Configuration Memory) +* +* INPUTS: +* irlUnit - resource unit to be accessed +* res - IRL Resource data +* +* OUTPUTS: +* Nont. +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlWriteResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_PIRL_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + int i; + + op = PIRL_WRITE_RESOURCE; + + /* reg0 data */ + data[0] = (GT_U16)((res->bktRateType << 15) | /* Bit[15] : Bucket Rate Type */ + (res->bktTypeMask << 4 ) | /* Bit[14:4] : Traffic Type */ + res->byteTobeCounted ); /* Bit[3:0] : Bytes to be counted */ + + /* reg1 data */ + data[1] = (GT_U16)res->bktIncrement; /* Bit[11:0] : Bucket Increment */ + + /* reg2 data */ + data[2] = (GT_U16)res->bktRateFactor; /* Bit[15:0] : Bucket Rate Factor */ + + /* reg3 data */ + data[3] = (GT_U16)(res->cbsLimit & 0xFFF) << 4; /* Bit[15:4] : CBS Limit[11:0] */ + + /* reg4 data */ + data[4] = (GT_U16)(res->cbsLimit >> 12); /* Bit[11:0] : CBS Limit[23:12] */ + + /* reg5 data */ + data[5] = (GT_U16)(res->ebsLimit & 0xFFFF); /* Bit[15:0] : EBS Limit[15:0] */ + + /* reg6 data */ + data[6] = (GT_U16)((res->ebsLimit >> 16) | /* Bit[7:0] : EBS Limit[23:16] */ + (res->ebsLimitAction << 12) | /* Bit[12] : EBS Limit Action */ + (res->accountFiltered << 14)| /* Bit[14] : Account Filtered */ + (res->accountQConf << 15)); /* Bit[15] : Account QConf */ + /* reg7 data */ + data[7] = 0; /* Reserved */ + + for(i=0; i<8; i++) + { + opData.irlUnit = irlUnit; + opData.irlReg = i; + opData.irlData = data[i]; + + retVal = pirlOperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + } + + return GT_OK; +} + + +/******************************************************************************* +* pirlReadResource +* +* DESCRIPTION: +* This function reads IRL Resource from BCM (Bucket Configuration Memory) +* +* INPUTS: +* irlUnit - resource unit to be accessed +* +* OUTPUTS: +* res - IRL Resource data +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlReadResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_PIRL_RESOURCE *res +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_U16 data[8]; /* temporary Data storage */ + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + int i; + + op = PIRL_READ_RESOURCE; + + for(i=0; i<8; i++) + { + opData.irlUnit = irlUnit; + opData.irlReg = i; + opData.irlData = 0; + + retVal = pirlOperationPerform(dev, op, &opData); + if (retVal != GT_OK) + { + DBG_INFO(("PIRL OP Failed.\n")); + return retVal; + } + + data[i] = (GT_U16)opData.irlData; + } + + + /* reg0 data */ + res->bktRateType = (data[0] >> 15) & 0x1; + res->bktTypeMask = (data[0] >> 4) & 0x7F; + + res->byteTobeCounted = data[0] & 0xF; + + /* reg1 data */ + res->bktIncrement = data[1] & 0xFFF; + + /* reg2 data */ + res->bktRateFactor = data[2] & 0xFFFF; + + /* reg3,4 data */ + res->cbsLimit = ((data[3] >> 4) & 0xFFF) | ((data[4] & 0xFFF) << 12); + + /* reg5,6 data */ + res->ebsLimit = data[5] | ((data[6] & 0xFF) << 16); + + /* reg6 data */ + res->ebsLimitAction = (data[6] >> 12) & 0x1; + res->accountFiltered = (data[6] >> 14) & 0x1; + res->accountQConf = (data[6] >> 15) & 0x1; + + return GT_OK; +} + +/******************************************************************************* +* pirlSetPortVec +* +* DESCRIPTION: +* This routine sets port list that share the bucket and resets ports that +* do not share the bucket. +* +* INPUTS: +* irlUnit - bucket to be used. +* portVec - the list of ports that share the bucket. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlSetPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 portVec +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_LPORT port; + GT_U8 hwPort; /* Physical port. */ + GT_U16 data; + + for(port=0; portnumOfPorts; port++) + { + if(GT_IS_PORT_SET(portVec,port)) + data = 1; + else + data = 0; + + hwPort = GT_LPORT_2_PORT(port); + + /* Set the resource vector. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,(GT_U8)irlUnit,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + + +/******************************************************************************* +* pirlGetPortVec +* +* DESCRIPTION: +* This routine gets port list that share the bucket. +* +* INPUTS: +* irlUnit - bucket to be used. +* +* OUTPUTS: +* portVec - the list of ports that share the bucket. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlGetPortVec +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + OUT GT_U32 *portVec +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_LPORT port; + GT_U8 hwPort; /* Physical port. */ + GT_U16 data; + + *portVec = 0; + + for(port=0; portnumOfPorts; port++) + { + hwPort = GT_LPORT_2_PORT(port); + + /* Set the resource vector. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,(GT_U8)irlUnit,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if(data == 1) + *portVec |= (1 << port); + } + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + + +/******************************************************************************* +* pirlSetFcMode +* +* DESCRIPTION: +* This routine gets Port Ingress Rate Limit Flow Control mode. +* When EBSLimitAction is programmed to generate a flow control message, +* the deassertion of flow control is controlled by this mode. +* GT_PIRL_FC_DEASSERT_EMPTY: +* De-assert when the ingress rate resource has become empty +* GT_PIRL_FC_DEASSERT_CBS_LIMIT +* De-assert when the ingress rate resource has enough room as +* specified by the CBSLimit. +* Please refer to GT_PIRL_RESOURCE structure for EBSLimitAction and +* CBSLimit. +* +* INPUTS: +* port - logical port number +* mode - GT_PIRL_FC_DEASSERT enum type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +static GT_STATUS pirlSetFcMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PIRL_FC_DEASSERT mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* Physical port. */ + + DBG_INFO(("pirlSetFcMode Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + + data = (GT_U16) mode; + + /* Set the PirlFcMode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_INGRESS_RATE_CTRL,12,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + + return GT_OK; +} + +#define PIRL_DEBUG +#ifdef PIRL_DEBUG +/******************************************************************************* +* pirlDumpResource +* +* DESCRIPTION: +* This function dumps IRL Resource register values. +* +* INPUTS: +* irlUnit - resource unit to be accessed +* dataLen - data size. +* +* OUTPUTS: +* data - IRL Resource data +* +* RETURNS: +* GT_OK on success, +* GT_FAIL otherwise. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS pirlDumpResource +( + IN GT_QD_DEV *dev, + IN GT_U32 irlUnit, + IN GT_U32 dataLen, + OUT GT_U16 *data +) +{ + GT_STATUS retVal; /* Functions return value */ + GT_PIRL_OPERATION op; + GT_PIRL_OP_DATA opData; + GT_U32 i; + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_PIRL_RESOURCE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + op = PIRL_READ_RESOURCE; + + for(i=0; i + +/******************************************************************************** +* gtPolicy.c +* +* DESCRIPTION: +* API definitions to handle Policy Mapping +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* gprtSetPolicy +* +* DESCRIPTION: +* This routine sets the Policy for ports. +* Supported Policies are defined as GT_FRAME_POLICY as follows: +* FRAME_POLICY_NONE - normal frame switching +* FRAME_POLICY_MIRROR - mirror (copy) frame to MirrorDest port +* FRAME_POLICY_TRAP - trap(re-direct) frame to the CPUDest port +* FRAME_POLICY_DISCARD - discard(filter) the frame +* Supported Policy types are defined as GT_POLICY_TYPE: +* POLICY_TYPE_DA - DA Policy Mapping +* DA Policy Mapping occurs when the DA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_SA - SA Policy Mapping +* SA Policy Mapping occurs when the SA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_VTU - VTU Policy Mapping +* VTU Policy Mapping occurs when the VID of a frame is contained in +* the VTU database with the VidPolicy is enabled. +* POLICY_TYPE_ETYPE - EtherType Policy Mapping +* EType Policy Mapping occurs when the EtherType of a frame matches +* the PortEType (see gprtSetPortEType API) +* POLICY_TYPE_PPPoE - PPPoE Policy Mapping +* PPPoE Policy Mapping occurs when the EtherType of a frame matches 0x8863 +* POLICY_TYPE_VBAS - VBAS Policy Mapping +* VBAS Policy Mapping occurs when the EtherType of a frame matches 0x8200 +* POLICY_TYPE_OPT82 - DHCP Option 82 Policy Mapping +* DHCP Option 82 Policy Mapping occurs when the ingressing frame is an +* IPv4 UDP with a UDP Destination port = 0x0043 or 0x0044, or an +* IPv6 UDP with a UDP Destination port = 0x0223 or 0x0222 +* POLICY_TYPE_UDP - UDP Policy Mapping +* UDP Policy Mapping occurs when the ingressing frame is +* a Broadcast IPv4 UDP or a Multicast IPv6 UDP. +* +* INPUTS: +* port - logical port number. +* type - policy type (GT_POLICY_TYPE) +* policy - policy (GT_FRAME_POLICY) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetPolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_POLICY_TYPE type, + IN GT_FRAME_POLICY policy +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* Physical port. */ + GT_U8 offset; + + DBG_INFO(("gprtSetPolicy Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_POLICY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (policy) + { + case FRAME_POLICY_NONE: + case FRAME_POLICY_MIRROR: + case FRAME_POLICY_TRAP: + case FRAME_POLICY_DISCARD: + break; + default: + DBG_INFO(("Bad Policy\n")); + return GT_BAD_PARAM; + } + + switch (type) + { + case POLICY_TYPE_DA: + offset = 14; + break; + case POLICY_TYPE_SA: + offset = 12; + break; + case POLICY_TYPE_VTU: + offset = 10; + break; + case POLICY_TYPE_ETYPE: + offset = 8; + break; + case POLICY_TYPE_PPPoE: + offset = 6; + break; + case POLICY_TYPE_VBAS: + offset = 4; + break; + case POLICY_TYPE_OPT82: + offset = 2; + break; + case POLICY_TYPE_UDP: + offset = 0; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + retVal = hwSetPortRegField(dev,hwPort, QD_REG_POLICY_CONTROL, offset, 2, (GT_U16)policy); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* gprtGetPolicy +* +* DESCRIPTION: +* This routine gets the Policy of the given policy type. +* Supported Policies are defined as GT_FRAME_POLICY as follows: +* FRAME_POLICY_NONE - normal frame switching +* FRAME_POLICY_MIRROR - mirror (copy) frame to MirrorDest port +* FRAME_POLICY_TRAP - trap(re-direct) frame to the CPUDest port +* FRAME_POLICY_DISCARD - discard(filter) the frame +* Supported Policy types are defined as GT_POLICY_TYPE: +* POLICY_TYPE_DA - DA Policy Mapping +* DA Policy Mapping occurs when the DA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_SA - SA Policy Mapping +* SA Policy Mapping occurs when the SA of a frame is contained in +* the ATU address database with an Entry State that indicates Policy. +* POLICY_TYPE_VTU - VTU Policy Mapping +* VTU Policy Mapping occurs when the VID of a frame is contained in +* the VTU database with the VidPolicy is enabled. +* POLICY_TYPE_ETYPE - EtherType Policy Mapping +* EType Policy Mapping occurs when the EtherType of a frame matches +* the PortEType (see gprtSetPortEType API) +* POLICY_TYPE_PPPoE - PPPoE Policy Mapping +* PPPoE Policy Mapping occurs when the EtherType of a frame matches 0x8863 +* POLICY_TYPE_VBAS - VBAS Policy Mapping +* VBAS Policy Mapping occurs when the EtherType of a frame matches 0x8200 +* POLICY_TYPE_OPT82 - DHCP Option 82 Policy Mapping +* DHCP Option 82 Policy Mapping occurs when the ingressing frame is an +* IPv4 UDP with a UDP Destination port = 0x0043 or 0x0044, or an +* IPv6 UDP with a UDP Destination port = 0x0223 or 0x0222 +* POLICY_TYPE_UDP - UDP Policy Mapping +* UDP Policy Mapping occurs when the ingressing frame is +* a Broadcast IPv4 UDP or a Multicast IPv6 UDP. +* +* INPUTS: +* port - logical port number. +* type - policy type (GT_POLICY_TYPE) +* +* OUTPUTS: +* policy - policy (GT_FRAME_POLICY) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetPolicy +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_POLICY_TYPE type, + OUT GT_FRAME_POLICY *policy +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* Physical port. */ + GT_U8 offset; + GT_U16 data; + + DBG_INFO(("gprtGetPolicy Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_POLICY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (type) + { + case POLICY_TYPE_DA: + offset = 14; + break; + case POLICY_TYPE_SA: + offset = 12; + break; + case POLICY_TYPE_VTU: + offset = 10; + break; + case POLICY_TYPE_ETYPE: + offset = 8; + break; + case POLICY_TYPE_PPPoE: + offset = 6; + break; + case POLICY_TYPE_VBAS: + offset = 4; + break; + case POLICY_TYPE_OPT82: + offset = 2; + break; + case POLICY_TYPE_UDP: + offset = 0; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + retVal = hwGetPortRegField(dev,hwPort, QD_REG_POLICY_CONTROL, offset, 2, &data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *policy = (GT_FRAME_POLICY)data; + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortCtrl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortCtrl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortCtrl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortCtrl.c 2011-04-04 13:57:35.105597042 -0400 @@ -0,0 +1,6684 @@ +#include + +/******************************************************************************** +* gtPortCtrl.c +* +* DESCRIPTION: +* API implementation for switch port control. +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 3 $ +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* gprtSetForceFc +* +* DESCRIPTION: +* This routine set the force flow control state. +* +* INPUTS: +* port - the logical port number. +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetForceFc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL force +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_PORT_STP_STATE state; + + DBG_INFO(("gprtSetForceFc Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + if(force) + data = 3; + else + data = 0; + + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,6,2,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; + } + + /* Port should be disabled before Set Force Flow Control bit */ + retVal = gstpGetPortState(dev,port, &state); + if(retVal != GT_OK) + { + DBG_INFO(("gstpGetPortState failed.\n")); + return retVal; + } + + retVal = gstpSetPortState(dev,port, GT_PORT_DISABLE); + if(retVal != GT_OK) + { + DBG_INFO(("gstpSetPortState failed.\n")); + return retVal; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(force, data); + + /* Set the force flow control bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,15,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + /* Restore original stp state. */ + if(gstpSetPortState(dev,port, state) != GT_OK) + { + DBG_INFO(("gstpSetPortState failed.\n")); + return GT_FAIL; + } + + return retVal; +} + + + +/******************************************************************************* +* gprtGetForceFc +* +* DESCRIPTION: +* This routine get the force flow control state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetForceFc +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *force +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetForceFc Called.\n")); + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,6,2,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + if(data & 0x1) + *force = GT_TRUE; + else + *force = GT_FALSE; + + return retVal; + } + + /* Get the force flow control bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,15,1,&data); + /* translate binary to BOOL */ + BIT_2_BOOL(data, *force); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetUseCoreTag +* +* DESCRIPTION: +* This routine set the UseCoreTag bit in Port Control Register. +* When this bit is cleared to a zero, ingressing frames are considered +* Tagged if the 16-bits following the frame's Source Address is 0x8100. +* When this bit is set to a one, ingressing frames are considered Tagged +* if the 16-bits following the frame's Source Address is equal to the +* CoreTag register value. +* +* INPUTS: +* port - the logical port number. +* force - GT_TRUE for force flow control or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetUseCoreTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL force +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetUseCoreTag Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_CORE_TAG)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(force, data); + + /* Set the UseCoreTag bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,15,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + + +/******************************************************************************* +* gprtGetUseCoreTag +* +* DESCRIPTION: +* This routine get the Use Core Tag state. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* force - GT_TRUE for using core tag register or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetUseCoreTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *force +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetUseCoreTag Called.\n")); + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_CORE_TAG)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the UseCoreTag bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,15,1,&data); + /* translate binary to BOOL */ + BIT_2_BOOL(data, *force); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetTrailerMode +* +* DESCRIPTION: +* This routine set the egress trailer mode. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for add trailer or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetTrailerMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetTrailerMode Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRAILER|DEV_TRAILER_P5|DEV_TRAILER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if(hwPort < 4) + { + /* check if device supports this feature for this port */ + if (IS_IN_DEV_GROUP(dev,DEV_TRAILER_P5|DEV_TRAILER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + else if(hwPort == 4) + { + /* check if device supports this feature for this port*/ + if (IS_IN_DEV_GROUP(dev,DEV_TRAILER_P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Set the trailer mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,14,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetTrailerMode +* +* DESCRIPTION: +* This routine get the egress trailer mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE for add trailer or GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetTrailerMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetTrailerMode Called.\n")); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRAILER|DEV_TRAILER_P5|DEV_TRAILER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if(hwPort < 4) + { + /* check if device supports this feature for this port */ + if (IS_IN_DEV_GROUP(dev,DEV_TRAILER_P5|DEV_TRAILER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + else if(hwPort == 4) + { + /* check if device supports this feature for this port */ + if (IS_IN_DEV_GROUP(dev,DEV_TRAILER_P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Get the Trailer mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,14,1,&data); + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + + + +/******************************************************************************* +* gprtSetIngressMode +* +* DESCRIPTION: +* This routine set the ingress mode. +* +* INPUTS: +* port - the logical port number. +* mode - the ingress mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIngressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_INGRESS_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIngressMode Called.\n")); + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Gigabit Switch does not support this status. */ + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* check if device supports this feature */ + switch (mode) + { + case (GT_UNMODIFY_INGRESS): + break; + + case (GT_TRAILER_INGRESS): + if(!(IS_IN_DEV_GROUP(dev,DEV_TRAILER|DEV_TRAILER_P5|DEV_TRAILER_P4P5))) + { + DBG_INFO(("Given ingress mode is not supported by this device\n")); + return GT_NOT_SUPPORTED; + } + break; + + case (GT_UNTAGGED_INGRESS): + if(!(IS_IN_DEV_GROUP(dev,DEV_TAGGING))) + { + DBG_INFO(("Given ingress mode is not supported by this device\n")); + return GT_NOT_SUPPORTED; + } + break; + + case (GT_CPUPORT_INGRESS): + if(!(IS_IN_DEV_GROUP(dev,DEV_IGMP_SNOOPING))) + { + DBG_INFO(("Given ingress mode is not supported by this device\n")); + return GT_NOT_SUPPORTED; + } + + if(hwPort != GT_LPORT_2_PORT(dev->cpuPortNum)) + { + DBG_INFO(("Given ingress mode is supported by CPU port only\n")); + return GT_NOT_SUPPORTED; + } + + break; + + default: + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + /* Set the Ingress Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,8,2,(GT_U16)mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + + +/******************************************************************************* +* gprtGetIngressMode +* +* DESCRIPTION: +* This routine get the ingress mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the ingress mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIngressMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_INGRESS_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIngressMode Called.\n")); + + /* Gigabit Switch does not support this status. */ + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + /* Get the Ingress Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 8, 2,&data); + *mode = data; + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetMcRateLimit +* +* DESCRIPTION: +* This routine set the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* rate - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetMcRateLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_MC_RATE rate +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetMcRateLimit Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* this feature only exits in 6051, 6052, and 6012. It is replace with + * Rate Cotrol Register in the future products, starting from clippership + */ + if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_MC_RATE_PERCENT)) != GT_OK) + return retVal; + + /* Set the multicast rate limit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,2,2,(GT_U16)rate); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + + +/******************************************************************************* +* gprtGetMcRateLimit +* +* DESCRIPTION: +* This routine Get the port multicast rate limit. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* rate - GT_TRUE to Enable, GT_FALSE for otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetMcRateLimit +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_MC_RATE *rate +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read data */ + + DBG_INFO(("gprtGetMcRateLimit Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* this feature only exits in 6051, 6052, and 6012. It is replace with + * Rate Cotrol Register in the future products, starting from clippership + */ + if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_MC_RATE_PERCENT)) != GT_OK) + return retVal; + + /* Get the multicast rate limit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 2, 2,&data); + *rate = data; + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/* the following two APIs are added to support fullsail and clippership */ + +/******************************************************************************* +* gprtSetIGMPSnoop +* +* DESCRIPTION: +* This routine set the IGMP Snoop. When set to one and this port receives +* IGMP frame, the frame is switched to the CPU port, overriding all other +* switching decisions, with exception for CPU's Trailer. +* CPU port is determined by the Ingress Mode bits. A port is considered +* the CPU port if its Ingress Mode are either GT_TRAILER_INGRESS or +* GT_CPUPORT_INGRESS. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for IGMP Snoop or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIGMPSnoop +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIGMPSnoop Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_IGMP_SNOOPING)) != GT_OK) + return retVal; + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the IGMP Snooping mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,10,1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetIGMPSnoop +* +* DESCRIPTION: +* This routine get the IGMP Snoop mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: IGMP Snoop enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIGMPSnoop +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIGMPSnoop Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_IGMP_SNOOPING)) != GT_OK) + return retVal; + + /* Get the Ingress Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 10, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/* the following two APIs are added to support clippership */ + +/******************************************************************************* +* gprtSetHeaderMode +* +* DESCRIPTION: +* This routine set ingress and egress header mode of a switch port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for header mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetHeaderMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetHeaderMode Called.\n")); + + /* only devices beyond quarterdeck (6052) has this feature */ + /* Fullsail (DEV_QD_88E6502) is an exception, and does not support this feature */ + if(IS_VALID_API_CALL(dev,port, DEV_HEADER|DEV_HEADER_P5|DEV_HEADER_P4P5) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if(hwPort < 4) + { + if (IS_IN_DEV_GROUP(dev,DEV_HEADER_P5|DEV_HEADER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + else if(hwPort == 4) + { + if (IS_IN_DEV_GROUP(dev,DEV_HEADER_P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Set the header mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,11,1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetHeaderMode +* +* DESCRIPTION: +* This routine gets ingress and egress header mode of a switch port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetHeaderMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetHeaderMode Called.\n")); + + /* only devices beyond quarterdeck (6052) has this feature */ + /* Fullsail (DEV_QD_88E602) is an exception, and does not support this feature */ + if(IS_VALID_API_CALL(dev,port, DEV_HEADER|DEV_HEADER_P5|DEV_HEADER_P4P5) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if(hwPort < 4) + { + if (IS_IN_DEV_GROUP(dev,DEV_HEADER_P5|DEV_HEADER_P4P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + else if(hwPort == 4) + { + if (IS_IN_DEV_GROUP(dev,DEV_HEADER_P5)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + } + + /* Get the Header Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 11, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/* the following four APIs are added to support Octane */ + +/******************************************************************************* +* gprtSetProtectedMode +* +* DESCRIPTION: +* This routine set protected mode of a switch port. +* When this mode is set to GT_TRUE, frames are allowed to egress port +* defined by the 802.1Q VLAN membership for the frame's VID 'AND' +* by the port's VLANTable if 802.1Q is enabled on the port. Both must +* allow the frame to Egress. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for protected mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetProtectedMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetProtectedMode Called.\n")); + + /* Check if this feature is supported */ + if(IS_VALID_API_CALL(dev,port, DEV_PORT_SECURITY) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_CROSS_CHIP_VLAN)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Set the protected mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,3,1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetProtectedMode +* +* DESCRIPTION: +* This routine gets protected mode of a switch port. +* When this mode is set to GT_TRUE, frames are allowed to egress port +* defined by the 802.1Q VLAN membership for the frame's VID 'AND' +* by the port's VLANTable if 802.1Q is enabled on the port. Both must +* allow the frame to Egress. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetProtectedMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetProtectedMode Called.\n")); + + if(IS_VALID_API_CALL(dev,port, DEV_PORT_SECURITY) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_CROSS_CHIP_VLAN)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the protected Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 3, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetForwardUnknown +* +* DESCRIPTION: +* This routine set Forward Unknown mode of a switch port. +* When this mode is set to GT_TRUE, normal switch operation occurs. +* When this mode is set to GT_FALSE, unicast frame with unknown DA addresses +* will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for protected mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetForwardUnknown +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetForwardUnknown Called.\n")); + + if(IS_VALID_API_CALL(dev,port, DEV_PORT_SECURITY|DEV_EGRESS_FLOOD) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Set the forward unknown mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,2,1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetForwardUnknown +* +* DESCRIPTION: +* This routine gets Forward Unknown mode of a switch port. +* When this mode is set to GT_TRUE, normal switch operation occurs. +* When this mode is set to GT_FALSE, unicast frame with unknown DA addresses +* will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: header mode enabled +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetForwardUnknown +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetForwardUnknown Called.\n")); + + if(IS_VALID_API_CALL(dev,port, DEV_PORT_SECURITY|DEV_EGRESS_FLOOD) != GT_OK) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get the forward unknown Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 2, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetDropOnLock +* +* DESCRIPTION: +* This routine set the Drop on Lock. When set to one, Ingress frames will +* be discarded if their SA field is not in the ATU's address database. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Unknown SA drop or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDropOnLock +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDropOnLock Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CASCADE_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the DropOnLock mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,14,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetDropOnLock +* +* DESCRIPTION: +* This routine gets DropOnLock mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: DropOnLock enabled, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDropOnLock +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDropOnLock Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CASCADE_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DropOnLock Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 14, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetDoubleTag +* +* DESCRIPTION: +* This routine set the Ingress Double Tag Mode. When set to one, +* ingressing frames are examined to see if they contain an 802.3ac tag. +* If they do, the tag is removed and then the frame is processed from +* there (i.e., removed tag is ignored). Essentially, untagged frames +* remain untagged, single tagged frames become untagged and double tagged +* frames become single tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for DoulbeTag mode or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDoubleTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDoubleTag Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_INGRESS_DOUBLE_TAGGING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the DoubleTag mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,9,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetDoubleTag +* +* DESCRIPTION: +* This routine gets DoubleTag mode. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: DoubleTag enabled, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDoubleTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDoubleTag Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_INGRESS_DOUBLE_TAGGING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DoubleTag Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 9, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetInterswitchPort +* +* DESCRIPTION: +* This routine set Interswitch Port. When set to one, +* it indicates this port is a interswitch port used to communicated with +* CPU or to cascade with another switch device. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Interswitch port or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetInterswitchPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetInterswitchPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CASCADE_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the InterswitchPort. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,8,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + + +/******************************************************************************* +* gprtGetInterswithPort +* +* DESCRIPTION: +* This routine gets InterswitchPort. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: This port is interswitch port, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetInterswitchPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetInterswitchPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CASCADE_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the InterswitchPort Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 8, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetLearnDisable +* +* DESCRIPTION: +* This routine enables/disables automatic learning of new source MAC +* addresses on the given port ingress +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for disable or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetLearnDisable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetLearnDisable Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the LearnDisable mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_VLAN_MAP,11,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetLearnDisable +* +* DESCRIPTION: +* This routine gets LearnDisable setup +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: Learning disabled on the given port ingress frames, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetLearnDisable +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetLearnDisable Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the LearnDisable Mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_VLAN_MAP, 11, 1, &data); + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetIgnoreFCS +* +* DESCRIPTION: +* This routine sets FCS Ignore mode. When this bit is set to a one, +* the last four bytes of frames received on this port are overwritten with +* a good CRC and the frames will be accepted by the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for ignore FCS or GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIgnoreFCS +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIgnoreFCS Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the IgnoreFCS mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + retVal = hwSetPortRegField(dev,hwPort,QD_REG_PORT_CONTROL2,15,1,data ); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_VLAN_MAP,10,1,data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetIgnoreFCS +* +* DESCRIPTION: +* This routine gets Ignore FCS setup +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE: Ignore FCS on the given port's ingress frames, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIgnoreFCS +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIgnoreFCS Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the IgnoreFCS Mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + retVal = hwGetPortRegField(dev,hwPort,QD_REG_PORT_CONTROL2,15,1,&data ); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_VLAN_MAP, 10, 1, &data); + } + + /* translate binary to BOOL */ + BIT_2_BOOL(data, *mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetVTUPriOverride +* +* DESCRIPTION: +* VTU Priority Override. The following modes are supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetVTUPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PRI_OVERRIDE mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetVTUPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (mode) + { + case PRI_OVERRIDE_NONE: + data = 0; + break; + case PRI_OVERRIDE_FRAME_QUEUE: + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + data = 3; + } + else + { + data = 1; + } + break; + case PRI_OVERRIDE_FRAME: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 1; + break; + case PRI_OVERRIDE_QUEUE: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 2; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set the VTUPri Override mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,10,2,data); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,14,1,data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetVTUPriOverride +* +* DESCRIPTION: +* VTU Priority Override. The following modes are supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's VID (in the VTU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetVTUPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetVTUPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the VTUPriOverride Mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,10,2,&data); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 14, 1, &data); + if(data == 1) + data = 3; + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + else + { + DBG_INFO(("OK.\n")); + } + + switch (data) + { + case 0: + *mode = PRI_OVERRIDE_NONE; + break; + case 3: + *mode = PRI_OVERRIDE_FRAME_QUEUE; + break; + case 1: + *mode = PRI_OVERRIDE_FRAME; + break; + case 2: + *mode = PRI_OVERRIDE_QUEUE; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + return GT_OK; +} + + +/******************************************************************************* +* gprtSetSAPriOverride +* +* DESCRIPTION: +* SA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetSAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetSAPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (mode) + { + case PRI_OVERRIDE_NONE: + data = 0; + break; + case PRI_OVERRIDE_FRAME_QUEUE: + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + data = 3; + } + else + { + data = 1; + } + break; + case PRI_OVERRIDE_FRAME: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 1; + break; + case PRI_OVERRIDE_QUEUE: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 2; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set the SAPriOverride mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,12,2,data); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,13,1,data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetSAPriOverride +* +* DESCRIPTION: +* SA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's SA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetSAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetSAPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the SAPriOverride Mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,12,2,&data); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 13, 1, &data); + if(data == 1) + data = 3; + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + else + { + DBG_INFO(("OK.\n")); + } + + switch (data) + { + case 0: + *mode = PRI_OVERRIDE_NONE; + break; + case 3: + *mode = PRI_OVERRIDE_FRAME_QUEUE; + break; + case 1: + *mode = PRI_OVERRIDE_FRAME; + break; + case 2: + *mode = PRI_OVERRIDE_QUEUE; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + return GT_OK; +} + +/******************************************************************************* +* gprtSetDAPriOverride +* +* DESCRIPTION: +* DA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* +* INPUTS: +* port - the logical port number. +* mode - GT_PRI_OVERRIDE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is invalid +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtSetDAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PRI_OVERRIDE mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDAPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (mode) + { + case PRI_OVERRIDE_NONE: + data = 0; + break; + case PRI_OVERRIDE_FRAME_QUEUE: + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + data = 3; + } + else + { + data = 1; + } + break; + case PRI_OVERRIDE_FRAME: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 1; + break; + case PRI_OVERRIDE_QUEUE: + if (!IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + data = 2; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set the DAPriOverride mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,14,2,data); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,12,1,data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetDAPriOverride +* +* DESCRIPTION: +* DA Priority Override. The following mode is supported: +* PRI_OVERRIDE_NONE - +* Normal frame priority processing occurs. +* PRI_OVERRIDE_FRAME - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's FPri (frame priority). +* If the frame egresses tagged, the priority in the frame will be +* this new priority value. +* PRI_OVERRIDE_QUEUE - +* Priority assigned to the frame's DA (in the ATU table) is used +* to overwite the frame's QPri (queue priority). +* QPri is used internally to map the frame to one of the egress +* queues inside the switch. +* PRI_OVERRIDE_FRAME_QUEUE - +* Both frame and queue overrides take place on the frame. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_PRI_OVERRIDE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* PRI_OVERRIDE_FRAME and PRI_OVERRIDE_QUEUE modes are supported only on +* certain switch device. Please refer to the device datasheet. +* +*******************************************************************************/ +GT_STATUS gprtGetDAPriOverride +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PRI_OVERRIDE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDAPriOverride Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PRIORITY_OVERRIDE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DAPriOverride Mode. */ + if (IS_IN_DEV_GROUP(dev,DEV_EXT_PRIORITY_OVERRIDE)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PRI_OVERRIDE,14,2,&data); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 12, 1, &data); + if(data == 1) + data = 3; + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + else + { + DBG_INFO(("OK.\n")); + } + + switch (data) + { + case 0: + *mode = PRI_OVERRIDE_NONE; + break; + case 3: + *mode = PRI_OVERRIDE_FRAME_QUEUE; + break; + case 1: + *mode = PRI_OVERRIDE_FRAME; + break; + case 2: + *mode = PRI_OVERRIDE_QUEUE; + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + return GT_OK; +} + + +/******************************************************************************* +* gprtSetCPUPort +* +* DESCRIPTION: +* This routine sets CPU Port number. When Snooping is enabled on this port +* or when this port is configured as an Interswitch Port and it receives a +* To_CPU frame, the switch needs to know what port on this device the frame +* should egress. +* +* INPUTS: +* port - the logical port number. +* cpuPort - CPU Port number or interswitch port where CPU Port is connected +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetCPUPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LPORT cpuPort +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetCPUPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + data = (GT_U16)GT_LPORT_2_PORT(cpuPort); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CPU_DEST_PER_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Set the CPU Port. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,0,4,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetCPUPort +* +* DESCRIPTION: +* This routine gets CPU Logical Port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* cpuPort - CPU Port's logical number +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetCPUPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_LPORT *cpuLPort +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetCPUPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_CPU_DEST_PER_PORT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the CPUPort. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 0, 4, &data); + + *cpuLPort = GT_PORT_2_LPORT((GT_U8)data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetLockedPort +* +* DESCRIPTION: +* This routine sets LockedPort. When it's set to one, CPU directed +* learning for 802.1x MAC authentication is enabled on this port. In this +* mode, an ATU Miss Violation interrupt will occur when a new SA address +* is received in a frame on this port. Automatically SA learning and +* refreshing is disabled in this mode. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for Locked Port, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetLockedPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetLockedPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Locked Port. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 13, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetLockedPort +* +* DESCRIPTION: +* This routine gets Locked Port mode for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if LockedPort, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetLockedPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetLockedPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the LockedPort. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 13, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetIgnoreWrongData +* +* DESCRIPTION: +* This routine sets Ignore Wrong Data. If the frame's SA address is found +* in the database and if the entry is 'static' or if the port is 'locked' +* the source port's bit is checked to insure the SA has been assigned to +* this port. If the SA is NOT assigned to this port, it is considered an +* ATU Member Violation. If the IgnoreWrongData is set to GT_FALSE, an ATU +* Member Violation interrupt will be generated. If it's set to GT_TRUE, +* the ATU Member Violation error will be masked and ignored. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE for IgnoreWrongData, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIgnoreWrongData +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIgnoreWrongData Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set IgnoreWrongData. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 12, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetIgnoreWrongData +* +* DESCRIPTION: +* This routine gets Ignore Wrong Data mode for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if IgnoreWrongData, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIgnoreWrongData +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIgnoreWrongData Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Only Gigabit Switch supports this status. */ + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the IgnoreWrongData. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 12, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetDiscardTagged +* +* DESCRIPTION: +* When this bit is set to a one, all non-MGMT frames that are processed as +* Tagged will be discarded as they enter this switch port. Priority only +* tagged frames (with a VID of 0x000) are considered tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to discard tagged frame, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardTagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDiscardTagged Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set DiscardTagged. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 9, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetDiscardTagged +* +* DESCRIPTION: +* This routine gets DiscardTagged bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DiscardTagged bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardTagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDiscardTagged Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DiscardTagged. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 9, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetDiscardUntagged +* +* DESCRIPTION: +* When this bit is set to a one, all non-MGMT frames that are processed as +* Untagged will be discarded as they enter this switch port. Priority only +* tagged frames (with a VID of 0x000) are considered tagged. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to discard untagged frame, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardUntagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDiscardUntagged Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set DiscardUnTagged. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 8, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetDiscardUntagged +* +* DESCRIPTION: +* This routine gets DiscardUntagged bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DiscardUntagged bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardUntagged +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDiscardUnTagged Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DiscardUnTagged. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 8, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetMapDA +* +* DESCRIPTION: +* When this bit is set to a one, normal switch operation will occur where a +* frame's DA address is used to direct the frame out the correct port. +* When this be is cleared to a zero, the frame will be sent out the port(s) +* defined by ForwardUnknown bits or the DefaultForward bits even if the DA +* is ound in the address database. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to use MapDA, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetMapDA +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetMapDA Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set MapDA. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 7, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetMapDA +* +* DESCRIPTION: +* This routine gets MapDA bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if MapDA bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetMapDA +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetMapDA Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY|DEV_ENHANCED_FE_SWITCH)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the MapDA. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 7, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetDefaultForward +* +* DESCRIPTION: +* When this bit is set to a one, normal switch operation will occurs and +* multicast frames with unknown DA addresses are allowed to egress out this +* port (assuming the VLAN settings allow the frame to egress this port too). +* When this bit is cleared to a zero, multicast frames with unknown DA +* addresses will not egress out this port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to use DefaultForward, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetDefaultForward +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDefaultForward Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set DefaultForward. */ + if (!IS_IN_DEV_GROUP(dev,DEV_EGRESS_FLOOD)) + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 6, 1, data); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 3, 1, data); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetDefaultForward +* +* DESCRIPTION: +* This routine gets DefaultForward bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if DefaultForward bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDefaultForward +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetDefaultForward Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the DefaultForward. */ + if (!IS_IN_DEV_GROUP(dev,DEV_EGRESS_FLOOD)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 6, 1, &data); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 3, 1, &data); + } + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + +/******************************************************************************* +* gprtSetEgressMonitorSource +* +* DESCRIPTION: +* When this be is cleared to a zero, normal network switching occurs. +* When this bit is set to a one, any frame that egresses out this port will +* also be sent to the EgressMonitorDest Port +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to set EgressMonitorSource, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetEgressMonitorSource Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set EgressMonitorSource. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 5, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetEgressMonitorSource +* +* DESCRIPTION: +* This routine gets EgressMonitorSource bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if EgressMonitorSource bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetEgressMonitorSource Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the EgressMonitorSource. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 5, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetIngressMonitorSource +* +* DESCRIPTION: +* When this be is cleared to a zero, normal network switching occurs. +* When this bit is set to a one, any frame that egresses out this port will +* also be sent to the EgressMonitorDest Port +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to set EgressMonitorSource, GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetIngressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIngressMonitorSource Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set IngressMonitorSource. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 4, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetIngressMonitorSource +* +* DESCRIPTION: +* This routine gets IngressMonitorSource bit for the given port +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE if IngressMonitorSource bit is set, GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetIngressMonitorSource +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIngressMonitorSource Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the IngressMonitorSource. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2, 4, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetMessagePort +* +* DESCRIPTION: +* When the Learn2All bit is set to one, learning message frames are +* generated. These frames will be sent out all ports whose Message Port is +* set to one. +* If this feature is used, it is recommended that all Marvell Tag ports, +* except for the CPU's port, have their MessagePort bit set to one. +* Ports that are not Marvell Tag ports should not have their Message Port +* bit set to one. +* +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to make this port a Message Port. GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetMessagePort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetMessagePort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set IngressMonitorSource. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 15, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetMessagePort +* +* DESCRIPTION: +* When the Learn2All bit is set to one, learning message frames are +* generated. These frames will be sent out all ports whose Message Port is +* set to one. +* If this feature is used, it is recommended that all Marvell Tag ports, +* except for the CPU's port, have their MessagePort bit set to one. +* Ports that are not Marvell Tag ports should not have their Message Port +* bit set to one. +* +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to make this port a Message Port. GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetMessagePort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetMessagePort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the IngressMonitorSource. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 15, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetTrunkPort +* +* DESCRIPTION: +* This function enables/disables and sets the trunk ID. +* +* INPUTS: +* port - the logical port number. +* en - GT_TRUE to make the port be a member of a trunk with the given trunkId. +* GT_FALSE, otherwise. +* trunkId - valid ID is 0 ~ 15. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if trunkId is neither valid nor INVALID_TRUNK_ID +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetTrunkPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en, + IN GT_U32 trunkId +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetTrunkPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(en, data); + + if(en == GT_TRUE) + { + /* need to enable trunk. so check the trunkId */ + if (!IS_TRUNK_ID_VALID(dev, trunkId)) + { + DBG_INFO(("GT_BAD_PARAM\n")); + return GT_BAD_PARAM; + } + + /* Set TrunkId. */ + if (IS_IN_DEV_GROUP(dev,DEV_TRUNK_NEW_ID_LOCATION)) + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 8, 4, (GT_U16)trunkId); + } + else + { + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 4, 4, (GT_U16)trunkId); + } + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + } + else + { + /* + Need to reset trunkId for 88E6095 rev0. + */ + if (IS_IN_DEV_GROUP(dev,DEV_NEW_FEATURE_IN_REV) && + ((GT_DEVICE_REV)dev->revision < GT_REV_1)) + { + trunkId = 0; + + /* Set TrunkId. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 4, 4, (GT_U16)trunkId); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + } + } + + /* Set TrunkPort bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 14, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetTrunkPort +* +* DESCRIPTION: +* This function returns trunk state of the port. +* When trunk is disabled, trunkId field won't have valid value. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* en - GT_TRUE, if the port is a member of a trunk, +* GT_FALSE, otherwise. +* trunkId - 0 ~ 15, valid only if en is GT_TRUE +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetTrunkPort +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en, + OUT GT_U32 *trunkId +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetTrunkPort Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_TRUNK)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = 0; + + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 14, 1, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data, *en); + + if (IS_IN_DEV_GROUP(dev,DEV_TRUNK_NEW_ID_LOCATION)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 8, 4, &data); + } + else + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL1, 4, 4, &data); + } + + *trunkId = (GT_U32)data; + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetDiscardBCastMode +* +* DESCRIPTION: +* This routine gets the Discard Broadcast Mode. If the mode is enabled, +* all the broadcast frames to the given port will be discarded. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* en - GT_TRUE, if enabled, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetDiscardBCastMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetDiscardBCastMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_DROP_BCAST)) + { + if (!IS_IN_DEV_GROUP(dev,DEV_NEW_FEATURE_IN_REV) || + ((GT_DEVICE_REV)dev->revision < GT_REV_1)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + } + + data = 0; + + retVal = hwGetPortRegField(dev,hwPort, 0x15, 6, 1, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data, *en); + + return GT_OK; +} + + +/******************************************************************************* +* gprtSetDiscardBCastMode +* +* DESCRIPTION: +* This routine sets the Discard Broadcast mode. +* If the mode is enabled, all the broadcast frames to the given port will +* be discarded. +* +* INPUTS: +* port - logical port number +* en - GT_TRUE, to enable the mode, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetDiscardBCastMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +) +{ + GT_U16 data; /* Used to poll the data */ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetDiscardBCastMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_DROP_BCAST)) + { + if (!IS_IN_DEV_GROUP(dev,DEV_NEW_FEATURE_IN_REV) || + ((GT_DEVICE_REV)dev->revision < GT_REV_1)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + } + + /* translate BOOL to binary */ + BOOL_2_BIT(en, data); + + retVal = hwSetPortRegField(dev,hwPort, 0x15, 6, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + +/******************************************************************************* +* gprtGetFCOnRateLimitMode +* +* DESCRIPTION: +* This routine returns mode that tells if ingress rate limiting uses Flow +* Control. When this mode is enabled and the port receives frames over the +* limit, Ingress Rate Limiting will be performed by stalling the +* link partner using flow control, instead of discarding frames. +* +* INPUTS: +* port - logical port number +* +* OUTPUTS: +* en - GT_TRUE, if the mode is enabled, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* In order for this mode to work, Flow Control and Rate Limiting +* should be configured properly. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetFCOnRateLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetFCOnRateLimitMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_BURST_RATE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = 0; + + retVal = hwGetPortRegField(dev,hwPort, 0x15, 4, 2, &data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if (data == 0x3) + *en = GT_TRUE; + else + *en = GT_FALSE; + + return GT_OK; +} + + +/******************************************************************************* +* gprtSetFCOnRateLimitMode +* +* DESCRIPTION: +* This routine sets the mode that tells if ingress rate limiting uses Flow +* Control. When this mode is enabled and the port receives frames over the +* limit, Ingress Rate Limiting will be performed by stalling the +* link partner using flow control, instead of discarding frames. +* +* INPUTS: +* port - logical port number +* en - GT_TRUE, to enable the mode, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* This routine won't configure Flow Control or Rate Limiting. +* In order for this mode to work, Flow Control and Rate Limiting +* should be configured properly. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetFCOnRateLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL en +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetFCOnRateLimitMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if the given Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_BURST_RATE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + if (en) + data = 0x3; + else + data = 0; + + retVal = hwSetPortRegField(dev,hwPort, 0x15, 4, 2, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + return GT_OK; +} + + +/******************************************************************************* +* gprtSetSAFiltering +* +* DESCRIPTION: +* This routine set the Source Address(SA) fitering method. +* GT_SA_FILTERING_DISABLE : +* no frame will be filtered. +* GT_SA_DROP_ON_LOCK : +* discard if SA field is not in the ATU's address database. +* GT_SA_DROP_ON_UNLOCK : +* discard if SA field is in the ATU's address database as Static +* entry with a PortVec of all zeros. +* GT_SA_DROP_TO_CPU : +* Ingressing frames will be mapped to the CPU Port if their SA +* field is in the ATU's address database as Static entry with a +* PortVec of all zeros. Otherwise, the frames will be discarded +* if their SA field is not in the ATU's address database or if this +* port's bit is not set in the PortVec bits for the frame's SA. +* +* INPUTS: +* port - the logical port number. +* mode - GT_SA_FILTERING structure +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtSetSAFiltering +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_SA_FILTERING mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + + DBG_INFO(("gprtSetSAFiltering Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_SA_FILTERING)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + data = (GT_U16) mode; + + /* Set the SA Filtering bits. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,14,2,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtGetSAFiltering +* +* DESCRIPTION: +* This routine gets the Source Address(SA) fitering method. +* GT_SA_FILTERING_DISABLE : +* no frame will be filtered. +* GT_SA_DROP_ON_LOCK : +* discard if SA field is not in the ATU's address database. +* GT_SA_DROP_ON_UNLOCK : +* discard if SA field is in the ATU's address database as Static +* entry with a PortVec of all zeros. +* GT_SA_DROP_TO_CPU : +* Ingressing frames will be mapped to the CPU Port if their SA +* field is in the ATU's address database as Static entry with a +* PortVec of all zeros. Otherwise, the frames will be discarded +* if their SA field is not in the ATU's address database or if this +* port's bit is not set in the PortVec bits for the frame's SA. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_SA_FILTERING structure +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtGetSAFiltering +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_SA_FILTERING *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + + DBG_INFO(("gprtSetSAFiltering Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_SA_FILTERING)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the SA Filtering bits. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,14,2,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *mode = (GT_SA_FILTERING)data; + + return retVal; +} + + +/******************************************************************************* +* gprtSetARPtoCPU +* +* DESCRIPTION: +* When ARPtoCPU (or ARP Mirror) is set to GT_TRUE, ARP frames are mirrored +* to the CPU port. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE, to map ARP frames to CPU Port, +* GT_FALSE, otherwise. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtSetARPtoCPU +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetARPtoCPU Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_ARP_TO_CPU)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set the ARPtoCPU bits. */ + if (IS_IN_DEV_GROUP(dev,DEV_FASTETH_SWITCH)) + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,8,1,data); + else + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,6,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtGetARPtoCPU +* +* DESCRIPTION: +* When ARPtoCPU (or ARP Mirror) is set to GT_TRUE, ARP frames are mirrored +* to the CPU port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE, to map ARP frames to CPU Port, +* GT_FALSE, otherwise. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +*******************************************************************************/ +GT_STATUS gprtGetARPtoCPU +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetARPtoCPU Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device supports the feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_ARP_TO_CPU)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the ARPtoCPU bits. */ + if (IS_IN_DEV_GROUP(dev,DEV_FASTETH_SWITCH)) + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,8,1,&data); + else + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL2,6,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + BIT_2_BOOL(data, *mode); + + return retVal; +} + + +/******************************************************************************* +* gprtSetEgressFlood +* +* DESCRIPTION: +* This routine set Egress Flooding Mode. +* Frames with unknown DA (Destination Address that is not in ATU database) +* generally flood out all the ports. This mode can be used to prevent +* those frames from egressing this port as follows: +* GT_BLOCK_EGRESS_UNKNOWN +* do not egress frame with unknown DA (both unicast and multicast) +* GT_BLOCK_EGRESS_UNKNOWN_MULTICAST +* do not egress frame with unknown multicast DA +* GT_BLOCK_EGRESS_UNKNOWN_UNICAST +* do not egress frame with unknown unicast DA +* GT_BLOCK_EGRESS_NONE +* egress all frames with unknown DA +* +* INPUTS: +* port - the logical port number. +* mode - GT_EGRESS_FLOOD type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetEgressFlood +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_EGRESS_FLOOD mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + + DBG_INFO(("gprtSetEgressFlood Called.\n")); + + /* check if device supports the feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_EGRESS_FLOOD)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + data = (GT_U16) mode; + + /* Set the Egress Flood mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,2,2,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetEgressFlood +* +* DESCRIPTION: +* This routine gets Egress Flooding Mode. +* Frames with unknown DA (Destination Address that is not in ATU database) +* generally flood out all the ports. This mode can be used to prevent +* those frames from egressing this port as follows: +* GT_BLOCK_EGRESS_UNKNOWN +* do not egress frame with unknown DA (both unicast and multicast) +* GT_BLOCK_EGRESS_UNKNOWN_MULTICAST +* do not egress frame with unknown multicast DA +* GT_BLOCK_EGRESS_UNKNOWN_UNICAST +* do not egress frame with unknown unicast DA +* GT_BLOCK_EGRESS_NONE +* egress all frames with unknown DA +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_EGRESS_FLOOD type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetEgressFlood +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_EGRESS_FLOOD *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetEgressFlood Called.\n")); + + /* check if device supports the feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_EGRESS_FLOOD)) + { + DBG_INFO(("GT_NOT_SUPPORTED.\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* get the Egress Flood mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL,2,2,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *mode = (GT_EGRESS_FLOOD) data; + + return retVal; +} + + +/******************************************************************************* +* gprtSetPortSched +* +* DESCRIPTION: +* This routine sets Port Scheduling Mode. +* When usePortSched is enablied, this mode is used to select the Queue +* controller's scheduling on the port as follows: +* GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling +* GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme +* +* INPUTS: +* port - the logical port number +* mode - GT_PORT_SCHED_MODE enum type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPortSched +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PORT_SCHED_MODE mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetPortSched Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_SCHEDULE|DEV_PORT_MIXED_SCHEDULE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_PORT_MIXED_SCHEDULE)) + { + switch(mode) + { + case GT_PORT_SCHED_WEIGHTED_RRB: + data = 0; + break; + case GT_PORT_SCHED_STRICT_PRI: + data = 3; + break; + case GT_PORT_SCHED_STRICT_PRI3: + data = 1; + break; + case GT_PORT_SCHED_STRICT_PRI2_3: + data = 2; + break; + default: + return GT_BAD_PARAM; + } + + retVal = hwSetPortRegField(dev,hwPort, QD_REG_RATE_CTRL, 12,2,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; + + } + + + data = mode; + + /* Set the gprtSetPortSched mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,14,1,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetPortSched +* +* DESCRIPTION: +* This routine gets Port Scheduling Mode. +* When usePortSched is enablied, this mode is used to select the Queue +* controller's scheduling on the port as follows: +* GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling +* GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_PORT_SCHED_MODE enum type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPortSched +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_PORT_SCHED_MODE *mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPortSched Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_SCHEDULE|DEV_PORT_MIXED_SCHEDULE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (IS_IN_DEV_GROUP(dev,DEV_PORT_MIXED_SCHEDULE)) + { + retVal = hwGetPortRegField(dev,hwPort, QD_REG_RATE_CTRL, 12,2,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + switch(data) + { + case 0: + *mode = GT_PORT_SCHED_WEIGHTED_RRB; + break; + case 1: + *mode = GT_PORT_SCHED_STRICT_PRI3; + break; + case 2: + *mode = GT_PORT_SCHED_STRICT_PRI2_3; + break; + case 3: + *mode = GT_PORT_SCHED_STRICT_PRI; + break; + default: + return GT_BAD_PARAM; + } + + return GT_OK; + + } + + /* Get the gprtGetPortSched mode. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION,14,1,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *mode = (GT_PORT_SCHED_MODE)data; + + return retVal; +} + + +/******************************************************************************* +* gprtSetProviderTag +* +* DESCRIPTION: +* This routine sets Provider Tag which indicates the provider tag (Ether +* Type) value that needs to be matched to in ingress to determine if a +* frame is Provider tagged or not. +* +* INPUTS: +* port - the logical port number +* tag - Provider Tag (Ether Type) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetProviderTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 tag +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetProviderTag Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PROVIDER_TAG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Set Provider Tag. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PROVIDER_TAG, 0, 16, tag); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetProviderTag +* +* DESCRIPTION: +* This routine gets Provider Tag which indicates the provider tag (Ether +* Type) value that needs to be matched to in ingress to determine if a +* frame is Provider tagged or not. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* tag - Provider Tag (Ether Type) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetProviderTag +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *tag +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetProviderTag Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PROVIDER_TAG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Provider Tag. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PROVIDER_TAG, 0, 16, tag); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtSetPauseLimitOut +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be transmitted +* from this port. When full duplex Flow Control is enabled on this port, +* these bits are used to limit the number of Pause refresh frames that can +* be generated from this port to keep this port's link partner from sending +* any data. +* Setting this value to 0 will allow continuous Pause frame refreshes to +* egress this port as long as this port remains congested. +* Setting this value to 1 will allow 1 Pause frame to egress from this port +* for each congestion situation. +* Setting this value to 2 will allow 2 Pause frames to egress from this port +* for each congestion situation, etc. +* +* INPUTS: +* port - the logical port number +* limit - the max number of Pause refresh frames for each congestion situation +* ( 0 ~ 0xFF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPauseLimitOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 limit +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetPauseLimitOut Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PAUSE_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (limit > 0xFF) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set Pause Limit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_LIMIT_PAUSE_CONTROL, 8, 8, limit); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetPauseLimitOut +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be transmitted +* from this port. When full duplex Flow Control is enabled on this port, +* these bits are used to limit the number of Pause refresh frames that can +* be generated from this port to keep this port's link partner from sending +* any data. +* Setting this value to 0 will allow continuous Pause frame refreshes to +* egress this port as long as this port remains congested. +* Setting this value to 1 will allow 1 Pause frame to egress from this port +* for each congestion situation. +* Setting this value to 2 will allow 2 Pause frames to egress from this port +* for each congestion situation, etc. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* limit - the max number of Pause refresh frames for each congestion situation +* ( 0 ~ 0xFF) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPauseLimitOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *limit +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPauseLimitOut Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PAUSE_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Pause Limit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_LIMIT_PAUSE_CONTROL, 8, 8, limit); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtSetPauseLimitIn +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be received +* on this port. When a port has flow Control enabled, this value can be +* used to limit how long this port can be Paused off to prevent a port stall +* through jamming. +* When this value is in the range of 0x01 to 0xFF, and a frame is ready to +* be transmitted out this port, but it cannot be transmitted due to the port +* being jammed, this limit mechanism starts. The limit mechanism starts +* counting new Pause refresh frames or counts of 16 consecutive collisions. +* If the counter reaches the value set through this API, the following event +* will occur: +* 1) Port's ForceFC is enabled, +* 2) Port's FCValue is cleared to a zero, and +* 3) Jam Limit Interrupt is asserted. +* This effectively disables Flow Control on the port once the Pause timer +* expires. If a frame gets transmitted out this port before the counter +* reaches this limit, then this limit mechanism counter resets back to zero. +* +* Setting this value to 0 will allow continuous jamming to be received on +* this port without the Port's ForceFC and FCValue getting modified. +* +* The modification of Port's ForceFC and FCValue is the only indication that +* the limit was reached on this port. +* +* INPUTS: +* port - the logical port number +* limit - the max number of continuous Pause refresh frames for each trasmition +* ( 0 ~ 0xFF) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if limit > 0xFF +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPauseLimitIn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 limit +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetPauseLimitIn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PAUSE_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + if (limit > 0xFF) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set Pause Limit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_LIMIT_PAUSE_CONTROL, 0, 8, limit); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetPauseLimitIn +* +* DESCRIPTION: +* Limit the number of continuous Pause refresh frames that can be received +* on this port. When a port has flow Control enabled, this value can be +* used to limit how long this port can be Paused off to prevent a port stall +* through jamming. +* When this value is in the range of 0x01 to 0xFF, and a frame is ready to +* be transmitted out this port, but it cannot be transmitted due to the port +* being jammed, this limit mechanism starts. The limit mechanism starts +* counting new Pause refresh frames or counts of 16 consecutive collisions. +* If the counter reaches the value set through this API, the following event +* will occur: +* 1) Port's ForceFC is enabled, +* 2) Port's FCValue is cleared to a zero, and +* 3) Jam Limit Interrupt is asserted. +* This effectively disables Flow Control on the port once the Pause timer +* expires. If a frame gets transmitted out this port before the counter +* reaches this limit, then this limit mechanism counter resets back to zero. +* +* Setting this value to 0 will allow continuous jamming to be received on +* this port without the Port's ForceFC and FCValue getting modified. +* +* The modification of Port's ForceFC and FCValue is the only indication that +* the limit was reached on this port. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* limit - the max number of continuous Pause refresh frames for each trasmition +* ( 0 ~ 0xFF) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPauseLimitIn +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *limit +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPauseLimitIn Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PAUSE_LIMIT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Pause Limit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_LIMIT_PAUSE_CONTROL, 0, 8, limit); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtSetFrameMode +* +* DESCRIPTION: +* Frmae Mode is used to define the expected Ingress and the generated Egress +* tagging frame format for this port as follows: +* GT_FRAME_MODE_NORMAL - +* Normal Network mode uses industry standard IEEE 802.3ac Tagged or +* Untagged frames. Tagged frames use an Ether Type of 0x8100. +* GT_FRAME_MODE_DSA - +* DSA mode uses a Marvell defined tagged frame format for +* Chip-to-Chip and Chip-to-CPU connections. +* GT_FRAME_MODE_PROVIDER - +* Provider mode uses user definable Ether Types per port +* (see gprtSetPortEType/gprtGetPortEType API). +* GT_FRAME_MODE_ETHER_TYPE_DSA - +* Ether Type DSA mode uses standard Marvell DSA Tagged frame info +* flowing a user definable Ether Type. This mode allows the mixture +* of Normal Network frames with DSA Tagged frames and is useful to +* be used on ports that connect to a CPU. +* +* INPUTS: +* port - the logical port number +* mode - GT_FRAME_MODE type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - if mode is unknown +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetFrameMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_FRAME_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetFrameMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_FRAME_MODE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (mode) + { + case GT_FRAME_MODE_NORMAL: + case GT_FRAME_MODE_DSA: + case GT_FRAME_MODE_PROVIDER: + case GT_FRAME_MODE_ETHER_TYPE_DSA: + break; + default: + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + /* Set Frame Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 8, 2, (GT_U16)mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + +/******************************************************************************* +* gprtGetFrameMode +* +* DESCRIPTION: +* Frmae Mode is used to define the expected Ingress and the generated Egress +* tagging frame format for this port as follows: +* GT_FRAME_MODE_NORMAL - +* Normal Network mode uses industry standard IEEE 802.3ac Tagged or +* Untagged frames. Tagged frames use an Ether Type of 0x8100. +* GT_FRAME_MODE_DSA - +* DSA mode uses a Marvell defined tagged frame format for +* Chip-to-Chip and Chip-to-CPU connections. +* GT_FRAME_MODE_PROVIDER - +* Provider mode uses user definable Ether Types per port +* (see gprtSetPortEType/gprtGetPortEType API). +* GT_FRAME_MODE_ETHER_TYPE_DSA - +* Ether Type DSA mode uses standard Marvell DSA Tagged frame info +* flowing a user definable Ether Type. This mode allows the mixture +* of Normal Network frames with DSA Tagged frames and is useful to +* be used on ports that connect to a CPU. +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* mode - GT_FRAME_MODE type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetFrameMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_FRAME_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetFrameMode Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_FRAME_MODE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get Pause Limit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_CONTROL, 8, 2, &data); + *mode = data; + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtSetHoldAt1 +* +* DESCRIPTION: +* Hold Aging ATU Entries at an Entry State value of 1. When this feature +* is set to GT_TRUE, ATU entries associated with this port will age down +* to an Entry State of 0x1, but will not go to 0x0 (0x0 would purge the +* entry) +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to hold aging ATU entry with Entry State of 1, +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetHoldAt1 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetHoldAt1 Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_HOLD)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set HoldAt1 */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 15, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetHoldAt1 +* +* DESCRIPTION: +* Hold Aging ATU Entries at an Entry State value of 1. When this feature +* is set to GT_TRUE, ATU entries associated with this port will age down +* to an Entry State of 0x1, but will not go to 0x0 (0x0 would purge the +* entry) +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to hold aging ATU entry with Entry State of 1, +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetHoldAt1 +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetHoldAt1 Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_HOLD)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get HoldAt1 */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 15, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetIntOnAgeOut +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable AgeOutViloation interrupt +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetIntOnAgeOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetIntOnAgeOut Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set Age Out Interrupt Enable Mode. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 14, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetIntOnAgeOut +* +* DESCRIPTION: +* Interrupt on Age Out. When aging is enabled, all non-static address +* entries in the ATU's address database are periodically aged. +* When this feature is set to GT_TRUE and an entry associated with this +* port is aged out, an AgeOutViolation will be captured for that entry. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable AgeOutViloation interrupt +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetIntOnAgeOut +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetIntOnAgeOut Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AGE_OUT_INT)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get IntOnAgeOut */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 14, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetRefreshLocked +* +* DESCRIPTION: +* Auto Refresh known addresses when port is Locked. Already known addresses +* will be auto refreshed when this feature is enabled. When this feature +* is disabled, auto refreshing will not occur on Locked ports. +* +* INPUTS: +* port - the logical port number. +* mode - GT_TRUE to enable Auto Refresh known addresses on locked port +* GT_FALSE otherwise +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetRefreshLocked +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetRefreshLocked Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AUTO_REFRESH_LOCKED)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate BOOL to binary */ + BOOL_2_BIT(mode, data); + + /* Set RefreshLocked */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 11, 1, data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetRefreshLocked +* +* DESCRIPTION: +* Auto Refresh known addresses when port is Locked. Already known addresses +* will be auto refreshed when this feature is enabled. When this feature +* is disabled, auto refreshing will not occur on Locked ports. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_TRUE to enable Auto Refresh known addresses on locked port +* GT_FALSE otherwise +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetRefreshLocked +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gprtGetRefreshLocked Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* check if device allows to force a flowcontrol disabled */ + if (!IS_IN_DEV_GROUP(dev,DEV_AUTO_REFRESH_LOCKED)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get RefreshLocked */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_ASSOCIATION, 11, 1, &data); + + BIT_2_BOOL(data, *mode); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtSetPortEType +* +* DESCRIPTION: +* This routine sets the port's special Ether Type. This Ether Type is used +* for Policy (see gprtSetPolicy API) and FrameMode (see gprtSetFrameMode API). +* +* INPUTS: +* port - the logical port number +* etype - port's special ether type +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtSetPortEType +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_ETYPE etype +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetPortEType Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_ETYPE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + data = (GT_U16)etype; + + /* Set the EtherType. */ + retVal = hwWritePortReg(dev,hwPort, QD_REG_PORT_ETH_TYPE,data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + return retVal; +} + + +/******************************************************************************* +* gprtGetPortEType +* +* DESCRIPTION: +* This routine retrieves the port's special Ether Type. This Ether Type is used +* for Policy (see gprtSetPolicy API) and FrameMode (see gprtSetFrameMode API). +* +* INPUTS: +* port - the logical port number +* +* OUTPUTS: +* etype - port's special ether type +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gprtGetPortEType +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_ETYPE *etype +) +{ + GT_U16 data; + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetPortEType Called.\n")); + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (!IS_IN_DEV_GROUP(dev,DEV_PORT_ETYPE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the EtherType. */ + retVal = hwReadPortReg(dev,hwPort, QD_REG_PORT_ETH_TYPE,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *etype = (GT_ETYPE) data; + + return retVal; +} + + +/******************************************************************************* +* gsysSetJumboMode +* +* DESCRIPTION: +* This routine Set the max frame size allowed to be received and transmitted +* from or to a given port. +* +* INPUTS: +* port - the logical port number +* mode - GT_JUMBO_MODE (1522, 2048, or 10240) +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gsysSetJumboMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_JUMBO_MODE mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gsysSetJumboMode Called.\n")); + + if (mode > GT_JUMBO_MODE_10240) + { + DBG_INFO(("Bad Parameter\n")); + return GT_BAD_PARAM; + } + + if (!IS_IN_DEV_GROUP(dev,DEV_JUMBO_MODE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Set the Jumbo Fram Size bit. */ + retVal = hwSetPortRegField(dev,hwPort,QD_REG_PORT_CONTROL2,12,2,(GT_U16)mode); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gsysGetJumboMode +* +* DESCRIPTION: +* This routine gets the max frame size allowed to be received and transmitted +* from or to a given port. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - GT_JUMBO_MODE (1522, 2048, or 10240) +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* +*******************************************************************************/ +GT_STATUS gsysGetJumboMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_JUMBO_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; /* to keep the read valve */ + + DBG_INFO(("gsysGetJumboMode Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_JUMBO_MODE)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + /* Get Jumbo Frame Mode. */ + retVal = hwGetPortRegField(dev,hwPort,QD_REG_PORT_CONTROL2,12,2,&data ); + + *mode = (GT_JUMBO_MODE)data; + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + return retVal; +} + + +/******************************************************************************* +* gprtGet200Base +* +* DESCRIPTION: +* 200 Base mode. This bit can be used to change the port's Px_GTXCLK +* frequency to 50MHz to support 200 BASE mode as follows: +* 0 = 25MHz Px_GTXCLK +* 1 = 50MHz Px_GTXCLK +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - 0 for 100Mbps, 1 for 200Mbps +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* C_Mode should be set to 0x2 in order for this API to work +* +*******************************************************************************/ +GT_STATUS gprtGet200Base +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U32 *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + GT_U16 data; + + DBG_INFO(("gprtGet200Base Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_200BASE_CFG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (hwPort < (dev->maxPorts - 2)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* Get the high error rate bit. */ + retVal = hwGetPortRegField(dev,hwPort, QD_REG_PORT_STATUS,6,1,&data); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + *mode = (GT_U32)data; + + /* return */ + return retVal; +} + +/******************************************************************************* +* gprtSet200Base +* +* DESCRIPTION: +* 200 Base mode. This bit can be used to change the port's Px_GTXCLK +* frequency to 50MHz to support 200 BASE mode as follows: +* 0 = 25MHz Px_GTXCLK +* 1 = 50MHz Px_GTXCLK +* +* INPUTS: +* port - the logical port number. +* mode - 0 for 100Mbps, 1 for 200Mbps +* +* OUTPUTS: +* None +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* C_Mode should be set to 0x2 in order for this API to work +* +*******************************************************************************/ +GT_STATUS gprtSet200Base +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSet200Base Called.\n")); + + if (!IS_IN_DEV_GROUP(dev,DEV_200BASE_CFG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + /* translate LPORT to hardware port */ + hwPort = GT_LPORT_2_PORT(port); + + if (hwPort < (dev->maxPorts - 2)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_BAD_PARAM; + } + + /* Get the high error rate bit. */ + retVal = hwSetPortRegField(dev,hwPort, QD_REG_PORT_STATUS,6,1,(GT_U16)(mode&0x1)); + + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + } + else + { + DBG_INFO(("OK.\n")); + } + + /* return */ + return retVal; +} + + +/******************************************************************************* +* gprtGetSwitchReg +* +* DESCRIPTION: +* This routine reads Switch Port Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetSwitchReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + OUT GT_U16 *data +) +{ + GT_U16 u16Data; /* The register's read data. */ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetSwitchReg Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + + /* Get Phy Register. */ + if(hwReadPortReg(dev,hwPort,(GT_U8)regAddr,&u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + *data = u16Data; + + return GT_OK; +} + +/******************************************************************************* +* gprtSetSwitchReg +* +* DESCRIPTION: +* This routine writes Switch Port Registers. +* +* INPUTS: +* port - logical port number +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetSwitchReg +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U32 regAddr, + IN GT_U16 data +) +{ + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetSwitchReg Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + + /* Get the Scheduling bit. */ + if(hwWritePortReg(dev,hwPort,(GT_U8)regAddr,data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + return GT_OK; +} + + +/******************************************************************************* +* gprtGetGlobalReg +* +* DESCRIPTION: +* This routine reads Switch Global Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + OUT GT_U16 *data +) +{ + GT_U16 u16Data; /* The register's read data. */ + + DBG_INFO(("gprtGetGlobalReg Called.\n")); + + /* Get Phy Register. */ + if(hwReadGlobalReg(dev,(GT_U8)regAddr,&u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + *data = u16Data; + + return GT_OK; +} + +/******************************************************************************* +* gprtSetGlobalReg +* +* DESCRIPTION: +* This routine writes Switch Global Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetGlobalReg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + IN GT_U16 data +) +{ + DBG_INFO(("gprtSetGlobalReg Called.\n")); + + /* Get the Scheduling bit. */ + if(hwWriteGlobalReg(dev,(GT_U8)regAddr,data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + return GT_OK; +} + +/******************************************************************************* +* gprtGetGlobal2Reg +* +* DESCRIPTION: +* This routine reads Switch Global 2 Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtGetGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + OUT GT_U16 *data +) +{ + GT_U16 u16Data; /* The register's read data. */ + + DBG_INFO(("gprtGetGlobal2Reg Called.\n")); + + /* Get Phy Register. */ + if(hwReadGlobal2Reg(dev,(GT_U8)regAddr,&u16Data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + *data = u16Data; + + return GT_OK; +} + +/******************************************************************************* +* gprtSetGlobal2Reg +* +* DESCRIPTION: +* This routine writes Switch Global2 Registers. +* +* INPUTS: +* regAddr - The register's address. +* +* OUTPUTS: +* data - The read register's data. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* None. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gprtSetGlobal2Reg +( + IN GT_QD_DEV *dev, + IN GT_U32 regAddr, + IN GT_U16 data +) +{ + DBG_INFO(("gprtSetGlobal2Reg Called.\n")); + + /* Get the Scheduling bit. */ + if(hwWriteGlobal2Reg(dev,(GT_U8)regAddr,data) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return GT_FAIL; + } + + return GT_OK; +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortLed.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortLed.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortLed.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortLed.c 2011-04-04 13:57:35.105597042 -0400 @@ -0,0 +1,801 @@ +#include + +/******************************************************************************** +* gtPortLed.c +* +* DESCRIPTION: +* API definitions for LED Control +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: $ +*******************************************************************************/ + +#include +#include +#include +#include + + +static GT_STATUS convertLED2APP +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value, + OUT GT_U32 *data +); + + +static GT_STATUS convertAPP2LED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value, + OUT GT_U32 *data +); + + +/******************************************************************************* +* gprtSetLED +* +* DESCRIPTION: +* This API allows to configure 4 LED sections, Pulse stretch, Blink rate, +* and special controls. +* +* INPUTS: +* port - the logical port number +* cfg - GT_LED_CFG value +* value - value to be configured +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gprtSetLED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + GT_U32 ptr, conv, mask; + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtSetLED Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + if (hwPort >= 5) + return GT_BAD_PARAM; + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_LED_CFG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (cfg) + { + case GT_LED_CFG_LED0: + ptr = 0; + mask = 0xF; + break; + case GT_LED_CFG_LED1: + ptr = 0; + mask = 0xF0; + break; + case GT_LED_CFG_LED2: + ptr = 1; + mask = 0xF; + break; + case GT_LED_CFG_LED3: + ptr = 1; + mask = 0xF0; + break; + case GT_LED_CFG_PULSE_STRETCH: + ptr = 6; + mask = 0x70; + break; + case GT_LED_CFG_BLINK_RATE: + ptr = 6; + mask = 0x7; + break; + case GT_LED_CFG_SPECIAL_CONTROL: + ptr = 7; + mask = (1 << dev->maxPorts) - 1; + break; + default: + return GT_BAD_PARAM; + } + + retVal = convertAPP2LED(dev,port,cfg,value,&conv); + if (retVal != GT_OK) + { + return retVal; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* Wait until the Table is ready. */ + do + { + retVal = hwGetPortRegField(dev,hwPort,QD_REG_LED_CONTROL,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + } while(data == 1); + + /* read the current data */ + data = (GT_U16)(ptr << 12); + + retVal = hwWritePortReg(dev, hwPort, QD_REG_LED_CONTROL, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + retVal = hwGetPortRegField(dev, hwPort, QD_REG_LED_CONTROL,0,11,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + /* overwrite the data */ + data = (GT_U16)((1 << 15) | (ptr << 12) | (conv | (data & ~mask))); + + retVal = hwWritePortReg(dev, hwPort, QD_REG_LED_CONTROL, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + gtSemGive(dev,dev->tblRegsSem); + + return GT_OK; +} + + +/******************************************************************************* +* gprtGetLED +* +* DESCRIPTION: +* This API allows to retrieve 4 LED sections, Pulse stretch, Blink rate, +* and special controls. +* +* INPUTS: +* port - the logical port number +* cfg - GT_LED_CFG value +* +* OUTPUTS: +* value - value to be configured +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_NOT_SUPPORTED - if current device does not support this feature. +* +* COMMENTS: +* None +* +*******************************************************************************/ +GT_STATUS gprtGetLED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + OUT GT_U32 *value +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + GT_U32 ptr; + GT_U8 hwPort; /* the physical port number */ + + DBG_INFO(("gprtGetLED Called.\n")); + + hwPort = GT_LPORT_2_PORT(port); + if (hwPort >= 5) + return GT_BAD_PARAM; + + /* Check if Switch supports this feature. */ + if (!IS_IN_DEV_GROUP(dev,DEV_LED_CFG)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + switch (cfg) + { + case GT_LED_CFG_LED0: + ptr = 0; + break; + case GT_LED_CFG_LED1: + ptr = 0; + break; + case GT_LED_CFG_LED2: + ptr = 1; + break; + case GT_LED_CFG_LED3: + ptr = 1; + break; + case GT_LED_CFG_PULSE_STRETCH: + ptr = 6; + break; + case GT_LED_CFG_BLINK_RATE: + ptr = 6; + break; + case GT_LED_CFG_SPECIAL_CONTROL: + ptr = 7; + break; + default: + return GT_BAD_PARAM; + } + + gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER); + + /* Wait until the Table is ready. */ + do + { + retVal = hwGetPortRegField(dev,hwPort,QD_REG_LED_CONTROL,15,1,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + } while(data == 1); + + /* read the current data */ + data = (GT_U16)(ptr << 12); + + retVal = hwWritePortReg(dev, hwPort, QD_REG_LED_CONTROL, data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + retVal = hwGetPortRegField(dev, hwPort, QD_REG_LED_CONTROL,0,11,&data); + if(retVal != GT_OK) + { + gtSemGive(dev,dev->tblRegsSem); + return retVal; + } + + retVal = convertLED2APP(dev,port,cfg,data,value); + if (retVal != GT_OK) + { + return retVal; + } + + + gtSemGive(dev,dev->tblRegsSem); + + return GT_OK; +} + + +static GT_STATUS convertAPP2LED +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value, + OUT GT_U32 *data +) +{ + GT_STATUS retVal = GT_OK; + + switch (cfg) + { + case GT_LED_CFG_LED0: + switch (value) + { + case GT_LED_LINK_ACT: + *data = 3; + break; + case GT_LED_LINK: + *data = 8; + break; + case GT_LED_10_LINK_ACT: + *data = 10; + break; + case GT_LED_10_LINK: + *data = 9; + break; + case GT_LED_1000_LINK_ACT: + *data = 2; + break; + case GT_LED_100_1000_LINK_ACT: + *data = 1; + break; + case GT_LED_100_1000_LINK: + *data = 11; + break; + case GT_LED_SPECIAL: + *data = 7; + break; + case GT_LED_DUPLEX_COL: + *data = 6; + break; + case GT_LED_PTP_ACT: + *data = 0; + break; + case GT_LED_FORCE_BLINK: + *data = 13; + break; + case GT_LED_FORCE_OFF: + *data = 14; + break; + case GT_LED_FORCE_ON: + *data = 15; + break; + default: + retVal = GT_BAD_PARAM; + break; + } + break; + + case GT_LED_CFG_LED1: + switch (value) + { + case GT_LED_LINK_ACT_SPEED: + *data = 0; + break; + case GT_LED_100_LINK_ACT: + *data = 10; + break; + case GT_LED_100_LINK: + *data = 9; + break; + case GT_LED_1000_LINK: + *data = 3; + break; + case GT_LED_10_100_LINK_ACT: + *data = 1; + break; + case GT_LED_10_100_LINK: + *data = 11; + break; + case GT_LED_SPECIAL: + *data = 6; + break; + case GT_LED_DUPLEX_COL: + *data = 7; + break; + case GT_LED_ACTIVITY: + *data = 8; + break; + case GT_LED_PTP_ACT: + *data = 12; + break; + case GT_LED_FORCE_BLINK: + *data = 13; + break; + case GT_LED_FORCE_OFF: + *data = 14; + break; + case GT_LED_FORCE_ON: + *data = 15; + break; + default: + retVal = GT_BAD_PARAM; + break; + } + *data <<= 4; + break; + + case GT_LED_CFG_LED2: + switch (value) + { + case GT_LED_10_LINK_ACT: + *data = 6; + break; + case GT_LED_100_LINK: + *data = 8; + break; + case GT_LED_1000_LINK_ACT: + *data = 10; + break; + case GT_LED_1000_LINK: + *data = 9; + break; + case GT_LED_10_1000_LINK_ACT: + *data = 1; + break; + case GT_LED_10_1000_LINK: + *data = 11; + break; + case GT_LED_100_1000_LINK_ACT: + *data = 7; + break; + case GT_LED_100_1000_LINK: + *data = 3; + break; + case GT_LED_SPECIAL: + *data = 2; + break; + case GT_LED_DUPLEX_COL: + *data = 0; + break; + case GT_LED_PTP_ACT: + *data = 12; + break; + case GT_LED_FORCE_BLINK: + *data = 13; + break; + case GT_LED_FORCE_OFF: + *data = 14; + break; + case GT_LED_FORCE_ON: + *data = 15; + break; + default: + retVal = GT_BAD_PARAM; + break; + } + break; + + case GT_LED_CFG_LED3: + switch (value) + { + case GT_LED_LINK_ACT: + *data = 10; + break; + case GT_LED_LINK: + *data = 9; + break; + case GT_LED_10_LINK: + *data = 8; + break; + case GT_LED_100_LINK_ACT: + *data = 6; + break; + case GT_LED_10_1000_LINK_ACT: + *data = 7; + break; + case GT_LED_SPECIAL: + *data = 0; + break; + case GT_LED_DUPLEX_COL: + *data = 1; + break; + case GT_LED_ACTIVITY: + *data = 11; + break; + case GT_LED_PTP_ACT: + *data = 12; + break; + case GT_LED_FORCE_BLINK: + *data = 13; + break; + case GT_LED_FORCE_OFF: + *data = 14; + break; + case GT_LED_FORCE_ON: + *data = 15; + break; + default: + retVal = GT_BAD_PARAM; + break; + } + *data <<= 4; + break; + + case GT_LED_CFG_PULSE_STRETCH: + if (value > 0x4) + retVal = GT_BAD_PARAM; + *data = value << 4; + break; + case GT_LED_CFG_BLINK_RATE: + if (value > 0x5) + retVal = GT_BAD_PARAM; + *data = value; + break; + + case GT_LED_CFG_SPECIAL_CONTROL: + if (value >= (GT_U32)(1 << dev->maxPorts)) + retVal = GT_BAD_PARAM; + *data = value; + break; + + default: + retVal = GT_BAD_PARAM; + break; + } + + return retVal; + +} + + +static GT_STATUS convertLED2APP +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_LED_CFG cfg, + IN GT_U32 value, + OUT GT_U32 *data +) +{ + GT_STATUS retVal = GT_OK; + + switch (cfg) + { + case GT_LED_CFG_LED0: + value &= 0xF; + switch (value) + { + case 0: + *data = GT_LED_PTP_ACT; + break; + case 1: + *data = GT_LED_100_1000_LINK_ACT; + break; + case 2: + *data = GT_LED_1000_LINK_ACT; + break; + case 3: + *data = GT_LED_LINK_ACT; + break; + case 4: + *data = GT_LED_RESERVE; + break; + case 5: + *data = GT_LED_RESERVE; + break; + case 6: + *data = GT_LED_DUPLEX_COL; + break; + case 7: + *data = GT_LED_SPECIAL; + break; + case 8: + *data = GT_LED_LINK; + break; + case 9: + *data = GT_LED_10_LINK; + break; + case 10: + *data = GT_LED_10_LINK_ACT; + break; + case 11: + *data = GT_LED_100_1000_LINK; + break; + case 12: + *data = GT_LED_PTP_ACT; + break; + case 13: + *data = GT_LED_FORCE_BLINK; + break; + case 14: + *data = GT_LED_FORCE_OFF; + break; + case 15: + *data = GT_LED_FORCE_ON; + break; + default: + retVal = GT_FAIL; + break; + } + break; + + case GT_LED_CFG_LED1: + value >>= 4; + value &= 0xF; + switch (value) + { + case 0: + *data = GT_LED_LINK_ACT_SPEED; + break; + case 1: + *data = GT_LED_10_100_LINK_ACT; + break; + case 2: + *data = GT_LED_10_100_LINK_ACT; + break; + case 3: + *data = GT_LED_1000_LINK; + break; + case 4: + *data = GT_LED_RESERVE; + break; + case 5: + *data = GT_LED_RESERVE; + break; + case 6: + *data = GT_LED_SPECIAL; + break; + case 7: + *data = GT_LED_DUPLEX_COL; + break; + case 8: + *data = GT_LED_ACTIVITY; + break; + case 9: + *data = GT_LED_100_LINK; + break; + case 10: + *data = GT_LED_100_LINK_ACT; + break; + case 11: + *data = GT_LED_10_100_LINK; + break; + case 12: + *data = GT_LED_PTP_ACT; + break; + case 13: + *data = GT_LED_FORCE_BLINK; + break; + case 14: + *data = GT_LED_FORCE_OFF; + break; + case 15: + *data = GT_LED_FORCE_ON; + break; + default: + retVal = GT_FAIL; + break; + } + break; + + case GT_LED_CFG_LED2: + value &= 0xF; + switch (value) + { + case 0: + *data = GT_LED_DUPLEX_COL; + break; + case 1: + *data = GT_LED_10_1000_LINK_ACT; + break; + case 2: + *data = GT_LED_SPECIAL; + break; + case 3: + *data = GT_LED_100_1000_LINK; + break; + case 4: + *data = GT_LED_RESERVE; + break; + case 5: + *data = GT_LED_RESERVE; + break; + case 6: + *data = GT_LED_10_LINK_ACT; + break; + case 7: + *data = GT_LED_100_1000_LINK_ACT; + break; + case 8: + *data = GT_LED_100_LINK; + break; + case 9: + *data = GT_LED_1000_LINK; + break; + case 10: + *data = GT_LED_1000_LINK_ACT; + break; + case 11: + *data = GT_LED_10_1000_LINK; + break; + case 12: + *data = GT_LED_PTP_ACT; + break; + case 13: + *data = GT_LED_FORCE_BLINK; + break; + case 14: + *data = GT_LED_FORCE_OFF; + break; + case 15: + *data = GT_LED_FORCE_ON; + break; + default: + retVal = GT_FAIL; + break; + } + break; + + case GT_LED_CFG_LED3: + value >>= 4; + value &= 0xF; + switch (value) + { + case 0: + *data = GT_LED_SPECIAL; + break; + case 1: + *data = GT_LED_DUPLEX_COL; + break; + case 2: + *data = GT_LED_DUPLEX_COL; + break; + case 3: + *data = GT_LED_SPECIAL; + break; + case 4: + *data = GT_LED_RESERVE; + break; + case 5: + *data = GT_LED_RESERVE; + break; + case 6: + *data = GT_LED_100_LINK_ACT; + break; + case 7: + *data = GT_LED_10_1000_LINK_ACT; + break; + case 8: + *data = GT_LED_10_LINK; + break; + case 9: + *data = GT_LED_LINK; + break; + case 10: + *data = GT_LED_LINK_ACT; + break; + case 11: + *data = GT_LED_ACTIVITY; + break; + case 12: + *data = GT_LED_PTP_ACT; + break; + case 13: + *data = GT_LED_FORCE_BLINK; + break; + case 14: + *data = GT_LED_FORCE_OFF; + break; + case 15: + *data = GT_LED_FORCE_ON; + break; + default: + retVal = GT_FAIL; + break; + } + break; + + case GT_LED_CFG_PULSE_STRETCH: + *data = (value >> 4) & 0x7; + break; + + case GT_LED_CFG_BLINK_RATE: + *data = value & 0x7; + break; + + case GT_LED_CFG_SPECIAL_CONTROL: + *data = value & ((1 << dev->maxPorts) - 1); + break; + + default: + retVal = GT_BAD_PARAM; + break; + } + + return retVal; + +} diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortPav.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortPav.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortPav.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortPav.c 2011-04-04 13:57:35.105597042 -0400 @@ -0,0 +1,270 @@ +#include + +/******************************************************************************** +* gtPortPav.c +* +* DESCRIPTION: +* API definitions to handle Port Association Vector (0xB). +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +*******************************************************************************/ + +#include +#include +#include + +/******************************************************************************* +* gpavSetPAV +* +* DESCRIPTION: +* This routine sets the Port Association Vector +* +* INPUTS: +* port - logical port number. +* pav - Port Association Vector +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpavSetPAV +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_U16 pav +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + GT_U16 hwPav; + + DBG_INFO(("gpavSetPAV Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_PORT_MONITORING)) != GT_OK ) + return retVal; + + /* + * translate Logical Port Vector to Physical Port Vector. + */ + hwPav = (GT_U16)GT_LPORTVEC_2_PORTVEC(pav); + + if(hwPav == (GT_U16)GT_INVALID_PORT_VEC) + { + return GT_BAD_PARAM; + } + + /* there are 7 ports in the switch */ + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_ASSOCIATION,0,dev->maxPorts,hwPav); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gpavGetPAV +* +* DESCRIPTION: +* This routine gets the Port Association Vector +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* pav - Port Association Vector +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpavGetPAV +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_U16 *pav +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gpavGetPAV Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_PORT_MONITORING)) != GT_OK ) + return retVal; + + if(pav == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + retVal = hwGetPortRegField(dev,phyPort,(GT_U8)QD_REG_PORT_ASSOCIATION,0,dev->maxPorts,&data ); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + /* + * translate Physical Port Vector to Logical Port Vector. + */ + *pav = (GT_U16)GT_PORTVEC_2_LPORTVEC(data); + + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* gpavSetIngressMonitor +* +* DESCRIPTION: +* This routine sets the Ingress Monitor bit in the PAV. +* +* INPUTS: +* port - the logical port number. +* mode - the ingress monitor bit in the PAV +* GT_FALSE: Ingress Monitor enabled +* GT_TRUE: Ingress Monitor disabled +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpavSetIngressMonitor +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("gpavSetIngressMonitorCalled.\n")); + + phyPort = GT_LPORT_2_PORT(port); + BOOL_2_BIT(mode,data); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_ENABLE_MONITORING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_ASSOCIATION,15,1,data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* gpavGetIngressMonitor +* +* DESCRIPTION: +* This routine gets the Ingress Monitor bit in the PAV. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the ingress monitor bit in the PAV +* GT_FALSE: Ingress Monitor enabled +* GT_TRUE: Ingress Monitor disabled +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS gpavGetIngressMonitor +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcGetIngressMonitor Called.\n")); + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if (!IS_IN_DEV_GROUP(dev,DEV_ENABLE_MONITORING)) + { + DBG_INFO(("GT_NOT_SUPPORTED\n")); + return GT_NOT_SUPPORTED; + } + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_ASSOCIATION,15,1,&data); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + diff -Naur u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortRateCtrl.c u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortRateCtrl.c --- u-boot-2009.08.orig/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortRateCtrl.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2009.08/board/marvell/mv_hal/qd-dsdt/src/msapi/gtPortRateCtrl.c 2011-04-04 13:57:35.115596594 -0400 @@ -0,0 +1,2807 @@ +#include + +/******************************************************************************** +* gtPortRateCtrl.c +* +* DESCRIPTION: +* API definitions to handle port rate control registers (0xA). +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 5 $ +*******************************************************************************/ + +#include +#include +#include + +/* + Convert given hw Rate Limit to sw defined Rate Limit. + This routine is only for Gigabit Managed Switch Device. + If the given device is not an accepted device, it'll simply copy the hw limit + to sw limit. +*/ +static GT_STATUS cRateLimit(GT_QD_DEV *dev, GT_U32 hwLimit, GT_U32* swLimit) +{ + GT_U32 sLimit, hLimit, startLimit, endLimit, i; + + if (!IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH|DEV_ENHANCED_FE_SWITCH)) + { + *swLimit = hwLimit; + return GT_OK; + } + + if(hwLimit == 0) + { + *swLimit = GT_NO_LIMIT; + return GT_OK; + } + + sLimit = 1000; + + if (IS_IN_DEV_GROUP(dev,DEV_ENHANCED_FE_SWITCH)) + hLimit = GT_GET_RATE_LIMIT3(sLimit); + else if (!IS_IN_DEV_GROUP(dev,DEV_88E6183_FAMILY)) + hLimit = GT_GET_RATE_LIMIT2(sLimit); + else + hLimit = GT_GET_RATE_LIMIT(sLimit); + if(hLimit == hwLimit) + { + *swLimit = GT_1M; + return GT_OK; + } + + if(hLimit > hwLimit) + { + startLimit = 2000; + endLimit = 256000; + *swLimit = GT_2M; + } + else + { + startLimit = 128; + endLimit = 512; + *swLimit = GT_128K; + } + + i = 0; + for(sLimit=startLimit;sLimit<=endLimit;sLimit *= 2, i++) + { + if (IS_IN_DEV_GROUP(dev,DEV_ENHANCED_FE_SWITCH)) + hLimit = GT_GET_RATE_LIMIT3(sLimit); + else if (!IS_IN_DEV_GROUP(dev,DEV_88E6183_FAMILY)) + hLimit = GT_GET_RATE_LIMIT2(sLimit); + else + hLimit = GT_GET_RATE_LIMIT(sLimit); + + if(hLimit == 0) + hLimit = 1; + + if(hLimit == hwLimit) + { + *swLimit += i; + return GT_OK; + } + + if(hLimit < hwLimit) + break; + } + + *swLimit = hwLimit; + return GT_OK; +} + + +/* + Convert given sw defined Burst Rate to meaningful number. +*/ +static GT_STATUS cBurstEnum2Number(GT_QD_DEV *dev, GT_BURST_RATE rate, GT_U32 *rLimit) +{ + GT_U32 rateLimit; + + GT_UNUSED_PARAM(dev); + + switch(rate) + { + case GT_BURST_NO_LIMIT : + rateLimit = 0; /* MAX_RATE_LIMIT; */ + break; + case GT_BURST_64K : + rateLimit = 64; + break; + case GT_BURST_128K : + rateLimit = 128; + break; + case GT_BURST_256K : + rateLimit = 256; + break; + case GT_BURST_384K : + rateLimit = 384; + break; + case GT_BURST_512K : + rateLimit = 512; + break; + case GT_BURST_640K : + rateLimit = 640; + break; + case GT_BURST_768K : + rateLimit = 768; + break; + case GT_BURST_896K : + rateLimit = 896; + break; + case GT_BURST_1M : + rateLimit = 1000; + break; + case GT_BURST_1500K : + rateLimit = 1500; + break; + case GT_BURST_2M : + rateLimit = 2000; + break; + case GT_BURST_4M : + rateLimit = 4000; + break; + case GT_BURST_8M : + rateLimit = 8000; + break; + case GT_BURST_16M : + rateLimit = 16000; + break; + case GT_BURST_32M : + rateLimit = 32000; + break; + case GT_BURST_64M : + rateLimit = 64000; + break; + case GT_BURST_128M : + rateLimit = 128000; + break; + case GT_BURST_256M : + rateLimit = 256000; + break; + default : + return GT_BAD_PARAM; + } + + *rLimit = rateLimit; + return GT_OK; +} + + +/* + Convert given hw Burst Rate Limit to sw defined Burst Rate Limit. +*/ +static GT_STATUS cBurstRateLimit(GT_QD_DEV *dev, GT_U32 burstSize, GT_U32 hwLimit, GT_BURST_RATE* swLimit) +{ + GT_BURST_RATE sLimit, startLimit, endLimit; + GT_U32 rLimit, tmpLimit; + GT_STATUS retVal; /* Functions return value. */ + + if(hwLimit == 0) + { + *swLimit = GT_BURST_NO_LIMIT; + return GT_OK; + } + + startLimit = GT_BURST_64K; + endLimit = GT_BURST_256M; + + for(sLimit=startLimit;sLimit<=endLimit;sLimit++) + { + if((retVal = cBurstEnum2Number(dev, sLimit, &rLimit)) != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + tmpLimit = GT_GET_BURST_RATE_LIMIT(burstSize,rLimit); + + if(hwLimit == tmpLimit) + { + *swLimit = sLimit; + return GT_OK; + } + } + + return GT_FAIL; +} + + +/* + Convert given sw defined Burst Rate to meaningful number. +*/ +static GT_STATUS cTCPBurstRate(GT_QD_DEV *dev, GT_BURST_RATE rate, GT_U32 *data) +{ + GT_UNUSED_PARAM(dev); + + switch(rate) + { + case GT_BURST_NO_LIMIT : + *data = 0; /* MAX_RATE_LIMIT; */ + break; + case GT_BURST_64K : + *data = 0x1D00; + break; + case GT_BURST_128K : + *data = 0x3FFF; + break; + case GT_BURST_256K : + *data = 0x7FFF; + break; + case GT_BURST_384K : + *data = 0x7DE0; + break; + case GT_BURST_512K : + *data = 0x76F0; + break; + case GT_BURST_640K : + *data = 0x7660; + break; + case GT_BURST_768K : + *data = 0x7600; + break; + case GT_BURST_896K : + *data = 0x74EF; + break; + case GT_BURST_1M : + *data = 0x7340; + break; + case GT_BURST_1500K : + *data = 0x7300; + break; + default : + return GT_BAD_PARAM; + } + + return GT_OK; +} + +static GT_STATUS setEnhancedERate(GT_QD_DEV *dev, GT_LPORT port, GT_ERATE_TYPE *rateType) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; + GT_U32 rate, eDec; + GT_PIRL_ELIMIT_MODE mode; + GT_U8 phyPort; /* Physical port. */ + + phyPort = GT_LPORT_2_PORT(port); + + if((retVal = grcGetELimitMode(dev,port,&mode)) != GT_OK) + { + return retVal; + } + + if (mode == GT_PIRL_ELIMIT_FRAME) + { + /* Count Per Frame */ + rate = rateType->fRate; + + if (rate == 0) /* disable egress rate limit */ + { + eDec = 0; + data = 0; + } + else if((rate < 7600) || (rate > 1488000)) + { + return GT_BAD_PARAM; + } + else + { + eDec = 1; + data = (GT_U16)GT_GET_RATE_LIMIT_PER_FRAME(rate,eDec); + } + } + else + { + /* Count Per Byte */ + rate = rateType->kbRate; + + if(rate == 0) + { + eDec = 0; + } + else if(rate < 1000) /* less than 1Mbps */ + { + /* it should be divided by 64 */ + if(rate % 64) + return GT_BAD_PARAM; + eDec = rate/64; + } + else if(rate <= 100000) /* less than or equal to 100Mbps */ + { + /* it should be divided by 1000 */ + if(rate % 1000) + return GT_BAD_PARAM; + eDec = rate/1000; + } + else if(rate <= 1000000) /* less than or equal to 1000Mbps */ + { + /* it should be divided by 10000 */ + if(rate % 10000) + return GT_BAD_PARAM; + eDec = rate/10000; + } + else + return GT_BAD_PARAM; + + if(rate == 0) + { + data = 0; + } + else + { + data = (GT_U16)GT_GET_RATE_LIMIT_PER_BYTE(rate,eDec); + } + } + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_RATE_CTRL0,0,7,(GT_U16)eDec); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + retVal = hwSetPortRegField(dev,phyPort,QD_REG_EGRESS_RATE_CTRL,0,12,(GT_U16)data ); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +static GT_STATUS getEnhancedERate(GT_QD_DEV *dev, GT_LPORT port, GT_ERATE_TYPE *rateType) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 rate, eDec; + GT_PIRL_ELIMIT_MODE mode; + GT_U8 phyPort; /* Physical port. */ + + phyPort = GT_LPORT_2_PORT(port); + + if((retVal = grcGetELimitMode(dev,port,&mode)) != GT_OK) + { + return retVal; + } + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_RATE_CTRL0,0,7,&eDec); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + retVal = hwGetPortRegField(dev,phyPort,QD_REG_EGRESS_RATE_CTRL,0,12,&rate ); + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + if (mode == GT_PIRL_ELIMIT_FRAME) + { + rateType->fRate = GT_GET_RATE_LIMIT_PER_FRAME(rate,eDec); + } + else + { + /* Count Per Byte */ + rateType->kbRate = GT_GET_RATE_LIMIT_PER_BYTE(rate,eDec); + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* grcSetLimitMode +* +* DESCRIPTION: +* This routine sets the port's rate control ingress limit mode. +* +* INPUTS: +* port - logical port number. +* mode - rate control ingress limit mode. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_RATE_LIMIT_MODE mode +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcSetLimitMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_EGRESS_RATE_CTRL,14,2,(GT_U16)mode ); + } + else + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,14,2,(GT_U16)mode ); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* grcGetLimitMode +* +* DESCRIPTION: +* This routine gets the port's rate control ingress limit mode. +* +* INPUTS: +* port - logical port number. +* +* OUTPUTS: +* mode - rate control ingress limit mode. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetLimitMode +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_RATE_LIMIT_MODE *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcGetLimitMode Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_EGRESS_RATE_CTRL,14,2,&data ); + } + else + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,14,2,&data ); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + *mode = data; + DBG_INFO(("OK.\n")); + return GT_OK; +} + +/******************************************************************************* +* grcSetPri3Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 3 frames. +* Priority 3 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 3 frame rate limit mode +* GT_FALSE: use the same rate as Pri2Rate +* GT_TRUE: use twice the rate as Pri2Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetPri3Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcSetPri3Rate Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + BOOL_2_BIT(mode,data); + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,14,1,data ); + } + else + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,13,1,data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* grcGetPri3Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 3 frames. +* Priority 3 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 3 frame rate limit mode +* GT_FALSE: use the same rate as Pri2Rate +* GT_TRUE: use twice the rate as Pri2Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetPri3Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcGetPri3Rate Called.\n")); + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,14,1,&data ); + } + else + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,13,1,&data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* grcSetPri2Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 2 frames. +* Priority 2 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 2 frame rate limit mode +* GT_FALSE: use the same rate as Pri1Rate +* GT_TRUE: use twice the rate as Pri1Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetPri2Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcSetPri2Rate Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + BOOL_2_BIT(mode,data); + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,13,1,data ); + } + else + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,12,1,data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* grcGetPri2Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 2 frames. +* Priority 2 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 2 frame rate limit mode +* GT_FALSE: use the same rate as Pri1Rate +* GT_TRUE: use twice the rate as Pri1Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetPri2Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcGetPri2Rate Called.\n")); + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,13,1,&data ); + } + else + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,12,1,&data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* grcSetPri1Rate +* +* DESCRIPTION: +* This routine sets the ingress data rate limit for priority 1 frames. +* Priority 1 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* mode - the priority 1 frame rate limit mode +* GT_FALSE: use the same rate as Pri0Rate +* GT_TRUE: use twice the rate as Pri0Rate +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetPri1Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_BOOL mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* Data to be set into the */ + /* register. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcSetPri1Rate Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + BOOL_2_BIT(mode,data); + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,12,1,data ); + } + else + { + retVal = hwSetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,11,1,data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + DBG_INFO(("OK.\n")); + return GT_OK; +} + + + +/******************************************************************************* +* grcGetPri1Rate +* +* DESCRIPTION: +* This routine gets the ingress data rate limit for priority 1 frames. +* Priority 1 frames will be discarded after the ingress rate selection +* is reached or exceeded. +* +* INPUTS: +* port - the logical port number. +* +* OUTPUTS: +* mode - the priority 1 frame rate limit mode +* GT_FALSE: use the same rate as Pri0Rate +* GT_TRUE: use twice the rate as Pri0Rate +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcGetPri1Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + OUT GT_BOOL *mode +) +{ + GT_STATUS retVal; /* Functions return value. */ + GT_U16 data; /* The register's read data. */ + GT_U8 phyPort; /* Physical port. */ + + DBG_INFO(("grcGetPri1Rate Called.\n")); + if(mode == NULL) + { + DBG_INFO(("Failed.\n")); + return GT_BAD_PARAM; + } + + phyPort = GT_LPORT_2_PORT(port); + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_INGRESS_RATE_CTRL,12,1,&data ); + } + else + { + retVal = hwGetPortRegField(dev,phyPort,QD_REG_RATE_CTRL,11,1,&data); + } + if(retVal != GT_OK) + { + DBG_INFO(("Failed.\n")); + return retVal; + } + + BIT_2_BOOL(data,*mode); + DBG_INFO(("OK.\n")); + return GT_OK; +} + + +/******************************************************************************* +* grcSetPri0Rate +* +* DESCRIPTION: +* This routine sets the port's ingress data limit for priority 0 frames. +* +* INPUTS: +* port - logical port number. +* rate - ingress data rate limit for priority 0 frames. These frames +* will be discarded after the ingress rate selected is reached +* or exceeded. +* +* OUTPUTS: +* None. +* +* RETURNS: +* GT_OK - on success +* GT_FAIL - on error +* GT_BAD_PARAM - on bad parameters +* +* COMMENTS: +* GT_16M, GT_32M, GT_64M, GT_128M, and GT_256M in GT_PRI0_RATE enum +* are supported only by Gigabit Ethernet Switch. +* +* GalTis: +* +*******************************************************************************/ +GT_STATUS grcSetPri0Rate +( + IN GT_QD_DEV *dev, + IN GT_LPORT port, + IN GT_PRI0_RATE rate +) +{ + + GT_STATUS retVal; /* Functions return value. */ + GT_U8 phyPort; /* Physical port. */ + GT_U32 rateLimit, tmpLimit; + + DBG_INFO(("grcSetPri0Rate Called.\n")); + + phyPort = GT_LPORT_2_PORT(port); + + /* check if device supports this feature */ + if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_INGRESS_RATE_KBPS|DEV_UNMANAGED_SWITCH)) != GT_OK ) + return retVal; + + if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_MANAGED_SWITCH)) + { + dev->devStorage &= ~(GT_RATE_ENUM_NOT_USED); + switch(rate) + { + case GT_NO_LIMIT : + rateLimit = 0; /* MAX_RATE_LIMIT; */ + break; + case GT_128K : + rateLimit = 128; + break; + case GT_256K : + rateLimit = 256; + break; + case GT_512K : + rateLimit = 512; + break; + case GT_1M : + rateLimit = 1000; + break; + case GT_2M : + rateLimit = 2000; + break;