diff -Naur u-boot-2009.08.orig/board/freescale/m5253demo/m5253demo.c u-boot-2009.08/board/freescale/m5253demo/m5253demo.c
--- u-boot-2009.08.orig/board/freescale/m5253demo/m5253demo.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/board/freescale/m5253demo/m5253demo.c	2010-08-17 11:04:37.187699433 -0400
@@ -37,14 +37,14 @@
 
 phys_size_t initdram(int board_type)
 {
-	u32 dramsize = 0;
+	volatile u32 dramsize = 0;
 
 	/*
 	 * Check to see if the SDRAM has already been initialized
 	 * by a run control tool
 	 */
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
-		u32 RC, temp;
+		volatile u32 RC, temp;
 
 		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
@@ -82,7 +82,8 @@
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		__asm__("nop");
 
-		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		*(volatile u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		__asm__("nop");
 	}
 
 	return dramsize;
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/config.mk u-boot-2009.08/board/freescale/m54418twr/config.mk
--- u-boot-2009.08.orig/board/freescale/m54418twr/config.mk	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,25 @@
+# Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/m54418twr.c u-boot-2009.08/board/freescale/m54418twr/m54418twr.c
--- u-boot-2009.08.orig/board/freescale/m54418twr/m54418twr.c	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/m54418twr.c	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Freescale M54418 Tower System\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile pm_t *pm = (pm_t *) MMAP_PM;
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+
+	pm->pmcr0 = 0x2E;
+	gpio->mscr_sdram = 1;
+	ccm->misccr2 &= ~CCM_MISCCR2_FBHALF;
+	ccm->misccr2 |= CCM_MISCCR2_DDR2CLK;
+
+	sdram->rcrcr = 0x40000000;
+	sdram->padcr = 0x01030203;
+
+	sdram->cr00 = 0x01010101;
+	sdram->cr01 = 0x00000101;
+	sdram->cr02 = 0x01010100;
+	sdram->cr03 = 0x01010000;
+	sdram->cr04 = 0x00010101;
+	sdram->cr06 = 0x00010100;
+	sdram->cr07 = 0x00000001;
+	sdram->cr08 = 0x01000001;
+	sdram->cr09 = 0x00000100;
+	sdram->cr10 = 0x00010001;
+	sdram->cr11 = 0x00000200;
+	sdram->cr12 = 0x01000002;
+	sdram->cr13 = 0x00000000;
+	sdram->cr14 = 0x00000100;
+	sdram->cr15 = 0x02000100;
+	sdram->cr16 = 0x02000407;
+	sdram->cr17 = 0x02030007;
+	sdram->cr18 = 0x02000100;
+	sdram->cr19 = 0x0A030203;
+	sdram->cr20 = 0x00020708;
+	sdram->cr21 = 0x00050008;
+/*	sdram->cr22 = 0x04030002;*/
+	sdram->cr22 = 0x04020002;
+	sdram->cr23 = 0x00000004;
+	sdram->cr24 = 0x020A0000;
+	sdram->cr25 = 0x0C00000E;
+	sdram->cr26 = 0x00002004;
+	sdram->cr28 = 0x00100010;
+	sdram->cr29 = 0x00100010;
+	sdram->cr31 = 0x07990000;
+	sdram->cr40 = 0x00000000;
+	sdram->cr41 = 0x00C80064;
+	sdram->cr42 = 0x44520002;
+	sdram->cr43 = 0x00C80023;
+	sdram->cr45 = 0x0000C350;
+	sdram->cr56 = 0x04000000;
+/*	sdram->cr57 = 0x03000304; */
+	sdram->cr57 = 0x03000305;
+	sdram->cr58 = 0x40040000;
+	sdram->cr59 = 0xC0004004;
+	sdram->cr60 = 0x0642C000;
+	sdram->cr61 = 0x00000642;
+	asm("tpf");
+
+	sdram->cr09 = 0x01000100;
+
+/*	while ((sdram->cr27 & 0xC) != 8); */
+
+	udelay(100);
+#endif
+	return (dramsize);
+};
+#if 0
+u32 memTestDataBus(u32 adr)
+{
+	volatile u8 *address = (u8 *)adr;
+	u8 pattern;
+	u8 readback;
+
+	printf("\nRunning memTestDataBus test ...\n");
+
+	/* Perform a walking 1's test at the given address. */
+	for (pattern = 1; pattern != 0; pattern <<= 1)
+	{
+		/* Write the test pattern. */
+		*address = pattern;
+
+		/* Read it back (immediately is okay for this test). */
+		readback = *address;
+		if (readback != pattern)
+		{
+			printf("memTestDataBus pattern %02x @ 0x%08x - 0x%x\n",
+			       pattern, (u32)address, readback);
+		}
+	}
+
+	printf("End memTestDataBus test\n");
+
+	return (0);
+}
+
+u32 memTestAddressBus(u32 adr, u32 nBytes)
+{
+	volatile u8 *baseAddress = (u8 *)adr;
+	u32 addressMask = (nBytes - 1);
+	u32 offset;
+	u32 testOffset;
+
+	u8 pattern      = (u8) 0xAAAAAAAA;
+	u8 antipattern  = (u8) 0x55555555;
+	u8 readback8;
+
+	printf("\nRunning memTestAddressBus test ...\n");
+
+	/* Write the default pattern at each of the power-of-two offsets. */
+	for (offset = sizeof(u8); (offset & addressMask) != 0; offset <<= 1)
+		baseAddress[offset] = pattern;
+
+	/* Check for address bits stuck high. */
+	testOffset = 0;
+	baseAddress[testOffset] = antipattern;
+	printf("Check for stuck high\n");
+
+	for (offset = sizeof(u8); (offset & addressMask) != 0; offset <<= 1)
+	{
+		readback8 = baseAddress[offset];
+		if (readback8 != pattern)
+		{
+			printf("memTestAddressBus high @ addr:0x%08lx data:0x%02x pattern %0x02x\n",
+			     (u32)(baseAddress+offset), readback8, pattern);
+		}
+	}
+
+	baseAddress[testOffset] = pattern;
+	printf("Check for stuck low\n");
+
+	/* Check for address bits stuck low or shorted. */
+	for (testOffset = sizeof(u8); (testOffset & addressMask) != 0; testOffset <<= 1)
+	{
+		baseAddress[testOffset] = antipattern;
+
+		for (offset = sizeof(u8); (offset & addressMask) != 0; offset <<= 1)
+		{
+			readback8 = baseAddress[offset];
+
+			if ((readback8 != pattern) && (offset != testOffset))
+			{
+				printf("memTestAddressBus low @ addr:0x%08lx data:0x%02x pattern 0x%02x\n",
+				       (u32)(baseAddress+offset), readback8, pattern);
+			}
+		}
+
+		baseAddress[testOffset] = pattern;
+	}
+
+	printf("End memTestAddressBus test\n");
+
+	return (0);
+}
+#endif
+
+int testdram(void)
+{
+#if 0
+	memTestDataBus(CONFIG_SYS_MEMTEST_START);
+	memTestAddressBus(CONFIG_SYS_MEMTEST_START, 0x2000);
+#endif
+	return (0);
+}
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/Makefile u-boot-2009.08/board/freescale/m54418twr/Makefile
--- u-boot-2009.08.orig/board/freescale/m54418twr/Makefile	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/Makefile	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,43 @@
+# Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.lds u-boot-2009.08/board/freescale/m54418twr/u-boot.lds
--- u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.lds	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/u-boot.lds	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf5445x/start.o	(.text)
+    cpu/mcf5445x/libmcf5445x.a	(.text)
+    board/freescale/m54418twr/libm54418twr.a	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.nor u-boot-2009.08/board/freescale/m54418twr/u-boot.nor
--- u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.nor	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/u-boot.nor	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf5445x/start.o	(.text)
+    cpu/mcf5445x/libmcf5445x.a	(.text)
+    board/freescale/m54418twr/libm54418twr.a	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff -Naur u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.ser u-boot-2009.08/board/freescale/m54418twr/u-boot.ser
--- u-boot-2009.08.orig/board/freescale/m54418twr/u-boot.ser	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/board/freescale/m54418twr/u-boot.ser	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf5445x/start.o		(.text)
+    cpu/mcf5445x/libmcf5445x.a	(.text)
+
+/*
+    lib_m68k/board.o			(.text)
+    common/serial.o			(.text)
+    common/console.o			(.text)
+    lib_generic/display_options.o	(.text)
+    board/freescale/m54455evb/m54455evb.o	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+*/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff -Naur u-boot-2009.08.orig/board/freescale/m54455evb/m54455evb.c u-boot-2009.08/board/freescale/m54455evb/m54455evb.c
--- u-boot-2009.08.orig/board/freescale/m54455evb/m54455evb.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/board/freescale/m54455evb/m54455evb.c	2010-08-17 11:04:37.197702095 -0400
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -206,12 +207,14 @@
 
 	info->size              = 0;
 	info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
-	info->start[0] = base;
+	info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
 	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
 		info->size += sect[i] * sectsz[i];
 
 		for (j = 0; j < sect[i]; j++, k++) {
-			info->start[k + 1] = info->start[k] + sectsz[i];
+			info->start[k + 1] = (ulong)
+				map_physmem(info->start[k] + sectsz[i],
+						info->portwidth, MAP_NOCACHE);
 			info->protect[k] = 0;
 		}
 	}
diff -Naur u-boot-2009.08.orig/common/cmd_nvedit.c u-boot-2009.08/common/cmd_nvedit.c
--- u-boot-2009.08.orig/common/cmd_nvedit.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/common/cmd_nvedit.c	2010-08-17 11:04:37.197702095 -0400
@@ -60,9 +60,10 @@
     !defined(CONFIG_ENV_IS_IN_NVRAM)	&& \
     !defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
     !defined(CONFIG_ENV_IS_IN_SPI_FLASH)	&& \
-    !defined(CONFIG_ENV_IS_NOWHERE)
+    !defined(CONFIG_ENV_IS_NOWHERE)	&& \
+    !defined(CONFIG_ENV_IS_IN_MRAM)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|NOWHERE}
+SPI_FLASH|MG_DISK|NVRAM|NOWHERE|MRAM}
 #endif
 
 #define XMK_STR(x)	#x
diff -Naur u-boot-2009.08.orig/common/env_mram.c u-boot-2009.08/common/env_mram.c
--- u-boot-2009.08.orig/common/env_mram.c	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/common/env_mram.c	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved
+ * Jason Jin <Jason.jin@freescale.com>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* references to names in env_common.c */
+extern uchar default_environment[];
+char *env_name_spec = "MRAM";
+env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+
+uchar env_get_char_spec(int index)
+{
+	return ( *((uchar *)(gd->env_addr + index)) );
+}
+
+void env_relocate_spec(void)
+{
+	memcpy (env_ptr, (char*)CONFIG_ENV_ADDR , CONFIG_ENV_SIZE);
+}
+
+
+int saveenv(void)
+{
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	/*Protect off mram*/
+	fbcs->csmr0 &= ~0x100;
+
+	if (memcpy ((char*)CONFIG_ENV_ADDR, env_ptr, CONFIG_ENV_SIZE) == NULL)
+		return 1;
+
+	/*Protect on mram*/
+	fbcs->csmr0 |= 0x100;
+
+	return 0;
+}
+
+
+ /* Initialize Environment use */
+int  env_init(void)
+{
+	ulong crc = *(ulong *) CONFIG_ENV_ADDR;
+
+	if (crc32(0, env_ptr->data, ENV_SIZE) == crc) {
+		gd->env_addr  = (ulong)CONFIG_ENV_ADDR + sizeof(ulong);
+		gd->env_valid = 1;
+	} else {
+		gd->env_addr  = (ulong)&default_environment[0];
+		gd->env_valid = 0;
+	}
+
+	return (0);
+}
+
+int do_protect_mram(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	if (argc < 2) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if (strcmp(argv[1], "off") == 0) {
+		fbcs->csmr0 &= ~0x100;
+	} else if (strcmp(argv[1], "on") == 0) {
+		fbcs->csmr0 |= 0x100;
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+}
+
+U_BOOT_CMD(
+	protect,  3,  0,   do_protect_mram,
+	"enable or disable MRAM write protection",
+	"on mram\n    - protect all the mram space\n"
+	"protect off mram\n    - make all the mram writable\n"
+);
diff -Naur u-boot-2009.08.orig/common/Makefile u-boot-2009.08/common/Makefile
--- u-boot-2009.08.orig/common/Makefile	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/common/Makefile	2010-08-17 11:04:37.197702095 -0400
@@ -62,6 +62,7 @@
 COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
 COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+COBJS-$(CONFIG_ENV_IS_IN_MRAM) += env_mram.o
 
 # command
 COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
diff -Naur u-boot-2009.08.orig/cpu/mcf5227x/config.mk u-boot-2009.08/cpu/mcf5227x/config.mk
--- u-boot-2009.08.orig/cpu/mcf5227x/config.mk	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5227x/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+ifneq ($(findstring 4.1.,$(shell $(CC) --version)),4.1.)
 PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
diff -Naur u-boot-2009.08.orig/cpu/mcf52x2/config.mk u-boot-2009.08/cpu/mcf52x2/config.mk
--- u-boot-2009.08.orig/cpu/mcf52x2/config.mk	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf52x2/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -35,7 +35,7 @@
 is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+ifneq ($(findstring 4.1.,$(shell $(CC) --version)),4.1.)
 
 ifneq (,$(findstring CONFIG_M5208,$(is5208)))
 PLATFORM_CPPFLAGS += -mcpu=5208
diff -Naur u-boot-2009.08.orig/cpu/mcf532x/config.mk u-boot-2009.08/cpu/mcf532x/config.mk
--- u-boot-2009.08.orig/cpu/mcf532x/config.mk	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf532x/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -24,8 +24,18 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is53015:=$(shell grep CONFIG_M53015 $(TOPDIR)/include/$(cfg))
+
+ifneq ($(findstring 4.1.,$(shell $(CC) --version)),4.1.)
+
+ifneq (,$(findstring CONFIG_M53015,$(is53015)))
+PLATFORM_CPPFLAGS += -mcpu=53017 -fPIC
+else
 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
+endif
+
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
 endif
diff -Naur u-boot-2009.08.orig/cpu/mcf532x/start.S u-boot-2009.08/cpu/mcf532x/start.S
--- u-boot-2009.08.orig/cpu/mcf532x/start.S	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf532x/start.S	2010-08-17 11:04:37.197702095 -0400
@@ -280,7 +280,7 @@
 icache_enable:
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xfc000), %d0
 	movec	%d0, %ACR0			/* Enable cache */
 
 	move.l	#0x80000200, %d0		/* Setup cache mask */
diff -Naur u-boot-2009.08.orig/cpu/mcf5445x/config.mk u-boot-2009.08/cpu/mcf5445x/config.mk
--- u-boot-2009.08.orig/cpu/mcf5445x/config.mk	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5445x/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -24,8 +24,18 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+
+ifneq ($(findstring 4.1.,$(shell $(CC) --version)),4.1.)
+
+ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
+PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
+else
 PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+endif
+
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC
 endif
diff -Naur u-boot-2009.08.orig/cpu/mcf5445x/cpu.c u-boot-2009.08/cpu/mcf5445x/cpu.c
--- u-boot-2009.08.orig/cpu/mcf5445x/cpu.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5445x/cpu.c	2010-08-17 11:04:37.197702095 -0400
@@ -73,6 +73,21 @@
 	case 0x4f:
 		id = 54450;
 		break;
+	case 0x9F:
+		id = 54410;
+		break;
+	case 0xA0:
+		id = 54415;
+		break;
+	case 0xA1:
+		id = 54416;
+		break;
+	case 0xA2:
+		id = 54417;
+		break;
+	case 0xA3:
+		id = 54418;
+		break;
 	}
 
 	if (id) {
diff -Naur u-boot-2009.08.orig/cpu/mcf5445x/cpu_init.c u-boot-2009.08/cpu/mcf5445x/cpu_init.c
--- u-boot-2009.08.orig/cpu/mcf5445x/cpu_init.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5445x/cpu_init.c	2010-08-17 11:04:37.197702095 -0400
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,37 +36,11 @@
 #include <asm/fec.h>
 #endif
 
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-	scm1->pacrg = 0;
-
-	/* FlexBus */
-	gpio->par_be =
-	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
-	    GPIO_PAR_BE_BE0_BE0;
-	gpio->par_fbctl =
-	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
-	    GPIO_PAR_FBCTL_TS_TS;
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
 	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
@@ -75,7 +49,6 @@
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
-	/* Latch chipselect */
 	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
 	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
 	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
@@ -104,11 +77,94 @@
 	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+	volatile scm_t *scm = (scm_t *) MMAP_SCM;
+	volatile pm_t *pm = (pm_t *) MMAP_PM;
+
+	/* Disable core watchdog */
+	scm->cwcr = 0;
+	gpio->par_fbctl =
+	    GPIO_PAR_FBCTL_ALE_FB_TS | GPIO_PAR_FBCTL_OE_FB_OE |
+	    GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+            GPIO_PAR_FBCTL_TA_TA;
+	gpio->par_be =
+	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
+	    GPIO_PAR_BE_BE0_BE0;
+
+
+	pm->pmcr0 = 17;	/* eDMA */
+
+	pm->pmcr0 = 18;	/* INTR0 */
+	pm->pmcr0 = 19;	/* INTR1 */
+	pm->pmcr0 = 20;	/* INTR2 */
+
+	pm->pmcr0 = 22;	/* I2C0 */
+
+	pm->pmcr0 = 28;	/* DTMR0 */
+	pm->pmcr0 = 29;	/* DTMR1 */
+	pm->pmcr0 = 30;	/* DTMR2 */
+	pm->pmcr0 = 31;	/* DTMR3 */
+
+	pm->pmcr0 = 32;	/* PIT0 */
+	pm->pmcr0 = 33;	/* PIT1 */
+	pm->pmcr0 = 34;	/* PIT2 */
+	pm->pmcr0 = 35;	/* PIT3 */
+
+	pm->pmcr0 = 36;	/* Edge Port */
+	pm->pmcr0 = 37;	/* Edge Port */
+
+	pm->pmcr0 = 44;	/* USB OTG */
+	pm->pmcr0 = 45;	/* USB Host */
+
+	pm->pmcr0 = 51;	/* esdhc */
+	pm->pmcr0 = 53;	/* enet 0 */
+	pm->pmcr0 = 54;	/* enet 1 */
+//	pm->pmcr0 = 63;	/* nand */
+
+#endif		/* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+	scm1->pacrg = 0;
+
+	/* FlexBus */
+	gpio->par_be =
+	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
+	    GPIO_PAR_BE_BE0_BE0;
+	gpio->par_fbctl =
+	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
+	    GPIO_PAR_FBCTL_TS_TS;
 
 #ifdef CONFIG_FSL_I2C
 	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
 #endif
+#endif		/* CONFIG_MCF5445x */
 
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	icache_enable();
 	icache_enable();
 }
 
@@ -124,16 +180,94 @@
 	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
 	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
 #endif
-
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+	volatile pm_t *pm = (pm_t *) MMAP_PM;
+#endif
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
+#ifdef CONFIG_MCF5441x
+	case 0:
+		pm->pmcr0 = 24;	/* UART0 */
+		gpio->par_uart0 &=
+		    (GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK);
+		gpio->par_uart0 |=
+		    (GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+		break;
+	case 1:
+		pm->pmcr0 = 25;	/* UART1 */
+		gpio->par_uart1 &=
+		    (GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK);
+		gpio->par_uart1 |=
+		    (GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+		break;
+	case 2:
+		pm->pmcr0 = 26;	/* UART2 */
+		gpio->par_uart2 &=
+		    (GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK);
+		gpio->par_uart2 |=
+		    (GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+		break;
+	case 3:
+		pm->pmcr0 = 27;	/* UART3 */
+		gpio->par_dspi0 &=
+		    (GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK);
+		gpio->par_dspi0 |=
+		    (GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+		break;
+	case 4:
+		pm->pmcr1 = 24; /* UART4 */
+		gpio->par_uart0 &=
+		    (GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK);
+		gpio->par_uart0 |=
+		    (GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+		break;
+	case 5:
+		pm->pmcr1 = 25; /* UART5 */
+		gpio->par_uart1 &=
+		    (GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK);
+		gpio->par_uart1 |=
+		    (GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+		break;
+	case 6:
+		pm->pmcr1 = 26; /* UART6 */
+		gpio->par_uart2 &=
+		    (GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK);
+		gpio->par_uart2 |=
+		    (GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+		break;
+	case 7:
+		pm->pmcr1 = 27; /* UART7 */
+		gpio->par_ssi0h &= (GPIO_PAR_SSI0H_RXD_MASK);
+		gpio->par_ssi0l &= (GPIO_PAR_SSI0L_BCLK_MASK);
+		gpio->par_ssi0h |= (GPIO_PAR_SSI0H_FS_U7TXD);
+		gpio->par_ssi0l |= (GPIO_PAR_SSI0L_BCLK_U7RXD);
+		break;
+	case 8:
+		pm->pmcr1 = 28; /* UART8 */
+		gpio->par_cani2c &=
+		    (GPIO_PAR_CANI2C_I2C0SCL_MASK |
+		     GPIO_PAR_CANI2C_I2C0SDA_MASK);
+		gpio->par_cani2c |=
+		    (GPIO_PAR_CANI2C_I2C0SCL_U8TXD |
+		     GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+		break;
+	case 9:
+		pm->pmcr1 = 29; /* UART9 */
+		gpio->par_cani2c &=
+		    (GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK);
+		gpio->par_cani2c |=
+		    (GPIO_PAR_CANI2C_CAN1TX_U9TXD |
+		     GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+		break;
+#endif
+#ifdef CONFIG_MCF5445x
 	case 0:
 		gpio->par_uart =
 		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@@ -142,6 +276,7 @@
 		gpio->par_uart =
 		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 		break;
+#endif
 	}
 }
 
@@ -151,6 +286,24 @@
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
+#ifdef CONFIG_MCF5441x
+	if (setclear) {
+		gpio->par_fec = 0x03;
+		gpio->srcr_fec = 0x0F;
+		gpio->par_simp0h = ( gpio->par_simp0h &
+			GPIO_PAR_SIMP0H_DAT_MASK) |
+			GPIO_PAR_SIMP0H_DAT_GPIO;
+		gpio->pddr_g = 	( gpio->pddr_g &
+			GPIO_PDDR_G4_MASK) |
+			GPIO_PDDR_G4_OUTPUT;
+		gpio->podr_g &= GPIO_PODR_G4_MASK;
+
+	} else {
+		gpio->par_fec &= GPIO_PAR_FEC_FEC_MASK;
+	}
+#endif
+
+#ifdef CONFIG_MCF5445x
 	if (setclear) {
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
@@ -168,6 +321,7 @@
 		else
 			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
 	}
+#endif
 	return 0;
 }
 #endif
@@ -177,8 +331,19 @@
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
+#ifdef CONFIG_MCF5441x
+	volatile pm_t *pm = (pm_t *) MMAP_PM;
+
+	gpio->par_dspi0 = GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+	    GPIO_PAR_DSPI0_SCK_DSPI0SCK;
+	gpio->srcr_dspiow = 3;
+
+	pm->pmcr0 = 23;	/* DSPI0 */
+#endif
+#ifdef CONFIG_MCF5445x
 	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
 	    GPIO_PAR_DSPI_SCK_SCK;
+#endif
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
@@ -192,6 +357,20 @@
 	/* Clear FIFO and resume transfer */
 	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
+#ifdef CONFIG_MCF5441x
+	switch (cs) {
+	case 0:
+		gpio->par_dspi0 &= GPIO_PAR_DSPI0_PCS0_MASK;
+		gpio->par_dspi0 |= GPIO_PAR_DSPI0_PCS0_DSPI0PCS0;
+		break;
+	case 1:
+		gpio->par_dspiow &= ~GPIO_PAR_DSPIOW_DSPI0PSC1;
+		gpio->par_dspiow |= GPIO_PAR_DSPIOW_DSPI0PSC1;
+		break;
+	}
+#endif
+
+#ifdef CONFIG_MCF5445x
 	switch (cs) {
 	case 0:
 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
@@ -210,7 +389,7 @@
 		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
 		break;
 	}
-
+#endif
 	return 0;
 }
 
@@ -221,6 +400,18 @@
 
 	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
 
+#ifdef CONFIG_MCF5441x
+	switch (cs) {
+	case 0:
+/*		gpio->par_dspi0 &= GPIO_PAR_DSPI0_PCS0_MASK;*/
+		break;
+	case 1:
+		gpio->par_dspiow &= ~GPIO_PAR_DSPIOW_DSPI0PSC1;
+		break;
+	}
+#endif
+
+#ifdef CONFIG_MCF5445x
 	switch (cs) {
 	case 0:
 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
@@ -235,5 +426,6 @@
 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
 		break;
 	}
+#endif
 }
 #endif
diff -Naur u-boot-2009.08.orig/cpu/mcf5445x/speed.c u-boot-2009.08/cpu/mcf5445x/speed.c
--- u-boot-2009.08.orig/cpu/mcf5445x/speed.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5445x/speed.c	2010-08-17 11:04:37.197702095 -0400
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -56,8 +56,14 @@
 	/* Round divider down to nearest power of two */
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
+#ifdef CONFIG_MCF5445x
+	/* Apply the divider to the system clock */
+	/*ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);*/
+#endif
+#ifdef CONFIG_MCF5445x
 	/* Apply the divider to the system clock */
 	ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+#endif
 
 	/* Enable Limp Mode */
 	ccm->misccr |= CCM_MISCCR_LIMP;
@@ -79,12 +85,48 @@
 	while (!(pll->psr & PLL_PSR_LOCK)) ;
 }
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
 {
+	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	int temp, vco = 0, bootmod_ccr, pdr;
+
+	bootmod_ccr = (ccm->ccr & CCM_CCR_BOOTMOD) >> 14;
+
+	switch (bootmod_ccr) {
+	case 0:
+		pll->pcr = 0x00000013;
+		pll->pdr = 0x00e70c61;
+		clock_exit_limp();
+		break;
+	case 2:
+		break;
+	case 3:
+		break;
+	}
+
+	vco =  ((pll->pcr & PLL_CR_FBKDIV_BITS) + 1) * CONFIG_SYS_INPUT_CLKSRC;
+	gd->vco_clk = vco;
+
+	gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
+
+	pdr = pll->pdr;
+	temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+	gd->cpu_clk = vco / temp;	/* cpu clock */
+
+	temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+	gd->bus_clk = vco / temp;	/* bus clock */
 
+	gd->flb_clk = vco / temp;	/* FlexBus clock */
+	gd->flb_clk >>= 1;
+
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
 	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
 	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
 	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
@@ -208,10 +250,23 @@
 		}
 #endif
 	}
+}
+#endif
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+	setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+	setup_5445x_clocks();
+#endif
 
 #ifdef CONFIG_FSL_I2C
 	gd->i2c1_clk = gd->bus_clk;
 #endif
-
 	return (0);
 }
diff -Naur u-boot-2009.08.orig/cpu/mcf5445x/start.S u-boot-2009.08/cpu/mcf5445x/start.S
--- u-boot-2009.08.orig/cpu/mcf5445x/start.S	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf5445x/start.S	2010-08-17 11:04:37.197702095 -0400
@@ -2,6 +2,9 @@
  * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
  * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
  *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.  All Rights Reserved
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -21,6 +24,7 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
@@ -47,8 +51,9 @@
 	addl	#60,%sp;		/* space for 15 regs */ \
 	rte;
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 #define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N	(asm_dram_init - TEXT_BASE)
 #define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
@@ -59,10 +64,15 @@
  *	These vectors are to catch any un-intended traps.
  */
 _vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 
 INITSP:	.long	0		/* Initial SP	*/
+#ifdef CONFIG_CF_SBF
 INITPC:	.long	ASM_DRAMINIT	/* Initial PC 	*/
+#endif
+#ifdef CONFIG_NAND_BOOT
+INITPC:	.long	ASM_DRAMINIT_N	/* Initial PC 	*/
+#endif
 
 #else
 
@@ -99,7 +109,7 @@
 vector1E:	.long	_FAULT	/* Autovector Level 6	*/
 vector1F:	.long	_FAULT	/* Autovector Level 7	*/
 
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -142,7 +152,7 @@
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 #endif
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 asm_sbf_img_hdr:
 	.long	0x00000000	/* checksum, not yet implemented */
@@ -152,6 +162,16 @@
 asm_dram_init:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
+#ifdef CONFIG_NAND_BOOT
+	/* for assembly stack */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
 	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
 	movec	%d0, %VBR
 
@@ -186,7 +206,89 @@
 	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
 	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+#endif			/* CONFIG_CF_SBF */
 
+#ifdef CONFIG_MCF5441x
+	/* TC: enable all peripherals, in the future only enable certain peripherals */
+	move.l	#0xFC04002D, %a1
+
+#if defined(CONFIG_CF_SBF)
+	move.b	#23, (%a1)	/* dspi */
+#endif
+	move.b	#46, (%a1)	/* DDR */
+
+	/* slew settings */
+	move.l	#0xEC094060, %a1
+	move.b	#1, (%a1)
+
+	/* use vco instead of cpu*2 clock for ddr clock */
+	move.l	#0xEC09001A, %a1
+	move.w	#0xE01D, (%a1)
+
+	/* DDR settings */
+	move.l	#0xFC0B8180, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	move.l	#0xFC0B81AC, %a1
+	move.l	#0x01030203, (%a1)
+
+	move.l	#0xFC0B8000, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#0xFC0B8018, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#0xFC0B80A0, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#0xFC0B80B4, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#0xFC0B80E0, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#0xFC0B8024, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	jsr	asm_delay
+#endif		/* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
 	/* Dram Initialization a1, a2, and d0 */
 	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
@@ -209,6 +311,7 @@
 	add.l	#1, %d1
 	cmp.l	#1, %d2
 	bne	dramsz_loop
+	beq	asm_nand_chk_status
 
 	/* SDRAM Chip 0 and 1 */
 	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
@@ -281,7 +384,9 @@
 
 	move.l	#2000, %d1
 	jsr	asm_delay
+#endif			/* CONFIG_MCF5445x */
 
+#ifdef CONFIG_CF_SBF
 	/*
 	 * DSPI Initialization
 	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -292,15 +397,28 @@
 	 */
 	/* Enable pins for DSPI mode - chip-selects are enabled later */
 asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+	move.l	#0xEC09404E, %a1
+	move.l	#0xEC09404F, %a2
+	move.b	#0xFF, (%a1)
+	move.b	#0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
 	move.l	#0xFC0A4063, %a0
 	move.b	#0x7F, (%a0)
-
+#endif
 	/* Configure DSPI module */
 	move.l	#0xFC05C000, %a0
 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
 
 	move.l	#0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+	move.l	#0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
 	move.l	#0x3E000011, (%a0)
+#endif
 
 	move.l	#0xFC05C034, %a2	/* dtfr */
 	move.l	#0xFC05C03B, %a3	/* drfr */
@@ -380,24 +498,158 @@
 	move.l	(%a1), %d0		/* status */
 	and.l	#0x000000F0, %d0
 	lsr.l	#4, %d0
+
 	cmp.l	#0, %d0
 	beq	asm_dspi_rd_status
 
 	move.b	(%a3), %d1
 	rts
+#endif			/* CONFIG_CF_SBF */
+
+#ifdef CONFIG_NAND_BOOT
+	/* copy 4 boot pages to dram as soon as possible */
+	/* each page is 996 bytes (1056 total with 60 ECC bytes */
+	move.l  #0x00000000, %a1	/* src */
+	move.l	#TEXT_BASE, %a2		/* dst */
+	move.l	#0x3E0, %d0		/* sz in long */
+
+asm_boot_nand_copy:
+	move.l	(%a1)+, (%a2)+
+	subq.l	#1, %d0
+	bne	asm_boot_nand_copy
+
+	/* jump to memory and execute */
+	move.l	#(asm_nand_init), %a0
+	jmp	(%a0)
+
+asm_nand_init:
+	/* exit nand boot-mode */
+	move.l	#0xFC0FFF30, %a1
+	or.l	#0x00000040, %d1
+	move.l	%d1, (%a1)
+
+/*	move.l	#TEXT_BASE, %d0
+	movec	%d0, %VBR
+*/
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(CACR_STATUS), %a1	/* CACR */
+	move.l #(ICACHE_STATUS), %a2	/* icache */
+	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/* NAND port configuration */
+	move.l	#0xEC094048, %a1
+	move.b	#0xFD, (%a1)+
+	move.b	#0x5F, (%a1)+
+	move.b	#0x04, (%a1)+
+
+	/* reset nand */
+	move.l  #0xFC0FFF38, %a1	/* isr */
+	move.l  #0x000e0000, (%a1)
+	move.l	#0xFC0FFF08, %a2
+	move.l	#0x00000000, (%a2)+	/* car */
+	move.l	#0x11000000, (%a2)+	/* rar */
+	move.l	#0x00000000, (%a2)+	/* rpt */
+	move.l	#0x00000000, (%a2)+	/* rai */
+	move.l  #0xFC0FFF2c, %a2	/* cfg */
+	move.l  #0x00000000, (%a2)+	/* secsz */
+	move.l  #0x000e0681, (%a2)+
+	move.l  #0xFC0FFF04, %a2	/* cmd2 */
+	move.l  #0xFF404001, (%a2)
+	move.l  #0x000e0000, (%a1)
+
+	move.l	#0x2000, %d1
+	jsr	asm_delay
+
+	/* setup nand */
+	move.l  #0xFC0FFF00, %a1
+	move.l  #0x30700000, (%a1)+	/* cmd1 */
+	move.l  #0x007EF000, (%a1)+	/* cmd2 */
+
+	move.l  #0xFC0FFF2C, %a1
+	move.l  #0x0000083F, (%a1)+	/* secsz */
+	move.l  #0x000e0681, (%a1)+	/* cfg */
+
+	move.l	#76, %d4		/* 80 pages ~160KB */
+	move.l	#4, %d2			/* start at 4 */
+	move.l  #0xFC0FFF04, %a0	/* cmd2 */
+	move.l  #0xFC0FFF0C, %a1	/* rar */
+	move.l	#(TEXT_BASE + 0xF80), %a2	/* dst */
+
+asm_nand_read:
+	move.l	#0x11000000, %d0	/* rar */
+	or.l	%d2, %d0
+	move.l	%d0, (%a1)
+	add.l	#1, %d2
+
+	move.l	(%a0), %d0		/* cmd2 */
+	or.l	#1, %d0
+	move.l	%d0, (%a0)
+
+	move.l	#0x200, %d1
+	jsr	asm_delay
+
+asm_nand_chk_status:
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	and.l	#0x40000000, %d0
+	tst.l	%d0
+	beq	asm_nand_chk_status
+
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	or.l	#0x000E0000, %d0
+	move.l	%d0, (%a4)
+
+	move.l	#0x200, %d3
+	move.l	#0xFC0FC000, %a3	/* buf 1 */
+asm_nand_copy:
+	move.l	(%a3)+, (%a2)+
+	subq.l	#1, %d3
+	bgt	asm_nand_copy
+
+	subq.l	#1, %d4
+	bgt	asm_nand_read
+
+	/* jump to memory and execute */
+	move.l	#(TEXT_BASE + 0x400), %a0
+	jmp	(%a0)
+
+#endif			/* CONFIG_NAND_U_BOOT */
 
 asm_delay:
 	nop
 	subq.l	#1, %d1
 	bne	asm_delay
 	rts
-#endif			/* CONFIG_CF_SBF */
+
+#endif			/* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
 
 	.text
 	. = 0x400
 	.globl	_start
 _start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 	nop
 	nop
 	move.w #0x2700,%sr		/* Mask off Interrupt */
@@ -426,12 +678,15 @@
 	movec	%d0, %ACR1
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
+#else
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
-#endif
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
@@ -603,6 +858,15 @@
 
 	move.l	#0x01040100, %d0
 	movec	%d0, %CACR		/* Invalidate dcache */
+	clr.l   %d0
+	movec   %d0, %CACR
+
+	move.l	#0xF00FA048, %d0
+	movec	%d0, %ACR0
+	move.l	#0x400FA028, %d0
+/*	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xFA048), %d0*/	/* Setup icache */
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
 
 	move.l	#0x80088020, %d0	/* Enable bcache and icache */
 	movec	%d0, %CACR
diff -Naur u-boot-2009.08.orig/cpu/mcf547x_8x/config.mk u-boot-2009.08/cpu/mcf547x_8x/config.mk
--- u-boot-2009.08.orig/cpu/mcf547x_8x/config.mk	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/cpu/mcf547x_8x/config.mk	2010-08-17 11:04:37.197702095 -0400
@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+ifneq ($(findstring 4.1.,$(shell $(CC) --version)),4.1.)
 PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC
diff -Naur u-boot-2009.08.orig/drivers/mtd/nand/fsl_nfc.c u-boot-2009.08/drivers/mtd/nand/fsl_nfc.c
--- u-boot-2009.08.orig/drivers/mtd/nand/fsl_nfc.c	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/drivers/mtd/nand/fsl_nfc.c	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,844 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Shaohui Xie <b21989@freescale.com>
+ *	   Jason Jin <jason.jin@freescale.com>
+ *
+ * Description:
+ * MPC5125 Nand driver.
+ * Port to m54418twr board.
+ *
+ * Based on original driver mpc5121_nfc.c.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/compat.h>
+
+#include <mtd/fsl_nfc.h>
+
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+#define	DRV_NAME		"fsl_nfc"
+#define	DRV_VERSION		"0.5"
+
+/* Timeouts */
+#define NFC_RESET_TIMEOUT	1000		/* 1 ms */
+#define NFC_TIMEOUT		5000	/* 1/10 s */
+#define ECC_SRAM_ADDR	0x100
+#define ECC_STATUS_MASK	0x80
+#define ECC_ERR_COUNT	0x3F
+
+#define MIN(x, y)		((x < y) ? x : y)
+
+#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC
+static int hardware_ecc;
+#else
+static int hardware_ecc = 1;
+#endif
+
+struct fsl_nfc_prv {
+	struct mtd_info		mtd;
+	struct nand_chip	chip;
+	int			irq;
+	void __iomem		*regs;
+	struct clk		*clk;
+	uint			column;
+	int			spareonly;
+	u8			*testbuf;
+};
+
+int fsl_nfc_chip;
+
+static int get_status;
+static int get_id;
+
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	11,
+	.len = 4,
+	.veroffs = 15,
+	.maxblocks = 4,
+	.pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	11,
+	.len = 4,
+	.veroffs = 15,
+	.maxblocks = 4,
+	.pattern = mirror_pattern,
+};
+
+static struct nand_ecclayout nand_hw_eccoob_512 = {
+	.eccbytes = 8,
+	.eccpos = {
+		8, 9, 10, 11, 12, 13, 14, 15,
+	},
+	.oobfree = {
+		{0, 5} /* byte 5 is factory bad block marker */
+	},
+};
+
+static struct nand_ecclayout fsl_nfc_ecc45 = {
+	.eccbytes = 45,
+	.eccpos = {19, 20, 21, 22, 23,
+		   24, 25, 26, 27, 28, 29, 30, 31,
+		   32, 33, 34, 35, 36, 37, 38, 39,
+		   40, 41, 42, 43, 44, 45, 46, 47,
+		   48, 49, 50, 51, 52, 53, 54, 55,
+		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 8,
+		.length = 11} }
+};
+
+static struct nand_ecclayout fsl_nfc_ecc15 = {
+	.eccbytes = 15,
+	.eccpos = {49, 50, 51, 52, 53, 54, 55,
+		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 8,
+		.length = 41} }
+};
+
+static struct nand_ecclayout fsl_nfc_ecc23 = {
+	.eccbytes = 23,
+	.eccpos = {41, 42, 43, 44, 45, 46, 47,
+		   48, 49, 50, 51, 52, 53, 54, 55,
+		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 8,
+		.length = 33} }
+};
+
+
+static struct nand_ecclayout nand_hw_eccoob_2k = {
+	.eccbytes = 32,
+	.eccpos = {
+		/* 8 bytes of ecc for each 512 bytes of data */
+		8, 9, 10, 11, 12, 13, 14, 15,
+		24, 25, 26, 27, 28, 29, 30, 31,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		56, 57, 58, 59, 60, 61, 62, 63,
+	},
+	.oobfree = {
+		{2, 5}, /* bytes 0 and 1 are factory bad block markers */
+		{16, 7},
+		{32, 7},
+		{48, 7},
+	},
+};
+
+
+/* ecc struct for nand 5125 */
+static struct nand_ecclayout nand5125_hw_eccoob_2k = {
+	.eccbytes = 60,
+	.eccpos = {
+		/* 60 bytes of ecc for one page bytes of data */
+		4, 5,
+		6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+		16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+		26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
+		36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
+		46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+		56, 57, 58, 59, 60, 61, 62, 63,
+	},
+	.oobfree = {
+		{2, 2}, /* bytes 0 and 1 are factory bad block markers */
+	},
+};
+
+static inline u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+
+	return in_be32(prv->regs + reg);
+}
+
+/* Write NFC register */
+static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+
+	out_be32(prv->regs + reg, val);
+}
+
+/* Set bits in NFC register */
+static inline void nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
+}
+
+/* Clear bits in NFC register */
+static inline void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
+}
+
+static inline void
+nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+
+	out_be32(prv->regs + reg,
+			(in_be32(prv->regs + reg) & (~mask))
+			| val << shift);
+}
+
+static inline int
+nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+
+	return in_be32(prv->regs + reg) & field_mask;
+}
+
+static inline u8 nfc_check_status(struct mtd_info *mtd)
+{
+	u8 fls_status = 0;
+	fls_status = nfc_get_field(mtd, NFC_FLASH_STATUS2, STATUS_BYTE1_MASK);
+	return fls_status;
+}
+
+/* clear cmd_done and cmd_idle falg for the coming command */
+static void fsl_nfc_clear(struct mtd_info *mtd)
+{
+	nfc_write(mtd, NFC_IRQ_STATUS, 1 << CMD_DONE_CLEAR_SHIFT);
+	nfc_write(mtd, NFC_IRQ_STATUS, 1 << IDLE_CLEAR_SHIFT);
+}
+
+/* Wait for operation complete */
+static void fsl_nfc_done(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+	uint start = 0;
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK,
+			START_SHIFT, 1);
+
+	start = get_timer(0);
+
+	while (!nfc_get_field(mtd, NFC_IRQ_STATUS, CMD_DONE_IRQ_MASK)) {
+		if (get_timer(start) > NFC_TIMEOUT) {
+			printf("Timeout while waiting for BUSY.\n");
+		}
+	}
+	fsl_nfc_clear(mtd);
+}
+
+static u8 fsl_nfc_get_id(struct mtd_info *mtd, int col)
+{
+	u32 flash_id1 = 0;
+	u8 *pid;
+
+	flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1);
+	pid = (u8 *)&flash_id1;
+
+	return *(pid + col);
+}
+
+static inline u8 fsl_nfc_get_status(struct mtd_info *mtd)
+{
+	u32 flash_status = 0;
+	u8 *pstatus;
+
+	flash_status = nfc_read(mtd, NFC_FLASH_STATUS2);
+	pstatus = (u8 *)&flash_status;
+
+	return *(pstatus + 3);
+}
+
+/* Invoke command cycle */
+static inline void
+fsl_nfc_send_cmd(struct mtd_info *mtd, u32 cmd_byte1,
+		u32 cmd_byte2, u32 cmd_code)
+{
+	fsl_nfc_clear(mtd);
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+			CMD_BYTE1_SHIFT, cmd_byte1);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK,
+			CMD_BYTE2_SHIFT, cmd_byte2);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+			BUFNO_SHIFT, 0);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
+			CMD_CODE_SHIFT, cmd_code);
+
+	if (cmd_code == RANDOM_OUT_CMD_CODE)
+		nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+			BUFNO_SHIFT, 1);
+}
+
+/* Receive ID and status from NAND flash */
+static inline void
+fsl_nfc_send_one_byte(struct mtd_info *mtd, u32 cmd_byte1, u32 cmd_code)
+{
+	fsl_nfc_clear(mtd);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+			CMD_BYTE1_SHIFT, cmd_byte1);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+			BUFNO_SHIFT, 0);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
+			CMD_CODE_SHIFT, cmd_code);
+}
+
+
+/* Do address cycle(s) */
+static void
+fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
+{
+
+	if (column != -1) {
+		nfc_set_field(mtd, NFC_COL_ADDR,
+				COL_ADDR_MASK,
+				COL_ADDR_SHIFT, column);
+	}
+
+	if (page != -1) {
+		nfc_set_field(mtd, NFC_ROW_ADDR,
+				ROW_ADDR_MASK,
+				ROW_ADDR_SHIFT, page);
+	}
+
+	/* DMA Disable */
+	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
+
+	/* PAGE_CNT = 1 */
+	nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
+			CONFIG_PAGE_CNT_SHIFT, 0x1);
+}
+
+
+/* Control chips select signal on m54418twr board */
+static void
+m54418twr_select_chip(struct mtd_info *mtd, int chip)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (chip < 0) {
+		gpio->par_fbctl &= (GPIO_PAR_FBCTL_ALE_MASK &
+				   GPIO_PAR_FBCTL_TA_MASK);
+		gpio->par_fbctl |= GPIO_PAR_FBCTL_ALE_FB_TS |
+				   GPIO_PAR_FBCTL_TA_TA;
+		gpio->par_be =
+		    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		    GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0;
+		gpio->par_cs &= ~GPIO_PAR_CS_CS1_NFC_CE;
+		gpio->par_cs = GPIO_PAR_CS_CS0_CS0;
+		return;
+	}
+
+	gpio->par_fbctl &= (GPIO_PAR_FBCTL_ALE_MASK & GPIO_PAR_FBCTL_TA_MASK);
+	gpio->par_fbctl |= GPIO_PAR_FBCTL_ALE_FB_ALE |
+			   GPIO_PAR_FBCTL_TA_NFC_RB;
+	gpio->par_be =
+	    GPIO_PAR_BE_BE3_FB_A1 | GPIO_PAR_BE_BE2_FB_A0 |
+	    GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0;
+	gpio->par_cs &= (GPIO_PAR_BE_BE3_MASK & GPIO_PAR_BE_BE2_MASK);
+	gpio->par_cs = GPIO_PAR_CS_CS1_NFC_CE;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	fsl_nfc_chip = chip;
+}
+
+/* Read NAND Ready/Busy signal */
+static int
+fsl_nfc_dev_ready(struct mtd_info *mtd)
+{
+	/*
+	 * NFC handles ready/busy signal internally. Therefore, this function
+	 * always returns status as ready.
+	 */
+	return 1;
+}
+
+/* Write command to NAND flash */
+static void
+fsl_nfc_command(struct mtd_info *mtd, unsigned command,
+					int column, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+
+	prv->column = (column >= 0) ? column : 0;
+	prv->spareonly = 0;
+	get_id = 0;
+	get_status = 0;
+
+	switch (command) {
+	case NAND_CMD_PAGEPROG:
+		fsl_nfc_send_cmd(mtd,
+				PROGRAM_PAGE_CMD_BYTE1,
+				PROGRAM_PAGE_CMD_BYTE2,
+				PROGRAM_PAGE_CMD_CODE);
+		break;
+	/*
+	 * NFC does not support sub-page reads and writes,
+	 * so emulate them using full page transfers.
+	 */
+	case NAND_CMD_READ0:
+		column = 0;
+		goto read0;
+		break;
+
+	case NAND_CMD_READ1:
+		prv->column += 256;
+		command = NAND_CMD_READ0;
+		column = 0;
+		goto read0;
+		break;
+
+	case NAND_CMD_READOOB:
+		prv->spareonly = 1;
+		command = NAND_CMD_READ0;
+		column = 0;
+read0:
+		fsl_nfc_send_cmd(mtd,
+				PAGE_READ_CMD_BYTE1,
+				PAGE_READ_CMD_BYTE2,
+				READ_PAGE_CMD_CODE);
+		break;
+
+	case NAND_CMD_SEQIN:
+		fsl_nfc_command(mtd, NAND_CMD_READ0, column, page);
+		column = 0;
+		break;
+
+	case NAND_CMD_ERASE1:
+		fsl_nfc_send_cmd(mtd,
+				ERASE_CMD_BYTE1,
+				ERASE_CMD_BYTE2,
+				ERASE_CMD_CODE);
+		break;
+	case NAND_CMD_ERASE2:
+		return;
+	case NAND_CMD_READID:
+		get_id = 1;
+		fsl_nfc_send_one_byte(mtd, command, READ_ID_CMD_CODE);
+		break;
+	case NAND_CMD_STATUS:
+		get_status = 1;
+		fsl_nfc_send_one_byte(mtd, command, STATUS_READ_CMD_CODE);
+		break;
+	case NAND_CMD_RNDOUT:
+		fsl_nfc_send_cmd(mtd,
+				RANDOM_OUT_CMD_BYTE1,
+				RANDOM_OUT_CMD_BYTE2,
+				RANDOM_OUT_CMD_CODE);
+		break;
+	case NAND_CMD_RESET:
+		fsl_nfc_send_one_byte(mtd, command, RESET_CMD_CODE);
+		break;
+	default:
+		return;
+	}
+
+	fsl_nfc_addr_cycle(mtd, column, page);
+
+	fsl_nfc_done(mtd);
+}
+
+/* Copy data from/to NFC spare buffers. */
+static void
+fsl_nfc_copy_spare(struct mtd_info *mtd, uint offset,
+			u8 *buffer, uint size, int wr)
+{
+	struct nand_chip *nand = mtd->priv;
+	struct fsl_nfc_prv *prv = nand->priv;
+	uint o, s, sbsize, blksize;
+
+	/*
+	 * NAND spare area is available through NFC spare buffers.
+	 * The NFC divides spare area into (page_size / 512) chunks.
+	 * Each chunk is placed into separate spare memory area, using
+	 * first (spare_size / num_of_chunks) bytes of the buffer.
+	 *
+	 * For NAND device in which the spare area is not divided fully
+	 * by the number of chunks, number of used bytes in each spare
+	 * buffer is rounded down to the nearest even number of bytes,
+	 * and all remaining bytes are added to the last used spare area.
+	 *
+	 * For more information read section 26.6.10 of MPC5121e
+	 * Microcontroller Reference Manual, Rev. 3.
+	 */
+
+	/* Calculate number of valid bytes in each spare buffer */
+/*	sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;*/
+	sbsize = (mtd->oobsize / (mtd->writesize / 2048)) & ~1;
+
+
+	while (size) {
+		/* Calculate spare buffer number */
+		s = offset / sbsize;
+		if (s > NFC_SPARE_BUFFERS - 1)
+			s = NFC_SPARE_BUFFERS - 1;
+
+		/*
+		 * Calculate offset to requested data block in selected spare
+		 * buffer and its size.
+		 */
+		o = offset - (s * sbsize);
+		blksize = min(sbsize - o, size);
+
+		if (wr)
+			memcpy(prv->regs + NFC_SPARE_AREA(s) + o,
+							buffer, blksize);
+		else {
+			memcpy(buffer,
+				prv->regs + NFC_SPARE_AREA(s) + o, blksize);
+		}
+
+		buffer += blksize;
+		offset += blksize;
+		size -= blksize;
+	};
+}
+
+/* Copy data from/to NFC main and spare buffers */
+static void
+fsl_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len, int wr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+	uint c = prv->column;
+	uint l;
+
+	/* Handle spare area access */
+	if (prv->spareonly || c >= mtd->writesize) {
+		/* Calculate offset from beginning of spare area */
+		if (c >= mtd->writesize)
+			c -= mtd->writesize;
+
+		prv->column += len;
+		fsl_nfc_copy_spare(mtd, c, buf, len, wr);
+		return;
+	}
+
+	/*
+	 * Handle main area access - limit copy length to prevent
+	 * crossing main/spare boundary.
+	 */
+	l = min((uint)len, mtd->writesize - c);
+	prv->column += l;
+
+	if (wr)
+		memcpy(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
+	else {
+		if (get_status) {
+			get_status = 0;
+			*buf = fsl_nfc_get_status(mtd);
+		} else if (l == 1 && c <= 3 && get_id) {
+			*buf = fsl_nfc_get_id(mtd, c);
+		} else
+			memcpy(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
+	}
+
+	/* Handle crossing main/spare boundary */
+	if (l != len) {
+		buf += l;
+		len -= l;
+		fsl_nfc_buf_copy(mtd, buf, len, wr);
+	}
+}
+
+/* Read data from NFC buffers */
+static void
+fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	fsl_nfc_buf_copy(mtd, buf, len, 0);
+}
+
+/* Write data to NFC buffers */
+static void
+fsl_nfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	fsl_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
+}
+
+/* Compare buffer with NAND flash */
+static int
+fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	u_char tmp[256];
+	uint bsize;
+
+	while (len) {
+		bsize = min(len, 256);
+		fsl_nfc_read_buf(mtd, tmp, bsize);
+
+		if (memcmp(buf, tmp, bsize))
+			return 1;
+
+		buf += bsize;
+		len -= bsize;
+	}
+
+	return 0;
+}
+
+/* Read byte from NFC buffers */
+static u8
+fsl_nfc_read_byte(struct mtd_info *mtd)
+{
+	u8 tmp;
+	fsl_nfc_read_buf(mtd, &tmp, sizeof(tmp));
+	return tmp;
+}
+
+/* Read word from NFC buffers */
+static u16
+fsl_nfc_read_word(struct mtd_info *mtd)
+{
+	u16 tmp;
+	fsl_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
+	return tmp;
+}
+
+static void fsl_nfc_check_ecc_status(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+	u8 ecc_status, ecc_count;
+
+	ecc_status = *(u8 *)(prv->regs + ECC_SRAM_ADDR * 8 + 7);
+	ecc_count = ecc_status & ECC_ERR_COUNT;
+	if (ecc_status & ECC_STATUS_MASK) {
+		/*mtd->ecc_stats.failed++;*/
+		printf("ECC failed to correct all errors!\n");
+	} else if (ecc_count) {
+		/*mtd->ecc_stats.corrected += ecc_count;*/
+		printf("ECC corrected %d errors\n", ecc_count);
+	}
+
+}
+
+static void
+copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct fsl_nfc_prv *prv = chip->priv;
+	int i = 0, copy_count, copy_size;
+
+/*	copy_count = mtd->writesize / 512;*/
+	copy_count = mtd->writesize / 2048;
+	/*
+	 * Each spare area has 16 bytes for 512, 2K and normal 4K nand.
+	 * For 4K nand with large 218 byte spare size, the size is 26 bytes for
+	 * the first 7 buffers and 36 for the last.
+	 */
+/*	copy_size = mtd->oobsize == 218 ? 26 : 16;*/
+	copy_size = 64;
+	/*
+	 * Each spare area has 16 bytes for 512, 2K and normal 4K nand.
+	 * For 4K nand with large 218 byte spare size, the size is 26
+	 * bytes for the first 7 buffers and 36 for the last.
+	 */
+	for (i = 0; i < copy_count - 1 && len > 0; i++) {
+		if (wr)
+			memcpy(prv->regs + NFC_SPARE_AREA(i),
+					pbuf, MIN(len, copy_size));
+		else
+			memcpy(pbuf, prv->regs + NFC_SPARE_AREA(i),
+					MIN(len, copy_size));
+		pbuf += copy_size;
+		len -= copy_size;
+	}
+	if (len > 0) {
+		if (wr)
+			memcpy(prv->regs + NFC_SPARE_AREA(i),
+				pbuf, len);
+		else
+			memcpy(pbuf,
+				prv->regs + NFC_SPARE_AREA(i), len);
+	}
+}
+
+
+static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				int page, int sndcmd)
+{
+	fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page);
+	copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0);
+	return 0;
+}
+
+static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+					int page)
+{
+	fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page);
+	/* copy the oob data */
+	copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1);
+	fsl_nfc_command(mtd, NAND_CMD_PAGEPROG, 0, page);
+
+	return 0;
+}
+
+static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+					uint8_t *buf)
+{
+	struct fsl_nfc_prv *prv = chip->priv;
+	/*fsl_nfc_check_ecc_status(mtd);*/
+
+	memcpy((void *)buf, prv->regs + NFC_MAIN_AREA(0),
+			mtd->writesize);
+	copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0);
+	return 0;
+}
+
+static void fsl_nfc_write_page(struct mtd_info *mtd,
+		struct nand_chip *chip, const uint8_t *buf)
+{
+	struct fsl_nfc_prv *prv = chip->priv;
+	memcpy(prv->regs + NFC_MAIN_AREA(0), buf, mtd->writesize);
+	copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1);
+}
+
+static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	return;
+}
+
+int board_nand_init(struct nand_chip *chip)
+{
+	struct fsl_nfc_prv *prv;
+	struct resource *res;
+	struct mtd_info *mtd;
+
+	uint chips_no = 0;
+	int retval = 0;
+	u8 *testbuf;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile ccm_t *ccm = (gpio_t *) MMAP_CCM;
+
+	if (chip->IO_ADDR_R == NULL) {
+		return -1;
+	}
+
+	prv = malloc(sizeof(*prv));
+	if (!prv) {
+		printf(KERN_ERR DRV_NAME ": Memory exhausted!\n");
+		return -ENOMEM;
+	}
+
+	mtd = &nand_info[chips_no++];
+	mtd->priv = chip;
+	chip->priv = prv;
+
+	prv->regs = (void __iomem *)chip->IO_ADDR_R;
+	prv->testbuf = testbuf;
+
+	mtd->name = "NAND";
+	mtd->writesize = 2048;
+	mtd->oobsize = 64;
+	chip->dev_ready = fsl_nfc_dev_ready;
+	chip->cmdfunc = fsl_nfc_command;
+	chip->read_byte = fsl_nfc_read_byte;
+	chip->read_word = fsl_nfc_read_word;
+	chip->read_buf = fsl_nfc_read_buf;
+	chip->write_buf = fsl_nfc_write_buf;
+	chip->verify_buf = fsl_nfc_verify_buf;
+	chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16 | NAND_CACHEPRG;
+
+	chip->select_chip = m54418twr_select_chip;
+
+	if (hardware_ecc) {
+		chip->ecc.read_page = fsl_nfc_read_page;
+		chip->ecc.write_page = fsl_nfc_write_page;
+		chip->ecc.read_oob = fsl_nfc_read_oob;
+		chip->ecc.write_oob = fsl_nfc_write_oob;
+		chip->ecc.layout = &fsl_nfc_ecc45;
+
+		/* propagate ecc.layout to mtd_info */
+		mtd->ecclayout = chip->ecc.layout;
+		chip->ecc.calculate = NULL;
+		chip->ecc.hwctl = fsl_nfc_enable_hwecc;
+		chip->ecc.correct = NULL;
+		chip->ecc.mode = NAND_ECC_HW;
+		/* RS-ECC is applied for both MAIN+SPARE not MAIN alone */
+		chip->ecc.steps = 1;
+		chip->ecc.bytes = 45;
+		chip->ecc.size = 0x800;
+
+		nfc_set_field(mtd, NFC_FLASH_CONFIG,
+				CONFIG_ECC_MODE_MASK,
+				CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+		/* set ECC_STATUS write position */
+		nfc_set_field(mtd, NFC_FLASH_CONFIG,
+				CONFIG_ECC_SRAM_ADDR_MASK,
+				CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
+		/* enable ECC_STATUS results write */
+		nfc_set_field(mtd, NFC_FLASH_CONFIG,
+				CONFIG_ECC_SRAM_REQ_MASK,
+				CONFIG_ECC_SRAM_REQ_SHIFT, 1);
+	} else {
+		chip->ecc.mode = NAND_ECC_SOFT;
+		/* set ECC BY_PASS */
+		nfc_set_field(mtd, NFC_FLASH_CONFIG,
+				CONFIG_ECC_MODE_MASK,
+				CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
+	}
+	chip->bbt_td = &bbt_main_descr;
+	chip->bbt_md = &bbt_mirror_descr;
+	bbt_main_descr.pattern = bbt_pattern;
+	bbt_mirror_descr.pattern = mirror_pattern;
+
+	/* SET SECTOR SIZE */
+	nfc_write(mtd, NFC_SECTOR_SIZE, PAGE_2K | PAGE_64);
+
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+			CONFIG_ADDR_AUTO_INCR_MASK,
+			CONFIG_ADDR_AUTO_INCR_SHIFT, 0);
+
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+			CONFIG_BUFNO_AUTO_INCR_MASK,
+			CONFIG_BUFNO_AUTO_INCR_SHIFT, 0);
+
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+			CONFIG_16BIT_MASK,
+			CONFIG_16BIT_SHIFT, 1);
+
+	/* SET FAST_FLASH = 1 */
+#if 0
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+			CONFIG_FAST_FLASH_MASK,
+			CONFIG_FAST_FLASH_SHIFT, 1);
+
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+			CONFIG_BOOT_MODE_MASK,
+			CONFIG_BOOT_MODE_SHIFT, 0);
+#endif
+	return 0;
+}
+
diff -Naur u-boot-2009.08.orig/drivers/mtd/nand/Makefile u-boot-2009.08/drivers/mtd/nand/Makefile
--- u-boot-2009.08.orig/drivers/mtd/nand/Makefile	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/nand/Makefile	2010-08-17 11:04:37.197702095 -0400
@@ -46,6 +46,7 @@
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_FSL_NFC) += fsl_nfc.o
 endif
 
 COBJS	:= $(COBJS-y)
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/atmel.c u-boot-2009.08/drivers/mtd/spi/atmel.c
--- u-boot-2009.08.orig/drivers/mtd/spi/atmel.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/spi/atmel.c	2010-08-17 11:04:37.197702095 -0400
@@ -2,6 +2,10 @@
  * Atmel SPI DataFlash support
  *
  * Copyright (C) 2008 Atmel Corporation
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  */
 
 #include <common.h>
@@ -20,6 +24,18 @@
 #define CMD_AT45_PROG_BUF1		0x88
 #define CMD_AT45_PROG_BUF2		0x89
 
+#define CMD_AT26_READ_STATUS		0x05
+#define CMD_AT26_WRITE_STATUS		0x01
+#define CMD_AT26_WRITE_DIS		0x04
+#define CMD_AT26_WRITE_EN		0x06
+#define CMD_AT26_ERASE_BLOCK_4K		0x20
+#define CMD_AT26_ERASE_BLOCK_32K	0x52
+#define CMD_AT26_ERASE_BLOCK_64K	0xD8
+#define CMD_AT26_PROG_PAGE		0x02
+#define CMD_AT26_READ_ARRAY		0x0B
+#define CMD_AT26_UNPROT_SECTOR		0x39
+#define AT26_STATUS_READY		(0x1)
+
 /* AT45 status register bits */
 #define AT45_STATUS_P2_PAGE_SIZE	(1 << 0)
 #define AT45_STATUS_READY		(1 << 7)
@@ -53,6 +69,14 @@
 
 static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
 	{
+		.idcode1		= 0x45,
+		.l2_page_size		= 8,
+		.pages_per_block	= 128,
+		.blocks_per_sector	= 2,
+		.nr_sectors		= 16,
+		.name			= "AT26DF081A",
+	},
+	{
 		.idcode1		= 0x22,
 		.l2_page_size		= 8,
 		.pages_per_block	= 8,
@@ -110,6 +134,40 @@
 	},
 };
 
+static int at26_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+	struct spi_slave *spi = flash->spi;
+	unsigned long timebase;
+	int ret;
+	u8 cmd = CMD_AT26_READ_STATUS;
+	u8 status;
+
+	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+	if (ret) {
+		debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+		return ret;
+	}
+
+	timebase = get_timer(0);
+	do {
+		ret = spi_xfer(spi, 8, NULL, &status, 0);
+		if (ret)
+			return -1;
+
+		if ((status & AT26_STATUS_READY) == 0)
+			break;
+
+	} while (get_timer(timebase) < timeout);
+
+	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+	if ((status & AT26_STATUS_READY) == 0)
+		return 0;
+
+	/* Timed out */
+	return -1;
+}
+
 static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
 {
 	struct spi_slave *spi = flash->spi;
@@ -183,6 +241,26 @@
 	return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
 }
 
+static int dataflash_read_fast_at26(struct spi_flash *flash,
+			     u32 offset, size_t len, void *buf)
+{
+	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+	unsigned long page_addr;
+	unsigned long page_size;
+	u8 cmd[5];
+
+	page_size = asf->params->l2_page_size;
+	page_addr = offset / page_size;
+
+	cmd[0] = CMD_READ_ARRAY_FAST;
+	cmd[1] = page_addr >> 8;
+	cmd[2] = page_addr;
+	cmd[3] = offset % page_size;
+	cmd[4] = 0x00;
+
+	return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
 static int dataflash_read_fast_at45(struct spi_flash *flash,
 		u32 offset, size_t len, void *buf)
 {
@@ -265,6 +343,94 @@
 	return ret;
 }
 
+static int dataflash_write_at26(struct spi_flash *flash,
+		u32 offset, size_t len, const void *buf)
+{
+	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+	unsigned long page_addr;
+	unsigned long byte_addr;
+	unsigned long page_size;
+	size_t chunk_len;
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	/*
+	 * TODO: This function currently uses only page buffer #1.  We can
+	 * speed this up by using both buffers and loading one buffer while
+	 * the other is being programmed into main memory.
+	 */
+
+	page_size = (1 << asf->params->l2_page_size);
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		debug("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+#if 0
+	ret = spi_flash_cmd(flash->spi, CMD_AT26_WRITE_EN, NULL, 0);
+	if (ret < 0) {
+		debug("SF: Enabling Write failed\n");
+		return ret;
+	}
+
+	cmd[0] = CMD_AT26_WRITE_STATUS;
+	cmd[1] = 0;
+	ret = spi_flash_cmd_write(flash->spi, cmd, 2, NULL, 0);
+	if (ret < 0) {
+		debug("SF: AT26 page erase failed\n");
+		return ret;
+	}
+
+	ret = at26_wait_ready(flash, SPI_FLASH_SECTOR_ERASE_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: AT45 page programming timed out\n");
+		return ret;
+	}
+#endif
+	ret = 0;
+	for (actual = 0; actual < len; actual += chunk_len) {
+		chunk_len = min(len - actual, page_size - byte_addr);
+
+		/* Use the same address bits for both commands */
+		cmd[0] = CMD_AT26_PROG_PAGE;
+		cmd[1] = page_addr >> 8;
+		cmd[2] = page_addr;
+		cmd[3] = byte_addr;
+
+		ret = spi_flash_cmd(flash->spi, CMD_AT26_WRITE_EN, NULL, 0);
+		if (ret < 0) {
+			debug("SF: Enabling Write failed\n");
+			break;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+				buf + actual, chunk_len);
+		if (ret < 0) {
+			debug("SF: Loading AT26 buffer failed\n");
+			break;
+		}
+
+		ret = at26_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+		if (ret < 0) {
+			debug("SF: AT45 page programming timed out\n");
+			break;
+		}
+
+		page_addr++;
+		byte_addr = 0;
+	}
+
+	debug("SF: AT26: Successfully programmed %zu bytes @ 0x%x\n",
+			len, offset);
+
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
 static int dataflash_write_at45(struct spi_flash *flash,
 		u32 offset, size_t len, const void *buf)
 {
@@ -400,6 +566,91 @@
 	return ret;
 }
 
+int dataflash_erase_at26(struct spi_flash *flash, u32 offset, size_t len)
+{
+	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+	unsigned long sector_size;
+	unsigned long page_size;
+
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	/*
+	 * TODO: This function currently uses page erase only. We can
+	 * probably speed things up by using block and/or sector erase
+	 * when possible.
+	 */
+
+	page_size = (1 << asf->params->l2_page_size);
+	sector_size = page_size * asf->params->pages_per_block * asf->params->blocks_per_sector;
+
+	if (offset % page_size || len % page_size) {
+		debug("SF: Erase offset/length not multiple of page size\n");
+		return -1;
+	}
+
+	len /= sector_size;
+	cmd[2] = 0x00;
+	cmd[3] = 0x00;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		debug("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+
+	ret = spi_flash_cmd(flash->spi, CMD_AT26_WRITE_EN, NULL, 0);
+	if (ret < 0) {
+		debug("SF: Enabling Write failed\n");
+		return ret;
+	}
+
+	/* Global unprotect all sectors */
+	cmd[0] = CMD_AT26_WRITE_STATUS;
+	cmd[1] = 0;
+	ret = spi_flash_cmd_write(flash->spi, cmd, 2, NULL, 0);
+	if (ret < 0) {
+		debug("SF: AT26 page erase failed\n");
+		return ret;
+	}
+
+	ret = at26_wait_ready(flash, SPI_FLASH_SECTOR_ERASE_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: AT45 page programming timed out\n");
+		return ret;
+	}
+
+	ret = 0;
+	cmd[0] = CMD_AT26_ERASE_BLOCK_64K;
+	for (actual = 0; actual < len; actual++) {
+		cmd[1] = (offset / sector_size) + actual;
+		ret = spi_flash_cmd(flash->spi, CMD_AT26_WRITE_EN, NULL, 0);
+		if (ret < 0) {
+			debug("SF: Enabling Write failed\n");
+			break;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+		if (ret < 0) {
+			debug("SF: AT26 page erase failed\n");
+			break;
+		}
+
+		ret = at26_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+		if (ret < 0) {
+			debug("SF: AT26 page erase timed out\n");
+			break;
+		}
+	}
+
+	debug("SF: AT26: Successfully erased %zu bytes @ 0x%x\n",
+	    len * sector_size, offset);
+
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
 int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len)
 {
 	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
@@ -527,7 +778,9 @@
 
 	case DF_FAMILY_AT26F:
 	case DF_FAMILY_AT26DF:
-		asf->flash.read = dataflash_read_fast_p2;
+		asf->flash.read = dataflash_read_fast_at26;
+		asf->flash.write = dataflash_write_at26;
+		asf->flash.erase = dataflash_erase_at26;
 		break;
 
 	default:
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/Makefile u-boot-2009.08/drivers/mtd/spi/Makefile
--- u-boot-2009.08.orig/drivers/mtd/spi/Makefile	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/spi/Makefile	2010-08-17 11:04:37.197702095 -0400
@@ -31,6 +31,7 @@
 COBJS-$(CONFIG_SPI_FLASH_SPANSION)	+= spansion.o
 COBJS-$(CONFIG_SPI_FLASH_SST)	+= sst.o
 COBJS-$(CONFIG_SPI_FLASH_STMICRO)	+= stmicro.o
+COBJS-$(CONFIG_SPI_FLASH_WINBOND)	+= winbond.o
 COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
 
 COBJS	:= $(COBJS-y)
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/spi_flash.c u-boot-2009.08/drivers/mtd/spi/spi_flash.c
--- u-boot-2009.08.orig/drivers/mtd/spi/spi_flash.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/spi/spi_flash.c	2010-08-17 11:04:37.197702095 -0400
@@ -21,14 +21,14 @@
 
 	ret = spi_xfer(spi, 8, &cmd, NULL, flags);
 	if (ret) {
-		debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+		printf("SF: Failed to send command %02x: %d\n", cmd, ret);
 		return ret;
 	}
 
 	if (len) {
 		ret = spi_xfer(spi, len * 8, NULL, response, SPI_XFER_END);
 		if (ret)
-			debug("SF: Failed to read response (%zu bytes): %d\n",
+			printf("SF: Failed to read response (%zu bytes): %d\n",
 					len, ret);
 	}
 
@@ -46,12 +46,12 @@
 
 	ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
 	if (ret) {
-		debug("SF: Failed to send read command (%zu bytes): %d\n",
+		printf("SF: Failed to send read command (%zu bytes): %d\n",
 				cmd_len, ret);
 	} else if (data_len != 0) {
 		ret = spi_xfer(spi, data_len * 8, NULL, data, SPI_XFER_END);
 		if (ret)
-			debug("SF: Failed to read %zu bytes of data: %d\n",
+			printf("SF: Failed to read %zu bytes of data: %d\n",
 					data_len, ret);
 	}
 
@@ -69,12 +69,12 @@
 
 	ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
 	if (ret) {
-		debug("SF: Failed to send read command (%zu bytes): %d\n",
+		printf("SF: Failed to send read command (%zu bytes): %d\n",
 				cmd_len, ret);
 	} else if (data_len != 0) {
 		ret = spi_xfer(spi, data_len * 8, data, NULL, SPI_XFER_END);
 		if (ret)
-			debug("SF: Failed to read %zu bytes of data: %d\n",
+			printf("SF: Failed to read %zu bytes of data: %d\n",
 					data_len, ret);
 	}
 
@@ -105,13 +105,13 @@
 
 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
 	if (!spi) {
-		debug("SF: Failed to set up slave\n");
+		printf("SF: Failed to set up slave\n");
 		return NULL;
 	}
 
 	ret = spi_claim_bus(spi);
 	if (ret) {
-		debug("SF: Failed to claim SPI bus: %d\n", ret);
+		printf("SF: Failed to claim SPI bus: %d\n", ret);
 		goto err_claim_bus;
 	}
 
@@ -120,7 +120,7 @@
 	if (ret)
 		goto err_read_id;
 
-	debug("SF: Got idcode %02x %02x %02x %02x %02x\n", idcode[0],
+	printf("SF: Got idcode %02x %02x %02x %02x %02x\n", idcode[0],
 			idcode[1], idcode[2], idcode[3], idcode[4]);
 
 	switch (idcode[0]) {
@@ -140,6 +140,7 @@
 		break;
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO
+	case 0x1F:
 	case 0x20:
 		flash = spi_flash_probe_stmicro(spi, idcode);
 		break;
@@ -149,8 +150,13 @@
 		flash = spi_flash_probe_sst(spi, idcode);
 		break;
 #endif
+#ifdef CONFIG_SPI_FLASH_WINBOND
+	case 0xEF:
+		flash = spi_flash_probe_winbond(spi, idcode);
+		break;
+#endif
 	default:
-		debug("SF: Unsupported manufacturer %02X\n", idcode[0]);
+		printf("SF: Unsupported manufacturer %02X\n", idcode[0]);
 		flash = NULL;
 		break;
 	}
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/spi_flash_internal.h u-boot-2009.08/drivers/mtd/spi/spi_flash_internal.h
--- u-boot-2009.08.orig/drivers/mtd/spi/spi_flash_internal.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/spi/spi_flash_internal.h	2010-08-17 11:04:37.197702095 -0400
@@ -49,3 +49,4 @@
 struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/stmicro.c u-boot-2009.08/drivers/mtd/spi/stmicro.c
--- u-boot-2009.08.orig/drivers/mtd/spi/stmicro.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/mtd/spi/stmicro.c	2010-08-17 11:04:37.197702095 -0400
@@ -54,6 +54,8 @@
 #define STM_ID_M25P80		0x14
 #define STM_ID_M25P128		0x18
 
+#define ATM_ID_AT26DF081	0x01
+
 #define STMICRO_SR_WIP		(1 << 0)	/* Write-in-Progress */
 
 struct stmicro_spi_flash_params {
@@ -78,6 +80,13 @@
 
 static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
 	{
+		.idcode1 = ATM_ID_AT26DF081,
+		.page_size = 256,
+		.pages_per_sector = 256,
+		.nr_sectors = 16,
+		.name = "AT26DF081",
+	},
+	{
 		.idcode1 = STM_ID_M25P16,
 		.page_size = 256,
 		.pages_per_sector = 256,
@@ -213,7 +222,7 @@
 		cmd[2] = page_addr;
 		cmd[3] = byte_addr;
 
-		debug
+		printf
 		    ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
 		     buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
diff -Naur u-boot-2009.08.orig/drivers/mtd/spi/winbond.c u-boot-2009.08/drivers/mtd/spi/winbond.c
--- u-boot-2009.08.orig/drivers/mtd/spi/winbond.c	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/drivers/mtd/spi/winbond.c	2010-08-17 11:04:37.197702095 -0400
@@ -0,0 +1,324 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+/* W25XXX-specific commands */
+#define CMD_W25XXX_WREN		0x06	/* Write Enable */
+#define CMD_W25XXX_WRDI		0x04	/* Write Disable */
+#define CMD_W25XXX_RDSR		0x05	/* Read Status Register */
+#define CMD_W25XXX_WRSR		0x01	/* Write Status Register */
+#define CMD_W25XXX_READ		0x03	/* Read Data Bytes */
+#define CMD_W25XXX_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
+#define CMD_W25XXX_FAST_READ_D	0x3b	/* Read Data Bytes at Higher Speed Dual Output */
+#define CMD_W25XXX_PP		0x02	/* Page Program */
+#define CMD_W25XXX_SE		0x20	/* Sector Erase */
+#define CMD_W25XXX_BLK		0xd8	/* Block Erase */
+#define CMD_W25XXX_CHIP		0xc7	/* Chip Erase */
+#define CMD_W25XXX_DP		0xb9	/* Deep Power-down */
+#define CMD_W25XXX_RES		0xab	/* Release from DP, and Read Signature */
+#define CMD_W25XXX_DEV_ID	0x90	/* Manufacturer / Device ID */
+#define CMD_W25XXX_JEDEC_ID	0x9f	/* Jedec ID */
+
+#define WBD_ID_W25X10		0x10
+#define WBD_ID_W25X20		0x11
+#define WBD_ID_W25X40		0x12
+#define WBD_ID_W25X80		0x13
+
+#define winbond_SR_WIP		(1 << 0)	/* Write-in-Progress */
+
+struct winbond_spi_flash_params {
+	u8 idcode1;
+	u16 page_size;
+	u16 pages_per_sector;
+	u16 nr_sectors;
+	const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct winbond_spi_flash {
+	struct spi_flash flash;
+	const struct winbond_spi_flash_params *params;
+};
+
+static inline struct winbond_spi_flash *to_winbond_spi_flash(struct spi_flash
+							     *flash)
+{
+	return container_of(flash, struct winbond_spi_flash, flash);
+}
+
+static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
+	{
+		.idcode1 = WBD_ID_W25X10,
+		.page_size = 256,
+		.pages_per_sector = 256,
+		.nr_sectors = 32,
+		.name = "W25X16",
+	},
+	{
+		.idcode1 = WBD_ID_W25X20,
+		.page_size = 256,
+		.pages_per_sector = 256,
+		.nr_sectors = 4,
+		.name = "W25X20",
+	},
+	{
+		.idcode1 = WBD_ID_W25X40,
+		.page_size = 256,
+		.pages_per_sector = 256,
+		.nr_sectors = 8,
+		.name = "W25X40",
+	},
+	{
+		.idcode1 = WBD_ID_W25X80,
+		.page_size = 256,
+		.pages_per_sector = 256,
+		.nr_sectors = 16,
+		.name = "W25X80",
+	},
+};
+
+static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+	struct spi_slave *spi = flash->spi;
+	unsigned long timebase;
+	int ret;
+	u8 cmd = CMD_W25XXX_RDSR;
+	u8 status;
+
+	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+	if (ret) {
+		printf("SF: Failed to send command %02x: %d\n", cmd, ret);
+		return ret;
+	}
+
+	timebase = get_timer(0);
+	do {
+		ret = spi_xfer(spi, 8, NULL, &status, 0);
+		if (ret)
+			return -1;
+
+		if ((status & winbond_SR_WIP) == 0)
+			break;
+
+	} while (get_timer(timebase) < timeout);
+
+	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+	if ((status & winbond_SR_WIP) == 0)
+		return 0;
+
+	/* Timed out */
+	return -1;
+}
+
+static int winbond_read_fast(struct spi_flash *flash,
+			     u32 offset, size_t len, void *buf)
+{
+	struct winbond_spi_flash *wbd = to_winbond_spi_flash(flash);
+	unsigned long page_addr;
+	unsigned long page_size;
+	u8 cmd[5];
+
+	page_size = wbd->params->page_size;
+	page_addr = offset / page_size;
+
+	cmd[0] = CMD_READ_ARRAY_FAST;
+	cmd[1] = page_addr >> 8;
+	cmd[2] = page_addr;
+	cmd[3] = offset % page_size;
+	cmd[4] = 0x00;
+
+	return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
+static int winbond_write(struct spi_flash *flash,
+			 u32 offset, size_t len, const void *buf)
+{
+	struct winbond_spi_flash *wbd = to_winbond_spi_flash(flash);
+	unsigned long page_addr;
+	unsigned long byte_addr;
+	unsigned long page_size;
+	size_t chunk_len;
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	page_size = wbd->params->page_size;
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		printf("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+
+	ret = 0;
+	for (actual = 0; actual < len; actual += chunk_len) {
+		chunk_len = min(len - actual, page_size - byte_addr);
+
+		cmd[0] = CMD_W25XXX_PP;
+		cmd[1] = page_addr >> 8;
+		cmd[2] = page_addr;
+		cmd[3] = byte_addr;
+
+		printf
+		    ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
+		     buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+		ret = spi_flash_cmd(flash->spi, CMD_W25XXX_WREN, NULL, 0);
+		if (ret < 0) {
+			printf("SF: Enabling Write failed\n");
+			break;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+					  buf + actual, chunk_len);
+		if (ret < 0) {
+			printf("SF: winbond Page Program failed\n");
+			break;
+		}
+
+		ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+		if (ret < 0) {
+			printf("SF: winbond page programming timed out\n");
+			break;
+		}
+
+		page_addr++;
+		byte_addr = 0;
+	}
+
+	printf("SF: winbond: Successfully programmed %u bytes @ 0x%x\n",
+	      len, offset);
+
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
+int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+	struct winbond_spi_flash *wbd = to_winbond_spi_flash(flash);
+	unsigned long sector_size;
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	/*
+	 * This function currently uses sector erase only.
+	 * probably speed things up by using bulk erase
+	 * when possible.
+	 */
+
+	sector_size = wbd->params->page_size * wbd->params->pages_per_sector;
+
+	if (offset % sector_size || len % sector_size) {
+		printf("SF: Erase offset/length not multiple of sector size\n");
+		return -1;
+	}
+
+	len /= sector_size;
+	cmd[0] = CMD_W25XXX_SE;
+	cmd[2] = 0x00;
+	cmd[3] = 0x00;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		printf("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+
+	ret = 0;
+	for (actual = 0; actual < len; actual++) {
+		cmd[1] = (offset / sector_size) + actual;
+
+		ret = spi_flash_cmd(flash->spi, CMD_W25XXX_WREN, NULL, 0);
+		if (ret < 0) {
+			printf("SF: Enabling Write failed\n");
+			break;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+		if (ret < 0) {
+			printf("SF: winbond page erase failed\n");
+			break;
+		}
+
+		ret = winbond_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+		if (ret < 0) {
+			printf("SF: winbond page erase timed out\n");
+			break;
+		}
+	}
+
+	printf("SF: winbond: Successfully erased %u bytes @ 0x%x\n",
+	      len * sector_size, offset);
+
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 * idcode)
+{
+	const struct winbond_spi_flash_params *params;
+	struct winbond_spi_flash *wbd;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
+		params = &winbond_spi_flash_table[i];
+		if (params->idcode1 == idcode[2]) {
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
+		printf("SF: Unsupported winbond ID %02x\n", idcode[1]);
+		return NULL;
+	}
+
+	wbd = malloc(sizeof(struct winbond_spi_flash));
+	if (!wbd) {
+		printf("SF: Failed to allocate memory\n");
+		return NULL;
+	}
+
+	wbd->params = params;
+	wbd->flash.spi = spi;
+	wbd->flash.name = params->name;
+
+	wbd->flash.write = winbond_write;
+	wbd->flash.erase = winbond_erase;
+	wbd->flash.read = winbond_read_fast;
+	wbd->flash.size = params->page_size * params->pages_per_sector
+	    * params->nr_sectors;
+
+	printf("SF: Detected %s with page size %u, total %u bytes\n",
+	      params->name, params->page_size, wbd->flash.size);
+
+	return &wbd->flash;
+}
diff -Naur u-boot-2009.08.orig/drivers/net/fsl_mcdmafec.c u-boot-2009.08/drivers/net/fsl_mcdmafec.c
--- u-boot-2009.08.orig/drivers/net/fsl_mcdmafec.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/net/fsl_mcdmafec.c	2010-08-17 11:04:37.207699943 -0400
@@ -584,5 +584,7 @@
 	/* default speed */
 	bis->bi_ethspeed = 10;
 
+	fec_init(dev, bis);
+
 	return 0;
 }
diff -Naur u-boot-2009.08.orig/drivers/net/mcffec.c u-boot-2009.08/drivers/net/mcffec.c
--- u-boot-2009.08.orig/drivers/net/mcffec.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/net/mcffec.c	2010-08-17 11:04:37.207699943 -0400
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -48,6 +48,14 @@
 #define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
 #define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)
 
+#ifndef CONFIG_SYS_FEC0_PHYADDR
+#define CONFIG_SYS_FEC0_PHYADDR	-1
+#endif
+
+#ifndef CONFIG_SYS_FEC1_PHYADDR
+#define CONFIG_SYS_FEC1_PHYADDR	-1
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct fec_info_s fec_info[] = {
@@ -57,7 +65,7 @@
 	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
 	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
 	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
-	 -1,			/* phy_addr */
+	 CONFIG_SYS_FEC0_PHYADDR,	/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
 	 0,			/* phyname init */
@@ -67,6 +75,7 @@
 	 0,			/* tx Index */
 	 0,			/* tx buffer */
 	 0,			/* initialized flag */
+	 0,			/* link status */
 	 (struct fec_info_s *)-1,
 	 },
 #endif
@@ -76,7 +85,7 @@
 	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
 	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
 	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
-	 -1,			/* phy_addr */
+	 CONFIG_SYS_FEC1_PHYADDR,	/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
 	 0,			/* phy name init */
@@ -90,6 +99,7 @@
 	 0,			/* tx Index */
 	 0,			/* tx buffer */
 	 0,			/* initialized flag */
+	 0,			/* link status */
 	 (struct fec_info_s *)-1,
 	 }
 #endif
@@ -100,32 +110,38 @@
 int fec_init(struct eth_device *dev, bd_t * bd);
 void fec_halt(struct eth_device *dev);
 void fec_reset(struct eth_device *dev);
+static int fec_rst = 0;
 
 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
 {
 	if ((dup_spd >> 16) == FULL) {
 		/* Set maximum frame length */
-		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
-		    FEC_RCR_PROM | 0x100;
+		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | FEC_RCR_PROM |FEC_RCR_RMII_MODE;
 		fecp->tcr = FEC_TCR_FDEN;
+#ifdef MII_DEBUG
+		printf("Full duplex\n");
+#endif
 	} else {
 		/* Half duplex mode */
 		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
-		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
+		    FEC_RCR_MII_MODE | FEC_RCR_DRT | FEC_RCR_RMII_MODE;
 		fecp->tcr &= ~FEC_TCR_FDEN;
+#ifdef MII_DEBUG
+		printf("Half duplex\n");
+#endif
 	}
 
 	if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef CONFIG_MCF5445x
-		fecp->rcr &= ~0x200;	/* disabled 10T base */
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
+		fecp->rcr &= ~FEC_RCR_RMII_10T;	/* disabled 10T base */
 #endif
 #ifdef MII_DEBUG
 		printf("100Mbps\n");
 #endif
 		bd->bi_ethspeed = 100;
 	} else {
-#ifdef CONFIG_MCF5445x
-		fecp->rcr |= 0x200;	/* enabled 10T base */
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
+		fecp->rcr |= FEC_RCR_RMII_10T;	/* enabled 10T base */
 #endif
 #ifdef MII_DEBUG
 		printf("10Mbps\n");
@@ -141,7 +157,7 @@
 	int j, rc;
 	u16 phyStatus;
 
-	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+/*	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); */
 
 	/* section 16.9.23.3
 	 * Wait for ready
@@ -160,6 +176,8 @@
 	info->txbd[info->txIdx].cbd_datlen = length;
 	info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
 
+	__asm__("tpf");
+
 	/* Activate transmit Buffer Descriptor polling */
 	fecp->tdar = 0x01000000;	/* Descriptor polling active    */
 
@@ -231,6 +249,7 @@
 			printf("%s[%d] err: %x\n",
 			       __FUNCTION__, __LINE__,
 			       info->rxbd[info->rxIdx].cbd_sc);
+			dbgFecRegs(dev);
 #endif
 		} else {
 
@@ -290,7 +309,7 @@
 	printf("r_drng       %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
 	printf("x_drng       %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
 	printf("r_bufsz      %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
-
+#if 0
 	printf("\n");
 	printf("rmon_t_drop        %x - %x\n", (int)&fecp->rmon_t_drop,
 	       fecp->rmon_t_drop);
@@ -406,41 +425,18 @@
 	       fecp->ieee_r_fdxfc);
 	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
 	       fecp->ieee_r_octets_ok);
-
+#endif
 	printf("\n\n\n");
 }
 #endif
 
-int fec_init(struct eth_device *dev, bd_t * bd)
+/* Set station address */
+static void fec_set_mac(struct eth_device *dev)
 {
 	struct fec_info_s *info = dev->priv;
 	volatile fec_t *fecp = (fec_t *) (info->iobase);
-	int i;
 	uchar ea[6];
 
-	fecpin_setclear(dev, 1);
-
-	fec_reset(dev);
-
-#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
-	defined (CONFIG_SYS_DISCOVER_PHY)
-
-	mii_init();
-
-	setFecDuplexSpeed(fecp, bd, info->dup_spd);
-#else
-#ifndef CONFIG_SYS_DISCOVER_PHY
-	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
-#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
-#endif				/* CONFIG_CMD_MII || CONFIG_MII */
-
-	/* We use strictly polling mode only */
-	fecp->eimr = 0;
-
-	/* Clear any pending interrupt */
-	fecp->eir = 0xffffffff;
-
-	/* Set station address   */
 	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
 #ifdef CONFIG_SYS_FEC1_IOBASE
 		volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
@@ -468,6 +464,45 @@
 		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
 #endif
 	}
+}
+
+
+
+
+int fec_init(struct eth_device *dev, bd_t * bd)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+	int i;
+	uchar ea[6];
+
+	fecpin_setclear(dev, 1);
+
+	fec_reset(dev);
+
+#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
+	defined (CONFIG_SYS_DISCOVER_PHY)
+	mii_init(dev);
+	if(info->link)
+		setFecDuplexSpeed(fecp, bd, info->dup_spd);
+	else
+	{
+		debug("No link for %s\n", dev->name);
+		return -1;
+	}
+#else
+#ifndef CONFIG_SYS_DISCOVER_PHY
+	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
+#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
+#endif				/* CONFIG_CMD_MII || CONFIG_MII */
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	fec_set_mac(dev);
 
 	/* Clear unicast address hash table */
 	fecp->iaur = 0;
@@ -506,7 +541,7 @@
 	for (i = 0; i < TX_BUF_CNT; i++) {
 		info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
 		info->txbd[i].cbd_datlen = 0;	/* Reset */
-		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
+		info->txbd[i].cbd_bufaddr = 0;
 	}
 	info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
@@ -529,6 +564,9 @@
 	volatile fec_t *fecp = (fec_t *) (info->iobase);
 	int i;
 
+	if (fec_rst)
+		return;
+
 	fecp->ecr = FEC_ECR_RESET;
 	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
 		udelay(1);
@@ -536,6 +574,7 @@
 	if (i == FEC_RESET_DELAY) {
 		printf("FEC_RESET_DELAY timeout\n");
 	}
+	fec_rst++;
 }
 
 void fec_halt(struct eth_device *dev)
@@ -549,7 +588,6 @@
 	info->rxIdx = info->txIdx = 0;
 	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
 	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
-	memset(info->txbuf, 0, DBUF_LENGTH);
 }
 
 int mcffec_initialize(bd_t * bis)
@@ -586,10 +624,6 @@
 		    (cbd_t *)((u32)fec_info[i].txbd + tmp +
 		    (PKTBUFSRX * sizeof(cbd_t)));
 		tmp = (u32)fec_info[i].txbd;
-		fec_info[i].txbuf =
-		    (char *)((u32)fec_info[i].txbuf + tmp +
-		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
-		tmp = (u32)fec_info[i].txbuf;
 #else
 		fec_info[i].rxbd =
 		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
@@ -597,8 +631,6 @@
 		fec_info[i].txbd =
 		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 				       (TX_BUF_CNT * sizeof(cbd_t)));
-		fec_info[i].txbuf =
-		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
 #endif
 
 #ifdef ET_DEBUG
@@ -611,16 +643,21 @@
 		eth_register(dev);
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined (CONFIG_SYS_DISCOVER_PHY)
 		miiphy_register(dev->name,
 				mcffec_miiphy_read, mcffec_miiphy_write);
 #endif
+#endif
 		if (i > 0)
 			fec_info[i - 1].next = &fec_info[i];
-	}
-	fec_info[i - 1].next = &fec_info[0];
 
-	/* default speed */
-	bis->bi_ethspeed = 10;
+		/* default speed */
+		bis->bi_ethspeed = 10;
 
+		/* Set mac addr to fec even if we will not use it, then kernel can
+		 * get it
+		 */
+		fec_set_mac(dev);
+	}
 	return 0;
 }
diff -Naur u-boot-2009.08.orig/drivers/net/mcfmii.c u-boot-2009.08/drivers/net/mcfmii.c
--- u-boot-2009.08.orig/drivers/net/mcfmii.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/net/mcfmii.c	2010-08-17 11:04:37.207699943 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -154,12 +154,13 @@
 	int phyaddr, pass;
 	uint phyno, phytype;
 	int i, found = 0;
+	int no_phy = 1;
 
 	if (info->phyname_init)
 		return info->phy_addr;
 
-	phyaddr = -1;		/* didn't find a PHY yet */
-	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+	phyaddr = info->phy_addr;		/*Try to find PHY at phy_addr */
+	for (pass = 1; pass <= MAX_PHY_PASSES && no_phy; ++pass) {
 		if (pass > 1) {
 			/* PHY may need more time to recover from reset.
 			 * The LXT970 needs 50ms typical, no maximum is
@@ -169,17 +170,20 @@
 			udelay(10000);	/* wait 10ms */
 		}
 
-		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+		for (phyno = 0; phyno < 32 && no_phy; ++phyno) {
 
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+			phytype = mii_send(
+				  mk_mii_read((phyaddr < 0) ? phyno : phyaddr, PHY_PHYIDR1));
 #ifdef ET_DEBUG
 			printf("PHY type 0x%x pass %d type\n", phytype, pass);
 #endif
 			if (phytype != 0xffff) {
-				phyaddr = phyno;
+				if ( phyaddr < 0)
+					phyaddr = phyno;
+				no_phy = 0;
 				phytype <<= 16;
 				phytype |=
-				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+				    mii_send(mk_mii_read(phyaddr, PHY_PHYIDR2));
 
 #ifdef ET_DEBUG
 				printf("PHY @ 0x%x pass %d\n", phyno, pass);
@@ -210,27 +214,24 @@
 			}
 		}
 	}
-
-	if (phyaddr < 0)
+	if (no_phy)
 		printf("No PHY device found.\n");
 
 	return phyaddr;
 }
 #endif				/* CONFIG_SYS_DISCOVER_PHY */
 
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(struct eth_device *dev) __attribute__((weak,alias("__mii_init")));
 
-void __mii_init(void)
+void __mii_init(struct eth_device *dev)
 {
 	FEC_INFO_T *info;
 	volatile FEC_T *fecp;
-	struct eth_device *dev;
 	int miispd = 0, i = 0;
 	u16 status = 0;
 	u16 linkgood = 0;
 
 	/* retrieve from register structure */
-	dev = eth_get_dev();
 	info = dev->priv;
 
 	fecp = (FEC_T *) info->miibase;
@@ -247,8 +248,9 @@
 
 	/* Set MII speed */
 	miispd = (gd->bus_clk / 1000000) / 5;
+	miispd += 1;
 	fecp->mscr = miispd << 1;
-
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 	info->phy_addr = mii_discover_phy(dev);
 
 	while (i < MCFFEC_TOUT_LOOP) {
@@ -273,12 +275,16 @@
 		udelay(1);
 	}
 	if (i >= MCFFEC_TOUT_LOOP) {
-		printf("Link UP timeout\n");
+		printf("%s Link UP timeout\n", dev->name);
+		info->link = 0;
+		return;
 	}
-
+	info->link = 1;
 	/* adapt to the duplex and speed settings of the phy */
 	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
 	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+
+#endif
 }
 
 /*
diff -Naur u-boot-2009.08.orig/drivers/serial/mcfuart.c u-boot-2009.08/drivers/serial/mcfuart.c
--- u-boot-2009.08.orig/drivers/serial/mcfuart.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/drivers/serial/mcfuart.c	2010-08-17 11:04:37.207699943 -0400
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void uart_port_conf(void);
+extern void uart_port_conf(int port);
 
 int serial_init(void)
 {
@@ -43,7 +43,7 @@
 
 	uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
 
-	uart_port_conf();
+	uart_port_conf(CONFIG_SYS_UART_PORT);
 
 	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
 	uart->ucr = UART_UCR_RESET_RX;
diff -Naur u-boot-2009.08.orig/include/asm-m68k/fec.h u-boot-2009.08/include/asm-m68k/fec.h
--- u-boot-2009.08.orig/include/asm-m68k/fec.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/asm-m68k/fec.h	2010-08-17 11:04:37.207699943 -0400
@@ -6,7 +6,7 @@
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  *
  * Add FEC Structure and definitions
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -33,7 +33,7 @@
 
 /* Buffer descriptors used FEC.
 */
-typedef struct cpm_buf_desc {
+typedef volatile struct cpm_buf_desc {
 	ushort cbd_sc;		/* Status and Control */
 	ushort cbd_datlen;	/* Data length in buffer */
 	uint cbd_bufaddr;	/* Buffer address in host memory */
@@ -54,8 +54,7 @@
 #define BD_SC_OV		((ushort)0x0002)	/* Overrun */
 #define BD_SC_CD		((ushort)0x0001)	/* Carrier Detect lost */
 
-/* Buffer descriptor control/status used by Ethernet receive.
-*/
+/* Buffer descriptor control/status used by Ethernet receive. */
 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
 #define BD_ENET_RX_RO1		((ushort)0x4000)
 #define BD_ENET_RX_WRAP		((ushort)0x2000)
@@ -75,8 +74,7 @@
 #define BD_ENET_RX_TR		BD_ENET_RX_CL
 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
 
-/* Buffer descriptor control/status used by Ethernet transmit.
-*/
+/* Buffer descriptor control/status used by Ethernet transmit. */
 #define BD_ENET_TX_READY	((ushort)0x8000)
 #define BD_ENET_TX_PAD		((ushort)0x4000)
 #define BD_ENET_TX_TO1		BD_ENET_TX_PAD
@@ -90,14 +88,13 @@
 #define BD_ENET_TX_HB		((ushort)0x0100)
 #define BD_ENET_TX_LC		((ushort)0x0080)
 #define BD_ENET_TX_RL		((ushort)0x0040)
+
 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
 #define BD_ENET_TX_UN		((ushort)0x0002)
 #define BD_ENET_TX_CSL		((ushort)0x0001)
 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
 
-/*********************************************************************
-* Fast Ethernet Controller (FEC)
-*********************************************************************/
+/* Fast Ethernet Controller (FEC) */
 /* FEC private information */
 struct fec_info_s {
 	int index;
@@ -114,12 +111,13 @@
 	uint txIdx;
 	char *txbuf;
 	int initialized;
+	u16 link;
 	struct fec_info_s *next;
 };
 
 #ifdef CONFIG_MCFFEC
 /* Register read/write struct */
-typedef struct fec {
+typedef volatile struct fec {
 #ifdef CONFIG_M5272
 	u32 ecr;		/* 0x00 */
 	u32 eir;		/* 0x04 */
@@ -153,7 +151,6 @@
 	u32 erdsr;		/* 0x3D0 */
 	u32 etdsr;		/* 0x3D4 */
 	u32 emrbr;		/* 0x3D8 */
-	u8 resv12[0x74];	/* 0x18C */
 #else
 	u8 resv0[0x4];
 	u32 eir;
@@ -190,9 +187,27 @@
 	u32 erdsr;
 	u32 etdsr;
 	u32 emrbr;
-	u8 resv12[0x74];
 #endif
 
+#ifdef CONFIG_MCF5441x
+	u32 rsvd12;
+	u32 rsfl;
+	u32 rsem;
+	u32 raem;
+	u32 rafl;
+	u32 tsem;
+	u32 taem;
+	u32 tafl;
+	u32 tipg;
+	u32 ftrl;
+	u32 rsvd13[3];
+	u32 tacc;
+	u32 racc;
+#endif
+} fec_t;
+#endif				/* CONFIG_MCFFEC */
+
+struct fec_ieee_rmon {
 	u32 rmon_t_drop;
 	u32 rmon_t_packets;
 	u32 rmon_t_bc_pkt;
@@ -252,13 +267,9 @@
 	u32 ieee_r_macerr;
 	u32 ieee_r_fdxfc;
 	u32 ieee_r_octets_ok;
-} fec_t;
-#endif				/* CONFIG_MCFFEC */
+} fec_ieee_rmon_t;
 
-/*********************************************************************
-* Fast Ethernet Controller (FEC)
-*********************************************************************/
-/* Bit definitions and macros for FEC_EIR */
+/* Fast Ethernet Controller (FEC) Bit definitions */
 #define FEC_EIR_CLEAR_ALL		(0xFFF80000)
 #define FEC_EIR_HBERR			(0x80000000)
 #define FEC_EIR_BABR			(0x40000000)
@@ -273,18 +284,24 @@
 #define FEC_EIR_LC			(0x00200000)
 #define FEC_EIR_RL			(0x00100000)
 #define FEC_EIR_UN			(0x00080000)
+#define FEC_EIR_PLR			(0x00040000)
+#define FEC_EIR_WAKEUP			(0x00020000)
+#define FEC_EIR_TSAVAIL			(0x00010000)
+#define FEC_EIR_TSTMR			(0x00008000)
 
-/* Bit definitions and macros for FEC_RDAR */
 #define FEC_RDAR_R_DES_ACTIVE		(0x01000000)
 
-/* Bit definitions and macros for FEC_TDAR */
 #define FEC_TDAR_X_DES_ACTIVE		(0x01000000)
 
-/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_STOPEN			(0x00000080)
+#define FEC_ECR_DBGEN			(0x00000040)
+#define FEC_ECR_SPEED			(0x00000020)
+#define FEC_ECR_1588EN			(0x00000010)
+#define FEC_ECR_SLEEP			(0x00000008)
+#define FEC_ECR_MAGICEN			(0x00000004)
 #define FEC_ECR_ETHER_EN		(0x00000002)
 #define FEC_ECR_RESET			(0x00000001)
 
-/* Bit definitions and macros for FEC_MMFR */
 #define FEC_MMFR_DATA(x)		(((x)&0xFFFF))
 #define FEC_MMFR_ST(x)			(((x)&0x03)<<30)
 #define FEC_MMFR_ST_01			(0x40000000)
@@ -295,16 +312,23 @@
 #define FEC_MMFR_TA(x)			(((x)&0x03)<<16)
 #define FEC_MMFR_TA_10			(0x00020000)
 
-/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_HOLDTIME(x)		(((x)&7)<<8)
 #define FEC_MSCR_DIS_PREAMBLE		(0x00000080)
 #define FEC_MSCR_MII_SPEED(x)		(((x)&0x3F)<<1)
 
-/* Bit definitions and macros for FEC_MIBC */
 #define FEC_MIBC_MIB_DISABLE		(0x80000000)
 #define FEC_MIBC_MIB_IDLE		(0x40000000)
+#define FEC_MIBC_MIB_CLEAR		(0x20000000)
 
-/* Bit definitions and macros for FEC_RCR */
-#define FEC_RCR_MAX_FL(x)		(((x)&0x7FF)<<16)
+#define FEC_RCR_GRS			(0x80000000)
+#define FEC_RCR_NLC			(0x40000000)
+#define FEC_RCR_MAX_FL(x)		(((x)&0x3FFF)<<16)
+#define FEC_RCR_CFEN			(0x00008000)
+#define FEC_RCR_CRC_FWD			(0x00004000)
+#define FEC_RCR_PAU_FWD			(0x00002000)
+#define FEC_RCR_PADEN			(0x00001000)
+#define FEC_RCR_RMII_10T		(0x00000200)
+#define FEC_RCR_RMII_MODE		(0x00000100)
 #define FEC_RCR_FCE			(0x00000020)
 #define FEC_RCR_BC_REJ			(0x00000010)
 #define FEC_RCR_PROM			(0x00000008)
@@ -312,41 +336,72 @@
 #define FEC_RCR_DRT			(0x00000002)
 #define FEC_RCR_LOOP			(0x00000001)
 
-/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_CRC_FWD			(0x00000200)
+#define FEC_TCR_ADD_INS			(0x00000100)
+#define FEC_TCR_ADDSEL(x)		(((x)&7)<<5)
 #define FEC_TCR_RFC_PAUSE		(0x00000010)
 #define FEC_TCR_TFC_PAUSE		(0x00000008)
 #define FEC_TCR_FDEN			(0x00000004)
 #define FEC_TCR_HBC			(0x00000002)
 #define FEC_TCR_GTS			(0x00000001)
 
-/* Bit definitions and macros for FEC_PAUR */
 #define FEC_PAUR_PADDR2(x)		(((x)&0xFFFF)<<16)
 #define FEC_PAUR_TYPE(x)		((x)&0xFFFF)
 
-/* Bit definitions and macros for FEC_OPD */
-#define FEC_OPD_PAUSE_DUR(x)		(((x)&0x0000FFFF)<<0)
-#define FEC_OPD_OPCODE(x)		(((x)&0x0000FFFF)<<16)
+#define FEC_OPD_PAUSE_DUR(x)		((x)&0xFFFF)
+#define FEC_OPD_OPCODE(x)		(((x)&0xFFFF)<<16)
 
-/* Bit definitions and macros for FEC_TFWR */
-#define FEC_TFWR_X_WMRK(x)		((x)&0x03)
+#define FEC_TFWR_X_STR_FWD		(0x100)
+#define FEC_TFWR_X_WMRK(x)		((x)&0x3F)	/* 5441x uses 6 bits */
 #define FEC_TFWR_X_WMRK_64		(0x01)
 #define FEC_TFWR_X_WMRK_128		(0x02)
 #define FEC_TFWR_X_WMRK_192		(0x03)
 
-/* Bit definitions and macros for FEC_FRBR */
 #define FEC_FRBR_R_BOUND(x)		(((x)&0xFF)<<2)
 
-/* Bit definitions and macros for FEC_FRSR */
 #define FEC_FRSR_R_FSTART(x)		(((x)&0xFF)<<2)
 
-/* Bit definitions and macros for FEC_ERDSR */
+#ifdef CONFIG_MCF5441x
+#define FEC_ERDSR_R_DES_START(x)	(((x)&0x1FFFFFFF)<<3)
+#define FEC_ETDSR_X_DES_START(x)	(((x)&0x1FFFFFFF)<<3)
+#define FEC_EMRBR_R_BUF_SIZE(x)		(((x)&0x3FF)<<4)
+#else
 #define FEC_ERDSR_R_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for FEC_ETDSR */
 #define FEC_ETDSR_X_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for FEC_EMRBR */
 #define FEC_EMRBR_R_BUF_SIZE(x)		(((x)&0x7F)<<4)
+#endif
+
+#define FEC_RSFL(x)			((x)&0xFF)
+#define FEC_RSEM(x)			((x)&0xFF)
+#define FEC_RAEM(x)			((x)&0xFF)
+#define FEC_RAFL(x)			((x)&0xFF)
+#define FEC_TSEM(x)			((x)&0xFF)
+#define FEC_TAEM(x)			((x)&0xFF)
+#define FEC_TAFL(x)			((x)&0xFF)
+#define FEC_TIPG(x)			((x)&0x1F)
+#define FEC_FTRL(x)			((x)&0x3FFF)
+
+#define FEC_TACC_PRO_CHK		(0x00000010)
+#define FEC_TACC_IP_CHK			(0x00000008)
+#define FEC_TACC_SHIFT_16		(0x00000001)
+
+#define FEC_RACC_SHIFT_16		(0x00000080)
+#define FEC_RACC_LINE_DIS		(0x00000040)
+#define FEC_RACC_PRO_DIS		(0x00000004)
+#define FEC_RACC_IP_DIS			(0x00000002)
+#define FEC_RACC_PAD_REM		(0x00000001)
+
+#define FEC_ATCR_SLAVE			(0x00002000)
+#define FEC_ATCR_CAPTURE		(0x00000800)
+#define FEC_ATCR_RESTART		(0x00000200)
+#define FEC_ATCR_PIN_PER		(0x00000080)
+#define FEC_ATCR_PER_EN			(0x00000010)
+#define FEC_ATCR_OFF_RST		(0x00000008)
+#define FEC_ATCR_OFF_EN			(0x00000004)
+#define FEC_ATCR_EN			(0x00000001)
+
+#define FEC_ATINC_INC_CORR(x)		(((x)&0x7F)<<8)
+#define FEC_ATINC_INC(x)		((x&0x7F)
 
 #define	FEC_RESET_DELAY			100
 #define FEC_RX_TOUT			100
@@ -354,7 +409,7 @@
 int fecpin_setclear(struct eth_device *dev, int setclear);
 
 #ifdef CONFIG_SYS_DISCOVER_PHY
-void __mii_init(void);
+void __mii_init(struct eth_device *dev);
 uint mii_send(uint mii_cmd);
 int mii_discover_phy(struct eth_device *dev);
 int mcffec_miiphy_read(char *devname, unsigned char addr,
diff -Naur u-boot-2009.08.orig/include/asm-m68k/immap_5441x.h u-boot-2009.08/include/asm-m68k/immap_5441x.h
--- u-boot-2009.08.orig/include/asm-m68k/immap_5441x.h	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/include/asm-m68k/immap_5441x.h	2010-08-17 11:04:37.207699943 -0400
@@ -0,0 +1,386 @@
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS	0xFC004000
+#define MMAP_FBCS	0xFC008000
+#define MMAP_CAN0	0xFC020000
+#define MMAP_CAN1	0xFC024000
+#define MMAP_I2C1	0xFC038000
+#define MMAP_DSPI1	0xFC03C000
+#define MMAP_SCM	0xFC040000
+#define MMAP_PM		0xFC04002C
+#define MMAP_EDMA	0xFC044000
+#define MMAP_INTC0	0xFC048000
+#define MMAP_INTC1	0xFC04C000
+#define MMAP_INTC2	0xFC050000
+#define MMAP_IACK	0xFC054000
+#define MMAP_I2C0	0xFC058000
+#define MMAP_DSPI0	0xFC05C000
+#define MMAP_UART0	0xFC060000
+#define MMAP_UART1	0xFC064000
+#define MMAP_UART2	0xFC068000
+#define MMAP_UART3	0xFC06C000
+#define MMAP_DTMR0	0xFC070000
+#define MMAP_DTMR1	0xFC074000
+#define MMAP_DTMR2	0xFC078000
+#define MMAP_DTMR3	0xFC07C000
+#define MMAP_PIT0	0xFC080000
+#define MMAP_PIT1	0xFC084000
+#define MMAP_PIT2	0xFC088000
+#define MMAP_PIT3	0xFC08C000
+#define MMAP_EPORT0	0xFC090000
+#define MMAP_ADC	0xFC094000
+#define MMAP_DAC0	0xFC098000
+#define MMAP_DAC1	0xFC09C000
+#define MMAP_RTC	0xFC0A8000
+#define MMAP_SIM	0xFC0A8000
+#define MMAP_USBOTG	0xFC0B0000
+#define MMAP_USBEHCI	0xFC0B4000
+#define MMAP_SDRAM	0xFC0B8000
+#define MMAP_SSI0	0xFC0BC000
+#define MMAP_PLL	0xFC0C0000
+#define MMAP_RNG	0xFC0C4000
+#define MMAP_SSI1	0xFC0C8000
+#define MMAP_ESDHC	0xFC0CC000
+#define MMAP_FEC0	0xFC0D4000
+#define MMAP_FEC1	0xFC0D8000
+#define MMAP_L2_SW0	0xFC0DC000
+#define MMAP_L2_SW1	0xFC0E0000
+
+#define MMAP_NFC_RAM	0xFC0FC000
+
+#define MMAP_1WIRE	0xEC008000
+#define MMAP_I2C2	0xEC010000
+#define MMAP_I2C3	0xEC014000
+#define MMAP_I2C4	0xEC018000
+#define MMAP_I2C5	0xEC01C000
+#define MMAP_DSPI2	0xEC038000
+#define MMAP_DSPI3	0xEC03C000
+#define MMAP_UART4	0xEC060000
+#define MMAP_UART5	0xEC064000
+#define MMAP_UART6	0xEC068000
+#define MMAP_UART7	0xEC06C000
+#define MMAP_UART8	0xEC070000
+#define MMAP_UART9	0xEC074000
+#define MMAP_RCM	0xEC090000
+#define MMAP_CCM	0xEC090000
+#define MMAP_GPIO	0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+	u8 resv0[0x18];
+	u16 sbfsr;		/* Serial Boot Facility Status */
+	u8 resv1[0x6];
+	u16 sbfcr;		/* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u8 ccm_resv0[0x4];	/* 0x00 */
+	u16 ccr;		/* 0x04 Chip Configuration */
+	u8 resv1[0x2];		/* 0x06 */
+	u16 rcon;		/* 0x08 Reset Configuration */
+	u16 cir;		/* 0x0A Chip Identification */
+	u8 resv2[0x2];		/* 0x0C */
+	u16 misccr;		/* 0x0E Miscellaneous Control */
+	u16 cdrh;		/* 0x10 Clock Divider */
+	u16 cdrl;		/* 0x12 Clock Divider */
+	u16 uocsr;		/* 0x14 USB On-the-Go Controller Status */
+	u16 uhcsr;		/* 0x16 */
+	u16 misccr3;		/* 0x18 */
+	u16 misccr2;		/* 0x1A */
+	u16 adctsr;		/* 0x1C */
+	u16 dactsr;		/* 0x1E */
+	u16 sbfsr;		/* 0x20 */
+	u16 sbfcr;		/* 0x22 */
+	u32 fnacr;		/* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	u8 podr_a;		/* 0x00 */
+	u8 podr_b;		/* 0x01 */
+	u8 podr_c;		/* 0x02 */
+	u8 podr_d;		/* 0x03 */
+	u8 podr_e;		/* 0x04 */
+	u8 podr_f;		/* 0x05 */
+	u8 podr_g;		/* 0x06 */
+	u8 podr_h;		/* 0x07 */
+	u8 podr_i;		/* 0x08 */
+	u8 podr_j;		/* 0x09 */
+	u8 podr_k;		/* 0x0A */
+	u8 rsvd0;		/* 0x0B */
+
+	u8 pddr_a;		/* 0x0C */
+	u8 pddr_b;		/* 0x0D */
+	u8 pddr_c;		/* 0x0E */
+	u8 pddr_d;		/* 0x0F */
+	u8 pddr_e;		/* 0x10 */
+	u8 pddr_f;		/* 0x11 */
+	u8 pddr_g;		/* 0x12 */
+	u8 pddr_h;		/* 0x13 */
+	u8 pddr_i;		/* 0x14 */
+	u8 pddr_j;		/* 0x15 */
+	u8 pddr_k;		/* 0x16 */
+	u8 rsvd1;		/* 0x17 */
+
+	u8 ppdsdr_a;		/* 0x18 */
+	u8 ppdsdr_b;		/* 0x19 */
+	u8 ppdsdr_c;		/* 0x1A */
+	u8 ppdsdr_d;		/* 0x1B */
+	u8 ppdsdr_e;		/* 0x1C */
+	u8 ppdsdr_f;		/* 0x1D */
+	u8 ppdsdr_g;		/* 0x1E */
+	u8 ppdsdr_h;		/* 0x1F */
+	u8 ppdsdr_i;		/* 0x20 */
+	u8 ppdsdr_j;		/* 0x21 */
+	u8 ppdsdr_k;		/* 0x22 */
+	u8 rsvd2;		/* 0x23 */
+
+	u8 pclrr_a;		/* 0x24 */
+	u8 pclrr_b;		/* 0x25 */
+	u8 pclrr_c;		/* 0x26 */
+	u8 pclrr_d;		/* 0x27 */
+	u8 pclrr_e;		/* 0x28 */
+	u8 pclrr_f;		/* 0x29 */
+	u8 pclrr_g;		/* 0x2A */
+	u8 pclrr_h;		/* 0x2B */
+	u8 pclrr_i;		/* 0x2C */
+	u8 pclrr_j;		/* 0x2D */
+	u8 pclrr_k;		/* 0x2E */
+	u8 rsvd3;		/* 0x2F */
+
+	u16 pcr_a;		/* 0x30 */
+	u16 pcr_b;		/* 0x32 */
+	u16 pcr_c;		/* 0x34 */
+	u16 pcr_d;		/* 0x36 */
+	u16 pcr_e;		/* 0x38 */
+	u16 pcr_f;		/* 0x3A */
+	u16 pcr_g;		/* 0x3C */
+	u16 pcr_h;		/* 0x3E */
+	u16 pcr_i;		/* 0x40 */
+	u16 pcr_j;		/* 0x42 */
+	u16 pcr_k;		/* 0x44 */
+	u16 rsvd4;		/* 0x46 */
+
+	u8 par_fbctl;		/* 0x48 */
+	u8 par_be;		/* 0x49 */
+	u8 par_cs;		/* 0x4A */
+	u8 par_cani2c;		/* 0x4B */
+	u8 par_irqh;		/* 0x4C */
+	u8 par_irql;		/* 0x4D */
+	u8 par_dspi0;		/* 0x4E */
+	u8 par_dspiow;		/* 0x4F */
+	u8 par_timer;		/* 0x50 */
+	u8 par_uart2;		/* 0x51 */
+	u8 par_uart1;		/* 0x52 */
+	u8 par_uart0;		/* 0x53 */
+	u8 par_sdhch;		/* 0x54 */
+	u8 par_sdhcl;		/* 0x55 */
+	u8 par_simp0h;		/* 0x56 */
+	u8 par_simp1h;		/* 0x57 */
+	u8 par_ssi0h;		/* 0x58 */
+	u8 par_ssi0l;		/* 0x59 */
+	u8 par_dbg1h;		/* 0x5A */
+	u8 par_dbg0h;		/* 0x5B */
+	u8 par_dbgl;		/* 0x5C */
+	u8 rsvd5;		/* 0x5D */
+	u8 par_fec;		/* 0x5E */
+	u8 rsvd6;		/* 0x5F */
+
+	u8 mscr_sdram;		/* 0x60 */
+	u8 rsvd7[3];		/* 0x61-0x63 */
+
+	u8 srcr_fb1;		/* 0x64 */
+	u8 srcr_fb2;		/* 0x65 */
+	u8 srcr_fb3;		/* 0x66 */
+	u8 srcr_fb4;		/* 0x67 */
+	u8 srcr_dspiow;		/* 0x68 */
+	u8 srcr_cani2c;		/* 0x69 */
+	u8 srcr_irq;		/* 0x6A */
+	u8 srcr_timer;		/* 0x6B */
+	u8 srcr_uart;		/* 0x6C */
+	u8 srcr_fec;		/* 0x6D */
+	u8 srcr_sdhc;		/* 0x6E */
+	u8 srcr_simp0;		/* 0x6F */
+	u8 srcr_ssi0;		/* 0x70 */
+	u8 rsvd8[3];		/* 0x71-0x73 */
+
+	u16 urts_pol;		/* 0x74 */
+	u16 ucts_pol;		/* 0x76 */
+	u16 utxd_wom;		/* 0x78 */
+	u32 urxd_wom;		/* 0x7c */
+
+	u32 hcr1;		/* 0x80 */
+	u32 hcr0;		/* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 cr00;		/* 0x00 */
+	u32 cr01;		/* 0x04 */
+	u32 cr02;		/* 0x08 */
+	u32 cr03;		/* 0x0C */
+	u32 cr04;		/* 0x10 */
+	u32 cr05;		/* 0x14 */
+	u32 cr06;		/* 0x18 */
+	u32 cr07;		/* 0x1C */
+
+	u32 cr08;		/* 0x20 */
+	u32 cr09;		/* 0x24 */
+	u32 cr10;		/* 0x28 */
+	u32 cr11;		/* 0x2C */
+	u32 cr12;		/* 0x30 */
+	u32 cr13;		/* 0x34 */
+	u32 cr14;		/* 0x38 */
+	u32 cr15;		/* 0x3C */
+
+	u32 cr16;		/* 0x40 */
+	u32 cr17;		/* 0x44 */
+	u32 cr18;		/* 0x48 */
+	u32 cr19;		/* 0x4C */
+	u32 cr20;		/* 0x50 */
+	u32 cr21;		/* 0x54 */
+	u32 cr22;		/* 0x58 */
+	u32 cr23;		/* 0x5C */
+
+	u32 cr24;		/* 0x60 */
+	u32 cr25;		/* 0x64 */
+	u32 cr26;		/* 0x68 */
+	u32 cr27;		/* 0x6C */
+	u32 cr28;		/* 0x70 */
+	u32 cr29;		/* 0x74 */
+	u32 cr30;		/* 0x78 */
+	u32 cr31;		/* 0x7C */
+
+	u32 cr32;		/* 0x80 */
+	u32 cr33;		/* 0x84 */
+	u32 cr34;		/* 0x88 */
+	u32 cr35;		/* 0x8C */
+	u32 cr36;		/* 0x90 */
+	u32 cr37;		/* 0x94 */
+	u32 cr38;		/* 0x98 */
+	u32 cr39;		/* 0x9C */
+
+	u32 cr40;		/* 0xA0 */
+	u32 cr41;		/* 0xA4 */
+	u32 cr42;		/* 0xA8 */
+	u32 cr43;		/* 0xAC */
+	u32 cr44;		/* 0xB0 */
+	u32 cr45;		/* 0xB4 */
+	u32 cr46;		/* 0xB8 */
+	u32 cr47;		/* 0xBC */
+	u32 cr48;		/* 0xC0 */
+	u32 cr49;		/* 0xC4 */
+	u32 cr50;		/* 0xC8 */
+	u32 cr51;		/* 0xCC */
+	u32 cr52;		/* 0xD0 */
+	u32 cr53;		/* 0xD4 */
+	u32 cr54;		/* 0xD8 */
+	u32 cr55;		/* 0xDC */
+	u32 cr56;		/* 0xE0 */
+	u32 cr57;		/* 0xE4 */
+	u32 cr58;		/* 0xE8 */
+	u32 cr59;		/* 0xEC */
+	u32 cr60;		/* 0xF0 */
+	u32 cr61;		/* 0xF4 */
+	u32 cr62;		/* 0xF8 */
+	u32 cr63;		/* 0xFC */
+
+	u32 rsvd3[32];		/* 0xF4-0x1A8 */
+
+	u32 rcrcr;		/* 0x180 */
+	u32 swrcr;		/* 0x184 */
+	u32 rcr;		/* 0x188 */
+	u32 msovr;		/* 0x18C */
+	u32 rcrdbg;		/* 0x190 */
+	u32 sl0adj;		/* 0x194 */
+	u32 sl1adj;		/* 0x198 */
+	u32 sl2adj;		/* 0x19C */
+	u32 sl3adj;		/* 0x1A0 */
+	u32 sl4adj;		/* 0x1A4 */
+	u32 flight_tm;		/* 0x1A8 */
+	u32 padcr;		/* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* Control */
+	u32 pdr;		/* Divider */
+	u32 psr;		/* Status */
+} pll_t;
+
+typedef struct scm {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u32 bcr;		/* 0x24 */
+	u8 rsvd6[72];		/* 0x28 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm_t;
+
+typedef struct pm {
+	u8 pmsr0;		/* */
+	u8 pmcr0;
+	u8 pmsr1;
+	u8 pmcr1;
+	u32 pmhr0;
+	u32 pmlr0;
+	u32 pmhr1;
+	u32 pmlr1;
+} pm_t;
+
+#endif				/* __IMMAP_5441X__ */
diff -Naur u-boot-2009.08.orig/include/asm-m68k/immap.h u-boot-2009.08/include/asm-m68k/immap.h
--- u-boot-2009.08.orig/include/asm-m68k/immap.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/asm-m68k/immap.h	2010-08-17 11:04:37.207699943 -0400
@@ -1,7 +1,7 @@
 /*
  * ColdFire Internal Memory Map and Defines
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2009-2010 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -318,6 +318,45 @@
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE		(MMAP_UART4 + ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI			MMAP_DSPI0
+/*#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)*/
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+#endif				/* CONFIG_M54418 */
+
 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
 #include <asm/immap_5445x.h>
 #include <asm/m5445x.h>
diff -Naur u-boot-2009.08.orig/include/asm-m68k/io.h u-boot-2009.08/include/asm-m68k/io.h
--- u-boot-2009.08.orig/include/asm-m68k/io.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/asm-m68k/io.h	2010-08-17 11:04:37.207699943 -0400
@@ -56,6 +56,9 @@
  * are arrays of bytes, and byte-swapping is not appropriate in
  * that case.  - paulus
  */
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
 #define insb(port, buf, ns)	_insb((u8 *)((port)+_IO_BASE), (buf), (ns))
 #define outsb(port, buf, ns)	_outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
 #define insw(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
diff -Naur u-boot-2009.08.orig/include/asm-m68k/m5441x.h u-boot-2009.08/include/asm-m68k/m5441x.h
--- u-boot-2009.08.orig/include/asm-m68k/m5441x.h	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/include/asm-m68k/m5441x.h	2010-08-17 11:04:37.207699943 -0400
@@ -0,0 +1,887 @@
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM			(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_UART3			(29)
+#define INT0_LO_I2C0			(30)
+#define INT0_LO_DSPI0			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_MACNET0_TXF		(36)
+#define INT0_HI_MACNET0_TXB		(37)
+#define INT0_HI_MACNET0_UN		(38)
+#define INT0_HI_MACNET0_RL		(39)
+#define INT0_HI_MACNET0_RXF		(40)
+#define INT0_HI_MACNET0_RXB		(41)
+#define INT0_HI_MACNET0_MII		(42)
+#define INT0_HI_MACNET0_LC		(43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA		(45)
+#define INT0_HI_MACNET0_EBERR		(46)
+#define INT0_HI_MACNET0_BABT		(47)
+#define INT0_HI_MACNET0_BABR		(48)
+#define INT0_HI_MACNET1_TXF		(49)
+#define INT0_HI_MACNET1_TXB		(50)
+#define INT0_HI_MACNET1_UN		(51)
+#define INT0_HI_MACNET1_RL		(52)
+#define INT0_HI_MACNET1_RXF		(53)
+#define INT0_HI_MACNET1_RXB		(54)
+#define INT0_HI_MACNET1_MII		(55)
+#define INT0_HI_MACNET1_LC		(56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA		(58)
+#define INT0_HI_MACNET1_EBERR		(59)
+#define INT0_HI_MACNET1_BABT		(60)
+#define INT0_HI_MACNET1_BABR		(61)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_OW			(63)
+
+#define INT1_LO_CAN0_IFG		(0)
+#define INT1_LO_CAN0_BOFF		(1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN		(3)
+#define INT1_LO_CAN1_IFG		(4)
+#define INT1_LO_CAN1_BOFF		(5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN		(7)
+#define INT1_LO_EDMA_16			(8)
+#define INT1_LO_EDMA_17			(9)
+#define INT1_LO_EDMA_18			(10)
+#define INT1_LO_EDMA_19			(11)
+#define INT1_LO_EDMA_20			(12)
+#define INT1_LO_EDMA_21			(13)
+#define INT1_LO_EDMA_22			(14)
+#define INT1_LO_EDMA_23			(15)
+#define INT1_LO_EDMA_24			(16)
+#define INT1_LO_EDMA_25			(17)
+#define INT1_LO_EDMA_26			(18)
+#define INT1_LO_EDMA_27			(19)
+#define INT1_LO_EDMA_28			(20)
+#define INT1_LO_EDMA_29			(21)
+#define INT1_LO_EDMA_30			(22)
+#define INT1_LO_EDMA_31			(23)
+#define INT1_LO_EDMA_32			(24)
+#define INT1_LO_EDMA_33			(25)
+#define INT1_LO_EDMA_34			(26)
+#define INT1_LO_EDMA_35			(27)
+#define INT1_LO_EDMA_36			(28)
+#define INT1_LO_EDMA_37			(29)
+#define INT1_LO_EDMA_38			(30)
+#define INT1_LO_EDMA_39			(31)
+#define INT1_LO_EDMA_40			(32)
+#define INT1_HI_EDMA_41			(33)
+#define INT1_HI_EDMA_42			(34)
+#define INT1_HI_EDMA_43			(35)
+#define INT1_HI_EDMA_44			(36)
+#define INT1_HI_EDMA_45			(37)
+#define INT1_HI_EDMA_46			(38)
+#define INT1_HI_EDMA_47			(39)
+#define INT1_HI_EDMA_48			(40)
+#define INT1_HI_EDMA_49			(41)
+#define INT1_HI_EDMA_50			(42)
+#define INT1_HI_EDMA_51			(43)
+#define INT1_HI_EDMA_52			(44)
+#define INT1_HI_EDMA_53			(45)
+#define INT1_HI_EDMA_54			(46)
+#define INT1_HI_EDMA_55			(47)
+#define INT1_HI_UART4			(48)
+#define INT1_HI_UART5			(49)
+#define INT1_HI_UART6			(50)
+#define INT1_HI_UART7			(51)
+#define INT1_HI_UART8			(52)
+#define INT1_HI_UART9			(53)
+#define INT1_HI_DSPI1			(54)
+#define INT1_HI_DSPI2			(55)
+#define INT1_HI_DSPI3			(56)
+#define INT1_HI_I2C1			(57)
+#define INT1_HI_I2C2			(58)
+#define INT1_HI_I2C3			(59)
+#define INT1_HI_I2C4			(60)
+#define INT1_HI_I2C5			(61)
+
+#define INT2_LO_EDMA56_63		(0)
+#define INT2_LO_PWM_SM0SR_CF		(1)
+#define INT2_LO_PWM_SM1SR_CF		(2)
+#define INT2_LO_PWM_SM2SR_CF		(3)
+#define INT2_LO_PWM_SM3SR_CF		(4)
+#define INT2_LO_PWM_SM0SR_RF		(5)
+#define INT2_LO_PWM_SM1SR_RF		(6)
+#define INT2_LO_PWM_SM2SR_RF		(7)
+#define INT2_LO_PWM_SM3SR_RF		(8)
+#define INT2_LO_PWM_FSR			(9)
+#define INT2_LO_PWM_SMSR_REF		(10)
+#define INT2_LO_PLL_SR_LOCF		(11)
+#define INT2_LO_PLL_SR_LOLF		(12)
+#define INT2_LO_PIT0_PIF		(13)
+#define INT2_LO_PIT1_PIF		(14)
+#define INT2_LO_PIT2_PIF		(15)
+#define INT2_LO_PIT3_PIF		(16)
+#define INT2_LO_USBOTG_USBSTS		(17)
+#define INT2_LO_USBH_USBSTS		(18)
+/* not used 19-20 */
+#define INT2_LO_SSI0			(21)
+#define INT2_LO_SSI1			(22)
+#define INT2_LO_NFC			(23)
+/* not used 24-25 */
+#define INT2_LO_RTC			(26)
+#define INT2_LO_CCM_UOCSR		(27)
+#define INT2_LO_RNG_EI			(28)
+#define INT2_LO_SIM1_DATA		(29)
+#define INT2_LO_SIM1			(30)
+#define INT2_LO_SDHC			(31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR		(38)
+#define INT2_HI_L2SW_RXB		(39)
+#define INT2_HI_L2SW_RXF		(40)
+#define INT2_HI_L2SW_TXB		(41)
+#define INT2_HI_L2SW_TXF		(42)
+#define INT2_HI_L2SW_QM			(43)
+#define INT2_HI_L2SW_OD0		(44)
+#define INT2_HI_L2SW_OD1		(45)
+#define INT2_HI_L2SW_OD2		(46)
+#define INT2_HI_L2SW_LRN		(47)
+#define INT2_HI_MACNET0_TS		(48)
+#define INT2_HI_MACNET0_WAKE		(49)
+#define INT2_HI_MACNET0_PLR		(50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS		(51)
+#define INT2_HI_MACNET1_WAKE		(52)
+#define INT2_HI_MACNET1_PLR		(53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))
+#define SBF_SBFCR_FR			(0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST			(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_LOC			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD			(0xC000)
+#define CCM_CCR_PLLMULT			(0x0FC0)
+#define CCM_CCR_BOOTPS			(0x0030)
+#define CCM_CCR_BOOTPS_32		(0x0000)
+#define CCM_CCR_BOOTPS_16		(0x0020)
+#define CCM_CCR_BOOTPS_8		(0x0010)
+#define CCM_CCR_BOOTPS_			(0x0000)
+#define CCM_CCR_ALESEL			(0x0008)
+#define CCM_CCR_OSCMOD			(0x0004)
+#define CCM_CCR_PLLMOD			(0x0002)
+#define CCM_CCR_BOOTMEM			(0x0001)
+
+#define CCM_CIR_PIN_MASK		(0xFFC0)
+#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN_MCF54410		(0x9F<<6)
+#define CCM_CIR_PIN_MCF54415		(0xA0<<6)
+#define CCM_CIR_PIN_MCF54416		(0xA1<<6)
+#define CCM_CIR_PIN_MCF54417		(0xA2<<6)
+#define CCM_CIR_PIN_MCF54418		(0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x)	(((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK	(0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0	(0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1	(0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2	(0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3	(0xC000)
+#define CCM_MISCCR_LIMP			(0x1000)
+#define CCM_MISCCR_BME			(0x0800)
+#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+#define CCM_MISCCR_SDHCSRC		(0x0040)
+#define CCM_MISCCR_SSI1SRC		(0x0020)
+#define CCM_MISCCR_SSI0SRC		(0x0010)
+#define CCM_MISCCR_USBHOC		(0x0008)
+#define CCM_MISCCR_USBOOC		(0x0004)
+#define CCM_MISCCR_USBPUE		(0x0002)
+#define CCM_MISCCR_USBSRC		(0x0001)
+
+#define CCM_CDRH_SSI0DIV(x)		(((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK		(0x00FF)
+#define CCM_CDRH_SSI1DIV(x)		(((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK		(0xFF00)
+#define CCM_CDRL_LPDIV(x)		(((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK		(0xFF0F)
+#define CCM_CDR_LPDIV(x)		CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE			(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+#define CCM_UHCSR_DRV_VBUS		(0x0010)
+#define CCM_UHCSR_PWRFLT		(0x0008)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UOMIE			(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+#define CCM_MISCCR3_TMR_ENET		(0x1000)
+#define CCM_MISCCR3_ENETCLK(x)		(((x)&7))<<8)
+#define CCM_MISCCR3_ENETCLK_MASK	(0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII		(0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC		(0x0600)
+#define CCM_MISCCR3_ENETCLK_USB		(0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3	(0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2	(0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1	(0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0	(0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS	(0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP		(0x8000)
+#define CCM_MISCCR2_DDR2CLK		(0x4000)
+#define CCM_MISCCR2_RGPIO_HALF		(0x2000)
+#define CCM_MISCCR2_SWTSCR		(0x1000)
+#define CCM_MISCCR2_PLLMODE(x)		(((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK	(0xF8FF)
+#define CCM_MISCCR2_DCCBYP		(0x0080)
+#define CCM_MISCCR2_DAC1SEL		(0x0040)
+#define CCM_MISCCR2_DAC0SEL		(0x0020)
+#define CCM_MISCCR2_ADCEN		(0x0010)
+#define CCM_MISCCR2_ADC7SEL		(0x0008)
+#define CCM_MISCCR2_ADC3SEL		(0x0004)
+#define CCM_MISCCR2_FBHALF		(0x0002)
+#define CCM_MISCCR2_ULPI		(0x0001)
+
+#define CCM_FNACR_PCR(x)		(((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK		(0xF0FFFFFF)
+#define CCM_FNACR_MCC(x)		((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK		(0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x)		(((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK		(0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE	(0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS	(0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_OE(x)		(((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK		(0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE		(0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST	(0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE	(0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_FBCLK		(0x08)
+#define GPIO_PAR_FBCTL_RW		(0x04)
+#define GPIO_PAR_FBCTL_TA(x)		((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK		(0xFC)
+#define GPIO_PAR_FBCTL_TA_TA		(0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB	(0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
+
+#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK		(0x3F)
+#define GPIO_PAR_BE_BE3_BE3		(0xC0)
+#define GPIO_PAR_BE_BE3_CS3		(0x80)
+#define GPIO_PAR_BE_BE3_FB_A1		(0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE		(0x40)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK		(0xCF)
+#define GPIO_PAR_BE_BE2_BE2		(0x30)
+#define GPIO_PAR_BE_BE2_CS2		(0x20)
+#define GPIO_PAR_BE_BE2_FB_A0		(0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE		(0x10)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK		(0xF3)
+#define GPIO_PAR_BE_BE1_BE1		(0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1		(0x08)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BS0(x)		((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK		(0xFC)
+#define GPIO_PAR_BE_BE0_BE0		(0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0		(0x02)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+#define GPIO_PAR_CS_CS5(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK		(0x3F)
+#define GPIO_PAR_CS_CS5_CS5		(0xC0)
+#define GPIO_PAR_CS_CS5_DACK1		(0x80)
+#define GPIO_PAR_CS_CS5_GPIO		(0x00)
+#define GPIO_PAR_CS_CS4(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK		(0xCF)
+#define GPIO_PAR_CS_CS4_CS4		(0x30)
+#define GPIO_PAR_CS_CS4_DREQ1		(0x20)
+#define GPIO_PAR_CS_CS4_GPIO		(0x00)
+#define GPIO_PAR_CS_CS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK		(0xF3)
+#define GPIO_PAR_CS_CS1_CS1		(0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE		(0x04)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS_CS0_CS0		(0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK	(0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL	(0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD	(0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX	(0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK	(0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA	(0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD	(0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX	(0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK	(0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX	(0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD	(0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL	(0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x)	((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK	(0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX	(0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD	(0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA	(0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO	(0x00)
+
+#define GPIO_PAR_IRQH_IRQ7		(0x10)
+#define GPIO_PAR_IRQH_IRQ4(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK		(0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4		(0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0	(0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO		(0x00)
+#define GPIO_PAR_IRQH_IRQ1		(0x01)
+
+#define GPIO_PAR_IRQL_IRQ6(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK		(0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6		(0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN	(0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO		(0x00)
+#define GPIO_PAR_IRQL_IRQ3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK		(0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3		(0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3	(0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN	(0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO		(0x00)
+#define GPIO_PAR_IRQL_IRQ2(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK		(0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2		(0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2	(0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC	(0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO		(0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK		(0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD	(0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD	(0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO		(0x00)
+#define GPIO_PAR_DSPI0_SOUT(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK	(0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD	(0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0	(0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_SCK(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK		(0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL	(0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK	(0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO		(0x00)
+#define GPIO_PAR_DSPI0_PCS0(x)		((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK	(0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0	(0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS		(0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA	(0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3	(0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO	(0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1	(0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS		(0x80)
+#define GPIO_PAR_DSPIOW_OWDAT		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT	(0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0	(0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO	(0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN	(0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN(x)		((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC	(0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK	(0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS	(0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD	(0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK	(0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RTS(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK	(0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS	(0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD	(0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS	(0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RXD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK	(0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD	(0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3	(0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD	(0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2TXD(x)		((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK	(0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD	(0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3	(0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD	(0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO		(0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK	(0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS	(0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD	(0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK	(0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RTS(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK	(0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS	(0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD	(0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0	(0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RXD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK	(0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD	(0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA	(0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN	(0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1TXD(x)		((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK	(0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD	(0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL	(0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT	(0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO	(0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK	(0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS	(0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD	(0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK	(0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RTS(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK	(0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS	(0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD	(0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0	(0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RXD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK	(0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD	(0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA	(0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN	(0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0TXD(x)		((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK	(0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD	(0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL	(0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT	(0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK	(0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3	(0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1	(0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0	(0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK	(0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2	(0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1	(0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2	(0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK	(0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1	(0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2	(0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1	(0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT0(x)		((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK	(0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0	(0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2	(0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT	(0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK		(0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD		(0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0	(0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN	(0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO		(0x00)
+#define GPIO_PAR_SDHCL_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK		(0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK		(0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0	(0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK	(0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO		(0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK	(0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT		(0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2	(0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7	(0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_VEN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK	(0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN		(0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0	(0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_RST(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK	(0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST		(0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE	(0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6	(0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_PD(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK		(0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD		(0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC	(0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5	(0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO		(0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK	(0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK		(0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1	(0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4	(0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK		(0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD		(0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA	(0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN	(0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO		(0x00)
+#define GPIO_PAR_SSI0H_TXD(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK		(0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD		(0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL	(0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT	(0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO		(0x00)
+#define GPIO_PAR_SSI0H_FS(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK		(0xF3)
+#define GPIO_PAR_SSI0H_FS_FS		(0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD		(0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST	(0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO		(0x00)
+#define GPIO_PAR_SSI0H_MCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK	(0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN	(0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK	(0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK	(0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD	(0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD	(0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO	(0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3		(0x40)
+#define GPIO_PAR_DEBUGH1_DAT2		(0x10)
+#define GPIO_PAR_DEBUGH1_DAT1		(0x04)
+#define GPIO_PAR_DEBUGH1_DAT0		(0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3		(0x40)
+#define GPIO_PAR_DEBUGH0_PST2		(0x10)
+#define GPIO_PAR_DEBUGH0_PST1		(0x04)
+#define GPIO_PAR_DEBUGH0_PST0		(0x01)
+
+#define GPIO_PODR_G4_VAL		(0x01 << 4)
+#define GPIO_PODR_G4_MASK		(0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT		(0x01 << 4)
+#define GPIO_PDDR_G4_MASK		(0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST		(0x01)
+
+#define GPIO_PAR_FEC_FEC(x)		((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK		(0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO		(0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1		(0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL	(0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI	(0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0		(0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI	(0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL	(0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL	(0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1	(0x05)	/* 0:Full 1: */
+#define GPIO_PAR_FEC_FEC_RMII0_1	(0x04)	/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL	(0x03)
+#define GPIO_PAR_FEC_FEC_MII		(0x01)	/* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL		(0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x)		((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK	(0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x)		((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK		(0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x)		((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK		(0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x)		((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK		(0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK		(0xF3)
+#define GPIO_SRCR_FB4_FB4(x)		((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK		(0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x)	(((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x)	((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK	(0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x)	(((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK	(0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x)	((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK	(0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x)		((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK	(0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x)		(((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK	(0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x)		(((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK	(0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK	(0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x)		((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK	(0xFC)
+
+#define GPIO_SRCR_UART_U2(x)		(((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK		(0xCF)
+#define GPIO_SRCR_UART_U1(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK		(0xF3)
+#define GPIO_SRCR_UART_U0(x)		((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK		(0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK	(0xF3)
+#define GPIO_SRCR_FEC_RMII1(x)		((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK	(0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x)		((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK	(0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x)		((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK	(0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x)		((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK	(0xFC)
+
+#define GPIO_PCR_URTS_U2		(0x0004)
+#define GPIO_PCR_URTS_U1		(0x0002)
+#define GPIO_PCR_URTS_U0		(0x0001)
+
+#define GPIO_PCR_UCTS_U2		(0x0004)
+#define GPIO_PCR_UCTS_U1		(0x0002)
+#define GPIO_PCR_UCTS_U0		(0x0001)
+
+#define GPIO_UTXD_WOM_U9		(0x0200)
+#define GPIO_UTXD_WOM_U8		(0x0100)
+#define GPIO_UTXD_WOM_U7		(0x0080)
+#define GPIO_UTXD_WOM_U6		(0x0040)
+#define GPIO_UTXD_WOM_U5		(0x0020)
+#define GPIO_UTXD_WOM_U4		(0x0010)
+#define GPIO_UTXD_WOM_U3		(0x0008)
+#define GPIO_UTXD_WOM_U2		(0x0004)
+#define GPIO_UTXD_WOM_U1		(0x0002)
+#define GPIO_UTXD_WOM_U0		(0x0001)
+
+#define GPIO_URXD_WOM_U9(x)		(((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK		(0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x)		(((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK		(0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x)		(((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK		(0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x)		(((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK		(0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x)		(((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK		(0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x)		(((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK		(0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x)		(((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK		(0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x)		(((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK		(0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x)		(((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK		(0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x)		((x)&3)
+#define GPIO_URXD_WOM_U0_MASK		(0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x)		(((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK		(0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x)		(((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK		(0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x)		(((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK		(0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x)		(((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK		(0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x)		(((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK		(0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x)		((x)&7))
+#define GPIO_HCR1_PB2_0_MASK		(0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3			(0x00000400)
+#define GPIO_HCR0_PK0			(0x00000200)
+#define GPIO_HCR0_PD2_0(x)		(((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK		(0xFFFFFE3F)
+#define GPIO_HCR0_PE7			(0x00000020)
+#define GPIO_HCR0_PH7_3(x)		((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x)		(0xFFFFFFE0)
+
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ			(0x00040000)
+#define PLL_CR_LOCRE			(0x00020000)
+#define PLL_CR_LOCEN			(0x00010000)
+#define PLL_CR_LOLIRQ			(0x00004000)
+#define PLL_CR_LOLRE			(0x00002000)
+#define PLL_CR_LOLEN			(0x00001000)
+#define PLL_CR_REFDIV(x)		(((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK		(0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x)		((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK		(0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS		(0x3F)
+
+#define PLL_DR_OUTDIV5(x)		(((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK		(0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS		(0x03E00000)
+#define PLL_DR_OUTDIV4(x)		(((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK		(0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS		(0x001F0000)
+#define PLL_DR_OUTDIV3(x)		(((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK		(0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS		(0x00007C00)
+#define PLL_DR_OUTDIV2(x)		(((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK		(0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS		(0x000003E0)
+#define PLL_DR_OUTDIV1(x)		((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK		(0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS		(0x0000001F)
+
+#define PLL_SR_LOCF			(0x00000200)
+#define PLL_SR_LOC			(0x00000100)
+#define PLL_SR_LOLF			(0x00000040)
+#define PLL_SR_LOCKS			(0x00000020)
+#define PLL_SR_LOCK			(0x00000010)
+#define PLL_PSR_LOCK			PLL_SR_LOCK	/* compatible with 5x */
+#define PLL_SR_MODE(x)			((x)&7)
+#define PLL_SR_MODE_MASK		(0xFFFFFFF8)
+
+#endif				/* __MCF5441X__ */
diff -Naur u-boot-2009.08.orig/include/common.h u-boot-2009.08/include/common.h
--- u-boot-2009.08.orig/include/common.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/common.h	2010-08-17 11:04:37.207699943 -0400
@@ -543,7 +543,7 @@
 #if defined(CONFIG_8xx) || defined(CONFIG_8260)
 void	cpu_init_f    (volatile immap_t *immr);
 #endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_M68K) ||defined(CONFIG_MPC86xx)
 void	cpu_init_f    (void);
 #endif
 
@@ -579,7 +579,9 @@
 #define BOOTCOUNT_MAGIC		0xB001C041
 
 /* $(CPU)/.../<eth> */
+#ifndef CONFIG_MCFFEC
 void mii_init (void);
+#endif
 
 /* $(CPU)/.../lcd.c */
 ulong	lcd_setmem (ulong);
diff -Naur u-boot-2009.08.orig/include/configs/M5208EVBE.h u-boot-2009.08/include/configs/M5208EVBE.h
--- u-boot-2009.08.orig/include/configs/M5208EVBE.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/configs/M5208EVBE.h	2010-08-17 11:04:37.207699943 -0400
@@ -158,7 +158,7 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
 #define CONFIG_SYS_SDRAM_CTRL		0xE1002000
diff -Naur u-boot-2009.08.orig/include/configs/M5253DEMO.h u-boot-2009.08/include/configs/M5253DEMO.h
--- u-boot-2009.08.orig/include/configs/M5253DEMO.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/configs/M5253DEMO.h	2010-08-17 11:04:37.207699943 -0400
@@ -109,9 +109,9 @@
 		"u-boot=u-boot.bin\0"			\
 		"load=tftp ${loadaddr) ${u-boot}\0"	\
 		"upd=run load; run prog\0"		\
-		"prog=prot off 0 2ffff;"	\
-		"era 0 2ffff;"			\
-		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"prog=prot off ff800000 ff82ffff;"	\
+		"era ff800000 ff82ffff;"			\
+		"cp.b ${loadaddr} ff800000 ${filesize};"	\
 		"save\0"				\
 		""
 #endif
diff -Naur u-boot-2009.08.orig/include/configs/M53017EVB.h u-boot-2009.08/include/configs/M53017EVB.h
--- u-boot-2009.08.orig/include/configs/M53017EVB.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/configs/M53017EVB.h	2010-08-17 11:04:37.207699943 -0400
@@ -69,6 +69,8 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_SYS_DISCOVER_PHY
 #	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
+#	define CONFIG_SYS_TX_ETH_BUFFER 8
 #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #	define CONFIG_HAS_ETH1
 
@@ -166,7 +168,7 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
 #define CONFIG_SYS_INIT_RAM_END		0x20000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
@@ -180,7 +182,7 @@
 #define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD		0x80010000
 #define CONFIG_SYS_SDRAM_MODE		0x00CD0000
 
diff -Naur u-boot-2009.08.orig/include/configs/M5329EVB.h u-boot-2009.08/include/configs/M5329EVB.h
--- u-boot-2009.08.orig/include/configs/M5329EVB.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/configs/M5329EVB.h	2010-08-17 11:04:37.207699943 -0400
@@ -41,6 +41,7 @@
 #define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
diff -Naur u-boot-2009.08.orig/include/configs/M54418TWR.h u-boot-2009.08/include/configs/M54418TWR.h
--- u-boot-2009.08.orig/include/configs/M54418TWR.h	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/include/configs/M54418TWR.h	2010-08-17 11:04:37.207699943 -0400
@@ -0,0 +1,374 @@
+/*
+ * Configuation settings for the Freescale MCF54418 TWR board.
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54418TEST_H
+#define _M54418TEST_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5441x		/* define processor family */
+#define CONFIG_M54418		/* define processor type */
+#define CONFIG_M54418TEST	/* M54418TEST board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE		0xFC0FC000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define	CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#endif
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	2
+#	define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+#	define CONFIG_SYS_TX_ETH_BUFFER	2
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_MIIBASE
+#	define MCFFEC_TOUT_LOOP 50000
+#	define CONFIG_SYS_FEC0_PHYADDR	0
+#	define CONFIG_SYS_FEC1_PHYADDR	1
+
+#	define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds */
+
+#ifdef	CONFIG_NAND_BOOT
+#	define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
+#else
+#	define CONFIG_BOOTARGS		"root=/dev/nfs rw nfsroot=" MK_STR(CONFIG_SERVERIP) ":/tftpboot/"MK_STR(CONFIG_IPADDR) "  ip="MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP)":" MK_STR(CONFIG_GATEWAYIP)": "MK_STR(CONFIG_NETMASK)"::eth0:off:rw console=ttyS0,115200"
+#endif
+
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR		00:e0:0c:bc:e5:61
+#	define CONFIG_ETHPRIME		"FEC0"
+#	define CONFIG_IPADDR		192.168.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.168.1.1
+#	define CONFIG_GATEWAYIP		192.168.1.1
+/**/
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		M54418TWR
+#ifdef CONFIG_SERIAL_BOOT
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#else
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off mram" " ;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+#endif
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#undef CONFIG_FSL_I2C
+#undef CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
+#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_ATMEL
+
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
+#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_MBAR			0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END		0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF) || defined(CONFIG_NAND_BOOT)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
+#	define CONFIG_SYS_NO_FLASH
+#	define CONFIG_ENV_IS_IN_MRAM	1
+#	define CONFIG_ENV_ADDR		(0x40000 - 0x1000) /*MRAM size 40000*/
+#	define CONFIG_ENV_SIZE		0x1000
+#endif
+
+#if defined(CONFIG_CF_SBF)
+#	define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#	define CONFIG_ENV_SPI_CS		1
+#	define CONFIG_ENV_OFFSET		0x20000
+#	define CONFIG_ENV_SIZE			0x2000
+#	define CONFIG_ENV_SECT_SIZE		0x10000
+#endif
+#if defined(CONFIG_NAND_BOOT)
+#	define CONFIG_SYS_NO_FLASH
+#	define CONFIG_ENV_IS_IN_NAND	1
+#	define CONFIG_ENV_OFFSET	0x80000
+#	define CONFIG_ENV_SIZE		0x20000
+#	define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	270	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#else
+#	define CONFIG_SYS_MAX_FLASH_SECT	270	/* max number of sectors on one chip */
+#	define CONFIG_SYS_MAX_FLASH_BANKS	0	/* max number of memory banks */
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_OFFSET	(0x800000)
+#	define CONFIG_CMD_MTDPARTS
+#	define CONFIG_MTD_DEVICE
+#	define MTDIDS_DEFAULT		"nand0=m54418twr.nand"
+
+#define MTDPARTS_DEFAULT	"mtdparts=m54418twr.nand:1m(data),"	\
+						"7m(kernel),"		\
+						"-(rootfs)"
+
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x000F0101
+#define CONFIG_SYS_CS0_CTRL		0x00001D60
+
+#endif				/* _M54418TEST_H */
diff -Naur u-boot-2009.08.orig/include/configs/M54455EVB.h u-boot-2009.08/include/configs/M54455EVB.h
--- u-boot-2009.08.orig/include/configs/M54455EVB.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/configs/M54455EVB.h	2010-08-17 11:04:37.207699943 -0400
@@ -42,6 +42,7 @@
 #define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 
 #undef CONFIG_WATCHDOG
 
@@ -364,7 +365,6 @@
 #ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 #	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
diff -Naur u-boot-2009.08.orig/include/linux/mtd/nand.h u-boot-2009.08/include/linux/mtd/nand.h
--- u-boot-2009.08.orig/include/linux/mtd/nand.h	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/include/linux/mtd/nand.h	2010-08-17 11:04:37.207699943 -0400
@@ -50,7 +50,7 @@
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	218
+#define NAND_MAX_OOBSIZE	224 /*some dma need 8 bytes aligned*/
 #define NAND_MAX_PAGESIZE	4096
 
 /*
diff -Naur u-boot-2009.08.orig/include/mtd/fsl_nfc.h u-boot-2009.08/include/mtd/fsl_nfc.h
--- u-boot-2009.08.orig/include/mtd/fsl_nfc.h	1969-12-31 19:00:00.000000000 -0500
+++ u-boot-2009.08/include/mtd/fsl_nfc.h	2010-08-17 11:04:37.207699943 -0400
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Shaohui Xie <b21989@freescale.com>
+ *
+ * Description:
+ * MPC5125/M54418TWR Nand driver.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef MPC5125_NFC_H
+#define MPC5125_NFC_H
+
+
+/* NFC PAD Define */
+#define PAD_NFC_IO                	PAD_FUNC0
+#define PAD_NFC_ALE               	PAD_FUNC0
+#define PAD_NFC_CLE               	PAD_FUNC0
+#define PAD_NFC_WE                	PAD_FUNC0
+#define PAD_NFC_RE                	PAD_FUNC0
+#define PAD_NFC_CE0               	PAD_FUNC0
+#define PAD_NFC_CE1               	PAD_FUNC1
+#define PAD_NFC_CE2               	PAD_FUNC2
+#define PAD_NFC_CE3               	PAD_FUNC2
+#define PAD_NFC_RB0               	PAD_FUNC0
+#define PAD_NFC_RB1               	PAD_FUNC2
+#define PAD_NFC_RB2               	PAD_FUNC2
+#define PAD_NFC_RB3               	PAD_FUNC2
+
+/* NFC Control PAD Define */
+#define BALL_NFC_CE0			IOCTL_NFC_CE0_B
+#define BALL_NFC_CE1			IOCTL_SDHC1_CLK
+#define BALL_NFC_CE2			IOCTL_PSC1_4
+#define BALL_NFC_CE3			IOCTL_J1850_TX
+#define BALL_NFC_RB0			IOCTL_NFC_RB
+#define BALL_NFC_RB1			IOCTL_FEC1_TXD_0
+#define BALL_NFC_RB2			IOCTL_PSC1_3
+#define BALL_NFC_RB3			IOCTL_J1850_RX
+#define BALL_NFC_ALE			IOCTL_EMB_AD19
+#define BALL_NFC_CLE			IOCTL_EMB_AD18
+#define BALL_NFC_WE			IOCTL_EMB_AD16
+#define BALL_NFC_RE			IOCTL_EMB_AD17
+
+/* NFC IO Pad Define */
+#define BALL_NFC_IO0			IOCTL_EMB_AD00
+#define BALL_NFC_IO1			IOCTL_EMB_AD01
+#define BALL_NFC_IO2			IOCTL_EMB_AD02
+#define BALL_NFC_IO3			IOCTL_EMB_AD03
+#define BALL_NFC_IO4			IOCTL_EMB_AD04
+#define BALL_NFC_IO5			IOCTL_EMB_AD05
+#define BALL_NFC_IO6			IOCTL_EMB_AD06
+#define BALL_NFC_IO7			IOCTL_EMB_AD07
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n)		((n) *  0x1000)
+
+/* Addresses for NFC SPARE BUFFER areas */
+#define NFC_SPARE_BUFFERS		8
+#define NFC_SPARE_LEN			0x10
+#define NFC_SPARE_AREA(n)		(0x800 + ((n) * NFC_SPARE_LEN))
+
+#define PAGE_2K                   	0x0800
+#define PAGE_64                   	0x0040
+
+/* MPC5125 NFC registers */
+/* Typical Flash Commands */
+#define READ_PAGE_CMD_CODE		0x7EE0
+#define PROGRAM_PAGE_CMD_CODE		0x7FC0
+#define ERASE_CMD_CODE			0x4EC0
+#define READ_ID_CMD_CODE		0x4804
+#define RESET_CMD_CODE			0x4040
+#define DMA_PROGRAM_PAGE_CMD_CODE	0xFFC8
+#define RANDOM_IN_CMD_CODE		0x7140
+#define RANDOM_OUT_CMD_CODE		0x70E0
+#define STATUS_READ_CMD_CODE		0x4068
+
+#define PAGE_READ_CMD_BYTE1		0x00
+#define PAGE_READ_CMD_BYTE2		0x30
+#define PROGRAM_PAGE_CMD_BYTE1		0x80
+#define PROGRAM_PAGE_CMD_BYTE2		0x10
+#define READ_STATUS_CMD_BYTE		0x70
+#define ERASE_CMD_BYTE1			0x60
+#define ERASE_CMD_BYTE2			0xD0
+#define READ_ID_CMD_BYTE		0x90
+#define RESET_CMD_BYTE			0xFF
+#define RANDOM_OUT_CMD_BYTE1		0x05
+#define RANDOM_OUT_CMD_BYTE2		0xE0
+
+/* NFC ECC mode define */
+#define ECC_BYPASS			0x0
+#define ECC_8_BYTE			0x1
+#define ECC_12_BYTE			0x2
+#define ECC_15_BYTE			0x3
+#define ECC_23_BYTE			0x4
+#define ECC_30_BYTE			0x5
+#define ECC_45_BYTE			0x6
+#define ECC_60_BYTE			0x7
+#define ECC_ERROR			1
+#define ECC_RIGHT			0
+
+/***************** Module-Relative Register Offsets *************************/
+#define NFC_SRAM_BUFFER			0x0000
+#define NFC_FLASH_CMD1 			0x3F00
+#define NFC_FLASH_CMD2			0x3F04
+#define NFC_COL_ADDR			0x3F08
+#define NFC_ROW_ADDR			0x3F0c
+#define NFC_FLASH_COMMAND_REPEAT	0x3F10
+#define NFC_ROW_ADDR_INC		0x3F14
+#define NFC_FLASH_STATUS1		0x3F18
+#define NFC_FLASH_STATUS2		0x3F1c
+#define NFC_DMA1_ADDR			0x3F20
+#define NFC_DMA2_ADDR			0x3F34
+#define NFC_DMA_CONFIG			0x3F24
+#define NFC_CACHE_SWAP			0x3F28
+#define NFC_SECTOR_SIZE			0x3F2c
+#define NFC_FLASH_CONFIG		0x3F30
+#define NFC_IRQ_STATUS			0x3F38
+
+/***************** Module-Relative Register Reset Value *********************/
+#define NFC_SRAM_BUFFER_RSTVAL                	0x00000000
+#define NFC_FLASH_CMD1_RSTVAL 			0x30FF0000
+#define NFC_FLASH_CMD2_RSTVAL			0x007EE000
+#define NFC_COL_ADDR_RSTVAL			0x00000000
+#define NFC_ROW_ADDR_RSTVAL			0x11000000
+#define NFC_FLASH_COMMAND_REPEAT_RSTVAL		0x00000000
+#define NFC_ROW_ADDR_INC_RSTVAL			0x00000001
+#define NFC_FLASH_STATUS1_RSTVAL		0x00000000
+#define NFC_FLASH_STATUS2_RSTVAL		0x00000000
+#define NFC_DMA1_ADDR_RSTVAL			0x00000000
+#define NFC_DMA2_ADDR_RSTVAL			0x00000000
+#define NFC_DMA_CONFIG_RSTVAL			0x00000000
+#define NFC_CACHE_SWAP_RSTVAL			0x0FFE0FFE
+#define NFC_SECTOR_SIZE_RSTVAL			0x00000420
+#define NFC_FLASH_CONFIG_RSTVAL			0x000EA631
+#define NFC_IRQ_STATUS_RSTVAL			0x04000000
+
+/***************** Module-Relative Register Mask *************************/
+
+/* NFC_FLASH_CMD1 Field */
+#define CMD1_MASK				0xFFFF0000
+#define CMD1_SHIFT				0
+#define CMD_BYTE2_MASK    			0xFF000000
+#define CMD_BYTE2_SHIFT   			24
+#define CMD_BYTE3_MASK    			0x00FF0000
+#define CMD_BYTE3_SHIFT   			16
+
+/* NFC_FLASH_CM2 Field */
+#define CMD2_MASK				0xFFFFFF07
+#define CMD2_SHIFT				0
+#define CMD_BYTE1_MASK			    	0xFF000000
+#define CMD_BYTE1_SHIFT   			24
+#define CMD_CODE_MASK				0x00FFFF00
+#define CMD_CODE_SHIFT				8
+#define BUFNO_MASK				0x00000006
+#define BUFNO_SHIFT				1
+#define BUSY_MASK				0x00000001
+#define BUSY_SHIFT				0
+#define START_MASK				0x00000001
+#define START_SHIFT				0
+
+/* NFC_COL_ADDR Field */
+#define COL_ADDR_MASK				0x0000FFFF
+#define COL_ADDR_SHIFT				0
+#define COL_ADDR_COL_ADDR2_MASK			0x0000FF00
+#define COL_ADDR_COL_ADDR2_SHIFT		8
+#define COL_ADDR_COL_ADDR1_MASK			0x000000FF
+#define COL_ADDR_COL_ADDR1_SHIFT		0
+
+/* NFC_ROW_ADDR Field */
+#define ROW_ADDR_MASK				0x00FFFFFF
+#define ROW_ADDR_SHIFT				0
+#define ROW_ADDR_CHIP_SEL_RB_MASK		0xF0000000
+#define ROW_ADDR_CHIP_SEL_RB_SHIFT		28
+#define ROW_ADDR_CHIP_SEL_MASK			0x0F000000
+#define ROW_ADDR_CHIP_SEL_SHIFT			24
+#define ROW_ADDR_ROW_ADDR3_MASK			0x00FF0000
+#define ROW_ADDR_ROW_ADDR3_SHIFT		16
+#define ROW_ADDR_ROW_ADDR2_MASK			0x0000FF00
+#define ROW_ADDR_ROW_ADDR2_SHIFT		8
+#define ROW_ADDR_ROW_ADDR1_MASK			0x000000FF
+#define ROW_ADDR_ROW_ADDR1_SHIFT		0
+
+/* NFC_FLASH_COMMAND_REPEAT Field */
+#define COMMAND_REPEAT_MASK			0x0000FFFF
+#define COMMAND_REPEAT_SHIFT			0
+#define COMMAND_REPEAT_REPEAT_COUNT_MASK	0x0000FFFF
+#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT	0
+
+/* NFC_ROW_ADDR_INC Field */
+#define ROW_ADDR_INC_MASK			0x00FFFFFF
+#define ROW_ADDR_INC_SHIFT			0
+#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK		0x00FF0000
+#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT	16
+#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK		0x0000FF00
+#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT	8
+#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK		0x000000FF
+#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT	0
+
+/* NFC_FLASH_STATUS1 Field */
+#define STATUS1_MASK				0xFFFFFFFF
+#define STATUS1_SHIFT				0
+#define STATUS1_ID_BYTE1_MASK			0xFF000000
+#define STATUS1_ID_BYTE1_SHIFT			24
+#define STATUS1_ID_BYTE2_MASK			0x00FF0000
+#define STATUS1_ID_BYTE2_SHIFT			16
+#define STATUS1_ID_BYTE3_MASK			0x0000FF00
+#define STATUS1_ID_BYTE3_SHIFT			8
+#define STATUS1_ID_BYTE4_MASK			0x000000FF
+#define STATUS1_ID_BYTE4_SHIFT			0
+
+/* NFC_FLASH_STATUS2 Field */
+#define STATUS2_MASK				0xFF0000FF
+#define STATUS2_SHIFT				0
+#define STATUS2_ID_BYTE5_MASK			0xFF000000
+#define STATUS2_ID_BYTE5_SHIFT			24
+#define STATUS_BYTE1_MASK			0x000000FF
+#define STATUS2_STATUS_BYTE1_SHIFT		0
+
+/* NFC_DMA1_ADDR Field */
+#define DMA1_ADDR_MASK				0xFFFFFFFF
+#define DMA1_ADDR_SHIFT				0
+#define DMA1_ADDR_DMA1_ADDR_MASK		0xFFFFFFFF
+#define DMA1_ADDR_DMA1_ADDR_SHIFT		0
+
+/* DMA2_ADDR Field */
+#define DMA2_ADDR_MASK				0xFFFFFFFF
+#define DMA2_ADDR_SHIFT				0
+#define DMA2_ADDR_DMA2_ADDR_MASK		0xFFFFFFFF
+#define DMA2_ADDR_DMA2_ADDR_SHIFT		0
+
+/* DMA_CONFIG Field */
+#define DMA_CONFIG_MASK				0xFFFFFFFF
+#define DMA_CONFIG_SHIFT			0
+#define DMA_CONFIG_DMA1_CNT_MASK		0xFFF00000
+#define DMA_CONFIG_DMA1_CNT_SHIFT		20
+#define DMA_CONFIG_DMA2_CNT_MASK		0x000FE000
+#define DMA_CONFIG_DMA2_CNT_SHIFT		13
+#define DMA_CONFIG_DMA2_OFFSET_MASK		0x00001FC0
+#define DMA_CONFIG_DMA2_OFFSET_SHIFT		2
+#define DMA_CONFIG_DMA1_ACT_MASK		0x00000002
+#define DMA_CONFIG_DMA1_ACT_SHIFT		1
+#define DMA_CONFIG_DMA2_ACT_MASK		0x00000001
+#define DMA_CONFIG_DMA2_ACT_SHIFT		0
+
+/* NFC_CACHE_SWAP Field */
+#define CACHE_SWAP_MASK				0x0FFE0FFE
+#define CACHE_SWAP_SHIFT			1
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK	0x0FFE0000
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT	17
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK	0x00000FFE
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT	1
+
+/* NFC_SECTOR_SIZE Field */
+#define SECTOR_SIZE_MASK			0x00001FFF
+#define SECTOR_SIZE_SHIFT			0
+#define SECTOR_SIZE_SECTOR_SIZE_MASK		0x00001FFF
+#define SECTOR_SIZE_SECTOR_SIZE_SHIFT		0
+
+/* NFC_FLASH_CONFIG Field */
+#define CONFIG_MASK				0xFFFFFFFF
+#define CONFIG_SHIFT				0
+#define CONFIG_STOP_ON_WERR_MASK		0x80000000
+#define CONFIG_STOP_ON_WERR_SHIFT		31
+#define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
+#define CONFIG_ECC_SRAM_ADDR_SHIFT		22
+#define CONFIG_ECC_SRAM_REQ_MASK		0x00200000
+#define CONFIG_ECC_SRAM_REQ_SHIFT		21
+#define CONFIG_DMA_REQ_MASK			0x00100000
+#define CONFIG_DMA_REQ_SHIFT			20
+#define CONFIG_ECC_MODE_MASK			0x000E0000
+#define CONFIG_ECC_MODE_SHIFT			17
+#define CONFIG_FAST_FLASH_MASK			0x00010000
+#define CONFIG_FAST_FLASH_SHIFT			16
+#define CONFIG_ID_COUNT_MASK			0x0000E000
+#define CONFIG_ID_COUNT_SHIFT			13
+#define CONFIG_CMD_TIMEOUT_MASK			0x00001F00
+#define CONFIG_CMD_TIMEOUT_SHIFT		8
+#define CONFIG_16BIT_MASK			0x00000080
+#define CONFIG_16BIT_SHIFT			7
+#define CONFIG_BOOT_MODE_MASK			0x00000040
+#define CONFIG_BOOT_MODE_SHIFT			6
+#define CONFIG_ADDR_AUTO_INCR_MASK		0x00000020
+#define CONFIG_ADDR_AUTO_INCR_SHIFT		5
+#define CONFIG_BUFNO_AUTO_INCR_MASK		0x00000010
+#define CONFIG_BUFNO_AUTO_INCR_SHIFT		4
+#define CONFIG_PAGE_CNT_MASK			0x0000000F
+#define CONFIG_PAGE_CNT_SHIFT			0
+
+/* NFC_IRQ_STATUS Field */
+#define MASK					0xEFFC003F
+#define SHIFT					0
+#define WERR_IRQ_MASK				0x80000000
+#define WERR_IRQ_SHIFT				31
+#define CMD_DONE_IRQ_MASK			0x40000000
+#define CMD_DONE_IRQ_SHIFT			30
+#define IDLE_IRQ_MASK				0x20000000
+#define IDLE_IRQ_SHIFT				29
+#define WERR_STATUS_MASK			0x08000000
+#define WERR_STATUS_SHIFT			27
+#define FLASH_CMD_BUSY_MASK			0x04000000
+#define FLASH_CMD_BUSY_SHIFT			26
+#define RESIDUE_BUSY_MASK			0x02000000
+#define RESIDUE_BUSY_SHIFT			25
+#define ECC_BUSY_MASK				0x01000000
+#define ECC_BUSY_SHIFT				24
+#define DMA_BUSY_MASK				0x00800000
+#define DMA_BUSY_SHIFT				23
+#define WERR_EN_MASK				0x00400000
+#define WERR_EN_SHIFT				22
+#define CMD_DONE_EN_MASK			0x00200000
+#define CMD_DONE_EN_SHIFT			21
+#define IDLE_EN_MASK				0x00100000
+#define IDLE_EN_SHIFT				20
+#define WERR_CLEAR_MASK				0x00080000
+#define WERR_CLEAR_SHIFT			19
+#define CMD_DONE_CLEAR_MASK			0x00040000
+#define CMD_DONE_CLEAR_SHIFT			18
+#define IDLE_CLEAR_MASK				0x00020000
+#define IDLE_CLEAR_SHIFT			17
+#define RESIDUE_BUFF_NO_MASK			0x00000030
+#define RESIDUE_BUFF_NO_SHIFT			4
+#define ECC_BUFF_NO_MASK			0x000000C0
+#define ECC_BUFF_NO_SHIFT			2
+#define DMA_BUFF_NO_MASK			0x00000003
+
+#endif /* MPC5125_NFC_H */
diff -Naur u-boot-2009.08.orig/lib_m68k/board.c u-boot-2009.08/lib_m68k/board.c
--- u-boot-2009.08.orig/lib_m68k/board.c	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/lib_m68k/board.c	2010-08-17 11:04:37.207699943 -0400
@@ -573,6 +573,12 @@
 	spi_init_r ();
 #endif
 
+#if defined(CONFIG_CMD_NAND)
+	WATCHDOG_RESET ();
+	puts ("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate ();
 
@@ -659,12 +665,6 @@
 	doc_init ();
 #endif
 
-#if defined(CONFIG_CMD_NAND)
-	WATCHDOG_RESET ();
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
 #if defined(CONFIG_CMD_NET)
 	WATCHDOG_RESET();
 #if defined(FEC_ENET)
diff -Naur u-boot-2009.08.orig/Makefile u-boot-2009.08/Makefile
--- u-boot-2009.08.orig/Makefile	2009-08-31 13:57:42.000000000 -0400
+++ u-boot-2009.08/Makefile	2010-08-17 11:04:37.217701537 -0400
@@ -2112,6 +2112,48 @@
 	fi
 	@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
 
+M54418TWR_config \
+M54418TWR_mii_config \
+M54418TWR_rmii_config \
+M54418TWR_nand_config \
+M54418TWR_nand_mii_config \
+M54418TWR_nand_rmii_config \
+M54418TWR_serial_mii_config \
+M54418TWR_serial_rmii_config \
+M54418TWR_serial_config :	unconfig
+	@case "$@" in \
+	M54418TWR_config)		FLASH=NOR; FREQ=25000000;; \
+	M54418TWR_mii_config)		FLASH=NOR; FREQ=25000000;; \
+	M54418TWR_rmii_config)		FLASH=NOR; FREQ=50000000;; \
+	M54418TWR_nand_config)		FLASH=NAND; FREQ=25000000;; \
+	M54418TWR_nand_mii_config)	FLASH=NAND; FREQ=25000000;; \
+	M54418TWR_nand_rmii_config)	FLASH=NAND; FREQ=50000000;; \
+	M54418TWR_serial_config)	FLASH=SERIAL; FREQ=25000000;; \
+	M54418TWR_serial_mii_config)	FLASH=SERIAL; FREQ=25000000;; \
+	M54418TWR_serial_rmii_config)	FLASH=SERIAL; FREQ=50000000;; \
+	esac; \
+	if [ "$${FLASH}" = "NOR" ] ; then \
+		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54418twr/config.tmp ; \
+		cp $(obj)board/freescale/m54418twr/u-boot.nor $(obj)board/freescale/m54418twr/u-boot.lds ; \
+		$(XECHO) "... with NOR boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "NAND" ] ; then \
+		echo "#define CONFIG_NAND_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54418twr/config.tmp ; \
+		cp $(obj)board/freescale/m54418twr/u-boot.nor $(obj)board/freescale/m54418twr/u-boot.lds ; \
+		$(XECHO) "... with NAND boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "SERIAL" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_SERIAL_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54418twr/config.tmp ; \
+		cp $(obj)board/freescale/m54418twr/u-boot.ser $(obj)board/freescale/m54418twr/u-boot.lds ; \
+		$(XECHO) "... with Serial boot..." ; \
+	fi; \
+	echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ;	\
+	$(XECHO) "System Input Clock Source $${FREQ} Mhz" ;
+	@$(MKCONFIG) -a M54418TWR m68k mcf5445x m54418twr freescale
+
 M54451EVB_config \
 M54451EVB_stmicro_config :	unconfig
 	@case "$@" in \
@@ -2174,6 +2216,7 @@
 	$(XECHO) "... with $${FREQ}Hz input clock"
 	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
 
+M5474LITE_config\
 M5475AFE_config \
 M5475BFE_config \
 M5475CFE_config \
@@ -2182,6 +2225,7 @@
 M5475FFE_config \
 M5475GFE_config :	unconfig
 	@case "$@" in \
+	M5474LITE_config)       BOOT=4;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \
 	M5475AFE_config)	BOOT=2;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	M5475BFE_config)	BOOT=2;CODE=16;VID=0;USB=0;RAM=64;RAM1=0;; \
 	M5475CFE_config)	BOOT=2;CODE=16;VID=1;USB=1;RAM=64;RAM1=0;; \
