/*************************************************************************/ /*!
@Title          RGX Configuration for BVNC 35.V.1632.21 (kernel defines)
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@License        Dual MIT/GPLv2

The contents of this file are subject to the MIT license as set out below.

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*/ /**************************************************************************/

#ifndef RGXCONFIG_KM_35_V_1632_21_H
#define RGXCONFIG_KM_35_V_1632_21_H

/***** Automatically generated file. Do not edit manually ********************/

/******************************************************************************
 * B.V.N.C Validation defines
 *****************************************************************************/
#define RGX_BNC_KM_B 35
#define RGX_BNC_KM_N 1632
#define RGX_BNC_KM_C 21

/******************************************************************************
 * DDK Defines
 *****************************************************************************/
#define RGX_FEATURE_ALBIORIX_TOP_INFRASTRUCTURE
#define RGX_FEATURE_AXI_ACE
#define RGX_FEATURE_BARREX_TOP_INFRASTRUCTURE
#define RGX_FEATURE_CDM_CONTROL_STREAM_FORMAT (4U)
#define RGX_FEATURE_CLUSTER_GROUPING
#define RGX_FEATURE_COMPUTE
#define RGX_FEATURE_COMPUTE_MORTON_CAPABLE
#define RGX_FEATURE_COMPUTE_OVERLAP
#define RGX_FEATURE_COMPUTE_OVERLAP_WITH_BARRIERS
#define RGX_FEATURE_CONTEXT_SWITCH_3D_LEVEL (4U)
#define RGX_FEATURE_COREID_PER_OS
#define RGX_FEATURE_DUST_POWER_ISLAND_S7
#define RGX_FEATURE_ECC_RAMS (0U)
#define RGX_FEATURE_FASTRENDER_DM
#define RGX_FEATURE_FBCDC (4U)
#define RGX_FEATURE_FBCDC_ALGORITHM (4U)
#define RGX_FEATURE_FBCDC_ARCHITECTURE (6U)
#define RGX_FEATURE_GPU_MULTICORE_SUPPORT
#define RGX_FEATURE_GPU_VIRTUALISATION
#define RGX_FEATURE_GS_RTA_SUPPORT
#define RGX_FEATURE_LAYOUT_MARS (0U)
#define RGX_FEATURE_MAX_TPU_PER_SPU (2U)
#define RGX_FEATURE_META (MTP219)
#define RGX_FEATURE_META_COREMEM_BANKS (8U)
#define RGX_FEATURE_META_COREMEM_SIZE (96U)
#define RGX_FEATURE_META_DMA
#define RGX_FEATURE_META_DMA_CHANNEL_COUNT (4U)
#define RGX_FEATURE_META_REGISTER_UNPACKED_ACCESSES
#define RGX_FEATURE_MMU_VERSION (4U)
#define RGX_FEATURE_NUM_CLUSTERS (4U)
#define RGX_FEATURE_NUM_ISP_IPP_PIPES (16U)
#define RGX_FEATURE_NUM_ISP_PER_SPU (2U)
#define RGX_FEATURE_NUM_MEMBUS (2U)
#define RGX_FEATURE_NUM_OSIDS (8U)
#define RGX_FEATURE_NUM_SPU (2U)
#define RGX_FEATURE_PBE_CHECKSUM_2D
#define RGX_FEATURE_PBE_PER_SPU (1U)
#define RGX_FEATURE_PBVNC_COREID_REG
#define RGX_FEATURE_PDS_TEMPSIZE8
#define RGX_FEATURE_PERFBUS
#define RGX_FEATURE_PERF_COUNTER_BATCH
#define RGX_FEATURE_PHYS_BUS_WIDTH (40U)
#define RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES
#define RGX_FEATURE_POWER_ISLAND_VERSION (2U)
#define RGX_FEATURE_RAY_TRACING_ARCH (0U)
#define RGX_FEATURE_RENDER_TARGET_XY_MAX (32768U)
#define RGX_FEATURE_S7_CACHE_HIERARCHY
#define RGX_FEATURE_S7_TOP_INFRASTRUCTURE
#define RGX_FEATURE_SCALABLE_TE_ARCH (2U)
#define RGX_FEATURE_SCALABLE_VCE (2U)
#define RGX_FEATURE_SCALABLE_VDM_GPP
#define RGX_FEATURE_SIGNAL_SNOOPING
#define RGX_FEATURE_SLC_BANKS (4U)
#define RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS (1024U)
#define RGX_FEATURE_SLC_SIZE_ADJUSTMENT /* Specifies the SLC is */
                                        /* customer-configurable. True SLC */
                                        /* size must be sourced from */
                                        /* register. */
#define RGX_FEATURE_SLC_SIZE_IN_KILOBYTES (512U)
#define RGX_FEATURE_SLC_VIVT
#define RGX_FEATURE_SYS_BUS_SECURE_RESET
#define RGX_FEATURE_TDM_PDS_CHECKSUM
#define RGX_FEATURE_TESSELLATION
#define RGX_FEATURE_TILE_SIZE_X (32U)
#define RGX_FEATURE_TILE_SIZE_Y (32U)
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS
#define RGX_FEATURE_VDM_DRAWINDIRECT
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS
#define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS (40U)
#define RGX_FEATURE_ZLS_CHECKSUM

#endif /* RGXCONFIG_KM_35_V_1632_21_H */
