/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 *
 * (C) COPYRIGHT 2023-2024 ARM Limited. All rights reserved.
 *
 * This program is free software and is provided to you under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation, and any use by you of this program is subject to the terms
 * of such GNU license.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, you can access it online at
 * http://www.gnu.org/licenses/gpl-2.0.html.
 *
 */

/*
 * This header is autogenerated. Avoid modifying this file unless absolutely
 * necessary.
 */

#ifndef _MALI_KBASE_REGMAP_JM_ENUMS_H_
#define _MALI_KBASE_REGMAP_JM_ENUMS_H_

#if MALI_USE_CSF
#error "Cannot be compiled with CSF"
#endif

enum kbase_regmap_enum_v6_0 {
	GPU_CONTROL__GPU_ID = 0, /* (RO) 32-bit 0x0 */
	GPU_CONTROL__L2_FEATURES, /* (RO) 32-bit 0x4 */
	GPU_CONTROL__TILER_FEATURES, /* (RO) 32-bit 0xC */
	GPU_CONTROL__MEM_FEATURES, /* (RO) 32-bit 0x10 */
	GPU_CONTROL__MMU_FEATURES, /* (RO) 32-bit 0x14 */
	GPU_CONTROL__AS_PRESENT, /* (RO) 32-bit 0x18 */
	GPU_CONTROL__JS_PRESENT, /* (RO) 32-bit 0x1C */
	GPU_CONTROL__GPU_IRQ_RAWSTAT, /* (RW) 32-bit 0x20 */
	GPU_CONTROL__GPU_IRQ_CLEAR, /* (WO) 32-bit 0x24 */
	GPU_CONTROL__GPU_IRQ_MASK, /* (RW) 32-bit 0x28 */
	GPU_CONTROL__GPU_IRQ_STATUS, /* (RO) 32-bit 0x2C */
	GPU_CONTROL__GPU_COMMAND, /* (WO) 32-bit 0x30 */
	GPU_CONTROL__GPU_STATUS, /* (RO) 32-bit 0x34 */
	GPU_CONTROL__LATEST_FLUSH, /* (RO) 32-bit 0x38 */
	GPU_CONTROL__GPU_FAULTSTATUS, /* (RO) 32-bit 0x3C */
	GPU_CONTROL__GPU_FAULTADDRESS, /* (RO) 64-bit 0x40 */
	GPU_CONTROL__AFBC_FEATURES, /* (RO) 32-bit 0x4C */
	GPU_CONTROL__PWR_KEY, /* (WO) 32-bit 0x50 */
	GPU_CONTROL__PWR_OVERRIDE0, /* (RW) 32-bit 0x54 */
	GPU_CONTROL__PWR_OVERRIDE1, /* (RW) 32-bit 0x58 */
	GPU_CONTROL__PRFCNT_BASE, /* (RW) 64-bit 0x60 */
	GPU_CONTROL__PRFCNT_CONFIG, /* (RW) 32-bit 0x68 */
	GPU_CONTROL__PRFCNT_JM_EN, /* (RW) 32-bit 0x6C */
	GPU_CONTROL__PRFCNT_SHADER_EN, /* (RW) 32-bit 0x70 */
	GPU_CONTROL__PRFCNT_TILER_EN, /* (RW) 32-bit 0x74 */
	GPU_CONTROL__PRFCNT_MMU_L2_EN, /* (RW) 32-bit 0x7C */
	GPU_CONTROL__CYCLE_COUNT, /* (RO) 64-bit 0x90 */
	GPU_CONTROL__TIMESTAMP, /* (RO) 64-bit 0x98 */
	GPU_CONTROL__THREAD_MAX_THREADS, /* (RO) 32-bit 0xA0 */
	GPU_CONTROL__THREAD_MAX_WORKGROUP_SIZE, /* (RO) 32-bit 0xA4 */
	GPU_CONTROL__THREAD_MAX_BARRIER_SIZE, /* (RO) 32-bit 0xA8 */
	GPU_CONTROL__THREAD_FEATURES, /* (RO) 32-bit 0xAC */
	GPU_CONTROL__TEXTURE_FEATURES_0, /* (RO) 32-bit 0xB0 */
	GPU_CONTROL__TEXTURE_FEATURES_1, /* (RO) 32-bit 0xB4 */
	GPU_CONTROL__TEXTURE_FEATURES_2, /* (RO) 32-bit 0xB8 */
	GPU_CONTROL__JS0_FEATURES, /* (RO) 32-bit 0xC0 */
	GPU_CONTROL__JS1_FEATURES, /* (RO) 32-bit 0xC4 */
	GPU_CONTROL__JS2_FEATURES, /* (RO) 32-bit 0xC8 */
	GPU_CONTROL__JS3_FEATURES, /* (RO) 32-bit 0xCC */
	GPU_CONTROL__JS4_FEATURES, /* (RO) 32-bit 0xD0 */
	GPU_CONTROL__JS5_FEATURES, /* (RO) 32-bit 0xD4 */
	GPU_CONTROL__JS6_FEATURES, /* (RO) 32-bit 0xD8 */
	GPU_CONTROL__JS7_FEATURES, /* (RO) 32-bit 0xDC */
	GPU_CONTROL__JS8_FEATURES, /* (RO) 32-bit 0xE0 */
	GPU_CONTROL__JS9_FEATURES, /* (RO) 32-bit 0xE4 */
	GPU_CONTROL__JS10_FEATURES, /* (RO) 32-bit 0xE8 */
	GPU_CONTROL__JS11_FEATURES, /* (RO) 32-bit 0xEC */
	GPU_CONTROL__JS12_FEATURES, /* (RO) 32-bit 0xF0 */
	GPU_CONTROL__JS13_FEATURES, /* (RO) 32-bit 0xF4 */
	GPU_CONTROL__JS14_FEATURES, /* (RO) 32-bit 0xF8 */
	GPU_CONTROL__JS15_FEATURES, /* (RO) 32-bit 0xFC */
	GPU_CONTROL__SHADER_PRESENT, /* (RO) 64-bit 0x100 */
	GPU_CONTROL__TILER_PRESENT, /* (RO) 64-bit 0x110 */
	GPU_CONTROL__L2_PRESENT, /* (RO) 64-bit 0x120 */
	GPU_CONTROL__SHADER_READY, /* (RO) 64-bit 0x140 */
	GPU_CONTROL__TILER_READY, /* (RO) 64-bit 0x150 */
	GPU_CONTROL__L2_READY, /* (RO) 64-bit 0x160 */
	GPU_CONTROL__SHADER_PWRON, /* (WO) 64-bit 0x180 */
	GPU_CONTROL__TILER_PWRON, /* (WO) 64-bit 0x190 */
	GPU_CONTROL__L2_PWRON, /* (WO) 64-bit 0x1A0 */
	GPU_CONTROL__SHADER_PWROFF, /* (WO) 64-bit 0x1C0 */
	GPU_CONTROL__TILER_PWROFF, /* (WO) 64-bit 0x1D0 */
	GPU_CONTROL__L2_PWROFF, /* (WO) 64-bit 0x1E0 */
	GPU_CONTROL__SHADER_PWRTRANS, /* (RO) 64-bit 0x200 */
	GPU_CONTROL__TILER_PWRTRANS, /* (RO) 64-bit 0x210 */
	GPU_CONTROL__L2_PWRTRANS, /* (RO) 64-bit 0x220 */
	GPU_CONTROL__SHADER_PWRACTIVE, /* (RO) 64-bit 0x240 */
	GPU_CONTROL__TILER_PWRACTIVE, /* (RO) 64-bit 0x250 */
	GPU_CONTROL__L2_PWRACTIVE, /* (RO) 64-bit 0x260 */
	GPU_CONTROL__COHERENCY_FEATURES, /* (RO) 32-bit 0x300 */
	GPU_CONTROL__COHERENCY_ENABLE, /* (RW) 32-bit 0x304 */
	GPU_CONTROL__GPU_USER_INn, /* (RO) 32-bit 0x400 */
	GPU_CONTROL__GPU_USER_OUTn, /* (RW) 32-bit 0x500 */
	GPU_CONTROL__JM_CONFIG, /* (RW) 32-bit 0xF00 */
	GPU_CONTROL__SHADER_CONFIG, /* (RW) 32-bit 0xF04 */
	GPU_CONTROL__TILER_CONFIG, /* (RW) 32-bit 0xF08 */
	GPU_CONTROL__L2_MMU_CONFIG, /* (RW) 32-bit 0xF0C */
	JOB_CONTROL__JOB_IRQ_RAWSTAT, /* (RW) 32-bit 0x1000 */
	JOB_CONTROL__JOB_IRQ_CLEAR, /* (WO) 32-bit 0x1004 */
	JOB_CONTROL__JOB_IRQ_MASK, /* (RW) 32-bit 0x1008 */
	JOB_CONTROL__JOB_IRQ_STATUS, /* (RO) 32-bit 0x100C */
	JOB_CONTROL__JOB_IRQ_JS_STATE, /* (RO) 32-bit 0x1010 */
	JOB_CONTROL__JOB_IRQ_THROTTLE, /* (RW) 32-bit 0x1014 */
	JOB_CONTROL__EVENT_IRQ_RAWSTAT, /* (RW) 32-bit 0x1020 */
	JOB_CONTROL__EVENT_IRQ_CLEAR, /* (WO) 32-bit 0x1024 */
	JOB_CONTROL__EVENT_IRQ_MASK, /* (RW) 32-bit 0x1028 */
	JOB_CONTROL__EVENT_IRQ_STATUS, /* (RO) 32-bit 0x102C */
	JOB_CONTROL__JS0__HEAD, /* (RO) 64-bit 0x1800 */
	JOB_CONTROL__JS0__TAIL, /* (RO) 64-bit 0x1808 */
	JOB_CONTROL__JS0__AFFINITY, /* (RO) 64-bit 0x1810 */
	JOB_CONTROL__JS0__CONFIG, /* (RO) 32-bit 0x1818 */
	JOB_CONTROL__JS0__XAFFINITY, /* (RO) 32-bit 0x181C */
	JOB_CONTROL__JS0__COMMAND, /* (RW) 32-bit 0x1820 */
	JOB_CONTROL__JS0__STATUS, /* (RO) 32-bit 0x1824 */
	JOB_CONTROL__JS0__FLUSH_ID, /* (RO) 32-bit 0x1830 */
	JOB_CONTROL__JS0__EVENT_0, /* (RW) 32-bit 0x1834 */
	JOB_CONTROL__JS0__EVENT_1, /* (RW) 32-bit 0x1838 */
	JOB_CONTROL__JS0__EVENT_MASK, /* (RW) 32-bit 0x183C */
	JOB_CONTROL__JS0__HEAD_NEXT, /* (RW) 64-bit 0x1840 */
	JOB_CONTROL__JS0__TAIL_NEXT, /* (RW) 64-bit 0x1848 */
	JOB_CONTROL__JS0__AFFINITY_NEXT, /* (RW) 64-bit 0x1850 */
	JOB_CONTROL__JS0__CONFIG_NEXT, /* (RW) 32-bit 0x1858 */
	JOB_CONTROL__JS0__XAFFINITY_NEXT, /* (RW) 32-bit 0x185C */
	JOB_CONTROL__JS0__COMMAND_NEXT, /* (RW) 32-bit 0x1860 */
	JOB_CONTROL__JS0__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1870 */
	JOB_CONTROL__JS0__EVENT_MASK_NEXT, /* (RW) 32-bit 0x187C */
	JOB_CONTROL__JS1__HEAD, /* (RO) 64-bit 0x1880 */
	JOB_CONTROL__JS1__TAIL, /* (RO) 64-bit 0x1888 */
	JOB_CONTROL__JS1__AFFINITY, /* (RO) 64-bit 0x1890 */
	JOB_CONTROL__JS1__CONFIG, /* (RO) 32-bit 0x1898 */
	JOB_CONTROL__JS1__XAFFINITY, /* (RO) 32-bit 0x189C */
	JOB_CONTROL__JS1__COMMAND, /* (RW) 32-bit 0x18A0 */
	JOB_CONTROL__JS1__STATUS, /* (RO) 32-bit 0x18A4 */
	JOB_CONTROL__JS1__FLUSH_ID, /* (RO) 32-bit 0x18B0 */
	JOB_CONTROL__JS1__EVENT_0, /* (RW) 32-bit 0x18B4 */
	JOB_CONTROL__JS1__EVENT_1, /* (RW) 32-bit 0x18B8 */
	JOB_CONTROL__JS1__EVENT_MASK, /* (RW) 32-bit 0x18BC */
	JOB_CONTROL__JS1__HEAD_NEXT, /* (RW) 64-bit 0x18C0 */
	JOB_CONTROL__JS1__TAIL_NEXT, /* (RW) 64-bit 0x18C8 */
	JOB_CONTROL__JS1__AFFINITY_NEXT, /* (RW) 64-bit 0x18D0 */
	JOB_CONTROL__JS1__CONFIG_NEXT, /* (RW) 32-bit 0x18D8 */
	JOB_CONTROL__JS1__XAFFINITY_NEXT, /* (RW) 32-bit 0x18DC */
	JOB_CONTROL__JS1__COMMAND_NEXT, /* (RW) 32-bit 0x18E0 */
	JOB_CONTROL__JS1__FLUSH_ID_NEXT, /* (RW) 32-bit 0x18F0 */
	JOB_CONTROL__JS1__EVENT_MASK_NEXT, /* (RW) 32-bit 0x18FC */
	JOB_CONTROL__JS2__HEAD, /* (RO) 64-bit 0x1900 */
	JOB_CONTROL__JS2__TAIL, /* (RO) 64-bit 0x1908 */
	JOB_CONTROL__JS2__AFFINITY, /* (RO) 64-bit 0x1910 */
	JOB_CONTROL__JS2__CONFIG, /* (RO) 32-bit 0x1918 */
	JOB_CONTROL__JS2__XAFFINITY, /* (RO) 32-bit 0x191C */
	JOB_CONTROL__JS2__COMMAND, /* (RW) 32-bit 0x1920 */
	JOB_CONTROL__JS2__STATUS, /* (RO) 32-bit 0x1924 */
	JOB_CONTROL__JS2__FLUSH_ID, /* (RO) 32-bit 0x1930 */
	JOB_CONTROL__JS2__EVENT_0, /* (RW) 32-bit 0x1934 */
	JOB_CONTROL__JS2__EVENT_1, /* (RW) 32-bit 0x1938 */
	JOB_CONTROL__JS2__EVENT_MASK, /* (RW) 32-bit 0x193C */
	JOB_CONTROL__JS2__HEAD_NEXT, /* (RW) 64-bit 0x1940 */
	JOB_CONTROL__JS2__TAIL_NEXT, /* (RW) 64-bit 0x1948 */
	JOB_CONTROL__JS2__AFFINITY_NEXT, /* (RW) 64-bit 0x1950 */
	JOB_CONTROL__JS2__CONFIG_NEXT, /* (RW) 32-bit 0x1958 */
	JOB_CONTROL__JS2__XAFFINITY_NEXT, /* (RW) 32-bit 0x195C */
	JOB_CONTROL__JS2__COMMAND_NEXT, /* (RW) 32-bit 0x1960 */
	JOB_CONTROL__JS2__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1970 */
	JOB_CONTROL__JS2__EVENT_MASK_NEXT, /* (RW) 32-bit 0x197C */
	JOB_CONTROL__JS3__HEAD, /* (RO) 64-bit 0x1980 */
	JOB_CONTROL__JS3__TAIL, /* (RO) 64-bit 0x1988 */
	JOB_CONTROL__JS3__AFFINITY, /* (RO) 64-bit 0x1990 */
	JOB_CONTROL__JS3__CONFIG, /* (RO) 32-bit 0x1998 */
	JOB_CONTROL__JS3__XAFFINITY, /* (RO) 32-bit 0x199C */
	JOB_CONTROL__JS3__COMMAND, /* (RW) 32-bit 0x19A0 */
	JOB_CONTROL__JS3__STATUS, /* (RO) 32-bit 0x19A4 */
	JOB_CONTROL__JS3__FLUSH_ID, /* (RO) 32-bit 0x19B0 */
	JOB_CONTROL__JS3__EVENT_0, /* (RW) 32-bit 0x19B4 */
	JOB_CONTROL__JS3__EVENT_1, /* (RW) 32-bit 0x19B8 */
	JOB_CONTROL__JS3__EVENT_MASK, /* (RW) 32-bit 0x19BC */
	JOB_CONTROL__JS3__HEAD_NEXT, /* (RW) 64-bit 0x19C0 */
	JOB_CONTROL__JS3__TAIL_NEXT, /* (RW) 64-bit 0x19C8 */
	JOB_CONTROL__JS3__AFFINITY_NEXT, /* (RW) 64-bit 0x19D0 */
	JOB_CONTROL__JS3__CONFIG_NEXT, /* (RW) 32-bit 0x19D8 */
	JOB_CONTROL__JS3__XAFFINITY_NEXT, /* (RW) 32-bit 0x19DC */
	JOB_CONTROL__JS3__COMMAND_NEXT, /* (RW) 32-bit 0x19E0 */
	JOB_CONTROL__JS3__FLUSH_ID_NEXT, /* (RW) 32-bit 0x19F0 */
	JOB_CONTROL__JS3__EVENT_MASK_NEXT, /* (RW) 32-bit 0x19FC */
	JOB_CONTROL__JS4__HEAD, /* (RO) 64-bit 0x1A00 */
	JOB_CONTROL__JS4__TAIL, /* (RO) 64-bit 0x1A08 */
	JOB_CONTROL__JS4__AFFINITY, /* (RO) 64-bit 0x1A10 */
	JOB_CONTROL__JS4__CONFIG, /* (RO) 32-bit 0x1A18 */
	JOB_CONTROL__JS4__XAFFINITY, /* (RO) 32-bit 0x1A1C */
	JOB_CONTROL__JS4__COMMAND, /* (RW) 32-bit 0x1A20 */
	JOB_CONTROL__JS4__STATUS, /* (RO) 32-bit 0x1A24 */
	JOB_CONTROL__JS4__FLUSH_ID, /* (RO) 32-bit 0x1A30 */
	JOB_CONTROL__JS4__EVENT_0, /* (RW) 32-bit 0x1A34 */
	JOB_CONTROL__JS4__EVENT_1, /* (RW) 32-bit 0x1A38 */
	JOB_CONTROL__JS4__EVENT_MASK, /* (RW) 32-bit 0x1A3C */
	JOB_CONTROL__JS4__HEAD_NEXT, /* (RW) 64-bit 0x1A40 */
	JOB_CONTROL__JS4__TAIL_NEXT, /* (RW) 64-bit 0x1A48 */
	JOB_CONTROL__JS4__AFFINITY_NEXT, /* (RW) 64-bit 0x1A50 */
	JOB_CONTROL__JS4__CONFIG_NEXT, /* (RW) 32-bit 0x1A58 */
	JOB_CONTROL__JS4__XAFFINITY_NEXT, /* (RW) 32-bit 0x1A5C */
	JOB_CONTROL__JS4__COMMAND_NEXT, /* (RW) 32-bit 0x1A60 */
	JOB_CONTROL__JS4__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1A70 */
	JOB_CONTROL__JS4__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1A7C */
	JOB_CONTROL__JS5__HEAD, /* (RO) 64-bit 0x1A80 */
	JOB_CONTROL__JS5__TAIL, /* (RO) 64-bit 0x1A88 */
	JOB_CONTROL__JS5__AFFINITY, /* (RO) 64-bit 0x1A90 */
	JOB_CONTROL__JS5__CONFIG, /* (RO) 32-bit 0x1A98 */
	JOB_CONTROL__JS5__XAFFINITY, /* (RO) 32-bit 0x1A9C */
	JOB_CONTROL__JS5__COMMAND, /* (RW) 32-bit 0x1AA0 */
	JOB_CONTROL__JS5__STATUS, /* (RO) 32-bit 0x1AA4 */
	JOB_CONTROL__JS5__FLUSH_ID, /* (RO) 32-bit 0x1AB0 */
	JOB_CONTROL__JS5__EVENT_0, /* (RW) 32-bit 0x1AB4 */
	JOB_CONTROL__JS5__EVENT_1, /* (RW) 32-bit 0x1AB8 */
	JOB_CONTROL__JS5__EVENT_MASK, /* (RW) 32-bit 0x1ABC */
	JOB_CONTROL__JS5__HEAD_NEXT, /* (RW) 64-bit 0x1AC0 */
	JOB_CONTROL__JS5__TAIL_NEXT, /* (RW) 64-bit 0x1AC8 */
	JOB_CONTROL__JS5__AFFINITY_NEXT, /* (RW) 64-bit 0x1AD0 */
	JOB_CONTROL__JS5__CONFIG_NEXT, /* (RW) 32-bit 0x1AD8 */
	JOB_CONTROL__JS5__XAFFINITY_NEXT, /* (RW) 32-bit 0x1ADC */
	JOB_CONTROL__JS5__COMMAND_NEXT, /* (RW) 32-bit 0x1AE0 */
	JOB_CONTROL__JS5__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1AF0 */
	JOB_CONTROL__JS5__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1AFC */
	JOB_CONTROL__JS6__HEAD, /* (RO) 64-bit 0x1B00 */
	JOB_CONTROL__JS6__TAIL, /* (RO) 64-bit 0x1B08 */
	JOB_CONTROL__JS6__AFFINITY, /* (RO) 64-bit 0x1B10 */
	JOB_CONTROL__JS6__CONFIG, /* (RO) 32-bit 0x1B18 */
	JOB_CONTROL__JS6__XAFFINITY, /* (RO) 32-bit 0x1B1C */
	JOB_CONTROL__JS6__COMMAND, /* (RW) 32-bit 0x1B20 */
	JOB_CONTROL__JS6__STATUS, /* (RO) 32-bit 0x1B24 */
	JOB_CONTROL__JS6__FLUSH_ID, /* (RO) 32-bit 0x1B30 */
	JOB_CONTROL__JS6__EVENT_0, /* (RW) 32-bit 0x1B34 */
	JOB_CONTROL__JS6__EVENT_1, /* (RW) 32-bit 0x1B38 */
	JOB_CONTROL__JS6__EVENT_MASK, /* (RW) 32-bit 0x1B3C */
	JOB_CONTROL__JS6__HEAD_NEXT, /* (RW) 64-bit 0x1B40 */
	JOB_CONTROL__JS6__TAIL_NEXT, /* (RW) 64-bit 0x1B48 */
	JOB_CONTROL__JS6__AFFINITY_NEXT, /* (RW) 64-bit 0x1B50 */
	JOB_CONTROL__JS6__CONFIG_NEXT, /* (RW) 32-bit 0x1B58 */
	JOB_CONTROL__JS6__XAFFINITY_NEXT, /* (RW) 32-bit 0x1B5C */
	JOB_CONTROL__JS6__COMMAND_NEXT, /* (RW) 32-bit 0x1B60 */
	JOB_CONTROL__JS6__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1B70 */
	JOB_CONTROL__JS6__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1B7C */
	JOB_CONTROL__JS7__HEAD, /* (RO) 64-bit 0x1B80 */
	JOB_CONTROL__JS7__TAIL, /* (RO) 64-bit 0x1B88 */
	JOB_CONTROL__JS7__AFFINITY, /* (RO) 64-bit 0x1B90 */
	JOB_CONTROL__JS7__CONFIG, /* (RO) 32-bit 0x1B98 */
	JOB_CONTROL__JS7__XAFFINITY, /* (RO) 32-bit 0x1B9C */
	JOB_CONTROL__JS7__COMMAND, /* (RW) 32-bit 0x1BA0 */
	JOB_CONTROL__JS7__STATUS, /* (RO) 32-bit 0x1BA4 */
	JOB_CONTROL__JS7__FLUSH_ID, /* (RO) 32-bit 0x1BB0 */
	JOB_CONTROL__JS7__EVENT_0, /* (RW) 32-bit 0x1BB4 */
	JOB_CONTROL__JS7__EVENT_1, /* (RW) 32-bit 0x1BB8 */
	JOB_CONTROL__JS7__EVENT_MASK, /* (RW) 32-bit 0x1BBC */
	JOB_CONTROL__JS7__HEAD_NEXT, /* (RW) 64-bit 0x1BC0 */
	JOB_CONTROL__JS7__TAIL_NEXT, /* (RW) 64-bit 0x1BC8 */
	JOB_CONTROL__JS7__AFFINITY_NEXT, /* (RW) 64-bit 0x1BD0 */
	JOB_CONTROL__JS7__CONFIG_NEXT, /* (RW) 32-bit 0x1BD8 */
	JOB_CONTROL__JS7__XAFFINITY_NEXT, /* (RW) 32-bit 0x1BDC */
	JOB_CONTROL__JS7__COMMAND_NEXT, /* (RW) 32-bit 0x1BE0 */
	JOB_CONTROL__JS7__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1BF0 */
	JOB_CONTROL__JS7__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1BFC */
	JOB_CONTROL__JS8__HEAD, /* (RO) 64-bit 0x1C00 */
	JOB_CONTROL__JS8__TAIL, /* (RO) 64-bit 0x1C08 */
	JOB_CONTROL__JS8__AFFINITY, /* (RO) 64-bit 0x1C10 */
	JOB_CONTROL__JS8__CONFIG, /* (RO) 32-bit 0x1C18 */
	JOB_CONTROL__JS8__XAFFINITY, /* (RO) 32-bit 0x1C1C */
	JOB_CONTROL__JS8__COMMAND, /* (RW) 32-bit 0x1C20 */
	JOB_CONTROL__JS8__STATUS, /* (RO) 32-bit 0x1C24 */
	JOB_CONTROL__JS8__FLUSH_ID, /* (RO) 32-bit 0x1C30 */
	JOB_CONTROL__JS8__EVENT_0, /* (RW) 32-bit 0x1C34 */
	JOB_CONTROL__JS8__EVENT_1, /* (RW) 32-bit 0x1C38 */
	JOB_CONTROL__JS8__EVENT_MASK, /* (RW) 32-bit 0x1C3C */
	JOB_CONTROL__JS8__HEAD_NEXT, /* (RW) 64-bit 0x1C40 */
	JOB_CONTROL__JS8__TAIL_NEXT, /* (RW) 64-bit 0x1C48 */
	JOB_CONTROL__JS8__AFFINITY_NEXT, /* (RW) 64-bit 0x1C50 */
	JOB_CONTROL__JS8__CONFIG_NEXT, /* (RW) 32-bit 0x1C58 */
	JOB_CONTROL__JS8__XAFFINITY_NEXT, /* (RW) 32-bit 0x1C5C */
	JOB_CONTROL__JS8__COMMAND_NEXT, /* (RW) 32-bit 0x1C60 */
	JOB_CONTROL__JS8__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1C70 */
	JOB_CONTROL__JS8__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1C7C */
	JOB_CONTROL__JS9__HEAD, /* (RO) 64-bit 0x1C80 */
	JOB_CONTROL__JS9__TAIL, /* (RO) 64-bit 0x1C88 */
	JOB_CONTROL__JS9__AFFINITY, /* (RO) 64-bit 0x1C90 */
	JOB_CONTROL__JS9__CONFIG, /* (RO) 32-bit 0x1C98 */
	JOB_CONTROL__JS9__XAFFINITY, /* (RO) 32-bit 0x1C9C */
	JOB_CONTROL__JS9__COMMAND, /* (RW) 32-bit 0x1CA0 */
	JOB_CONTROL__JS9__STATUS, /* (RO) 32-bit 0x1CA4 */
	JOB_CONTROL__JS9__FLUSH_ID, /* (RO) 32-bit 0x1CB0 */
	JOB_CONTROL__JS9__EVENT_0, /* (RW) 32-bit 0x1CB4 */
	JOB_CONTROL__JS9__EVENT_1, /* (RW) 32-bit 0x1CB8 */
	JOB_CONTROL__JS9__EVENT_MASK, /* (RW) 32-bit 0x1CBC */
	JOB_CONTROL__JS9__HEAD_NEXT, /* (RW) 64-bit 0x1CC0 */
	JOB_CONTROL__JS9__TAIL_NEXT, /* (RW) 64-bit 0x1CC8 */
	JOB_CONTROL__JS9__AFFINITY_NEXT, /* (RW) 64-bit 0x1CD0 */
	JOB_CONTROL__JS9__CONFIG_NEXT, /* (RW) 32-bit 0x1CD8 */
	JOB_CONTROL__JS9__XAFFINITY_NEXT, /* (RW) 32-bit 0x1CDC */
	JOB_CONTROL__JS9__COMMAND_NEXT, /* (RW) 32-bit 0x1CE0 */
	JOB_CONTROL__JS9__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1CF0 */
	JOB_CONTROL__JS9__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1CFC */
	JOB_CONTROL__JS10__HEAD, /* (RO) 64-bit 0x1D00 */
	JOB_CONTROL__JS10__TAIL, /* (RO) 64-bit 0x1D08 */
	JOB_CONTROL__JS10__AFFINITY, /* (RO) 64-bit 0x1D10 */
	JOB_CONTROL__JS10__CONFIG, /* (RO) 32-bit 0x1D18 */
	JOB_CONTROL__JS10__XAFFINITY, /* (RO) 32-bit 0x1D1C */
	JOB_CONTROL__JS10__COMMAND, /* (RW) 32-bit 0x1D20 */
	JOB_CONTROL__JS10__STATUS, /* (RO) 32-bit 0x1D24 */
	JOB_CONTROL__JS10__FLUSH_ID, /* (RO) 32-bit 0x1D30 */
	JOB_CONTROL__JS10__EVENT_0, /* (RW) 32-bit 0x1D34 */
	JOB_CONTROL__JS10__EVENT_1, /* (RW) 32-bit 0x1D38 */
	JOB_CONTROL__JS10__EVENT_MASK, /* (RW) 32-bit 0x1D3C */
	JOB_CONTROL__JS10__HEAD_NEXT, /* (RW) 64-bit 0x1D40 */
	JOB_CONTROL__JS10__TAIL_NEXT, /* (RW) 64-bit 0x1D48 */
	JOB_CONTROL__JS10__AFFINITY_NEXT, /* (RW) 64-bit 0x1D50 */
	JOB_CONTROL__JS10__CONFIG_NEXT, /* (RW) 32-bit 0x1D58 */
	JOB_CONTROL__JS10__XAFFINITY_NEXT, /* (RW) 32-bit 0x1D5C */
	JOB_CONTROL__JS10__COMMAND_NEXT, /* (RW) 32-bit 0x1D60 */
	JOB_CONTROL__JS10__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1D70 */
	JOB_CONTROL__JS10__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1D7C */
	JOB_CONTROL__JS11__HEAD, /* (RO) 64-bit 0x1D80 */
	JOB_CONTROL__JS11__TAIL, /* (RO) 64-bit 0x1D88 */
	JOB_CONTROL__JS11__AFFINITY, /* (RO) 64-bit 0x1D90 */
	JOB_CONTROL__JS11__CONFIG, /* (RO) 32-bit 0x1D98 */
	JOB_CONTROL__JS11__XAFFINITY, /* (RO) 32-bit 0x1D9C */
	JOB_CONTROL__JS11__COMMAND, /* (RW) 32-bit 0x1DA0 */
	JOB_CONTROL__JS11__STATUS, /* (RO) 32-bit 0x1DA4 */
	JOB_CONTROL__JS11__FLUSH_ID, /* (RO) 32-bit 0x1DB0 */
	JOB_CONTROL__JS11__EVENT_0, /* (RW) 32-bit 0x1DB4 */
	JOB_CONTROL__JS11__EVENT_1, /* (RW) 32-bit 0x1DB8 */
	JOB_CONTROL__JS11__EVENT_MASK, /* (RW) 32-bit 0x1DBC */
	JOB_CONTROL__JS11__HEAD_NEXT, /* (RW) 64-bit 0x1DC0 */
	JOB_CONTROL__JS11__TAIL_NEXT, /* (RW) 64-bit 0x1DC8 */
	JOB_CONTROL__JS11__AFFINITY_NEXT, /* (RW) 64-bit 0x1DD0 */
	JOB_CONTROL__JS11__CONFIG_NEXT, /* (RW) 32-bit 0x1DD8 */
	JOB_CONTROL__JS11__XAFFINITY_NEXT, /* (RW) 32-bit 0x1DDC */
	JOB_CONTROL__JS11__COMMAND_NEXT, /* (RW) 32-bit 0x1DE0 */
	JOB_CONTROL__JS11__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1DF0 */
	JOB_CONTROL__JS11__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1DFC */
	JOB_CONTROL__JS12__HEAD, /* (RO) 64-bit 0x1E00 */
	JOB_CONTROL__JS12__TAIL, /* (RO) 64-bit 0x1E08 */
	JOB_CONTROL__JS12__AFFINITY, /* (RO) 64-bit 0x1E10 */
	JOB_CONTROL__JS12__CONFIG, /* (RO) 32-bit 0x1E18 */
	JOB_CONTROL__JS12__XAFFINITY, /* (RO) 32-bit 0x1E1C */
	JOB_CONTROL__JS12__COMMAND, /* (RW) 32-bit 0x1E20 */
	JOB_CONTROL__JS12__STATUS, /* (RO) 32-bit 0x1E24 */
	JOB_CONTROL__JS12__FLUSH_ID, /* (RO) 32-bit 0x1E30 */
	JOB_CONTROL__JS12__EVENT_0, /* (RW) 32-bit 0x1E34 */
	JOB_CONTROL__JS12__EVENT_1, /* (RW) 32-bit 0x1E38 */
	JOB_CONTROL__JS12__EVENT_MASK, /* (RW) 32-bit 0x1E3C */
	JOB_CONTROL__JS12__HEAD_NEXT, /* (RW) 64-bit 0x1E40 */
	JOB_CONTROL__JS12__TAIL_NEXT, /* (RW) 64-bit 0x1E48 */
	JOB_CONTROL__JS12__AFFINITY_NEXT, /* (RW) 64-bit 0x1E50 */
	JOB_CONTROL__JS12__CONFIG_NEXT, /* (RW) 32-bit 0x1E58 */
	JOB_CONTROL__JS12__XAFFINITY_NEXT, /* (RW) 32-bit 0x1E5C */
	JOB_CONTROL__JS12__COMMAND_NEXT, /* (RW) 32-bit 0x1E60 */
	JOB_CONTROL__JS12__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1E70 */
	JOB_CONTROL__JS12__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1E7C */
	JOB_CONTROL__JS13__HEAD, /* (RO) 64-bit 0x1E80 */
	JOB_CONTROL__JS13__TAIL, /* (RO) 64-bit 0x1E88 */
	JOB_CONTROL__JS13__AFFINITY, /* (RO) 64-bit 0x1E90 */
	JOB_CONTROL__JS13__CONFIG, /* (RO) 32-bit 0x1E98 */
	JOB_CONTROL__JS13__XAFFINITY, /* (RO) 32-bit 0x1E9C */
	JOB_CONTROL__JS13__COMMAND, /* (RW) 32-bit 0x1EA0 */
	JOB_CONTROL__JS13__STATUS, /* (RO) 32-bit 0x1EA4 */
	JOB_CONTROL__JS13__FLUSH_ID, /* (RO) 32-bit 0x1EB0 */
	JOB_CONTROL__JS13__EVENT_0, /* (RW) 32-bit 0x1EB4 */
	JOB_CONTROL__JS13__EVENT_1, /* (RW) 32-bit 0x1EB8 */
	JOB_CONTROL__JS13__EVENT_MASK, /* (RW) 32-bit 0x1EBC */
	JOB_CONTROL__JS13__HEAD_NEXT, /* (RW) 64-bit 0x1EC0 */
	JOB_CONTROL__JS13__TAIL_NEXT, /* (RW) 64-bit 0x1EC8 */
	JOB_CONTROL__JS13__AFFINITY_NEXT, /* (RW) 64-bit 0x1ED0 */
	JOB_CONTROL__JS13__CONFIG_NEXT, /* (RW) 32-bit 0x1ED8 */
	JOB_CONTROL__JS13__XAFFINITY_NEXT, /* (RW) 32-bit 0x1EDC */
	JOB_CONTROL__JS13__COMMAND_NEXT, /* (RW) 32-bit 0x1EE0 */
	JOB_CONTROL__JS13__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1EF0 */
	JOB_CONTROL__JS13__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1EFC */
	JOB_CONTROL__JS14__HEAD, /* (RO) 64-bit 0x1F00 */
	JOB_CONTROL__JS14__TAIL, /* (RO) 64-bit 0x1F08 */
	JOB_CONTROL__JS14__AFFINITY, /* (RO) 64-bit 0x1F10 */
	JOB_CONTROL__JS14__CONFIG, /* (RO) 32-bit 0x1F18 */
	JOB_CONTROL__JS14__XAFFINITY, /* (RO) 32-bit 0x1F1C */
	JOB_CONTROL__JS14__COMMAND, /* (RW) 32-bit 0x1F20 */
	JOB_CONTROL__JS14__STATUS, /* (RO) 32-bit 0x1F24 */
	JOB_CONTROL__JS14__FLUSH_ID, /* (RO) 32-bit 0x1F30 */
	JOB_CONTROL__JS14__EVENT_0, /* (RW) 32-bit 0x1F34 */
	JOB_CONTROL__JS14__EVENT_1, /* (RW) 32-bit 0x1F38 */
	JOB_CONTROL__JS14__EVENT_MASK, /* (RW) 32-bit 0x1F3C */
	JOB_CONTROL__JS14__HEAD_NEXT, /* (RW) 64-bit 0x1F40 */
	JOB_CONTROL__JS14__TAIL_NEXT, /* (RW) 64-bit 0x1F48 */
	JOB_CONTROL__JS14__AFFINITY_NEXT, /* (RW) 64-bit 0x1F50 */
	JOB_CONTROL__JS14__CONFIG_NEXT, /* (RW) 32-bit 0x1F58 */
	JOB_CONTROL__JS14__XAFFINITY_NEXT, /* (RW) 32-bit 0x1F5C */
	JOB_CONTROL__JS14__COMMAND_NEXT, /* (RW) 32-bit 0x1F60 */
	JOB_CONTROL__JS14__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1F70 */
	JOB_CONTROL__JS14__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1F7C */
	JOB_CONTROL__JS15__HEAD, /* (RO) 64-bit 0x1F80 */
	JOB_CONTROL__JS15__TAIL, /* (RO) 64-bit 0x1F88 */
	JOB_CONTROL__JS15__AFFINITY, /* (RO) 64-bit 0x1F90 */
	JOB_CONTROL__JS15__CONFIG, /* (RO) 32-bit 0x1F98 */
	JOB_CONTROL__JS15__XAFFINITY, /* (RO) 32-bit 0x1F9C */
	JOB_CONTROL__JS15__COMMAND, /* (RW) 32-bit 0x1FA0 */
	JOB_CONTROL__JS15__STATUS, /* (RO) 32-bit 0x1FA4 */
	JOB_CONTROL__JS15__FLUSH_ID, /* (RO) 32-bit 0x1FB0 */
	JOB_CONTROL__JS15__EVENT_0, /* (RW) 32-bit 0x1FB4 */
	JOB_CONTROL__JS15__EVENT_1, /* (RW) 32-bit 0x1FB8 */
	JOB_CONTROL__JS15__EVENT_MASK, /* (RW) 32-bit 0x1FBC */
	JOB_CONTROL__JS15__HEAD_NEXT, /* (RW) 64-bit 0x1FC0 */
	JOB_CONTROL__JS15__TAIL_NEXT, /* (RW) 64-bit 0x1FC8 */
	JOB_CONTROL__JS15__AFFINITY_NEXT, /* (RW) 64-bit 0x1FD0 */
	JOB_CONTROL__JS15__CONFIG_NEXT, /* (RW) 32-bit 0x1FD8 */
	JOB_CONTROL__JS15__XAFFINITY_NEXT, /* (RW) 32-bit 0x1FDC */
	JOB_CONTROL__JS15__COMMAND_NEXT, /* (RW) 32-bit 0x1FE0 */
	JOB_CONTROL__JS15__FLUSH_ID_NEXT, /* (RW) 32-bit 0x1FF0 */
	JOB_CONTROL__JS15__EVENT_MASK_NEXT, /* (RW) 32-bit 0x1FFC */
	MMU_STAGE1__ST1MMU__IRQ_RAWSTAT, /* (RW) 32-bit 0x2000 */
	MMU_STAGE1__ST1MMU__IRQ_CLEAR, /* (WO) 32-bit 0x2004 */
	MMU_STAGE1__ST1MMU__IRQ_MASK, /* (RW) 32-bit 0x2008 */
	MMU_STAGE1__ST1MMU__IRQ_STATUS, /* (RO) 32-bit 0x200C */
	MMU_STAGE1__ST1MMU__AS0__TRANSTAB, /* (RW) 64-bit 0x2400 */
	MMU_STAGE1__ST1MMU__AS0__MEMATTR, /* (RW) 64-bit 0x2408 */
	MMU_STAGE1__ST1MMU__AS0__LOCKADDR, /* (RW) 64-bit 0x2410 */
	MMU_STAGE1__ST1MMU__AS0__COMMAND, /* (WO) 32-bit 0x2418 */
	MMU_STAGE1__ST1MMU__AS0__FAULTSTATUS, /* (RO) 32-bit 0x241C */
	MMU_STAGE1__ST1MMU__AS0__FAULTADDRESS, /* (RO) 64-bit 0x2420 */
	MMU_STAGE1__ST1MMU__AS0__STATUS, /* (RO) 32-bit 0x2428 */
	MMU_STAGE1__ST1MMU__AS0__TRANSCFG, /* (RW) 64-bit 0x2430 */
	MMU_STAGE1__ST1MMU__AS0__FAULTEXTRA, /* (RO) 64-bit 0x2438 */
	MMU_STAGE1__ST1MMU__AS1__TRANSTAB, /* (RW) 64-bit 0x2440 */
	MMU_STAGE1__ST1MMU__AS1__MEMATTR, /* (RW) 64-bit 0x2448 */
	MMU_STAGE1__ST1MMU__AS1__LOCKADDR, /* (RW) 64-bit 0x2450 */
	MMU_STAGE1__ST1MMU__AS1__COMMAND, /* (WO) 32-bit 0x2458 */
	MMU_STAGE1__ST1MMU__AS1__FAULTSTATUS, /* (RO) 32-bit 0x245C */
	MMU_STAGE1__ST1MMU__AS1__FAULTADDRESS, /* (RO) 64-bit 0x2460 */
	MMU_STAGE1__ST1MMU__AS1__STATUS, /* (RO) 32-bit 0x2468 */
	MMU_STAGE1__ST1MMU__AS1__TRANSCFG, /* (RW) 64-bit 0x2470 */
	MMU_STAGE1__ST1MMU__AS1__FAULTEXTRA, /* (RO) 64-bit 0x2478 */
	MMU_STAGE1__ST1MMU__AS2__TRANSTAB, /* (RW) 64-bit 0x2480 */
	MMU_STAGE1__ST1MMU__AS2__MEMATTR, /* (RW) 64-bit 0x2488 */
	MMU_STAGE1__ST1MMU__AS2__LOCKADDR, /* (RW) 64-bit 0x2490 */
	MMU_STAGE1__ST1MMU__AS2__COMMAND, /* (WO) 32-bit 0x2498 */
	MMU_STAGE1__ST1MMU__AS2__FAULTSTATUS, /* (RO) 32-bit 0x249C */
	MMU_STAGE1__ST1MMU__AS2__FAULTADDRESS, /* (RO) 64-bit 0x24A0 */
	MMU_STAGE1__ST1MMU__AS2__STATUS, /* (RO) 32-bit 0x24A8 */
	MMU_STAGE1__ST1MMU__AS2__TRANSCFG, /* (RW) 64-bit 0x24B0 */
	MMU_STAGE1__ST1MMU__AS2__FAULTEXTRA, /* (RO) 64-bit 0x24B8 */
	MMU_STAGE1__ST1MMU__AS3__TRANSTAB, /* (RW) 64-bit 0x24C0 */
	MMU_STAGE1__ST1MMU__AS3__MEMATTR, /* (RW) 64-bit 0x24C8 */
	MMU_STAGE1__ST1MMU__AS3__LOCKADDR, /* (RW) 64-bit 0x24D0 */
	MMU_STAGE1__ST1MMU__AS3__COMMAND, /* (WO) 32-bit 0x24D8 */
	MMU_STAGE1__ST1MMU__AS3__FAULTSTATUS, /* (RO) 32-bit 0x24DC */
	MMU_STAGE1__ST1MMU__AS3__FAULTADDRESS, /* (RO) 64-bit 0x24E0 */
	MMU_STAGE1__ST1MMU__AS3__STATUS, /* (RO) 32-bit 0x24E8 */
	MMU_STAGE1__ST1MMU__AS3__TRANSCFG, /* (RW) 64-bit 0x24F0 */
	MMU_STAGE1__ST1MMU__AS3__FAULTEXTRA, /* (RO) 64-bit 0x24F8 */
	MMU_STAGE1__ST1MMU__AS4__TRANSTAB, /* (RW) 64-bit 0x2500 */
	MMU_STAGE1__ST1MMU__AS4__MEMATTR, /* (RW) 64-bit 0x2508 */
	MMU_STAGE1__ST1MMU__AS4__LOCKADDR, /* (RW) 64-bit 0x2510 */
	MMU_STAGE1__ST1MMU__AS4__COMMAND, /* (WO) 32-bit 0x2518 */
	MMU_STAGE1__ST1MMU__AS4__FAULTSTATUS, /* (RO) 32-bit 0x251C */
	MMU_STAGE1__ST1MMU__AS4__FAULTADDRESS, /* (RO) 64-bit 0x2520 */
	MMU_STAGE1__ST1MMU__AS4__STATUS, /* (RO) 32-bit 0x2528 */
	MMU_STAGE1__ST1MMU__AS4__TRANSCFG, /* (RW) 64-bit 0x2530 */
	MMU_STAGE1__ST1MMU__AS4__FAULTEXTRA, /* (RO) 64-bit 0x2538 */
	MMU_STAGE1__ST1MMU__AS5__TRANSTAB, /* (RW) 64-bit 0x2540 */
	MMU_STAGE1__ST1MMU__AS5__MEMATTR, /* (RW) 64-bit 0x2548 */
	MMU_STAGE1__ST1MMU__AS5__LOCKADDR, /* (RW) 64-bit 0x2550 */
	MMU_STAGE1__ST1MMU__AS5__COMMAND, /* (WO) 32-bit 0x2558 */
	MMU_STAGE1__ST1MMU__AS5__FAULTSTATUS, /* (RO) 32-bit 0x255C */
	MMU_STAGE1__ST1MMU__AS5__FAULTADDRESS, /* (RO) 64-bit 0x2560 */
	MMU_STAGE1__ST1MMU__AS5__STATUS, /* (RO) 32-bit 0x2568 */
	MMU_STAGE1__ST1MMU__AS5__TRANSCFG, /* (RW) 64-bit 0x2570 */
	MMU_STAGE1__ST1MMU__AS5__FAULTEXTRA, /* (RO) 64-bit 0x2578 */
	MMU_STAGE1__ST1MMU__AS6__TRANSTAB, /* (RW) 64-bit 0x2580 */
	MMU_STAGE1__ST1MMU__AS6__MEMATTR, /* (RW) 64-bit 0x2588 */
	MMU_STAGE1__ST1MMU__AS6__LOCKADDR, /* (RW) 64-bit 0x2590 */
	MMU_STAGE1__ST1MMU__AS6__COMMAND, /* (WO) 32-bit 0x2598 */
	MMU_STAGE1__ST1MMU__AS6__FAULTSTATUS, /* (RO) 32-bit 0x259C */
	MMU_STAGE1__ST1MMU__AS6__FAULTADDRESS, /* (RO) 64-bit 0x25A0 */
	MMU_STAGE1__ST1MMU__AS6__STATUS, /* (RO) 32-bit 0x25A8 */
	MMU_STAGE1__ST1MMU__AS6__TRANSCFG, /* (RW) 64-bit 0x25B0 */
	MMU_STAGE1__ST1MMU__AS6__FAULTEXTRA, /* (RO) 64-bit 0x25B8 */
	MMU_STAGE1__ST1MMU__AS7__TRANSTAB, /* (RW) 64-bit 0x25C0 */
	MMU_STAGE1__ST1MMU__AS7__MEMATTR, /* (RW) 64-bit 0x25C8 */
	MMU_STAGE1__ST1MMU__AS7__LOCKADDR, /* (RW) 64-bit 0x25D0 */
	MMU_STAGE1__ST1MMU__AS7__COMMAND, /* (WO) 32-bit 0x25D8 */
	MMU_STAGE1__ST1MMU__AS7__FAULTSTATUS, /* (RO) 32-bit 0x25DC */
	MMU_STAGE1__ST1MMU__AS7__FAULTADDRESS, /* (RO) 64-bit 0x25E0 */
	MMU_STAGE1__ST1MMU__AS7__STATUS, /* (RO) 32-bit 0x25E8 */
	MMU_STAGE1__ST1MMU__AS7__TRANSCFG, /* (RW) 64-bit 0x25F0 */
	MMU_STAGE1__ST1MMU__AS7__FAULTEXTRA, /* (RO) 64-bit 0x25F8 */
	MMU_STAGE1__ST1MMU__AS8__TRANSTAB, /* (RW) 64-bit 0x2600 */
	MMU_STAGE1__ST1MMU__AS8__MEMATTR, /* (RW) 64-bit 0x2608 */
	MMU_STAGE1__ST1MMU__AS8__LOCKADDR, /* (RW) 64-bit 0x2610 */
	MMU_STAGE1__ST1MMU__AS8__COMMAND, /* (WO) 32-bit 0x2618 */
	MMU_STAGE1__ST1MMU__AS8__FAULTSTATUS, /* (RO) 32-bit 0x261C */
	MMU_STAGE1__ST1MMU__AS8__FAULTADDRESS, /* (RO) 64-bit 0x2620 */
	MMU_STAGE1__ST1MMU__AS8__STATUS, /* (RO) 32-bit 0x2628 */
	MMU_STAGE1__ST1MMU__AS8__TRANSCFG, /* (RW) 64-bit 0x2630 */
	MMU_STAGE1__ST1MMU__AS8__FAULTEXTRA, /* (RO) 64-bit 0x2638 */
	MMU_STAGE1__ST1MMU__AS9__TRANSTAB, /* (RW) 64-bit 0x2640 */
	MMU_STAGE1__ST1MMU__AS9__MEMATTR, /* (RW) 64-bit 0x2648 */
	MMU_STAGE1__ST1MMU__AS9__LOCKADDR, /* (RW) 64-bit 0x2650 */
	MMU_STAGE1__ST1MMU__AS9__COMMAND, /* (WO) 32-bit 0x2658 */
	MMU_STAGE1__ST1MMU__AS9__FAULTSTATUS, /* (RO) 32-bit 0x265C */
	MMU_STAGE1__ST1MMU__AS9__FAULTADDRESS, /* (RO) 64-bit 0x2660 */
	MMU_STAGE1__ST1MMU__AS9__STATUS, /* (RO) 32-bit 0x2668 */
	MMU_STAGE1__ST1MMU__AS9__TRANSCFG, /* (RW) 64-bit 0x2670 */
	MMU_STAGE1__ST1MMU__AS9__FAULTEXTRA, /* (RO) 64-bit 0x2678 */
	MMU_STAGE1__ST1MMU__AS10__TRANSTAB, /* (RW) 64-bit 0x2680 */
	MMU_STAGE1__ST1MMU__AS10__MEMATTR, /* (RW) 64-bit 0x2688 */
	MMU_STAGE1__ST1MMU__AS10__LOCKADDR, /* (RW) 64-bit 0x2690 */
	MMU_STAGE1__ST1MMU__AS10__COMMAND, /* (WO) 32-bit 0x2698 */
	MMU_STAGE1__ST1MMU__AS10__FAULTSTATUS, /* (RO) 32-bit 0x269C */
	MMU_STAGE1__ST1MMU__AS10__FAULTADDRESS, /* (RO) 64-bit 0x26A0 */
	MMU_STAGE1__ST1MMU__AS10__STATUS, /* (RO) 32-bit 0x26A8 */
	MMU_STAGE1__ST1MMU__AS10__TRANSCFG, /* (RW) 64-bit 0x26B0 */
	MMU_STAGE1__ST1MMU__AS10__FAULTEXTRA, /* (RO) 64-bit 0x26B8 */
	MMU_STAGE1__ST1MMU__AS11__TRANSTAB, /* (RW) 64-bit 0x26C0 */
	MMU_STAGE1__ST1MMU__AS11__MEMATTR, /* (RW) 64-bit 0x26C8 */
	MMU_STAGE1__ST1MMU__AS11__LOCKADDR, /* (RW) 64-bit 0x26D0 */
	MMU_STAGE1__ST1MMU__AS11__COMMAND, /* (WO) 32-bit 0x26D8 */
	MMU_STAGE1__ST1MMU__AS11__FAULTSTATUS, /* (RO) 32-bit 0x26DC */
	MMU_STAGE1__ST1MMU__AS11__FAULTADDRESS, /* (RO) 64-bit 0x26E0 */
	MMU_STAGE1__ST1MMU__AS11__STATUS, /* (RO) 32-bit 0x26E8 */
	MMU_STAGE1__ST1MMU__AS11__TRANSCFG, /* (RW) 64-bit 0x26F0 */
	MMU_STAGE1__ST1MMU__AS11__FAULTEXTRA, /* (RO) 64-bit 0x26F8 */
	MMU_STAGE1__ST1MMU__AS12__TRANSTAB, /* (RW) 64-bit 0x2700 */
	MMU_STAGE1__ST1MMU__AS12__MEMATTR, /* (RW) 64-bit 0x2708 */
	MMU_STAGE1__ST1MMU__AS12__LOCKADDR, /* (RW) 64-bit 0x2710 */
	MMU_STAGE1__ST1MMU__AS12__COMMAND, /* (WO) 32-bit 0x2718 */
	MMU_STAGE1__ST1MMU__AS12__FAULTSTATUS, /* (RO) 32-bit 0x271C */
	MMU_STAGE1__ST1MMU__AS12__FAULTADDRESS, /* (RO) 64-bit 0x2720 */
	MMU_STAGE1__ST1MMU__AS12__STATUS, /* (RO) 32-bit 0x2728 */
	MMU_STAGE1__ST1MMU__AS12__TRANSCFG, /* (RW) 64-bit 0x2730 */
	MMU_STAGE1__ST1MMU__AS12__FAULTEXTRA, /* (RO) 64-bit 0x2738 */
	MMU_STAGE1__ST1MMU__AS13__TRANSTAB, /* (RW) 64-bit 0x2740 */
	MMU_STAGE1__ST1MMU__AS13__MEMATTR, /* (RW) 64-bit 0x2748 */
	MMU_STAGE1__ST1MMU__AS13__LOCKADDR, /* (RW) 64-bit 0x2750 */
	MMU_STAGE1__ST1MMU__AS13__COMMAND, /* (WO) 32-bit 0x2758 */
	MMU_STAGE1__ST1MMU__AS13__FAULTSTATUS, /* (RO) 32-bit 0x275C */
	MMU_STAGE1__ST1MMU__AS13__FAULTADDRESS, /* (RO) 64-bit 0x2760 */
	MMU_STAGE1__ST1MMU__AS13__STATUS, /* (RO) 32-bit 0x2768 */
	MMU_STAGE1__ST1MMU__AS13__TRANSCFG, /* (RW) 64-bit 0x2770 */
	MMU_STAGE1__ST1MMU__AS13__FAULTEXTRA, /* (RO) 64-bit 0x2778 */
	MMU_STAGE1__ST1MMU__AS14__TRANSTAB, /* (RW) 64-bit 0x2780 */
	MMU_STAGE1__ST1MMU__AS14__MEMATTR, /* (RW) 64-bit 0x2788 */
	MMU_STAGE1__ST1MMU__AS14__LOCKADDR, /* (RW) 64-bit 0x2790 */
	MMU_STAGE1__ST1MMU__AS14__COMMAND, /* (WO) 32-bit 0x2798 */
	MMU_STAGE1__ST1MMU__AS14__FAULTSTATUS, /* (RO) 32-bit 0x279C */
	MMU_STAGE1__ST1MMU__AS14__FAULTADDRESS, /* (RO) 64-bit 0x27A0 */
	MMU_STAGE1__ST1MMU__AS14__STATUS, /* (RO) 32-bit 0x27A8 */
	MMU_STAGE1__ST1MMU__AS14__TRANSCFG, /* (RW) 64-bit 0x27B0 */
	MMU_STAGE1__ST1MMU__AS14__FAULTEXTRA, /* (RO) 64-bit 0x27B8 */
	MMU_STAGE1__ST1MMU__AS15__TRANSTAB, /* (RW) 64-bit 0x27C0 */
	MMU_STAGE1__ST1MMU__AS15__MEMATTR, /* (RW) 64-bit 0x27C8 */
	MMU_STAGE1__ST1MMU__AS15__LOCKADDR, /* (RW) 64-bit 0x27D0 */
	MMU_STAGE1__ST1MMU__AS15__COMMAND, /* (WO) 32-bit 0x27D8 */
	MMU_STAGE1__ST1MMU__AS15__FAULTSTATUS, /* (RO) 32-bit 0x27DC */
	MMU_STAGE1__ST1MMU__AS15__FAULTADDRESS, /* (RO) 64-bit 0x27E0 */
	MMU_STAGE1__ST1MMU__AS15__STATUS, /* (RO) 32-bit 0x27E8 */
	MMU_STAGE1__ST1MMU__AS15__TRANSCFG, /* (RW) 64-bit 0x27F0 */
	MMU_STAGE1__ST1MMU__AS15__FAULTEXTRA, /* (RO) 64-bit 0x27F8 */
	MMU_STAGE2__ST2MMU__IRQ_RAWSTAT, /* (RW) 32-bit 0x10000 */
	MMU_STAGE2__ST2MMU__IRQ_CLEAR, /* (WO) 32-bit 0x10004 */
	MMU_STAGE2__ST2MMU__IRQ_MASK, /* (RW) 32-bit 0x10008 */
	MMU_STAGE2__ST2MMU__IRQ_STATUS, /* (RO) 32-bit 0x1000C */
	MMU_STAGE2__ST2MMU__AS0__TRANSTAB, /* (RW) 64-bit 0x10400 */
	MMU_STAGE2__ST2MMU__AS0__MEMATTR, /* (RW) 64-bit 0x10408 */
	MMU_STAGE2__ST2MMU__AS0__LOCKADDR, /* (RW) 64-bit 0x10410 */
	MMU_STAGE2__ST2MMU__AS0__COMMAND, /* (WO) 32-bit 0x10418 */
	MMU_STAGE2__ST2MMU__AS0__FAULTSTATUS, /* (RO) 32-bit 0x1041C */
	MMU_STAGE2__ST2MMU__AS0__FAULTADDRESS, /* (RO) 64-bit 0x10420 */
	MMU_STAGE2__ST2MMU__AS0__STATUS, /* (RO) 32-bit 0x10428 */
	MMU_STAGE2__ST2MMU__AS0__TRANSCFG, /* (RW) 64-bit 0x10430 */
	MMU_STAGE2__ST2MMU__AS0__FAULTEXTRA, /* (RO) 64-bit 0x10438 */
	MMU_STAGE2__ST2MMU__AS1__TRANSTAB, /* (RW) 64-bit 0x10440 */
	MMU_STAGE2__ST2MMU__AS1__MEMATTR, /* (RW) 64-bit 0x10448 */
	MMU_STAGE2__ST2MMU__AS1__LOCKADDR, /* (RW) 64-bit 0x10450 */
	MMU_STAGE2__ST2MMU__AS1__COMMAND, /* (WO) 32-bit 0x10458 */
	MMU_STAGE2__ST2MMU__AS1__FAULTSTATUS, /* (RO) 32-bit 0x1045C */
	MMU_STAGE2__ST2MMU__AS1__FAULTADDRESS, /* (RO) 64-bit 0x10460 */
	MMU_STAGE2__ST2MMU__AS1__STATUS, /* (RO) 32-bit 0x10468 */
	MMU_STAGE2__ST2MMU__AS1__TRANSCFG, /* (RW) 64-bit 0x10470 */
	MMU_STAGE2__ST2MMU__AS1__FAULTEXTRA, /* (RO) 64-bit 0x10478 */
	MMU_STAGE2__ST2MMU__AS2__TRANSTAB, /* (RW) 64-bit 0x10480 */
	MMU_STAGE2__ST2MMU__AS2__MEMATTR, /* (RW) 64-bit 0x10488 */
	MMU_STAGE2__ST2MMU__AS2__LOCKADDR, /* (RW) 64-bit 0x10490 */
	MMU_STAGE2__ST2MMU__AS2__COMMAND, /* (WO) 32-bit 0x10498 */
	MMU_STAGE2__ST2MMU__AS2__FAULTSTATUS, /* (RO) 32-bit 0x1049C */
	MMU_STAGE2__ST2MMU__AS2__FAULTADDRESS, /* (RO) 64-bit 0x104A0 */
	MMU_STAGE2__ST2MMU__AS2__STATUS, /* (RO) 32-bit 0x104A8 */
	MMU_STAGE2__ST2MMU__AS2__TRANSCFG, /* (RW) 64-bit 0x104B0 */
	MMU_STAGE2__ST2MMU__AS2__FAULTEXTRA, /* (RO) 64-bit 0x104B8 */
	MMU_STAGE2__ST2MMU__AS3__TRANSTAB, /* (RW) 64-bit 0x104C0 */
	MMU_STAGE2__ST2MMU__AS3__MEMATTR, /* (RW) 64-bit 0x104C8 */
	MMU_STAGE2__ST2MMU__AS3__LOCKADDR, /* (RW) 64-bit 0x104D0 */
	MMU_STAGE2__ST2MMU__AS3__COMMAND, /* (WO) 32-bit 0x104D8 */
	MMU_STAGE2__ST2MMU__AS3__FAULTSTATUS, /* (RO) 32-bit 0x104DC */
	MMU_STAGE2__ST2MMU__AS3__FAULTADDRESS, /* (RO) 64-bit 0x104E0 */
	MMU_STAGE2__ST2MMU__AS3__STATUS, /* (RO) 32-bit 0x104E8 */
	MMU_STAGE2__ST2MMU__AS3__TRANSCFG, /* (RW) 64-bit 0x104F0 */
	MMU_STAGE2__ST2MMU__AS3__FAULTEXTRA, /* (RO) 64-bit 0x104F8 */
	MMU_STAGE2__ST2MMU__AS4__TRANSTAB, /* (RW) 64-bit 0x10500 */
	MMU_STAGE2__ST2MMU__AS4__MEMATTR, /* (RW) 64-bit 0x10508 */
	MMU_STAGE2__ST2MMU__AS4__LOCKADDR, /* (RW) 64-bit 0x10510 */
	MMU_STAGE2__ST2MMU__AS4__COMMAND, /* (WO) 32-bit 0x10518 */
	MMU_STAGE2__ST2MMU__AS4__FAULTSTATUS, /* (RO) 32-bit 0x1051C */
	MMU_STAGE2__ST2MMU__AS4__FAULTADDRESS, /* (RO) 64-bit 0x10520 */
	MMU_STAGE2__ST2MMU__AS4__STATUS, /* (RO) 32-bit 0x10528 */
	MMU_STAGE2__ST2MMU__AS4__TRANSCFG, /* (RW) 64-bit 0x10530 */
	MMU_STAGE2__ST2MMU__AS4__FAULTEXTRA, /* (RO) 64-bit 0x10538 */
	MMU_STAGE2__ST2MMU__AS5__TRANSTAB, /* (RW) 64-bit 0x10540 */
	MMU_STAGE2__ST2MMU__AS5__MEMATTR, /* (RW) 64-bit 0x10548 */
	MMU_STAGE2__ST2MMU__AS5__LOCKADDR, /* (RW) 64-bit 0x10550 */
	MMU_STAGE2__ST2MMU__AS5__COMMAND, /* (WO) 32-bit 0x10558 */
	MMU_STAGE2__ST2MMU__AS5__FAULTSTATUS, /* (RO) 32-bit 0x1055C */
	MMU_STAGE2__ST2MMU__AS5__FAULTADDRESS, /* (RO) 64-bit 0x10560 */
	MMU_STAGE2__ST2MMU__AS5__STATUS, /* (RO) 32-bit 0x10568 */
	MMU_STAGE2__ST2MMU__AS5__TRANSCFG, /* (RW) 64-bit 0x10570 */
	MMU_STAGE2__ST2MMU__AS5__FAULTEXTRA, /* (RO) 64-bit 0x10578 */
	MMU_STAGE2__ST2MMU__AS6__TRANSTAB, /* (RW) 64-bit 0x10580 */
	MMU_STAGE2__ST2MMU__AS6__MEMATTR, /* (RW) 64-bit 0x10588 */
	MMU_STAGE2__ST2MMU__AS6__LOCKADDR, /* (RW) 64-bit 0x10590 */
	MMU_STAGE2__ST2MMU__AS6__COMMAND, /* (WO) 32-bit 0x10598 */
	MMU_STAGE2__ST2MMU__AS6__FAULTSTATUS, /* (RO) 32-bit 0x1059C */
	MMU_STAGE2__ST2MMU__AS6__FAULTADDRESS, /* (RO) 64-bit 0x105A0 */
	MMU_STAGE2__ST2MMU__AS6__STATUS, /* (RO) 32-bit 0x105A8 */
	MMU_STAGE2__ST2MMU__AS6__TRANSCFG, /* (RW) 64-bit 0x105B0 */
	MMU_STAGE2__ST2MMU__AS6__FAULTEXTRA, /* (RO) 64-bit 0x105B8 */
	MMU_STAGE2__ST2MMU__AS7__TRANSTAB, /* (RW) 64-bit 0x105C0 */
	MMU_STAGE2__ST2MMU__AS7__MEMATTR, /* (RW) 64-bit 0x105C8 */
	MMU_STAGE2__ST2MMU__AS7__LOCKADDR, /* (RW) 64-bit 0x105D0 */
	MMU_STAGE2__ST2MMU__AS7__COMMAND, /* (WO) 32-bit 0x105D8 */
	MMU_STAGE2__ST2MMU__AS7__FAULTSTATUS, /* (RO) 32-bit 0x105DC */
	MMU_STAGE2__ST2MMU__AS7__FAULTADDRESS, /* (RO) 64-bit 0x105E0 */
	MMU_STAGE2__ST2MMU__AS7__STATUS, /* (RO) 32-bit 0x105E8 */
	MMU_STAGE2__ST2MMU__AS7__TRANSCFG, /* (RW) 64-bit 0x105F0 */
	MMU_STAGE2__ST2MMU__AS7__FAULTEXTRA, /* (RO) 64-bit 0x105F8 */
	MMU_STAGE2__ST2MMU__AS8__TRANSTAB, /* (RW) 64-bit 0x10600 */
	MMU_STAGE2__ST2MMU__AS8__MEMATTR, /* (RW) 64-bit 0x10608 */
	MMU_STAGE2__ST2MMU__AS8__LOCKADDR, /* (RW) 64-bit 0x10610 */
	MMU_STAGE2__ST2MMU__AS8__COMMAND, /* (WO) 32-bit 0x10618 */
	MMU_STAGE2__ST2MMU__AS8__FAULTSTATUS, /* (RO) 32-bit 0x1061C */
	MMU_STAGE2__ST2MMU__AS8__FAULTADDRESS, /* (RO) 64-bit 0x10620 */
	MMU_STAGE2__ST2MMU__AS8__STATUS, /* (RO) 32-bit 0x10628 */
	MMU_STAGE2__ST2MMU__AS8__TRANSCFG, /* (RW) 64-bit 0x10630 */
	MMU_STAGE2__ST2MMU__AS8__FAULTEXTRA, /* (RO) 64-bit 0x10638 */
	MMU_STAGE2__ST2MMU__AS9__TRANSTAB, /* (RW) 64-bit 0x10640 */
	MMU_STAGE2__ST2MMU__AS9__MEMATTR, /* (RW) 64-bit 0x10648 */
	MMU_STAGE2__ST2MMU__AS9__LOCKADDR, /* (RW) 64-bit 0x10650 */
	MMU_STAGE2__ST2MMU__AS9__COMMAND, /* (WO) 32-bit 0x10658 */
	MMU_STAGE2__ST2MMU__AS9__FAULTSTATUS, /* (RO) 32-bit 0x1065C */
	MMU_STAGE2__ST2MMU__AS9__FAULTADDRESS, /* (RO) 64-bit 0x10660 */
	MMU_STAGE2__ST2MMU__AS9__STATUS, /* (RO) 32-bit 0x10668 */
	MMU_STAGE2__ST2MMU__AS9__TRANSCFG, /* (RW) 64-bit 0x10670 */
	MMU_STAGE2__ST2MMU__AS9__FAULTEXTRA, /* (RO) 64-bit 0x10678 */
	MMU_STAGE2__ST2MMU__AS10__TRANSTAB, /* (RW) 64-bit 0x10680 */
	MMU_STAGE2__ST2MMU__AS10__MEMATTR, /* (RW) 64-bit 0x10688 */
	MMU_STAGE2__ST2MMU__AS10__LOCKADDR, /* (RW) 64-bit 0x10690 */
	MMU_STAGE2__ST2MMU__AS10__COMMAND, /* (WO) 32-bit 0x10698 */
	MMU_STAGE2__ST2MMU__AS10__FAULTSTATUS, /* (RO) 32-bit 0x1069C */
	MMU_STAGE2__ST2MMU__AS10__FAULTADDRESS, /* (RO) 64-bit 0x106A0 */
	MMU_STAGE2__ST2MMU__AS10__STATUS, /* (RO) 32-bit 0x106A8 */
	MMU_STAGE2__ST2MMU__AS10__TRANSCFG, /* (RW) 64-bit 0x106B0 */
	MMU_STAGE2__ST2MMU__AS10__FAULTEXTRA, /* (RO) 64-bit 0x106B8 */
	MMU_STAGE2__ST2MMU__AS11__TRANSTAB, /* (RW) 64-bit 0x106C0 */
	MMU_STAGE2__ST2MMU__AS11__MEMATTR, /* (RW) 64-bit 0x106C8 */
	MMU_STAGE2__ST2MMU__AS11__LOCKADDR, /* (RW) 64-bit 0x106D0 */
	MMU_STAGE2__ST2MMU__AS11__COMMAND, /* (WO) 32-bit 0x106D8 */
	MMU_STAGE2__ST2MMU__AS11__FAULTSTATUS, /* (RO) 32-bit 0x106DC */
	MMU_STAGE2__ST2MMU__AS11__FAULTADDRESS, /* (RO) 64-bit 0x106E0 */
	MMU_STAGE2__ST2MMU__AS11__STATUS, /* (RO) 32-bit 0x106E8 */
	MMU_STAGE2__ST2MMU__AS11__TRANSCFG, /* (RW) 64-bit 0x106F0 */
	MMU_STAGE2__ST2MMU__AS11__FAULTEXTRA, /* (RO) 64-bit 0x106F8 */
	MMU_STAGE2__ST2MMU__AS12__TRANSTAB, /* (RW) 64-bit 0x10700 */
	MMU_STAGE2__ST2MMU__AS12__MEMATTR, /* (RW) 64-bit 0x10708 */
	MMU_STAGE2__ST2MMU__AS12__LOCKADDR, /* (RW) 64-bit 0x10710 */
	MMU_STAGE2__ST2MMU__AS12__COMMAND, /* (WO) 32-bit 0x10718 */
	MMU_STAGE2__ST2MMU__AS12__FAULTSTATUS, /* (RO) 32-bit 0x1071C */
	MMU_STAGE2__ST2MMU__AS12__FAULTADDRESS, /* (RO) 64-bit 0x10720 */
	MMU_STAGE2__ST2MMU__AS12__STATUS, /* (RO) 32-bit 0x10728 */
	MMU_STAGE2__ST2MMU__AS12__TRANSCFG, /* (RW) 64-bit 0x10730 */
	MMU_STAGE2__ST2MMU__AS12__FAULTEXTRA, /* (RO) 64-bit 0x10738 */
	MMU_STAGE2__ST2MMU__AS13__TRANSTAB, /* (RW) 64-bit 0x10740 */
	MMU_STAGE2__ST2MMU__AS13__MEMATTR, /* (RW) 64-bit 0x10748 */
	MMU_STAGE2__ST2MMU__AS13__LOCKADDR, /* (RW) 64-bit 0x10750 */
	MMU_STAGE2__ST2MMU__AS13__COMMAND, /* (WO) 32-bit 0x10758 */
	MMU_STAGE2__ST2MMU__AS13__FAULTSTATUS, /* (RO) 32-bit 0x1075C */
	MMU_STAGE2__ST2MMU__AS13__FAULTADDRESS, /* (RO) 64-bit 0x10760 */
	MMU_STAGE2__ST2MMU__AS13__STATUS, /* (RO) 32-bit 0x10768 */
	MMU_STAGE2__ST2MMU__AS13__TRANSCFG, /* (RW) 64-bit 0x10770 */
	MMU_STAGE2__ST2MMU__AS13__FAULTEXTRA, /* (RO) 64-bit 0x10778 */
	MMU_STAGE2__ST2MMU__AS14__TRANSTAB, /* (RW) 64-bit 0x10780 */
	MMU_STAGE2__ST2MMU__AS14__MEMATTR, /* (RW) 64-bit 0x10788 */
	MMU_STAGE2__ST2MMU__AS14__LOCKADDR, /* (RW) 64-bit 0x10790 */
	MMU_STAGE2__ST2MMU__AS14__COMMAND, /* (WO) 32-bit 0x10798 */
	MMU_STAGE2__ST2MMU__AS14__FAULTSTATUS, /* (RO) 32-bit 0x1079C */
	MMU_STAGE2__ST2MMU__AS14__FAULTADDRESS, /* (RO) 64-bit 0x107A0 */
	MMU_STAGE2__ST2MMU__AS14__STATUS, /* (RO) 32-bit 0x107A8 */
	MMU_STAGE2__ST2MMU__AS14__TRANSCFG, /* (RW) 64-bit 0x107B0 */
	MMU_STAGE2__ST2MMU__AS14__FAULTEXTRA, /* (RO) 64-bit 0x107B8 */
	MMU_STAGE2__ST2MMU__AS15__TRANSTAB, /* (RW) 64-bit 0x107C0 */
	MMU_STAGE2__ST2MMU__AS15__MEMATTR, /* (RW) 64-bit 0x107C8 */
	MMU_STAGE2__ST2MMU__AS15__LOCKADDR, /* (RW) 64-bit 0x107D0 */
	MMU_STAGE2__ST2MMU__AS15__COMMAND, /* (WO) 32-bit 0x107D8 */
	MMU_STAGE2__ST2MMU__AS15__FAULTSTATUS, /* (RO) 32-bit 0x107DC */
	MMU_STAGE2__ST2MMU__AS15__FAULTADDRESS, /* (RO) 64-bit 0x107E0 */
	MMU_STAGE2__ST2MMU__AS15__STATUS, /* (RO) 32-bit 0x107E8 */
	MMU_STAGE2__ST2MMU__AS15__TRANSCFG, /* (RW) 64-bit 0x107F0 */
	MMU_STAGE2__ST2MMU__AS15__FAULTEXTRA, /* (RO) 64-bit 0x107F8 */
	NR_V6_0_REGS,
};

enum kbase_regmap_enum_v6_2 {
	GPU_CONTROL__REVIDR = NR_V6_0_REGS, /* (RO) 32-bit 0x280 */
	GPU_CONTROL__STACK_PRESENT, /* (RO) 64-bit 0xE00 */
	GPU_CONTROL__STACK_PWROFF, /* (WO) 64-bit 0xE30 */
	GPU_CONTROL__STACK_PWRON, /* (WO) 64-bit 0xE20 */
	GPU_CONTROL__STACK_PWRTRANS, /* (RO) 64-bit 0xE40 */
	GPU_CONTROL__STACK_READY, /* (RO) 64-bit 0xE10 */
	NR_V6_2_REGS,
};

enum kbase_regmap_enum_v7_0 {
	GPU_CONTROL__TEXTURE_FEATURES_3 = NR_V6_2_REGS, /* (RO) 32-bit 0xBC */
	NR_V7_0_REGS,
};

enum kbase_regmap_enum_v7_2 {
	GPU_CONTROL__CORE_FEATURES = NR_V7_0_REGS, /* (RO) 32-bit 0x8 */
	GPU_CONTROL__THREAD_TLS_ALLOC, /* (RO) 32-bit 0x310 */
	NR_V7_2_REGS,
};

enum kbase_regmap_enum_v9_0 {
	NR_V9_0_REGS = NR_V7_2_REGS,
};

/*
 * V9_0_REMOVED_REGS:
 * GPU_CONTROL__CORE_FEATURES
 * GPU_CONTROL__THREAD_TLS_ALLOC
 * JOB_CONTROL__JOB_IRQ_THROTTLE
 */

enum kbase_regmap_enum_v9_2 {
	GPU_CONTROL__L2_CONFIG = NR_V9_0_REGS, /* (RW) 32-bit 0x48 */
	NR_V9_2_REGS,
};

enum kbase_regmap_enum_v9_14 {
	PTM_AW_IRQ_CLEAR = NR_V9_2_REGS, /* (RW) 32-bit 0x1FFC8 */
	PTM_AW_IRQ_INJECTION, /* (RW) 32-bit 0x1FFD4 */
	PTM_AW_IRQ_MASK, /* (RW) 32-bit 0x1FFCC */
	PTM_AW_IRQ_RAWSTAT, /* (RO) 32-bit 0x1FFC4 */
	PTM_AW_IRQ_STATUS, /* (RO) 32-bit 0x1FFD0 */
	PTM_AW_MESSAGE__PTM_INCOMING_MESSAGE0, /* (RO) 32-bit 0x1FFD8 */
	PTM_AW_MESSAGE__PTM_INCOMING_MESSAGE1, /* (RO) 32-bit 0x1FFDC */
	PTM_AW_MESSAGE__PTM_OUTGOING_MESSAGE0, /* (RW) 32-bit 0x1FFE4 */
	PTM_AW_MESSAGE__PTM_OUTGOING_MESSAGE1, /* (RW) 32-bit 0x1FFE8 */
	PTM_AW_MESSAGE__PTM_OUTGOING_MESSAGE_STATUS, /* (RO) 32-bit 0x1FFE0 */
	PTM_ID, /* (RO) 32-bit 0x1FFC0 */
	NR_V9_14_REGS,
};

#endif /* _MALI_KBASE_REGMAP_JM_ENUMS_H_ */
