/*************************************************************************/ /*!
@Title          Hardware definition file rgx_cr_defs_km.h
@Brief          The file contains auto-generated hardware definitions without
                BVNC-specific compile time conditionals.
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@License        Dual MIT/GPLv2

The contents of this file are subject to the MIT license as set out below.

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.

If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.

This License is also included in this distribution in the file called
"MIT-COPYING".

EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/

/*               ****   Autogenerated C -- do not edit    ****               */

/*
 */


#ifndef RGX_CR_DEFS_KM_H
#define RGX_CR_DEFS_KM_H

#if !defined(IMG_EXPLICIT_INCLUDE_HWDEFS)
#error This file may only be included if explicitly defined
#endif

#include "img_types.h"
#include "img_defs.h"


#define RGX_CR_DEFS_KM_REVISION 144

/*
    Register RGX_CR_USC_INDIRECT
*/
#define RGX_CR_USC_INDIRECT                               (0x8000U)
#define RGX_CR_USC_INDIRECT_MASKFULL                      (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_USC_INDIRECT_ADDRESS_SHIFT                 (0U)
#define RGX_CR_USC_INDIRECT_ADDRESS_CLRMSK                (0xFFFFFFC0U)


/*
    Register RGX_CR_MERCER_INDIRECT
*/
#define RGX_CR_MERCER_INDIRECT                            (0x8238U)
#define RGX_CR_MERCER_INDIRECT_MASKFULL                   (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_MERCER_INDIRECT_ADDRESS_SHIFT              (0U)
#define RGX_CR_MERCER_INDIRECT_ADDRESS_CLRMSK             (0xFFFFFFC0U)


/*
    Register RGX_CR_PBE_INDIRECT
*/
#define RGX_CR_PBE_INDIRECT                               (0x83E0U)
#define RGX_CR_PBE_INDIRECT_MASKFULL                      (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_PBE_INDIRECT_ADDRESS_SHIFT                 (0U)
#define RGX_CR_PBE_INDIRECT_ADDRESS_CLRMSK                (0xFFFFFFC0U)


/*
    Register RGX_CR_PBE_SHARED_INDIRECT
*/
#define RGX_CR_PBE_SHARED_INDIRECT                        (0x8388U)
#define RGX_CR_PBE_SHARED_INDIRECT_MASKFULL               (IMG_UINT64_C(0x000000000000001F))
#define RGX_CR_PBE_SHARED_INDIRECT_ADDRESS_SHIFT          (0U)
#define RGX_CR_PBE_SHARED_INDIRECT_ADDRESS_CLRMSK         (0xFFFFFFE0U)


/*
    Register RGX_CR_ISP_INDIRECT
*/
#define RGX_CR_ISP_INDIRECT                               (0x83F8U)
#define RGX_CR_ISP_INDIRECT_MASKFULL                      (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_ISP_INDIRECT_ADDRESS_SHIFT                 (0U)
#define RGX_CR_ISP_INDIRECT_ADDRESS_CLRMSK                (0xFFFFFFC0U)


/*
    Register RGX_CR_TPU_INDIRECT
*/
#define RGX_CR_TPU_INDIRECT                               (0x83E8U)
#define RGX_CR_TPU_INDIRECT_MASKFULL                      (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_TPU_INDIRECT_ADDRESS_SHIFT                 (0U)
#define RGX_CR_TPU_INDIRECT_ADDRESS_CLRMSK                (0xFFFFFFC0U)


/*
    Register RGX_CR_SWIFT_INDIRECT
*/
#define RGX_CR_SWIFT_INDIRECT                             (0x8308U)
#define RGX_CR_SWIFT_INDIRECT_MASKFULL                    (IMG_UINT64_C(0x000000000000003F))
#define RGX_CR_SWIFT_INDIRECT_ADDRESS_SHIFT               (0U)
#define RGX_CR_SWIFT_INDIRECT_ADDRESS_CLRMSK              (0xFFFFFFC0U)


/*
    Register RGX_CR_TEXAS_INDIRECT
*/
#define RGX_CR_TEXAS_INDIRECT                             (0x8390U)
#define RGX_CR_TEXAS_INDIRECT_MASKFULL                    (IMG_UINT64_C(0x000000000000001F))
#define RGX_CR_TEXAS_INDIRECT_ADDRESS_SHIFT               (0U)
#define RGX_CR_TEXAS_INDIRECT_ADDRESS_CLRMSK              (0xFFFFFFE0U)


/*
    Register RGX_CR_CLK_CTRL0
*/
#define RGX_CR_CLK_CTRL0                                  (0x0000U)
#define RGX_CR_CLK_CTRL0_MASKFULL                         (IMG_UINT64_C(0xFFCF03000F3F3303))
#define RGX_CR_CLK_CTRL0_BIF_TEXAS_SHIFT                  (62U)
#define RGX_CR_CLK_CTRL0_BIF_TEXAS_CLRMSK                 (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_BIF_TEXAS_OFF                    (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_BIF_TEXAS_ON                     (IMG_UINT64_C(0x4000000000000000))
#define RGX_CR_CLK_CTRL0_BIF_TEXAS_AUTO                   (IMG_UINT64_C(0x8000000000000000))
#define RGX_CR_CLK_CTRL0_FBCACHE_SHIFT                    (60U)
#define RGX_CR_CLK_CTRL0_FBCACHE_CLRMSK                   (IMG_UINT64_C(0xCFFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_FBCACHE_OFF                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_FBCACHE_ON                       (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_CLK_CTRL0_FBCACHE_AUTO                     (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_CLK_CTRL0_FBC_SHIFT                        (58U)
#define RGX_CR_CLK_CTRL0_FBC_CLRMSK                       (IMG_UINT64_C(0xF3FFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_FBC_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_FBC_ON                           (IMG_UINT64_C(0x0400000000000000))
#define RGX_CR_CLK_CTRL0_FBC_AUTO                         (IMG_UINT64_C(0x0800000000000000))
#define RGX_CR_CLK_CTRL0_FBDC_SHIFT                       (56U)
#define RGX_CR_CLK_CTRL0_FBDC_CLRMSK                      (IMG_UINT64_C(0xFCFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_FBDC_OFF                         (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_FBDC_ON                          (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_CLK_CTRL0_FBDC_AUTO                        (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_CLK_CTRL0_FBM_SHIFT                        (54U)
#define RGX_CR_CLK_CTRL0_FBM_CLRMSK                       (IMG_UINT64_C(0xFF3FFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_FBM_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_FBM_ON                           (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_CLK_CTRL0_FBM_AUTO                         (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_CLK_CTRL0_PBE_SHIFT                        (50U)
#define RGX_CR_CLK_CTRL0_PBE_CLRMSK                       (IMG_UINT64_C(0xFFF3FFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_PBE_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_PBE_ON                           (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_CLK_CTRL0_PBE_AUTO                         (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_CLK_CTRL0_MCU_L1_SHIFT                     (48U)
#define RGX_CR_CLK_CTRL0_MCU_L1_CLRMSK                    (IMG_UINT64_C(0xFFFCFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_MCU_L1_OFF                       (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_MCU_L1_ON                        (IMG_UINT64_C(0x0001000000000000))
#define RGX_CR_CLK_CTRL0_MCU_L1_AUTO                      (IMG_UINT64_C(0x0002000000000000))
#define RGX_CR_CLK_CTRL0_BIF_SHIFT                        (40U)
#define RGX_CR_CLK_CTRL0_BIF_CLRMSK                       (IMG_UINT64_C(0xFFFFFCFFFFFFFFFF))
#define RGX_CR_CLK_CTRL0_BIF_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_BIF_ON                           (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_CLK_CTRL0_BIF_AUTO                         (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_CLK_CTRL0_MCU_L0_SHIFT                     (26U)
#define RGX_CR_CLK_CTRL0_MCU_L0_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFF3FFFFFF))
#define RGX_CR_CLK_CTRL0_MCU_L0_OFF                       (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_MCU_L0_ON                        (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_CLK_CTRL0_MCU_L0_AUTO                      (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_CLK_CTRL0_TPU_SHIFT                        (24U)
#define RGX_CR_CLK_CTRL0_TPU_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFCFFFFFF))
#define RGX_CR_CLK_CTRL0_TPU_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_TPU_ON                           (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_CLK_CTRL0_TPU_AUTO                         (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_CLK_CTRL0_USC_SHIFT                        (20U)
#define RGX_CR_CLK_CTRL0_USC_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFFCFFFFF))
#define RGX_CR_CLK_CTRL0_USC_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_USC_ON                           (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_CLK_CTRL0_USC_AUTO                         (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_CLK_CTRL0_SLC_BANK_SHIFT                   (18U)
#define RGX_CR_CLK_CTRL0_SLC_BANK_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFF3FFFF))
#define RGX_CR_CLK_CTRL0_SLC_BANK_OFF                     (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_SLC_BANK_ON                      (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_CLK_CTRL0_SLC_BANK_AUTO                    (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_CLK_CTRL0_SLC_SHIFT                        (16U)
#define RGX_CR_CLK_CTRL0_SLC_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFFFCFFFF))
#define RGX_CR_CLK_CTRL0_SLC_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_SLC_ON                           (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_CLK_CTRL0_SLC_AUTO                         (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_CLK_CTRL0_PDS_SHIFT                        (12U)
#define RGX_CR_CLK_CTRL0_PDS_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFFFFCFFF))
#define RGX_CR_CLK_CTRL0_PDS_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_PDS_ON                           (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_CLK_CTRL0_PDS_AUTO                         (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_CLK_CTRL0_PM_SHIFT                         (8U)
#define RGX_CR_CLK_CTRL0_PM_CLRMSK                        (IMG_UINT64_C(0xFFFFFFFFFFFFFCFF))
#define RGX_CR_CLK_CTRL0_PM_OFF                           (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_PM_ON                            (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_CLK_CTRL0_PM_AUTO                          (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_CLK_CTRL0_ISP_SHIFT                        (0U)
#define RGX_CR_CLK_CTRL0_ISP_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))
#define RGX_CR_CLK_CTRL0_ISP_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL0_ISP_ON                           (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_CLK_CTRL0_ISP_AUTO                         (IMG_UINT64_C(0x0000000000000002))


/*
    Register RGX_CR_CLK_STATUS0
*/
#define RGX_CR_CLK_STATUS0                                (0x0008U)
#define RGX_CR_CLK_STATUS0_MASKFULL                       (IMG_UINT64_C(0x00000001BF101751))
#define RGX_CR_CLK_STATUS0_MCU_L0_SHIFT                   (32U)
#define RGX_CR_CLK_STATUS0_MCU_L0_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_CLK_STATUS0_MCU_L0_GATED                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_MCU_L0_RUNNING                 (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_CLK_STATUS0_BIF_TEXAS_SHIFT                (31U)
#define RGX_CR_CLK_STATUS0_BIF_TEXAS_CLRMSK               (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_CLK_STATUS0_BIF_TEXAS_GATED                (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_BIF_TEXAS_RUNNING              (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CLK_STATUS0_FBCACHE_SHIFT                  (29U)
#define RGX_CR_CLK_STATUS0_FBCACHE_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_CLK_STATUS0_FBCACHE_GATED                  (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_FBCACHE_RUNNING                (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_CLK_STATUS0_FBC_SHIFT                      (28U)
#define RGX_CR_CLK_STATUS0_FBC_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_CLK_STATUS0_FBC_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_FBC_RUNNING                    (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_CLK_STATUS0_FBDC_SHIFT                     (27U)
#define RGX_CR_CLK_STATUS0_FBDC_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_CLK_STATUS0_FBDC_GATED                     (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_FBDC_RUNNING                   (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_CLK_STATUS0_FBM_SHIFT                      (26U)
#define RGX_CR_CLK_STATUS0_FBM_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_CLK_STATUS0_FBM_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_FBM_RUNNING                    (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_CLK_STATUS0_PBE_SHIFT                      (25U)
#define RGX_CR_CLK_STATUS0_PBE_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_CLK_STATUS0_PBE_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_PBE_RUNNING                    (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_CLK_STATUS0_MCU_L1_SHIFT                   (24U)
#define RGX_CR_CLK_STATUS0_MCU_L1_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_CLK_STATUS0_MCU_L1_GATED                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_MCU_L1_RUNNING                 (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_CLK_STATUS0_BIF_SHIFT                      (20U)
#define RGX_CR_CLK_STATUS0_BIF_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_CLK_STATUS0_BIF_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_BIF_RUNNING                    (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_CLK_STATUS0_TPU_SHIFT                      (12U)
#define RGX_CR_CLK_STATUS0_TPU_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_CLK_STATUS0_TPU_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_TPU_RUNNING                    (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_CLK_STATUS0_USC_SHIFT                      (10U)
#define RGX_CR_CLK_STATUS0_USC_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_CLK_STATUS0_USC_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_USC_RUNNING                    (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_CLK_STATUS0_SLC_BANK_SHIFT                 (9U)
#define RGX_CR_CLK_STATUS0_SLC_BANK_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_CLK_STATUS0_SLC_BANK_GATED                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_SLC_BANK_RUNNING               (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_CLK_STATUS0_SLC_SHIFT                      (8U)
#define RGX_CR_CLK_STATUS0_SLC_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_CLK_STATUS0_SLC_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_SLC_RUNNING                    (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_CLK_STATUS0_PDS_SHIFT                      (6U)
#define RGX_CR_CLK_STATUS0_PDS_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_CLK_STATUS0_PDS_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_PDS_RUNNING                    (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_CLK_STATUS0_PM_SHIFT                       (4U)
#define RGX_CR_CLK_STATUS0_PM_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_CLK_STATUS0_PM_GATED                       (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_PM_RUNNING                     (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_CLK_STATUS0_ISP_SHIFT                      (0U)
#define RGX_CR_CLK_STATUS0_ISP_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_CLK_STATUS0_ISP_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS0_ISP_RUNNING                    (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_CORE_ID
*/
#define RGX_CR_CORE_ID                                    (0x0020U)
#define RGX_CR_CORE_ID_MASKFULL                           (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_CORE_ID_BRANCH_ID_SHIFT                    (48U)
#define RGX_CR_CORE_ID_BRANCH_ID_CLRMSK                   (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
#define RGX_CR_CORE_ID_VERSION_ID_SHIFT                   (32U)
#define RGX_CR_CORE_ID_VERSION_ID_CLRMSK                  (IMG_UINT64_C(0xFFFF0000FFFFFFFF))
#define RGX_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT     (16U)
#define RGX_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK    (IMG_UINT64_C(0xFFFFFFFF0000FFFF))
#define RGX_CR_CORE_ID_CONFIG_ID_SHIFT                    (0U)
#define RGX_CR_CORE_ID_CONFIG_ID_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFF0000))


/*
    Register RGX_CR_SPU_ENABLE
*/
#define RGX_CR_SPU_ENABLE                                 (0x0050U)
#define RGX_CR_SPU_ENABLE_MASKFULL                        (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_SPU_ENABLE_ENABLE_SHIFT                    (0U)
#define RGX_CR_SPU_ENABLE_ENABLE_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_SOC_TIMER_GRAY
*/
#define RGX_CR_SOC_TIMER_GRAY                             (0x00E0U)
#define RGX_CR_SOC_TIMER_GRAY_MASKFULL                    (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SOC_TIMER_GRAY_VALUE_SHIFT                 (0U)
#define RGX_CR_SOC_TIMER_GRAY_VALUE_CLRMSK                (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SOC_TIMER_BINARY
*/
#define RGX_CR_SOC_TIMER_BINARY                           (0x00E8U)
#define RGX_CR_SOC_TIMER_BINARY_MASKFULL                  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SOC_TIMER_BINARY_VALUE_SHIFT               (0U)
#define RGX_CR_SOC_TIMER_BINARY_VALUE_CLRMSK              (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_CLK_CTRL1
*/
#define RGX_CR_CLK_CTRL1                                  (0x0080U)
#define RGX_CR_CLK_CTRL1_MASKFULL                         (IMG_UINT64_C(0xFFFC3F3FFFCFFFFF))
#define RGX_CR_CLK_CTRL1_BSC_SHIFT                        (62U)
#define RGX_CR_CLK_CTRL1_BSC_CLRMSK                       (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_BSC_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_BSC_ON                           (IMG_UINT64_C(0x4000000000000000))
#define RGX_CR_CLK_CTRL1_BSC_AUTO                         (IMG_UINT64_C(0x8000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SAP_SHIFT               (60U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_SAP_CLRMSK              (IMG_UINT64_C(0xCFFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SAP_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SAP_ON                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SAP_AUTO                (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_PAP_CMN_SHIFT           (58U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_PAP_CMN_CLRMSK          (IMG_UINT64_C(0xF3FFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_PAP_CMN_OFF             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_PAP_CMN_ON              (IMG_UINT64_C(0x0400000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_PAP_CMN_AUTO            (IMG_UINT64_C(0x0800000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TPX_SHIFT               (56U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_TPX_CLRMSK              (IMG_UINT64_C(0xFCFFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TPX_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TPX_ON                  (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TPX_AUTO                (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMIPSB_SHIFT            (54U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMIPSB_CLRMSK           (IMG_UINT64_C(0xFF3FFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMIPSB_OFF              (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMIPSB_ON               (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMIPSB_AUTO             (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_CLK_CTRL1_PSB_SHIFT                        (52U)
#define RGX_CR_CLK_CTRL1_PSB_CLRMSK                       (IMG_UINT64_C(0xFFCFFFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_PSB_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_PSB_ON                           (IMG_UINT64_C(0x0010000000000000))
#define RGX_CR_CLK_CTRL1_PSB_AUTO                         (IMG_UINT64_C(0x0020000000000000))
#define RGX_CR_CLK_CTRL1_TPU_USC_SELECT_SHIFT             (50U)
#define RGX_CR_CLK_CTRL1_TPU_USC_SELECT_CLRMSK            (IMG_UINT64_C(0xFFF3FFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_TPU_USC_SELECT_OFF               (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_TPU_USC_SELECT_ON                (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_CLK_CTRL1_TPU_USC_SELECT_AUTO              (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_CLK_CTRL1_CDM_PIPE_SHIFT                   (44U)
#define RGX_CR_CLK_CTRL1_CDM_PIPE_CLRMSK                  (IMG_UINT64_C(0xFFFFCFFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_CDM_PIPE_OFF                     (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_CDM_PIPE_ON                      (IMG_UINT64_C(0x0000100000000000))
#define RGX_CR_CLK_CTRL1_CDM_PIPE_AUTO                    (IMG_UINT64_C(0x0000200000000000))
#define RGX_CR_CLK_CTRL1_USC_L2ICACHE_SHIFT               (42U)
#define RGX_CR_CLK_CTRL1_USC_L2ICACHE_CLRMSK              (IMG_UINT64_C(0xFFFFF3FFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_USC_L2ICACHE_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_L2ICACHE_ON                  (IMG_UINT64_C(0x0000040000000000))
#define RGX_CR_CLK_CTRL1_USC_L2ICACHE_AUTO                (IMG_UINT64_C(0x0000080000000000))
#define RGX_CR_CLK_CTRL1_TCU_L1_SHIFT                     (40U)
#define RGX_CR_CLK_CTRL1_TCU_L1_CLRMSK                    (IMG_UINT64_C(0xFFFFFCFFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_TCU_L1_OFF                       (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_TCU_L1_ON                        (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_CLK_CTRL1_TCU_L1_AUTO                      (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_CLK_CTRL1_TDM_SHIFT                        (36U)
#define RGX_CR_CLK_CTRL1_TDM_CLRMSK                       (IMG_UINT64_C(0xFFFFFFCFFFFFFFFF))
#define RGX_CR_CLK_CTRL1_TDM_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_TDM_ON                           (IMG_UINT64_C(0x0000001000000000))
#define RGX_CR_CLK_CTRL1_TDM_AUTO                         (IMG_UINT64_C(0x0000002000000000))
#define RGX_CR_CLK_CTRL1_ASTC_SHIFT                       (34U)
#define RGX_CR_CLK_CTRL1_ASTC_CLRMSK                      (IMG_UINT64_C(0xFFFFFFF3FFFFFFFF))
#define RGX_CR_CLK_CTRL1_ASTC_OFF                         (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_ASTC_ON                          (IMG_UINT64_C(0x0000000400000000))
#define RGX_CR_CLK_CTRL1_ASTC_AUTO                        (IMG_UINT64_C(0x0000000800000000))
#define RGX_CR_CLK_CTRL1_IPF_SHIFT                        (32U)
#define RGX_CR_CLK_CTRL1_IPF_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFCFFFFFFFF))
#define RGX_CR_CLK_CTRL1_IPF_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_IPF_ON                           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_CLK_CTRL1_IPF_AUTO                         (IMG_UINT64_C(0x0000000200000000))
#define RGX_CR_CLK_CTRL1_COMPUTE_SHIFT                    (30U)
#define RGX_CR_CLK_CTRL1_COMPUTE_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFF3FFFFFFF))
#define RGX_CR_CLK_CTRL1_COMPUTE_OFF                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_COMPUTE_ON                       (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_CLK_CTRL1_COMPUTE_AUTO                     (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CLK_CTRL1_PIXEL_SHIFT                      (28U)
#define RGX_CR_CLK_CTRL1_PIXEL_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFCFFFFFFF))
#define RGX_CR_CLK_CTRL1_PIXEL_OFF                        (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_PIXEL_ON                         (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_CLK_CTRL1_PIXEL_AUTO                       (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_CLK_CTRL1_VERTEX_SHIFT                     (26U)
#define RGX_CR_CLK_CTRL1_VERTEX_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFF3FFFFFF))
#define RGX_CR_CLK_CTRL1_VERTEX_OFF                       (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_VERTEX_ON                        (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_CLK_CTRL1_VERTEX_AUTO                      (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_CLK_CTRL1_TPF_SHIFT                        (24U)
#define RGX_CR_CLK_CTRL1_TPF_CLRMSK                       (IMG_UINT64_C(0xFFFFFFFFFCFFFFFF))
#define RGX_CR_CLK_CTRL1_TPF_OFF                          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_TPF_ON                           (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_CLK_CTRL1_TPF_AUTO                         (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_CLK_CTRL1_GEO_VERTEX_SHIFT                 (22U)
#define RGX_CR_CLK_CTRL1_GEO_VERTEX_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFF3FFFFF))
#define RGX_CR_CLK_CTRL1_GEO_VERTEX_OFF                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_GEO_VERTEX_ON                    (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_CLK_CTRL1_GEO_VERTEX_AUTO                  (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_CLK_CTRL1_GEO_SHARED_SHIFT                 (18U)
#define RGX_CR_CLK_CTRL1_GEO_SHARED_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFF3FFFF))
#define RGX_CR_CLK_CTRL1_GEO_SHARED_OFF                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_GEO_SHARED_ON                    (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_CLK_CTRL1_GEO_SHARED_AUTO                  (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_CLK_CTRL1_GEO_TESS_SHIFT                   (16U)
#define RGX_CR_CLK_CTRL1_GEO_TESS_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFFCFFFF))
#define RGX_CR_CLK_CTRL1_GEO_TESS_OFF                     (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_GEO_TESS_ON                      (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_CLK_CTRL1_GEO_TESS_AUTO                    (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SMP_SHIFT               (14U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_SMP_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFF3FFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SMP_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SMP_ON                  (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_SMP_AUTO                (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_DMA_SHIFT               (12U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_DMA_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFCFFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_DMA_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_DMA_ON                  (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_DMA_AUTO                (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TAP_SHIFT               (10U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_TAP_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFF3FF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TAP_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TAP_ON                  (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_CLK_CTRL1_USC_PIPE_TAP_AUTO                (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_CLK_CTRL1_USC_PIPE_AP_SHIFT                (8U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_AP_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFCFF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_AP_OFF                  (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_AP_ON                   (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_CLK_CTRL1_USC_PIPE_AP_AUTO                 (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMI_SHIFT               (6U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMI_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFF3F))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMI_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMI_ON                  (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_CLK_CTRL1_USC_PIPE_EMI_AUTO                (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_CLK_CTRL1_USC_PIPE_ITR_SHIFT               (4U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_ITR_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFCF))
#define RGX_CR_CLK_CTRL1_USC_PIPE_ITR_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_ITR_ON                  (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_CLK_CTRL1_USC_PIPE_ITR_AUTO                (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_CLK_CTRL1_USC_PIPE_CPX_SHIFT               (2U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_CPX_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFF3))
#define RGX_CR_CLK_CTRL1_USC_PIPE_CPX_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_CPX_ON                  (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_CLK_CTRL1_USC_PIPE_CPX_AUTO                (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_CLK_CTRL1_USC_PIPE_MOV_SHIFT               (0U)
#define RGX_CR_CLK_CTRL1_USC_PIPE_MOV_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))
#define RGX_CR_CLK_CTRL1_USC_PIPE_MOV_OFF                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_CTRL1_USC_PIPE_MOV_ON                  (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_CLK_CTRL1_USC_PIPE_MOV_AUTO                (IMG_UINT64_C(0x0000000000000002))


/*
    Register RGX_CR_CLK_STATUS1
*/
#define RGX_CR_CLK_STATUS1                                (0x0088U)
#define RGX_CR_CLK_STATUS1_MASKFULL                       (IMG_UINT64_C(0x00000000FFFE77FB))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SAP_SHIFT             (31U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_SAP_CLRMSK            (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SAP_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SAP_RUNNING           (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_PAP_CMN_SHIFT         (30U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_PAP_CMN_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_PAP_CMN_GATED         (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_PAP_CMN_RUNNING       (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TPX_SHIFT             (29U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_TPX_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TPX_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TPX_RUNNING           (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMIPSB_SHIFT          (28U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMIPSB_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMIPSB_GATED          (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMIPSB_RUNNING        (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_CLK_STATUS1_BSC_SHIFT                      (27U)
#define RGX_CR_CLK_STATUS1_BSC_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_CLK_STATUS1_BSC_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_BSC_RUNNING                    (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_CLK_STATUS1_PSB_SHIFT                      (26U)
#define RGX_CR_CLK_STATUS1_PSB_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_CLK_STATUS1_PSB_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_PSB_RUNNING                    (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_CLK_STATUS1_TPU_USC_SELECT_SHIFT           (25U)
#define RGX_CR_CLK_STATUS1_TPU_USC_SELECT_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_CLK_STATUS1_TPU_USC_SELECT_GATED           (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_TPU_USC_SELECT_RUNNING         (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SMP_SHIFT             (24U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_SMP_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SMP_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_SMP_RUNNING           (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_DMA_SHIFT             (23U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_DMA_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_DMA_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_DMA_RUNNING           (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TAP_SHIFT             (22U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_TAP_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TAP_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_TAP_RUNNING           (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_AP_SHIFT              (21U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_AP_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_AP_GATED              (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_AP_RUNNING            (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMI_SHIFT             (20U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMI_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMI_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_EMI_RUNNING           (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_ITR_SHIFT             (19U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_ITR_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_ITR_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_ITR_RUNNING           (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_CPX_SHIFT             (18U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_CPX_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_CPX_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_CPX_RUNNING           (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_MOV_SHIFT             (17U)
#define RGX_CR_CLK_STATUS1_USC_PIPE_MOV_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_CLK_STATUS1_USC_PIPE_MOV_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_PIPE_MOV_RUNNING           (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_CLK_STATUS1_CDM_PIPE_SHIFT                 (14U)
#define RGX_CR_CLK_STATUS1_CDM_PIPE_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_CLK_STATUS1_CDM_PIPE_GATED                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_CDM_PIPE_RUNNING               (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_CLK_STATUS1_TCU_L1_SHIFT                   (13U)
#define RGX_CR_CLK_STATUS1_TCU_L1_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_CLK_STATUS1_TCU_L1_GATED                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_TCU_L1_RUNNING                 (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_CLK_STATUS1_USC_L2ICACHE_SHIFT             (12U)
#define RGX_CR_CLK_STATUS1_USC_L2ICACHE_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_CLK_STATUS1_USC_L2ICACHE_GATED             (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_USC_L2ICACHE_RUNNING           (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_CLK_STATUS1_TDM_SHIFT                      (10U)
#define RGX_CR_CLK_STATUS1_TDM_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_CLK_STATUS1_TDM_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_TDM_RUNNING                    (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_CLK_STATUS1_IPF_SHIFT                      (9U)
#define RGX_CR_CLK_STATUS1_IPF_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_CLK_STATUS1_IPF_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_IPF_RUNNING                    (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_CLK_STATUS1_COMPUTE_SHIFT                  (8U)
#define RGX_CR_CLK_STATUS1_COMPUTE_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_CLK_STATUS1_COMPUTE_GATED                  (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_COMPUTE_RUNNING                (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_CLK_STATUS1_ASTC_SHIFT                     (7U)
#define RGX_CR_CLK_STATUS1_ASTC_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_CLK_STATUS1_ASTC_GATED                     (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_ASTC_RUNNING                   (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_CLK_STATUS1_PIXEL_SHIFT                    (6U)
#define RGX_CR_CLK_STATUS1_PIXEL_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_CLK_STATUS1_PIXEL_GATED                    (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_PIXEL_RUNNING                  (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_CLK_STATUS1_VERTEX_SHIFT                   (5U)
#define RGX_CR_CLK_STATUS1_VERTEX_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_CLK_STATUS1_VERTEX_GATED                   (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_VERTEX_RUNNING                 (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_CLK_STATUS1_TPF_SHIFT                      (4U)
#define RGX_CR_CLK_STATUS1_TPF_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_CLK_STATUS1_TPF_GATED                      (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_TPF_RUNNING                    (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_CLK_STATUS1_GEO_SHARED_SHIFT               (3U)
#define RGX_CR_CLK_STATUS1_GEO_SHARED_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_CLK_STATUS1_GEO_SHARED_GATED               (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_GEO_SHARED_RUNNING             (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_CLK_STATUS1_GEO_VERTEX_SHIFT               (1U)
#define RGX_CR_CLK_STATUS1_GEO_VERTEX_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_CLK_STATUS1_GEO_VERTEX_GATED               (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_GEO_VERTEX_RUNNING             (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_CLK_STATUS1_GEO_TESS_SHIFT                 (0U)
#define RGX_CR_CLK_STATUS1_GEO_TESS_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_CLK_STATUS1_GEO_TESS_GATED                 (IMG_UINT64_C(0x0000000000000000))
#define RGX_CR_CLK_STATUS1_GEO_TESS_RUNNING               (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_SOFT_RESET
*/
#define RGX_CR_SOFT_RESET                                 (0x0100U)
#define RGX_CR_SOFT_RESET_MASKFULL                        (IMG_UINT64_C(0x03FFFFE0000BDEFF))
#define RGX_CR_SOFT_RESET_RAC_SHIFT                       (57U)
#define RGX_CR_SOFT_RESET_RAC_CLRMSK                      (IMG_UINT64_C(0xFDFFFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_RAC_EN                          (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_SOFT_RESET_GEO_TESS_SHIFT                  (56U)
#define RGX_CR_SOFT_RESET_GEO_TESS_CLRMSK                 (IMG_UINT64_C(0xFEFFFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_GEO_TESS_EN                     (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_SOFT_RESET_INT_SHIFT                       (55U)
#define RGX_CR_SOFT_RESET_INT_CLRMSK                      (IMG_UINT64_C(0xFF7FFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_INT_EN                          (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_SOFT_RESET_FP_SHIFT                        (54U)
#define RGX_CR_SOFT_RESET_FP_CLRMSK                       (IMG_UINT64_C(0xFFBFFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_FP_EN                           (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_SOFT_RESET_YUV_SHIFT                       (53U)
#define RGX_CR_SOFT_RESET_YUV_CLRMSK                      (IMG_UINT64_C(0xFFDFFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_YUV_EN                          (IMG_UINT64_C(0x0020000000000000))
#define RGX_CR_SOFT_RESET_PSB_SHIFT                       (52U)
#define RGX_CR_SOFT_RESET_PSB_CLRMSK                      (IMG_UINT64_C(0xFFEFFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_PSB_EN                          (IMG_UINT64_C(0x0010000000000000))
#define RGX_CR_SOFT_RESET_ASC_SHIFT                       (51U)
#define RGX_CR_SOFT_RESET_ASC_CLRMSK                      (IMG_UINT64_C(0xFFF7FFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_ASC_EN                          (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_SOFT_RESET_RCE_SHIFT                       (50U)
#define RGX_CR_SOFT_RESET_RCE_CLRMSK                      (IMG_UINT64_C(0xFFFBFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_RCE_EN                          (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_SOFT_RESET_BSC_SHIFT                       (49U)
#define RGX_CR_SOFT_RESET_BSC_CLRMSK                      (IMG_UINT64_C(0xFFFDFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_BSC_EN                          (IMG_UINT64_C(0x0002000000000000))
#define RGX_CR_SOFT_RESET_TPU_USC_SELECT_SHIFT            (48U)
#define RGX_CR_SOFT_RESET_TPU_USC_SELECT_CLRMSK           (IMG_UINT64_C(0xFFFEFFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_TPU_USC_SELECT_EN               (IMG_UINT64_C(0x0001000000000000))
#define RGX_CR_SOFT_RESET_USC_L2ICACHE_SHIFT              (47U)
#define RGX_CR_SOFT_RESET_USC_L2ICACHE_CLRMSK             (IMG_UINT64_C(0xFFFF7FFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_USC_L2ICACHE_EN                 (IMG_UINT64_C(0x0000800000000000))
#define RGX_CR_SOFT_RESET_TCU_L1_SHIFT                    (46U)
#define RGX_CR_SOFT_RESET_TCU_L1_CLRMSK                   (IMG_UINT64_C(0xFFFFBFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_TCU_L1_EN                       (IMG_UINT64_C(0x0000400000000000))
#define RGX_CR_SOFT_RESET_BIF_TEXAS_SHIFT                 (45U)
#define RGX_CR_SOFT_RESET_BIF_TEXAS_CLRMSK                (IMG_UINT64_C(0xFFFFDFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_BIF_TEXAS_EN                    (IMG_UINT64_C(0x0000200000000000))
#define RGX_CR_SOFT_RESET_BIF_JONES_SHIFT                 (44U)
#define RGX_CR_SOFT_RESET_BIF_JONES_CLRMSK                (IMG_UINT64_C(0xFFFFEFFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_BIF_JONES_EN                    (IMG_UINT64_C(0x0000100000000000))
#define RGX_CR_SOFT_RESET_SLC_SHIFT                       (43U)
#define RGX_CR_SOFT_RESET_SLC_CLRMSK                      (IMG_UINT64_C(0xFFFFF7FFFFFFFFFF))
#define RGX_CR_SOFT_RESET_SLC_EN                          (IMG_UINT64_C(0x0000080000000000))
#define RGX_CR_SOFT_RESET_FBCACHE_SHIFT                   (42U)
#define RGX_CR_SOFT_RESET_FBCACHE_CLRMSK                  (IMG_UINT64_C(0xFFFFFBFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_FBCACHE_EN                      (IMG_UINT64_C(0x0000040000000000))
#define RGX_CR_SOFT_RESET_FBM_SHIFT                       (41U)
#define RGX_CR_SOFT_RESET_FBM_CLRMSK                      (IMG_UINT64_C(0xFFFFFDFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_FBM_EN                          (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_SOFT_RESET_FBDC_SHIFT                      (40U)
#define RGX_CR_SOFT_RESET_FBDC_CLRMSK                     (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_SOFT_RESET_FBDC_EN                         (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_SOFT_RESET_FBC_SHIFT                       (39U)
#define RGX_CR_SOFT_RESET_FBC_CLRMSK                      (IMG_UINT64_C(0xFFFFFF7FFFFFFFFF))
#define RGX_CR_SOFT_RESET_FBC_EN                          (IMG_UINT64_C(0x0000008000000000))
#define RGX_CR_SOFT_RESET_PM_SHIFT                        (38U)
#define RGX_CR_SOFT_RESET_PM_CLRMSK                       (IMG_UINT64_C(0xFFFFFFBFFFFFFFFF))
#define RGX_CR_SOFT_RESET_PM_EN                           (IMG_UINT64_C(0x0000004000000000))
#define RGX_CR_SOFT_RESET_GARTEN_SHIFT                    (37U)
#define RGX_CR_SOFT_RESET_GARTEN_CLRMSK                   (IMG_UINT64_C(0xFFFFFFDFFFFFFFFF))
#define RGX_CR_SOFT_RESET_GARTEN_EN                       (IMG_UINT64_C(0x0000002000000000))
#define RGX_CR_SOFT_RESET_PBE_SHIFT                       (19U)
#define RGX_CR_SOFT_RESET_PBE_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_SOFT_RESET_PBE_EN                          (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_SOFT_RESET_MCU_L1_SHIFT                    (17U)
#define RGX_CR_SOFT_RESET_MCU_L1_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_SOFT_RESET_MCU_L1_EN                       (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_SOFT_RESET_CDM_PIPE_SHIFT                  (16U)
#define RGX_CR_SOFT_RESET_CDM_PIPE_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_SOFT_RESET_CDM_PIPE_EN                     (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_SOFT_RESET_TDM_SHIFT                       (15U)
#define RGX_CR_SOFT_RESET_TDM_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_SOFT_RESET_TDM_EN                          (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_SOFT_RESET_ASTC_SHIFT                      (14U)
#define RGX_CR_SOFT_RESET_ASTC_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_SOFT_RESET_ASTC_EN                         (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_SOFT_RESET_PDS_SHIFT                       (12U)
#define RGX_CR_SOFT_RESET_PDS_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_SOFT_RESET_PDS_EN                          (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_SOFT_RESET_ISP_SHIFT                       (11U)
#define RGX_CR_SOFT_RESET_ISP_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_SOFT_RESET_ISP_EN                          (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_SOFT_RESET_TPF_SHIFT                       (10U)
#define RGX_CR_SOFT_RESET_TPF_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_SOFT_RESET_TPF_EN                          (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_SOFT_RESET_IPF_SHIFT                       (9U)
#define RGX_CR_SOFT_RESET_IPF_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_SOFT_RESET_IPF_EN                          (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_SOFT_RESET_GEO_SHARED_SHIFT                (7U)
#define RGX_CR_SOFT_RESET_GEO_SHARED_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_SOFT_RESET_GEO_SHARED_EN                   (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_SOFT_RESET_GEO_VERTEX_SHIFT                (6U)
#define RGX_CR_SOFT_RESET_GEO_VERTEX_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_SOFT_RESET_GEO_VERTEX_EN                   (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_SOFT_RESET_PIXEL_SHIFT                     (5U)
#define RGX_CR_SOFT_RESET_PIXEL_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_SOFT_RESET_PIXEL_EN                        (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_SOFT_RESET_COMPUTE_SHIFT                   (4U)
#define RGX_CR_SOFT_RESET_COMPUTE_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_SOFT_RESET_COMPUTE_EN                      (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_SOFT_RESET_MCU_L0_SHIFT                    (3U)
#define RGX_CR_SOFT_RESET_MCU_L0_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_SOFT_RESET_MCU_L0_EN                       (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_SOFT_RESET_TPU_SHIFT                       (2U)
#define RGX_CR_SOFT_RESET_TPU_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_SOFT_RESET_TPU_EN                          (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_SOFT_RESET_VERTEX_SHIFT                    (1U)
#define RGX_CR_SOFT_RESET_VERTEX_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_SOFT_RESET_VERTEX_EN                       (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_SOFT_RESET_USC_SHIFT                       (0U)
#define RGX_CR_SOFT_RESET_USC_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_SOFT_RESET_USC_EN                          (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_SOFT_RESET_SPU
*/
#define RGX_CR_SOFT_RESET_SPU                             (0x0108U)
#define RGX_CR_SOFT_RESET_SPU_MASKFULL                    (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_SOFT_RESET_SPU_SPU31_SHIFT                 (31U)
#define RGX_CR_SOFT_RESET_SPU_SPU31_CLRMSK                (0x7FFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU31_EN                    (0x80000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU30_SHIFT                 (30U)
#define RGX_CR_SOFT_RESET_SPU_SPU30_CLRMSK                (0xBFFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU30_EN                    (0x40000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU29_SHIFT                 (29U)
#define RGX_CR_SOFT_RESET_SPU_SPU29_CLRMSK                (0xDFFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU29_EN                    (0x20000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU28_SHIFT                 (28U)
#define RGX_CR_SOFT_RESET_SPU_SPU28_CLRMSK                (0xEFFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU28_EN                    (0x10000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU27_SHIFT                 (27U)
#define RGX_CR_SOFT_RESET_SPU_SPU27_CLRMSK                (0xF7FFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU27_EN                    (0x08000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU26_SHIFT                 (26U)
#define RGX_CR_SOFT_RESET_SPU_SPU26_CLRMSK                (0xFBFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU26_EN                    (0x04000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU25_SHIFT                 (25U)
#define RGX_CR_SOFT_RESET_SPU_SPU25_CLRMSK                (0xFDFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU25_EN                    (0x02000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU24_SHIFT                 (24U)
#define RGX_CR_SOFT_RESET_SPU_SPU24_CLRMSK                (0xFEFFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU24_EN                    (0x01000000U)
#define RGX_CR_SOFT_RESET_SPU_SPU23_SHIFT                 (23U)
#define RGX_CR_SOFT_RESET_SPU_SPU23_CLRMSK                (0xFF7FFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU23_EN                    (0x00800000U)
#define RGX_CR_SOFT_RESET_SPU_SPU22_SHIFT                 (22U)
#define RGX_CR_SOFT_RESET_SPU_SPU22_CLRMSK                (0xFFBFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU22_EN                    (0x00400000U)
#define RGX_CR_SOFT_RESET_SPU_SPU21_SHIFT                 (21U)
#define RGX_CR_SOFT_RESET_SPU_SPU21_CLRMSK                (0xFFDFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU21_EN                    (0x00200000U)
#define RGX_CR_SOFT_RESET_SPU_SPU20_SHIFT                 (20U)
#define RGX_CR_SOFT_RESET_SPU_SPU20_CLRMSK                (0xFFEFFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU20_EN                    (0x00100000U)
#define RGX_CR_SOFT_RESET_SPU_SPU19_SHIFT                 (19U)
#define RGX_CR_SOFT_RESET_SPU_SPU19_CLRMSK                (0xFFF7FFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU19_EN                    (0x00080000U)
#define RGX_CR_SOFT_RESET_SPU_SPU18_SHIFT                 (18U)
#define RGX_CR_SOFT_RESET_SPU_SPU18_CLRMSK                (0xFFFBFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU18_EN                    (0x00040000U)
#define RGX_CR_SOFT_RESET_SPU_SPU17_SHIFT                 (17U)
#define RGX_CR_SOFT_RESET_SPU_SPU17_CLRMSK                (0xFFFDFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU17_EN                    (0x00020000U)
#define RGX_CR_SOFT_RESET_SPU_SPU16_SHIFT                 (16U)
#define RGX_CR_SOFT_RESET_SPU_SPU16_CLRMSK                (0xFFFEFFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU16_EN                    (0x00010000U)
#define RGX_CR_SOFT_RESET_SPU_SPU15_SHIFT                 (15U)
#define RGX_CR_SOFT_RESET_SPU_SPU15_CLRMSK                (0xFFFF7FFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU15_EN                    (0x00008000U)
#define RGX_CR_SOFT_RESET_SPU_SPU14_SHIFT                 (14U)
#define RGX_CR_SOFT_RESET_SPU_SPU14_CLRMSK                (0xFFFFBFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU14_EN                    (0x00004000U)
#define RGX_CR_SOFT_RESET_SPU_SPU13_SHIFT                 (13U)
#define RGX_CR_SOFT_RESET_SPU_SPU13_CLRMSK                (0xFFFFDFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU13_EN                    (0x00002000U)
#define RGX_CR_SOFT_RESET_SPU_SPU12_SHIFT                 (12U)
#define RGX_CR_SOFT_RESET_SPU_SPU12_CLRMSK                (0xFFFFEFFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU12_EN                    (0x00001000U)
#define RGX_CR_SOFT_RESET_SPU_SPU11_SHIFT                 (11U)
#define RGX_CR_SOFT_RESET_SPU_SPU11_CLRMSK                (0xFFFFF7FFU)
#define RGX_CR_SOFT_RESET_SPU_SPU11_EN                    (0x00000800U)
#define RGX_CR_SOFT_RESET_SPU_SPU10_SHIFT                 (10U)
#define RGX_CR_SOFT_RESET_SPU_SPU10_CLRMSK                (0xFFFFFBFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU10_EN                    (0x00000400U)
#define RGX_CR_SOFT_RESET_SPU_SPU9_SHIFT                  (9U)
#define RGX_CR_SOFT_RESET_SPU_SPU9_CLRMSK                 (0xFFFFFDFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU9_EN                     (0x00000200U)
#define RGX_CR_SOFT_RESET_SPU_SPU8_SHIFT                  (8U)
#define RGX_CR_SOFT_RESET_SPU_SPU8_CLRMSK                 (0xFFFFFEFFU)
#define RGX_CR_SOFT_RESET_SPU_SPU8_EN                     (0x00000100U)
#define RGX_CR_SOFT_RESET_SPU_SPU7_SHIFT                  (7U)
#define RGX_CR_SOFT_RESET_SPU_SPU7_CLRMSK                 (0xFFFFFF7FU)
#define RGX_CR_SOFT_RESET_SPU_SPU7_EN                     (0x00000080U)
#define RGX_CR_SOFT_RESET_SPU_SPU6_SHIFT                  (6U)
#define RGX_CR_SOFT_RESET_SPU_SPU6_CLRMSK                 (0xFFFFFFBFU)
#define RGX_CR_SOFT_RESET_SPU_SPU6_EN                     (0x00000040U)
#define RGX_CR_SOFT_RESET_SPU_SPU5_SHIFT                  (5U)
#define RGX_CR_SOFT_RESET_SPU_SPU5_CLRMSK                 (0xFFFFFFDFU)
#define RGX_CR_SOFT_RESET_SPU_SPU5_EN                     (0x00000020U)
#define RGX_CR_SOFT_RESET_SPU_SPU4_SHIFT                  (4U)
#define RGX_CR_SOFT_RESET_SPU_SPU4_CLRMSK                 (0xFFFFFFEFU)
#define RGX_CR_SOFT_RESET_SPU_SPU4_EN                     (0x00000010U)
#define RGX_CR_SOFT_RESET_SPU_SPU3_SHIFT                  (3U)
#define RGX_CR_SOFT_RESET_SPU_SPU3_CLRMSK                 (0xFFFFFFF7U)
#define RGX_CR_SOFT_RESET_SPU_SPU3_EN                     (0x00000008U)
#define RGX_CR_SOFT_RESET_SPU_SPU2_SHIFT                  (2U)
#define RGX_CR_SOFT_RESET_SPU_SPU2_CLRMSK                 (0xFFFFFFFBU)
#define RGX_CR_SOFT_RESET_SPU_SPU2_EN                     (0x00000004U)
#define RGX_CR_SOFT_RESET_SPU_SPU1_SHIFT                  (1U)
#define RGX_CR_SOFT_RESET_SPU_SPU1_CLRMSK                 (0xFFFFFFFDU)
#define RGX_CR_SOFT_RESET_SPU_SPU1_EN                     (0x00000002U)
#define RGX_CR_SOFT_RESET_SPU_SPU0_SHIFT                  (0U)
#define RGX_CR_SOFT_RESET_SPU_SPU0_CLRMSK                 (0xFFFFFFFEU)
#define RGX_CR_SOFT_RESET_SPU_SPU0_EN                     (0x00000001U)


/*
    Register RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON
*/
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON             (0x24B0U)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_MASKFULL    (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT (30U)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK (0x3FFFFFFFU)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_EXECUTE_COUNT_SHIFT (8U)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_EXECUTE_COUNT_CLRMSK (0xC00000FFU)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT (0U)
#define RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_CLRMSK (0xFFFFFF00U)


/*
    Register RGX_CR_MULTICORE_TDM_CTRL_COMMON
*/
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON                  (0x24B8U)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_MASKFULL         (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_WORKLOAD_TYPE_SHIFT (30U)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK (0x3FFFFFFFU)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_EXECUTE_COUNT_SHIFT (8U)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_EXECUTE_COUNT_CLRMSK (0xC00000FFU)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_GPU_ENABLE_SHIFT (0U)
#define RGX_CR_MULTICORE_TDM_CTRL_COMMON_GPU_ENABLE_CLRMSK (0xFFFFFF00U)


/*
    Register RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON
*/
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON              (0x24C0U)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_MASKFULL     (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT (30U)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK (0x3FFFFFFFU)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_EXECUTE_COUNT_SHIFT (8U)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_EXECUTE_COUNT_CLRMSK (0xC00000FFU)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT (0U)
#define RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK (0xFFFFFF00U)


/*
    Register RGX_CR_MULTICORE_BROADCAST
*/
#define RGX_CR_MULTICORE_BROADCAST                        (0x24E0U)
#define RGX_CR_MULTICORE_BROADCAST_MASKFULL               (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_MULTICORE_BROADCAST_PROGRAMMER_MASK_SHIFT  (8U)
#define RGX_CR_MULTICORE_BROADCAST_PROGRAMMER_MASK_CLRMSK (0xFFFF00FFU)
#define RGX_CR_MULTICORE_BROADCAST_FIRMWARE_MASK_SHIFT    (0U)
#define RGX_CR_MULTICORE_BROADCAST_FIRMWARE_MASK_CLRMSK   (0xFFFFFF00U)


/*
    Register RGX_CR_MULTICORE
*/
#define RGX_CR_MULTICORE                                  (0x24E8U)
#define RGX_CR_MULTICORE_MASKFULL                         (IMG_UINT64_C(0x00000007FFFFFFFF))
#define RGX_CR_MULTICORE_DOMAIN_GPU_MASK_SHIFT            (27U)
#define RGX_CR_MULTICORE_DOMAIN_GPU_MASK_CLRMSK           (IMG_UINT64_C(0xFFFFFFF807FFFFFF))
#define RGX_CR_MULTICORE_PRIMARY_CORE_ID_SHIFT            (3U)
#define RGX_CR_MULTICORE_PRIMARY_CORE_ID_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFF8000007))
#define RGX_CR_MULTICORE_ID_SHIFT                         (0U)
#define RGX_CR_MULTICORE_ID_CLRMSK                        (IMG_UINT64_C(0xFFFFFFFFFFFFFFF8))


/*
    Register RGX_CR_MULTICORE_SYSTEM
*/
#define RGX_CR_MULTICORE_SYSTEM                           (0x24F0U)
#define RGX_CR_MULTICORE_SYSTEM_MASKFULL                  (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT           (0U)
#define RGX_CR_MULTICORE_SYSTEM_GPU_COUNT_CLRMSK          (0xFFFFFFF0U)


/*
    Register RGX_CR_MULTICORE_DOMAIN
*/
#define RGX_CR_MULTICORE_DOMAIN                           (0x24F8U)
#define RGX_CR_MULTICORE_DOMAIN_MASKFULL                  (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_MULTICORE_DOMAIN_GPU_COUNT_SHIFT           (0U)
#define RGX_CR_MULTICORE_DOMAIN_GPU_COUNT_CLRMSK          (0xFFFFFFF0U)


/*
    Register RGX_CR_EVENT_STATUS
*/
#define RGX_CR_EVENT_STATUS                               (0x0130U)
#define RGX_CR_EVENT_STATUS__ALRIF_V1__MASKFULL           (IMG_UINT64_C(0x00000000E007FFFF))
#define RGX_CR_EVENT_STATUS__ALRIF_V2__MASKFULL           (IMG_UINT64_C(0x00000000F80FFFFF))
#define RGX_CR_EVENT_STATUS_MASKFULL                      (IMG_UINT64_C(0x00000000E007FFFF))
#define RGX_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT      (31U)
#define RGX_CR_EVENT_STATUS_TDM_FENCE_FINISHED_CLRMSK     (0x7FFFFFFFU)
#define RGX_CR_EVENT_STATUS_TDM_FENCE_FINISHED_EN         (0x80000000U)
#define RGX_CR_EVENT_STATUS_TDM_FINISHED_SHIFT            (31U)
#define RGX_CR_EVENT_STATUS_TDM_FINISHED_CLRMSK           (0x7FFFFFFFU)
#define RGX_CR_EVENT_STATUS_TDM_FINISHED_EN               (0x80000000U)
#define RGX_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT        (30U)
#define RGX_CR_EVENT_STATUS_TDM_BUFFER_STALL_CLRMSK       (0xBFFFFFFFU)
#define RGX_CR_EVENT_STATUS_TDM_BUFFER_STALL_EN           (0x40000000U)
#define RGX_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT  (29U)
#define RGX_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_CLRMSK (0xDFFFFFFFU)
#define RGX_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_EN     (0x20000000U)
#define RGX_CR_EVENT_STATUS_RCE_FINISHED_SHIFT            (28U)
#define RGX_CR_EVENT_STATUS_RCE_FINISHED_CLRMSK           (0xEFFFFFFFU)
#define RGX_CR_EVENT_STATUS_RCE_FINISHED_EN               (0x10000000U)
#define RGX_CR_EVENT_STATUS_RCE_BARRIER_HIT_SHIFT         (27U)
#define RGX_CR_EVENT_STATUS_RCE_BARRIER_HIT_CLRMSK        (0xF7FFFFFFU)
#define RGX_CR_EVENT_STATUS_RCE_BARRIER_HIT_EN            (0x08000000U)
#define RGX_CR_EVENT_STATUS_WDT_TIMEOUT_SHIFT             (19U)
#define RGX_CR_EVENT_STATUS_WDT_TIMEOUT_CLRMSK            (0xFFF7FFFFU)
#define RGX_CR_EVENT_STATUS_WDT_TIMEOUT_EN                (0x00080000U)
#define RGX_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT (18U)
#define RGX_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_CLRMSK (0xFFFBFFFFU)
#define RGX_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_EN (0x00040000U)
#define RGX_CR_EVENT_STATUS_CDM_BARRIER_HIT_SHIFT         (18U)
#define RGX_CR_EVENT_STATUS_CDM_BARRIER_HIT_CLRMSK        (0xFFFBFFFFU)
#define RGX_CR_EVENT_STATUS_CDM_BARRIER_HIT_EN            (0x00040000U)
#define RGX_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT  (17U)
#define RGX_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_CLRMSK (0xFFFDFFFFU)
#define RGX_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_EN     (0x00020000U)
#define RGX_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT    (16U)
#define RGX_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_CLRMSK   (0xFFFEFFFFU)
#define RGX_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_EN       (0x00010000U)
#define RGX_CR_EVENT_STATUS_USC_TRIGGER_SHIFT             (15U)
#define RGX_CR_EVENT_STATUS_USC_TRIGGER_CLRMSK            (0xFFFF7FFFU)
#define RGX_CR_EVENT_STATUS_USC_TRIGGER_EN                (0x00008000U)
#define RGX_CR_EVENT_STATUS_FAULT_FW_SHIFT                (14U)
#define RGX_CR_EVENT_STATUS_FAULT_FW_CLRMSK               (0xFFFFBFFFU)
#define RGX_CR_EVENT_STATUS_FAULT_FW_EN                   (0x00004000U)
#define RGX_CR_EVENT_STATUS_GPIO_ACK_SHIFT                (13U)
#define RGX_CR_EVENT_STATUS_GPIO_ACK_CLRMSK               (0xFFFFDFFFU)
#define RGX_CR_EVENT_STATUS_GPIO_ACK_EN                   (0x00002000U)
#define RGX_CR_EVENT_STATUS_GPIO_REQ_SHIFT                (12U)
#define RGX_CR_EVENT_STATUS_GPIO_REQ_CLRMSK               (0xFFFFEFFFU)
#define RGX_CR_EVENT_STATUS_GPIO_REQ_EN                   (0x00001000U)
#define RGX_CR_EVENT_STATUS_POWER_ABORT_SHIFT             (11U)
#define RGX_CR_EVENT_STATUS_POWER_ABORT_CLRMSK            (0xFFFFF7FFU)
#define RGX_CR_EVENT_STATUS_POWER_ABORT_EN                (0x00000800U)
#define RGX_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT          (10U)
#define RGX_CR_EVENT_STATUS_POWER_COMPLETE_CLRMSK         (0xFFFFFBFFU)
#define RGX_CR_EVENT_STATUS_POWER_COMPLETE_EN             (0x00000400U)
#define RGX_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT          (9U)
#define RGX_CR_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK         (0xFFFFFDFFU)
#define RGX_CR_EVENT_STATUS_MMU_PAGE_FAULT_EN             (0x00000200U)
#define RGX_CR_EVENT_STATUS_PM_FRAG_DONE_SHIFT            (8U)
#define RGX_CR_EVENT_STATUS_PM_FRAG_DONE_CLRMSK           (0xFFFFFEFFU)
#define RGX_CR_EVENT_STATUS_PM_FRAG_DONE_EN               (0x00000100U)
#define RGX_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT        (7U)
#define RGX_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_CLRMSK       (0xFFFFFF7FU)
#define RGX_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_EN           (0x00000080U)
#define RGX_CR_EVENT_STATUS_TA_TERMINATE_SHIFT            (6U)
#define RGX_CR_EVENT_STATUS_TA_TERMINATE_CLRMSK           (0xFFFFFFBFU)
#define RGX_CR_EVENT_STATUS_TA_TERMINATE_EN               (0x00000040U)
#define RGX_CR_EVENT_STATUS_TA_FINISHED_SHIFT             (5U)
#define RGX_CR_EVENT_STATUS_TA_FINISHED_CLRMSK            (0xFFFFFFDFU)
#define RGX_CR_EVENT_STATUS_TA_FINISHED_EN                (0x00000020U)
#define RGX_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT       (4U)
#define RGX_CR_EVENT_STATUS_ISP_END_MACROTILE_CLRMSK      (0xFFFFFFEFU)
#define RGX_CR_EVENT_STATUS_ISP_END_MACROTILE_EN          (0x00000010U)
#define RGX_CR_EVENT_STATUS_IPP_END_RENDER_SENT_SHIFT     (4U)
#define RGX_CR_EVENT_STATUS_IPP_END_RENDER_SENT_CLRMSK    (0xFFFFFFEFU)
#define RGX_CR_EVENT_STATUS_IPP_END_RENDER_SENT_EN        (0x00000010U)
#define RGX_CR_EVENT_STATUS_ISP_END_RENDER_SHIFT          (3U)
#define RGX_CR_EVENT_STATUS_ISP_END_RENDER_CLRMSK         (0xFFFFFFF7U)
#define RGX_CR_EVENT_STATUS_ISP_END_RENDER_EN             (0x00000008U)
#define RGX_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT        (2U)
#define RGX_CR_EVENT_STATUS_COMPUTE_FINISHED_CLRMSK       (0xFFFFFFFBU)
#define RGX_CR_EVENT_STATUS_COMPUTE_FINISHED_EN           (0x00000004U)
#define RGX_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT         (1U)
#define RGX_CR_EVENT_STATUS_KERNEL_FINISHED_CLRMSK        (0xFFFFFFFDU)
#define RGX_CR_EVENT_STATUS_KERNEL_FINISHED_EN            (0x00000002U)
#define RGX_CR_EVENT_STATUS_TE_END_SHIFT                  (1U)
#define RGX_CR_EVENT_STATUS_TE_END_CLRMSK                 (0xFFFFFFFDU)
#define RGX_CR_EVENT_STATUS_TE_END_EN                     (0x00000002U)
#define RGX_CR_EVENT_STATUS_FAULT_GPU_SHIFT               (0U)
#define RGX_CR_EVENT_STATUS_FAULT_GPU_CLRMSK              (0xFFFFFFFEU)
#define RGX_CR_EVENT_STATUS_FAULT_GPU_EN                  (0x00000001U)


/*
    Register RGX_CR_EVENT_CLEAR
*/
#define RGX_CR_EVENT_CLEAR                                (0x0138U)
#define RGX_CR_EVENT_CLEAR__ALRIF_V1__MASKFULL            (IMG_UINT64_C(0x00000000E007FFFF))
#define RGX_CR_EVENT_CLEAR__ALRIF_V2__MASKFULL            (IMG_UINT64_C(0x00000000F80FFFFF))
#define RGX_CR_EVENT_CLEAR_MASKFULL                       (IMG_UINT64_C(0x00000000E007FFFF))
#define RGX_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT       (31U)
#define RGX_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK      (0x7FFFFFFFU)
#define RGX_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN          (0x80000000U)
#define RGX_CR_EVENT_CLEAR_TDM_FINISHED_SHIFT             (31U)
#define RGX_CR_EVENT_CLEAR_TDM_FINISHED_CLRMSK            (0x7FFFFFFFU)
#define RGX_CR_EVENT_CLEAR_TDM_FINISHED_EN                (0x80000000U)
#define RGX_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT         (30U)
#define RGX_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK        (0xBFFFFFFFU)
#define RGX_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN            (0x40000000U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT   (29U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK  (0xDFFFFFFFU)
#define RGX_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN      (0x20000000U)
#define RGX_CR_EVENT_CLEAR_RCE_FINISHED_SHIFT             (28U)
#define RGX_CR_EVENT_CLEAR_RCE_FINISHED_CLRMSK            (0xEFFFFFFFU)
#define RGX_CR_EVENT_CLEAR_RCE_FINISHED_EN                (0x10000000U)
#define RGX_CR_EVENT_CLEAR_RCE_BARRIER_HIT_SHIFT          (27U)
#define RGX_CR_EVENT_CLEAR_RCE_BARRIER_HIT_CLRMSK         (0xF7FFFFFFU)
#define RGX_CR_EVENT_CLEAR_RCE_BARRIER_HIT_EN             (0x08000000U)
#define RGX_CR_EVENT_CLEAR_WDT_TIMEOUT_SHIFT              (19U)
#define RGX_CR_EVENT_CLEAR_WDT_TIMEOUT_CLRMSK             (0xFFF7FFFFU)
#define RGX_CR_EVENT_CLEAR_WDT_TIMEOUT_EN                 (0x00080000U)
#define RGX_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT (18U)
#define RGX_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK (0xFFFBFFFFU)
#define RGX_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN  (0x00040000U)
#define RGX_CR_EVENT_CLEAR_CDM_BARRIER_HIT_SHIFT          (18U)
#define RGX_CR_EVENT_CLEAR_CDM_BARRIER_HIT_CLRMSK         (0xFFFBFFFFU)
#define RGX_CR_EVENT_CLEAR_CDM_BARRIER_HIT_EN             (0x00040000U)
#define RGX_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT   (17U)
#define RGX_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK  (0xFFFDFFFFU)
#define RGX_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN      (0x00020000U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT     (16U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK    (0xFFFEFFFFU)
#define RGX_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN        (0x00010000U)
#define RGX_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT              (15U)
#define RGX_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK             (0xFFFF7FFFU)
#define RGX_CR_EVENT_CLEAR_USC_TRIGGER_EN                 (0x00008000U)
#define RGX_CR_EVENT_CLEAR_FAULT_FW_SHIFT                 (14U)
#define RGX_CR_EVENT_CLEAR_FAULT_FW_CLRMSK                (0xFFFFBFFFU)
#define RGX_CR_EVENT_CLEAR_FAULT_FW_EN                    (0x00004000U)
#define RGX_CR_EVENT_CLEAR_GPIO_ACK_SHIFT                 (13U)
#define RGX_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK                (0xFFFFDFFFU)
#define RGX_CR_EVENT_CLEAR_GPIO_ACK_EN                    (0x00002000U)
#define RGX_CR_EVENT_CLEAR_GPIO_REQ_SHIFT                 (12U)
#define RGX_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK                (0xFFFFEFFFU)
#define RGX_CR_EVENT_CLEAR_GPIO_REQ_EN                    (0x00001000U)
#define RGX_CR_EVENT_CLEAR_POWER_ABORT_SHIFT              (11U)
#define RGX_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK             (0xFFFFF7FFU)
#define RGX_CR_EVENT_CLEAR_POWER_ABORT_EN                 (0x00000800U)
#define RGX_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT           (10U)
#define RGX_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK          (0xFFFFFBFFU)
#define RGX_CR_EVENT_CLEAR_POWER_COMPLETE_EN              (0x00000400U)
#define RGX_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT           (9U)
#define RGX_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK          (0xFFFFFDFFU)
#define RGX_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN              (0x00000200U)
#define RGX_CR_EVENT_CLEAR_PM_FRAG_DONE_SHIFT             (8U)
#define RGX_CR_EVENT_CLEAR_PM_FRAG_DONE_CLRMSK            (0xFFFFFEFFU)
#define RGX_CR_EVENT_CLEAR_PM_FRAG_DONE_EN                (0x00000100U)
#define RGX_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT         (7U)
#define RGX_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK        (0xFFFFFF7FU)
#define RGX_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN            (0x00000080U)
#define RGX_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT             (6U)
#define RGX_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK            (0xFFFFFFBFU)
#define RGX_CR_EVENT_CLEAR_TA_TERMINATE_EN                (0x00000040U)
#define RGX_CR_EVENT_CLEAR_TA_FINISHED_SHIFT              (5U)
#define RGX_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK             (0xFFFFFFDFU)
#define RGX_CR_EVENT_CLEAR_TA_FINISHED_EN                 (0x00000020U)
#define RGX_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT        (4U)
#define RGX_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK       (0xFFFFFFEFU)
#define RGX_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN           (0x00000010U)
#define RGX_CR_EVENT_CLEAR_IPP_END_RENDER_SENT_SHIFT      (4U)
#define RGX_CR_EVENT_CLEAR_IPP_END_RENDER_SENT_CLRMSK     (0xFFFFFFEFU)
#define RGX_CR_EVENT_CLEAR_IPP_END_RENDER_SENT_EN         (0x00000010U)
#define RGX_CR_EVENT_CLEAR_ISP_END_RENDER_SHIFT           (3U)
#define RGX_CR_EVENT_CLEAR_ISP_END_RENDER_CLRMSK          (0xFFFFFFF7U)
#define RGX_CR_EVENT_CLEAR_ISP_END_RENDER_EN              (0x00000008U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT         (2U)
#define RGX_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK        (0xFFFFFFFBU)
#define RGX_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN            (0x00000004U)
#define RGX_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT          (1U)
#define RGX_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK         (0xFFFFFFFDU)
#define RGX_CR_EVENT_CLEAR_KERNEL_FINISHED_EN             (0x00000002U)
#define RGX_CR_EVENT_CLEAR_TE_END_SHIFT                   (1U)
#define RGX_CR_EVENT_CLEAR_TE_END_CLRMSK                  (0xFFFFFFFDU)
#define RGX_CR_EVENT_CLEAR_TE_END_EN                      (0x00000002U)
#define RGX_CR_EVENT_CLEAR_FAULT_GPU_SHIFT                (0U)
#define RGX_CR_EVENT_CLEAR_FAULT_GPU_CLRMSK               (0xFFFFFFFEU)
#define RGX_CR_EVENT_CLEAR_FAULT_GPU_EN                   (0x00000001U)


/*
    Register RGX_CR_TIMER
*/
#define RGX_CR_TIMER                                      (0x0160U)
#define RGX_CR_TIMER_MASKFULL                             (IMG_UINT64_C(0x8000FFFFFFFFFFFF))
#define RGX_CR_TIMER_BIT31_SHIFT                          (63U)
#define RGX_CR_TIMER_BIT31_CLRMSK                         (IMG_UINT64_C(0x7FFFFFFFFFFFFFFF))
#define RGX_CR_TIMER_BIT31_EN                             (IMG_UINT64_C(0x8000000000000000))
#define RGX_CR_TIMER_VALUE_SHIFT                          (0U)
#define RGX_CR_TIMER_VALUE_CLRMSK                         (IMG_UINT64_C(0xFFFF000000000000))


/*
    Register RGX_CR_FAULT_FW_STATUS
*/
#define RGX_CR_FAULT_FW_STATUS                            (0x0170U)
#define RGX_CR_FAULT_FW_STATUS_MASKFULL                   (IMG_UINT64_C(0x000000000007000F))
#define RGX_CR_FAULT_FW_STATUS_META_CORRECT_SHIFT         (18U)
#define RGX_CR_FAULT_FW_STATUS_META_CORRECT_CLRMSK        (0xFFFBFFFFU)
#define RGX_CR_FAULT_FW_STATUS_META_CORRECT_EN            (0x00040000U)
#define RGX_CR_FAULT_FW_STATUS_SLC_CORRECT_SHIFT          (17U)
#define RGX_CR_FAULT_FW_STATUS_SLC_CORRECT_CLRMSK         (0xFFFDFFFFU)
#define RGX_CR_FAULT_FW_STATUS_SLC_CORRECT_EN             (0x00020000U)
#define RGX_CR_FAULT_FW_STATUS_MMU_CORRECT_SHIFT          (16U)
#define RGX_CR_FAULT_FW_STATUS_MMU_CORRECT_CLRMSK         (0xFFFEFFFFU)
#define RGX_CR_FAULT_FW_STATUS_MMU_CORRECT_EN             (0x00010000U)
#define RGX_CR_FAULT_FW_STATUS_LOCKSTEP_DETECT_SHIFT      (3U)
#define RGX_CR_FAULT_FW_STATUS_LOCKSTEP_DETECT_CLRMSK     (0xFFFFFFF7U)
#define RGX_CR_FAULT_FW_STATUS_LOCKSTEP_DETECT_EN         (0x00000008U)
#define RGX_CR_FAULT_FW_STATUS_META_DETECT_SHIFT          (2U)
#define RGX_CR_FAULT_FW_STATUS_META_DETECT_CLRMSK         (0xFFFFFFFBU)
#define RGX_CR_FAULT_FW_STATUS_META_DETECT_EN             (0x00000004U)
#define RGX_CR_FAULT_FW_STATUS_SLC_DETECT_SHIFT           (1U)
#define RGX_CR_FAULT_FW_STATUS_SLC_DETECT_CLRMSK          (0xFFFFFFFDU)
#define RGX_CR_FAULT_FW_STATUS_SLC_DETECT_EN              (0x00000002U)
#define RGX_CR_FAULT_FW_STATUS_MMU_DETECT_SHIFT           (0U)
#define RGX_CR_FAULT_FW_STATUS_MMU_DETECT_CLRMSK          (0xFFFFFFFEU)
#define RGX_CR_FAULT_FW_STATUS_MMU_DETECT_EN              (0x00000001U)


/*
    Register RGX_CR_FAULT_FW_CLEAR
*/
#define RGX_CR_FAULT_FW_CLEAR                             (0x0178U)
#define RGX_CR_FAULT_FW_CLEAR_MASKFULL                    (IMG_UINT64_C(0x000000000007000F))
#define RGX_CR_FAULT_FW_CLEAR_META_CORRECT_SHIFT          (18U)
#define RGX_CR_FAULT_FW_CLEAR_META_CORRECT_CLRMSK         (0xFFFBFFFFU)
#define RGX_CR_FAULT_FW_CLEAR_META_CORRECT_EN             (0x00040000U)
#define RGX_CR_FAULT_FW_CLEAR_SLC_CORRECT_SHIFT           (17U)
#define RGX_CR_FAULT_FW_CLEAR_SLC_CORRECT_CLRMSK          (0xFFFDFFFFU)
#define RGX_CR_FAULT_FW_CLEAR_SLC_CORRECT_EN              (0x00020000U)
#define RGX_CR_FAULT_FW_CLEAR_MMU_CORRECT_SHIFT           (16U)
#define RGX_CR_FAULT_FW_CLEAR_MMU_CORRECT_CLRMSK          (0xFFFEFFFFU)
#define RGX_CR_FAULT_FW_CLEAR_MMU_CORRECT_EN              (0x00010000U)
#define RGX_CR_FAULT_FW_CLEAR_LOCKSTEP_DETECT_SHIFT       (3U)
#define RGX_CR_FAULT_FW_CLEAR_LOCKSTEP_DETECT_CLRMSK      (0xFFFFFFF7U)
#define RGX_CR_FAULT_FW_CLEAR_LOCKSTEP_DETECT_EN          (0x00000008U)
#define RGX_CR_FAULT_FW_CLEAR_META_DETECT_SHIFT           (2U)
#define RGX_CR_FAULT_FW_CLEAR_META_DETECT_CLRMSK          (0xFFFFFFFBU)
#define RGX_CR_FAULT_FW_CLEAR_META_DETECT_EN              (0x00000004U)
#define RGX_CR_FAULT_FW_CLEAR_SLC_DETECT_SHIFT            (1U)
#define RGX_CR_FAULT_FW_CLEAR_SLC_DETECT_CLRMSK           (0xFFFFFFFDU)
#define RGX_CR_FAULT_FW_CLEAR_SLC_DETECT_EN               (0x00000002U)
#define RGX_CR_FAULT_FW_CLEAR_MMU_DETECT_SHIFT            (0U)
#define RGX_CR_FAULT_FW_CLEAR_MMU_DETECT_CLRMSK           (0xFFFFFFFEU)
#define RGX_CR_FAULT_FW_CLEAR_MMU_DETECT_EN               (0x00000001U)


/*
    Register RGX_CR_JONES_RAM_STATUS
*/
#define RGX_CR_JONES_RAM_STATUS                           (0x1148U)
#define RGX_CR_JONES_RAM_STATUS_MASKFULL                  (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_JONES_RAM_STATUS_GARTEN_SHIFT              (8U)
#define RGX_CR_JONES_RAM_STATUS_GARTEN_CLRMSK             (0xFFFFFEFFU)
#define RGX_CR_JONES_RAM_STATUS_GARTEN_EN                 (0x00000100U)
#define RGX_CR_JONES_RAM_STATUS_TDM_SHIFT                 (7U)
#define RGX_CR_JONES_RAM_STATUS_TDM_CLRMSK                (0xFFFFFF7FU)
#define RGX_CR_JONES_RAM_STATUS_TDM_EN                    (0x00000080U)
#define RGX_CR_JONES_RAM_STATUS_VERTEX_SHIFT              (6U)
#define RGX_CR_JONES_RAM_STATUS_VERTEX_CLRMSK             (0xFFFFFFBFU)
#define RGX_CR_JONES_RAM_STATUS_VERTEX_EN                 (0x00000040U)
#define RGX_CR_JONES_RAM_STATUS_PIXEL_SHIFT               (5U)
#define RGX_CR_JONES_RAM_STATUS_PIXEL_CLRMSK              (0xFFFFFFDFU)
#define RGX_CR_JONES_RAM_STATUS_PIXEL_EN                  (0x00000020U)
#define RGX_CR_JONES_RAM_STATUS_COMPUTE_SHIFT             (4U)
#define RGX_CR_JONES_RAM_STATUS_COMPUTE_CLRMSK            (0xFFFFFFEFU)
#define RGX_CR_JONES_RAM_STATUS_COMPUTE_EN                (0x00000010U)
#define RGX_CR_JONES_RAM_STATUS_FBCDC_SHIFT               (3U)
#define RGX_CR_JONES_RAM_STATUS_FBCDC_CLRMSK              (0xFFFFFFF7U)
#define RGX_CR_JONES_RAM_STATUS_FBCDC_EN                  (0x00000008U)
#define RGX_CR_JONES_RAM_STATUS_PM_SHIFT                  (2U)
#define RGX_CR_JONES_RAM_STATUS_PM_CLRMSK                 (0xFFFFFFFBU)
#define RGX_CR_JONES_RAM_STATUS_PM_EN                     (0x00000004U)
#define RGX_CR_JONES_RAM_STATUS_BIF_SHIFT                 (1U)
#define RGX_CR_JONES_RAM_STATUS_BIF_CLRMSK                (0xFFFFFFFDU)
#define RGX_CR_JONES_RAM_STATUS_BIF_EN                    (0x00000002U)
#define RGX_CR_JONES_RAM_STATUS_SLC_SHIFT                 (0U)
#define RGX_CR_JONES_RAM_STATUS_SLC_CLRMSK                (0xFFFFFFFEU)
#define RGX_CR_JONES_RAM_STATUS_SLC_EN                    (0x00000001U)


/*
    Register RGX_CR_JONES_RAM_INIT_KICK
*/
#define RGX_CR_JONES_RAM_INIT_KICK                        (0x1158U)
#define RGX_CR_JONES_RAM_INIT_KICK_MASKFULL               (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_JONES_RAM_INIT_KICK_GARTEN_SHIFT           (8U)
#define RGX_CR_JONES_RAM_INIT_KICK_GARTEN_CLRMSK          (0xFFFFFEFFU)
#define RGX_CR_JONES_RAM_INIT_KICK_GARTEN_EN              (0x00000100U)
#define RGX_CR_JONES_RAM_INIT_KICK_TDM_SHIFT              (7U)
#define RGX_CR_JONES_RAM_INIT_KICK_TDM_CLRMSK             (0xFFFFFF7FU)
#define RGX_CR_JONES_RAM_INIT_KICK_TDM_EN                 (0x00000080U)
#define RGX_CR_JONES_RAM_INIT_KICK_VERTEX_SHIFT           (6U)
#define RGX_CR_JONES_RAM_INIT_KICK_VERTEX_CLRMSK          (0xFFFFFFBFU)
#define RGX_CR_JONES_RAM_INIT_KICK_VERTEX_EN              (0x00000040U)
#define RGX_CR_JONES_RAM_INIT_KICK_PIXEL_SHIFT            (5U)
#define RGX_CR_JONES_RAM_INIT_KICK_PIXEL_CLRMSK           (0xFFFFFFDFU)
#define RGX_CR_JONES_RAM_INIT_KICK_PIXEL_EN               (0x00000020U)
#define RGX_CR_JONES_RAM_INIT_KICK_COMPUTE_SHIFT          (4U)
#define RGX_CR_JONES_RAM_INIT_KICK_COMPUTE_CLRMSK         (0xFFFFFFEFU)
#define RGX_CR_JONES_RAM_INIT_KICK_COMPUTE_EN             (0x00000010U)
#define RGX_CR_JONES_RAM_INIT_KICK_FBCDC_SHIFT            (3U)
#define RGX_CR_JONES_RAM_INIT_KICK_FBCDC_CLRMSK           (0xFFFFFFF7U)
#define RGX_CR_JONES_RAM_INIT_KICK_FBCDC_EN               (0x00000008U)
#define RGX_CR_JONES_RAM_INIT_KICK_PM_SHIFT               (2U)
#define RGX_CR_JONES_RAM_INIT_KICK_PM_CLRMSK              (0xFFFFFFFBU)
#define RGX_CR_JONES_RAM_INIT_KICK_PM_EN                  (0x00000004U)
#define RGX_CR_JONES_RAM_INIT_KICK_BIF_SHIFT              (1U)
#define RGX_CR_JONES_RAM_INIT_KICK_BIF_CLRMSK             (0xFFFFFFFDU)
#define RGX_CR_JONES_RAM_INIT_KICK_BIF_EN                 (0x00000002U)
#define RGX_CR_JONES_RAM_INIT_KICK_SLC_SHIFT              (0U)
#define RGX_CR_JONES_RAM_INIT_KICK_SLC_CLRMSK             (0xFFFFFFFEU)
#define RGX_CR_JONES_RAM_INIT_KICK_SLC_EN                 (0x00000001U)


/*
    Register RGX_CR_PM_PARTIAL_RENDER_ENABLE
*/
#define RGX_CR_PM_PARTIAL_RENDER_ENABLE                   (0x0338U)
#define RGX_CR_PM_PARTIAL_RENDER_ENABLE_MASKFULL          (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT          (0U)
#define RGX_CR_PM_PARTIAL_RENDER_ENABLE_OP_CLRMSK         (0xFFFFFFFEU)
#define RGX_CR_PM_PARTIAL_RENDER_ENABLE_OP_EN             (0x00000001U)


/*
    Register RGX_CR_CDM_CONTEXT_STORE_STATUS
*/
#define RGX_CR_CDM_CONTEXT_STORE_STATUS                   (0x04A0U)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_MASKFULL          (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT (1U)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK (0xFFFFFFFDU)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN    (0x00000002U)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT    (0U)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK   (0xFFFFFFFEU)
#define RGX_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_EN       (0x00000001U)


/*
    Register RGX_CR_CDM_CONTEXT_PDS0
*/
#define RGX_CR_CDM_CONTEXT_PDS0                           (0x04A8U)
#define RGX_CR_CDM_CONTEXT_PDS0_MASKFULL                  (IMG_UINT64_C(0xFFFFFFF0FFFFFFF0))
#define RGX_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT           (36U)
#define RGX_CR_CDM_CONTEXT_PDS0_DATA_ADDR_CLRMSK          (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT      (4U)
#define RGX_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE       (16U)
#define RGX_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT           (4U)
#define RGX_CR_CDM_CONTEXT_PDS0_CODE_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT      (4U)
#define RGX_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE       (16U)


/*
    Register RGX_CR_CDM_CONTEXT_PDS1
*/
#define RGX_CR_CDM_CONTEXT_PDS1                           (0x04B0U)
#define RGX_CR_CDM_CONTEXT_PDS1_MASKFULL                  (IMG_UINT64_C(0x00000001FFFFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT         (32U)
#define RGX_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_CLRMSK        (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_EN            (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT         (31U)
#define RGX_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_CLRMSK        (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_EN            (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT              (30U)
#define RGX_CR_CDM_CONTEXT_PDS1_TARGET_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_TARGET_EN                 (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT        (23U)
#define RGX_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC07FFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_ALIGNSHIFT   (1U)
#define RGX_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_ALIGNSIZE    (2U)
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_TYPE_SHIFT      (22U)
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_TYPE_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_TYPE_EN         (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_SIZE_SHIFT      (11U)
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_SIZE_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFFFC007FF))
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_SIZE_ALIGNSHIFT (4U)
#define RGX_CR_CDM_CONTEXT_PDS1_USC_ALLOC_SIZE_ALIGNSIZE  (16U)
#define RGX_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT           (6U)
#define RGX_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFFFFF83F))
#define RGX_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_ALIGNSHIFT      (1U)
#define RGX_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_ALIGNSIZE       (2U)
#define RGX_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT           (0U)
#define RGX_CR_CDM_CONTEXT_PDS1_DATA_SIZE_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFFFFFFC0))
#define RGX_CR_CDM_CONTEXT_PDS1_DATA_SIZE_ALIGNSHIFT      (2U)
#define RGX_CR_CDM_CONTEXT_PDS1_DATA_SIZE_ALIGNSIZE       (4U)


/*
    Register RGX_CR_CDM_CONTEXT_LOAD_PDS0
*/
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0                      (0x04D8U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_MASKFULL             (IMG_UINT64_C(0xFFFFFFF0FFFFFFF0))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT      (36U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_CLRMSK     (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT (4U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE  (16U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT      (4U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_CLRMSK     (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT (4U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE  (16U)


/*
    Register RGX_CR_CDM_CONTEXT_LOAD_PDS1
*/
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1                      (0x04E0U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_MASKFULL             (IMG_UINT64_C(0x00000001BFFFFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT    (32U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_CLRMSK   (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_EN       (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT    (31U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_CLRMSK   (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_EN       (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT   (23U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFC07FFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_ALIGNSHIFT (1U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_ALIGNSIZE (2U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_TYPE_SHIFT (22U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_TYPE_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_TYPE_EN    (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_SIZE_SHIFT (11U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_SIZE_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFC007FF))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_SIZE_ALIGNSHIFT (6U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_USC_ALLOC_SIZE_ALIGNSIZE (64U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT      (6U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFFFFFF83F))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_ALIGNSHIFT (1U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_ALIGNSIZE  (2U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT      (0U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFFFFFFFC0))
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_ALIGNSHIFT (2U)
#define RGX_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_ALIGNSIZE  (4U)


/*
    Register RGX_CR_CDM_TERMINATE_PDS
*/
#define RGX_CR_CDM_TERMINATE_PDS                          (0x04B8U)
#define RGX_CR_CDM_TERMINATE_PDS_MASKFULL                 (IMG_UINT64_C(0xFFFFFFF0FFFFFFF0))
#define RGX_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT          (36U)
#define RGX_CR_CDM_TERMINATE_PDS_DATA_ADDR_CLRMSK         (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT     (4U)
#define RGX_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE      (16U)
#define RGX_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT          (4U)
#define RGX_CR_CDM_TERMINATE_PDS_CODE_ADDR_CLRMSK         (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT     (4U)
#define RGX_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE      (16U)


/*
    Register RGX_CR_CDM_TERMINATE_PDS1
*/
#define RGX_CR_CDM_TERMINATE_PDS1                         (0x04C0U)
#define RGX_CR_CDM_TERMINATE_PDS1_MASKFULL                (IMG_UINT64_C(0x00000001BFFFFFFF))
#define RGX_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT       (32U)
#define RGX_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_CLRMSK      (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_EN          (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT       (31U)
#define RGX_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_CLRMSK      (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_EN          (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT      (23U)
#define RGX_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFC07FFFFF))
#define RGX_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_ALIGNSHIFT (1U)
#define RGX_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_ALIGNSIZE  (2U)
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_TYPE_SHIFT    (22U)
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_TYPE_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_TYPE_EN       (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_SIZE_SHIFT    (11U)
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_SIZE_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFFFC007FF))
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_SIZE_ALIGNSHIFT (6U)
#define RGX_CR_CDM_TERMINATE_PDS1_USC_ALLOC_SIZE_ALIGNSIZE (64U)
#define RGX_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT         (6U)
#define RGX_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFF83F))
#define RGX_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_ALIGNSHIFT    (1U)
#define RGX_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_ALIGNSIZE     (2U)
#define RGX_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT         (0U)
#define RGX_CR_CDM_TERMINATE_PDS1_DATA_SIZE_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFC0))
#define RGX_CR_CDM_TERMINATE_PDS1_DATA_SIZE_ALIGNSHIFT    (2U)
#define RGX_CR_CDM_TERMINATE_PDS1_DATA_SIZE_ALIGNSIZE     (4U)


/*
    Register group: RGX_CR_SCRATCH, with 16 repeats
*/
#define RGX_CR_SCRATCH_REPEATCOUNT                        (16U)
/*
    Register RGX_CR_SCRATCH0
*/
#define RGX_CR_SCRATCH0                                   (0x0800U)
#define RGX_CR_SCRATCH0_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH0_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH0_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH1
*/
#define RGX_CR_SCRATCH1                                   (0x0808U)
#define RGX_CR_SCRATCH1_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH1_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH1_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH2
*/
#define RGX_CR_SCRATCH2                                   (0x0810U)
#define RGX_CR_SCRATCH2_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH2_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH2_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH3
*/
#define RGX_CR_SCRATCH3                                   (0x0818U)
#define RGX_CR_SCRATCH3_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH3_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH3_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH4
*/
#define RGX_CR_SCRATCH4                                   (0x0820U)
#define RGX_CR_SCRATCH4_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH4_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH4_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH5
*/
#define RGX_CR_SCRATCH5                                   (0x0828U)
#define RGX_CR_SCRATCH5_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH5_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH5_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH6
*/
#define RGX_CR_SCRATCH6                                   (0x0830U)
#define RGX_CR_SCRATCH6_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH6_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH6_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH7
*/
#define RGX_CR_SCRATCH7                                   (0x0838U)
#define RGX_CR_SCRATCH7_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH7_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH7_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH8
*/
#define RGX_CR_SCRATCH8                                   (0x0840U)
#define RGX_CR_SCRATCH8_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH8_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH8_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH9
*/
#define RGX_CR_SCRATCH9                                   (0x0848U)
#define RGX_CR_SCRATCH9_MASKFULL                          (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH9_DATA_SHIFT                        (0U)
#define RGX_CR_SCRATCH9_DATA_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH10
*/
#define RGX_CR_SCRATCH10                                  (0x0850U)
#define RGX_CR_SCRATCH10_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH10_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH10_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH11
*/
#define RGX_CR_SCRATCH11                                  (0x0858U)
#define RGX_CR_SCRATCH11_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH11_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH11_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH12
*/
#define RGX_CR_SCRATCH12                                  (0x0860U)
#define RGX_CR_SCRATCH12_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH12_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH12_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH13
*/
#define RGX_CR_SCRATCH13                                  (0x0868U)
#define RGX_CR_SCRATCH13_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH13_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH13_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH14
*/
#define RGX_CR_SCRATCH14                                  (0x0870U)
#define RGX_CR_SCRATCH14_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH14_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH14_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_SCRATCH15
*/
#define RGX_CR_SCRATCH15                                  (0x0878U)
#define RGX_CR_SCRATCH15_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SCRATCH15_DATA_SHIFT                       (0U)
#define RGX_CR_SCRATCH15_DATA_CLRMSK                      (IMG_UINT64_C(0x0000000000000000))


/*
    Register group: RGX_CR_OS0_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS0_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS0_SCRATCH0
*/
#define RGX_CR_OS0_SCRATCH0                               (0x0880U)
#define RGX_CR_OS0_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS0_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS0_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS0_SCRATCH1
*/
#define RGX_CR_OS0_SCRATCH1                               (0x0888U)
#define RGX_CR_OS0_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS0_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS0_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS0_SCRATCH2
*/
#define RGX_CR_OS0_SCRATCH2                               (0x0890U)
#define RGX_CR_OS0_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS0_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS0_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS0_SCRATCH3
*/
#define RGX_CR_OS0_SCRATCH3                               (0x0898U)
#define RGX_CR_OS0_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS0_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS0_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS1_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS1_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS1_SCRATCH0
*/
#define RGX_CR_OS1_SCRATCH0                               (0x10880U)
#define RGX_CR_OS1_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS1_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS1_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS1_SCRATCH1
*/
#define RGX_CR_OS1_SCRATCH1                               (0x10888U)
#define RGX_CR_OS1_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS1_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS1_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS1_SCRATCH2
*/
#define RGX_CR_OS1_SCRATCH2                               (0x10890U)
#define RGX_CR_OS1_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS1_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS1_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS1_SCRATCH3
*/
#define RGX_CR_OS1_SCRATCH3                               (0x10898U)
#define RGX_CR_OS1_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS1_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS1_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS2_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS2_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS2_SCRATCH0
*/
#define RGX_CR_OS2_SCRATCH0                               (0x20880U)
#define RGX_CR_OS2_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS2_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS2_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS2_SCRATCH1
*/
#define RGX_CR_OS2_SCRATCH1                               (0x20888U)
#define RGX_CR_OS2_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS2_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS2_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS2_SCRATCH2
*/
#define RGX_CR_OS2_SCRATCH2                               (0x20890U)
#define RGX_CR_OS2_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS2_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS2_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS2_SCRATCH3
*/
#define RGX_CR_OS2_SCRATCH3                               (0x20898U)
#define RGX_CR_OS2_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS2_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS2_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS3_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS3_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS3_SCRATCH0
*/
#define RGX_CR_OS3_SCRATCH0                               (0x30880U)
#define RGX_CR_OS3_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS3_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS3_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS3_SCRATCH1
*/
#define RGX_CR_OS3_SCRATCH1                               (0x30888U)
#define RGX_CR_OS3_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS3_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS3_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS3_SCRATCH2
*/
#define RGX_CR_OS3_SCRATCH2                               (0x30890U)
#define RGX_CR_OS3_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS3_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS3_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS3_SCRATCH3
*/
#define RGX_CR_OS3_SCRATCH3                               (0x30898U)
#define RGX_CR_OS3_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS3_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS3_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS4_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS4_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS4_SCRATCH0
*/
#define RGX_CR_OS4_SCRATCH0                               (0x40880U)
#define RGX_CR_OS4_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS4_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS4_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS4_SCRATCH1
*/
#define RGX_CR_OS4_SCRATCH1                               (0x40888U)
#define RGX_CR_OS4_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS4_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS4_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS4_SCRATCH2
*/
#define RGX_CR_OS4_SCRATCH2                               (0x40890U)
#define RGX_CR_OS4_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS4_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS4_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS4_SCRATCH3
*/
#define RGX_CR_OS4_SCRATCH3                               (0x40898U)
#define RGX_CR_OS4_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS4_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS4_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS5_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS5_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS5_SCRATCH0
*/
#define RGX_CR_OS5_SCRATCH0                               (0x50880U)
#define RGX_CR_OS5_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS5_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS5_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS5_SCRATCH1
*/
#define RGX_CR_OS5_SCRATCH1                               (0x50888U)
#define RGX_CR_OS5_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS5_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS5_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS5_SCRATCH2
*/
#define RGX_CR_OS5_SCRATCH2                               (0x50890U)
#define RGX_CR_OS5_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS5_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS5_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS5_SCRATCH3
*/
#define RGX_CR_OS5_SCRATCH3                               (0x50898U)
#define RGX_CR_OS5_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS5_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS5_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS6_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS6_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS6_SCRATCH0
*/
#define RGX_CR_OS6_SCRATCH0                               (0x60880U)
#define RGX_CR_OS6_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS6_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS6_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS6_SCRATCH1
*/
#define RGX_CR_OS6_SCRATCH1                               (0x60888U)
#define RGX_CR_OS6_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS6_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS6_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS6_SCRATCH2
*/
#define RGX_CR_OS6_SCRATCH2                               (0x60890U)
#define RGX_CR_OS6_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS6_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS6_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS6_SCRATCH3
*/
#define RGX_CR_OS6_SCRATCH3                               (0x60898U)
#define RGX_CR_OS6_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS6_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS6_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register group: RGX_CR_OS7_SCRATCH, with 4 repeats
*/
#define RGX_CR_OS7_SCRATCH_REPEATCOUNT                    (4U)
/*
    Register RGX_CR_OS7_SCRATCH0
*/
#define RGX_CR_OS7_SCRATCH0                               (0x70880U)
#define RGX_CR_OS7_SCRATCH0_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS7_SCRATCH0_DATA_SHIFT                    (0U)
#define RGX_CR_OS7_SCRATCH0_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS7_SCRATCH1
*/
#define RGX_CR_OS7_SCRATCH1                               (0x70888U)
#define RGX_CR_OS7_SCRATCH1_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS7_SCRATCH1_DATA_SHIFT                    (0U)
#define RGX_CR_OS7_SCRATCH1_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS7_SCRATCH2
*/
#define RGX_CR_OS7_SCRATCH2                               (0x70890U)
#define RGX_CR_OS7_SCRATCH2_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS7_SCRATCH2_DATA_SHIFT                    (0U)
#define RGX_CR_OS7_SCRATCH2_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_OS7_SCRATCH3
*/
#define RGX_CR_OS7_SCRATCH3                               (0x70898U)
#define RGX_CR_OS7_SCRATCH3_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_OS7_SCRATCH3_DATA_SHIFT                    (0U)
#define RGX_CR_OS7_SCRATCH3_DATA_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_META_SP_MSLVDATAX
*/
#define RGX_CR_META_SP_MSLVDATAX__META_REGISTER_UNPACKED_ACCESSES (0x3000U)
#define RGX_CR_META_SP_MSLVDATAX__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVDATAX__META_REGISTER_UNPACKED_ACCESSES__MSLVDATAX_SHIFT (0U)
#define RGX_CR_META_SP_MSLVDATAX__META_REGISTER_UNPACKED_ACCESSES__MSLVDATAX_CLRMSK (0x00000000U)


/*
    Register RGX_CR_META_SP_MSLVDATAX
*/
#define RGX_CR_META_SP_MSLVDATAX                          (0x0A00U)
#define RGX_CR_META_SP_MSLVDATAX_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT          (0U)
#define RGX_CR_META_SP_MSLVDATAX_MSLVDATAX_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_META_SP_MSLVDATAT
*/
#define RGX_CR_META_SP_MSLVDATAT__META_REGISTER_UNPACKED_ACCESSES (0x3040U)
#define RGX_CR_META_SP_MSLVDATAT__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVDATAT__META_REGISTER_UNPACKED_ACCESSES__MSLVDATAT_SHIFT (0U)
#define RGX_CR_META_SP_MSLVDATAT__META_REGISTER_UNPACKED_ACCESSES__MSLVDATAT_CLRMSK (0x00000000U)


/*
    Register RGX_CR_META_SP_MSLVDATAT
*/
#define RGX_CR_META_SP_MSLVDATAT                          (0x0A08U)
#define RGX_CR_META_SP_MSLVDATAT_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT          (0U)
#define RGX_CR_META_SP_MSLVDATAT_MSLVDATAT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_META_SP_MSLVCTRL0
*/
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES (0x3080U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__ADDR_SHIFT (2U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__ADDR_CLRMSK (0x00000003U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__AUTOINCR_SHIFT (1U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__AUTOINCR_CLRMSK (0xFFFFFFFDU)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__AUTOINCR_EN (0x00000002U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__RD_SHIFT (0U)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__RD_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVCTRL0__META_REGISTER_UNPACKED_ACCESSES__RD_EN (0x00000001U)


/*
    Register RGX_CR_META_SP_MSLVCTRL0
*/
#define RGX_CR_META_SP_MSLVCTRL0                          (0x0A10U)
#define RGX_CR_META_SP_MSLVCTRL0_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_META_SP_MSLVCTRL0_ADDR_SHIFT               (2U)
#define RGX_CR_META_SP_MSLVCTRL0_ADDR_CLRMSK              (0x00000003U)
#define RGX_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT           (1U)
#define RGX_CR_META_SP_MSLVCTRL0_AUTOINCR_CLRMSK          (0xFFFFFFFDU)
#define RGX_CR_META_SP_MSLVCTRL0_AUTOINCR_EN              (0x00000002U)
#define RGX_CR_META_SP_MSLVCTRL0_RD_SHIFT                 (0U)
#define RGX_CR_META_SP_MSLVCTRL0_RD_CLRMSK                (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVCTRL0_RD_EN                    (0x00000001U)


/*
    Register RGX_CR_META_SP_MSLVCTRL1
*/
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES (0x30C0U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x00000000F7F4003F))
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERRTHREAD_SHIFT (30U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERRTHREAD_CLRMSK (0x3FFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__LOCK2_INTERLOCK_SHIFT (29U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__LOCK2_INTERLOCK_CLRMSK (0xDFFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__LOCK2_INTERLOCK_EN (0x20000000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__ATOMIC_INTERLOCK_SHIFT (28U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__ATOMIC_INTERLOCK_CLRMSK (0xEFFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__ATOMIC_INTERLOCK_EN (0x10000000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__GBLPORT_IDLE_SHIFT (26U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__GBLPORT_IDLE_CLRMSK (0xFBFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__GBLPORT_IDLE_EN (0x04000000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__COREMEM_IDLE_SHIFT (25U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__COREMEM_IDLE_CLRMSK (0xFDFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__COREMEM_IDLE_EN (0x02000000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__READY_SHIFT (24U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__READY_CLRMSK (0xFEFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__READY_EN (0x01000000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERRID_SHIFT (21U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERRID_CLRMSK (0xFF1FFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERR_SHIFT (20U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERR_CLRMSK (0xFFEFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__DEFERR_EN (0x00100000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__WR_ACTIVE_SHIFT (18U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__WR_ACTIVE_CLRMSK (0xFFFBFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__WR_ACTIVE_EN (0x00040000U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__THREAD_SHIFT (4U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__THREAD_CLRMSK (0xFFFFFFCFU)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__TRANS_SIZE_SHIFT (2U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__TRANS_SIZE_CLRMSK (0xFFFFFFF3U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__BYTE_ROUND_SHIFT (0U)
#define RGX_CR_META_SP_MSLVCTRL1__META_REGISTER_UNPACKED_ACCESSES__BYTE_ROUND_CLRMSK (0xFFFFFFFCU)


/*
    Register RGX_CR_META_SP_MSLVCTRL1
*/
#define RGX_CR_META_SP_MSLVCTRL1                          (0x0A18U)
#define RGX_CR_META_SP_MSLVCTRL1_MASKFULL                 (IMG_UINT64_C(0x00000000F7F4003F))
#define RGX_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT       (30U)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_CLRMSK      (0x3FFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT    (29U)
#define RGX_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_CLRMSK   (0xDFFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_EN       (0x20000000U)
#define RGX_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT   (28U)
#define RGX_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_CLRMSK  (0xEFFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_EN      (0x10000000U)
#define RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT       (26U)
#define RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_CLRMSK      (0xFBFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN          (0x04000000U)
#define RGX_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT       (25U)
#define RGX_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_CLRMSK      (0xFDFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_EN          (0x02000000U)
#define RGX_CR_META_SP_MSLVCTRL1_READY_SHIFT              (24U)
#define RGX_CR_META_SP_MSLVCTRL1_READY_CLRMSK             (0xFEFFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_READY_EN                 (0x01000000U)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT           (21U)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERRID_CLRMSK          (0xFF1FFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT             (20U)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERR_CLRMSK            (0xFFEFFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_DEFERR_EN                (0x00100000U)
#define RGX_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT          (18U)
#define RGX_CR_META_SP_MSLVCTRL1_WR_ACTIVE_CLRMSK         (0xFFFBFFFFU)
#define RGX_CR_META_SP_MSLVCTRL1_WR_ACTIVE_EN             (0x00040000U)
#define RGX_CR_META_SP_MSLVCTRL1_THREAD_SHIFT             (4U)
#define RGX_CR_META_SP_MSLVCTRL1_THREAD_CLRMSK            (0xFFFFFFCFU)
#define RGX_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT         (2U)
#define RGX_CR_META_SP_MSLVCTRL1_TRANS_SIZE_CLRMSK        (0xFFFFFFF3U)
#define RGX_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT         (0U)
#define RGX_CR_META_SP_MSLVCTRL1_BYTE_ROUND_CLRMSK        (0xFFFFFFFCU)


/*
    Register RGX_CR_META_SP_MSLVHANDSHKE
*/
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES (0x3280U)
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES__INPUT_SHIFT (2U)
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES__INPUT_CLRMSK (0xFFFFFFF3U)
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES__OUTPUT_SHIFT (0U)
#define RGX_CR_META_SP_MSLVHANDSHKE__META_REGISTER_UNPACKED_ACCESSES__OUTPUT_CLRMSK (0xFFFFFFFCU)


/*
    Register RGX_CR_META_SP_MSLVHANDSHKE
*/
#define RGX_CR_META_SP_MSLVHANDSHKE                       (0x0A50U)
#define RGX_CR_META_SP_MSLVHANDSHKE_MASKFULL              (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT           (2U)
#define RGX_CR_META_SP_MSLVHANDSHKE_INPUT_CLRMSK          (0xFFFFFFF3U)
#define RGX_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT          (0U)
#define RGX_CR_META_SP_MSLVHANDSHKE_OUTPUT_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_META_SP_MSLVT0KICK
*/
#define RGX_CR_META_SP_MSLVT0KICK__META_REGISTER_UNPACKED_ACCESSES (0x3400U)
#define RGX_CR_META_SP_MSLVT0KICK__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT0KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT0KICK_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT0KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT0KICK_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT0KICK
*/
#define RGX_CR_META_SP_MSLVT0KICK                         (0x0A80U)
#define RGX_CR_META_SP_MSLVT0KICK_MASKFULL                (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT        (0U)
#define RGX_CR_META_SP_MSLVT0KICK_MSLVT0KICK_CLRMSK       (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT0KICKI
*/
#define RGX_CR_META_SP_MSLVT0KICKI__META_REGISTER_UNPACKED_ACCESSES (0x3440U)
#define RGX_CR_META_SP_MSLVT0KICKI__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT0KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT0KICKI_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT0KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT0KICKI_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT0KICKI
*/
#define RGX_CR_META_SP_MSLVT0KICKI                        (0x0A88U)
#define RGX_CR_META_SP_MSLVT0KICKI_MASKFULL               (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT      (0U)
#define RGX_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_CLRMSK     (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT1KICK
*/
#define RGX_CR_META_SP_MSLVT1KICK__META_REGISTER_UNPACKED_ACCESSES (0x3480U)
#define RGX_CR_META_SP_MSLVT1KICK__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT1KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT1KICK_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT1KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT1KICK_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT1KICK
*/
#define RGX_CR_META_SP_MSLVT1KICK                         (0x0A90U)
#define RGX_CR_META_SP_MSLVT1KICK_MASKFULL                (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT        (0U)
#define RGX_CR_META_SP_MSLVT1KICK_MSLVT1KICK_CLRMSK       (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT1KICKI
*/
#define RGX_CR_META_SP_MSLVT1KICKI__META_REGISTER_UNPACKED_ACCESSES (0x34C0U)
#define RGX_CR_META_SP_MSLVT1KICKI__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT1KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT1KICKI_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT1KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT1KICKI_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT1KICKI
*/
#define RGX_CR_META_SP_MSLVT1KICKI                        (0x0A98U)
#define RGX_CR_META_SP_MSLVT1KICKI_MASKFULL               (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT      (0U)
#define RGX_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_CLRMSK     (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT2KICK
*/
#define RGX_CR_META_SP_MSLVT2KICK__META_REGISTER_UNPACKED_ACCESSES (0x3500U)
#define RGX_CR_META_SP_MSLVT2KICK__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT2KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT2KICK_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT2KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT2KICK_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT2KICK
*/
#define RGX_CR_META_SP_MSLVT2KICK                         (0x0AA0U)
#define RGX_CR_META_SP_MSLVT2KICK_MASKFULL                (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT        (0U)
#define RGX_CR_META_SP_MSLVT2KICK_MSLVT2KICK_CLRMSK       (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT2KICKI
*/
#define RGX_CR_META_SP_MSLVT2KICKI__META_REGISTER_UNPACKED_ACCESSES (0x3540U)
#define RGX_CR_META_SP_MSLVT2KICKI__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT2KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT2KICKI_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT2KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT2KICKI_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT2KICKI
*/
#define RGX_CR_META_SP_MSLVT2KICKI                        (0x0AA8U)
#define RGX_CR_META_SP_MSLVT2KICKI_MASKFULL               (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT      (0U)
#define RGX_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_CLRMSK     (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT3KICK
*/
#define RGX_CR_META_SP_MSLVT3KICK__META_REGISTER_UNPACKED_ACCESSES (0x3580U)
#define RGX_CR_META_SP_MSLVT3KICK__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT3KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT3KICK_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT3KICK__META_REGISTER_UNPACKED_ACCESSES__MSLVT3KICK_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT3KICK
*/
#define RGX_CR_META_SP_MSLVT3KICK                         (0x0AB0U)
#define RGX_CR_META_SP_MSLVT3KICK_MASKFULL                (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT        (0U)
#define RGX_CR_META_SP_MSLVT3KICK_MSLVT3KICK_CLRMSK       (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT3KICKI
*/
#define RGX_CR_META_SP_MSLVT3KICKI__META_REGISTER_UNPACKED_ACCESSES (0x35C0U)
#define RGX_CR_META_SP_MSLVT3KICKI__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT3KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT3KICKI_SHIFT (0U)
#define RGX_CR_META_SP_MSLVT3KICKI__META_REGISTER_UNPACKED_ACCESSES__MSLVT3KICKI_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVT3KICKI
*/
#define RGX_CR_META_SP_MSLVT3KICKI                        (0x0AB8U)
#define RGX_CR_META_SP_MSLVT3KICKI_MASKFULL               (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT      (0U)
#define RGX_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_CLRMSK     (0xFFFF0000U)


/*
    Register RGX_CR_META_SP_MSLVRST
*/
#define RGX_CR_META_SP_MSLVRST__META_REGISTER_UNPACKED_ACCESSES (0x3600U)
#define RGX_CR_META_SP_MSLVRST__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_META_SP_MSLVRST__META_REGISTER_UNPACKED_ACCESSES__SOFTRESET_SHIFT (0U)
#define RGX_CR_META_SP_MSLVRST__META_REGISTER_UNPACKED_ACCESSES__SOFTRESET_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVRST__META_REGISTER_UNPACKED_ACCESSES__SOFTRESET_EN (0x00000001U)


/*
    Register RGX_CR_META_SP_MSLVRST
*/
#define RGX_CR_META_SP_MSLVRST                            (0x0AC0U)
#define RGX_CR_META_SP_MSLVRST_MASKFULL                   (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_META_SP_MSLVRST_SOFTRESET_SHIFT            (0U)
#define RGX_CR_META_SP_MSLVRST_SOFTRESET_CLRMSK           (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVRST_SOFTRESET_EN               (0x00000001U)


/*
    Register RGX_CR_META_SP_MSLVIRQSTATUS
*/
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES (0x3640U)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000000C))
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT3_SHIFT (3U)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT3_CLRMSK (0xFFFFFFF7U)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT3_EN (0x00000008U)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT2_SHIFT (2U)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT2_CLRMSK (0xFFFFFFFBU)
#define RGX_CR_META_SP_MSLVIRQSTATUS__META_REGISTER_UNPACKED_ACCESSES__TRIGVECT2_EN (0x00000004U)


/*
    Register RGX_CR_META_SP_MSLVIRQSTATUS
*/
#define RGX_CR_META_SP_MSLVIRQSTATUS                      (0x0AC8U)
#define RGX_CR_META_SP_MSLVIRQSTATUS_MASKFULL             (IMG_UINT64_C(0x000000000000000C))
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT      (3U)
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_CLRMSK     (0xFFFFFFF7U)
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_EN         (0x00000008U)
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT      (2U)
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK     (0xFFFFFFFBU)
#define RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN         (0x00000004U)


/*
    Register RGX_CR_META_SP_MSLVIRQENABLE
*/
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES (0x3680U)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x000000000000000C))
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT1_SHIFT (3U)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT1_CLRMSK (0xFFFFFFF7U)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT1_EN (0x00000008U)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT0_SHIFT (2U)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT0_CLRMSK (0xFFFFFFFBU)
#define RGX_CR_META_SP_MSLVIRQENABLE__META_REGISTER_UNPACKED_ACCESSES__EVENT0_EN (0x00000004U)


/*
    Register RGX_CR_META_SP_MSLVIRQENABLE
*/
#define RGX_CR_META_SP_MSLVIRQENABLE                      (0x0AD0U)
#define RGX_CR_META_SP_MSLVIRQENABLE_MASKFULL             (IMG_UINT64_C(0x000000000000000C))
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT         (3U)
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT1_CLRMSK        (0xFFFFFFF7U)
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT1_EN            (0x00000008U)
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT         (2U)
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT0_CLRMSK        (0xFFFFFFFBU)
#define RGX_CR_META_SP_MSLVIRQENABLE_EVENT0_EN            (0x00000004U)


/*
    Register RGX_CR_META_SP_MSLVIRQLEVEL
*/
#define RGX_CR_META_SP_MSLVIRQLEVEL__META_REGISTER_UNPACKED_ACCESSES (0x36C0U)
#define RGX_CR_META_SP_MSLVIRQLEVEL__META_REGISTER_UNPACKED_ACCESSES__MASKFULL (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_META_SP_MSLVIRQLEVEL__META_REGISTER_UNPACKED_ACCESSES__MODE_SHIFT (0U)
#define RGX_CR_META_SP_MSLVIRQLEVEL__META_REGISTER_UNPACKED_ACCESSES__MODE_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVIRQLEVEL__META_REGISTER_UNPACKED_ACCESSES__MODE_EN (0x00000001U)


/*
    Register RGX_CR_META_SP_MSLVIRQLEVEL
*/
#define RGX_CR_META_SP_MSLVIRQLEVEL                       (0x0AD8U)
#define RGX_CR_META_SP_MSLVIRQLEVEL_MASKFULL              (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT            (0U)
#define RGX_CR_META_SP_MSLVIRQLEVEL_MODE_CLRMSK           (0xFFFFFFFEU)
#define RGX_CR_META_SP_MSLVIRQLEVEL_MODE_EN               (0x00000001U)


/*
    Register group: RGX_CR_FWCORE_DMI_RESERVED0, with 32 repeats
*/
#define RGX_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT           (32U)
/*
    Register RGX_CR_FWCORE_DMI_RESERVED00
*/
#define RGX_CR_FWCORE_DMI_RESERVED00                      (0x8FC0U)
#define RGX_CR_FWCORE_DMI_RESERVED00_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED01
*/
#define RGX_CR_FWCORE_DMI_RESERVED01                      (0x8FC8U)
#define RGX_CR_FWCORE_DMI_RESERVED01_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED02
*/
#define RGX_CR_FWCORE_DMI_RESERVED02                      (0x8FD0U)
#define RGX_CR_FWCORE_DMI_RESERVED02_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED03
*/
#define RGX_CR_FWCORE_DMI_RESERVED03                      (0x8FD8U)
#define RGX_CR_FWCORE_DMI_RESERVED03_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_DATA0
*/
#define RGX_CR_FWCORE_DMI_DATA0                           (0x90C0U)
#define RGX_CR_FWCORE_DMI_DATA0_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_DMI_DATA0_VAL_SHIFT                 (0U)
#define RGX_CR_FWCORE_DMI_DATA0_VAL_CLRMSK                (0x00000000U)


/*
    Register group: RGX_CR_FWCORE_DMI_RESERVED1, with 7 repeats
*/
#define RGX_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT           (7U)
/*
    Register RGX_CR_FWCORE_DMI_RESERVED10
*/
#define RGX_CR_FWCORE_DMI_RESERVED10                      (0x90C8U)
#define RGX_CR_FWCORE_DMI_RESERVED10_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED11
*/
#define RGX_CR_FWCORE_DMI_RESERVED11                      (0x90D0U)
#define RGX_CR_FWCORE_DMI_RESERVED11_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED12
*/
#define RGX_CR_FWCORE_DMI_RESERVED12                      (0x90D8U)
#define RGX_CR_FWCORE_DMI_RESERVED12_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED13
*/
#define RGX_CR_FWCORE_DMI_RESERVED13                      (0x90E0U)
#define RGX_CR_FWCORE_DMI_RESERVED13_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED14
*/
#define RGX_CR_FWCORE_DMI_RESERVED14                      (0x90E8U)
#define RGX_CR_FWCORE_DMI_RESERVED14_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED15
*/
#define RGX_CR_FWCORE_DMI_RESERVED15                      (0x90F0U)
#define RGX_CR_FWCORE_DMI_RESERVED15_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED16
*/
#define RGX_CR_FWCORE_DMI_RESERVED16                      (0x90F8U)
#define RGX_CR_FWCORE_DMI_RESERVED16_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_DATA1
*/
#define RGX_CR_FWCORE_DMI_DATA1                           (0x9100U)
#define RGX_CR_FWCORE_DMI_DATA1_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_DMI_DATA1_VAL_SHIFT                 (0U)
#define RGX_CR_FWCORE_DMI_DATA1_VAL_CLRMSK                (0x00000000U)


/*
    Register group: RGX_CR_FWCORE_DMI_RESERVED2, with 7 repeats
*/
#define RGX_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT           (7U)
/*
    Register RGX_CR_FWCORE_DMI_RESERVED20
*/
#define RGX_CR_FWCORE_DMI_RESERVED20                      (0x9108U)
#define RGX_CR_FWCORE_DMI_RESERVED20_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED21
*/
#define RGX_CR_FWCORE_DMI_RESERVED21                      (0x9110U)
#define RGX_CR_FWCORE_DMI_RESERVED21_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED22
*/
#define RGX_CR_FWCORE_DMI_RESERVED22                      (0x9118U)
#define RGX_CR_FWCORE_DMI_RESERVED22_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED23
*/
#define RGX_CR_FWCORE_DMI_RESERVED23                      (0x9120U)
#define RGX_CR_FWCORE_DMI_RESERVED23_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register group: RGX_CR_FWCORE_DMI_RESERVED3, with 80 repeats
*/
#define RGX_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT           (80U)
/*
    Register RGX_CR_FWCORE_DMI_RESERVED30
*/
#define RGX_CR_FWCORE_DMI_RESERVED30                      (0x9140U)
#define RGX_CR_FWCORE_DMI_RESERVED30_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED31
*/
#define RGX_CR_FWCORE_DMI_RESERVED31                      (0x9148U)
#define RGX_CR_FWCORE_DMI_RESERVED31_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED32
*/
#define RGX_CR_FWCORE_DMI_RESERVED32                      (0x9150U)
#define RGX_CR_FWCORE_DMI_RESERVED32_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED33
*/
#define RGX_CR_FWCORE_DMI_RESERVED33                      (0x9158U)
#define RGX_CR_FWCORE_DMI_RESERVED33_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED34
*/
#define RGX_CR_FWCORE_DMI_RESERVED34                      (0x9160U)
#define RGX_CR_FWCORE_DMI_RESERVED34_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED35
*/
#define RGX_CR_FWCORE_DMI_RESERVED35                      (0x9168U)
#define RGX_CR_FWCORE_DMI_RESERVED35_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED36
*/
#define RGX_CR_FWCORE_DMI_RESERVED36                      (0x9170U)
#define RGX_CR_FWCORE_DMI_RESERVED36_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED37
*/
#define RGX_CR_FWCORE_DMI_RESERVED37                      (0x9178U)
#define RGX_CR_FWCORE_DMI_RESERVED37_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED38
*/
#define RGX_CR_FWCORE_DMI_RESERVED38                      (0x9180U)
#define RGX_CR_FWCORE_DMI_RESERVED38_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED39
*/
#define RGX_CR_FWCORE_DMI_RESERVED39                      (0x9188U)
#define RGX_CR_FWCORE_DMI_RESERVED39_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED310
*/
#define RGX_CR_FWCORE_DMI_RESERVED310                     (0x9190U)
#define RGX_CR_FWCORE_DMI_RESERVED310_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED311
*/
#define RGX_CR_FWCORE_DMI_RESERVED311                     (0x9198U)
#define RGX_CR_FWCORE_DMI_RESERVED311_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED312
*/
#define RGX_CR_FWCORE_DMI_RESERVED312                     (0x91A0U)
#define RGX_CR_FWCORE_DMI_RESERVED312_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED313
*/
#define RGX_CR_FWCORE_DMI_RESERVED313                     (0x91A8U)
#define RGX_CR_FWCORE_DMI_RESERVED313_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED314
*/
#define RGX_CR_FWCORE_DMI_RESERVED314                     (0x91B0U)
#define RGX_CR_FWCORE_DMI_RESERVED314_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED315
*/
#define RGX_CR_FWCORE_DMI_RESERVED315                     (0x91B8U)
#define RGX_CR_FWCORE_DMI_RESERVED315_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED316
*/
#define RGX_CR_FWCORE_DMI_RESERVED316                     (0x91C0U)
#define RGX_CR_FWCORE_DMI_RESERVED316_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED317
*/
#define RGX_CR_FWCORE_DMI_RESERVED317                     (0x91C8U)
#define RGX_CR_FWCORE_DMI_RESERVED317_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED318
*/
#define RGX_CR_FWCORE_DMI_RESERVED318                     (0x91D0U)
#define RGX_CR_FWCORE_DMI_RESERVED318_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED319
*/
#define RGX_CR_FWCORE_DMI_RESERVED319                     (0x91D8U)
#define RGX_CR_FWCORE_DMI_RESERVED319_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED320
*/
#define RGX_CR_FWCORE_DMI_RESERVED320                     (0x91E0U)
#define RGX_CR_FWCORE_DMI_RESERVED320_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED321
*/
#define RGX_CR_FWCORE_DMI_RESERVED321                     (0x91E8U)
#define RGX_CR_FWCORE_DMI_RESERVED321_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED322
*/
#define RGX_CR_FWCORE_DMI_RESERVED322                     (0x91F0U)
#define RGX_CR_FWCORE_DMI_RESERVED322_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED323
*/
#define RGX_CR_FWCORE_DMI_RESERVED323                     (0x91F8U)
#define RGX_CR_FWCORE_DMI_RESERVED323_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED324
*/
#define RGX_CR_FWCORE_DMI_RESERVED324                     (0x9200U)
#define RGX_CR_FWCORE_DMI_RESERVED324_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED325
*/
#define RGX_CR_FWCORE_DMI_RESERVED325                     (0x9208U)
#define RGX_CR_FWCORE_DMI_RESERVED325_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED326
*/
#define RGX_CR_FWCORE_DMI_RESERVED326                     (0x9210U)
#define RGX_CR_FWCORE_DMI_RESERVED326_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED327
*/
#define RGX_CR_FWCORE_DMI_RESERVED327                     (0x9218U)
#define RGX_CR_FWCORE_DMI_RESERVED327_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED328
*/
#define RGX_CR_FWCORE_DMI_RESERVED328                     (0x9220U)
#define RGX_CR_FWCORE_DMI_RESERVED328_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED329
*/
#define RGX_CR_FWCORE_DMI_RESERVED329                     (0x9228U)
#define RGX_CR_FWCORE_DMI_RESERVED329_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED330
*/
#define RGX_CR_FWCORE_DMI_RESERVED330                     (0x9230U)
#define RGX_CR_FWCORE_DMI_RESERVED330_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED331
*/
#define RGX_CR_FWCORE_DMI_RESERVED331                     (0x9238U)
#define RGX_CR_FWCORE_DMI_RESERVED331_MASKFULL            (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_DMCONTROL
*/
#define RGX_CR_FWCORE_DMI_DMCONTROL                       (0x93C0U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_MASKFULL              (IMG_UINT64_C(0x00000000D0000003))
#define RGX_CR_FWCORE_DMI_DMCONTROL_HALTREQ_SHIFT         (31U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_HALTREQ_CLRMSK        (0x7FFFFFFFU)
#define RGX_CR_FWCORE_DMI_DMCONTROL_HALTREQ_EN            (0x80000000U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_SHIFT       (30U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_CLRMSK      (0xBFFFFFFFU)
#define RGX_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_EN          (0x40000000U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_SHIFT    (28U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_CLRMSK   (0xEFFFFFFFU)
#define RGX_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_EN       (0x10000000U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_NDMRESET_SHIFT        (1U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_NDMRESET_CLRMSK       (0xFFFFFFFDU)
#define RGX_CR_FWCORE_DMI_DMCONTROL_NDMRESET_EN           (0x00000002U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_SHIFT        (0U)
#define RGX_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_CLRMSK       (0xFFFFFFFEU)
#define RGX_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_EN           (0x00000001U)


/*
    Register group: RGX_CR_FWCORE_DMI_RESERVED4, with 7 repeats
*/
#define RGX_CR_FWCORE_DMI_RESERVED4_REPEATCOUNT           (7U)
/*
    Register RGX_CR_FWCORE_DMI_RESERVED40
*/
#define RGX_CR_FWCORE_DMI_RESERVED40                      (0x93C8U)
#define RGX_CR_FWCORE_DMI_RESERVED40_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_RESERVED41
*/
#define RGX_CR_FWCORE_DMI_RESERVED41                      (0x93D0U)
#define RGX_CR_FWCORE_DMI_RESERVED41_MASKFULL             (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_DMSTATUS
*/
#define RGX_CR_FWCORE_DMI_DMSTATUS                        (0x9400U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_MASKFULL               (IMG_UINT64_C(0x00000000004FFFFF))
#define RGX_CR_FWCORE_DMI_DMSTATUS_IMPEBREAK_SHIFT        (22U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_IMPEBREAK_CLRMSK       (0xFFBFFFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_IMPEBREAK_EN           (0x00400000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHAVERESET_SHIFT     (19U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHAVERESET_CLRMSK    (0xFFF7FFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHAVERESET_EN        (0x00080000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHAVERESET_SHIFT     (18U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHAVERESET_CLRMSK    (0xFFFBFFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHAVERESET_EN        (0x00040000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRESUMEACK_SHIFT     (17U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRESUMEACK_CLRMSK    (0xFFFDFFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRESUMEACK_EN        (0x00020000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRESUMEACK_SHIFT     (16U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRESUMEACK_CLRMSK    (0xFFFEFFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRESUMEACK_EN        (0x00010000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLNONEXISTENT_SHIFT   (15U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLNONEXISTENT_CLRMSK  (0xFFFF7FFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLNONEXISTENT_EN      (0x00008000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYNONEXISTENT_SHIFT   (14U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYNONEXISTENT_CLRMSK  (0xFFFFBFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYNONEXISTENT_EN      (0x00004000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLUNAVAIL_SHIFT       (13U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLUNAVAIL_CLRMSK      (0xFFFFDFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLUNAVAIL_EN          (0x00002000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYUNAVAIL_SHIFT       (12U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYUNAVAIL_CLRMSK      (0xFFFFEFFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYUNAVAIL_EN          (0x00001000U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRUNNING_SHIFT       (11U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRUNNING_CLRMSK      (0xFFFFF7FFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLRUNNING_EN          (0x00000800U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRUNNING_SHIFT       (10U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRUNNING_CLRMSK      (0xFFFFFBFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYRUNNING_EN          (0x00000400U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHALTED_SHIFT        (9U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHALTED_CLRMSK       (0xFFFFFDFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ALLHALTED_EN           (0x00000200U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHALTED_SHIFT        (8U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHALTED_CLRMSK       (0xFFFFFEFFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_ANYHALTED_EN           (0x00000100U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHENTICATED_SHIFT    (7U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHENTICATED_CLRMSK   (0xFFFFFF7FU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHENTICATED_EN       (0x00000080U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHBUSY_SHIFT         (6U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHBUSY_CLRMSK        (0xFFFFFFBFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_AUTHBUSY_EN            (0x00000040U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_HASRESETHALTREQ_SHIFT  (5U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_HASRESETHALTREQ_CLRMSK (0xFFFFFFDFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_HASRESETHALTREQ_EN     (0x00000020U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_CONFSTRPTRVALID_SHIFT  (4U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_CONFSTRPTRVALID_CLRMSK (0xFFFFFFEFU)
#define RGX_CR_FWCORE_DMI_DMSTATUS_CONFSTRPTRVALID_EN     (0x00000010U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_VERSION_SHIFT          (0U)
#define RGX_CR_FWCORE_DMI_DMSTATUS_VERSION_CLRMSK         (0xFFFFFFF0U)


/*
    Register RGX_CR_FWCORE_DMI_ABSTRACTCS
*/
#define RGX_CR_FWCORE_DMI_ABSTRACTCS                      (0x9540U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_MASKFULL             (IMG_UINT64_C(0x000000001F00170F))
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_PROGBUFSIZE_SHIFT    (24U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_PROGBUFSIZE_CLRMSK   (0xE0FFFFFFU)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_BUSY_SHIFT           (12U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_BUSY_CLRMSK          (0xFFFFEFFFU)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_BUSY_EN              (0x00001000U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_CMDERR_SHIFT         (8U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_CMDERR_CLRMSK        (0xFFFFF8FFU)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_DATACOUNT_SHIFT      (0U)
#define RGX_CR_FWCORE_DMI_ABSTRACTCS_DATACOUNT_CLRMSK     (0xFFFFFFF0U)


/*
    Register RGX_CR_FWCORE_DMI_COMMAND
*/
#define RGX_CR_FWCORE_DMI_COMMAND                         (0x9580U)
#define RGX_CR_FWCORE_DMI_COMMAND_MASKFULL                (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_DMI_COMMAND_CMDTYPE_SHIFT           (24U)
#define RGX_CR_FWCORE_DMI_COMMAND_CMDTYPE_CLRMSK          (0x00FFFFFFU)
#define RGX_CR_FWCORE_DMI_COMMAND_CONTROL_SHIFT           (0U)
#define RGX_CR_FWCORE_DMI_COMMAND_CONTROL_CLRMSK          (0xFF000000U)


/*
    Register RGX_CR_FWCORE_DMI_SBCS
*/
#define RGX_CR_FWCORE_DMI_SBCS                            (0x9DC0U)
#define RGX_CR_FWCORE_DMI_SBCS_MASKFULL                   (IMG_UINT64_C(0x00000000E07FFFFF))
#define RGX_CR_FWCORE_DMI_SBCS_SBVERSION_SHIFT            (29U)
#define RGX_CR_FWCORE_DMI_SBCS_SBVERSION_CLRMSK           (0x1FFFFFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSYERROR_SHIFT          (22U)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSYERROR_CLRMSK         (0xFFBFFFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSYERROR_EN             (0x00400000U)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSY_SHIFT               (21U)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSY_CLRMSK              (0xFFDFFFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBBUSY_EN                  (0x00200000U)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONADDR_SHIFT         (20U)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONADDR_CLRMSK        (0xFFEFFFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONADDR_EN            (0x00100000U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS_SHIFT             (17U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS_CLRMSK            (0xFFF1FFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBAUTOINCREMENT_SHIFT      (16U)
#define RGX_CR_FWCORE_DMI_SBCS_SBAUTOINCREMENT_CLRMSK     (0xFFFEFFFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBAUTOINCREMENT_EN         (0x00010000U)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONDATA_SHIFT         (15U)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONDATA_CLRMSK        (0xFFFF7FFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBREADONDATA_EN            (0x00008000U)
#define RGX_CR_FWCORE_DMI_SBCS_SBERROR_SHIFT              (12U)
#define RGX_CR_FWCORE_DMI_SBCS_SBERROR_CLRMSK             (0xFFFF8FFFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBASIZE_SHIFT              (5U)
#define RGX_CR_FWCORE_DMI_SBCS_SBASIZE_CLRMSK             (0xFFFFF01FU)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS128_SHIFT          (4U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS128_CLRMSK         (0xFFFFFFEFU)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS128_EN             (0x00000010U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS64_SHIFT           (3U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS64_CLRMSK          (0xFFFFFFF7U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS64_EN              (0x00000008U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS32_SHIFT           (2U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS32_CLRMSK          (0xFFFFFFFBU)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS32_EN              (0x00000004U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS16_SHIFT           (1U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS16_CLRMSK          (0xFFFFFFFDU)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS16_EN              (0x00000002U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS8_SHIFT            (0U)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS8_CLRMSK           (0xFFFFFFFEU)
#define RGX_CR_FWCORE_DMI_SBCS_SBACCESS8_EN               (0x00000001U)


/*
    Register RGX_CR_FWCORE_DMI_SBADDRESS0
*/
#define RGX_CR_FWCORE_DMI_SBADDRESS0                      (0x9E00U)
#define RGX_CR_FWCORE_DMI_SBADDRESS0_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_DMI_SBADDRESS0_ADDRESS_SHIFT        (0U)
#define RGX_CR_FWCORE_DMI_SBADDRESS0_ADDRESS_CLRMSK       (0x00000000U)


/*
    Register RGX_CR_FWCORE_DMI_SBDATA0
*/
#define RGX_CR_FWCORE_DMI_SBDATA0                         (0x9EC0U)
#define RGX_CR_FWCORE_DMI_SBDATA0_MASKFULL                (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_SBDATA1
*/
#define RGX_CR_FWCORE_DMI_SBDATA1                         (0x9F00U)
#define RGX_CR_FWCORE_DMI_SBDATA1_MASKFULL                (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_SBDATA2
*/
#define RGX_CR_FWCORE_DMI_SBDATA2                         (0x9F40U)
#define RGX_CR_FWCORE_DMI_SBDATA2_MASKFULL                (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_SBDATA3
*/
#define RGX_CR_FWCORE_DMI_SBDATA3                         (0x9F80U)
#define RGX_CR_FWCORE_DMI_SBDATA3_MASKFULL                (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_FWCORE_DMI_HALTSUM0
*/
#define RGX_CR_FWCORE_DMI_HALTSUM0                        (0x9FC0U)
#define RGX_CR_FWCORE_DMI_HALTSUM0_MASKFULL               (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_DMI_HALTSUM0_VAL_SHIFT              (0U)
#define RGX_CR_FWCORE_DMI_HALTSUM0_VAL_CLRMSK             (0x00000000U)


/*
    Register RGX_CR_MTS_SCHEDULE
*/
#define RGX_CR_MTS_SCHEDULE                               (0x0B00U)
#define RGX_CR_MTS_SCHEDULE_MASKFULL                      (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE_HOST_SHIFT                    (8U)
#define RGX_CR_MTS_SCHEDULE_HOST_CLRMSK                   (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE_HOST_BG_TIMER                 (0x00000000U)
#define RGX_CR_MTS_SCHEDULE_HOST_HOST                     (0x00000100U)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_SHIFT                (6U)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_CLRMSK               (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_PRT0                 (0x00000000U)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_PRT1                 (0x00000040U)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_PRT2                 (0x00000080U)
#define RGX_CR_MTS_SCHEDULE_PRIORITY_PRT3                 (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE_CONTEXT_SHIFT                 (5U)
#define RGX_CR_MTS_SCHEDULE_CONTEXT_CLRMSK                (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE_CONTEXT_BGCTX                 (0x00000000U)
#define RGX_CR_MTS_SCHEDULE_CONTEXT_INTCTX                (0x00000020U)
#define RGX_CR_MTS_SCHEDULE_TASK_SHIFT                    (4U)
#define RGX_CR_MTS_SCHEDULE_TASK_CLRMSK                   (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE_TASK_NON_COUNTED              (0x00000000U)
#define RGX_CR_MTS_SCHEDULE_TASK_COUNTED                  (0x00000010U)
#define RGX_CR_MTS_SCHEDULE_DM_SHIFT                      (0U)
#define RGX_CR_MTS_SCHEDULE_DM_CLRMSK                     (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE_DM_DM0                        (0x00000000U)
#define RGX_CR_MTS_SCHEDULE_DM_DM1                        (0x00000001U)
#define RGX_CR_MTS_SCHEDULE_DM_DM2                        (0x00000002U)
#define RGX_CR_MTS_SCHEDULE_DM_DM3                        (0x00000003U)
#define RGX_CR_MTS_SCHEDULE_DM_DM4                        (0x00000004U)
#define RGX_CR_MTS_SCHEDULE_DM_DM5                        (0x00000005U)
#define RGX_CR_MTS_SCHEDULE_DM_DM6                        (0x00000006U)
#define RGX_CR_MTS_SCHEDULE_DM_DM7                        (0x00000007U)
#define RGX_CR_MTS_SCHEDULE_DM_DM_ALL                     (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE1
*/
#define RGX_CR_MTS_SCHEDULE1                              (0x10B00U)
#define RGX_CR_MTS_SCHEDULE1_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE1_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE1_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE1_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE1_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE1_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE1_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE1_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE1_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE1_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE1_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE1_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE1_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE1_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE1_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE1_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE1_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE2
*/
#define RGX_CR_MTS_SCHEDULE2                              (0x20B00U)
#define RGX_CR_MTS_SCHEDULE2_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE2_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE2_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE2_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE2_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE2_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE2_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE2_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE2_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE2_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE2_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE2_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE2_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE2_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE2_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE2_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE2_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE3
*/
#define RGX_CR_MTS_SCHEDULE3                              (0x30B00U)
#define RGX_CR_MTS_SCHEDULE3_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE3_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE3_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE3_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE3_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE3_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE3_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE3_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE3_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE3_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE3_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE3_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE3_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE3_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE3_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE3_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE3_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE4
*/
#define RGX_CR_MTS_SCHEDULE4                              (0x40B00U)
#define RGX_CR_MTS_SCHEDULE4_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE4_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE4_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE4_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE4_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE4_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE4_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE4_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE4_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE4_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE4_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE4_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE4_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE4_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE4_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE4_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE4_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE5
*/
#define RGX_CR_MTS_SCHEDULE5                              (0x50B00U)
#define RGX_CR_MTS_SCHEDULE5_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE5_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE5_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE5_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE5_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE5_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE5_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE5_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE5_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE5_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE5_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE5_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE5_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE5_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE5_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE5_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE5_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE6
*/
#define RGX_CR_MTS_SCHEDULE6                              (0x60B00U)
#define RGX_CR_MTS_SCHEDULE6_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE6_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE6_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE6_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE6_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE6_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE6_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE6_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE6_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE6_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE6_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE6_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE6_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE6_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE6_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE6_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE6_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_SCHEDULE7
*/
#define RGX_CR_MTS_SCHEDULE7                              (0x70B00U)
#define RGX_CR_MTS_SCHEDULE7_MASKFULL                     (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_MTS_SCHEDULE7_HOST_SHIFT                   (8U)
#define RGX_CR_MTS_SCHEDULE7_HOST_CLRMSK                  (0xFFFFFEFFU)
#define RGX_CR_MTS_SCHEDULE7_HOST_BG_TIMER                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE7_HOST_HOST                    (0x00000100U)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_SHIFT               (6U)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_CLRMSK              (0xFFFFFF3FU)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_PRT0                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_PRT1                (0x00000040U)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_PRT2                (0x00000080U)
#define RGX_CR_MTS_SCHEDULE7_PRIORITY_PRT3                (0x000000C0U)
#define RGX_CR_MTS_SCHEDULE7_CONTEXT_SHIFT                (5U)
#define RGX_CR_MTS_SCHEDULE7_CONTEXT_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_MTS_SCHEDULE7_CONTEXT_BGCTX                (0x00000000U)
#define RGX_CR_MTS_SCHEDULE7_CONTEXT_INTCTX               (0x00000020U)
#define RGX_CR_MTS_SCHEDULE7_TASK_SHIFT                   (4U)
#define RGX_CR_MTS_SCHEDULE7_TASK_CLRMSK                  (0xFFFFFFEFU)
#define RGX_CR_MTS_SCHEDULE7_TASK_NON_COUNTED             (0x00000000U)
#define RGX_CR_MTS_SCHEDULE7_TASK_COUNTED                 (0x00000010U)
#define RGX_CR_MTS_SCHEDULE7_DM_SHIFT                     (0U)
#define RGX_CR_MTS_SCHEDULE7_DM_CLRMSK                    (0xFFFFFFF0U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM0                       (0x00000000U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM1                       (0x00000001U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM2                       (0x00000002U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM3                       (0x00000003U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM4                       (0x00000004U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM5                       (0x00000005U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM6                       (0x00000006U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM7                       (0x00000007U)
#define RGX_CR_MTS_SCHEDULE7_DM_DM_ALL                    (0x0000000FU)


/*
    Register RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC
*/
#define RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC                 (0x0B30U)
#define RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL        (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT  (0U)
#define RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC
*/
#define RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC                 (0x0B38U)
#define RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL        (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT  (0U)
#define RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC
*/
#define RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC                (0x0B40U)
#define RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL       (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT (0U)
#define RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC
*/
#define RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC                (0x0B48U)
#define RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL       (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT (0U)
#define RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_MTS_GARTEN_WRAPPER_CONFIG
*/
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG                  (0x0B50U)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG__S8_CPR__MASKFULL (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_MASKFULL         (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT (1U)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_CLRMSK (0xFFFFFFFDU)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_EN (0x00000002U)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT  (0U)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META   (0x00000000U)
#define RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_MTS    (0x00000001U)


/*
    Register RGX_CR_MTS_DM0_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM0_INTERRUPT_ENABLE                   (0x0B58U)
#define RGX_CR_MTS_DM0_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM1_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM1_INTERRUPT_ENABLE                   (0x0B60U)
#define RGX_CR_MTS_DM1_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM2_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM2_INTERRUPT_ENABLE                   (0x0B68U)
#define RGX_CR_MTS_DM2_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM3_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM3_INTERRUPT_ENABLE                   (0x0B70U)
#define RGX_CR_MTS_DM3_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM4_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM4_INTERRUPT_ENABLE                   (0x0B78U)
#define RGX_CR_MTS_DM4_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM5_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM5_INTERRUPT_ENABLE                   (0x0B80U)
#define RGX_CR_MTS_DM5_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM6_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM6_INTERRUPT_ENABLE                   (0xD138U)
#define RGX_CR_MTS_DM6_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM6_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM6_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_DM7_INTERRUPT_ENABLE
*/
#define RGX_CR_MTS_DM7_INTERRUPT_ENABLE                   (0xD140U)
#define RGX_CR_MTS_DM7_INTERRUPT_ENABLE_MASKFULL          (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_DM7_INTERRUPT_ENABLE_INT_ENABLE_SHIFT  (0U)
#define RGX_CR_MTS_DM7_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_MTS_INTCTX
*/
#define RGX_CR_MTS_INTCTX                                 (0x0B98U)
#define RGX_CR_MTS_INTCTX_MASKFULL                        (IMG_UINT64_C(0x000000003FC0FFFF))
#define RGX_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT          (22U)
#define RGX_CR_MTS_INTCTX_DM_HOST_SCHEDULE_CLRMSK         (0xC03FFFFFU)
#define RGX_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT         (8U)
#define RGX_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_CLRMSK        (0xFFFF00FFU)
#define RGX_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT     (0U)
#define RGX_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_CLRMSK    (0xFFFFFF00U)


/*
    Register RGX_CR_MTS_BGCTX
*/
#define RGX_CR_MTS_BGCTX                                  (0x0BA0U)
#define RGX_CR_MTS_BGCTX_MASKFULL                         (IMG_UINT64_C(0x00000000000000FF))
#define RGX_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT     (0U)
#define RGX_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_CLRMSK    (0xFFFFFF00U)


/*
    Register RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE
*/
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE                 (0x0BA8U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_MASKFULL        (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT       (56U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_CLRMSK      (IMG_UINT64_C(0x00FFFFFFFFFFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT       (48U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_CLRMSK      (IMG_UINT64_C(0xFF00FFFFFFFFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT       (40U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_CLRMSK      (IMG_UINT64_C(0xFFFF00FFFFFFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT       (32U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_CLRMSK      (IMG_UINT64_C(0xFFFFFF00FFFFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT       (24U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_CLRMSK      (IMG_UINT64_C(0xFFFFFFFF00FFFFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT       (16U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFF00FFFF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT       (8U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFF00FF))
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT       (0U)
#define RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_MTS_GPU_INT_STATUS
*/
#define RGX_CR_MTS_GPU_INT_STATUS                         (0x0BB0U)
#define RGX_CR_MTS_GPU_INT_STATUS_MASKFULL                (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT            (0U)
#define RGX_CR_MTS_GPU_INT_STATUS_STATUS_CLRMSK           (0x00000000U)


/*
    Register RGX_CR_IRQ_OS0_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS0_EVENT_STATUS                       (0x0BD0U)
#define RGX_CR_IRQ_OS0_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS0_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS0_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS0_EVENT_CLEAR                        (0x0BE0U)
#define RGX_CR_IRQ_OS0_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS1_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS1_EVENT_STATUS                       (0x10BD0U)
#define RGX_CR_IRQ_OS1_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS1_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS1_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS1_EVENT_CLEAR                        (0x10BE0U)
#define RGX_CR_IRQ_OS1_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS2_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS2_EVENT_STATUS                       (0x20BD0U)
#define RGX_CR_IRQ_OS2_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS2_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS2_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS2_EVENT_CLEAR                        (0x20BE0U)
#define RGX_CR_IRQ_OS2_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS3_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS3_EVENT_STATUS                       (0x30BD0U)
#define RGX_CR_IRQ_OS3_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS3_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS3_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS3_EVENT_CLEAR                        (0x30BE0U)
#define RGX_CR_IRQ_OS3_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS4_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS4_EVENT_STATUS                       (0x40BD0U)
#define RGX_CR_IRQ_OS4_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS4_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS4_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS4_EVENT_CLEAR                        (0x40BE0U)
#define RGX_CR_IRQ_OS4_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS5_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS5_EVENT_STATUS                       (0x50BD0U)
#define RGX_CR_IRQ_OS5_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS5_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS5_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS5_EVENT_CLEAR                        (0x50BE0U)
#define RGX_CR_IRQ_OS5_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS6_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS6_EVENT_STATUS                       (0x60BD0U)
#define RGX_CR_IRQ_OS6_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS6_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS6_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS6_EVENT_CLEAR                        (0x60BE0U)
#define RGX_CR_IRQ_OS6_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS7_EVENT_STATUS
*/
#define RGX_CR_IRQ_OS7_EVENT_STATUS                       (0x70BD0U)
#define RGX_CR_IRQ_OS7_EVENT_STATUS_MASKFULL              (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT          (0U)
#define RGX_CR_IRQ_OS7_EVENT_STATUS_SOURCE_CLRMSK         (0xFFFFFFFCU)


/*
    Register RGX_CR_IRQ_OS7_EVENT_CLEAR
*/
#define RGX_CR_IRQ_OS7_EVENT_CLEAR                        (0x70BE0U)
#define RGX_CR_IRQ_OS7_EVENT_CLEAR_MASKFULL               (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT           (0U)
#define RGX_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_CLRMSK          (0xFFFFFFFCU)


/*
    Register RGX_CR_MTS_SCHEDULE_ENABLE
*/
#define RGX_CR_MTS_SCHEDULE_ENABLE                        (0x0BD8U)
#define RGX_CR_MTS_SCHEDULE_ENABLE_MASKFULL               (IMG_UINT64_C(0x00000000000000FF))
#define RGX_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT             (0U)
#define RGX_CR_MTS_SCHEDULE_ENABLE_MASK_CLRMSK            (0xFFFFFF00U)


/*
    Register RGX_CR_FWCORE_BOOT
*/
#define RGX_CR_FWCORE_BOOT                                (0x70C0U)
#define RGX_CR_FWCORE_BOOT_MASKFULL                       (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_FWCORE_BOOT_MODE_SHIFT                     (0U)
#define RGX_CR_FWCORE_BOOT_MODE_CLRMSK                    (0xFFFFFFFEU)
#define RGX_CR_FWCORE_BOOT_MODE_EN                        (0x00000001U)


/*
    Register RGX_CR_META_BOOT
*/
#define RGX_CR_META_BOOT                                  (0x0BF8U)
#define RGX_CR_META_BOOT_MASKFULL                         (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_META_BOOT_MODE_SHIFT                       (0U)
#define RGX_CR_META_BOOT_MODE_CLRMSK                      (0xFFFFFFFEU)
#define RGX_CR_META_BOOT_MODE_EN                          (0x00000001U)


/*
    Register RGX_CR_GARTEN_SLC
*/
#define RGX_CR_GARTEN_SLC                                 (0x0BB8U)
#define RGX_CR_GARTEN_SLC_MASKFULL                        (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT           (0U)
#define RGX_CR_GARTEN_SLC_FORCE_COHERENCY_CLRMSK          (0xFFFFFFFEU)
#define RGX_CR_GARTEN_SLC_FORCE_COHERENCY_EN              (0x00000001U)


/*
    Register RGX_CR_ISP_RENDER
*/
#define RGX_CR_ISP_RENDER                                 (0x0F08U)
#define RGX_CR_ISP_RENDER__IPP_FAST_RENDER__MASKFULL      (IMG_UINT64_C(0x000000000003FFFF))
#define RGX_CR_ISP_RENDER__CS3DL_4__MASKFULL              (IMG_UINT64_C(0x000000000007FF53))
#define RGX_CR_ISP_RENDER_MASKFULL                        (IMG_UINT64_C(0x000000000003FFF0))
#define RGX_CR_ISP_RENDER_TILES_PER_ISP_SHIFT             (16U)
#define RGX_CR_ISP_RENDER_TILES_PER_ISP_CLRMSK            (0xFFFCFFFFU)
#define RGX_CR_ISP_RENDER__CS3DL_4__TILES_PER_ISP_SHIFT   (16U)
#define RGX_CR_ISP_RENDER__CS3DL_4__TILES_PER_ISP_CLRMSK  (0xFFF8FFFFU)
#define RGX_CR_ISP_RENDER_TILE_LIMIT_HIGH_SHIFT           (12U)
#define RGX_CR_ISP_RENDER_TILE_LIMIT_HIGH_CLRMSK          (0xFFFF0FFFU)
#define RGX_CR_ISP_RENDER_TILE_LIMIT_LOW_SHIFT            (8U)
#define RGX_CR_ISP_RENDER_TILE_LIMIT_LOW_CLRMSK           (0xFFFFF0FFU)
#define RGX_CR_ISP_RENDER_TILE_STARVATION_SHIFT           (7U)
#define RGX_CR_ISP_RENDER_TILE_STARVATION_CLRMSK          (0xFFFFFF7FU)
#define RGX_CR_ISP_RENDER_TILE_STARVATION_EN              (0x00000080U)
#define RGX_CR_ISP_RENDER_PROCESS_EMPTY_TILES_SHIFT       (6U)
#define RGX_CR_ISP_RENDER_PROCESS_EMPTY_TILES_CLRMSK      (0xFFFFFFBFU)
#define RGX_CR_ISP_RENDER_PROCESS_EMPTY_TILES_EN          (0x00000040U)
#define RGX_CR_ISP_RENDER_RESUME_SHIFT                    (4U)
#define RGX_CR_ISP_RENDER_RESUME_CLRMSK                   (0xFFFFFFCFU)
#define RGX_CR_ISP_RENDER_RESUME_CONTEXT_NONE             (0x00000000U)
#define RGX_CR_ISP_RENDER_RESUME_CONTEXT_TILE             (0x00000010U)
#define RGX_CR_ISP_RENDER_RESUME_CONTEXT_PBLK             (0x00000030U)
#define RGX_CR_ISP_RENDER__CS3DL_4__RESUME_SHIFT          (4U)
#define RGX_CR_ISP_RENDER__CS3DL_4__RESUME_CLRMSK         (0xFFFFFFEFU)
#define RGX_CR_ISP_RENDER__CS3DL_4__RESUME_CONTEXT_NONE   (0x00000000U)
#define RGX_CR_ISP_RENDER__CS3DL_4__RESUME_CONTEXT_RESUME (0x00000010U)
#define RGX_CR_ISP_RENDER_DIR_SHIFT                       (2U)
#define RGX_CR_ISP_RENDER_DIR_CLRMSK                      (0xFFFFFFF3U)
#define RGX_CR_ISP_RENDER_DIR_TL2BR                       (0x00000000U)
#define RGX_CR_ISP_RENDER_DIR_TR2BL                       (0x00000004U)
#define RGX_CR_ISP_RENDER_DIR_BL2TR                       (0x00000008U)
#define RGX_CR_ISP_RENDER_DIR_BR2TL                       (0x0000000CU)
#define RGX_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT   (1U)
#define RGX_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_CLRMSK  (0xFFFFFFFDU)
#define RGX_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_EN      (0x00000002U)
#define RGX_CR_ISP_RENDER_MODE_SHIFT                      (0U)
#define RGX_CR_ISP_RENDER_MODE_CLRMSK                     (0xFFFFFFFCU)
#define RGX_CR_ISP_RENDER_MODE_NORM                       (0x00000000U)
#define RGX_CR_ISP_RENDER_MODE_FAST_2D                    (0x00000002U)
#define RGX_CR_ISP_RENDER_MODE_FAST_SCALE                 (0x00000003U)
#define RGX_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT (0U)
#define RGX_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_EN    (0x00000001U)


/*
    Register RGX_CR_ISP_CTL
*/
#define RGX_CR_ISP_CTL                                    (0x0FB0U)
#define RGX_CR_ISP_CTL_MASKFULL                           (IMG_UINT64_C(0x00000000007BF8FF))
#define RGX_CR_ISP_CTL_DBUFFER_COUNT_SHIFT                (20U)
#define RGX_CR_ISP_CTL_DBUFFER_COUNT_CLRMSK               (0xFF8FFFFFU)
#define RGX_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT           (19U)
#define RGX_CR_ISP_CTL_OVERLAP_CHECK_MODE_CLRMSK          (0xFFF7FFFFU)
#define RGX_CR_ISP_CTL_OVERLAP_CHECK_MODE_EN              (0x00080000U)
#define RGX_CR_ISP_CTL_UPFRONT_DEPTH_DISABLE_SHIFT        (17U)
#define RGX_CR_ISP_CTL_UPFRONT_DEPTH_DISABLE_CLRMSK       (0xFFFDFFFFU)
#define RGX_CR_ISP_CTL_UPFRONT_DEPTH_DISABLE_EN           (0x00020000U)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ONE_SHIFT              (16U)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ONE_CLRMSK             (0xFFFEFFFFU)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ONE_EN                 (0x00010000U)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ZERO_SHIFT             (15U)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ZERO_CLRMSK            (0xFFFF7FFFU)
#define RGX_CR_ISP_CTL_DEPTH_CLAMP_ZERO_EN                (0x00008000U)
#define RGX_CR_ISP_CTL_LINE_SAMPLE_SHIFT                  (14U)
#define RGX_CR_ISP_CTL_LINE_SAMPLE_CLRMSK                 (0xFFFFBFFFU)
#define RGX_CR_ISP_CTL_LINE_SAMPLE_EN                     (0x00004000U)
#define RGX_CR_ISP_CTL_LINE_STYLE_SHIFT                   (13U)
#define RGX_CR_ISP_CTL_LINE_STYLE_CLRMSK                  (0xFFFFDFFFU)
#define RGX_CR_ISP_CTL_LINE_STYLE_EN                      (0x00002000U)
#define RGX_CR_ISP_CTL_LINE_STYLE_SINGLE_PIXEL_SHIFT      (12U)
#define RGX_CR_ISP_CTL_LINE_STYLE_SINGLE_PIXEL_CLRMSK     (0xFFFFEFFFU)
#define RGX_CR_ISP_CTL_LINE_STYLE_SINGLE_PIXEL_EN         (0x00001000U)
#define RGX_CR_ISP_CTL_DBIAS_IS_INT_SHIFT                 (11U)
#define RGX_CR_ISP_CTL_DBIAS_IS_INT_CLRMSK                (0xFFFFF7FFU)
#define RGX_CR_ISP_CTL_DBIAS_IS_INT_EN                    (0x00000800U)
#define RGX_CR_ISP_CTL_UPASS_START_SHIFT                  (0U)
#define RGX_CR_ISP_CTL_UPASS_START_CLRMSK                 (0xFFFFFF00U)


/*
    Register group: RGX_CR_MEM_TILING_CFG, with 8 repeats
*/
#define RGX_CR_MEM_TILING_CFG_REPEATCOUNT                 (8U)
/*
    Register RGX_CR_MEM_TILING_CFG0
*/
#define RGX_CR_MEM_TILING_CFG0                            (0x12D8U)
#define RGX_CR_MEM_TILING_CFG0_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG0_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG0_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG0_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG0_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG0_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG0_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG0_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG0_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG0_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG1
*/
#define RGX_CR_MEM_TILING_CFG1                            (0x12E0U)
#define RGX_CR_MEM_TILING_CFG1_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG1_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG1_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG1_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG1_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG1_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG1_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG1_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG1_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG1_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG2
*/
#define RGX_CR_MEM_TILING_CFG2                            (0x12E8U)
#define RGX_CR_MEM_TILING_CFG2_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG2_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG2_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG2_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG2_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG2_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG2_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG2_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG2_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG2_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG3
*/
#define RGX_CR_MEM_TILING_CFG3                            (0x12F0U)
#define RGX_CR_MEM_TILING_CFG3_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG3_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG3_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG3_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG3_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG3_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG3_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG3_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG3_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG3_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG4
*/
#define RGX_CR_MEM_TILING_CFG4                            (0x12F8U)
#define RGX_CR_MEM_TILING_CFG4_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG4_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG4_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG4_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG4_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG4_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG4_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG4_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG4_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG4_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG5
*/
#define RGX_CR_MEM_TILING_CFG5                            (0x1300U)
#define RGX_CR_MEM_TILING_CFG5_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG5_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG5_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG5_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG5_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG5_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG5_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG5_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG5_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG5_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG6
*/
#define RGX_CR_MEM_TILING_CFG6                            (0x1308U)
#define RGX_CR_MEM_TILING_CFG6_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG6_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG6_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG6_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG6_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG6_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG6_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG6_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG6_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG6_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MEM_TILING_CFG7
*/
#define RGX_CR_MEM_TILING_CFG7                            (0x1310U)
#define RGX_CR_MEM_TILING_CFG7_MASKFULL                   (IMG_UINT64_C(0xFFFFFFFF0FFFFFFF))
#define RGX_CR_MEM_TILING_CFG7_XSTRIDE_SHIFT              (61U)
#define RGX_CR_MEM_TILING_CFG7_XSTRIDE_CLRMSK             (IMG_UINT64_C(0x1FFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG7_ENABLE_SHIFT               (60U)
#define RGX_CR_MEM_TILING_CFG7_ENABLE_CLRMSK              (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MEM_TILING_CFG7_ENABLE_EN                  (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MEM_TILING_CFG7_MAX_ADDRESS_SHIFT          (32U)
#define RGX_CR_MEM_TILING_CFG7_MAX_ADDRESS_CLRMSK         (IMG_UINT64_C(0xF0000000FFFFFFFF))
#define RGX_CR_MEM_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE      (4096U)
#define RGX_CR_MEM_TILING_CFG7_MIN_ADDRESS_SHIFT          (0U)
#define RGX_CR_MEM_TILING_CFG7_MIN_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFF0000000))
#define RGX_CR_MEM_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT     (12U)
#define RGX_CR_MEM_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_USC_TIMER
*/
#define RGX_CR_USC_TIMER                                  (0x46C8U)
#define RGX_CR_USC_TIMER_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_USC_TIMER_CNT_SHIFT                        (0U)
#define RGX_CR_USC_TIMER_CNT_CLRMSK                       (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_CR_USC_TIMER_CNT
*/
#define RGX_CR_USC_TIMER_CNT                              (0x46D0U)
#define RGX_CR_USC_TIMER_CNT_MASKFULL                     (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_USC_TIMER_CNT_RESET_SHIFT                  (0U)
#define RGX_CR_USC_TIMER_CNT_RESET_CLRMSK                 (0xFFFFFFFEU)
#define RGX_CR_USC_TIMER_CNT_RESET_EN                     (0x00000001U)


/*
    Register RGX_CR_TE_CHECKSUM
*/
#define RGX_CR_TE_CHECKSUM                                (0x5110U)
#define RGX_CR_TE_CHECKSUM_MASKFULL                       (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_TE_CHECKSUM_VALUE_SHIFT                    (0U)
#define RGX_CR_TE_CHECKSUM_VALUE_CLRMSK                   (0x00000000U)


/*
    Register RGX_CR_USC_UVB_CHECKSUM
*/
#define RGX_CR_USC_UVB_CHECKSUM                           (0x5118U)
#define RGX_CR_USC_UVB_CHECKSUM_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_USC_UVB_CHECKSUM_VALUE_SHIFT               (0U)
#define RGX_CR_USC_UVB_CHECKSUM_VALUE_CLRMSK              (0x00000000U)


/*
    Register RGX_CR_TE_TMA_CHECKSUM
*/
#define RGX_CR_TE_TMA_CHECKSUM                            (0x5128U)
#define RGX_CR_TE_TMA_CHECKSUM_MASKFULL                   (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_TE_TMA_CHECKSUM_VALUE_SHIFT                (0U)
#define RGX_CR_TE_TMA_CHECKSUM_VALUE_CLRMSK               (0x00000000U)


/*
    Register RGX_CR_CDM_PDS_CHECKSUM
*/
#define RGX_CR_CDM_PDS_CHECKSUM                           (0x5130U)
#define RGX_CR_CDM_PDS_CHECKSUM_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_CDM_PDS_CHECKSUM_VALUE_SHIFT               (0U)
#define RGX_CR_CDM_PDS_CHECKSUM_VALUE_CLRMSK              (0x00000000U)


/*
    Register RGX_CR_VCE_CHECKSUM
*/
#define RGX_CR_VCE_CHECKSUM                               (0x5030U)
#define RGX_CR_VCE_CHECKSUM_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_VCE_CHECKSUM_VALUE_SHIFT                   (0U)
#define RGX_CR_VCE_CHECKSUM_VALUE_CLRMSK                  (0x00000000U)


/*
    Register RGX_CR_ISP_PDS_CHECKSUM
*/
#define RGX_CR_ISP_PDS_CHECKSUM                           (0x5038U)
#define RGX_CR_ISP_PDS_CHECKSUM_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT               (0U)
#define RGX_CR_ISP_PDS_CHECKSUM_VALUE_CLRMSK              (0x00000000U)


/*
    Register RGX_CR_ISP_TPF_CHECKSUM
*/
#define RGX_CR_ISP_TPF_CHECKSUM                           (0x5040U)
#define RGX_CR_ISP_TPF_CHECKSUM_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT               (0U)
#define RGX_CR_ISP_TPF_CHECKSUM_VALUE_CLRMSK              (0x00000000U)


/*
    Register RGX_CR_TFPU_CHECKSUM
*/
#define RGX_CR_TFPU_CHECKSUM                              (0x5048U)
#define RGX_CR_TFPU_CHECKSUM_MASKFULL                     (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_TFPU_CHECKSUM_VALUE_SHIFT                  (0U)
#define RGX_CR_TFPU_CHECKSUM_VALUE_CLRMSK                 (0x00000000U)


/*
    Register RGX_CR_ZLS_CHECKSUM
*/
#define RGX_CR_ZLS_CHECKSUM                               (0x5050U)
#define RGX_CR_ZLS_CHECKSUM_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_ZLS_CHECKSUM_VALUE_SHIFT                   (0U)
#define RGX_CR_ZLS_CHECKSUM_VALUE_CLRMSK                  (0x00000000U)


/*
    Register RGX_CR_PBE_CHECKSUM_3D
*/
#define RGX_CR_PBE_CHECKSUM_3D__PBE_CHECKSUM_2D           (0x5058U)
#define RGX_CR_PBE_CHECKSUM_3D__PBE_CHECKSUM_2D__MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PBE_CHECKSUM_3D__PBE_CHECKSUM_2D__VALUE_SHIFT (0U)
#define RGX_CR_PBE_CHECKSUM_3D__PBE_CHECKSUM_2D__VALUE_CLRMSK (0x00000000U)


/*
    Register RGX_CR_PBE_CHECKSUM
*/
#define RGX_CR_PBE_CHECKSUM                               (0x5058U)
#define RGX_CR_PBE_CHECKSUM_MASKFULL                      (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PBE_CHECKSUM_VALUE_SHIFT                   (0U)
#define RGX_CR_PBE_CHECKSUM_VALUE_CLRMSK                  (0x00000000U)


/*
    Register RGX_CR_PDS_DOUTM_STM_CHECKSUM
*/
#define RGX_CR_PDS_DOUTM_STM_CHECKSUM                     (0x5060U)
#define RGX_CR_PDS_DOUTM_STM_CHECKSUM_MASKFULL            (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PDS_DOUTM_STM_CHECKSUM_VALUE_SHIFT         (0U)
#define RGX_CR_PDS_DOUTM_STM_CHECKSUM_VALUE_CLRMSK        (0x00000000U)


/*
    Register RGX_CR_IFPU_ISP_CHECKSUM
*/
#define RGX_CR_IFPU_ISP_CHECKSUM                          (0x5068U)
#define RGX_CR_IFPU_ISP_CHECKSUM_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT              (0U)
#define RGX_CR_IFPU_ISP_CHECKSUM_VALUE_CLRMSK             (0x00000000U)


/*
    Register RGX_CR_PPP_CLIP_CHECKSUM
*/
#define RGX_CR_PPP_CLIP_CHECKSUM                          (0x5120U)
#define RGX_CR_PPP_CLIP_CHECKSUM_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT              (0U)
#define RGX_CR_PPP_CLIP_CHECKSUM_VALUE_CLRMSK             (0x00000000U)


/*
    Register RGX_CR_VCE_PRIM_CHECKSUM
*/
#define RGX_CR_VCE_PRIM_CHECKSUM                          (0x5140U)
#define RGX_CR_VCE_PRIM_CHECKSUM_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_VCE_PRIM_CHECKSUM_VALUE_SHIFT              (0U)
#define RGX_CR_VCE_PRIM_CHECKSUM_VALUE_CLRMSK             (0x00000000U)


/*
    Register RGX_CR_TDM_PDS_CHECKSUM
*/
#define RGX_CR_TDM_PDS_CHECKSUM                           (0x5148U)
#define RGX_CR_TDM_PDS_CHECKSUM_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_TDM_PDS_CHECKSUM_VALUE_SHIFT               (0U)
#define RGX_CR_TDM_PDS_CHECKSUM_VALUE_CLRMSK              (0x00000000U)


/*
    Register RGX_CR_PBE_CHECKSUM_2D
*/
#define RGX_CR_PBE_CHECKSUM_2D                            (0x5158U)
#define RGX_CR_PBE_CHECKSUM_2D_MASKFULL                   (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PBE_CHECKSUM_2D_VALUE_SHIFT                (0U)
#define RGX_CR_PBE_CHECKSUM_2D_VALUE_CLRMSK               (0x00000000U)


/*
    Register RGX_CR_PERF_PHASE_GEOM
*/
#define RGX_CR_PERF_PHASE_GEOM                            (0x6008U)
#define RGX_CR_PERF_PHASE_GEOM_MASKFULL                   (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_PHASE_GEOM_COUNT_SHIFT                (0U)
#define RGX_CR_PERF_PHASE_GEOM_COUNT_CLRMSK               (0x00000000U)


/*
    Register RGX_CR_PERF_PHASE_FRAG
*/
#define RGX_CR_PERF_PHASE_FRAG                            (0x6010U)
#define RGX_CR_PERF_PHASE_FRAG_MASKFULL                   (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_PHASE_FRAG_COUNT_SHIFT                (0U)
#define RGX_CR_PERF_PHASE_FRAG_COUNT_CLRMSK               (0x00000000U)


/*
    Register RGX_CR_PERF_PHASE_COMP
*/
#define RGX_CR_PERF_PHASE_COMP                            (0x6018U)
#define RGX_CR_PERF_PHASE_COMP_MASKFULL                   (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_PHASE_COMP_COUNT_SHIFT                (0U)
#define RGX_CR_PERF_PHASE_COMP_COUNT_CLRMSK               (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_GEOM_TOTAL
*/
#define RGX_CR_PERF_CYCLE_GEOM_TOTAL                      (0x6020U)
#define RGX_CR_PERF_CYCLE_GEOM_TOTAL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_GEOM_TOTAL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_CYCLE_GEOM_TOTAL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_FRAG_TOTAL
*/
#define RGX_CR_PERF_CYCLE_FRAG_TOTAL                      (0x6028U)
#define RGX_CR_PERF_CYCLE_FRAG_TOTAL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_FRAG_TOTAL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_CYCLE_FRAG_TOTAL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_COMP_TOTAL
*/
#define RGX_CR_PERF_CYCLE_COMP_TOTAL                      (0x6030U)
#define RGX_CR_PERF_CYCLE_COMP_TOTAL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_COMP_TOTAL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_CYCLE_COMP_TOTAL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_GEOM_OR_FRAG_TOTAL
*/
#define RGX_CR_PERF_CYCLE_GEOM_OR_FRAG_TOTAL              (0x6038U)
#define RGX_CR_PERF_CYCLE_GEOM_OR_FRAG_TOTAL_MASKFULL     (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_GEOM_OR_FRAG_TOTAL_COUNT_SHIFT  (0U)
#define RGX_CR_PERF_CYCLE_GEOM_OR_FRAG_TOTAL_COUNT_CLRMSK (0x00000000U)


/*
    Register RGX_CR_PERF_PHASE_2D
*/
#define RGX_CR_PERF_PHASE_2D                              (0x6050U)
#define RGX_CR_PERF_PHASE_2D_MASKFULL                     (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_PHASE_2D_COUNT_SHIFT                  (0U)
#define RGX_CR_PERF_PHASE_2D_COUNT_CLRMSK                 (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_2D_TOTAL
*/
#define RGX_CR_PERF_CYCLE_2D_TOTAL                        (0x6058U)
#define RGX_CR_PERF_CYCLE_2D_TOTAL_MASKFULL               (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_2D_TOTAL_COUNT_SHIFT            (0U)
#define RGX_CR_PERF_CYCLE_2D_TOTAL_COUNT_CLRMSK           (0x00000000U)


/*
    Register RGX_CR_PERF_SLC0_READ_STALL
*/
#define RGX_CR_PERF_SLC0_READ_STALL                       (0x60B8U)
#define RGX_CR_PERF_SLC0_READ_STALL_MASKFULL              (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT           (0U)
#define RGX_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK          (0x00000000U)


/*
    Register RGX_CR_PERF_SLC0_WRITE_STALL
*/
#define RGX_CR_PERF_SLC0_WRITE_STALL                      (0x60C0U)
#define RGX_CR_PERF_SLC0_WRITE_STALL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_SLC1_READ_STALL
*/
#define RGX_CR_PERF_SLC1_READ_STALL                       (0x60E0U)
#define RGX_CR_PERF_SLC1_READ_STALL_MASKFULL              (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT           (0U)
#define RGX_CR_PERF_SLC1_READ_STALL_COUNT_CLRMSK          (0x00000000U)


/*
    Register RGX_CR_PERF_SLC1_WRITE_STALL
*/
#define RGX_CR_PERF_SLC1_WRITE_STALL                      (0x60E8U)
#define RGX_CR_PERF_SLC1_WRITE_STALL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_SLC1_WRITE_STALL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_SLC2_READ_STALL
*/
#define RGX_CR_PERF_SLC2_READ_STALL                       (0x6158U)
#define RGX_CR_PERF_SLC2_READ_STALL_MASKFULL              (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT           (0U)
#define RGX_CR_PERF_SLC2_READ_STALL_COUNT_CLRMSK          (0x00000000U)


/*
    Register RGX_CR_PERF_SLC2_WRITE_STALL
*/
#define RGX_CR_PERF_SLC2_WRITE_STALL                      (0x6160U)
#define RGX_CR_PERF_SLC2_WRITE_STALL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_SLC2_WRITE_STALL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_SLC3_READ_STALL
*/
#define RGX_CR_PERF_SLC3_READ_STALL                       (0x6180U)
#define RGX_CR_PERF_SLC3_READ_STALL_MASKFULL              (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT           (0U)
#define RGX_CR_PERF_SLC3_READ_STALL_COUNT_CLRMSK          (0x00000000U)


/*
    Register RGX_CR_PERF_SLC3_WRITE_STALL
*/
#define RGX_CR_PERF_SLC3_WRITE_STALL                      (0x6188U)
#define RGX_CR_PERF_SLC3_WRITE_STALL_MASKFULL             (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT          (0U)
#define RGX_CR_PERF_SLC3_WRITE_STALL_COUNT_CLRMSK         (0x00000000U)


/*
    Register RGX_CR_PERF_CYCLE_GEOM_AND_FRAG_TOTAL
*/
#define RGX_CR_PERF_CYCLE_GEOM_AND_FRAG_TOTAL             (0x6408U)
#define RGX_CR_PERF_CYCLE_GEOM_AND_FRAG_TOTAL_MASKFULL    (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_PERF_CYCLE_GEOM_AND_FRAG_TOTAL_COUNT_SHIFT (0U)
#define RGX_CR_PERF_CYCLE_GEOM_AND_FRAG_TOTAL_COUNT_CLRMSK (0x00000000U)


/*
    Register group: RGX_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT       (16U)
/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG0
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0                  (0x7020U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG1
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1                  (0x7028U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG1_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG2
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2                  (0x7030U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG2_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG3
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3                  (0x7038U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG3_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG4
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4                  (0x7040U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG4_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG5
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5                  (0x7048U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG5_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG6
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6                  (0x7050U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG6_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG7
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7                  (0x7058U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG7_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG8
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8                  (0x7060U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG8_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG9
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9                  (0x7068U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL         (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT   (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK  (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN      (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT       (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK      (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT   (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG9_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG10
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10                 (0x7070U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG10_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG11
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11                 (0x7078U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG11_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG12
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12                 (0x7080U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG12_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG13
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13                 (0x7088U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG13_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG14
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14                 (0x7090U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG14_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_ADDR_REMAP_CONFIG15
*/
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15                 (0x7098U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL        (IMG_UINT64_C(0x3FFFF0FFFFFFF0FF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT (61U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT  (60U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN     (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT      (44U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK     (IMG_UINT64_C(0xF0000FFFFFFFFFFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT  (12U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000FFF))
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_MMU_CONTEXT_SHIFT (0U)
#define RGX_CR_FWCORE_ADDR_REMAP_CONFIG15_MMU_CONTEXT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FWCORE_WRAPPER_NMI_ENABLE
*/
#define RGX_CR_FWCORE_WRAPPER_NMI_ENABLE                  (0x70A0U)
#define RGX_CR_FWCORE_WRAPPER_NMI_ENABLE_MASKFULL         (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_FWCORE_WRAPPER_NMI_ENABLE_EVENT_EN_SHIFT   (0U)
#define RGX_CR_FWCORE_WRAPPER_NMI_ENABLE_EVENT_EN_CLRMSK  (0xFFFFFFFEU)
#define RGX_CR_FWCORE_WRAPPER_NMI_ENABLE_EVENT_EN_EN      (0x00000001U)


/*
    Register RGX_CR_FWCORE_WRAPPER_NMI_EVENT
*/
#define RGX_CR_FWCORE_WRAPPER_NMI_EVENT                   (0x70A8U)
#define RGX_CR_FWCORE_WRAPPER_NMI_EVENT_MASKFULL          (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT  (0U)
#define RGX_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_EN     (0x00000001U)


/*
    Register RGX_CR_FWCORE_WRAPPER_RESET_VECTOR
*/
#define RGX_CR_FWCORE_WRAPPER_RESET_VECTOR                (0x70B0U)
#define RGX_CR_FWCORE_WRAPPER_RESET_VECTOR_MASKFULL       (IMG_UINT64_C(0x00000000FFFFFFFE))
#define RGX_CR_FWCORE_WRAPPER_RESET_VECTOR_ADDR_SHIFT     (1U)
#define RGX_CR_FWCORE_WRAPPER_RESET_VECTOR_ADDR_CLRMSK    (0x00000001U)


/*
    Register RGX_CR_FWCORE_WRAPPER_NMI_VECTOR
*/
#define RGX_CR_FWCORE_WRAPPER_NMI_VECTOR                  (0x70B8U)
#define RGX_CR_FWCORE_WRAPPER_NMI_VECTOR_MASKFULL         (IMG_UINT64_C(0x00000000FFFFFFFE))
#define RGX_CR_FWCORE_WRAPPER_NMI_VECTOR_ADDR_SHIFT       (1U)
#define RGX_CR_FWCORE_WRAPPER_NMI_VECTOR_ADDR_CLRMSK      (0x00000001U)


/*
    Register RGX_CR_JONES_IDLE
*/
#define RGX_CR_JONES_IDLE                                 (0x8328U)
#define RGX_CR_JONES_IDLE_MASKFULL                        (IMG_UINT64_C(0x000000000007FEFF))
#define RGX_CR_JONES_IDLE_ASC_SHIFT                       (18U)
#define RGX_CR_JONES_IDLE_ASC_CLRMSK                      (0xFFFBFFFFU)
#define RGX_CR_JONES_IDLE_ASC_EN                          (0x00040000U)
#define RGX_CR_JONES_IDLE_RCE_SHIFT                       (17U)
#define RGX_CR_JONES_IDLE_RCE_CLRMSK                      (0xFFFDFFFFU)
#define RGX_CR_JONES_IDLE_RCE_EN                          (0x00020000U)
#define RGX_CR_JONES_IDLE_AXI2IMG_SHIFT                   (16U)
#define RGX_CR_JONES_IDLE_AXI2IMG_CLRMSK                  (0xFFFEFFFFU)
#define RGX_CR_JONES_IDLE_AXI2IMG_EN                      (0x00010000U)
#define RGX_CR_JONES_IDLE_SLC_SHIFT                       (15U)
#define RGX_CR_JONES_IDLE_SLC_CLRMSK                      (0xFFFF7FFFU)
#define RGX_CR_JONES_IDLE_SLC_EN                          (0x00008000U)
#define RGX_CR_JONES_IDLE_TDM_SHIFT                       (14U)
#define RGX_CR_JONES_IDLE_TDM_CLRMSK                      (0xFFFFBFFFU)
#define RGX_CR_JONES_IDLE_TDM_EN                          (0x00004000U)
#define RGX_CR_JONES_IDLE_FB_CDC_TLA_SHIFT                (13U)
#define RGX_CR_JONES_IDLE_FB_CDC_TLA_CLRMSK               (0xFFFFDFFFU)
#define RGX_CR_JONES_IDLE_FB_CDC_TLA_EN                   (0x00002000U)
#define RGX_CR_JONES_IDLE_FB_CDC_SHIFT                    (12U)
#define RGX_CR_JONES_IDLE_FB_CDC_CLRMSK                   (0xFFFFEFFFU)
#define RGX_CR_JONES_IDLE_FB_CDC_EN                       (0x00001000U)
#define RGX_CR_JONES_IDLE_MMU_SHIFT                       (11U)
#define RGX_CR_JONES_IDLE_MMU_CLRMSK                      (0xFFFFF7FFU)
#define RGX_CR_JONES_IDLE_MMU_EN                          (0x00000800U)
#define RGX_CR_JONES_IDLE_DFU_SHIFT                       (10U)
#define RGX_CR_JONES_IDLE_DFU_CLRMSK                      (0xFFFFFBFFU)
#define RGX_CR_JONES_IDLE_DFU_EN                          (0x00000400U)
#define RGX_CR_JONES_IDLE_GARTEN_SHIFT                    (9U)
#define RGX_CR_JONES_IDLE_GARTEN_CLRMSK                   (0xFFFFFDFFU)
#define RGX_CR_JONES_IDLE_GARTEN_EN                       (0x00000200U)
#define RGX_CR_JONES_IDLE_SOCIF_SHIFT                     (7U)
#define RGX_CR_JONES_IDLE_SOCIF_CLRMSK                    (0xFFFFFF7FU)
#define RGX_CR_JONES_IDLE_SOCIF_EN                        (0x00000080U)
#define RGX_CR_JONES_IDLE_TILING_SHIFT                    (6U)
#define RGX_CR_JONES_IDLE_TILING_CLRMSK                   (0xFFFFFFBFU)
#define RGX_CR_JONES_IDLE_TILING_EN                       (0x00000040U)
#define RGX_CR_JONES_IDLE_IPP_SHIFT                       (5U)
#define RGX_CR_JONES_IDLE_IPP_CLRMSK                      (0xFFFFFFDFU)
#define RGX_CR_JONES_IDLE_IPP_EN                          (0x00000020U)
#define RGX_CR_JONES_IDLE_USC_GMUTEX_SHIFT                (4U)
#define RGX_CR_JONES_IDLE_USC_GMUTEX_CLRMSK               (0xFFFFFFEFU)
#define RGX_CR_JONES_IDLE_USC_GMUTEX_EN                   (0x00000010U)
#define RGX_CR_JONES_IDLE_PM_SHIFT                        (3U)
#define RGX_CR_JONES_IDLE_PM_CLRMSK                       (0xFFFFFFF7U)
#define RGX_CR_JONES_IDLE_PM_EN                           (0x00000008U)
#define RGX_CR_JONES_IDLE_CDM_SHIFT                       (2U)
#define RGX_CR_JONES_IDLE_CDM_CLRMSK                      (0xFFFFFFFBU)
#define RGX_CR_JONES_IDLE_CDM_EN                          (0x00000004U)
#define RGX_CR_JONES_IDLE_DCE_SHIFT                       (1U)
#define RGX_CR_JONES_IDLE_DCE_CLRMSK                      (0xFFFFFFFDU)
#define RGX_CR_JONES_IDLE_DCE_EN                          (0x00000002U)
#define RGX_CR_JONES_IDLE_BIF_SHIFT                       (0U)
#define RGX_CR_JONES_IDLE_BIF_CLRMSK                      (0xFFFFFFFEU)
#define RGX_CR_JONES_IDLE_BIF_EN                          (0x00000001U)


/*
    Register RGX_CR_SYS_BUS_SECURE
*/
#define RGX_CR_SYS_BUS_SECURE                             (0xA100U)
#define RGX_CR_SYS_BUS_SECURE__SYS_BUS_SECURE_RESET__MASKFULL (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_SYS_BUS_SECURE_MASKFULL                    (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_SYS_BUS_SECURE_ENABLE_SHIFT                (0U)
#define RGX_CR_SYS_BUS_SECURE_ENABLE_CLRMSK               (0xFFFFFFFEU)
#define RGX_CR_SYS_BUS_SECURE_ENABLE_EN                   (0x00000001U)


/*
    Register RGX_CR_MMU_CBASE_MAPPING_CONTEXT
*/
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT                  (0xE140U)
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT__MMU_GT_V3__MASKFULL (IMG_UINT64_C(0x000000000000001F))
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT_MASKFULL         (IMG_UINT64_C(0x00000000000000FF))
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT         (0U)
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK        (0xFFFFFF00U)
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT__MMU_GT_V3__ID_SHIFT (0U)
#define RGX_CR_MMU_CBASE_MAPPING_CONTEXT__MMU_GT_V3__ID_CLRMSK (0xFFFFFFE0U)


/*
    Register RGX_CR_MMU_CBASE_MAPPING
*/
#define RGX_CR_MMU_CBASE_MAPPING__VPU                     (0x1E010U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__MASKFULL           (IMG_UINT64_C(0x000000001FFFFFFF))
#define RGX_CR_MMU_CBASE_MAPPING__VPU__INVALID_SHIFT      (28U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__INVALID_CLRMSK     (0xEFFFFFFFU)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__INVALID_EN         (0x10000000U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__BASE_ADDR_SHIFT    (0U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__BASE_ADDR_CLRMSK   (0xF0000000U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__BASE_ADDR_ALIGNSHIFT (12U)
#define RGX_CR_MMU_CBASE_MAPPING__VPU__BASE_ADDR_ALIGNSIZE (4096U)


/*
    Register RGX_CR_MMU_CBASE_MAPPING
*/
#define RGX_CR_MMU_CBASE_MAPPING                          (0xE148U)
#define RGX_CR_MMU_CBASE_MAPPING_MASKFULL                 (IMG_UINT64_C(0x000000001FFFFFFF))
#define RGX_CR_MMU_CBASE_MAPPING_INVALID_SHIFT            (28U)
#define RGX_CR_MMU_CBASE_MAPPING_INVALID_CLRMSK           (0xEFFFFFFFU)
#define RGX_CR_MMU_CBASE_MAPPING_INVALID_EN               (0x10000000U)
#define RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT          (0U)
#define RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK         (0xF0000000U)
#define RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT     (12U)
#define RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE      (4096U)


/*
    Register RGX_CR_MMU_FAULT_STATUS1
*/
#define RGX_CR_MMU_FAULT_STATUS1                          (0xE150U)
#define RGX_CR_MMU_FAULT_STATUS1_MASKFULL                 (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS1_LEVEL_SHIFT              (62U)
#define RGX_CR_MMU_FAULT_STATUS1_LEVEL_CLRMSK             (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS1_REQ_ID_SHIFT             (56U)
#define RGX_CR_MMU_FAULT_STATUS1_REQ_ID_CLRMSK            (IMG_UINT64_C(0xC0FFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS1_CONTEXT_SHIFT            (48U)
#define RGX_CR_MMU_FAULT_STATUS1_CONTEXT_CLRMSK           (IMG_UINT64_C(0xFF00FFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS1_ADDRESS_SHIFT            (4U)
#define RGX_CR_MMU_FAULT_STATUS1_ADDRESS_CLRMSK           (IMG_UINT64_C(0xFFFF00000000000F))
#define RGX_CR_MMU_FAULT_STATUS1_RNW_SHIFT                (3U)
#define RGX_CR_MMU_FAULT_STATUS1_RNW_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_MMU_FAULT_STATUS1_RNW_EN                   (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_MMU_FAULT_STATUS1_TYPE_SHIFT               (1U)
#define RGX_CR_MMU_FAULT_STATUS1_TYPE_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFFF9))
#define RGX_CR_MMU_FAULT_STATUS1_FAULT_SHIFT              (0U)
#define RGX_CR_MMU_FAULT_STATUS1_FAULT_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_MMU_FAULT_STATUS1_FAULT_EN                 (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_MMU_FAULT_STATUS2
*/
#define RGX_CR_MMU_FAULT_STATUS2                          (0xE158U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__MASKFULL        (IMG_UINT64_C(0x00000000003FFFFF))
#define RGX_CR_MMU_FAULT_STATUS2_MASKFULL                 (IMG_UINT64_C(0x000000003FFF07FF))
#define RGX_CR_MMU_FAULT_STATUS2_WRITEBACK_SHIFT          (29U)
#define RGX_CR_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK         (0xDFFFFFFFU)
#define RGX_CR_MMU_FAULT_STATUS2_WRITEBACK_EN             (0x20000000U)
#define RGX_CR_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT        (28U)
#define RGX_CR_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK       (0xEFFFFFFFU)
#define RGX_CR_MMU_FAULT_STATUS2_CLEANUNIQUE_EN           (0x10000000U)
#define RGX_CR_MMU_FAULT_STATUS2_BANK_SHIFT               (24U)
#define RGX_CR_MMU_FAULT_STATUS2_BANK_CLRMSK              (0xF0FFFFFFU)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__FBM_FAULT_SHIFT (21U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__FBM_FAULT_CLRMSK (0xFFDFFFFFU)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__FBM_FAULT_EN    (0x00200000U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__WRITEBACK_SHIFT (20U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__WRITEBACK_CLRMSK (0xFFEFFFFFU)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__WRITEBACK_EN    (0x00100000U)
#define RGX_CR_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT          (16U)
#define RGX_CR_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK         (0xFF00FFFFU)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__BIF_ID_SHIFT    (12U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__BIF_ID_CLRMSK   (0xFFF00FFFU)
#define RGX_CR_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT          (10U)
#define RGX_CR_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK         (0xFFFFFBFFU)
#define RGX_CR_MMU_FAULT_STATUS2_FBM_FAULT_EN             (0x00000400U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__BANK_SHIFT      (8U)
#define RGX_CR_MMU_FAULT_STATUS2__ALBTOP__BANK_CLRMSK     (0xFFFFF0FFU)
#define RGX_CR_MMU_FAULT_STATUS2_BIF_ID_SHIFT             (0U)
#define RGX_CR_MMU_FAULT_STATUS2_BIF_ID_CLRMSK            (0xFFFFFC00U)
#define RGX_CR_MMU_FAULT_STATUS2_ACTIVE_ID_SHIFT          (0U)
#define RGX_CR_MMU_FAULT_STATUS2_ACTIVE_ID_CLRMSK         (0xFFFFFF00U)


/*
    Register RGX_CR_MMU_FAULT_STATUS_META
*/
#define RGX_CR_MMU_FAULT_STATUS_META                      (0xE160U)
#define RGX_CR_MMU_FAULT_STATUS_META_MASKFULL             (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT          (62U)
#define RGX_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK         (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT         (56U)
#define RGX_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK        (IMG_UINT64_C(0xC0FFFFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT        (48U)
#define RGX_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK       (IMG_UINT64_C(0xFF00FFFFFFFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT        (4U)
#define RGX_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK       (IMG_UINT64_C(0xFFFF00000000000F))
#define RGX_CR_MMU_FAULT_STATUS_META_RNW_SHIFT            (3U)
#define RGX_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_MMU_FAULT_STATUS_META_RNW_EN               (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT           (1U)
#define RGX_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFFFFFFF9))
#define RGX_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT          (0U)
#define RGX_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_MMU_FAULT_STATUS_META_FAULT_EN             (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_MMU_FAULT_STATUS2_META
*/
#define RGX_CR_MMU_FAULT_STATUS2_META                     (0xE198U)
#define RGX_CR_MMU_FAULT_STATUS2_META__ALBTOP__MASKFULL   (IMG_UINT64_C(0x0000000000001FFF))
#define RGX_CR_MMU_FAULT_STATUS2_META_MASKFULL            (IMG_UINT64_C(0x0000000000003FFF))
#define RGX_CR_MMU_FAULT_STATUS2_META_WRITEBACK_SHIFT     (13U)
#define RGX_CR_MMU_FAULT_STATUS2_META_WRITEBACK_CLRMSK    (0xFFFFDFFFU)
#define RGX_CR_MMU_FAULT_STATUS2_META_WRITEBACK_EN        (0x00002000U)
#define RGX_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_SHIFT   (12U)
#define RGX_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_CLRMSK  (0xFFFFEFFFU)
#define RGX_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_EN      (0x00001000U)
#define RGX_CR_MMU_FAULT_STATUS2_META__ALBTOP__WRITEBACK_SHIFT (12U)
#define RGX_CR_MMU_FAULT_STATUS2_META__ALBTOP__WRITEBACK_CLRMSK (0xFFFFEFFFU)
#define RGX_CR_MMU_FAULT_STATUS2_META__ALBTOP__WRITEBACK_EN (0x00001000U)
#define RGX_CR_MMU_FAULT_STATUS2_META_BANK_SHIFT          (8U)
#define RGX_CR_MMU_FAULT_STATUS2_META_BANK_CLRMSK         (0xFFFFF0FFU)
#define RGX_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_SHIFT     (0U)
#define RGX_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_CLRMSK    (0xFFFFFF00U)
#define RGX_CR_MMU_FAULT_STATUS2_META_ACTIVE_ID_SHIFT     (0U)
#define RGX_CR_MMU_FAULT_STATUS2_META_ACTIVE_ID_CLRMSK    (0xFFFFFF00U)


/*
    Register RGX_CR_MMU_FAULT_STATUS_PM
*/
#define RGX_CR_MMU_FAULT_STATUS_PM                        (0xE130U)
#define RGX_CR_MMU_FAULT_STATUS_PM__PM_RECYCLE__MASKFULL  (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_PM_MASKFULL               (IMG_UINT64_C(0x0000000007FFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_PM_DM_SHIFT               (24U)
#define RGX_CR_MMU_FAULT_STATUS_PM_DM_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFF8FFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_PM__PM_RECYCLE__DM_SHIFT  (24U)
#define RGX_CR_MMU_FAULT_STATUS_PM__PM_RECYCLE__DM_CLRMSK (IMG_UINT64_C(0xFFFFFFFFF0FFFFFF))
#define RGX_CR_MMU_FAULT_STATUS_PM_RNW_SHIFT              (23U)
#define RGX_CR_MMU_FAULT_STATUS_PM_RNW_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_MMU_FAULT_STATUS_PM_RNW_EN                 (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_MMU_FAULT_STATUS_PM_ADDRESS_SHIFT          (3U)
#define RGX_CR_MMU_FAULT_STATUS_PM_ADDRESS_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFF800007))
#define RGX_CR_MMU_FAULT_STATUS_PM_LEVEL_SHIFT            (1U)
#define RGX_CR_MMU_FAULT_STATUS_PM_LEVEL_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFFFF9))
#define RGX_CR_MMU_FAULT_STATUS_PM_FAULT_SHIFT            (0U)
#define RGX_CR_MMU_FAULT_STATUS_PM_FAULT_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_MMU_FAULT_STATUS_PM_FAULT_EN               (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_MMU_STATUS
*/
#define RGX_CR_MMU_STATUS__VPU                            (0x10288U)
#define RGX_CR_MMU_STATUS__VPU__MASKFULL                  (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_STATUS__VPU__MMU_STALLED_SHIFT         (40U)
#define RGX_CR_MMU_STATUS__VPU__MMU_STALLED_CLRMSK        (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_MMU_STATUS__VPU__MMU_STALLED_EN            (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_MMU_STATUS__VPU__PM_WRITES_SHIFT           (38U)
#define RGX_CR_MMU_STATUS__VPU__PM_WRITES_CLRMSK          (IMG_UINT64_C(0xFFFFFF3FFFFFFFFF))
#define RGX_CR_MMU_STATUS__VPU__PM_READS_SHIFT            (36U)
#define RGX_CR_MMU_STATUS__VPU__PM_READS_CLRMSK           (IMG_UINT64_C(0xFFFFFFCFFFFFFFFF))
#define RGX_CR_MMU_STATUS__VPU__PC_READS_SHIFT            (24U)
#define RGX_CR_MMU_STATUS__VPU__PC_READS_CLRMSK           (IMG_UINT64_C(0xFFFFFFF000FFFFFF))
#define RGX_CR_MMU_STATUS__VPU__PD_READS_SHIFT            (12U)
#define RGX_CR_MMU_STATUS__VPU__PD_READS_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFF000FFF))
#define RGX_CR_MMU_STATUS__VPU__PT_READS_SHIFT            (0U)
#define RGX_CR_MMU_STATUS__VPU__PT_READS_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFF000))


/*
    Register RGX_CR_MMU_STATUS
*/
#define RGX_CR_MMU_STATUS                                 (0xE170U)
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__MASKFULL (IMG_UINT64_C(0x000003FFFFFFFFFF))
#define RGX_CR_MMU_STATUS_MASKFULL                        (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__MMU_STALLED_SHIFT (41U)
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__MMU_STALLED_CLRMSK (IMG_UINT64_C(0xFFFFFDFFFFFFFFFF))
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__MMU_STALLED_EN (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_MMU_STATUS_MMU_STALLED_SHIFT               (40U)
#define RGX_CR_MMU_STATUS_MMU_STALLED_CLRMSK              (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_MMU_STATUS_MMU_STALLED_EN                  (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__PM_WRITES_SHIFT (39U)
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__PM_WRITES_CLRMSK (IMG_UINT64_C(0xFFFFFE7FFFFFFFFF))
#define RGX_CR_MMU_STATUS_PM_WRITES_SHIFT                 (38U)
#define RGX_CR_MMU_STATUS_PM_WRITES_CLRMSK                (IMG_UINT64_C(0xFFFFFF3FFFFFFFFF))
#define RGX_CR_MMU_STATUS_PM_READS_SHIFT                  (36U)
#define RGX_CR_MMU_STATUS_PM_READS_CLRMSK                 (IMG_UINT64_C(0xFFFFFFCFFFFFFFFF))
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__PM_READS_SHIFT (36U)
#define RGX_CR_MMU_STATUS__CATURIX_TOP_INFRASTRUCTURE__PM_READS_CLRMSK (IMG_UINT64_C(0xFFFFFF8FFFFFFFFF))
#define RGX_CR_MMU_STATUS_PC_READS_SHIFT                  (24U)
#define RGX_CR_MMU_STATUS_PC_READS_CLRMSK                 (IMG_UINT64_C(0xFFFFFFF000FFFFFF))
#define RGX_CR_MMU_STATUS_PD_READS_SHIFT                  (12U)
#define RGX_CR_MMU_STATUS_PD_READS_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFF000FFF))
#define RGX_CR_MMU_STATUS_PT_READS_SHIFT                  (0U)
#define RGX_CR_MMU_STATUS_PT_READS_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFFFFF000))


/*
    Register RGX_CR_MMU_ENTRY_STATUS
*/
#define RGX_CR_MMU_ENTRY_STATUS__VPU                      (0x1E028U)
#define RGX_CR_MMU_ENTRY_STATUS__VPU__MASKFULL            (IMG_UINT64_C(0x000000FFFFFF80FF))
#define RGX_CR_MMU_ENTRY_STATUS__VPU__ADDRESS_SHIFT       (15U)
#define RGX_CR_MMU_ENTRY_STATUS__VPU__ADDRESS_CLRMSK      (IMG_UINT64_C(0xFFFFFF0000007FFF))
#define RGX_CR_MMU_ENTRY_STATUS__VPU__CONTEXT_ID_SHIFT    (0U)
#define RGX_CR_MMU_ENTRY_STATUS__VPU__CONTEXT_ID_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_MMU_ENTRY_STATUS
*/
#define RGX_CR_MMU_ENTRY_STATUS                           (0xE178U)
#define RGX_CR_MMU_ENTRY_STATUS_MASKFULL                  (IMG_UINT64_C(0x000000FFFFFF80FF))
#define RGX_CR_MMU_ENTRY_STATUS_ADDRESS_SHIFT             (15U)
#define RGX_CR_MMU_ENTRY_STATUS_ADDRESS_CLRMSK            (IMG_UINT64_C(0xFFFFFF0000007FFF))
#define RGX_CR_MMU_ENTRY_STATUS_CONTEXT_ID_SHIFT          (0U)
#define RGX_CR_MMU_ENTRY_STATUS_CONTEXT_ID_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_MMU_ENTRY
*/
#define RGX_CR_MMU_ENTRY__VPU                             (0x1E030U)
#define RGX_CR_MMU_ENTRY__VPU__MASKFULL                   (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_MMU_ENTRY__VPU__ENABLE_SHIFT               (1U)
#define RGX_CR_MMU_ENTRY__VPU__ENABLE_CLRMSK              (0xFFFFFFFDU)
#define RGX_CR_MMU_ENTRY__VPU__ENABLE_EN                  (0x00000002U)
#define RGX_CR_MMU_ENTRY__VPU__PENDING_SHIFT              (0U)
#define RGX_CR_MMU_ENTRY__VPU__PENDING_CLRMSK             (0xFFFFFFFEU)
#define RGX_CR_MMU_ENTRY__VPU__PENDING_EN                 (0x00000001U)


/*
    Register RGX_CR_MMU_ENTRY
*/
#define RGX_CR_MMU_ENTRY                                  (0xE180U)
#define RGX_CR_MMU_ENTRY_MASKFULL                         (IMG_UINT64_C(0x0000000000000003))
#define RGX_CR_MMU_ENTRY_ENABLE_SHIFT                     (1U)
#define RGX_CR_MMU_ENTRY_ENABLE_CLRMSK                    (0xFFFFFFFDU)
#define RGX_CR_MMU_ENTRY_ENABLE_EN                        (0x00000002U)
#define RGX_CR_MMU_ENTRY_PENDING_SHIFT                    (0U)
#define RGX_CR_MMU_ENTRY_PENDING_CLRMSK                   (0xFFFFFFFEU)
#define RGX_CR_MMU_ENTRY_PENDING_EN                       (0x00000001U)


/*
    Register RGX_CR_MMU_PAGE_SIZE_RANGE_ONE
*/
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE                    (0xE350U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_MASKFULL           (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT    (38U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_CLRMSK   (IMG_UINT64_C(0xFFFFFE3FFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_SHIFT     (19U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_CLRMSK    (IMG_UINT64_C(0xFFFFFFC00007FFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSIZE (2097152U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_SHIFT    (0U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFFFF80000))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSIZE (2097152U)


/*
    Register RGX_CR_MMU_PAGE_SIZE_RANGE_TWO
*/
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO                    (0xE358U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_MASKFULL           (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT    (38U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_CLRMSK   (IMG_UINT64_C(0xFFFFFE3FFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_SHIFT     (19U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_CLRMSK    (IMG_UINT64_C(0xFFFFFFC00007FFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSIZE (2097152U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_SHIFT    (0U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFFFF80000))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSIZE (2097152U)


/*
    Register RGX_CR_MMU_PAGE_SIZE_RANGE_THREE
*/
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE                  (0xE360U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_MASKFULL         (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_SHIFT  (38U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0xFFFFFE3FFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_SHIFT   (19U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFFC00007FFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSIZE (2097152U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_SHIFT  (0U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFF80000))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSIZE (2097152U)


/*
    Register RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR
*/
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR                   (0xE368U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_MASKFULL          (IMG_UINT64_C(0x000001FFFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_SHIFT   (38U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_CLRMSK  (IMG_UINT64_C(0xFFFFFE3FFFFFFFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_SHIFT    (19U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFC00007FFFF))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSIZE (2097152U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_SHIFT   (0U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFF80000))
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSHIFT (21U)
#define RGX_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSIZE (2097152U)


/*
    Register RGX_CR_SLC_STATUS1
*/
#define RGX_CR_SLC_STATUS1                                (0xE210U)
#define RGX_CR_SLC_STATUS1_MASKFULL                       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_SHIFT        (48U)
#define RGX_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_CLRMSK       (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
#define RGX_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT  (36U)
#define RGX_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0xFFFF000FFFFFFFFF))
#define RGX_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT  (24U)
#define RGX_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0xFFFFFFF000FFFFFF))
#define RGX_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT   (12U)
#define RGX_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFF000FFF))
#define RGX_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT   (0U)
#define RGX_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFF000))


/*
    Register RGX_CR_SLC_STATUS2
*/
#define RGX_CR_SLC_STATUS2                                (0xE218U)
#define RGX_CR_SLC_STATUS2_MASKFULL                       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SLC_STATUS2_SLC_SIZE_IN_KB_SHIFT           (48U)
#define RGX_CR_SLC_STATUS2_SLC_SIZE_IN_KB_CLRMSK          (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
#define RGX_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT  (36U)
#define RGX_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0xFFFF000FFFFFFFFF))
#define RGX_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT  (24U)
#define RGX_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0xFFFFFFF000FFFFFF))
#define RGX_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT   (12U)
#define RGX_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFF000FFF))
#define RGX_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT   (0U)
#define RGX_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFF000))


/*
    Register RGX_CR_SLC_IDLE
*/
#define RGX_CR_SLC_IDLE                                   (0xE230U)
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__MASKFULL (IMG_UINT64_C(0x0000000001FFFFFF))
#define RGX_CR_SLC_IDLE_MASKFULL                          (IMG_UINT64_C(0x00000000001FFFFF))
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__FBCDC_ARB_SHIFT (24U)
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__FBCDC_ARB_CLRMSK (0xFEFFFFFFU)
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__FBCDC_ARB_EN (0x01000000U)
#define RGX_CR_SLC_IDLE_FBCDC_ARB_SHIFT                   (20U)
#define RGX_CR_SLC_IDLE_FBCDC_ARB_CLRMSK                  (0xFFEFFFFFU)
#define RGX_CR_SLC_IDLE_FBCDC_ARB_EN                      (0x00100000U)
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__OWDB_SHIFT (20U)
#define RGX_CR_SLC_IDLE__COHERENCY_AND_ALRIF_GT0__OWDB_CLRMSK (0xFF0FFFFFU)
#define RGX_CR_SLC_IDLE_OWDB_SHIFT                        (16U)
#define RGX_CR_SLC_IDLE_OWDB_CLRMSK                       (0xFFF0FFFFU)
#define RGX_CR_SLC_IDLE_ACE_CLBS_SHIFT                    (16U)
#define RGX_CR_SLC_IDLE_ACE_CLBS_CLRMSK                   (0xFFF0FFFFU)
#define RGX_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT              (12U)
#define RGX_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK             (0xFFFF0FFFU)
#define RGX_CR_SLC_IDLE_CACHE_BANKS_SHIFT                 (4U)
#define RGX_CR_SLC_IDLE_CACHE_BANKS_CLRMSK                (0xFFFFF00FU)
#define RGX_CR_SLC_IDLE_MMU_SHIFT                         (3U)
#define RGX_CR_SLC_IDLE_MMU_CLRMSK                        (0xFFFFFFF7U)
#define RGX_CR_SLC_IDLE_MMU_EN                            (0x00000008U)
#define RGX_CR_SLC_IDLE_CCM_SHIFT                         (2U)
#define RGX_CR_SLC_IDLE_CCM_CLRMSK                        (0xFFFFFFFBU)
#define RGX_CR_SLC_IDLE_CCM_EN                            (0x00000004U)
#define RGX_CR_SLC_IDLE_RDI_SHIFT                         (1U)
#define RGX_CR_SLC_IDLE_RDI_CLRMSK                        (0xFFFFFFFDU)
#define RGX_CR_SLC_IDLE_RDI_EN                            (0x00000002U)
#define RGX_CR_SLC_IDLE_XBAR_SHIFT                        (0U)
#define RGX_CR_SLC_IDLE_XBAR_CLRMSK                       (0xFFFFFFFEU)
#define RGX_CR_SLC_IDLE_XBAR_EN                           (0x00000001U)


/*
    Register RGX_CR_SLC_FAULT_STOP_STATUS
*/
#define RGX_CR_SLC_FAULT_STOP_STATUS__VPU                 (0x1E240U)
#define RGX_CR_SLC_FAULT_STOP_STATUS__VPU__MASKFULL       (IMG_UINT64_C(0x000000000001FFFF))
#define RGX_CR_SLC_FAULT_STOP_STATUS__VPU__BIF_SHIFT      (0U)
#define RGX_CR_SLC_FAULT_STOP_STATUS__VPU__BIF_CLRMSK     (0xFFFE0000U)


/*
    Register RGX_CR_SLC_FAULT_STOP_STATUS
*/
#define RGX_CR_SLC_FAULT_STOP_STATUS                      (0xE240U)
#define RGX_CR_SLC_FAULT_STOP_STATUS_MASKFULL             (IMG_UINT64_C(0x000000000001FFFF))
#define RGX_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT            (0U)
#define RGX_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK           (0xFFFE0000U)


/*
    Register RGX_CR_SLC_STATUS_DEBUG
*/
#define RGX_CR_SLC_STATUS_DEBUG__VPU                      (0x1E260U)
#define RGX_CR_SLC_STATUS_DEBUG__VPU__MASKFULL            (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_SLC_STATUS_DEBUG__VPU__ERR_COH_REQ_SHIFT   (16U)
#define RGX_CR_SLC_STATUS_DEBUG__VPU__ERR_COH_REQ_CLRMSK  (0x0000FFFFU)
#define RGX_CR_SLC_STATUS_DEBUG__VPU__ERR_ADDR_ALIAS_SHIFT (0U)
#define RGX_CR_SLC_STATUS_DEBUG__VPU__ERR_ADDR_ALIAS_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_SLC_STATUS_DEBUG
*/
#define RGX_CR_SLC_STATUS_DEBUG                           (0xE260U)
#define RGX_CR_SLC_STATUS_DEBUG_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT         (16U)
#define RGX_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK        (0x0000FFFFU)
#define RGX_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT      (0U)
#define RGX_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK     (0xFFFF0000U)


/*
    Register RGX_CR_HMMU_OSID_PAGE_SIZE
*/
#define RGX_CR_HMMU_OSID_PAGE_SIZE                        (0x80000U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_MASKFULL               (IMG_UINT64_C(0x0000000077777777))
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_7_SHIFT           (28U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_7_CLRMSK          (0x8FFFFFFFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_6_SHIFT           (24U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_6_CLRMSK          (0xF8FFFFFFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_5_SHIFT           (20U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_5_CLRMSK          (0xFF8FFFFFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_4_SHIFT           (16U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_4_CLRMSK          (0xFFF8FFFFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_3_SHIFT           (12U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_3_CLRMSK          (0xFFFF8FFFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_2_SHIFT           (8U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_2_CLRMSK          (0xFFFFF8FFU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_1_SHIFT           (4U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_1_CLRMSK          (0xFFFFFF8FU)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_0_SHIFT           (0U)
#define RGX_CR_HMMU_OSID_PAGE_SIZE_OSID_0_CLRMSK          (0xFFFFFFF8U)


/*
    Register RGX_CR_HMMU_BYPASS
*/
#define RGX_CR_HMMU_BYPASS                                (0x80008U)
#define RGX_CR_HMMU_BYPASS_MASKFULL                       (IMG_UINT64_C(0x00000000000000FF))
#define RGX_CR_HMMU_BYPASS_EN_SHIFT                       (0U)
#define RGX_CR_HMMU_BYPASS_EN_CLRMSK                      (0xFFFFFF00U)


/*
    Register RGX_CR_HMMU_INVAL
*/
#define RGX_CR_HMMU_INVAL                                 (0x80010U)
#define RGX_CR_HMMU_INVAL_MASKFULL                        (IMG_UINT64_C(0x000000000000007F))
#define RGX_CR_HMMU_INVAL_OS_ID_SHIFT                     (4U)
#define RGX_CR_HMMU_INVAL_OS_ID_CLRMSK                    (0xFFFFFF8FU)
#define RGX_CR_HMMU_INVAL_ALL_OS_IDS_SHIFT                (3U)
#define RGX_CR_HMMU_INVAL_ALL_OS_IDS_CLRMSK               (0xFFFFFFF7U)
#define RGX_CR_HMMU_INVAL_ALL_OS_IDS_EN                   (0x00000008U)
#define RGX_CR_HMMU_INVAL_HPC_SHIFT                       (2U)
#define RGX_CR_HMMU_INVAL_HPC_CLRMSK                      (0xFFFFFFFBU)
#define RGX_CR_HMMU_INVAL_HPC_EN                          (0x00000004U)
#define RGX_CR_HMMU_INVAL_HPD_SHIFT                       (1U)
#define RGX_CR_HMMU_INVAL_HPD_CLRMSK                      (0xFFFFFFFDU)
#define RGX_CR_HMMU_INVAL_HPD_EN                          (0x00000002U)
#define RGX_CR_HMMU_INVAL_HPT_SHIFT                       (0U)
#define RGX_CR_HMMU_INVAL_HPT_CLRMSK                      (0xFFFFFFFEU)
#define RGX_CR_HMMU_INVAL_HPT_EN                          (0x00000001U)


/*
    Register RGX_CR_HMMU_HPC_BASE_MAPPING0
*/
#define RGX_CR_HMMU_HPC_BASE_MAPPING0                     (0x80018U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_MASKFULL            (IMG_UINT64_C(0xFFFFFFF1FFFFFFF1))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_ADDR1_SHIFT         (36U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_ADDR1_CLRMSK        (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID1_SHIFT        (32U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID1_CLRMSK       (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID1_EN           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_ADDR0_SHIFT         (4U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_ADDR0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID0_SHIFT        (0U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID0_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_HPC_BASE_MAPPING0_VALID0_EN           (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_HMMU_HPC_BASE_MAPPING1
*/
#define RGX_CR_HMMU_HPC_BASE_MAPPING1                     (0x80020U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_MASKFULL            (IMG_UINT64_C(0xFFFFFFF1FFFFFFF1))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_ADDR3_SHIFT         (36U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_ADDR3_CLRMSK        (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID3_SHIFT        (32U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID3_CLRMSK       (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID3_EN           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_ADDR2_SHIFT         (4U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_ADDR2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID2_SHIFT        (0U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID2_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_HPC_BASE_MAPPING1_VALID2_EN           (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_HMMU_HPC_BASE_MAPPING2
*/
#define RGX_CR_HMMU_HPC_BASE_MAPPING2                     (0x80028U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_MASKFULL            (IMG_UINT64_C(0xFFFFFFF1FFFFFFF1))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_ADDR5_SHIFT         (36U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_ADDR5_CLRMSK        (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID5_SHIFT        (32U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID5_CLRMSK       (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID5_EN           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_ADDR4_SHIFT         (4U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_ADDR4_CLRMSK        (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID4_SHIFT        (0U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID4_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_HPC_BASE_MAPPING2_VALID4_EN           (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_HMMU_HPC_BASE_MAPPING3
*/
#define RGX_CR_HMMU_HPC_BASE_MAPPING3                     (0x80030U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_MASKFULL            (IMG_UINT64_C(0xFFFFFFF1FFFFFFF1))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_ADDR7_SHIFT         (36U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_ADDR7_CLRMSK        (IMG_UINT64_C(0x0000000FFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID7_SHIFT        (32U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID7_CLRMSK       (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID7_EN           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_ADDR6_SHIFT         (4U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_ADDR6_CLRMSK        (IMG_UINT64_C(0xFFFFFFFF0000000F))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID6_SHIFT        (0U)
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID6_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_HPC_BASE_MAPPING3_VALID6_EN           (IMG_UINT64_C(0x0000000000000001))


/*
    Register group: RGX_CR_HMMU_PAGE_FAULT_INFO, with 8 repeats
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO_REPEATCOUNT           (8U)
/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO0
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO0                      (0x80038U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO0_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO0_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO0_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO0_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO0_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO1
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO1                      (0x80040U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO1_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO1_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO1_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO1_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO1_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO2
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO2                      (0x80048U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO2_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO2_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO2_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO2_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO2_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO3
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO3                      (0x80050U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO3_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO3_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO3_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO3_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO3_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO4
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO4                      (0x80058U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO4_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO4_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO4_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO4_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO4_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO5
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO5                      (0x80060U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO5_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO5_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO5_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO5_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO5_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO6
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO6                      (0x80068U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO6_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO6_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO6_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO6_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO6_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PAGE_FAULT_INFO7
*/
#define RGX_CR_HMMU_PAGE_FAULT_INFO7                      (0x80070U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO7_MASKFULL             (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PAGE_FAULT_INFO7_ADDR_SHIFT           (2U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO7_ADDR_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PAGE_FAULT_INFO7_LEVEL_SHIFT          (0U)
#define RGX_CR_HMMU_PAGE_FAULT_INFO7_LEVEL_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register group: RGX_CR_HMMU_PENDING_ENTRY_INFO, with 8 repeats
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO_REPEATCOUNT        (8U)
/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO0
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0                   (0x800C0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO0_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO1
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1                   (0x800C8U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO1_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO2
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2                   (0x800D0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO2_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO3
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3                   (0x800D8U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO3_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO4
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4                   (0x800E0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO4_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO5
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5                   (0x800E8U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO5_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO6
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6                   (0x800F0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO6_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY_INFO7
*/
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7                   (0x800F8U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7_MASKFULL          (IMG_UINT64_C(0x000000003FFFFFFF))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7_ADDR_SHIFT        (2U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7_ADDR_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFC0000003))
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7_LEVEL_SHIFT       (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_INFO7_LEVEL_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFC))


/*
    Register RGX_CR_HMMU_HOST_IRQ_ENABLE
*/
#define RGX_CR_HMMU_HOST_IRQ_ENABLE                       (0x80100U)
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_MASKFULL              (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_SHIFT  (3U)
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_EN     (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_PM_SHIFT (2U)
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_PM_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_READONLY_FAULT_PM_EN  (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PAGE_FAULT_SHIFT      (1U)
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PAGE_FAULT_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PAGE_FAULT_EN         (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PENDING_ENTRY_SHIFT   (0U)
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PENDING_ENTRY_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_HOST_IRQ_ENABLE_PENDING_ENTRY_EN      (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_HMMU_PENDING_ENTRY
*/
#define RGX_CR_HMMU_PENDING_ENTRY                         (0x80108U)
#define RGX_CR_HMMU_PENDING_ENTRY_MASKFULL                (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_HMMU_PENDING_ENTRY_ENABLE_SHIFT            (0U)
#define RGX_CR_HMMU_PENDING_ENTRY_ENABLE_CLRMSK           (0xFFFFFFFEU)
#define RGX_CR_HMMU_PENDING_ENTRY_ENABLE_EN               (0x00000001U)


/*
    Register RGX_CR_HMMU_FAULT_STATUS
*/
#define RGX_CR_HMMU_FAULT_STATUS                          (0x80120U)
#define RGX_CR_HMMU_FAULT_STATUS_MASKFULL                 (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID7_SHIFT (31U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID7_CLRMSK (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID7_EN (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID6_SHIFT (30U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID6_CLRMSK (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID6_EN (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID5_SHIFT (29U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID5_CLRMSK (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID5_EN (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID4_SHIFT (28U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID4_CLRMSK (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID4_EN (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID3_SHIFT (27U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID3_CLRMSK (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID3_EN (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID2_SHIFT (26U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID2_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID2_EN (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID1_SHIFT (25U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID1_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID1_EN (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID0_SHIFT (24U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID0_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_PM_OSID0_EN (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID7_SHIFT (23U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID7_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID7_EN  (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID6_SHIFT (22U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID6_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID6_EN  (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID5_SHIFT (21U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID5_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID5_EN  (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID4_SHIFT (20U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID4_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID4_EN  (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID3_SHIFT (19U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID3_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID3_EN  (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID2_SHIFT (18U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID2_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID2_EN  (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID1_SHIFT (17U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID1_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID1_EN  (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID0_SHIFT (16U)
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID0_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_HMMU_FAULT_STATUS_READONLY_FAULT_OSID0_EN  (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID7_SHIFT (15U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID7_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID7_EN   (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID6_SHIFT (14U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID6_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID6_EN   (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID5_SHIFT (13U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID5_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID5_EN   (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID4_SHIFT (12U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID4_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID4_EN   (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID3_SHIFT (11U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID3_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID3_EN   (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID2_SHIFT (10U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID2_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID2_EN   (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID1_SHIFT (9U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID1_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID1_EN   (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID0_SHIFT (8U)
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID0_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_HMMU_FAULT_STATUS_PENDING_ENTRY_OSID0_EN   (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID7_SHIFT   (7U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID7_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID7_EN      (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID6_SHIFT   (6U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID6_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID6_EN      (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID5_SHIFT   (5U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID5_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID5_EN      (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID4_SHIFT   (4U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID4_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID4_EN      (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID3_SHIFT   (3U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID3_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID3_EN      (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID2_SHIFT   (2U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID2_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID2_EN      (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID1_SHIFT   (1U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID1_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID1_EN      (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID0_SHIFT   (0U)
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID0_CLRMSK  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_HMMU_FAULT_STATUS_PAGE_FAULT_OSID0_EN      (IMG_UINT64_C(0x0000000000000001))


/*
    Register group: RGX_CR_HMMU_READONLY_FAULT_INFO, with 8 repeats
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO_REPEATCOUNT       (8U)
/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO0
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO0                  (0x80190U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO0_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO0_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO0_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO1
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO1                  (0x80198U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO1_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO1_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO1_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO2
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO2                  (0x801A0U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO2_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO2_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO2_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO3
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO3                  (0x801A8U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO3_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO3_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO3_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO4
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO4                  (0x801B0U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO4_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO4_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO4_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO5
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO5                  (0x801B8U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO5_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO5_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO5_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO6
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO6                  (0x801C0U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO6_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO6_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO6_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_INFO7
*/
#define RGX_CR_HMMU_READONLY_FAULT_INFO7                  (0x801C8U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO7_MASKFULL         (IMG_UINT64_C(0x000000FFFFFFFFF0))
#define RGX_CR_HMMU_READONLY_FAULT_INFO7_ADDR_SHIFT       (4U)
#define RGX_CR_HMMU_READONLY_FAULT_INFO7_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF000000000F))


/*
    Register group: RGX_CR_HMMU_READONLY_FAULT_PM_INFO, with 8 repeats
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO_REPEATCOUNT    (8U)
/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO0
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO0               (0x801D0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO0_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO0_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO0_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO1
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO1               (0x801D8U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO1_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO1_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO1_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO2
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO2               (0x801E0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO2_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO2_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO2_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO3
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO3               (0x801E8U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO3_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO3_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO3_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO4
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO4               (0x801F0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO4_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO4_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO4_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO5
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO5               (0x801F8U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO5_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO5_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO5_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO6
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO6               (0x80200U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO6_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO6_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO6_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_HMMU_READONLY_FAULT_PM_INFO7
*/
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO7               (0x80208U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO7_MASKFULL      (IMG_UINT64_C(0x000000000FFFFFFF))
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO7_ADDR_SHIFT    (0U)
#define RGX_CR_HMMU_READONLY_FAULT_PM_INFO7_ADDR_CLRMSK   (IMG_UINT64_C(0xFFFFFFFFF0000000))


/*
    Register RGX_CR_ACE_CTRL
*/
#define RGX_CR_ACE_CTRL__VPU                              (0x1E320U)
#define RGX_CR_ACE_CTRL__VPU__MASKFULL                    (IMG_UINT64_C(0x00000000007FCFFF))
#define RGX_CR_ACE_CTRL__VPU__CLB_AXQOS_SHIFT             (19U)
#define RGX_CR_ACE_CTRL__VPU__CLB_AXQOS_CLRMSK            (0xFF87FFFFU)
#define RGX_CR_ACE_CTRL__VPU__PM_MMU_AXCACHE_SHIFT        (15U)
#define RGX_CR_ACE_CTRL__VPU__PM_MMU_AXCACHE_CLRMSK       (0xFFF87FFFU)
#define RGX_CR_ACE_CTRL__VPU__ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
#define RGX_CR_ACE_CTRL__VPU__ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0xFFFFBFFFU)
#define RGX_CR_ACE_CTRL__VPU__ENABLE_NONSECURE_PROT_MATCH_EN (0x00004000U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_SHIFT           (8U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_CLRMSK          (0xFFFFF0FFU)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_DEVICE_NON_BUFFERABLE (0x00000000U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_DEVICE_BUFFERABLE (0x00000100U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0x00000200U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0x00000300U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0x00000600U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0x00000E00U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0x00000700U)
#define RGX_CR_ACE_CTRL__VPU__MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0x00000F00U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_SHIFT           (4U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_CLRMSK          (0xFFFFFF0FU)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_DEVICE_NON_BUFFERABLE (0x00000000U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_DEVICE_BUFFERABLE (0x00000010U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0x00000020U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0x00000030U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0x000000A0U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0x000000E0U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0x000000B0U)
#define RGX_CR_ACE_CTRL__VPU__MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0x000000F0U)
#define RGX_CR_ACE_CTRL__VPU__MMU_DOMAIN_SHIFT            (2U)
#define RGX_CR_ACE_CTRL__VPU__MMU_DOMAIN_CLRMSK           (0xFFFFFFF3U)
#define RGX_CR_ACE_CTRL__VPU__COH_DOMAIN_SHIFT            (1U)
#define RGX_CR_ACE_CTRL__VPU__COH_DOMAIN_CLRMSK           (0xFFFFFFFDU)
#define RGX_CR_ACE_CTRL__VPU__COH_DOMAIN_INNER_SHAREABLE  (0x00000000U)
#define RGX_CR_ACE_CTRL__VPU__COH_DOMAIN_OUTER_SHAREABLE  (0x00000002U)
#define RGX_CR_ACE_CTRL__VPU__NON_COH_DOMAIN_SHIFT        (0U)
#define RGX_CR_ACE_CTRL__VPU__NON_COH_DOMAIN_CLRMSK       (0xFFFFFFFEU)
#define RGX_CR_ACE_CTRL__VPU__NON_COH_DOMAIN_NON_SHAREABLE (0x00000000U)
#define RGX_CR_ACE_CTRL__VPU__NON_COH_DOMAIN_SYSTEM       (0x00000001U)


/*
    Register RGX_CR_ACE_CTRL
*/
#define RGX_CR_ACE_CTRL                                   (0xE320U)
#define RGX_CR_ACE_CTRL_MASKFULL                          (IMG_UINT64_C(0x0000000000FFCFFF))
#define RGX_CR_ACE_CTRL_DISABLE_EMPTY_BURST_REMOVAL_SHIFT (23U)
#define RGX_CR_ACE_CTRL_DISABLE_EMPTY_BURST_REMOVAL_CLRMSK (0xFF7FFFFFU)
#define RGX_CR_ACE_CTRL_DISABLE_EMPTY_BURST_REMOVAL_EN    (0x00800000U)
#define RGX_CR_ACE_CTRL_CLB_AXQOS_SHIFT                   (19U)
#define RGX_CR_ACE_CTRL_CLB_AXQOS_CLRMSK                  (0xFF87FFFFU)
#define RGX_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT              (15U)
#define RGX_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK             (0xFFF87FFFU)
#define RGX_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
#define RGX_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0xFFFFBFFFU)
#define RGX_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN    (0x00004000U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_SHIFT                 (8U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK                (0xFFFFF0FFU)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (0x00000000U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE     (0x00000100U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0x00000200U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE  (0x00000300U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0x00000600U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0x00000E00U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0x00000700U)
#define RGX_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0x00000F00U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_SHIFT                 (4U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK                (0xFFFFFF0FU)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (0x00000000U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE     (0x00000010U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0x00000020U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE  (0x00000030U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0x000000A0U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0x000000E0U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0x000000B0U)
#define RGX_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0x000000F0U)
#define RGX_CR_ACE_CTRL_MMU_DOMAIN_SHIFT                  (2U)
#define RGX_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK                 (0xFFFFFFF3U)
#define RGX_CR_ACE_CTRL_COH_DOMAIN_SHIFT                  (1U)
#define RGX_CR_ACE_CTRL_COH_DOMAIN_CLRMSK                 (0xFFFFFFFDU)
#define RGX_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE        (0x00000000U)
#define RGX_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE        (0x00000002U)
#define RGX_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT              (0U)
#define RGX_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK             (0xFFFFFFFEU)
#define RGX_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE      (0x00000000U)
#define RGX_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM             (0x00000001U)


/*
    Register RGX_CR_SOC_AXI
*/
#define RGX_CR_SOC_AXI                                    (0xE338U)
#define RGX_CR_SOC_AXI_MASKFULL                           (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (3U)
#define RGX_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0xFFFFFFF7U)
#define RGX_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_EN (0x00000008U)
#define RGX_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (2U)
#define RGX_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0xFFFFFFFBU)
#define RGX_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_EN (0x00000004U)
#define RGX_CR_SOC_AXI_COHERENCY_SUPPORT_SHIFT            (0U)
#define RGX_CR_SOC_AXI_COHERENCY_SUPPORT_CLRMSK           (0xFFFFFFFCU)
#define RGX_CR_SOC_AXI_COHERENCY_SUPPORT_NO_COHERENCY     (0x00000000U)
#define RGX_CR_SOC_AXI_COHERENCY_SUPPORT_ACE_LITE_COHERENCY (0x00000001U)
#define RGX_CR_SOC_AXI_COHERENCY_SUPPORT_FULL_ACE_COHERENCY (0x00000002U)


/*
    Register RGX_CR_CONTEXT_MAPPING0
*/
#define RGX_CR_CONTEXT_MAPPING0                           (0xF078U)
#define RGX_CR_CONTEXT_MAPPING0_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_CONTEXT_MAPPING0_2D_SHIFT                  (24U)
#define RGX_CR_CONTEXT_MAPPING0_2D_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFF00FFFFFF))
#define RGX_CR_CONTEXT_MAPPING0_CDM_SHIFT                 (16U)
#define RGX_CR_CONTEXT_MAPPING0_CDM_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFF00FFFF))
#define RGX_CR_CONTEXT_MAPPING0_3D_SHIFT                  (8U)
#define RGX_CR_CONTEXT_MAPPING0_3D_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFFFF00FF))
#define RGX_CR_CONTEXT_MAPPING0_GEOM_SHIFT                (0U)
#define RGX_CR_CONTEXT_MAPPING0_GEOM_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_CONTEXT_MAPPING2
*/
#define RGX_CR_CONTEXT_MAPPING2                           (0xF088U)
#define RGX_CR_CONTEXT_MAPPING2_MASKFULL                  (IMG_UINT64_C(0x0000000000FFFFFF))
#define RGX_CR_CONTEXT_MAPPING2_ALIST0_SHIFT              (16U)
#define RGX_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK             (0xFF00FFFFU)
#define RGX_CR_CONTEXT_MAPPING2_TE0_SHIFT                 (8U)
#define RGX_CR_CONTEXT_MAPPING2_TE0_CLRMSK                (0xFFFF00FFU)
#define RGX_CR_CONTEXT_MAPPING2_VCE0_SHIFT                (0U)
#define RGX_CR_CONTEXT_MAPPING2_VCE0_CLRMSK               (0xFFFFFF00U)


/*
    Register RGX_CR_CONTEXT_MAPPING3
*/
#define RGX_CR_CONTEXT_MAPPING3                           (0xF090U)
#define RGX_CR_CONTEXT_MAPPING3_MASKFULL                  (IMG_UINT64_C(0x0000000000FFFFFF))
#define RGX_CR_CONTEXT_MAPPING3_ALIST1_SHIFT              (16U)
#define RGX_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK             (0xFF00FFFFU)
#define RGX_CR_CONTEXT_MAPPING3_TE1_SHIFT                 (8U)
#define RGX_CR_CONTEXT_MAPPING3_TE1_CLRMSK                (0xFFFF00FFU)
#define RGX_CR_CONTEXT_MAPPING3_VCE1_SHIFT                (0U)
#define RGX_CR_CONTEXT_MAPPING3_VCE1_CLRMSK               (0xFFFFFF00U)


/*
    Register RGX_CR_BIF_OUTSTANDING_READ
*/
#define RGX_CR_BIF_OUTSTANDING_READ                       (0xF098U)
#define RGX_CR_BIF_OUTSTANDING_READ_MASKFULL              (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT         (0U)
#define RGX_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK        (0xFFFF0000U)


/*
    Register RGX_CR_BIF_TEXAS1_OUTSTANDING_READ
*/
#define RGX_CR_BIF_TEXAS1_OUTSTANDING_READ                (0xF0A0U)
#define RGX_CR_BIF_TEXAS1_OUTSTANDING_READ_MASKFULL       (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_BIF_TEXAS1_OUTSTANDING_READ_COUNTER_SHIFT  (0U)
#define RGX_CR_BIF_TEXAS1_OUTSTANDING_READ_COUNTER_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_BIF_TEXAS0_OUTSTANDING_READ
*/
#define RGX_CR_BIF_TEXAS0_OUTSTANDING_READ                (0xF0A8U)
#define RGX_CR_BIF_TEXAS0_OUTSTANDING_READ_MASKFULL       (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_BIF_TEXAS0_OUTSTANDING_READ_COUNTER_SHIFT  (0U)
#define RGX_CR_BIF_TEXAS0_OUTSTANDING_READ_COUNTER_CLRMSK (0xFFFF0000U)


/*
    Register RGX_CR_BIF_PFS
*/
#define RGX_CR_BIF_PFS                                    (0xF0B0U)
#define RGX_CR_BIF_PFS_MASKFULL                           (IMG_UINT64_C(0x00000000000001FF))
#define RGX_CR_BIF_PFS_SLC_STALLING_SHIFT                 (8U)
#define RGX_CR_BIF_PFS_SLC_STALLING_CLRMSK                (0xFFFFFEFFU)
#define RGX_CR_BIF_PFS_SLC_STALLING_EN                    (0x00000100U)
#define RGX_CR_BIF_PFS_TILING_IDLE_SHIFT                  (7U)
#define RGX_CR_BIF_PFS_TILING_IDLE_CLRMSK                 (0xFFFFFF7FU)
#define RGX_CR_BIF_PFS_TILING_IDLE_EN                     (0x00000080U)
#define RGX_CR_BIF_PFS_ARB_IDLE_SHIFT                     (6U)
#define RGX_CR_BIF_PFS_ARB_IDLE_CLRMSK                    (0xFFFFFFBFU)
#define RGX_CR_BIF_PFS_ARB_IDLE_EN                        (0x00000040U)
#define RGX_CR_BIF_PFS_RTN_MEM_IF_IDLE_SHIFT              (5U)
#define RGX_CR_BIF_PFS_RTN_MEM_IF_IDLE_CLRMSK             (0xFFFFFFDFU)
#define RGX_CR_BIF_PFS_RTN_MEM_IF_IDLE_EN                 (0x00000020U)
#define RGX_CR_BIF_PFS_NONMETA_REQ_COMPLETE_SHIFT         (4U)
#define RGX_CR_BIF_PFS_NONMETA_REQ_COMPLETE_CLRMSK        (0xFFFFFFEFU)
#define RGX_CR_BIF_PFS_NONMETA_REQ_COMPLETE_EN            (0x00000010U)
#define RGX_CR_BIF_PFS_NONMETA_WDATA_COMPLETE_SHIFT       (3U)
#define RGX_CR_BIF_PFS_NONMETA_WDATA_COMPLETE_CLRMSK      (0xFFFFFFF7U)
#define RGX_CR_BIF_PFS_NONMETA_WDATA_COMPLETE_EN          (0x00000008U)
#define RGX_CR_BIF_PFS_WDATA_IP_IDLE_SHIFT                (2U)
#define RGX_CR_BIF_PFS_WDATA_IP_IDLE_CLRMSK               (0xFFFFFFFBU)
#define RGX_CR_BIF_PFS_WDATA_IP_IDLE_EN                   (0x00000004U)
#define RGX_CR_BIF_PFS_REQUEST_IP_IDLE_SHIFT              (1U)
#define RGX_CR_BIF_PFS_REQUEST_IP_IDLE_CLRMSK             (0xFFFFFFFDU)
#define RGX_CR_BIF_PFS_REQUEST_IP_IDLE_EN                 (0x00000002U)
#define RGX_CR_BIF_PFS_STALL_COMPLETE_SHIFT               (0U)
#define RGX_CR_BIF_PFS_STALL_COMPLETE_CLRMSK              (0xFFFFFFFEU)
#define RGX_CR_BIF_PFS_STALL_COMPLETE_EN                  (0x00000001U)


/*
    Register RGX_CR_BIF_TEXAS0_PFS
*/
#define RGX_CR_BIF_TEXAS0_PFS                             (0xF0B8U)
#define RGX_CR_BIF_TEXAS0_PFS_MASKFULL                    (IMG_UINT64_C(0x000000000000007F))
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_INFLIGHT_SHIFT    (6U)
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_INFLIGHT_CLRMSK   (0xFFFFFFBFU)
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_INFLIGHT_EN       (0x00000040U)
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_IDLE_SHIFT        (5U)
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_IDLE_CLRMSK       (0xFFFFFFDFU)
#define RGX_CR_BIF_TEXAS0_PFS_JONES_CFI_IDLE_EN           (0x00000020U)
#define RGX_CR_BIF_TEXAS0_PFS_SLC_STALLING_SHIFT          (4U)
#define RGX_CR_BIF_TEXAS0_PFS_SLC_STALLING_CLRMSK         (0xFFFFFFEFU)
#define RGX_CR_BIF_TEXAS0_PFS_SLC_STALLING_EN             (0x00000010U)
#define RGX_CR_BIF_TEXAS0_PFS_TILING_IDLE_SHIFT           (3U)
#define RGX_CR_BIF_TEXAS0_PFS_TILING_IDLE_CLRMSK          (0xFFFFFFF7U)
#define RGX_CR_BIF_TEXAS0_PFS_TILING_IDLE_EN              (0x00000008U)
#define RGX_CR_BIF_TEXAS0_PFS_ARB_IDLE_SHIFT              (2U)
#define RGX_CR_BIF_TEXAS0_PFS_ARB_IDLE_CLRMSK             (0xFFFFFFFBU)
#define RGX_CR_BIF_TEXAS0_PFS_ARB_IDLE_EN                 (0x00000004U)
#define RGX_CR_BIF_TEXAS0_PFS_RTN_MEM_IF_IDLE_SHIFT       (1U)
#define RGX_CR_BIF_TEXAS0_PFS_RTN_MEM_IF_IDLE_CLRMSK      (0xFFFFFFFDU)
#define RGX_CR_BIF_TEXAS0_PFS_RTN_MEM_IF_IDLE_EN          (0x00000002U)
#define RGX_CR_BIF_TEXAS0_PFS_STALL_COMPLETE_SHIFT        (0U)
#define RGX_CR_BIF_TEXAS0_PFS_STALL_COMPLETE_CLRMSK       (0xFFFFFFFEU)
#define RGX_CR_BIF_TEXAS0_PFS_STALL_COMPLETE_EN           (0x00000001U)


/*
    Register RGX_CR_BIF_TEXAS1_PFS
*/
#define RGX_CR_BIF_TEXAS1_PFS                             (0xF0C8U)
#define RGX_CR_BIF_TEXAS1_PFS_MASKFULL                    (IMG_UINT64_C(0x000000000000007F))
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_PDSRW_SHIFT (6U)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_PDSRW_CLRMSK (0xFFFFFFBFU)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_PDSRW_EN (0x00000040U)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_MCU_SHIFT (5U)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_MCU_CLRMSK (0xFFFFFFDFU)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_ACCUM_STALLING_MCU_EN   (0x00000020U)
#define RGX_CR_BIF_TEXAS1_PFS_SLC_STALLING_SHIFT          (4U)
#define RGX_CR_BIF_TEXAS1_PFS_SLC_STALLING_CLRMSK         (0xFFFFFFEFU)
#define RGX_CR_BIF_TEXAS1_PFS_SLC_STALLING_EN             (0x00000010U)
#define RGX_CR_BIF_TEXAS1_PFS_TILING_IDLE_SHIFT           (3U)
#define RGX_CR_BIF_TEXAS1_PFS_TILING_IDLE_CLRMSK          (0xFFFFFFF7U)
#define RGX_CR_BIF_TEXAS1_PFS_TILING_IDLE_EN              (0x00000008U)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_IDLE_SHIFT              (2U)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_IDLE_CLRMSK             (0xFFFFFFFBU)
#define RGX_CR_BIF_TEXAS1_PFS_ARB_IDLE_EN                 (0x00000004U)
#define RGX_CR_BIF_TEXAS1_PFS_RTN_MEM_IF_IDLE_SHIFT       (1U)
#define RGX_CR_BIF_TEXAS1_PFS_RTN_MEM_IF_IDLE_CLRMSK      (0xFFFFFFFDU)
#define RGX_CR_BIF_TEXAS1_PFS_RTN_MEM_IF_IDLE_EN          (0x00000002U)
#define RGX_CR_BIF_TEXAS1_PFS_STALL_COMPLETE_SHIFT        (0U)
#define RGX_CR_BIF_TEXAS1_PFS_STALL_COMPLETE_CLRMSK       (0xFFFFFFFEU)
#define RGX_CR_BIF_TEXAS1_PFS_STALL_COMPLETE_EN           (0x00000001U)


/*
    Register RGX_CR_JONES_FIX
*/
#define RGX_CR_JONES_FIX__ROGUE3                          (0xF0C0U)
#define RGX_CR_JONES_FIX__ROGUE3__MASKFULL                (IMG_UINT64_C(0x000000000000FFFF))
#define RGX_CR_JONES_FIX__ROGUE3__DISABLE_SHIFT           (0U)
#define RGX_CR_JONES_FIX__ROGUE3__DISABLE_CLRMSK          (0xFFFF0000U)


/*
    Register RGX_CR_FBCDC_STATUS
*/
#define RGX_CR_FBCDC_STATUS                               (0xF600U)
#define RGX_CR_FBCDC_STATUS_MASKFULL                      (IMG_UINT64_C(0x000000000F0F0F0F))
#define RGX_CR_FBCDC_STATUS_STATE_CHECK_FAIL_SHIFT        (24U)
#define RGX_CR_FBCDC_STATUS_STATE_CHECK_FAIL_CLRMSK       (0xF0FFFFFFU)
#define RGX_CR_FBCDC_STATUS_UFOD_DECODER_ERROR_SHIFT      (16U)
#define RGX_CR_FBCDC_STATUS_UFOD_DECODER_ERROR_CLRMSK     (0xFFF0FFFFU)
#define RGX_CR_FBCDC_STATUS_HEADER_CHECK_FAIL_SHIFT       (8U)
#define RGX_CR_FBCDC_STATUS_HEADER_CHECK_FAIL_CLRMSK      (0xFFFFF0FFU)
#define RGX_CR_FBCDC_STATUS_TILE_LENGTH_CHECK_FAIL_SHIFT  (0U)
#define RGX_CR_FBCDC_STATUS_TILE_LENGTH_CHECK_FAIL_CLRMSK (0xFFFFFFF0U)


/*
    Register RGX_CR_CONTEXT_MAPPING4
*/
#define RGX_CR_CONTEXT_MAPPING4                           (0xF210U)
#define RGX_CR_CONTEXT_MAPPING4_MASKFULL                  (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
#define RGX_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT        (40U)
#define RGX_CR_CONTEXT_MAPPING4_3D_MMU_STACK_CLRMSK       (IMG_UINT64_C(0xFFFF00FFFFFFFFFF))
#define RGX_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT          (32U)
#define RGX_CR_CONTEXT_MAPPING4_3D_UFSTACK_CLRMSK         (IMG_UINT64_C(0xFFFFFF00FFFFFFFF))
#define RGX_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT           (24U)
#define RGX_CR_CONTEXT_MAPPING4_3D_FSTACK_CLRMSK          (IMG_UINT64_C(0xFFFFFFFF00FFFFFF))
#define RGX_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT        (16U)
#define RGX_CR_CONTEXT_MAPPING4_TA_MMU_STACK_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFFF00FFFF))
#define RGX_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT          (8U)
#define RGX_CR_CONTEXT_MAPPING4_TA_UFSTACK_CLRMSK         (IMG_UINT64_C(0xFFFFFFFFFFFF00FF))
#define RGX_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT           (0U)
#define RGX_CR_CONTEXT_MAPPING4_TA_FSTACK_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_CR_FBCDC_IDLE
*/
#define RGX_CR_FBCDC_IDLE                                 (0xF218U)
#define RGX_CR_FBCDC_IDLE_MASKFULL                        (IMG_UINT64_C(0x0000000000003FFF))
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF3_SHIFT                (13U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF3_CLRMSK               (0xFFFFDFFFU)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF3_EN                   (0x00002000U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF3_SHIFT               (12U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF3_CLRMSK              (0xFFFFEFFFU)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF3_EN                  (0x00001000U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF3_SHIFT                (11U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF3_CLRMSK               (0xFFFFF7FFU)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF3_EN                   (0x00000800U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF2_SHIFT                (10U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF2_CLRMSK               (0xFFFFFBFFU)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF2_EN                   (0x00000400U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF2_SHIFT               (9U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF2_CLRMSK              (0xFFFFFDFFU)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF2_EN                  (0x00000200U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF2_SHIFT                (8U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF2_CLRMSK               (0xFFFFFEFFU)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF2_EN                   (0x00000100U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF1_SHIFT                (7U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF1_CLRMSK               (0xFFFFFF7FU)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF1_EN                   (0x00000080U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF1_SHIFT               (6U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF1_CLRMSK              (0xFFFFFFBFU)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF1_EN                  (0x00000040U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF1_SHIFT                (5U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF1_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF1_EN                   (0x00000020U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF0_SHIFT                (4U)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF0_CLRMSK               (0xFFFFFFEFU)
#define RGX_CR_FBCDC_IDLE_FBC_MEMIF0_EN                   (0x00000010U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF0_SHIFT               (3U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF0_CLRMSK              (0xFFFFFFF7U)
#define RGX_CR_FBCDC_IDLE_FBDC_MEMIF0_EN                  (0x00000008U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF0_SHIFT                (2U)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF0_CLRMSK               (0xFFFFFFFBU)
#define RGX_CR_FBCDC_IDLE_FBM_MEMIF0_EN                   (0x00000004U)
#define RGX_CR_FBCDC_IDLE_FBHC_SHIFT                      (1U)
#define RGX_CR_FBCDC_IDLE_FBHC_CLRMSK                     (0xFFFFFFFDU)
#define RGX_CR_FBCDC_IDLE_FBHC_EN                         (0x00000002U)
#define RGX_CR_FBCDC_IDLE_FBSC_SHIFT                      (0U)
#define RGX_CR_FBCDC_IDLE_FBSC_CLRMSK                     (0xFFFFFFFEU)
#define RGX_CR_FBCDC_IDLE_FBSC_EN                         (0x00000001U)


/*
    Register RGX_CR_MERCER_SOFT_RESET
*/
#define RGX_CR_MERCER_SOFT_RESET                          (0x0630U)
#define RGX_CR_MERCER_SOFT_RESET_MASKFULL                 (IMG_UINT64_C(0x7FFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER2_SHIFT      (62U)
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER2_CLRMSK     (IMG_UINT64_C(0xBFFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER2_EN         (IMG_UINT64_C(0x4000000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER1_SHIFT      (61U)
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER1_CLRMSK     (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER1_EN         (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER0_SHIFT      (60U)
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER0_CLRMSK     (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU20_MERCER0_EN         (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER2_SHIFT      (59U)
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER2_CLRMSK     (IMG_UINT64_C(0xF7FFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER2_EN         (IMG_UINT64_C(0x0800000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER1_SHIFT      (58U)
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER1_CLRMSK     (IMG_UINT64_C(0xFBFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER1_EN         (IMG_UINT64_C(0x0400000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER0_SHIFT      (57U)
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER0_CLRMSK     (IMG_UINT64_C(0xFDFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU19_MERCER0_EN         (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER2_SHIFT      (56U)
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER2_CLRMSK     (IMG_UINT64_C(0xFEFFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER2_EN         (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER1_SHIFT      (55U)
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER1_CLRMSK     (IMG_UINT64_C(0xFF7FFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER1_EN         (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER0_SHIFT      (54U)
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFBFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU18_MERCER0_EN         (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER2_SHIFT      (53U)
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFDFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER2_EN         (IMG_UINT64_C(0x0020000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER1_SHIFT      (52U)
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFEFFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER1_EN         (IMG_UINT64_C(0x0010000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER0_SHIFT      (51U)
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFF7FFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU17_MERCER0_EN         (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER2_SHIFT      (50U)
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFBFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER2_EN         (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER1_SHIFT      (49U)
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFDFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER1_EN         (IMG_UINT64_C(0x0002000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER0_SHIFT      (48U)
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFEFFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU16_MERCER0_EN         (IMG_UINT64_C(0x0001000000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER2_SHIFT      (47U)
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFF7FFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER2_EN         (IMG_UINT64_C(0x0000800000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER1_SHIFT      (46U)
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFBFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER1_EN         (IMG_UINT64_C(0x0000400000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER0_SHIFT      (45U)
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFDFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU15_MERCER0_EN         (IMG_UINT64_C(0x0000200000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER2_SHIFT      (44U)
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFFEFFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER2_EN         (IMG_UINT64_C(0x0000100000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER1_SHIFT      (43U)
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFF7FFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER1_EN         (IMG_UINT64_C(0x0000080000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER0_SHIFT      (42U)
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFFBFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU14_MERCER0_EN         (IMG_UINT64_C(0x0000040000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER2_SHIFT      (41U)
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFFFDFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER2_EN         (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER1_SHIFT      (40U)
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER1_EN         (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER0_SHIFT      (39U)
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFFF7FFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU13_MERCER0_EN         (IMG_UINT64_C(0x0000008000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER2_SHIFT      (38U)
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFFFFBFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER2_EN         (IMG_UINT64_C(0x0000004000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER1_SHIFT      (37U)
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFFFDFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER1_EN         (IMG_UINT64_C(0x0000002000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER0_SHIFT      (36U)
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFFFEFFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU12_MERCER0_EN         (IMG_UINT64_C(0x0000001000000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER2_SHIFT      (35U)
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFFFFF7FFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER2_EN         (IMG_UINT64_C(0x0000000800000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER1_SHIFT      (34U)
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFFFFBFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER1_EN         (IMG_UINT64_C(0x0000000400000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER0_SHIFT      (33U)
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFFFFDFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU11_MERCER0_EN         (IMG_UINT64_C(0x0000000200000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER2_SHIFT      (32U)
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER2_CLRMSK     (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER2_EN         (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER1_SHIFT      (31U)
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER1_CLRMSK     (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER1_EN         (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER0_SHIFT      (30U)
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER0_CLRMSK     (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU10_MERCER0_EN         (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER2_SHIFT       (29U)
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER2_EN          (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER1_SHIFT       (28U)
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER1_EN          (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER0_SHIFT       (27U)
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU9_MERCER0_EN          (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER2_SHIFT       (26U)
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER2_EN          (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER1_SHIFT       (25U)
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER1_EN          (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER0_SHIFT       (24U)
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU8_MERCER0_EN          (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER2_SHIFT       (23U)
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER2_EN          (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER1_SHIFT       (22U)
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER1_EN          (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER0_SHIFT       (21U)
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU7_MERCER0_EN          (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER2_SHIFT       (20U)
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER2_EN          (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER1_SHIFT       (19U)
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER1_EN          (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER0_SHIFT       (18U)
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU6_MERCER0_EN          (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER2_SHIFT       (17U)
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER2_EN          (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER1_SHIFT       (16U)
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER1_EN          (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER0_SHIFT       (15U)
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU5_MERCER0_EN          (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER2_SHIFT       (14U)
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER2_EN          (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER1_SHIFT       (13U)
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER1_EN          (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER0_SHIFT       (12U)
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU4_MERCER0_EN          (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER2_SHIFT       (11U)
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER2_EN          (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER1_SHIFT       (10U)
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER1_EN          (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER0_SHIFT       (9U)
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU3_MERCER0_EN          (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER2_SHIFT       (8U)
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER2_EN          (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER1_SHIFT       (7U)
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER1_EN          (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER0_SHIFT       (6U)
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_MERCER_SOFT_RESET_SPU2_MERCER0_EN          (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER2_SHIFT       (5U)
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER2_EN          (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER1_SHIFT       (4U)
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER1_EN          (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER0_SHIFT       (3U)
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_MERCER_SOFT_RESET_SPU1_MERCER0_EN          (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER2_SHIFT       (2U)
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER2_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER2_EN          (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER1_SHIFT       (1U)
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER1_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER1_EN          (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER0_SHIFT       (0U)
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER0_CLRMSK      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_MERCER_SOFT_RESET_SPU0_MERCER0_EN          (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_TEXAS_SOFT_RESET
*/
#define RGX_CR_TEXAS_SOFT_RESET                           (0x0640U)
#define RGX_CR_TEXAS_SOFT_RESET_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_TEXAS_SOFT_RESET_SPU31_SHIFT               (31U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU31_CLRMSK              (0x7FFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU31_EN                  (0x80000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU30_SHIFT               (30U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU30_CLRMSK              (0xBFFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU30_EN                  (0x40000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU29_SHIFT               (29U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU29_CLRMSK              (0xDFFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU29_EN                  (0x20000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU28_SHIFT               (28U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU28_CLRMSK              (0xEFFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU28_EN                  (0x10000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU27_SHIFT               (27U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU27_CLRMSK              (0xF7FFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU27_EN                  (0x08000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU26_SHIFT               (26U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU26_CLRMSK              (0xFBFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU26_EN                  (0x04000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU25_SHIFT               (25U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU25_CLRMSK              (0xFDFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU25_EN                  (0x02000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU24_SHIFT               (24U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU24_CLRMSK              (0xFEFFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU24_EN                  (0x01000000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU23_SHIFT               (23U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU23_CLRMSK              (0xFF7FFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU23_EN                  (0x00800000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU22_SHIFT               (22U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU22_CLRMSK              (0xFFBFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU22_EN                  (0x00400000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU21_SHIFT               (21U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU21_CLRMSK              (0xFFDFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU21_EN                  (0x00200000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU20_SHIFT               (20U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU20_CLRMSK              (0xFFEFFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU20_EN                  (0x00100000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU19_SHIFT               (19U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU19_CLRMSK              (0xFFF7FFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU19_EN                  (0x00080000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU18_SHIFT               (18U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU18_CLRMSK              (0xFFFBFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU18_EN                  (0x00040000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU17_SHIFT               (17U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU17_CLRMSK              (0xFFFDFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU17_EN                  (0x00020000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU16_SHIFT               (16U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU16_CLRMSK              (0xFFFEFFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU16_EN                  (0x00010000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU15_SHIFT               (15U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU15_CLRMSK              (0xFFFF7FFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU15_EN                  (0x00008000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU14_SHIFT               (14U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU14_CLRMSK              (0xFFFFBFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU14_EN                  (0x00004000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU13_SHIFT               (13U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU13_CLRMSK              (0xFFFFDFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU13_EN                  (0x00002000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU12_SHIFT               (12U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU12_CLRMSK              (0xFFFFEFFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU12_EN                  (0x00001000U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU11_SHIFT               (11U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU11_CLRMSK              (0xFFFFF7FFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU11_EN                  (0x00000800U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU10_SHIFT               (10U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU10_CLRMSK              (0xFFFFFBFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU10_EN                  (0x00000400U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU9_SHIFT                (9U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU9_CLRMSK               (0xFFFFFDFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU9_EN                   (0x00000200U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU8_SHIFT                (8U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU8_CLRMSK               (0xFFFFFEFFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU8_EN                   (0x00000100U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU7_SHIFT                (7U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU7_CLRMSK               (0xFFFFFF7FU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU7_EN                   (0x00000080U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU6_SHIFT                (6U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU6_CLRMSK               (0xFFFFFFBFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU6_EN                   (0x00000040U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU5_SHIFT                (5U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU5_CLRMSK               (0xFFFFFFDFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU5_EN                   (0x00000020U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU4_SHIFT                (4U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU4_CLRMSK               (0xFFFFFFEFU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU4_EN                   (0x00000010U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU3_SHIFT                (3U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU3_CLRMSK               (0xFFFFFFF7U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU3_EN                   (0x00000008U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU2_SHIFT                (2U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU2_CLRMSK               (0xFFFFFFFBU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU2_EN                   (0x00000004U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU1_SHIFT                (1U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU1_CLRMSK               (0xFFFFFFFDU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU1_EN                   (0x00000002U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU0_SHIFT                (0U)
#define RGX_CR_TEXAS_SOFT_RESET_SPU0_CLRMSK               (0xFFFFFFFEU)
#define RGX_CR_TEXAS_SOFT_RESET_SPU0_EN                   (0x00000001U)


/*
    Register RGX_CR_SWIFT_SOFT_RESET
*/
#define RGX_CR_SWIFT_SOFT_RESET                           (0x0650U)
#define RGX_CR_SWIFT_SOFT_RESET__ALRIF_GT0__MASKFULL      (IMG_UINT64_C(0x7FFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT2_SHIFT        (62U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT2_CLRMSK       (IMG_UINT64_C(0xBFFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT2_EN           (IMG_UINT64_C(0x4000000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT1_SHIFT        (61U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT1_CLRMSK       (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT1_EN           (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT0_SHIFT        (60U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT0_CLRMSK       (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SWIFT0_EN           (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT2_SHIFT        (59U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT2_CLRMSK       (IMG_UINT64_C(0xF7FFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT2_EN           (IMG_UINT64_C(0x0800000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT1_SHIFT        (58U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFBFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT1_EN           (IMG_UINT64_C(0x0400000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT0_SHIFT        (57U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFDFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SWIFT0_EN           (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT2_SHIFT        (56U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFEFFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT2_EN           (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT1_SHIFT        (55U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFF7FFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT1_EN           (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT0_SHIFT        (54U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFBFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SWIFT0_EN           (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT2_SHIFT        (53U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFDFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT2_EN           (IMG_UINT64_C(0x0020000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT1_SHIFT        (52U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFEFFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT1_EN           (IMG_UINT64_C(0x0010000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT0_SHIFT        (51U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFF7FFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SWIFT0_EN           (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT2_SHIFT        (50U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFBFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT2_EN           (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT1_SHIFT        (49U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFDFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT1_EN           (IMG_UINT64_C(0x0002000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT0_SHIFT        (48U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFEFFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SWIFT0_EN           (IMG_UINT64_C(0x0001000000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT2_SHIFT        (47U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFF7FFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT2_EN           (IMG_UINT64_C(0x0000800000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT1_SHIFT        (46U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFBFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT1_EN           (IMG_UINT64_C(0x0000400000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT0_SHIFT        (45U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFDFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SWIFT0_EN           (IMG_UINT64_C(0x0000200000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT2_SHIFT        (44U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFFEFFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT2_EN           (IMG_UINT64_C(0x0000100000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT1_SHIFT        (43U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFF7FFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT1_EN           (IMG_UINT64_C(0x0000080000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT0_SHIFT        (42U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFFBFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SWIFT0_EN           (IMG_UINT64_C(0x0000040000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT2_SHIFT        (41U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFFFDFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT2_EN           (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT1_SHIFT        (40U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT1_EN           (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT0_SHIFT        (39U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFFF7FFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SWIFT0_EN           (IMG_UINT64_C(0x0000008000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT2_SHIFT        (38U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFFFFBFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT2_EN           (IMG_UINT64_C(0x0000004000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT1_SHIFT        (37U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFFFDFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT1_EN           (IMG_UINT64_C(0x0000002000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT0_SHIFT        (36U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFFFEFFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SWIFT0_EN           (IMG_UINT64_C(0x0000001000000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT2_SHIFT        (35U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFFFFF7FFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT2_EN           (IMG_UINT64_C(0x0000000800000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT1_SHIFT        (34U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFFFFBFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT1_EN           (IMG_UINT64_C(0x0000000400000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT0_SHIFT        (33U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFFFFDFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SWIFT0_EN           (IMG_UINT64_C(0x0000000200000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT2_SHIFT        (32U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT2_CLRMSK       (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT2_EN           (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU31_SHIFT               (31U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU31_CLRMSK              (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU31_EN                  (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT1_SHIFT        (31U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT1_CLRMSK       (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT1_EN           (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU30_SHIFT               (30U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU30_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU30_EN                  (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT0_SHIFT        (30U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT0_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SWIFT0_EN           (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU29_SHIFT               (29U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU29_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU29_EN                  (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT2_SHIFT         (29U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT2_EN            (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU28_SHIFT               (28U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU28_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU28_EN                  (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT1_SHIFT         (28U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT1_EN            (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU27_SHIFT               (27U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU27_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU27_EN                  (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT0_SHIFT         (27U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SWIFT0_EN            (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU26_SHIFT               (26U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU26_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU26_EN                  (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT2_SHIFT         (26U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT2_EN            (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU25_SHIFT               (25U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU25_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU25_EN                  (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT1_SHIFT         (25U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT1_EN            (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU24_SHIFT               (24U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU24_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU24_EN                  (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT0_SHIFT         (24U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SWIFT0_EN            (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU23_SHIFT               (23U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU23_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU23_EN                  (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT2_SHIFT         (23U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT2_EN            (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU22_SHIFT               (22U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU22_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU22_EN                  (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT1_SHIFT         (22U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT1_EN            (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU21_SHIFT               (21U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU21_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU21_EN                  (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT0_SHIFT         (21U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SWIFT0_EN            (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_SHIFT               (20U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU20_EN                  (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT2_SHIFT         (20U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT2_EN            (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_SHIFT               (19U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU19_EN                  (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT1_SHIFT         (19U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT1_EN            (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_SHIFT               (18U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU18_EN                  (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT0_SHIFT         (18U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SWIFT0_EN            (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_SHIFT               (17U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU17_EN                  (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT2_SHIFT         (17U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT2_EN            (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_SHIFT               (16U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU16_EN                  (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT1_SHIFT         (16U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT1_EN            (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_SHIFT               (15U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU15_EN                  (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT0_SHIFT         (15U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SWIFT0_EN            (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_SHIFT               (14U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU14_EN                  (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT2_SHIFT         (14U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT2_EN            (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_SHIFT               (13U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU13_EN                  (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT1_SHIFT         (13U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT1_EN            (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_SHIFT               (12U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU12_EN                  (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT0_SHIFT         (12U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SWIFT0_EN            (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_SHIFT               (11U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU11_EN                  (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT2_SHIFT         (11U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT2_EN            (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_SHIFT               (10U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU10_EN                  (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT1_SHIFT         (10U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT1_EN            (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_SHIFT                (9U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU9_EN                   (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT0_SHIFT         (9U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SWIFT0_EN            (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_SHIFT                (8U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU8_EN                   (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT2_SHIFT         (8U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT2_EN            (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_SHIFT                (7U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_SWIFT_SOFT_RESET_SPU7_EN                   (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT1_SHIFT         (7U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT1_EN            (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_SHIFT                (6U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU6_EN                   (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT0_SHIFT         (6U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SWIFT0_EN            (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_SHIFT                (5U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU5_EN                   (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT2_SHIFT         (5U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT2_EN            (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_SHIFT                (4U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU4_EN                   (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT1_SHIFT         (4U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT1_EN            (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_SHIFT                (3U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_SWIFT_SOFT_RESET_SPU3_EN                   (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT0_SHIFT         (3U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SWIFT0_EN            (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_SHIFT                (2U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_SWIFT_SOFT_RESET_SPU2_EN                   (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT2_SHIFT         (2U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT2_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT2_EN            (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_SHIFT                (1U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_SWIFT_SOFT_RESET_SPU1_EN                   (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT1_SHIFT         (1U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT1_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT1_EN            (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SHIFT                (0U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_EN                   (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT0_SHIFT         (0U)
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT0_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_SWIFT_SOFT_RESET_SPU0_SWIFT0_EN            (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_RAC_SOFT_RESET
*/
#define RGX_CR_RAC_SOFT_RESET                             (0x0660U)
#define RGX_CR_RAC_SOFT_RESET_MASKFULL                    (IMG_UINT64_C(0x7FFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC2_SHIFT            (62U)
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC2_CLRMSK           (IMG_UINT64_C(0xBFFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC2_EN               (IMG_UINT64_C(0x4000000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC1_SHIFT            (61U)
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC1_CLRMSK           (IMG_UINT64_C(0xDFFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC1_EN               (IMG_UINT64_C(0x2000000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC0_SHIFT            (60U)
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC0_CLRMSK           (IMG_UINT64_C(0xEFFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU20_RAC0_EN               (IMG_UINT64_C(0x1000000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC2_SHIFT            (59U)
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC2_CLRMSK           (IMG_UINT64_C(0xF7FFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC2_EN               (IMG_UINT64_C(0x0800000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC1_SHIFT            (58U)
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC1_CLRMSK           (IMG_UINT64_C(0xFBFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC1_EN               (IMG_UINT64_C(0x0400000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC0_SHIFT            (57U)
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC0_CLRMSK           (IMG_UINT64_C(0xFDFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU19_RAC0_EN               (IMG_UINT64_C(0x0200000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC2_SHIFT            (56U)
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC2_CLRMSK           (IMG_UINT64_C(0xFEFFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC2_EN               (IMG_UINT64_C(0x0100000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC1_SHIFT            (55U)
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC1_CLRMSK           (IMG_UINT64_C(0xFF7FFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC1_EN               (IMG_UINT64_C(0x0080000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC0_SHIFT            (54U)
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC0_CLRMSK           (IMG_UINT64_C(0xFFBFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU18_RAC0_EN               (IMG_UINT64_C(0x0040000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC2_SHIFT            (53U)
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC2_CLRMSK           (IMG_UINT64_C(0xFFDFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC2_EN               (IMG_UINT64_C(0x0020000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC1_SHIFT            (52U)
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC1_CLRMSK           (IMG_UINT64_C(0xFFEFFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC1_EN               (IMG_UINT64_C(0x0010000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC0_SHIFT            (51U)
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC0_CLRMSK           (IMG_UINT64_C(0xFFF7FFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU17_RAC0_EN               (IMG_UINT64_C(0x0008000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC2_SHIFT            (50U)
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFBFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC2_EN               (IMG_UINT64_C(0x0004000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC1_SHIFT            (49U)
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFDFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC1_EN               (IMG_UINT64_C(0x0002000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC0_SHIFT            (48U)
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFEFFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU16_RAC0_EN               (IMG_UINT64_C(0x0001000000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC2_SHIFT            (47U)
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFF7FFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC2_EN               (IMG_UINT64_C(0x0000800000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC1_SHIFT            (46U)
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFBFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC1_EN               (IMG_UINT64_C(0x0000400000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC0_SHIFT            (45U)
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFDFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU15_RAC0_EN               (IMG_UINT64_C(0x0000200000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC2_SHIFT            (44U)
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFFEFFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC2_EN               (IMG_UINT64_C(0x0000100000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC1_SHIFT            (43U)
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFF7FFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC1_EN               (IMG_UINT64_C(0x0000080000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC0_SHIFT            (42U)
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFFBFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU14_RAC0_EN               (IMG_UINT64_C(0x0000040000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC2_SHIFT            (41U)
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFFFDFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC2_EN               (IMG_UINT64_C(0x0000020000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC1_SHIFT            (40U)
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFFEFFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC1_EN               (IMG_UINT64_C(0x0000010000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC0_SHIFT            (39U)
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFFF7FFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU13_RAC0_EN               (IMG_UINT64_C(0x0000008000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC2_SHIFT            (38U)
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFFFFBFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC2_EN               (IMG_UINT64_C(0x0000004000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC1_SHIFT            (37U)
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFFFDFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC1_EN               (IMG_UINT64_C(0x0000002000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC0_SHIFT            (36U)
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFFFEFFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU12_RAC0_EN               (IMG_UINT64_C(0x0000001000000000))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC2_SHIFT            (35U)
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFFFFF7FFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC2_EN               (IMG_UINT64_C(0x0000000800000000))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC1_SHIFT            (34U)
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFFFFBFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC1_EN               (IMG_UINT64_C(0x0000000400000000))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC0_SHIFT            (33U)
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFFFFDFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU11_RAC0_EN               (IMG_UINT64_C(0x0000000200000000))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC2_SHIFT            (32U)
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC2_CLRMSK           (IMG_UINT64_C(0xFFFFFFFEFFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC2_EN               (IMG_UINT64_C(0x0000000100000000))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC1_SHIFT            (31U)
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC1_CLRMSK           (IMG_UINT64_C(0xFFFFFFFF7FFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC1_EN               (IMG_UINT64_C(0x0000000080000000))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC0_SHIFT            (30U)
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC0_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFBFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU10_RAC0_EN               (IMG_UINT64_C(0x0000000040000000))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC2_SHIFT             (29U)
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC2_EN                (IMG_UINT64_C(0x0000000020000000))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC1_SHIFT             (28U)
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC1_EN                (IMG_UINT64_C(0x0000000010000000))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC0_SHIFT             (27U)
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFF7FFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU9_RAC0_EN                (IMG_UINT64_C(0x0000000008000000))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC2_SHIFT             (26U)
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFBFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC2_EN                (IMG_UINT64_C(0x0000000004000000))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC1_SHIFT             (25U)
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC1_EN                (IMG_UINT64_C(0x0000000002000000))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC0_SHIFT             (24U)
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU8_RAC0_EN                (IMG_UINT64_C(0x0000000001000000))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC2_SHIFT             (23U)
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFF7FFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC2_EN                (IMG_UINT64_C(0x0000000000800000))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC1_SHIFT             (22U)
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFBFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC1_EN                (IMG_UINT64_C(0x0000000000400000))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC0_SHIFT             (21U)
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFDFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU7_RAC0_EN                (IMG_UINT64_C(0x0000000000200000))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC2_SHIFT             (20U)
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFEFFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC2_EN                (IMG_UINT64_C(0x0000000000100000))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC1_SHIFT             (19U)
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFF7FFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC1_EN                (IMG_UINT64_C(0x0000000000080000))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC0_SHIFT             (18U)
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU6_RAC0_EN                (IMG_UINT64_C(0x0000000000040000))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC2_SHIFT             (17U)
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC2_EN                (IMG_UINT64_C(0x0000000000020000))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC1_SHIFT             (16U)
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC1_EN                (IMG_UINT64_C(0x0000000000010000))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC0_SHIFT             (15U)
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFF7FFF))
#define RGX_CR_RAC_SOFT_RESET_SPU5_RAC0_EN                (IMG_UINT64_C(0x0000000000008000))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC2_SHIFT             (14U)
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC2_EN                (IMG_UINT64_C(0x0000000000004000))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC1_SHIFT             (13U)
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC1_EN                (IMG_UINT64_C(0x0000000000002000))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC0_SHIFT             (12U)
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_CR_RAC_SOFT_RESET_SPU4_RAC0_EN                (IMG_UINT64_C(0x0000000000001000))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC2_SHIFT             (11U)
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFF7FF))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC2_EN                (IMG_UINT64_C(0x0000000000000800))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC1_SHIFT             (10U)
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC1_EN                (IMG_UINT64_C(0x0000000000000400))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC0_SHIFT             (9U)
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_CR_RAC_SOFT_RESET_SPU3_RAC0_EN                (IMG_UINT64_C(0x0000000000000200))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC2_SHIFT             (8U)
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC2_EN                (IMG_UINT64_C(0x0000000000000100))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC1_SHIFT             (7U)
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFF7F))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC1_EN                (IMG_UINT64_C(0x0000000000000080))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC0_SHIFT             (6U)
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFBF))
#define RGX_CR_RAC_SOFT_RESET_SPU2_RAC0_EN                (IMG_UINT64_C(0x0000000000000040))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC2_SHIFT             (5U)
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC2_EN                (IMG_UINT64_C(0x0000000000000020))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC1_SHIFT             (4U)
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC1_EN                (IMG_UINT64_C(0x0000000000000010))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC0_SHIFT             (3U)
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFF7))
#define RGX_CR_RAC_SOFT_RESET_SPU1_RAC0_EN                (IMG_UINT64_C(0x0000000000000008))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC2_SHIFT             (2U)
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC2_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC2_EN                (IMG_UINT64_C(0x0000000000000004))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC1_SHIFT             (1U)
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC1_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC1_EN                (IMG_UINT64_C(0x0000000000000002))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC0_SHIFT             (0U)
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC0_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_CR_RAC_SOFT_RESET_SPU0_RAC0_EN                (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_CR_FWCORE_WDT_RESET
*/
#define RGX_CR_FWCORE_WDT_RESET                           (0x4500U)
#define RGX_CR_FWCORE_WDT_RESET_MASKFULL                  (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_FWCORE_WDT_RESET_EN_SHIFT                  (0U)
#define RGX_CR_FWCORE_WDT_RESET_EN_CLRMSK                 (0xFFFFFFFEU)
#define RGX_CR_FWCORE_WDT_RESET_EN_EN                     (0x00000001U)


/*
    Register RGX_CR_FWCORE_WDT_CTRL
*/
#define RGX_CR_FWCORE_WDT_CTRL                            (0x4508U)
#define RGX_CR_FWCORE_WDT_CTRL_MASKFULL                   (IMG_UINT64_C(0x00000000FFFF1F01))
#define RGX_CR_FWCORE_WDT_CTRL_PROT_SHIFT                 (16U)
#define RGX_CR_FWCORE_WDT_CTRL_PROT_CLRMSK                (0x0000FFFFU)
#define RGX_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT            (8U)
#define RGX_CR_FWCORE_WDT_CTRL_THRESHOLD_CLRMSK           (0xFFFFE0FFU)
#define RGX_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT               (0U)
#define RGX_CR_FWCORE_WDT_CTRL_ENABLE_CLRMSK              (0xFFFFFFFEU)
#define RGX_CR_FWCORE_WDT_CTRL_ENABLE_EN                  (0x00000001U)


/*
    Register RGX_CR_FWCORE_WDT_COUNT
*/
#define RGX_CR_FWCORE_WDT_COUNT                           (0x4510U)
#define RGX_CR_FWCORE_WDT_COUNT_MASKFULL                  (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_FWCORE_WDT_COUNT_VALUE_SHIFT               (0U)
#define RGX_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK              (0x00000000U)


#endif /* RGX_CR_DEFS_KM_H */
/*****************************************************************************
 End of file (rgx_cr_defs_km.h)
*****************************************************************************/
