/*************************************************************************/ /*!
@Title          Hardware definition file rgxtbdefs_km.h
@Brief          The file contains auto-generated hardware definitions without
                BVNC-specific compile time conditionals.
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@License        Dual MIT/GPLv2

The contents of this file are subject to the MIT license as set out below.

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.

If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.

This License is also included in this distribution in the file called
"MIT-COPYING".

EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/

/*               ****   Autogenerated C -- do not edit    ****               */

/*
 */


#ifndef RGXTBDEFS_KM_H
#define RGXTBDEFS_KM_H

#include "img_types.h"
#include "img_defs.h"


#define RGXTBDEFS_KM_REVISION 1

/*
    Register RGX_TB_SOFT_RESET
*/
#define RGX_TB_SOFT_RESET                                 (0x0000U)
#define RGX_TB_SOFT_RESET_MASKFULL                        (IMG_UINT64_C(0x00000000FFFF0107))
#define RGX_TB_SOFT_RESET_SPU_SHIFT                       (16U)
#define RGX_TB_SOFT_RESET_SPU_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFF0000FFFF))
#define RGX_TB_SOFT_RESET_JONES_SHIFT                     (8U)
#define RGX_TB_SOFT_RESET_JONES_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_TB_SOFT_RESET_JONES_EN                        (IMG_UINT64_C(0x0000000000000100))
#define RGX_TB_SOFT_RESET_SYS_SHIFT                       (2U)
#define RGX_TB_SOFT_RESET_SYS_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_TB_SOFT_RESET_SYS_EN                          (IMG_UINT64_C(0x0000000000000004))
#define RGX_TB_SOFT_RESET_MEM_SHIFT                       (1U)
#define RGX_TB_SOFT_RESET_MEM_CLRMSK                      (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_TB_SOFT_RESET_MEM_EN                          (IMG_UINT64_C(0x0000000000000002))
#define RGX_TB_SOFT_RESET_CORE_SHIFT                      (0U)
#define RGX_TB_SOFT_RESET_CORE_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_SOFT_RESET_CORE_EN                         (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_PCI_MASTER
*/
#define RGX_TB_PCI_MASTER                                 (0x0008U)
#define RGX_TB_PCI_MASTER_MASKFULL                        (IMG_UINT64_C(0x0000000000000001))
#define RGX_TB_PCI_MASTER_MODE_SHIFT                      (0U)
#define RGX_TB_PCI_MASTER_MODE_CLRMSK                     (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_PCI_MASTER_MODE_EN                         (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_MEM_ARBITER
*/
#define RGX_TB_MEM_ARBITER                                (0x0088U)
#define RGX_TB_MEM_ARBITER_MASKFULL                       (IMG_UINT64_C(0x0000000000010F11))
#define RGX_TB_MEM_ARBITER_LIMIT_BW_SHIFT                 (16U)
#define RGX_TB_MEM_ARBITER_LIMIT_BW_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_TB_MEM_ARBITER_LIMIT_BW_EN                    (IMG_UINT64_C(0x0000000000010000))
#define RGX_TB_MEM_ARBITER_PRI_SKEW_SHIFT                 (8U)
#define RGX_TB_MEM_ARBITER_PRI_SKEW_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFF0FF))
#define RGX_TB_MEM_ARBITER_PRI_RNW_SHIFT                  (4U)
#define RGX_TB_MEM_ARBITER_PRI_RNW_CLRMSK                 (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_TB_MEM_ARBITER_PRI_RNW_EN                     (IMG_UINT64_C(0x0000000000000010))
#define RGX_TB_MEM_ARBITER_ENABLE_SHIFT                   (0U)
#define RGX_TB_MEM_ARBITER_ENABLE_CLRMSK                  (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_MEM_ARBITER_ENABLE_EN                      (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_QOS_RD_LATENCY
*/
#define RGX_TB_QOS_RD_LATENCY                             (0x0090U)
#define RGX_TB_QOS_RD_LATENCY_MASKFULL                    (IMG_UINT64_C(0xFFFF3FFF3FFF3FFF))
#define RGX_TB_QOS_RD_LATENCY_DIST_SHIFT                  (62U)
#define RGX_TB_QOS_RD_LATENCY_DIST_CLRMSK                 (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_TB_QOS_RD_LATENCY_MAX_15_SHIFT                (48U)
#define RGX_TB_QOS_RD_LATENCY_MAX_15_CLRMSK               (IMG_UINT64_C(0xC000FFFFFFFFFFFF))
#define RGX_TB_QOS_RD_LATENCY_MIN_15_SHIFT                (32U)
#define RGX_TB_QOS_RD_LATENCY_MIN_15_CLRMSK               (IMG_UINT64_C(0xFFFFC000FFFFFFFF))
#define RGX_TB_QOS_RD_LATENCY_MAX_0_SHIFT                 (16U)
#define RGX_TB_QOS_RD_LATENCY_MAX_0_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFC000FFFF))
#define RGX_TB_QOS_RD_LATENCY_MIN_0_SHIFT                 (0U)
#define RGX_TB_QOS_RD_LATENCY_MIN_0_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFC000))


/*
    Register RGX_TB_QOS_WR_LATENCY
*/
#define RGX_TB_QOS_WR_LATENCY                             (0x0098U)
#define RGX_TB_QOS_WR_LATENCY_MASKFULL                    (IMG_UINT64_C(0xFFFF3FFF3FFF3FFF))
#define RGX_TB_QOS_WR_LATENCY_DIST_SHIFT                  (62U)
#define RGX_TB_QOS_WR_LATENCY_DIST_CLRMSK                 (IMG_UINT64_C(0x3FFFFFFFFFFFFFFF))
#define RGX_TB_QOS_WR_LATENCY_MAX_15_SHIFT                (48U)
#define RGX_TB_QOS_WR_LATENCY_MAX_15_CLRMSK               (IMG_UINT64_C(0xC000FFFFFFFFFFFF))
#define RGX_TB_QOS_WR_LATENCY_MIN_15_SHIFT                (32U)
#define RGX_TB_QOS_WR_LATENCY_MIN_15_CLRMSK               (IMG_UINT64_C(0xFFFFC000FFFFFFFF))
#define RGX_TB_QOS_WR_LATENCY_MAX_0_SHIFT                 (16U)
#define RGX_TB_QOS_WR_LATENCY_MAX_0_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFC000FFFF))
#define RGX_TB_QOS_WR_LATENCY_MIN_0_SHIFT                 (0U)
#define RGX_TB_QOS_WR_LATENCY_MIN_0_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFC000))


/*
    Register RGX_TB_MAX_ID_OUTSTANDING
*/
#define RGX_TB_MAX_ID_OUTSTANDING                         (0x00B0U)
#define RGX_TB_MAX_ID_OUTSTANDING_MASKFULL                (IMG_UINT64_C(0x000003FF03FF03FF))
#define RGX_TB_MAX_ID_OUTSTANDING_RD_WR_SHIFT             (32U)
#define RGX_TB_MAX_ID_OUTSTANDING_RD_WR_CLRMSK            (IMG_UINT64_C(0xFFFFFC00FFFFFFFF))
#define RGX_TB_MAX_ID_OUTSTANDING_WRITE_SHIFT             (16U)
#define RGX_TB_MAX_ID_OUTSTANDING_WRITE_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFC00FFFF))
#define RGX_TB_MAX_ID_OUTSTANDING_READ_SHIFT              (0U)
#define RGX_TB_MAX_ID_OUTSTANDING_READ_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFFFFFC00))


/*
    Register RGX_TB_COHERENT_MEM_REGION
*/
#define RGX_TB_COHERENT_MEM_REGION                        (0x00C0U)
#define RGX_TB_COHERENT_MEM_REGION_MASKFULL               (IMG_UINT64_C(0x000000FFFFFFF000))
#define RGX_TB_COHERENT_MEM_REGION_START_ADDR_SHIFT       (12U)
#define RGX_TB_COHERENT_MEM_REGION_START_ADDR_CLRMSK      (IMG_UINT64_C(0xFFFFFF0000000FFF))


/*
    Register RGX_TB_LMA_MEM_REGION
*/
#define RGX_TB_LMA_MEM_REGION                             (0x00C8U)
#define RGX_TB_LMA_MEM_REGION_MASKFULL                    (IMG_UINT64_C(0x000000FFFFFFFFFF))
#define RGX_TB_LMA_MEM_REGION_SIZE_SHIFT                  (0U)
#define RGX_TB_LMA_MEM_REGION_SIZE_CLRMSK                 (IMG_UINT64_C(0xFFFFFF0000000000))


/*
    Register RGX_TB_UMA_MEM_REGION
*/
#define RGX_TB_UMA_MEM_REGION                             (0x00D0U)
#define RGX_TB_UMA_MEM_REGION_MASKFULL                    (IMG_UINT64_C(0x000000FFFFFFF000))
#define RGX_TB_UMA_MEM_REGION_START_ADDR_SHIFT            (12U)
#define RGX_TB_UMA_MEM_REGION_START_ADDR_CLRMSK           (IMG_UINT64_C(0xFFFFFF0000000FFF))


/*
    Register RGX_TB_SYSTEM_STATUS
*/
#define RGX_TB_SYSTEM_STATUS                              (0x00E0U)
#define RGX_TB_SYSTEM_STATUS_MASKFULL                     (IMG_UINT64_C(0xFFFFFFFF33F700FF))
#define RGX_TB_SYSTEM_STATUS_SPU_ISON_SHIFT               (48U)
#define RGX_TB_SYSTEM_STATUS_SPU_ISON_CLRMSK              (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
#define RGX_TB_SYSTEM_STATUS_SPU_POWER_SHIFT              (32U)
#define RGX_TB_SYSTEM_STATUS_SPU_POWER_CLRMSK             (IMG_UINT64_C(0xFFFF0000FFFFFFFF))
#define RGX_TB_SYSTEM_STATUS_JONES_ISON_SHIFT             (29U)
#define RGX_TB_SYSTEM_STATUS_JONES_ISON_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFDFFFFFFF))
#define RGX_TB_SYSTEM_STATUS_JONES_ISON_EN                (IMG_UINT64_C(0x0000000020000000))
#define RGX_TB_SYSTEM_STATUS_JONES_POWER_SHIFT            (28U)
#define RGX_TB_SYSTEM_STATUS_JONES_POWER_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFEFFFFFFF))
#define RGX_TB_SYSTEM_STATUS_JONES_POWER_EN               (IMG_UINT64_C(0x0000000010000000))
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_SHIFT (25U)
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFDFFFFFF))
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_EN    (IMG_UINT64_C(0x0000000002000000))
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_SHIFT (24U)
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_CLRMSK (IMG_UINT64_C(0xFFFFFFFFFEFFFFFF))
#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_EN (IMG_UINT64_C(0x0000000001000000))
#define RGX_TB_SYSTEM_STATUS_GPU_STATE_SHIFT              (20U)
#define RGX_TB_SYSTEM_STATUS_GPU_STATE_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFF0FFFFF))
#define RGX_TB_SYSTEM_STATUS_SYSTEM_IRQ_SHIFT             (18U)
#define RGX_TB_SYSTEM_STATUS_SYSTEM_IRQ_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFBFFFF))
#define RGX_TB_SYSTEM_STATUS_SYSTEM_IRQ_EN                (IMG_UINT64_C(0x0000000000040000))
#define RGX_TB_SYSTEM_STATUS_TRIGGER_SHIFT                (17U)
#define RGX_TB_SYSTEM_STATUS_TRIGGER_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFDFFFF))
#define RGX_TB_SYSTEM_STATUS_TRIGGER_EN                   (IMG_UINT64_C(0x0000000000020000))
#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_SHIFT               (16U)
#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFEFFFF))
#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_EN                  (IMG_UINT64_C(0x0000000000010000))
#define RGX_TB_SYSTEM_STATUS_IRQ_SHIFT                    (0U)
#define RGX_TB_SYSTEM_STATUS_IRQ_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFF00))


/*
    Register RGX_TB_SYSTEM_CONFIG
*/
#define RGX_TB_SYSTEM_CONFIG                              (0x00F0U)
#define RGX_TB_SYSTEM_CONFIG_MASKFULL                     (IMG_UINT64_C(0x0000000007007737))
#define RGX_TB_SYSTEM_CONFIG_SOC_AXI_FEATURE_SHIFT        (24U)
#define RGX_TB_SYSTEM_CONFIG_SOC_AXI_FEATURE_CLRMSK       (IMG_UINT64_C(0xFFFFFFFFF8FFFFFF))
#define RGX_TB_SYSTEM_CONFIG_ICE_CABLEIF256_SHIFT         (14U)
#define RGX_TB_SYSTEM_CONFIG_ICE_CABLEIF256_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFBFFF))
#define RGX_TB_SYSTEM_CONFIG_ICE_CABLEIF256_EN            (IMG_UINT64_C(0x0000000000004000))
#define RGX_TB_SYSTEM_CONFIG_VELOCE_TBX_SHIFT             (13U)
#define RGX_TB_SYSTEM_CONFIG_VELOCE_TBX_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFDFFF))
#define RGX_TB_SYSTEM_CONFIG_VELOCE_TBX_EN                (IMG_UINT64_C(0x0000000000002000))
#define RGX_TB_SYSTEM_CONFIG_VELOCE_ICE_SHIFT             (12U)
#define RGX_TB_SYSTEM_CONFIG_VELOCE_ICE_CLRMSK            (IMG_UINT64_C(0xFFFFFFFFFFFFEFFF))
#define RGX_TB_SYSTEM_CONFIG_VELOCE_ICE_EN                (IMG_UINT64_C(0x0000000000001000))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_AVIP_SHIFT           (10U)
#define RGX_TB_SYSTEM_CONFIG_CADENCE_AVIP_CLRMSK          (IMG_UINT64_C(0xFFFFFFFFFFFFFBFF))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_AVIP_EN              (IMG_UINT64_C(0x0000000000000400))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_TBA_SHIFT            (9U)
#define RGX_TB_SYSTEM_CONFIG_CADENCE_TBA_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFFDFF))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_TBA_EN               (IMG_UINT64_C(0x0000000000000200))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_ICE_SHIFT            (8U)
#define RGX_TB_SYSTEM_CONFIG_CADENCE_ICE_CLRMSK           (IMG_UINT64_C(0xFFFFFFFFFFFFFEFF))
#define RGX_TB_SYSTEM_CONFIG_CADENCE_ICE_EN               (IMG_UINT64_C(0x0000000000000100))
#define RGX_TB_SYSTEM_CONFIG_EMU_UMA_SHIFT                (5U)
#define RGX_TB_SYSTEM_CONFIG_EMU_UMA_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFDF))
#define RGX_TB_SYSTEM_CONFIG_EMU_UMA_EN                   (IMG_UINT64_C(0x0000000000000020))
#define RGX_TB_SYSTEM_CONFIG_EMU_BUILD_SHIFT              (4U)
#define RGX_TB_SYSTEM_CONFIG_EMU_BUILD_CLRMSK             (IMG_UINT64_C(0xFFFFFFFFFFFFFFEF))
#define RGX_TB_SYSTEM_CONFIG_EMU_BUILD_EN                 (IMG_UINT64_C(0x0000000000000010))
#define RGX_TB_SYSTEM_CONFIG_NS_NOC_SHIFT                 (2U)
#define RGX_TB_SYSTEM_CONFIG_NS_NOC_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFFFFB))
#define RGX_TB_SYSTEM_CONFIG_NS_NOC_EN                    (IMG_UINT64_C(0x0000000000000004))
#define RGX_TB_SYSTEM_CONFIG_IMG_NOC_SHIFT                (1U)
#define RGX_TB_SYSTEM_CONFIG_IMG_NOC_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFFFFFFD))
#define RGX_TB_SYSTEM_CONFIG_IMG_NOC_EN                   (IMG_UINT64_C(0x0000000000000002))
#define RGX_TB_SYSTEM_CONFIG_TB_NONCOHERENT_SHIFT         (0U)
#define RGX_TB_SYSTEM_CONFIG_TB_NONCOHERENT_CLRMSK        (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_SYSTEM_CONFIG_TB_NONCOHERENT_EN            (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_RDATA_CORRUPT_ENABLE
*/
#define RGX_TB_RDATA_CORRUPT_ENABLE                       (0x1560U)
#define RGX_TB_RDATA_CORRUPT_ENABLE_MASKFULL              (IMG_UINT64_C(0x0000000000000001))
#define RGX_TB_RDATA_CORRUPT_ENABLE_ENABLE_SHIFT          (0U)
#define RGX_TB_RDATA_CORRUPT_ENABLE_ENABLE_CLRMSK         (0xFFFFFFFEU)
#define RGX_TB_RDATA_CORRUPT_ENABLE_ENABLE_EN             (0x00000001U)


/*
    Register RGX_TB_RDATA_CORRUPT_MASK
*/
#define RGX_TB_RDATA_CORRUPT_MASK                         (0x1568U)
#define RGX_TB_RDATA_CORRUPT_MASK_MASKFULL                (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_TB_RDATA_CORRUPT_MASK_MMU_SHIFT               (31U)
#define RGX_TB_RDATA_CORRUPT_MASK_MMU_CLRMSK              (0x7FFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_MMU_EN                  (0x80000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_UPS_SHIFT               (30U)
#define RGX_TB_RDATA_CORRUPT_MASK_UPS_CLRMSK              (0xBFFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_UPS_EN                  (0x40000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_FBM_SHIFT               (29U)
#define RGX_TB_RDATA_CORRUPT_MASK_FBM_CLRMSK              (0xDFFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_FBM_EN                  (0x20000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_TUL_SHIFT               (28U)
#define RGX_TB_RDATA_CORRUPT_MASK_TUL_CLRMSK              (0xEFFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_TUL_EN                  (0x10000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_SHR_SHIFT               (27U)
#define RGX_TB_RDATA_CORRUPT_MASK_SHR_CLRMSK              (0xF7FFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_SHR_EN                  (0x08000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_FBA_SHIFT               (26U)
#define RGX_TB_RDATA_CORRUPT_MASK_FBA_CLRMSK              (0xFBFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_FBA_EN                  (0x04000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_VDM_SHIFT               (25U)
#define RGX_TB_RDATA_CORRUPT_MASK_VDM_CLRMSK              (0xFDFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_VDM_EN                  (0x02000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_USC_L2_SHIFT            (24U)
#define RGX_TB_RDATA_CORRUPT_MASK_USC_L2_CLRMSK           (0xFEFFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_USC_L2_EN               (0x01000000U)
#define RGX_TB_RDATA_CORRUPT_MASK_PDS_SHIFT               (23U)
#define RGX_TB_RDATA_CORRUPT_MASK_PDS_CLRMSK              (0xFF7FFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_PDS_EN                  (0x00800000U)
#define RGX_TB_RDATA_CORRUPT_MASK_PDSRW_SHIFT             (22U)
#define RGX_TB_RDATA_CORRUPT_MASK_PDSRW_CLRMSK            (0xFFBFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_PDSRW_EN                (0x00400000U)
#define RGX_TB_RDATA_CORRUPT_MASK_TPF_SHIFT               (21U)
#define RGX_TB_RDATA_CORRUPT_MASK_TPF_CLRMSK              (0xFFDFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_TPF_EN                  (0x00200000U)
#define RGX_TB_RDATA_CORRUPT_MASK_SHF_SHIFT               (20U)
#define RGX_TB_RDATA_CORRUPT_MASK_SHF_CLRMSK              (0xFFEFFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_SHF_EN                  (0x00100000U)
#define RGX_TB_RDATA_CORRUPT_MASK_AMC_SHIFT               (19U)
#define RGX_TB_RDATA_CORRUPT_MASK_AMC_CLRMSK              (0xFFF7FFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_AMC_EN                  (0x00080000U)
#define RGX_TB_RDATA_CORRUPT_MASK_RAC_SHIFT               (18U)
#define RGX_TB_RDATA_CORRUPT_MASK_RAC_CLRMSK              (0xFFFBFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_RAC_EN                  (0x00040000U)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_RTC_SHIFT           (17U)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_RTC_CLRMSK          (0xFFFDFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_RTC_EN              (0x00020000U)
#define RGX_TB_RDATA_CORRUPT_MASK_ISP_SHIFT               (16U)
#define RGX_TB_RDATA_CORRUPT_MASK_ISP_CLRMSK              (0xFFFEFFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_ISP_EN                  (0x00010000U)
#define RGX_TB_RDATA_CORRUPT_MASK_PPP_SHIFT               (15U)
#define RGX_TB_RDATA_CORRUPT_MASK_PPP_CLRMSK              (0xFFFF7FFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_PPP_EN                  (0x00008000U)
#define RGX_TB_RDATA_CORRUPT_MASK_IPF_SHIFT               (14U)
#define RGX_TB_RDATA_CORRUPT_MASK_IPF_CLRMSK              (0xFFFFBFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_IPF_EN                  (0x00004000U)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_SHIFT               (13U)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_CLRMSK              (0xFFFFDFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_VCE_EN                  (0x00002000U)
#define RGX_TB_RDATA_CORRUPT_MASK_PBE_SHIFT               (12U)
#define RGX_TB_RDATA_CORRUPT_MASK_PBE_CLRMSK              (0xFFFFEFFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_PBE_EN                  (0x00001000U)
#define RGX_TB_RDATA_CORRUPT_MASK_TCU_SHIFT               (11U)
#define RGX_TB_RDATA_CORRUPT_MASK_TCU_CLRMSK              (0xFFFFF7FFU)
#define RGX_TB_RDATA_CORRUPT_MASK_TCU_EN                  (0x00000800U)
#define RGX_TB_RDATA_CORRUPT_MASK_MCU_SHIFT               (10U)
#define RGX_TB_RDATA_CORRUPT_MASK_MCU_CLRMSK              (0xFFFFFBFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_MCU_EN                  (0x00000400U)
#define RGX_TB_RDATA_CORRUPT_MASK_RPM_SHIFT               (9U)
#define RGX_TB_RDATA_CORRUPT_MASK_RPM_CLRMSK              (0xFFFFFDFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_RPM_EN                  (0x00000200U)
#define RGX_TB_RDATA_CORRUPT_MASK_RTU_SHIFT               (8U)
#define RGX_TB_RDATA_CORRUPT_MASK_RTU_CLRMSK              (0xFFFFFEFFU)
#define RGX_TB_RDATA_CORRUPT_MASK_RTU_EN                  (0x00000100U)
#define RGX_TB_RDATA_CORRUPT_MASK_TILING_SHIFT            (7U)
#define RGX_TB_RDATA_CORRUPT_MASK_TILING_CLRMSK           (0xFFFFFF7FU)
#define RGX_TB_RDATA_CORRUPT_MASK_TILING_EN               (0x00000080U)
#define RGX_TB_RDATA_CORRUPT_MASK_META_DMA_SHIFT          (6U)
#define RGX_TB_RDATA_CORRUPT_MASK_META_DMA_CLRMSK         (0xFFFFFFBFU)
#define RGX_TB_RDATA_CORRUPT_MASK_META_DMA_EN             (0x00000040U)
#define RGX_TB_RDATA_CORRUPT_MASK_META_SHIFT              (5U)
#define RGX_TB_RDATA_CORRUPT_MASK_META_CLRMSK             (0xFFFFFFDFU)
#define RGX_TB_RDATA_CORRUPT_MASK_META_EN                 (0x00000020U)
#define RGX_TB_RDATA_CORRUPT_MASK_CDM_SHIFT               (4U)
#define RGX_TB_RDATA_CORRUPT_MASK_CDM_CLRMSK              (0xFFFFFFEFU)
#define RGX_TB_RDATA_CORRUPT_MASK_CDM_EN                  (0x00000010U)
#define RGX_TB_RDATA_CORRUPT_MASK_PM_SHIFT                (3U)
#define RGX_TB_RDATA_CORRUPT_MASK_PM_CLRMSK               (0xFFFFFFF7U)
#define RGX_TB_RDATA_CORRUPT_MASK_PM_EN                   (0x00000008U)
#define RGX_TB_RDATA_CORRUPT_MASK_TDM_SHIFT               (2U)
#define RGX_TB_RDATA_CORRUPT_MASK_TDM_CLRMSK              (0xFFFFFFFBU)
#define RGX_TB_RDATA_CORRUPT_MASK_TDM_EN                  (0x00000004U)
#define RGX_TB_RDATA_CORRUPT_MASK_DCE_SHIFT               (1U)
#define RGX_TB_RDATA_CORRUPT_MASK_DCE_CLRMSK              (0xFFFFFFFDU)
#define RGX_TB_RDATA_CORRUPT_MASK_DCE_EN                  (0x00000002U)
#define RGX_TB_RDATA_CORRUPT_MASK_IPP_SHIFT               (0U)
#define RGX_TB_RDATA_CORRUPT_MASK_IPP_CLRMSK              (0xFFFFFFFEU)
#define RGX_TB_RDATA_CORRUPT_MASK_IPP_EN                  (0x00000001U)


/*
    Register RGX_TB_RDATA_CORRUPT_FREQ
*/
#define RGX_TB_RDATA_CORRUPT_FREQ                         (0x1570U)
#define RGX_TB_RDATA_CORRUPT_FREQ_MASKFULL                (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_TB_RDATA_CORRUPT_FREQ_FREQ_SHIFT              (0U)
#define RGX_TB_RDATA_CORRUPT_FREQ_FREQ_CLRMSK             (0x00000000U)


/*
    Register RGX_TB_TRUSTED_DEVICE
*/
#define RGX_TB_TRUSTED_DEVICE                             (0x2000U)
#define RGX_TB_TRUSTED_DEVICE_MASKFULL                    (IMG_UINT64_C(0x000000000000001F))
#define RGX_TB_TRUSTED_DEVICE_ALLOW_SECURE_READS_SHIFT    (4U)
#define RGX_TB_TRUSTED_DEVICE_ALLOW_SECURE_READS_CLRMSK   (0xFFFFFFEFU)
#define RGX_TB_TRUSTED_DEVICE_ALLOW_SECURE_READS_EN       (0x00000010U)
#define RGX_TB_TRUSTED_DEVICE_HWCONFIG_SHIFT              (2U)
#define RGX_TB_TRUSTED_DEVICE_HWCONFIG_CLRMSK             (0xFFFFFFF3U)
#define RGX_TB_TRUSTED_DEVICE_OSID_DISABLE_SHIFT          (1U)
#define RGX_TB_TRUSTED_DEVICE_OSID_DISABLE_CLRMSK         (0xFFFFFFFDU)
#define RGX_TB_TRUSTED_DEVICE_OSID_DISABLE_EN             (0x00000002U)
#define RGX_TB_TRUSTED_DEVICE_ENABLE_SHIFT                (0U)
#define RGX_TB_TRUSTED_DEVICE_ENABLE_CLRMSK               (0xFFFFFFFEU)
#define RGX_TB_TRUSTED_DEVICE_ENABLE_EN                   (0x00000001U)


/*
    Register RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR
*/
#define RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR                 (0x2010U)
#define RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR_MASKFULL        (IMG_UINT64_C(0x0000000000000001))
#define RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR_PULSE_SHIFT     (0U)
#define RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR_PULSE_CLRMSK    (0xFFFFFFFEU)
#define RGX_TB_TRUSTED_DEVICE_FAULT_CLEAR_PULSE_EN        (0x00000001U)


/*
    Register group: RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS, with 8 repeats
*/
#define RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS_REPEATCOUNT  (8U)
/*
    Register RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS0
*/
#define RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS0             (0x2058U)
#define RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS0_MASKFULL    (IMG_UINT64_C(0x000000FFFFFFFFFF))
#define RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS0_ADDR_SHIFT  (0U)
#define RGX_TB_TRUSTED_DEVICE_REGION0_MAX_OS0_ADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000000))


/*
    Register group: RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS, with 8 repeats
*/
#define RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS_REPEATCOUNT  (8U)
/*
    Register RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS0
*/
#define RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS0             (0x20D8U)
#define RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS0_MASKFULL    (IMG_UINT64_C(0x000000FFFFFFFFFF))
#define RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS0_ADDR_SHIFT  (0U)
#define RGX_TB_TRUSTED_DEVICE_REGION1_MAX_OS0_ADDR_CLRMSK (IMG_UINT64_C(0xFFFFFF0000000000))


/*
    Register RGX_TB_BW_LIMITER
*/
#define RGX_TB_BW_LIMITER                                 (0x2118U)
#define RGX_TB_BW_LIMITER_MASKFULL                        (IMG_UINT64_C(0x00000000007707FF))
#define RGX_TB_BW_LIMITER_DROPN_EXT_SHIFT                 (20U)
#define RGX_TB_BW_LIMITER_DROPN_EXT_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFF8FFFFF))
#define RGX_TB_BW_LIMITER_PERIOD_EXT_SHIFT                (16U)
#define RGX_TB_BW_LIMITER_PERIOD_EXT_CLRMSK               (IMG_UINT64_C(0xFFFFFFFFFFF8FFFF))
#define RGX_TB_BW_LIMITER_DROPN_SHIFT                     (6U)
#define RGX_TB_BW_LIMITER_DROPN_CLRMSK                    (IMG_UINT64_C(0xFFFFFFFFFFFFF83F))
#define RGX_TB_BW_LIMITER_PERIOD_SHIFT                    (1U)
#define RGX_TB_BW_LIMITER_PERIOD_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFFC1))
#define RGX_TB_BW_LIMITER_ENABLE_SHIFT                    (0U)
#define RGX_TB_BW_LIMITER_ENABLE_CLRMSK                   (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_BW_LIMITER_ENABLE_EN                       (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_DRAM_CROSSBAR
*/
#define RGX_TB_DRAM_CROSSBAR                              (0x2128U)
#define RGX_TB_DRAM_CROSSBAR_MASKFULL                     (IMG_UINT64_C(0x0000000000003301))
#define RGX_TB_DRAM_CROSSBAR_CHANNELS_SHIFT               (12U)
#define RGX_TB_DRAM_CROSSBAR_CHANNELS_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFCFFF))
#define RGX_TB_DRAM_CROSSBAR_SEL_MODE_SHIFT               (8U)
#define RGX_TB_DRAM_CROSSBAR_SEL_MODE_CLRMSK              (IMG_UINT64_C(0xFFFFFFFFFFFFFCFF))
#define RGX_TB_DRAM_CROSSBAR_ENABLE_SHIFT                 (0U)
#define RGX_TB_DRAM_CROSSBAR_ENABLE_CLRMSK                (IMG_UINT64_C(0xFFFFFFFFFFFFFFFE))
#define RGX_TB_DRAM_CROSSBAR_ENABLE_EN                    (IMG_UINT64_C(0x0000000000000001))


/*
    Register RGX_TB_SOC_TIMER
*/
#define RGX_TB_SOC_TIMER                                  (0x2140U)
#define RGX_TB_SOC_TIMER_MASKFULL                         (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_TB_SOC_TIMER_COUNT_SHIFT                      (0U)
#define RGX_TB_SOC_TIMER_COUNT_CLRMSK                     (IMG_UINT64_C(0x0000000000000000))


/*
    Register RGX_TB_PROGRAMABLE_CLK_DIV
*/
#define RGX_TB_PROGRAMABLE_CLK_DIV                        (0x2150U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_MASKFULL               (IMG_UINT64_C(0x0000000000000FFF))
#define RGX_TB_PROGRAMABLE_CLK_DIV_MODE_SHIFT             (11U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_MODE_CLRMSK            (0xFFFFF7FFU)
#define RGX_TB_PROGRAMABLE_CLK_DIV_MODE_EN                (0x00000800U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_PROFILE_SEL_SHIFT      (9U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_PROFILE_SEL_CLRMSK     (0xFFFFF9FFU)
#define RGX_TB_PROGRAMABLE_CLK_DIV_DIV_SHIFT              (5U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_DIV_CLRMSK             (0xFFFFFE1FU)
#define RGX_TB_PROGRAMABLE_CLK_DIV_DELAY_SHIFT            (1U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_DELAY_CLRMSK           (0xFFFFFFE1U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_EVENT_SHIFT            (0U)
#define RGX_TB_PROGRAMABLE_CLK_DIV_EVENT_CLRMSK           (0xFFFFFFFEU)
#define RGX_TB_PROGRAMABLE_CLK_DIV_EVENT_EN               (0x00000001U)


/*
    Register RGX_TB_GPIO_FREQ_CTRL
*/
#define RGX_TB_GPIO_FREQ_CTRL                             (0x2160U)
#define RGX_TB_GPIO_FREQ_CTRL_MASKFULL                    (IMG_UINT64_C(0x000000000000001F))
#define RGX_TB_GPIO_FREQ_CTRL_COUNT_SHIFT                 (1U)
#define RGX_TB_GPIO_FREQ_CTRL_COUNT_CLRMSK                (0xFFFFFFE1U)
#define RGX_TB_GPIO_FREQ_CTRL_ENABLE_SHIFT                (0U)
#define RGX_TB_GPIO_FREQ_CTRL_ENABLE_CLRMSK               (0xFFFFFFFEU)
#define RGX_TB_GPIO_FREQ_CTRL_ENABLE_EN                   (0x00000001U)


/*
    Register RGX_TB_GPIO_MODE
*/
#define RGX_TB_GPIO_MODE                                  (0x2170U)
#define RGX_TB_GPIO_MODE_MASKFULL                         (IMG_UINT64_C(0x0000000000000003))
#define RGX_TB_GPIO_MODE_PROTOCOL_SHIFT                   (0U)
#define RGX_TB_GPIO_MODE_PROTOCOL_CLRMSK                  (0xFFFFFFFCU)


#endif /* RGXTBDEFS_KM_H */
/*****************************************************************************
 End of file (rgxtbdefs_km.h)
*****************************************************************************/
