diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/alchemyboard.c linux-2.6.29/arch/mips/alchemy/common/alchemyboard.c --- linux-2.6.29/arch/mips/alchemy/common/alchemyboard.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/common/alchemyboard.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,162 @@ +/* + * sysfs entry for alchemyboards. + * Copryright (C) 2009, RMI Corporation. + * Based on "Sample kobject implementation" by greg@kroah.com + * + * Copyright (C) 2004-2007 Greg Kroah-Hartman + * Copyright (C) 2007 Novell Inc. + * + * Released under the GPL version 2 only. + * + */ +#include +#include +#include +#include +#include +#include + +static boardInfo_t this_board; + +/* + * This module creates a board directory under /sys/firmware. + * It can be used for retrieving/storing board related parameters. + */ + +/* Board Name */ +static ssize_t boardName_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + memcpy(buf,this_board.boardName,sizeof(this_board.boardName)); + return sizeof(this_board.boardName); +} + +static ssize_t boardName_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + memcpy(this_board.boardName,buf,sizeof(this_board.boardName)); + return sizeof(this_board.boardName); +} + +static struct kobj_attribute boardName_attribute = + __ATTR(boardName, 0666, boardName_show, boardName_store); + +/* Board Major Number */ +static ssize_t boardMajor_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", this_board.boardMajor); +} + +static ssize_t boardMajor_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%du", &this_board.boardMajor); + return count; +} + +static struct kobj_attribute boardMajor_attribute = + __ATTR(boardMajor, 0666, boardMajor_show, boardMajor_store); + +/* Board Minor Number */ +static ssize_t boardMinor_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", this_board.boardMinor); +} + +static ssize_t boardMinor_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%du", &this_board.boardMinor); + return count; +} + +static struct kobj_attribute boardMinor_attribute = + __ATTR(boardMinor, 0666, boardMinor_show, boardMinor_store); + +/* Ethernet MAC Address */ +static ssize_t ethmac_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + memcpy(buf,this_board.ethmac,sizeof(this_board.ethmac)); + return sizeof(this_board.ethmac); +} + +static ssize_t ethmac_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + memcpy(this_board.ethmac,buf,sizeof(this_board.ethmac)); + return sizeof(this_board.ethmac); +} + +static struct kobj_attribute ethmac_attribute = + __ATTR(ethmac, 0666, ethmac_show, ethmac_store); + +/* Wifi MAC Address */ +static ssize_t wifimac_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + memcpy(buf,this_board.wifimac,sizeof(this_board.wifimac)); + return sizeof(this_board.wifimac); +} + +static ssize_t wifimac_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + memcpy(this_board.wifimac,buf,sizeof(this_board.wifimac)); + return sizeof(this_board.wifimac); +} + +static struct kobj_attribute wifimac_attribute = + __ATTR(wifimac, 0666, wifimac_show, wifimac_store); + +/****************************************************************************************/ +static struct attribute *attrs[] = { + &boardName_attribute.attr, + &boardMajor_attribute.attr, + &boardMinor_attribute.attr, + ðmac_attribute.attr, + &wifimac_attribute.attr, + NULL, /* need to NULL terminate the list of attributes */ +}; + +static struct attribute_group attr_group = { + .attrs = attrs, +}; + +static struct kobject *board_kobj; + +static int board_sysfs_init(void) +{ + int retval; + printk("Creating sysfs entry for board\n"); + board_kobj = kobject_create_and_add("board", firmware_kobj); + if (!board_kobj) + return -ENOMEM; + + /* Create the files associated with this kobject */ + retval = sysfs_create_group(board_kobj, &attr_group); + if (retval) + kobject_put(board_kobj); + + return retval; +} + +static void board_sysfs_exit(void) +{ + kobject_put(board_kobj); +} + +boardInfo_t *get_au1xxx_board_info(void) +{ + return (&this_board); +} + +EXPORT_SYMBOL(get_au1xxx_board_info); + + +module_init(board_sysfs_init); +module_exit(board_sysfs_exit); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("P. Sadik "); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/au13xx_res.c linux-2.6.29/arch/mips/alchemy/common/au13xx_res.c --- linux-2.6.29/arch/mips/alchemy/common/au13xx_res.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/common/au13xx_res.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,132 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include +#include +#include + +/* + * USB Resources for Au13xx + */ +static struct resource au13xx_usb_ehci_resources[] = { + [0] = { + .start = USB_EHCI_BASE, + .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = DMA_32BIT_MASK; + +static struct platform_device au13xx_usb_ehci_device = { + .name = "au13xx-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au13xx_usb_ehci_resources), + .resource = au13xx_usb_ehci_resources, +}; + +static struct resource au1200_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_LCD + 8, + .end = AU1300_IRQ_LCD + 8, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; + +static struct platform_device au1200_lcd_device = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au1200_lcd_resources), + .resource = au1200_lcd_resources, +}; + +extern struct platform_device au13xx_mmc1_device; + +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; +static struct resource ide_resources[] = { + [0] = { + .start = IDE_PHYS_ADDR, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IDE_INT, + .end = IDE_INT, + .flags = IORESOURCE_IRQ + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device ide_device = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(ide_resources), + .resource = ide_resources +}; + +static struct platform_device *au13xx_platform_devices[] __initdata = { + &au13xx_usb_ehci_device, + &au1200_lcd_device, + &ide_device, + &au13xx_mmc1_device, +}; + + +static int __init au13xx_add_devices(void) +{ + return platform_add_devices(au13xx_platform_devices, + ARRAY_SIZE(au13xx_platform_devices)); +} + +arch_initcall(au13xx_add_devices); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/dbdma.c linux-2.6.29/arch/mips/alchemy/common/dbdma.c --- linux-2.6.29/arch/mips/alchemy/common/dbdma.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/dbdma.c 2009-09-03 16:58:00.000000000 -0400 @@ -38,7 +38,8 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU13XX) /* * The Descriptor Based DMA supports up to 16 channels. @@ -150,6 +151,47 @@ #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x01011004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x01012004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x01013004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU13XX */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -324,6 +366,16 @@ if ((stp->dev_flags & DEV_FLAGS_SYNC) || (dtp->dev_flags & DEV_FLAGS_SYNC)) i |= DDMA_CFG_SYNC; +#ifdef CONFIG_CPU_BIG_ENDIAN + /* + * If we're compiled for BE, then set BE flag in + * cfg reg. + */ + if (dtp->dev_flags & DEV_FLAGS_OUT) + i |= DDMA_CFG_SBE; + else + i |= DDMA_CFG_DBE; +#endif cp->ddma_cfg = i; au_sync(); @@ -595,7 +647,11 @@ return 0; /* Load up buffer address and byte count. */ - dp->dscr_source0 = virt_to_phys(buf); + if (flags & DDMA_FLAGS_PHYSADDR) + dp->dscr_source0 = (u32)buf; + else + dp->dscr_source0 = virt_to_phys(buf); + dp->dscr_cmd1 = nbytes; /* Check flags */ if (flags & DDMA_FLAGS_IE) @@ -659,7 +715,11 @@ if (flags & DDMA_FLAGS_NOIE) dp->dscr_cmd0 &= ~DSCR_CMD0_IE; - dp->dscr_dest0 = virt_to_phys(buf); + if (flags & DDMA_FLAGS_PHYSADDR) + dp->dscr_dest0 = (u32)buf; + else + dp->dscr_dest0 = virt_to_phys(buf); + dp->dscr_cmd1 = nbytes; #if 0 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", @@ -881,6 +941,8 @@ irq_nr = AU1550_DDMA_INT; #elif defined(CONFIG_SOC_AU1200) irq_nr = AU1200_DDMA_INT; +#elif defined(CONFIG_SOC_AU13XX) + irq_nr = AU1300_IRQ_DDMA + GPINT_LINUX_IRQ_OFFSET; #else #error Unknown Au1x00 SOC #endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/gpio_int.c linux-2.6.29/arch/mips/alchemy/common/gpio_int.c --- linux-2.6.29/arch/mips/alchemy/common/gpio_int.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/common/gpio_int.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,383 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include /* For functions called by do_IRQ */ +#include + +#include +#include + +struct gpio_int_regs *const gpio_int = + (struct gpio_int_regs *)(GPIO_INT_CTRLR_BASE + KSEG1); + +static struct gpio_int_cfg __initdata basic_irqs[]; + +void (*board_irq_dispatch)(int) = NULL; + +#ifdef CONFIG_SOC_AU13XX +static struct gpio_int_cfg __initdata basic_irqs[] = { + { AU1300_IRQ_DDMA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTC_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOY_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_LCD, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART3, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_SD0, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_SD1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_SD2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_USB, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_BSA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MPE, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_ITE, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_GPU, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MMU, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MPU, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_2, 0, RISING, HW_INT_0, DEV_CTRL }, + + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_2, 1, RISING, HW_INT_1, DEV_CTRL }, + + + /* KH: TODO - Move this to the board file. */ + { 5, 0, LEVEL_HIGH, HW_INT_1, GPIO_IN }, +}; + +/* + * KH: TODO - Consider moving to board specific location... + */ +static struct gpio_int_cfg __initdata basic_gpios[] = { + { 0, 1, RISING, HW_INT_0, GPIO_IN }, + /* + * LCD PWM + */ + { 29, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 30, 0, DISABLED, HW_INT_0, DEV_CTRL }, + + { 32, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 33, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 34, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 35, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 36, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 37, 0, DISABLED, HW_INT_0, DEV_CTRL }, + + /* + * AC97 (PSC1) + */ + { 45, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 50, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 51, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 52, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 53, 0, DISABLED, HW_INT_0, DEV_CTRL }, + + /* + * I2S (PSC2) + */ + { 73, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 54, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 55, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 56, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 57, 0, DISABLED, HW_INT_0, DEV_CTRL }, + + /* + * SMBUS (PSC3) + */ + { 74, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 58, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 59, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 60, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 61, 0, DISABLED, HW_INT_0, DEV_CTRL }, + + /* + * IDE for MWDMA + */ + { 10, 0, DISABLED, HW_INT_0, GPIO_IN }, + + /* + * CF + */ + { 62, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 63, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 64, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 65, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 66, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 67, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 68, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 69, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 70, 0, DISABLED, HW_INT_0, DEV_CTRL }, +}; +#endif + +int __initdata nr_basic_irqs = ARRAY_SIZE(basic_irqs); + +/* + **************************************************************************** + * Functions and delcaration for irq_chip + **************************************************************************** + */ +void gpio_int_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_pend[bank]); + au_sync(); +} + +void gpio_int_mask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); + au_sync(); +} + +void gpio_int_unmask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_mask[bank]); + au_sync(); +} + +void gpio_int_mask_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); + au_sync(); +} + +static struct irq_chip gpio_int_irq_type = { + .name = "Au GPIO/INT", + .ack = gpio_int_ack, + .mask = gpio_int_mask, + .unmask = gpio_int_unmask, + .mask_ack = gpio_int_mask_ack +}; +/*****************************************************************************/ + +void set_pin_cfg(const struct gpio_int_cfg *cfg) +{ + u32 tmp; + tmp = GPINT_PINCTL_N(cfg->pinctl); + tmp |= GPINT_INTLINE_N(cfg->intline); + tmp |= GPINT_INTCFG_N(cfg->intcfg); + tmp |= cfg->intwake ? GPINT_INTWAKE_ENABLE : 0; + au_iowrite32(tmp, &gpio_int->gp_int[cfg->number]); +} + +void set_gpio(u8 gpio, u8 value) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + + if (value == 0) + au_iowrite32(1 << bit, &gpio_int->pin_valclr[bank]); + else + au_iowrite32(1 << bit, &gpio_int->pin_val[bank]); +} + +u8 get_gpio(u8 gpio) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + u32 tmp; + + tmp = au_ioread32(&gpio_int->pin_val[bank]); + return tmp >> bit; +} + +void set_dbdma_gpio(int dbdma_channel, u8 gpio) +{ + if (dbdma_channel) { + au_clear_bits_32(GPINT_DMASEL_DMA1_N(0xff), &gpio_int->dma_sel); + au_set_bits_32(GPINT_DMASEL_DMA1_N(gpio), &gpio_int->dma_sel); + } else { + au_clear_bits_32(GPINT_DMASEL_DMA0_N(0xff), &gpio_int->dma_sel); + au_set_bits_32(GPINT_DMASEL_DMA0_N(gpio), &gpio_int->dma_sel); + } +} + +void __init arch_init_irq(void) +{ + int i; + + /* + * Initialize the basic MIPS interrupt components. + */ + mips_cpu_irq_init(); + + for (i = 0; i < GPINT_NUM_BANKS; ++i) + gpio_int->int_maskclr[i] = ~0UL; + + + for (i = 0; i < ARRAY_SIZE(basic_gpios); ++i) + set_pin_cfg(&basic_gpios[i]); + + for (i = 0; i < nr_basic_irqs; ++i) { + printk(KERN_DEBUG "Initializing IRQ %d\n", + basic_irqs[i].number); + set_pin_cfg(&basic_irqs[i]); + if (basic_irqs[i].intcfg == LEVEL_LOW) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "lowlevel"); + else if (basic_irqs[i].intcfg == LEVEL_HIGH) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "highlevel"); + else if (basic_irqs[i].intcfg == FALLING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "fallingedge"); + else if (basic_irqs[i].intcfg == RISING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "risingedge"); + else if (basic_irqs[i].intcfg == ANY_CHANGE) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "bothedge"); + else + set_irq_chip( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type); + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); + + board_init_irq(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int intr; + u32 bank; + u32 reg_msk; + u32 cause = read_c0_cause(); + unsigned int pending = read_c0_status() & cause; + /* + * C0 timer tick + */ + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { + intr = au_ioread32(&gpio_int->pri_enc); + bank = GPINT_BANK_FROM_INT(intr); + reg_msk = GPINT_BIT_FROM_INT(bank, intr); + + if (intr != 127) { + if (board_irq_dispatch) + board_irq_dispatch(intr); + + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); + } else { + printk(KERN_WARNING "ALCHEMY GPIO_INT: Spurious interrupt! cause = 0x%08x\n", cause); + spurious_interrupt(); + } + } else { + printk(KERN_WARNING "ALCHEMY GPIO_INT: Spurious interrupt! cause = 0x%08x\n", cause); + spurious_interrupt(); + } + +} + +#ifdef CONFIG_PM + +static u32 save_gpio_intn[GPINT_MAX_INTS]; +static u32 save_masks[GPINT_NUM_BANKS]; +static u32 save_dev_sels[GPINT_NUM_BANKS]; +static u32 save_dma_sel; + +void save_au1xxx_intctl(void) +{ + int i; + for (i = 0; i < GPINT_NUM_BANKS; i++) { + save_masks[i] = au_ioread32(&gpio_int->int_mask[i]); + save_dev_sels[i] = au_ioread32(&gpio_int->dev_sel[i]); + au_iowrite32(0xffffffff, &gpio_int->int_maskclr[i]); + } + + for (i = 0; i < GPINT_MAX_INTS; i++) { + save_gpio_intn[i] = au_ioread32(&gpio_int->gp_int[i]); + } + + save_dma_sel = au_ioread32(&gpio_int->dma_sel); +} + +void restore_au1xxx_intctl(void) +{ + int i; + for (i = 0; i < GPINT_NUM_BANKS; i++) { + au_iowrite32(0xffffffff, &gpio_int->int_maskclr[i]); + } + + for (i = 0; i < GPINT_MAX_INTS; i++) { + au_iowrite32(save_gpio_intn[i], &gpio_int->gp_int[i]); + } + + au_iowrite32(save_dma_sel, &gpio_int->dma_sel); + + for (i = 0; i < GPINT_NUM_BANKS; i++) { + au_iowrite32(save_dev_sels[i], &gpio_int->dev_sel[i]); + } + + for (i = 0; i < GPINT_NUM_BANKS; i++) { + au_iowrite32(save_masks[i], &gpio_int->int_mask[i]); + } +} + + +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/irq.c linux-2.6.29/arch/mips/alchemy/common/irq.c --- linux-2.6.29/arch/mips/alchemy/common/irq.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/irq.c 2009-08-21 19:14:45.000000000 -0400 @@ -328,6 +328,29 @@ au_sync(); } +static void au1x_ic0_mask_ack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_WAKECLR); + au_sync(); + au_writel(1 << bit, IC0_FALLINGCLR); + au_writel(1 << bit, IC0_RISINGCLR); + au_sync(); +} + +static void au1x_ic1_mask_ack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + au_writel(1 << bit, IC1_MASKCLR); + au_writel(1 << bit, IC1_WAKECLR); + au_sync(); + au_writel(1 << bit, IC1_FALLINGCLR); + au_writel(1 << bit, IC1_RISINGCLR); + au_sync(); +} + + static void au1x_ic0_ack(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -386,18 +409,18 @@ */ static struct irq_chip au1x_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, /* edge */ + .ack = au1x_ic0_ack, .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_mask, /* level */ + .mask_ack = au1x_ic0_mask_ack, .unmask = au1x_ic0_unmask, .set_type = au1x_ic_settype, }; static struct irq_chip au1x_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, /* edge */ + .ack = au1x_ic1_ack, .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_mask, /* level */ + .mask_ack = au1x_ic1_mask_ack, .unmask = au1x_ic1_unmask, .set_type = au1x_ic_settype, .set_wake = au1x_ic1_setwake, diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/Makefile linux-2.6.29/arch/mips/alchemy/common/Makefile --- linux-2.6.29/arch/mips/alchemy/common/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/Makefile 2009-09-16 18:47:00.000000000 -0400 @@ -5,10 +5,14 @@ # Makefile for the Alchemy Au1xx0 CPUs, generic files. # -obj-y += prom.o irq.o puts.o time.o reset.o \ +obj-y += alchemyboard.o prom.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o gpio.o + sleeper.o dma.o dbdma.o gpio.o mempool.o +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_AU_GPIO_INT_CNTLR) += gpio_int.o +obj-$(CONFIG_AU_INT_CNTLR) += irq.o + EXTRA_CFLAGS += -Werror diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/mempool.c linux-2.6.29/arch/mips/alchemy/common/mempool.c --- linux-2.6.29/arch/mips/alchemy/common/mempool.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/common/mempool.c 2009-09-16 18:47:00.000000000 -0400 @@ -0,0 +1,404 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifdef CONFIG_AU_MEMPOOL + +#include +#include +#include +#include +#include +#include + +#include +#ifdef CONFIG_MIPS_DB1300 +#include +#endif +static struct list_head pools[AU_MAX_MEMPOOLS]; +static bool pool_cacheable[AU_MAX_MEMPOOLS]; + +int au_mempool_mmap(struct file *filep, struct vm_area_struct *vma) +{ + int minor = iminor(filep->f_dentry->d_inode); + + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { + return -EINVAL; + } + + if (pool_cacheable[minor]) + { + printk(KERN_INFO "MEMPOOL: mmap returning cacheable memory\n"); + pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; + pgprot_val(vma->vm_page_prot) |= _page_cachable_default; + } + else + { + printk(KERN_INFO "MEMPOOL: mmap returning non-cacheable memory\n"); + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + pgprot_val(vma->vm_page_prot) |= _CACHE_MASK; /* CCA=7 */ + } + + vma->vm_flags |= VM_IO; + + return io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); +} + + +static void print_desc(struct au_mempool_desc *desc) +{ + printk(KERN_INFO "%15s: %2d MB @ phys 0x%08x, %s\n", desc->name, + desc->size / MB, (u32)desc->phys, + desc->in_use ? "allocated" : "free"); +} + +void au_mempool_print(int pool) +{ + struct au_mempool_desc *desc; + + list_for_each_entry(desc, &pools[pool], list) + print_desc(desc); +} + +int au_mempool_alloc(int pool, struct au_mempool_region *region) +{ + struct au_mempool_desc *first_free; + struct au_mempool_desc *new_desc; + bool found = false; + + /* + * First, adjust the size to land on the next 4K boundary + */ + printk(KERN_DEBUG "MEMPOOL: Requesting %d bytes\n", region->size); + if (region->size & ~PAGE_MASK) + { + printk(KERN_DEBUG "MEMPOOL: Requested %d bytes ", region->size); + region->size = (region->size + PAGE_SIZE ) & PAGE_MASK; + printk(KERN_DEBUG "but getting %d bytes\n", region->size); + } + + list_for_each_entry(first_free, &pools[pool], list) { + if (!first_free->in_use && first_free->size >= region->size) { + found = true; + break; + } + } + + if (!found) + return -ENOMEM; + + /* + * If we get here then we have a good pool. Split it if the allocation + * does not use all of it. + */ + if (first_free->size > region->size) { + new_desc = kmalloc(sizeof(new_desc), GFP_KERNEL); + new_desc->name = first_free->name; + new_desc->size = first_free->size - region->size; + new_desc->in_use = 0; + new_desc->phys = first_free->phys + region->size; + list_add(&new_desc->list, &first_free->list); + + first_free->size = region->size; + } + + region->name = first_free->name; + first_free->in_use = 1; + region->phys = first_free->phys; + region->desc = (void *)first_free; + + return 0; +} +EXPORT_SYMBOL(au_mempool_alloc); + +void merge(struct au_mempool_desc *desc, + struct au_mempool_desc *neighbor) +{ + neighbor->size += desc->size; + neighbor->phys = neighbor->phys < desc->phys ? + neighbor->phys : desc->phys; + list_del(&desc->list); +} + +static void au_mempool_free_desc(int pool, struct au_mempool_desc *desc) +{ + struct au_mempool_desc* neighbor; + struct list_head *tmp; + desc->in_use = 0; + + /* + * Free up the provided region's descriptor and check to see if it can + * be merged with any of its neighbors. This gives us a better chance + * of having a large enough buffer for the next allocation. + */ + tmp = desc->list.prev; + if (tmp != &pools[pool]) { + neighbor = list_entry(tmp, struct au_mempool_desc, list); + + if (!neighbor->in_use) { + merge(desc, neighbor); + kfree(desc); + desc = neighbor; + } + } + + tmp = desc->list.next; + if (tmp != &pools[pool]) { + neighbor = list_entry(tmp, struct au_mempool_desc, list); + + if (!neighbor->in_use) { + merge(desc, neighbor); + kfree(desc); + } + } +} + +void au_mempool_free(int pool, struct au_mempool_region *region) +{ + struct au_mempool_desc* desc = + (struct au_mempool_desc*)region->desc; + au_mempool_free_desc(pool, desc); + region->desc = NULL; + +} +EXPORT_SYMBOL(au_mempool_free); + +int au_mempool_ioctl(struct inode *inode, struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct au_mempool_region region; + int minor = iminor(file->f_dentry->d_inode); + + switch(cmd) { + case AU_MEMPOOL_IOCTL_PRINT: + au_mempool_print(minor); + break; + + case AU_MEMPOOL_IOCTL_ALLOC: + + if (copy_from_user(®ion, (void __user *)arg, sizeof(region))) + return -EFAULT; + + if (region.size == 0) + return -EINVAL; + + if (au_mempool_alloc(minor, ®ion) < 0) + return -ENOMEM; + + au_mempool_print(minor); + region.virt = NULL; + copy_to_user((void __user *)arg, ®ion, sizeof(region)); + + break; + + case AU_MEMPOOL_IOCTL_FREE: + if (copy_from_user(®ion, (void __user *)arg, sizeof(region))) + return -EFAULT; + + au_mempool_free(minor, ®ion); + au_mempool_print(minor); + + region.virt = NULL; + region.phys = NULL; + region.size = 0; + region.desc = NULL; + + copy_to_user((void __user *)arg, ®ion, sizeof(region)); + break; + + case AU_MEMPOOL_IOCTL_SET_CACHEABLE: + pool_cacheable[minor] = true; + break; + + case AU_MEMPOOL_IOCTL_SET_NONCACHEABLE: + pool_cacheable[minor] = false; + break; + + default: + return -EINVAL; + }; + + return 0; +} + +static int au_mempool_release(struct inode *inode, struct file *file) +{ + int pool = iminor(file->f_dentry->d_inode); + struct au_mempool_desc *desc; + struct au_mempool_desc *desc_save; + + /* + * Mempool 0 is special - it is used by the LCD and is opened multiple + * times. The other pools are used as single-open (for now) so we + * should make sure they are empty at close. + */ + if (pool > 0) { + list_for_each_entry_safe(desc, desc_save, &pools[pool], list) { + au_mempool_free_desc(pool, desc); + } + } + + return 0; +} + +struct file_operations au_mempool_fops = { + .owner = THIS_MODULE, + .mmap = au_mempool_mmap, + .ioctl = au_mempool_ioctl, + .release = au_mempool_release, +}; + +#ifdef CONFIG_MIPS_DB1300 +static int au_mempool_probe(struct platform_device *dev) +{ + struct au_mempool_desc *new_desc; + struct resource *res; + int i; + + for (i = 0; i < dev->num_resources; i++) { + INIT_LIST_HEAD(&pools[i]); + res = platform_get_resource(dev, IORESOURCE_DMA, i); + + new_desc = kmalloc(sizeof(new_desc), GFP_KERNEL); + new_desc->name = res->name, + new_desc->size = res->end - res->start + 1; + new_desc->in_use = 0; + new_desc->phys = (void *)(res->start); + list_add(&new_desc->list, &pools[i]); + } + + return 0; +} + +static struct platform_driver mempool_driver = { + .probe = au_mempool_probe, + + .driver = { + .name = "au-mempool", + .owner = THIS_MODULE, + } + +}; +#else +void initialize_pools(void) +{ + struct au_mempool_desc *new_desc; + int i; + + for (i=0; i < AU_MAX_MEMPOOLS; ++i) { + INIT_LIST_HEAD(&pools[i]); + pool_cacheable[i] = true; + } + +/* + * TODO: Declare these outside this function. + */ +#ifdef CONFIG_MIPS_DB1200 + new_desc = kmalloc(sizeof(new_desc), GFP_KERNEL); + new_desc->name = "LCD"; + new_desc->size = 64 * MB; + new_desc->in_use = 0; + new_desc->phys = (void *)(128 * MB); + list_add(&new_desc->list, &pools[0]); +#endif + +#ifdef CONFIG_MIPS_HMP10 + new_desc = kmalloc(sizeof(new_desc), GFP_KERNEL); + new_desc->name = "LCD"; + /* + * 24 MB is enough for 4 double-buffered overlays at 1024x768@32bpp, + * the max supported by P10. + */ + new_desc->size = 24 * MB; + new_desc->in_use = 0; + new_desc->phys = (void *)((256-24) * MB); + list_add(&new_desc->list, &pools[0]); + + /* + * Set aside 32 MB for MAE. The MAE driver does not use the mempool but + * this keeps us from having to use mem= on the boot line. + */ + new_desc = kmalloc(sizeof(new_desc), GFP_KERNEL); + new_desc->name = "MAE"; + new_desc->size = 32 * MB; + new_desc->in_use = 0; + new_desc->phys = (void *)((256-24-32) * MB); + list_add(&new_desc->list, &pools[1]); + +#endif + +} +#endif + +static int __init au_mempool_init(void) +{ + int retval = 0; + int i; + + struct cdev *my_cdev = cdev_alloc(); + + printk(KERN_INFO "Alchemy MEMPOOL initializing\n"); + my_cdev->ops = &au_mempool_fops; + retval = cdev_add(my_cdev, MKDEV(AU_MEMPOOL_BLOCK_MAJOR, 0), AU_MAX_MEMPOOLS); + + if (retval < 0) { + printk(KERN_ERR "Alcehmy MEMPOOL failed to register.\n"); + return retval; + } else { + printk(KERN_INFO "Alchemy MEMPOOL registered at major %d\n", + AU_MEMPOOL_BLOCK_MAJOR); + } + +#ifdef CONFIG_MIPS_DB1300 + platform_driver_register(&mempool_driver); +#else + initialize_pools(); +#endif + + printk(KERN_INFO "Available memory pools:\n"); + for (i=0; i < AU_MAX_MEMPOOLS; ++i) + au_mempool_print(i); + + return 0; +} + +static void au_mempool_exit(void) +{ + /* + * TODO: Clean up the lists before exiting. + * Though in reality it doesn't matter because this is not a loadable + * module and therefore cannot exit except at reboot/shutdown when + * memory allocations are really no longer relevant. + */ + + unregister_chrdev_region(MKDEV(AU_MEMPOOL_BLOCK_MAJOR, 0), 2); + +} + +module_init(au_mempool_init); +module_exit(au_mempool_exit); + +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/platform.c linux-2.6.29/arch/mips/alchemy/common/platform.c --- linux-2.6.29/arch/mips/alchemy/common/platform.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/platform.c 2009-09-02 10:43:51.000000000 -0400 @@ -52,6 +52,11 @@ #elif defined(CONFIG_SOC_AU1200) PORT(UART0_ADDR, AU1200_UART0_INT), PORT(UART1_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU13XX) + PORT(UART2_ADDR, AU1300_IRQ_UART2 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART0_ADDR, AU1300_IRQ_UART0 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART1_ADDR, AU1300_IRQ_UART1 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART3_ADDR, AU1300_IRQ_UART3 + GPINT_LINUX_IRQ_OFFSET), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, @@ -331,6 +336,13 @@ }; #endif + +static struct platform_device dummy_battery_device = { + .name = "dummy-battery", + .id = -1, + .num_resources = 0, +}; + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, &au1xxx_usb_ohci_device, @@ -351,6 +363,7 @@ #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, #endif + &dummy_battery_device, }; static int __init au1xxx_platform_init(void) diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/power.c linux-2.6.29/arch/mips/alchemy/common/power.c --- linux-2.6.29/arch/mips/alchemy/common/power.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/power.c 2009-08-21 19:14:45.000000000 -0400 @@ -33,10 +33,11 @@ #include #include #include +#include #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) #include #endif @@ -57,11 +58,22 @@ static unsigned int sleep_uart0_linectl; static unsigned int sleep_uart0_clkdiv; static unsigned int sleep_uart0_enable; +#ifndef CONFIG_SOC_AU13XX static unsigned int sleep_usb[2]; +#endif + +#ifndef CONFIG_SOC_AU13XX static unsigned int sleep_sys_clocks[5]; -static unsigned int sleep_sys_pinfunc; -static unsigned int sleep_static_memctlr[4][3]; +#endif + +#ifdef CONFIG_MIPS_DB1300 +#define CONSOLE_UART_ADDR (UART2_ADDR) +#else +#define CONSOLE_UART_ADDR (UART0_ADDR) +#endif +extern void save_board_regs(void); +extern void restore_board_regs(void); static void save_core_regs(void) { @@ -74,13 +86,18 @@ * standard serial driver doesn't understand our Au1xxx * unique registers. */ +#ifdef CONFIG_MIPS_DB1300 + sleep_uart0_inten = au_readl(UART2_ADDR + UART_IER); +#else sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER); - sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR); - sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); - sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); - sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); +#endif + sleep_uart0_fifoctl = au_readl(CONSOLE_UART_ADDR + UART_FCR); + sleep_uart0_linectl = au_readl(CONSOLE_UART_ADDR + UART_LCR); + sleep_uart0_clkdiv = au_readl(CONSOLE_UART_ADDR + UART_CLK); + sleep_uart0_enable = au_readl(CONSOLE_UART_ADDR + UART_MOD_CNTRL); au_sync(); +#ifndef CONFIG_SOC_AU13XX #ifndef CONFIG_SOC_AU1200 /* Shutdown USB host/device. */ sleep_usb[0] = au_readl(USB_HOST_CONFIG); @@ -105,57 +122,45 @@ sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ #endif +#endif /* Save interrupt controller state. */ save_au1xxx_intctl(); + save_board_regs(); - /* Clocks and PLLs. */ - sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); - sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); - sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); - sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); - sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); - - /* pin mux config */ - sleep_sys_pinfunc = au_readl(SYS_PINFUNC); - - /* Save the static memory controller configuration. */ - sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); - sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); - sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); - sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); - sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); - sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); - sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); - sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); - sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); - sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); - sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); - sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); +#ifndef CONFIG_SOC_AU13XX + /* Clocks and PLLs. */ + sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); + sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); + sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); + sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); + sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); +#endif -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xxx_dbdma_suspend(); #endif } static void restore_core_regs(void) { - /* restore clock configuration. Writing CPUPLL last will - * stall a bit and stabilize other clocks (unless this is - * one of those Au1000 with a write-only PLL, where we dont - * have a valid value) - */ - au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); - au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); - au_writel(sleep_sys_clocks[2], SYS_CLKSRC); - au_writel(sleep_sys_clocks[4], SYS_AUXPLL); - if (!au1xxx_cpu_has_pll_wo()) - au_writel(sleep_sys_clocks[3], SYS_CPUPLL); - au_sync(); +#ifndef CONFIG_SOC_AU13XX + /* restore clock configuration. Writing CPUPLL last will + * stall a bit and stabilize other clocks (unless this is + * one of those Au1000 with a write-only PLL, where we dont + * have a valid value) + */ + au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); + au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); + au_writel(sleep_sys_clocks[2], SYS_CLKSRC); + au_writel(sleep_sys_clocks[4], SYS_AUXPLL); + if (!au1xxx_cpu_has_pll_wo()) + au_writel(sleep_sys_clocks[3], SYS_CPUPLL); + au_sync(); - au_writel(sleep_sys_pinfunc, SYS_PINFUNC); - au_sync(); +#endif +#ifndef CONFIG_SOC_AU13XX #ifndef CONFIG_SOC_AU1200 au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); @@ -171,40 +176,32 @@ au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ au_sync(); #endif - - /* Restore the static memory controller configuration. */ - au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); - au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); - au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); - au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); - au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); - au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); - au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); - au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); - au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); - au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); - au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); - au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); +#endif /* * Enable the UART if it was enabled before sleep. * I guess I should define module control bits........ */ if (sleep_uart0_enable & 0x02) { - au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); - au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); - au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); - au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); + au_writel(0, CONSOLE_UART_ADDR + UART_MOD_CNTRL); au_sync(); + au_writel(1, CONSOLE_UART_ADDR + UART_MOD_CNTRL); au_sync(); + au_writel(3, CONSOLE_UART_ADDR + UART_MOD_CNTRL); au_sync(); + au_writel(sleep_uart0_inten, + CONSOLE_UART_ADDR + UART_IER); au_sync(); + au_writel(sleep_uart0_fifoctl, + CONSOLE_UART_ADDR + UART_FCR); au_sync(); + au_writel(sleep_uart0_linectl, + CONSOLE_UART_ADDR + UART_LCR); au_sync(); + au_writel(sleep_uart0_clkdiv, + CONSOLE_UART_ADDR + UART_CLK); au_sync(); } - restore_au1xxx_intctl(); + restore_board_regs(); -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xxx_dbdma_resume(); #endif + restore_au1xxx_intctl(); } void au_sleep(void) @@ -214,4 +211,63 @@ restore_core_regs(); } +#ifdef CONFIG_SOC_AU13XX +int vss_block_power_up(int block) +{ + AU13XX_VSS_BLOCK *vss; + + vss = (AU13XX_VSS_BLOCK*)(KSEG1 + VSS_PHYS_ADDR + + sizeof(AU13XX_VSS_BLOCK) * block); + + au_iowrite32(3, &vss->clkrst); + + au_iowrite32(0x01fffffe, &vss->gate); + + au_iowrite32(1, &vss->ftr); + au_iowrite32(3, &vss->ftr); + au_iowrite32(7, &vss->ftr); + au_iowrite32(0xf, &vss->ftr); + __asm__ volatile ("sync"); + + au_iowrite32(0x01ffffff, &vss->gate); + __asm__ volatile ("sync"); + + au_iowrite32(2, &vss->clkrst); + __asm__ volatile ("sync"); + + au_iowrite32(0x1f, &vss->ftr); + __asm__ volatile ("sync"); + + return 0; +} +EXPORT_SYMBOL(vss_block_power_up); + +void vss_block_power_down(int block) +{ + AU13XX_VSS_BLOCK *vss; + + vss = (AU13XX_VSS_BLOCK*)(KSEG1 + VSS_PHYS_ADDR + + sizeof(AU13XX_VSS_BLOCK) * block); + + au_iowrite32(0xf, &vss->ftr); + __asm__ volatile ("sync"); + + au_iowrite32(0, &vss->gate); + __asm__ volatile ("sync"); + + au_iowrite32(2, &vss->clkrst); + __asm__ volatile ("sync"); + + au_iowrite32(1, &vss->clkrst); + __asm__ volatile ("sync"); + + au_iowrite32(0xf, &vss->ftr); + __asm__ volatile ("sync"); + +} +EXPORT_SYMBOL(vss_block_power_down); + +#endif + + #endif /* CONFIG_PM */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/prom.c linux-2.6.29/arch/mips/alchemy/common/prom.c --- linux-2.6.29/arch/mips/alchemy/common/prom.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/prom.c 2009-08-21 19:14:45.000000000 -0400 @@ -141,6 +141,30 @@ } EXPORT_SYMBOL(prom_get_ethernet_addr); +int prom_get_wifi_addr(char *wifi_addr) +{ + char *ethaddr_str; + char *argptr; + + /* Check the environment variables first */ + ethaddr_str = prom_getenv("wifiaddr"); + if (!ethaddr_str) { + /* Check command line */ + argptr = prom_getcmdline(); + ethaddr_str = strstr(argptr, "wifiaddr="); + if (!ethaddr_str) + return -1; + + ethaddr_str += strlen("wifiaddr="); + } + + str2eaddr(wifi_addr, ethaddr_str); + + return 0; +} +EXPORT_SYMBOL(prom_get_wifi_addr); + + void __init prom_free_prom_memory(void) { } diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/reset.c linux-2.6.29/arch/mips/alchemy/common/reset.c --- linux-2.6.29/arch/mips/alchemy/common/reset.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/reset.c 2009-08-21 19:14:45.000000000 -0400 @@ -152,6 +152,11 @@ void au1000_halt(void) { +#ifdef CONFIG_MIPS_DB1300 + printk(KERN_NOTICE "\nPowering off.\n"); + au_iowrite16(0xc000, (volatile u16*)0xb980001c); +#endif + #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) /* Power off system */ printk(KERN_NOTICE "\n** Powering off...\n"); @@ -163,7 +168,7 @@ #ifdef CONFIG_MIPS_MIRAGE au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); #endif -#ifdef CONFIG_MIPS_DB1200 +#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_DB1300) au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); #endif #ifdef CONFIG_PM diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/sleeper.S linux-2.6.29/arch/mips/alchemy/common/sleeper.S --- linux-2.6.29/arch/mips/alchemy/common/sleeper.S 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/common/sleeper.S 2009-08-21 19:14:45.000000000 -0400 @@ -75,14 +75,19 @@ /* Put SDRAM into self refresh: Preload instructions into cache, * issue a precharge, auto/self refresh, then sleep commands to it. */ - la t0, 1f + la t0, startcached + la t1, endcached + subu t2, t1, t0 +cacheloop: .set mips3 cache 0x14, 0(t0) - cache 0x14, 32(t0) - cache 0x14, 64(t0) - cache 0x14, 96(t0) + subu t2, t2, 32 + bgez t2, cacheloop + addu t0, t0, 32 .set mips0 + +startcached: 1: lui a0, 0xb400 /* mem_xxx */ #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \ defined(CONFIG_SOC_AU1500) @@ -116,6 +121,82 @@ sync #endif +#if defined(CONFIG_SOC_AU13XX) +#define MEM_SDCONFIGA 0x0840 +#define MEM_SDCONFIGB 0x0848 +#define MEM_SDPORTCFGA 0x0868 +#define MEM_SDPORTCFGB 0x0870 +#define MEM_SDCMD0 0x08d8 +#define MEM_SDCMD1 0x08dc +#define MEM_SDPRECMD 0x08c0 +#define MEM_SDAUTOREF 0x08c8 +#define MEM_SDSTAT 0x0850 + + /* + * Disable all ports in mem_sdportcfga + */ + sw zero, MEM_SDPORTCFGA(a0) + sync + + /* + * Disable ODT + */ + li t1, 0x03010000 + sw t1, MEM_SDCMD0(a0) + sw t1, MEM_SDCMD1(a0) + sync + + /* + * Precharge all + */ + li t1, 0x23000400 + /*sw t1, MEM_SDPRECMD(a0)*/ + sw t1, MEM_SDCMD1(a0) + sw t1, MEM_SDCMD0(a0) + sync + + /* + * Auto Refresh Command + */ + sw zero, MEM_SDAUTOREF(a0) + sync + + /* + * Block access to the DDR + */ + lw t1, MEM_SDCONFIGB(a0) + li t2, (1<<7 | 0x3F) + or t1, t1, t2 + sw t1, MEM_SDCONFIGB(a0) + sync + + /* + * Issue the Self Refresh command + */ + li t1, 0x10000000 + sw t1, MEM_SDCMD1(a0) + sw t1, MEM_SDCMD0(a0) + sync + + /* + * Poll for Self Refresh status + */ +poll: + li t9, 0x03000000 + lw t2, MEM_SDSTAT(a0) + and t4, t2, t9 + bne t4, t9, poll + nop + + /* + * Disable the DDR Clocks + */ + lw t1, MEM_SDCONFIGA(a0) + li t2, ~(3<<28) + and t1, t1, t2 + sw t1, MEM_SDCONFIGA(a0) +#endif + /* put power supply and processor to sleep */ sw zero, 0x0078(t3) /* sys_slppwr */ sync @@ -129,11 +210,17 @@ nop nop nop +endcached: /* This is where we return upon wakeup. * Reload all of the registers and return. */ -3: lw k0, 0x20(sp) +3: + lui t0, 0xb9c0 + li t2, 0x17 + sh t2, 0x0000(t0) + + lw k0, 0x20(sp) mtc0 k0, CP0_STATUS lw k0, 0x1c(sp) mtc0 k0, CP0_CONTEXT @@ -167,6 +254,11 @@ lw $28, PT_R28(sp) lw $30, PT_R30(sp) lw $31, PT_R31(sp) + + lui t0, 0xb9c0 + li t2, 0xff + sh t2, 0x0000(t0) + jr ra addiu sp, PT_SIZE END(au1xxx_save_and_sleep) diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/common/system_id.c linux-2.6.29/arch/mips/alchemy/common/system_id.c --- linux-2.6.29/arch/mips/alchemy/common/system_id.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/common/system_id.c 2009-09-09 18:55:39.000000000 -0400 @@ -0,0 +1,67 @@ +/* + * Copyright 2009 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifdef CONFIG_AU_SYSTEM_ID + +#include +#include +#include +#include +#include + + +static struct class *au_system_id_class; + + +static int au_system_id_ioctl(struct inode *inode, struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + + +static const struct file_operations au_system_id_fops = { + .ioctl = au_system_id_ioctl, +}; + +static int __init au_system_id_init(void) +{ + printk("AU SYSTEM ID Driver initializing... "); + register_chrdev(0, "au_system_id", &au_system_id_fops); + au_system_id_class = class_create(THIS_MODULE, "au_system_id"); + printk("Done.\n"); + + return 0; +} + +static void au_system_id_exit(void) +{ +} + +module_init(au_system_id_init); +module_exit(au_system_id_exit); + +#endif /* CONFIG_AU_SYSTEM_ID */ + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/cascade_irq.c linux-2.6.29/arch/mips/alchemy/devboards/cascade_irq.c --- linux-2.6.29/arch/mips/alchemy/devboards/cascade_irq.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/cascade_irq.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,170 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * The following must be declared/defined in an included file: + * - volatile struct bcsr_regs (declared) + * (which much include fields int_status, intset_mask, intclr_mask, intset, + * and intclr) + * - volatile struct bcsr_regs *const bcsr (defined) + * - CASCADE_IRQ_MIN + * - CASCADE_IRQ_MAX + * - CASCADE_IRQ_TYPE_STRING + * - CASCADE_IRQ (System IRQ to which the cascade is connected) + */ + +void __init board_init_irq(void); + +irqreturn_t cascade_handler(int irq, void *dev_id) +{ + u16 int_status = au_ioread16(&db_bcsr->int_status); + int irq_in_service; + + au_iowrite16(int_status, &db_bcsr->int_status); + for ( ; int_status; int_status &= int_status - 1) { + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); + db_set_hex((u8)(irq_in_service)); + do_IRQ(irq_in_service); + } + + return IRQ_RETVAL(1); +} + +DEFINE_MUTEX(cascade_use_count_mutex); +static int cascade_use_count; + +static void cascade_mask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr_mask); +} + +static void cascade_unmask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset_mask); +} + +static void cascade_enable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset); + cascade_unmask(irq); +} + +static void cascade_disable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr); + cascade_mask(irq); +} + + +static unsigned int cascade_startup(unsigned int irq) +{ + int retval = 0; + + mutex_lock(&cascade_use_count_mutex); + ++cascade_use_count; + if (cascade_use_count == 1) + retval = request_irq(CASCADE_IRQ, + &cascade_handler, 0, "Cascade", + &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); + + cascade_enable(irq); + cascade_unmask(irq); + + return retval; +} + +static void cascade_shutdown(unsigned int irq) +{ + cascade_mask(irq); + cascade_disable(irq); + + mutex_lock(&cascade_use_count_mutex); + --cascade_use_count; + if (cascade_use_count == 0) + free_irq(CASCADE_IRQ, &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); +} + +static struct irq_chip cascade_irq_type = { + .name = CASCADE_IRQ_TYPE_STRING, + .startup = cascade_startup, + .shutdown = cascade_shutdown, + .mask = cascade_mask, + .enable = cascade_enable, + .disable = cascade_disable, + .unmask = cascade_unmask, + .mask_ack = cascade_mask +}; + +void __init board_init_irq(void) +{ + int irq; + + /* + * Some bootloaders leave interrupts enabled. Clear them out. + */ + au_iowrite16(0xffff, &db_bcsr->intclr); + au_iowrite16(0xffff, &db_bcsr->intclr_mask); + + for (irq = CASCADE_IRQ_MIN; + irq < CASCADE_IRQ_MAX; ++irq) { + printk(KERN_DEBUG "Initializing IRQ %d\n", irq); + set_irq_chip_and_handler(irq, &cascade_irq_type, + handle_level_irq); + cascade_disable(irq); + } +} + +static struct bcsr_regs save_bcsr; + +void save_board_regs(void) +{ + save_bcsr.resets = au_ioread16(&db_bcsr->resets); + save_bcsr.pcmcia = au_ioread16(&db_bcsr->pcmcia); + save_bcsr.board = au_ioread16(&db_bcsr->board); + save_bcsr.system = au_ioread16(&db_bcsr->system); + save_bcsr.intset = au_ioread16(&db_bcsr->intset); + save_bcsr.intset_mask = au_ioread16(&db_bcsr->intset_mask); +} + +void restore_board_regs(void) +{ + au_iowrite16(save_bcsr.resets, &db_bcsr->resets); + au_iowrite16(save_bcsr.pcmcia, &db_bcsr->pcmcia); + au_iowrite16(save_bcsr.board, &db_bcsr->board); + au_iowrite16(save_bcsr.system, &db_bcsr->system); + au_iowrite16(save_bcsr.intset, &db_bcsr->intset); + au_iowrite16(save_bcsr.intset_mask, &db_bcsr->intset_mask); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/db1300/board_setup.c linux-2.6.29/arch/mips/alchemy/devboards/db1300/board_setup.c --- linux-2.6.29/arch/mips/alchemy/devboards/db1300/board_setup.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/db1300/board_setup.c 2009-09-02 10:43:52.000000000 -0400 @@ -0,0 +1,290 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include /* for printk */ + +#include +#include +#include +#include + +#include +#include +#include + +#define DB1300_SYSTEM_TYPE_STRING "RMI DBAu1300 Development Board" + +struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +extern void (*board_irq_dispatch)(unsigned int); + +/* + * Called by plat_irq_dispatch to do board-specific things (i.e. display the + * interrupt on a hex output). This should *not* be used for board-specific + * interrupt handling; for that register a new interrupt handler as a device + * driver would do. + */ +void db1300_board_irq_dispatch(unsigned int irq) +{ + static u8 dots; + static int delayer; + + if (irq != AU1300_IRQ_RTCMATCH_2 && irq != AU1300_IRQ_LCD) + db_set_hex((u8)irq); + + if (irq == AU1300_IRQ_RTCMATCH_2) { + if (++delayer > HZ) { + delayer = 0; + if (++dots > 3) + dots = 0; + db_set_hex_dots(dots); + } + } + +} + +static void db1300_wait(void) +{ + db_set_led(0); + + /* using the wait instruction makes CP0 counter unusable */ + __asm__(" .set mips3 \n" + " cache 0x14, 0(%0) \n" + " cache 0x14, 32(%0) \n" + " sync \n" + " nop \n" + " wait \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " .set mips0 \n" + : : "r" (db1300_wait)); + + db_clear_led(0); +} + +static int __init db1300_wait_init(void) +{ + if (cpu_wait) { + printk("Hooking cpu_wait\n"); + cpu_wait = db1300_wait; + } + + return 0; +} + +arch_initcall(db1300_wait_init); + +void __init board_setup(void) +{ + char *argptr = NULL; + + printk(KERN_INFO DB1300_SYSTEM_TYPE_STRING "\n"); + + /* + * Add some text to the command line to point the au1200fb driver to + * the board switch. + */ + argptr = prom_getcmdline(); + strcat(argptr, " video=au1200fb:panel:bs"); + + /* + * Enable VBUS to the USB Host port + */ + au_set_bits_16(BCSR_RESETS_USB_HOST, &bcsr->resets); + + /* + * Set the IDE GPIO to the DMA SEL register + * TODO: Name these constants + */ + set_dbdma_gpio(1, 10); + + + board_irq_dispatch = db1300_board_irq_dispatch; +} + +void board_reset(void) +{ + au_clear_bits_16(BCSR_SYSTEM_SW_RST, &db_bcsr->system); +} + +const char *get_system_type(void) +{ + return DB1300_SYSTEM_TYPE_STRING; +} + +/* + * Board specific functions for the Au1200 Framebuffer driver + */ + +int board_au1200fb_panel(void) +{ + u16 switches = (au_ioread16(&db_bcsr->switches) & 0x0f00) >> 8; + + printk(KERN_INFO "Returning LCD switch setting %d\n", switches); + return switches; +} + +int board_au1200fb_backlight_on(void) +{ + au_set_bits_16(0x4, &db_bcsr->board); + return 0; +} + +int board_au1200fb_backlight_off(void) +{ + au_clear_bits_16(0x4, &db_bcsr->board); + return 0; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + if (0 == board_au1200fb_panel()) { + /* + * The Samsung 800x480 panel's enable circuit is inverted. + */ + au_clear_bits_16(0x3, &db_bcsr->board); + au_set_bits_16(0x4, &db_bcsr->board); + } else { + au_set_bits_16(0x7, &db_bcsr->board); + } + + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + if (0 == board_au1200fb_panel()) { + au_set_bits_16(0x3, &db_bcsr->board); + au_clear_bits_16(0x4, &db_bcsr->board); + } else { + au_clear_bits_16(0x7, &db_bcsr->board); + } + return 0; +} + +static struct resource db1300_mempool_resources[] = { + [0] = { + .start = MEMPOOL_LCD_START, + .end = MEMPOOL_LCD_START + MEMPOOL_LCD_SIZE - 1, + .flags = IORESOURCE_DMA, + .name = "LCD" + }, + [1] = { + .start = MEMPOOL_BSA_START, + .end = MEMPOOL_BSA_START + MEMPOOL_BSA_SIZE - 1, + .flags = IORESOURCE_DMA, + .name = "BSA" + }, + [2] = { + .start = MEMPOOL_MPE_START, + .end = MEMPOOL_MPE_START + MEMPOOL_MPE_SIZE - 1, + .flags = IORESOURCE_DMA, + .name = "MPE" + }, + [3] = { + .start = MEMPOOL_OGL_START, + .end = MEMPOOL_OGL_START + MEMPOOL_OGL_SIZE - 1, + .flags = IORESOURCE_DMA, + .name = "OGL" + }, +}; + +static struct platform_device db1300_mempool_device = { + .name = "au-mempool", + .id = 0, + .num_resources = ARRAY_SIZE(db1300_mempool_resources), + .resource = db1300_mempool_resources, +}; + +static struct resource smsc9120_resources[] = { + [0] = { + .start = 0x19000000, + .end = 0x197FFFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETHERNET_IRQ, + .end = DB1300_ETHERNET_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc9210_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device smsc9210_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc9120_resources), + .resource = smsc9120_resources, + .dev = { + .platform_data = &smsc9210_config, + }, +}; + +static struct resource smbus_resources[] = { + { + .start = PSC_SMBUS_PHYS_ADDR, + .end = PSC_SMBUS_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device smbus_device = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(smbus_resources), + .resource = smbus_resources, +}; + +static struct platform_device rtc_device = { + .name = "rtc-au1xxx", + .id = -1, + .num_resources = 0, +}; + +static struct platform_device *db1300_platform_devices[] __initdata = { + &db1300_mempool_device, + &smsc9210_device, + &smbus_device, + &rtc_device, +}; + +static int __init db1300_add_devices(void) +{ + return platform_add_devices(db1300_platform_devices, + ARRAY_SIZE(db1300_platform_devices)); +} +arch_initcall(db1300_add_devices); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/db1300/init.c linux-2.6.29/arch/mips/alchemy/devboards/db1300/init.c --- linux-2.6.29/arch/mips/alchemy/devboards/db1300/init.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/db1300/init.c 2009-09-02 10:45:31.000000000 -0400 @@ -0,0 +1,79 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * HMP10 board setup, based on PB1200 Setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include + +#include + +void __init prom_init(void) +{ + if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { + /* fw_arg0 is not a valid number, or fw_arg1 is not a valid pointer */ + prom_argc = 0; + prom_argv = prom_envp = NULL; + printk("CKSEG0 0x%08x fw_arg0 0x%lx fw_arg1 0x%lx\n", + CKSEG0,fw_arg0,fw_arg1); + } else { + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + } + + prom_init_cmdline(); + + add_memory_region(0, MEMPOOL_LCD_START, BOOT_MEM_RAM); + /* + * The two reserved regions represent memory on each of the 16-bit + * memory controller channels that will be dedicated to hardware + * peripherals. These memory regions are exposed in the mempool driver + * (see arch/mips/alchemy/common/mempool.c). Loosely, the allocations + * are as follows: + * 24 MB for the LCD Framebuffer (Supports 1024x768@32bpp, 4 overlays double buffered) + * 64 MB for MAE + * 64 MB for OpenGL + * In the future, these may be more dynamically selected as some CPU models will not have OpenGL support. + */ + add_memory_region(MEMPOOL_LCD_START, MEMPOOL_LCD_SIZE, BOOT_MEM_RESERVED); + add_memory_region(MEMPOOL_BSA_START, MEMPOOL_BSA_SIZE, BOOT_MEM_RESERVED); + add_memory_region(MEMPOOL_MPE_START, MEMPOOL_MPE_SIZE, BOOT_MEM_RESERVED); + add_memory_region(MEMPOOL_OGL_START, MEMPOOL_OGL_SIZE, BOOT_MEM_RESERVED); + add_memory_region(MEMPOOL_OGL_START + MEMPOOL_OGL_SIZE, 256*MB - (MEMPOOL_OGL_START + MEMPOOL_OGL_SIZE), BOOT_MEM_RAM); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/db1300/Makefile linux-2.6.29/arch/mips/alchemy/devboards/db1300/Makefile --- linux-2.6.29/arch/mips/alchemy/devboards/db1300/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/db1300/Makefile 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,6 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey +# + +obj-y := board_setup.o init.o mmc.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/db1300/mmc.c linux-2.6.29/arch/mips/alchemy/devboards/db1300/mmc.c --- linux-2.6.29/arch/mips/alchemy/devboards/db1300/mmc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/db1300/mmc.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,154 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +static volatile struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +static int mmc_activity; +static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; + + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev db1300mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + + +static int db1300mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1_WP) ? 1 : 0; +} + +static int db1300mmc1_card_inserted(void *mmc_host) +{ + int retval; + retval = (bcsr->sig_status & BCSR_INT_SD1_INSERT) ? 1 : 0; + return retval; +} + +struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = NULL, + .card_inserted = NULL, + .card_readonly = NULL, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &db1300mmc_led, + }, + [1] = { + .set_power = NULL, + .card_inserted = db1300mmc1_card_inserted, + .card_readonly = db1300mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &db1300mmc_led, + }, +}; + +static struct resource au13xx_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc0_device = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc0_resources), + .resource = au13xx_mmc0_resources, +}; + +static struct resource au13xx_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc1_resources), + .resource = au13xx_mmc1_resources, +}; diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/board_setup.c linux-2.6.29/arch/mips/alchemy/devboards/hmp10/board_setup.c --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/board_setup.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/board_setup.c 2009-09-16 18:47:00.000000000 -0400 @@ -0,0 +1,253 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy HMP10 board setup. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +static boardInfo_t *this_board; + +//TODO: Move this function to alchemyboard.c +const char *get_system_type(void) +{ + return this_board->boardName; +} + +void board_reset(void) +{ + au_writel(0x01, 0xb190010c); +} + +static int wifi_mac_init(char *mac_addr) +{ + unsigned char mac[6]; + unsigned char *ptr=mac_addr; + int result; + int i=0,j=0,tmp=0; + extern int smsc_prom_get_wifi_mac_addr(char *addr); + + result = smsc_prom_get_wifi_mac_addr(mac); + if (result == 0) { + for(i=0,j=0;i<6;ptr++) + { + tmp = ((j==0) ? ((mac[i]&0xF0) >> 4) : (mac[i]&0x0F)); + if (tmp>= 0 && tmp<= 9) + *ptr = tmp + 0x30; + else if (tmp>= 0xa && tmp<= 0xf) + *ptr = tmp + 0x37; + if (j==1) { + i++; + j=0; + *++ptr=':'; + } + else + j++; + } + } + return result; +} + +void __init board_setup(void) +{ +#ifdef CONFIG_FB_AU1200 + char *argptr = NULL; +#endif + int boardMinor = 0; + u32 pin_func; + argptr = prom_getcmdline(); + +#ifdef CONFIG_SERIAL_8250_CONSOLE + argptr = strstr(argptr, "console="); + if (argptr == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + this_board=get_au1xxx_board_info(); + /* + Value 0 - Don't touch. 1 - the Pin will be tristated. + All interrupt input should be tristated. + No need to worry about other pins */ + au_writel(0x10AA, SYS_TRIOUTCLR); + au_writel(0x00, SYS_PINFUNC); + au_sync(); + pin_func = 0x678A49C0; + au_writel(pin_func, SYS_PINFUNC); + au_sync(); + + + au_writel(au_readl(GPIO2_DIR) | 0x8D1B, GPIO2_DIR); + + /* + Detect Board Minor. On boards 1 - 20, the GPIO 7 is pulled Low. + On later boards, it will be logic high. + */ + boardMinor = (au_readl(SYS_PINSTATERD) & 0x80); + if(boardMinor) { + this_board->boardMinor = 1; + } + else { + this_board->boardMinor = 0; + } + +#ifdef CONFIG_FB_AU1200 + argptr = prom_getcmdline(); + if (NULL == strstr(argptr, "au1200fb:panel")) + strcat(argptr, " video=au1200fb:panel:10"); +#endif + au_sync(); + sprintf(this_board->boardName,"RMI HMP10"); + + if(wifi_mac_init(this_board->wifimac)) + sprintf(this_board->wifimac,"00:0f:a0:b0:c0:d0"); + printk("%s Board. Board Minor %d\n",this_board->boardName,this_board->boardMinor); +} + + +int board_au1200fb_panel(void) +{ + au_writel(au_readl(GPIO2_DIR) & (~0x0004), GPIO2_DIR); + au_sync(); + + if ((au_readl(GPIO2_PINSTATE)) & 0x4) { + printk("selecting 1024x768 panel\n"); + return 10; + } + else { + printk("selecting 800x600 panel\n"); + return 11; + } +} + +int board_au1200fb_backlight_on(void) +{ + au_writel(0x10001000, GPIO2_OUTPUT); + au_sync(); + return 0; +} + +int board_au1200fb_backlight_off(void) +{ + au_writel(0x10000000, GPIO2_OUTPUT); /* BL GPIO 203 */ + au_sync(); + return 0; +} + +int +board_au1200fb_panel_init(void) +{ + au_writel(0x00000004, SYS_OUTPUTSET); + au_writel(0x10001000, GPIO2_OUTPUT); + au_sync(); + return 0; +} + +int +board_au1200fb_panel_shutdown(void) +{ + au_writel(0x10000000, GPIO2_OUTPUT); /* BL GPIO 203 */ + au_writel(0x00000004, SYS_OUTPUTCLR); /* LCD PWR GPIO 2 */ + au_sync(); + return 0; +} + +void save_board_regs(void) +{ + return; +} + +void restore_board_regs(void) +{ + return; +} + +static struct platform_device hmp10_keys_device = { + .name = "hmp10-keys", + .id = -1, + .num_resources = 0, +}; + +static struct resource smsc9120_resources[] = { + [0] = { + .start = 0x19000000, + .end = 0x197FFFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1XXX_SMC9210_IRQ, + .end = AU1XXX_SMC9210_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc9210_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device smsc9210_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc9120_resources), + .resource = smsc9120_resources, + .dev = { + .platform_data = &smsc9210_config, + }, +}; + +static struct platform_device *hmp10_platform_devices[] __initdata = { + &smsc9210_device, + &hmp10_keys_device, +}; + +static int __init hmp10_add_devices(void) +{ + return platform_add_devices(hmp10_platform_devices, + ARRAY_SIZE(hmp10_platform_devices)); +} +arch_initcall(hmp10_add_devices); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/eeprom.c linux-2.6.29/arch/mips/alchemy/devboards/hmp10/eeprom.c --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/eeprom.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/eeprom.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,250 @@ +/* + TODO: Cleanup. + This code is copied from drivers/net/smsc9210 files, and is nasty. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + + + +typedef unsigned char BYTE; +typedef unsigned short WORD; + +#define true ((bool)1) +#define false ((bool)0) + +#define HIBYTE(word) ((BYTE)(((WORD)(word))>>8)) +#define LOBYTE(word) ((BYTE)(((WORD)(word))&0x00FFU)) +#define HIWORD(dWord) ((WORD)(((u32)(dWord))>>16)) +#define LOWORD(dWord) ((WORD)(((u32)(dWord))&0x0000FFFFUL)) + +#define BASE_ADDRESS (0xB9000000UL) + +static void Eeprom_EnableAccess(void); +static void Eeprom_DisableAccess(void); + +static bool Eeprom_ReadLocation(BYTE address, BYTE * data); + +int get_data_from_eeprom(int start_offset, int num_bytes, char *read_addr); + + +volatile int *CMD_Eeprom = (volatile int *)(BASE_ADDRESS+0xb0); +volatile int *DATA_Eeprom = (volatile int *)(BASE_ADDRESS+0xb4); + + +#define CMD_READ (0x00<<28) +#define CMD_EWDS (0x01<<28) +#define CMD_EWEN (0x02<<28) +#define CMD_WRITE (0x03<<28) +#define CMD_WRAL (0x4<<28) +#define CMD_ERASE (0x05<<28) +#define CMD_ERAL (0x6<<28) +#define EN 0x80000000 +#define AT93C46 1 +#if AT93C46 +#define MEM_SIZE 128 +#elif +#define MEM_SIZE 256 +#endif + + +static inline void Platform_SetRegDW(u32 lan_base, u32 offset, u32 val) +{ + au_writel(val, (lan_base + offset)); +} + +static inline u32 Platform_GetRegDW(u32 lan_base, u32 offset) +{ + return au_readl(lan_base + offset); +} + +#define Lan_GetRegDW(dwOffset) \ + Platform_GetRegDW(BASE_ADDRESS,dwOffset) + +#define Lan_SetRegDW(dwOffset,dwVal) \ + Platform_SetRegDW(BASE_ADDRESS,dwOffset,dwVal) + +#define Lan_ClrBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(BASE_ADDRESS, \ + dwOffset,Platform_GetRegDW(BASE_ADDRESS, \ + dwOffset)&(~dwBits)) + +#define Lan_SetBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(BASE_ADDRESS, \ + dwOffset,Platform_GetRegDW(BASE_ADDRESS, \ + dwOffset)|dwBits); + + +#define GPIO_CFG (0x88UL) + + +#define E2P_CMD (0xB0UL) +#define E2P_CMD_EPC_BUSY_ (0x80000000UL) // Self Clearing +#define E2P_CMD_EPC_CMD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) // R/W +#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) // R +#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) // RO +#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) // R/W + +#define E2P_DATA (0xB4UL) +#define E2P_DATA_EEPROM_DATA_ (0x000000FFUL) // R/W + +void Eeprom_EnableAccess(void) +{ + Lan_ClrBitsDW(GPIO_CFG,0x00F00000UL); + udelay(100); +} + +void Eeprom_DisableAccess(void) +{ + /*if(debug_mode&0x04UL) { + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + }*/ +} + +bool Eeprom_ReadLocation(BYTE address, BYTE * data) +{ + u32 timeout=100000; + u32 temp=0; + if((temp=Lan_GetRegDW(E2P_CMD))&E2P_CMD_EPC_BUSY_) { + printk("Eeprom_ReadLocation: Busy at start, E2P_CMD=0x%08X \n",temp); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_READ_|((u32)address))); + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + (*data)=(BYTE)(Lan_GetRegDW(E2P_DATA)); + return true; +} + +int get_data_from_eeprom(int offset, int num_bytes, char *src) +{ + BYTE data=0; + BYTE index=0; + Eeprom_EnableAccess(); + printk("Read data = "); + for(index=offset ;index<(offset+num_bytes); index++) { + if(Eeprom_ReadLocation(index,&data)) { +#if 1 + printk("0x%02x ", (u32)data); +#endif + memcpy(src, &data, 1); + src++; + } else { + break; + } + } + Eeprom_DisableAccess(); + printk("\n"); + return 0; +} + +int smsc_prom_get_ethernet_mac_addr(char *addr) +{ + int ret = 0; + unsigned char ea[6]; + + /*0th byte should be 0xA5 in EEPROM */ + get_data_from_eeprom(0, 1, ea); + + if(ea[0] == 0xA5) { + printk("Reading Ethernet Mac Address from EEPROM\n"); + get_data_from_eeprom(1, 6, ea); + } else { + /*Get from envs*/ + printk("Reading Ethernet Mac from Environment variables\n"); + ret = prom_get_ethernet_addr(ea); + if( (ret<0) || + ((ea[0]== 0) && + (ea[1] == 0) && + (ea[2] == 0) && + (ea[3] == 0) && + (ea[4] == 0) && + (ea[5] == 0)) ) { + printk("####### ERROR!!!!######################\n"); + printk("###### ETHERNET MAC ADDRESS IS NOT SET #########\n"); + printk("###### PLEASE SET MAC ADDRESS #########\n"); + printk("#######################################\n"); + goto out; + } + } + + memcpy(addr, ea, 6); + +out: + return ret; +} + +int smsc_prom_get_wifi_mac_addr(char *addr) +{ + int ret = 0; + unsigned char ea[6]; + + /*0th byte should be 0xA5 in EEPROM */ + get_data_from_eeprom(0, 1, ea); + + if(ea[0] == 0xA5) { + printk("Reading Wifi Mac Address from EEPROM\n"); + get_data_from_eeprom(7, 6, ea); + } else { + /*Get from envs*/ + printk("Reading Wifi Mac from Environment variables\n"); + ret = prom_get_wifi_addr(ea); + if(ret<0){ + printk("####### ERROR!!!!######################\n"); + printk("###### WIFI MAC ADDRESS IS NOT SET #########\n"); + printk("###### PLEASE SET MAC ADDRESS #########\n"); + printk("#######################################\n"); + goto out; + } + } + + memcpy(addr, ea, 6); +out: + return ret; +} + +EXPORT_SYMBOL(get_data_from_eeprom); +EXPORT_SYMBOL(smsc_prom_get_ethernet_mac_addr); +EXPORT_SYMBOL(smsc_prom_get_wifi_mac_addr); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/init.c linux-2.6.29/arch/mips/alchemy/devboards/hmp10/init.c --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/init.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/init.c 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,78 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * HMP10 board setup, based on PB1200 Setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + + if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { + /* fw_arg0 is not a valid number, or fw_arg1 is not a valid pointer */ + prom_argc = 0; + prom_argv = prom_envp = NULL; + printk("CKSEG0 0x%08x fw_arg0 0x%lx fw_arg1 0x%lx\n", + CKSEG0,fw_arg0,fw_arg1); + } else { + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + } + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x10000000; + else + memsize = simple_strtol(memsize_str, NULL, 0); + + /* + * Reserve two sections of memory for the mempool driver. The 32 MB + * region is for MAE; the 24 MB region is for the LCD framebuffer. + * + * TODO: Couple these reservations with the mempool driver somehow. + */ + add_memory_region(memsize - (32*MB), (32*MB), BOOT_MEM_RESERVED); + memsize -= 32*MB; + add_memory_region(memsize - (24*MB), (24*MB), BOOT_MEM_RESERVED); + memsize -= 24*MB; + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/irqmap.c linux-2.6.29/arch/mips/alchemy/devboards/hmp10/irqmap.c --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/irqmap.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/irqmap.c 2009-05-29 11:43:37.000000000 -0400 @@ -0,0 +1,92 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx irq map table + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + + +struct au1xxx_irqmap __initdata au1xxx_irq_map[8]; + +struct au1xxx_irqmap au1xxx_irq_map_I[] = { + { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 }, // This is exteranl interrupt cascade + { AU1000_GPIO_12, IRQF_TRIGGER_LOW, 0 }, + { AU1200_GPIO_202, IRQF_TRIGGER_RISING, 0 }, + { AU1200_GPIO_205, IRQF_TRIGGER_RISING, 0 }, + { AU1200_GPIO_206, IRQF_TRIGGER_RISING, 0 }, + { AU1200_GPIO_207, IRQF_TRIGGER_RISING, 0 }, + { AU1200_GPIO_208_215, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, +}; + + +struct au1xxx_irqmap au1xxx_irq_map_II[] = { + { AU1000_GPIO_3, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, // This is exteranl interrupt cascade + { AU1000_GPIO_12, IRQF_TRIGGER_LOW, 0 }, + { AU1200_GPIO_202, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, + { AU1200_GPIO_203, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, + { AU1200_GPIO_205, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, + { AU1200_GPIO_206, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, + { AU1200_GPIO_207, IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, 0 }, +}; + +int au1xxx_nr_irqs = 0; // will be calculated at run time + +void __init board_init_irq(void) + +{ + int boardMinor = 0; + + boardInfo_t *hmp_board = get_au1xxx_board_info(); + boardMinor = hmp_board->boardMinor; + if (boardMinor == 0) { + au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map_I); + memcpy((u8 *)au1xxx_irq_map,(u8 *)au1xxx_irq_map_I,(au1xxx_nr_irqs * sizeof(struct au1xxx_irqmap))); + printk("Using GPIO mapping irq_map_I\n"); + }else { + au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map_II); + memcpy((u8 *)au1xxx_irq_map,(u8 *)au1xxx_irq_map_II,(au1xxx_nr_irqs * sizeof(struct au1xxx_irqmap))); + printk("Using GPIO mapping irq_map_II\n"); + } + au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/Makefile linux-2.6.29/arch/mips/alchemy/devboards/hmp10/Makefile --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/Makefile 2009-05-29 12:24:25.000000000 -0400 @@ -0,0 +1,7 @@ +# +# Makefile for the Alchemy HMP10 board. +# + +obj-y := board_setup.o init.o irqmap.o mmc.o eeprom.o + +EXTRA_CFLAGS += -Werror diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/hmp10/mmc.c linux-2.6.29/arch/mips/alchemy/devboards/hmp10/mmc.c --- linux-2.6.29/arch/mips/alchemy/devboards/hmp10/mmc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/hmp10/mmc.c 2009-05-29 11:43:37.000000000 -0400 @@ -0,0 +1,158 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#if 0 +static volatile struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1_OFFSET); + +static int mmc_activity; +static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; + + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev db1300mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + + +static int db1300mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1_WP) ? 1 : 0; +} + +static int db1300mmc1_card_inserted(void *mmc_host) +{ + int retval; + retval = (bcsr->sig_status & BCSR_INT_SD1_INSERT) ? 1 : 0; + return retval; +} +#endif + +struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = NULL, + .card_inserted = NULL, + .card_readonly = NULL, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = NULL, + }, + [1] = { + .set_power = NULL, + .card_inserted = NULL, + .card_readonly = NULL, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = NULL, + }, +}; + +#if 0 +static struct resource au13xx_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc0_device = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc0_resources), + .resource = au13xx_mmc0_resources, +}; + +static struct resource au13xx_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc1_resources), + .resource = au13xx_mmc1_resources, +}; +#endif + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/leds.c linux-2.6.29/arch/mips/alchemy/devboards/leds.c --- linux-2.6.29/arch/mips/alchemy/devboards/leds.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/leds.c 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,68 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +/* + * Requires the following to be defined in the board-specifc .h file: + * - HEX_REGS_KSEG1_ADDR + * - struct hex_regs with members: + * - hex (set the hex value) + * - BCSR_REGS_KSEG1_ADDR + * - struct bcsr_regs + */ + +static hex_regs *const hex = (hex_regs *)(HEX_REGS_KSEG1_ADDR); + +/* + * Takes a u8 because though the register is 16 bits, only 8 appear + */ +void db_set_hex(u8 val) +{ + au_iowrite16((u16)val, &hex->hex); +} + +/* + * 2 dots use the least significant 2 bits + * Setting a bit lights the LED (opposite of the register) + */ +void db_set_hex_dots(u8 val) +{ + u16 leds = au_ioread16(&db_bcsr->disk_leds); + leds |= 0x3; + leds &= (~(val & 0x3)); + au_iowrite16(leds, &db_bcsr->disk_leds); +} + +void db_set_led(u8 led) +{ + au_clear_bits_16(1<<(led+8), &db_bcsr->disk_leds); +} + +void db_clear_led(u8 led) +{ + au_set_bits_16(1<<(led+8), &db_bcsr->disk_leds); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/Makefile linux-2.6.29/arch/mips/alchemy/devboards/Makefile --- linux-2.6.29/arch/mips/alchemy/devboards/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/devboards/Makefile 2009-08-21 19:14:45.000000000 -0400 @@ -1,8 +1,6 @@ # # Alchemy Develboards # - -obj-y += prom.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1000) += pb1000/ obj-$(CONFIG_MIPS_PB1100) += pb1100/ @@ -12,7 +10,14 @@ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ +obj-$(CONFIG_MIPS_HMP10) += hmp10/ + +# These two files are used only by DB1300 today but will be used by DB1200 and +# possibly others in the future. +obj-$(CONFIG_MIPS_DB1300) += cascade_irq.o +obj-$(CONFIG_MIPS_DB1300) += leds.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/pb1200/board_setup.c linux-2.6.29/arch/mips/alchemy/devboards/pb1200/board_setup.c --- linux-2.6.29/arch/mips/alchemy/devboards/pb1200/board_setup.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/devboards/pb1200/board_setup.c 2009-08-21 19:14:45.000000000 -0400 @@ -42,6 +42,25 @@ bcsr->system = 0; } +static BCSR save_bcsr; + +void save_board_regs(void) +{ + save_bcsr.pcmcia = bcsr->pcmcia; + save_bcsr.disk_leds = bcsr->disk_leds; + save_bcsr.intset = bcsr->intset; + save_bcsr.intset_mask = bcsr->intset_mask; +} + +void restore_board_regs(void) +{ + bcsr->pcmcia = save_bcsr.pcmcia; + bcsr->disk_leds = save_bcsr.disk_leds; + bcsr->intset = save_bcsr.intset; + bcsr->intset_mask = save_bcsr.intset_mask; +} + + void __init board_setup(void) { char *argptr; @@ -142,6 +161,28 @@ return p; } +int board_au1200fb_backlight_on(void) +{ + /* Apply power */ + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; + + bcsr->board |= BCSR_BOARD_LCDBL; + /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ + return 0; + +} + +int board_au1200fb_backlight_off(void) +{ + /* Remove power */ + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; + + bcsr->board &= ~( BCSR_BOARD_LCDBL); + /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ + return 0; + +} + int board_au1200fb_panel_init(void) { /* Apply power */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/pb1200/init.c linux-2.6.29/arch/mips/alchemy/devboards/pb1200/init.c --- linux-2.6.29/arch/mips/alchemy/devboards/pb1200/init.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/alchemy/devboards/pb1200/init.c 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,78 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PB1200 Setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + + if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { + /* fw_arg0 is not a valid number, or fw_arg1 is not a valid pointer */ + prom_argc = 0; + prom_argv = prom_envp = NULL; + printk("CKSEG0 0x%08x fw_arg0 0x%lx fw_arg1 0x%lx\n", + CKSEG0,fw_arg0,fw_arg1); + } else { + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + } + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x10000000; + else + memsize = simple_strtol(memsize_str, NULL, 0); + + /* + * Reserve two sections of memory for the mempool driver. The 32 MB + * region is for MAE; the 24 MB region is for the LCD framebuffer. + * + * TODO: Couple these reservations with the mempool driver somehow. + */ + add_memory_region(memsize - (32*MB), (32*MB), BOOT_MEM_RESERVED); + memsize -= 32*MB; + add_memory_region(memsize - (24*MB), (24*MB), BOOT_MEM_RESERVED); + memsize -= 24*MB; + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/pb1200/Makefile linux-2.6.29/arch/mips/alchemy/devboards/pb1200/Makefile --- linux-2.6.29/arch/mips/alchemy/devboards/pb1200/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/devboards/pb1200/Makefile 2009-08-21 19:14:45.000000000 -0400 @@ -2,6 +2,6 @@ # Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. # -obj-y := board_setup.o irqmap.o platform.o +obj-y := board_setup.o irqmap.o platform.o init.o EXTRA_CFLAGS += -Werror diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/devboards/prom.c linux-2.6.29/arch/mips/alchemy/devboards/prom.c --- linux-2.6.29/arch/mips/alchemy/devboards/prom.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/devboards/prom.c 1969-12-31 19:00:00.000000000 -0500 @@ -1,62 +0,0 @@ -/* - * Common code used by all Alchemy develboards. - * - * Extracted from files which had this to say: - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ - defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 - -#else /* Au1550/Au1200-based develboards */ -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000 -#endif - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = (int)fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); -} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/alchemy/Kconfig linux-2.6.29/arch/mips/alchemy/Kconfig --- linux-2.6.29/arch/mips/alchemy/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/alchemy/Kconfig 2009-09-16 18:47:00.000000000 -0400 @@ -35,6 +35,14 @@ select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN + select AU_MEMPOOL + +config MIPS_HMP10 + bool "Alchemy HMP10 board" + select SOC_AU1200 + select DMA_COHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + select AU_MEMPOOL config MIPS_DB1500 bool "Alchemy DB1500 board" @@ -53,6 +61,14 @@ select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN +config MIPS_DB1300 + bool "Alchemy DB1300 board" + select SOC_AU13XX + select DMA_COHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select AU_MEMPOOL + config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT @@ -108,22 +124,32 @@ config SOC_AU1000 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1100 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1500 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1550 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1200 bool select SOC_AU1X00 + select AU_INT_CNTLR + +config SOC_AU13XX + bool + select SOC_AU1X00 + select AU_GPIO_INT_CNTLR config SOC_AU1X00 bool @@ -135,3 +161,12 @@ select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + +config AU_INT_CNTLR + bool + +config AU_GPIO_INT_CNTLR + bool + +config AU_MEMPOOL + bool diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/configs/db1200_defconfig linux-2.6.29/arch/mips/configs/db1200_defconfig --- linux-2.6.29/arch/mips/configs/db1200_defconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/configs/db1200_defconfig 2009-08-21 19:14:45.000000000 -0400 @@ -1,79 +1,101 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:25 2007 +# Linux kernel version: 2.6.29-RMI-81 +# Thu Aug 13 16:32:41 2009 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -CONFIG_MIPS_DB1200=y -# CONFIG_MIPS_MIRAGE is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1200=y +# CONFIG_MIPS_HMP10 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1300 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_INT_CNTLR=y +CONFIG_AU_MEMPOOL=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -86,6 +108,7 @@ # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -93,11 +116,13 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -112,24 +137,31 @@ CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -143,37 +175,48 @@ # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y +# CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y @@ -182,34 +225,37 @@ CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -223,15 +269,13 @@ # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +# CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m @@ -244,47 +288,44 @@ CONFIG_PCMCIA_AU1X00=m # -# PCI Hotplug Support -# - -# # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y # # Power management options # -# CONFIG_PM is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set +CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set CONFIG_INET=y -CONFIG_IP_MULTICAST=y +# CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set @@ -292,107 +333,24 @@ # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -402,21 +360,29 @@ # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -425,25 +391,22 @@ # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -456,6 +419,7 @@ # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -481,7 +445,6 @@ # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access @@ -505,91 +468,76 @@ # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_AU1550 is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# LPDDR flash memory drivers # -# CONFIG_PARPORT is not set +# CONFIG_MTD_LPDDR is not set # -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_BLK_DEV_HD is not set +# CONFIG_LBA_NAND is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set CONFIG_BLK_DEV_IDE_AU1XXX=y CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y # CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set -CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 -# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y -CONFIG_SCSI_TGT=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y @@ -599,8 +547,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set @@ -610,7 +557,8 @@ CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -618,111 +566,67 @@ # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# -# CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_DEBUG is not set - -# -# PCMCIA SCSI adapter support -# -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_SYM53C500 is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_MIPS_AU1X00_ENET is not set -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y # CONFIG_DM9000 is not set +# CONFIG_SMSC9210 is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set # -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # -# Token Ring devices +# Enable WiMAX (Networking options) to see the WiMAX drivers # # -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support +# USB Network Adapters # +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set # CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -730,6 +634,7 @@ # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -739,16 +644,33 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -758,7 +680,7 @@ CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=y # CONFIG_GAMEPORT is not set @@ -766,11 +688,12 @@ # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set # # Serial drivers @@ -789,22 +712,11 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # @@ -813,61 +725,134 @@ # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y # -# TPM devices +# I2C Hardware Bus support # -# CONFIG_TCG_TPM is not set # -# I2C support +# I2C system bus drivers (mostly embedded / system-on-chip) # -# CONFIG_I2C is not set +CONFIG_I2C_AU1550=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set # -# SPI support +# External I2C/SMBus adapter drivers # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set # -# Dallas's 1-wire bus +# Other I2C/SMBus bus drivers # -# CONFIG_W1 is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # -# Hardware Monitoring support +# Miscellaneous I2C Chip support # +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set CONFIG_FB_AU1200=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support @@ -875,108 +860,258 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set - -# -# Logo configuration -# +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_LOGO_RMI_ALCHEMY_VGA16=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_SEQUENCER=y +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_PCMCIA is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=m +CONFIG_SND_SOC_AU1XPSC_AC97=m +CONFIG_SND_SOC_SAMPLE_PSC_I2S=m +CONFIG_SND_SOC_SAMPLE_PSC_AC97=m +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_WM8731=m +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set # -# USB support +# USB Input Devices # +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_IMX is not set +CONFIG_USB_GADGET_M66592=y +CONFIG_USB_M66592=m +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set # -# MMC/SD Card support +# OTG and related infrastructure # CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_AU1X=y +CONFIG_MMC_UNSAFE_RESUME=y # -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# MMC/SD/SDIO Card Drivers # +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# Real Time Clock +# MMC/SD/SDIO Host Controller Drivers # +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -990,26 +1125,20 @@ CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set -CONFIG_JFS_FS=y -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set +# CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -1018,18 +1147,15 @@ # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=m +CONFIG_FAT_FS=y CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m +CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set @@ -1040,19 +1166,15 @@ CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set @@ -1061,187 +1183,228 @@ CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=m +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="mem=48M" +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +CONFIG_DYNAMIC_PRINTK_DEBUG=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_MANAGER=m -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set # -# Hardware crypto devices +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation # +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/configs/db1300_be_defconfig linux-2.6.29/arch/mips/configs/db1300_be_defconfig --- linux-2.6.29/arch/mips/configs/db1300_be_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/configs/db1300_be_defconfig 2009-09-03 17:28:38.000000000 -0400 @@ -0,0 +1,1466 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29.4-rmi-126 +# Thu Sep 3 16:22:05 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_HMP10 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +CONFIG_MIPS_DB1300=y +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU13XX=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_GPIO_INT_CNTLR=y +CONFIG_AU_MEMPOOL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-DB1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_ASHMEM is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_PCMCIA_AU1X00=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CT_ACCT=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +# CONFIG_NF_CT_PROTO_UDPLITE is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_LBA_NAND is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDE_AU1XXX=y +# CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA is not set +CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC9210 is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_AU1550=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Alchemy MAE +# +# CONFIG_AU13XX_MAE2 is not set +# CONFIG_ALCHEMY_MAE_ITE is not set +# CONFIG_ALCHEMY_MAE_BSA is not set +# CONFIG_ALCHEMY_MAE_MPE is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RMI_ALCHEMY_VGA16=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_PCMCIA is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +# CONFIG_SND_SOC_SAMPLE_PSC_I2S is not set +CONFIG_SND_SOC_SAMPLE_PSC_AC97=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_XFER_BUF_SWIZZLE=y +CONFIG_USB_AU13XX_BIG_ENDIAN=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +CONFIG_JFS_FS=y +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/configs/db1300_defconfig linux-2.6.29/arch/mips/configs/db1300_defconfig --- linux-2.6.29/arch/mips/configs/db1300_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/configs/db1300_defconfig 2009-09-02 10:45:55.000000000 -0400 @@ -0,0 +1,1472 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29.4-105 +# Mon Aug 24 07:57:33 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_HMP10 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +CONFIG_MIPS_DB1300=y +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU13XX=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_GPIO_INT_CNTLR=y +CONFIG_AU_MEMPOOL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-DB1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ASHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_PCMCIA_AU1X00=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_VERBOSE=y +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_LBA_NAND is not set +CONFIG_MISC_DEVICES=y +CONFIG_ANDROID_PMEM=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECS=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_IDE_AU1XXX is not set +# CONFIG_BLK_DEV_IDEDMA is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC9210 is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_AU1550=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_WM97XX is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_BATTERY_DUMMY=y +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Alchemy MAE +# +CONFIG_AU13XX_MAE2=y +CONFIG_ALCHEMY_MAE_ITE=y +CONFIG_ALCHEMY_MAE_BSA=y +CONFIG_ALCHEMY_MAE_MPE=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RMI_ALCHEMY_VGA16=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +CONFIG_SND_PCMCIA=y +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_PDAUDIOCF is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +# CONFIG_SND_SOC_SAMPLE_PSC_I2S is not set +CONFIG_SND_SOC_SAMPLE_PSC_AC97=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AU1XXX=y +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_MEILHAUS is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_INPUT_MIMIO is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y +# CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set +# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set +CONFIG_ANDROID_LOW_MEMORY_KILLER=y + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_TRACING=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/configs/hmp10_defconfig linux-2.6.29/arch/mips/configs/hmp10_defconfig --- linux-2.6.29/arch/mips/configs/hmp10_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/configs/hmp10_defconfig 2009-09-02 10:43:51.000000000 -0400 @@ -0,0 +1,1177 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-RMI-113 +# Wed Aug 26 14:34:20 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +CONFIG_MIPS_HMP10=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1300 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_INT_CNTLR=y +CONFIG_AU_MEMPOOL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=m +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_LBA_NAND=y +# CONFIG_LBA_DEBUG_MSG is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC9210 is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_APMPOWER=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_HMP=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +CONFIG_LOGO_LINUX_VGA16=y +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RMI_ALCHEMY_VGA16=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_SEQUENCER=y +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +# CONFIG_SND_SOC_SAMPLE_PSC_I2S is not set +# CONFIG_SND_SOC_SAMPLE_PSC_AC97 is not set +CONFIG_SND_SOC_HMP10_AC97=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="video=au1200fb:panel:10" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/configs/hmp10-ramfs_defconfig linux-2.6.29/arch/mips/configs/hmp10-ramfs_defconfig --- linux-2.6.29/arch/mips/configs/hmp10-ramfs_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/configs/hmp10-ramfs_defconfig 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,1135 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-RMI-81 +# Tue Aug 11 19:26:10 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +CONFIG_MIPS_HMP10=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1300 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_INT_CNTLR=y +CONFIG_AU_MEMPOOL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="${TOPDIR}/usr/initramfs_data.cpio" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m + +# +# Rate control algorithm selection +# +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_LBA_NAND=m +# CONFIG_LBA_DEBUG_MSG is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_SMSC911X=m +# CONFIG_SMSC9210 is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_HMP=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +CONFIG_LOGO_LINUX_VGA16=y +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RMI_ALCHEMY_VGA16=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=m +CONFIG_SND_SOC_AU1XPSC_AC97=m +# CONFIG_SND_SOC_SAMPLE_PSC_I2S is not set +# CONFIG_SND_SOC_SAMPLE_PSC_AC97 is not set +CONFIG_SND_SOC_HMP10_AC97=m +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=m +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=m +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="video=au1200fb:panel:10" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/addrspace.h linux-2.6.29/arch/mips/include/asm/addrspace.h --- linux-2.6.29/arch/mips/include/asm/addrspace.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/addrspace.h 2009-09-02 10:21:37.000000000 -0400 @@ -151,4 +151,10 @@ #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +/* + * Useful helper macros for memory area declarations. + */ +#define KB (1024) +#define MB (1024 * 1024) + #endif /* _ASM_ADDRSPACE_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/cpu.h linux-2.6.29/arch/mips/include/asm/cpu.h --- linux-2.6.29/arch/mips/include/asm/cpu.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/cpu.h 2009-06-01 11:32:02.000000000 -0400 @@ -33,9 +33,9 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 - /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -115,9 +115,13 @@ #define PRID_IMP_BCM3302 0x9000 /* - * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + * These are the PRID's for when 23:16 == PRID_COMP_RMI */ +#define PRID_IMP_AU13XX 0x8000 +/* + * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + */ #define PRID_IMP_CAVIUM_CN38XX 0x0000 #define PRID_IMP_CAVIUM_CN31XX 0x0100 #define PRID_IMP_CAVIUM_CN30XX 0x0200 @@ -210,7 +214,7 @@ */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_AU1550, CPU_AU13XX, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/fixmap.h linux-2.6.29/arch/mips/include/asm/fixmap.h --- linux-2.6.29/arch/mips/include/asm/fixmap.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/fixmap.h 2009-05-29 11:43:37.000000000 -0400 @@ -108,6 +108,9 @@ return __virt_to_fix(vaddr); } +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) + /* * Called from pgtable_init() */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/highmem.h linux-2.6.29/arch/mips/include/asm/highmem.h --- linux-2.6.29/arch/mips/include/asm/highmem.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/highmem.h 2009-08-17 09:11:43.000000000 -0400 @@ -30,8 +30,6 @@ /* declarations for highmem.c */ extern unsigned long highstart_pfn, highend_pfn; -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; extern pte_t *pkmap_page_table; /* @@ -54,6 +52,10 @@ extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); extern struct page *__kmap_atomic_to_page(void *ptr); +#ifdef CONFIG_MACH_ALCHEMY +extern unsigned long kmap_atomic_phys(void *kvaddr); +#endif + #define kmap __kmap #define kunmap __kunmap #define kmap_atomic __kmap_atomic @@ -62,6 +64,10 @@ #define flush_cache_kmaps() flush_cache_all() +extern void kmap_init(void); + +#define kmap_prot PAGE_KERNEL + #endif /* __KERNEL__ */ #endif /* _ASM_HIGHMEM_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/io.h linux-2.6.29/arch/mips/include/asm/io.h --- linux-2.6.29/arch/mips/include/asm/io.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/io.h 2009-09-02 10:43:51.000000000 -0400 @@ -267,6 +267,7 @@ */ #define ioremap_cachable(offset, size) \ __ioremap_mode((offset), (size), _page_cachable_default) +#define ioremap_cached(offset, size) ioremap_cachable(offset, size) /* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1000.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1000.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1000.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1000.h 2009-08-25 09:48:00.000000000 -0400 @@ -6,6 +6,9 @@ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -43,6 +46,8 @@ #include #include +#include + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -125,11 +130,53 @@ case 0x02030201: /* Au1100 BA */ case 0x02030202: /* Au1100 BC */ case 0x04030201: /* Au1200 AC */ + case 0x04030202: /* Au1250 */ + case 0x05030202: /* Au1210 */ return 1; } return 0; } +void static inline au_iowrite16(u16 val, volatile u16 *reg) +{ + *reg = val; +} + +static inline u16 au_ioread16(volatile u16 *reg) +{ + return *reg; +} + +void static inline au_iowrite32(u32 val, volatile u32 *reg) +{ + *reg = val; +} + +static inline u32 au_ioread32(volatile u32 *reg) +{ + return *reg; +} + +static inline void au_set_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) | mask), reg); +} + +static inline void au_clear_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) & ~mask), reg); +} + +static inline void au_set_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) | mask), reg); +} + +static inline void au_clear_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) & ~mask), reg); +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -903,6 +950,7 @@ AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, + AU1200_GPIO_203, AU1200_NAND_INT = AU1200_FIRST_INT + 23, AU1200_GPIO_204, AU1200_GPIO_205, @@ -1232,7 +1280,12 @@ #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ +#ifdef CONFIG_SOC_AU13XX +#define UART_BASE UART2_ADDR +#else #define UART_BASE UART0_ADDR +#endif + #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au13xx.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au13xx.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au13xx.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au13xx.h 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,398 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU13XX_H +#define _AU13XX_H + +#ifdef CONFIG_SOC_AU13XX +#include + +#define UART0_ADDR 0xB0100000 +#define UART1_ADDR 0xB0101000 +#define UART2_ADDR 0xB0102000 +#define UART3_ADDR 0xB0103000 + +#define GPIO_INT_CTRLR_BASE 0x10200000 +/* + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel + * bits need to be offset by 8 either when passed to do_IRQ or when received + * through the irq_chip calls + * + * KH: TODO - This is duplicated from gpio_int.h Is that the right thing to do? + */ +#define GPINT_LINUX_IRQ_OFFSET 8 + +#define AU1300_IRQ_UART1 17 +#define AU1300_IRQ_UART2 25 +#define AU1300_IRQ_UART3 27 +#define AU1300_IRQ_SD1 32 +#define AU1300_IRQ_SD2 38 +#define AU1300_IRQ_PSC0 48 +#define AU1300_IRQ_PSC1 52 +#define AU1300_IRQ_PSC2 56 +#define AU1300_IRQ_PSC3 60 +#define AU1300_IRQ_NAND 62 +#define AU1300_IRQ_DDMA 75 +#define AU1300_IRQ_GPU 78 +#define AU1300_IRQ_MPU 77 +#define AU1300_IRQ_MMU 76 +#define AU1300_IRQ_UDMA 79 +#define AU1300_IRQ_TOY_TICK 80 +#define AU1300_IRQ_TOYMATCH_0 81 +#define AU1300_IRQ_TOYMATCH_1 82 +#define AU1300_IRQ_TOYMATCH_2 83 +#define AU1300_IRQ_RTC_TICK 84 +#define AU1300_IRQ_RTCMATCH_0 85 +#define AU1300_IRQ_RTCMATCH_1 86 +#define AU1300_IRQ_RTCMATCH_2 87 +#define AU1300_IRQ_UART0 88 +#define AU1300_IRQ_SD0 89 +#define AU1300_IRQ_USB 90 +#define AU1300_IRQ_LCD 91 +#define AU1300_IRQ_BSA 94 +#define AU1300_IRQ_MPE 93 +#define AU1300_IRQ_ITE 92 +#define AU1300_IRQ_AES 95 +#define AU1300_IRQ_CIM 96 + +#define LCD_PHYS_ADDR 0x15000000 + +#define AU1200_LCD_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_LCD) +#define AU1000_RTC_MATCH2_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_RTCMATCH_2) + +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10601000 + +/* + * VSS Power Island registers and fields. + */ +#if !defined(ASSEMBLER) +typedef volatile struct +{ + /* 0x0000 */ u32 gate; + /* 0x0004 */ u32 clkrst; + /* 0x0008 */ u32 ftr; +} AU13XX_VSS_BLOCK; + +typedef volatile struct +{ + AU13XX_VSS_BLOCK mpe; + AU13XX_VSS_BLOCK bsa; + AU13XX_VSS_BLOCK gpu; + AU13XX_VSS_BLOCK mgp; +} AU13XX_VSSCTRL; +#endif /* ASSEMBLER */ + +#define VSS_PHYS_ADDR 0x11003000 + +#define VSS_GATE_NWAIT(n) ((n&0x3f)<<19) +#define VSS_GATE_MWAIT(n) ((n&0x3f)<<13) +#define VSS_GATE_LWAIT(n) ((n&0x3f)<<7) +#define VSS_GATE_KWAIT(n) ((n&0x3f)<<1) +#define VSS_GATE_EN (1<<0) + +#define VSS_CLOCK_EN (1<<1) +#define VSS_BLOCK_RST (1<<0) + +#define VSS_ISO_EN (1<<4) +#define VSS_FTR_EN(n) (1<<(n)) + +/* + * Non-register defines used for indexing + */ +#define VSS_MPE 0 +#define VSS_BSA 1 +#define VSS_GPU 2 +#define VSS_MGP 3 +#define VSS_MAX VSS_MGP + +int vss_block_power_up(int block); +void vss_block_power_down(int block); + +#define USB_BASE_PHYS_ADDR 0x14021000 +#define USB_EHCI_BASE 0x14020000 +#define USB_EHCI_LEN 0x400 +#define USB_OHCI_BASE 0x14020800 +#define USB_OHCI_LEN 0x400 +#define USB_UOC_BASE 0x14022000 +#define USB_UOC_LEN 0x20 +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 + +struct au13xx_usb_regs { + u32 dwc_ctrl1; + u32 dwc_ctrl2; + u32 reserved0[2]; + + u32 vbus_timer; + u32 sbus_ctrl; + u32 msr_err; + u32 dwc_ctrl3; + + u32 dwc_ctrl4; + u32 reserved1; + u32 otg_status; + u32 dwc_ctrl5; + + u32 dwc_ctrl6; + u32 dwc_ctrl7; + + u32 reserved2[(0xC0-0x38)/4]; + + u32 phy_status; + u32 intr_status; + u32 intr_enable; + +}; + +#define USB_DWC_CTRL1_OTGD (1<<2) +#define USB_DWC_CTRL1_HSTRS (1<<1) +#define USB_DWC_CTRL1_DCRS (1<<0) + +#define USB_DWC_CTRL2_HTBSE1 (1<<11) +#define USB_DWC_CTRL2_HTBSE0 (1<<10) +#define USB_DWC_CTRL2_LTBSE1 (1<<9) +#define USB_DWC_CTRL2_LTBSE0 (1<<8) +#define USB_DWC_CTRL2_LPBKE1 (1<<5) +#define USB_DWC_CTRL2_LPBKE0 (1<<4) +#define USB_DWC_CTRL2_VBUSD (1<<3) +#define USB_DWC_CTRL2_PH1RS (1<<2) +#define USB_DWC_CTRL2_PHY0RS (1<<1) +#define USB_DWC_CTRL2_PHYRS (1<<0) + +#define USB_VBUS_TIMER(n) (n) + +#define USB_SBUS_CTRL_SBCA (1<<2) +#define USB_SBUS_CTRL_HWSZ (1<<1) +#define USB_SBUS_CTRL_BSZ (1<<0) + +#define USB_MSR_ERR_ILLBM (1<<18) +#define USB_MSR_ERR_ILLBRST (1<<17) +#define USB_MSR_ERR_UADDRSTS (1<<16) +#define USB_MSR_ERR_BMMSK (1<<2) +#define USB_MSR_ERR_BRSTMSK (1<<1) +#define USB_MSR_ERR_UADMK (1<<0) + +#define USB_DWC_CTRL3_VATEST_EN (1<<20) +#define USB_DWC_CTRL3_OHC1_CLKEN (1<<19) +#define USB_DWC_CTRL3_OHC0_CLKEN (1<<18) +#define USB_DWC_CTRL3_EHC_CLKEN (1<<17) +#define USB_DWC_CTRL3_OTG_CLKEN (1<<16) +#define USB_DWC_CTRL3_OHCI_SUSP (1<<3) +#define USB_DWC_CTRL3_VBUS_VALID_PORT1 (1<<2) +#define USB_DWC_CTRL3_VBUS_VALID_PORT0 (1<<1) +#define USB_DWC_CTRL3_VBUS_VALID_SEL (1<<0) + +#define USB_DWC_CTRL4_USB_MODE (1<<16) +#define USB_DWC_CTRL4_AHB_CLKDIV(n) ((n&0xF)<<0) + +#define USB_OTG_STATUS_IDPULLUP (1<<8) +#define USB_OTG_STATUS_IDDIG (1<<7) +#define USB_OTG_STATUS_DISCHRGVBUS (1<<6) +#define USB_OTG_STATUS_CHRGVBUS (1<<5) +#define USB_OTG_STATUS_DRVVBUS (1<<4) +#define USB_OTG_STATUS_SESSIONEND (1<<3) +#define USB_OTG_STATUS_VBUSVALID (1<<2) +#define USB_OTG_STATUS_BVALID (1<<1) +#define USB_OTG_STATUS_AVALID (1<<0) + +#define USB_DWC_CTRL5_REFCLK_DIV(n) ((n&3)<<18) +#define USB_DWC_CTRL5_REFCLK_EN(n) ((n&3)<<16) +#define USB_DWC_CTRL5_SIDDQ (1<<1) +#define USB_DWC_CTRL5_COMMONONN (1<<0) + +#define USB_DWC_CTRL6_DMPULLDOWN_PORT1 (1<<3) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT1 (1<<2) +#define USB_DWC_CTRL6_DMPULLDOWN_PORT2 (1<<1) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT2 (1<<0) + +#define USB_DWC_CTRL7_OHC_STARTCLK (1<<0) + +#define USB_PHY_STATUS_VBUS (1<<0) + +#define USB_INTR_S2A (1<<6) +#define USB_INTR_FORCE (1<<5) +#define USB_INTR_PHY (1<<4) +#define USB_INTR_DEVICE (1<<3) +#define USB_INTR_EHCI (1<<2) +#define USB_INTR_OHCI1 (1<<1) +#define USB_INTR_OHCI0 (1<<0) + +#define AU1000_USB_HOST_INT (AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET) + +/* + * MAE ITE Registers and structure +*/ +/* SCF Registers */ +#define MAEITE_SCFHSR 0x0000 +#define MAEITE_SCFVSR 0x0004 +#define MAEITE_SCFDISABLE 0x0008 +#define MAEITE_SCFHALUT 0x0100 +#define MAEITE_SCFVALUT 0x0180 +#define MAEITE_SCFHBLUT 0x0200 +#define MAEITE_SFCVBLUT 0x0280 +#define MAEITE_SCFHCLUT 0x0300 +#define MAEITE_SCFVCLUT 0x0380 + +/* CSC Registers */ +#define MAEITE_CSCXCFFA 0x0400 +#define MAEITE_CSCXCFFB 0x0404 +#define MAEITE_CSCXCFFC 0x0408 +#define MAEITE_CSCYCFFA 0x040C +#define MAEITE_CSCYCFFB 0x0410 +#define MAEITE_CSCYCFFC 0x0414 +#define MAEITE_CSCZCFFA 0x0418 +#define MAEITE_CSCZCFFB 0x041C +#define MAEITE_CSCZCFFC 0x0420 +#define MAEITE_CSCXOFF 0x0424 +#define MAEITE_CSCYOFF 0x0428 +#define MAEITE_CSCZOFF 0x042C +#define MAEITE_CSCALPHA 0x0430 + +/* SRC Registers */ +#define MAEITE_SRCCFG 0x0500 +#define MAEITE_SRCFHW 0x0504 +#define MAEITE_SRCAADDR 0x0508 +#define MAEITE_SRCASTR 0x050C +#define MAEITE_SRCBADDR 0x0510 +#define MAEITE_SRCBSTR 0x0514 +#define MAEITE_SRCCADDR 0x0518 +#define MAEITE_SRCCSTR 0x051C + +/* DST Registers */ +#define MAEITE_DSTCFG 0x0600 +#define MAEITE_DSTHEIGHT 0x0604 +#define MAEITE_DSTADDR 0x0608 +#define MAEITE_DSTSTR 0x060C + +/* CTL Registers */ +#define MAEITE_CTLENABLE 0x0700 +#define MAEITE_CTLFPC 0x0704 +#define MAEITE_CTLSTAT 0x0708 +#define MAEITE_CTLINTENABLE 0x070C +#define MAEITE_CTLINTSTAT 0x0710 + + + +struct mae_ite { + u32 scfhsr; // 0x0000 + u32 scfvsr; // 0x0004 + u32 scfdisable; // 0x0008 + u32 reserved0[((MAEITE_SCFHALUT - MAEITE_SCFDISABLE) - 4)/sizeof(u32)]; // 0x000C 0xF4 + u32 scfhalut[32]; // 0x0100 + u32 scfvalut[32]; // 0x0180 + u32 scfhblut[32]; // 0x0200 + u32 scfvblut[32]; // 0x0280 + u32 scfhclut[32]; // 0x0300 + u32 scfvclut[32]; // 0x0380 + + u32 cscxcffa; // 0x0400 + u32 cscxcffb; // 0x0404 + u32 cscxcffc; // 0x0408 + u32 cscycffa; // 0x040C + u32 cscycffb; // 0x0410 + u32 cscycffc; // 0x0414 + u32 csczcffa; // 0x0418 + u32 csczcffb; // 0x041C + u32 csczcffc; // 0x0420 + u32 cscxoff; // 0x0424 + u32 cscyoff; // 0x0428 + u32 csczoff; // 0x042C + u32 cscalpha; // 0x0430 + + u8 reserved1[(MAEITE_SRCCFG - MAEITE_CSCALPHA) - 4]; // 0x0434 +0xCC + u32 srccfg; // 0x0500 + u32 srcfhw; // 0x0504 + u32 srcaaddr; // 0x0508 + u32 srcastr; // 0x050C + u32 srcbaddr; // 0x0510 + u32 srcbstr; // 0x0514 + u32 srccaddr; // 0x0518 + u32 srccstr; // 0x051C + + u8 reserved2[(MAEITE_DSTCFG - MAEITE_SRCCSTR) - 4]; // 0x0520 +0xE0 + u32 dstcfg; // 0x0600 + u32 dstheight; // 0x0604 + u32 dstaddr; // 0x0608 + u32 dststr; // 0x060C + + u8 reserved3[(MAEITE_CTLENABLE - MAEITE_DSTSTR) - 4]; // 0x0610 +0xF0 + u32 ctlenable; // 0x0700 + u32 ctlfpc; // 0x0704 + u32 ctlstat; // 0x0708 + u32 ctlintenable; // 0x070C + u32 ctlintstat; // 0x0710 +}; + +#define MAEITE_PHYS_ADDR 0x14010000 + +#define MAEITE_CTLENABLE_EN (1 << 0) + +#define MAEITE_CTLFPC_FRST (1 << 1) +#define MAEITE_CTLFPC_STR (1 << 0) + +#define MAEITE_CTLSTAT_FP (1 << 1) +#define MAEITE_CTLSTAT_FB (1 << 0) + +#define MAEITE_CTLINTSTAT_FC (1 << 0) + +#define MAEITE_SRCCFG_ICM (1 << 0) // Au1300 +#define MAEITE_SRCCFG_ILCE (1 << 1) // Au1300 +#define MAEITE_SRCCFG_IF (3 << 2) +#define MAEITE_SRCCFG_IF_420 (0 << 2) +#define MAEITE_SRCCFG_IF_422 (1 << 2) +#define MAEITE_SRCCFG_IF_411 (2 << 2) +#define MAEITE_SRCCFG_IF_444 (3 << 2) +#define MAEITE_SRCCFG_ILM (3 << 4) +#define MAEITE_SRCCFG_ILM_UYVY (0 << 4) +#define MAEITE_SRCCFG_ILM_VYUY (1 << 4) +#define MAEITE_SRCCFG_ILM_YUYV (2 << 4) +#define MAEITE_SRCCFG_ILM_YVYU (3 << 4) +#define MAEITE_SRCCFG_ILE (1 << 6) +#define MAEITE_SRCCFG_BM (3 << 7) +#define MAEITE_SRCCFG_BM_RG_GB (0 << 7) +#define MAEITE_SRCCFG_BM_GR_BG (1 << 7) +#define MAEITE_SRCCFG_BM_BG_GR (2 << 7) +#define MAEITE_SRCCFG_BM_GB_RG (3 << 7) +#define MAEITE_SRCCFG_BYE (1 << 9) +#define MAEITE_SRCCFG_EF (1 << 10) + +#define MAEITE_DSTCFG_EF_SHIFT (1) +#define MAEITE_DSTCFG_OF_SHIFT (2) +#define MAEITE_DSTCFG_BGR_SHIFT (4) +#define MAEITE_DSTCFG_ROT_SHIFT (5) +#define MAEITE_DSTCFG_R_SHIFT (7) +#define MAEITE_DSTCFG_EF (1 << MAEITE_DSTCFG_EF_SHIFT) +#define MAEITE_DSTCFG_OF (3 << MAEITE_DSTCFG_OF_SHIFT) +#define MAEITE_DSTCFG_BGR (1 << MAEITE_DSTCFG_BGR_SHIFT) +#define MAEITE_DSTCFG_ROT (3 << MAEITE_DSTCFG_ROT_SHIFT) +#define MAEITE_DSTCFG_R (1 << MAEITE_DSTCFG_R_SHIFT) + +#define MAEITE_SCFHSR_SRI_N(N) (N<<16) +#define MAEITE_SCFVSR_SRI_N(N) (N<<16) + + +#endif /* CONFIG_SOC_AU13XX */ +#endif /* _AU13XX_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h 2009-08-17 09:11:44.000000000 -0400 @@ -195,6 +195,39 @@ #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU13XX */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 @@ -384,8 +417,9 @@ /* * Flags for the put_source/put_dest functions. */ -#define DDMA_FLAGS_IE (1 << 0) -#define DDMA_FLAGS_NOIE (1 << 1) +#define DDMA_FLAGS_IE (1 << 0) +#define DDMA_FLAGS_NOIE (1 << 1) +#define DDMA_FLAGS_PHYSADDR (1 << 2) #endif /* _LANGUAGE_ASSEMBLY */ #endif /* _AU1000_DBDMA_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx.h 2009-07-15 10:25:21.000000000 -0400 @@ -35,9 +35,15 @@ #elif defined(CONFIG_MIPS_PB1200) #include -#elif defined(CONFIG_MIPS_DB1200) +#elif defined(CONFIG_MIPS_DB1200) #include +#elif defined(CONFIG_MIPS_HMP10) +#include + +#elif defined(CONFIG_MIPS_DB1300) +#include + #endif #endif /* _AU1XXX_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h 2009-06-03 11:22:29.000000000 -0400 @@ -47,6 +47,11 @@ #endif #ifdef CONFIG_PM +#define WAS_CONFIG_PM +#undef CONFIG_PM +#endif + +#ifdef CONFIG_PM /* * This will enable the device to be powered up when write() or read() * is called. If this is not defined, the driver will return -EBUSY. @@ -192,3 +197,7 @@ SBC_IDE_##mode##_TCSW | \ SBC_IDE_##mode##_TPM | \ SBC_IDE_##mode##_TA) + +#ifdef WAS_CONFIG_PM +#define CONFIG_PM +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h 2009-06-02 19:05:15.000000000 -0400 @@ -46,6 +46,13 @@ #define PSC1_BASE_ADDR 0xb1b00000 #endif +#ifdef CONFIG_SOC_AU13XX +#define PSC0_BASE_ADDR 0xB0A00000 +#define PSC1_BASE_ADDR 0xB0A01000 +#define PSC2_BASE_ADDR 0xB0A02000 +#define PSC3_BASE_ADDR 0xB0A03000 +#endif + /* * The PSC select and control registers are common to all protocols. */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/dev_boards.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/dev_boards.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/dev_boards.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/dev_boards.h 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,47 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU_DEV_BOARDS_H +#define _AU_DEV_BOARDS_H + +#ifdef CONFIG_MIPS_DB1300 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +void db_set_hex(u8 val); + +/* + * 2 dots use 2 bits + */ +void db_set_hex_dots(u8 val); + +void db_set_led(u8 led); +void db_clear_led(u8 led); + +#endif /* _AU_DEV_BOARDS_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/gpio_int.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/gpio_int.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/gpio_int.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/gpio_int.h 2009-08-21 19:14:45.000000000 -0400 @@ -0,0 +1,242 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _GPIO_INT_H +#define _GPIO_INT_H + +#include + +/* + * There are a total 128 'channels' defined by the Au13xx databook. However, + * this requires 4 sperate 32bit registers for programming. Each register is + * called a 'bank' for ease of use. + */ +#define GPINT_BANK0 0 +#define GPINT_BANK1 1 +#define GPINT_BANK2 2 +#define GPINT_BANK3 3 + +#define GPINT_NUM_BANKS 4 /* 0-3 */ +#define GPINT_MAX_BANK (GPINT_BANK3) + +#define GPINT_GPIO_PER_BANK 32 +#define GPINT_INTS_PER_BANK GPINT_GPIO_PER_BANK + +/* Total number of interrupts our architecture allows */ +#define GPINT_MAX_INTS (GPINT_NUM_BANKS*GPINT_INTS_PER_BANK) + +/* Current maximum supported GPIO/INTERRUPTs */ +#define GPINT_NUM_GPIO GPINT_MAX_INTS +#define GPINT_NUM_INTERRUPTS GPINT_MAX_INTS + +/* Starting GPIO/INTERRUPT for each bank */ +#define GPINT_BANK0_START 0 +#define GPINT_BANK1_START 32 +#define GPINT_BANK2_START 64 +#define GPINT_BANK3_START 96 + +/* divide by 32 to get bank */ +#define GPINT_BANK_FROM_GPIO(n) (n>>5) +#define GPINT_BANK_FROM_INT(n) GPINT_BANK_FROM_GPIO(n) +/* multiply by 32 to get base */ +#define GPINT_BIT_FROM_GPIO(b, n) (1<<(n-(b<<5))) +#define GPINT_BIT_FROM_INT(b, n) GPINT_BIT_FROM_GPIO(b, n) + +struct gpio_int_regs { + /* R/W1S */ + /* u32 pin_val0; 0x00 */ + /* u32 pin_val1; 0x04 */ + /* u32 pin_val2; 0x08 */ + /* u32 pin_val3; 0x0C */ + u32 pin_val[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 pin_valclr0 0x10 */ + /* u32 pin_valclr1; 0x14 */ + /* u32 pin_valclr2; 0x18 */ + /* u32 pin_valclr3; 0x1C */ + u32 pin_valclr[GPINT_NUM_BANKS]; + + /* R/W1C */ + /* u32 int_pend0; 0x20 */ + /* u32 int_pend1; 0x24 */ + /* u32 int_pend2; 0x28 */ + /* u32 int_pend3; 0x2c */ + u32 int_pend[GPINT_NUM_BANKS]; + + u32 pri_enc; /* 0x30 */ + u32 _resvd0[3]; /* 0x34-0x3c */ + + /* R/W1S */ + /* u32 int_mask0; 0x40 */ + /* u32 int_mask1; 0x44 */ + /* u32 int_mask2; 0x48 */ + /* u32 int_mask3; 0x4c */ + u32 int_mask[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 int_maskclr0; 0x50 */ + /* u32 int_maskclr1; 0x54 */ + /* u32 int_maskclr2; 0x58 */ + /* u32 int_maskclr3; 0x5C */ + u32 int_maskclr[GPINT_NUM_BANKS]; + + /* R/W */ + u32 dma_sel; /* 0x60 */ + u32 _resvd1[(0x80-0x64)/4]; /* 0x64-0x7C */ + + /* W */ + /* u32 dev_sel0; 0x80 */ + /* u32 dev_sel1; 0x84 */ + /* u32 dev_sel2; 0x88 */ + /* u32 dev_sel3; 0x8C */ + u32 dev_sel[GPINT_NUM_BANKS]; + + /* W */ + /* u32 dev_selclr0; 0x90 */ + /* u32 dev_selclr1; 0x94 */ + /* u32 dev_selclr2; 0x98 */ + /* u32 dev_selclr3; 0x9C */ + u32 dev_selclr[GPINT_NUM_BANKS]; + + /* R */ + /* u32 reset_val0; 0xA0 */ + /* u32 reset_val1; 0xA4 */ + /* u32 reset_val2; 0xA8 */ + /* u32 reset_val3; 0xAC */ + u32 reset_val[GPINT_NUM_BANKS]; + + /* 0xB0 - 0xFFC */ + u32 _resvd2[(0x1000-0xB0)/4]; + + /* R/W -- when interrupt mask is clear */ + /* R -- when interrupt mask is set */ + /* u32 gp_int0; 0x1000 */ + /* u32 gp_int1; 0x1004 */ + /* u32 gp_int2; 0x1008 */ + /* u32 gp_int2; 0x100C */ + /* u32 gp_intN; 0x1000 + (N*4) */ + u32 gp_int[GPINT_MAX_INTS]; +}; + +extern struct gpio_int_regs *const gpio_int; + +#define GPINT_DMASEL_DMA0 (0) +#define GPINT_DMASEL_DMA0_N(n) (((n)&0xFF)< + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _MACH_AU1X00_INT_H +#define _MACH_AU1X00_INT_H + +#define NR_IRQS 255 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* _MACH_AU1X00_INT_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/mempool.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/mempool.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/mempool.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/mempool.h 2009-09-16 18:47:00.000000000 -0400 @@ -0,0 +1,77 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef AU_MEMPOOL_H +#define AU_MEMPOOL_H + +#define AU_MEMPOOL_BLOCK_MAJOR 235 + +#define AU_MEMPOOL_IOCTL_ALLOC 5 +#define AU_MEMPOOL_IOCTL_FREE 6 +#define AU_MEMPOOL_IOCTL_PRINT 7 +#define AU_MEMPOOL_IOCTL_SET_CACHEABLE 9 +#define AU_MEMPOOL_IOCTL_SET_NONCACHEABLE 10 + +#define AU_MAX_MEMPOOLS 4 +/* + * A mempool descriptor, used by the driver to track allocations. + * @list: A Linux linked list head. + * @name: The name of the pool using this descriptor; useful for printing. + * @size: The size of this allocation + * @in_use: Set to true if this memory is in use; if false it is available for + * allocation. + * @phys: The physical address of the beginning of the allocation. + */ +struct au_mempool_desc { + struct list_head list; + const char *name; + u32 size; + bool in_use; + void *phys; +}; + +/* + * A mempool region, used by ioctl to pass information between the kernel and user. + * @name: The name of the pool configuring this region. Set by ioctl. + * @phys: The physical address of the allocated memory. Set by ioctl. + * @virt: * A placeholder for the user to store the virtual address if mapped by mmap. + * The ioctl does NOT set this to a useful value; you must mmap the memory if + * it is to be used in user space. + * @size: The size of the region. Set before calling ioctl. + * @desc: A pointer to the descriptor, used by the driver for housekeeping. + */ +struct au_mempool_region { + const char *name; + void *phys; + void *virt; + u32 size; + + void *desc; +}; + +int au_mempool_alloc(int pool, struct au_mempool_region *region); +void au_mempool_free(int pool, struct au_mempool_region *region); + +#endif /* AU_MEMPOOL_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mach-au1x00/prom.h linux-2.6.29/arch/mips/include/asm/mach-au1x00/prom.h --- linux-2.6.29/arch/mips/include/asm/mach-au1x00/prom.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mach-au1x00/prom.h 2009-06-02 19:05:14.000000000 -0400 @@ -9,5 +9,6 @@ extern char *prom_getcmdline(void); extern char *prom_getenv(char *envname); extern int prom_get_ethernet_addr(char *ethernet_addr); +extern int prom_get_wifi_addr(char *ethernet_addr); #endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mips-boards/alchemyboards.h linux-2.6.29/arch/mips/include/asm/mips-boards/alchemyboards.h --- linux-2.6.29/arch/mips/include/asm/mips-boards/alchemyboards.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mips-boards/alchemyboards.h 2009-06-02 09:39:51.000000000 -0400 @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2009 RMI Technologies, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef __ALCHEMY_BOARDS_H__ +#define __ALCHEMY_BOARDS_H__ + +typedef struct { + uint8_t boardName[16]; + int boardMajor; + int boardMinor; + uint8_t ethmac[17]; /* including ':' */ + uint8_t wifimac[17]; + void *private; +} boardInfo_t; + +boardInfo_t *get_au1xxx_board_info(void); + +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mips-boards/db1300.h linux-2.6.29/arch/mips/include/asm/mips-boards/db1300.h --- linux-2.6.29/arch/mips/include/asm/mips-boards/db1300.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mips-boards/db1300.h 2009-09-16 18:47:00.000000000 -0400 @@ -0,0 +1,198 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef ASM_DB1300_H +#define ASM_DB1300_H +#ifdef CONFIG_MIPS_DB1300 +#include +#include + +struct db1300_hex_regs { + u16 hex; /* Write 8-bit value here */ + u16 reserved; + u16 blank; /* Write 11b to blank */ +}; + + +#define DB1300_HEX_REGS_PHYS_ADDR 0x19C00000 + +/* For alchemy/dev_boards/leds.c */ +typedef struct db1300_hex_regs hex_regs; +#define HEX_REGS_KSEG1_ADDR (DB1300_HEX_REGS_PHYS_ADDR + KSEG1) + +struct bcsr_regs { + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; +}; + +#define DB1300_BCSR_REGS_PHYS_ADDR 0x19800000 +#define BCSR_REGS_KSEG1_ADDR (KSEG1 + DB1300_BCSR_REGS_PHYS_ADDR) + +static volatile struct bcsr_regs *const db_bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +#define BCSR_STATUS_SD1_WP (1<<10) +#define BCSR_INT_SD1_INSERT (1<<12) + +#define BCSR_SIG_STAT_HOST_VBUS_OVR (1<<15) +#define BCSR_SIG_STAT_OTG_VBUS_OVR (1<<14) +#define BCSR_SIG_STAT_SD_DETECT (1<<12) +#define BCSR_SIG_STAT_AC97_PEN_IRQ (1<<11) +#define BCSR_SIG_STAT_AC97_IRQ (1<<10) +#define BCSR_SIG_STAT_CF_DETECT (1<<9) +#define BCSR_SIG_STAT_FLASH_BUSY (1<<7) +#define BCSR_SIG_STAT_DC_IRQ (1<<6) +#define BCSR_SIG_STAT_HDMI_IRQ (1<<5) +#define BCSR_SIG_STAT_VIDEO_IRQ (1<<4) +#define BCSR_SIG_STAT_CF_IRQ (1<<2) +#define BCSR_SIG_STAT_ETH_IRQ (1<<1) +#define BCSR_SIG_STAT_IDE_IRQ (1<<0) + +#define BCSR_BRD_STAT_CF_WP (1<<14) + +#define BCSR_RESETS_USB_OTG 0x4000 +#define BCSR_RESETS_USB_HOST 0x8000 + +#define BCSR_CF_RESET 0x8000 +#define BCSR_CF_AUD_EN 0x1000 + +#define BCSR_SYSTEM_SW_RST (1<<15) + +#define CASCADE_IRQ_MIN 129 + +enum db1300_cascade_irqs { + DB1300_IDE_IRQ = CASCADE_IRQ_MIN, + DB1300_ETHERNET_IRQ, + DB1300_CF_IRQ, + DB1300_RESERVED_IRQ, + DB1300_VIDEO_IRQ, + DB1300_HDMI_IRQ, + DB1300_DC_IRQ, + DB1300_FLASH_BUSY_IRQ, + DB1300_CF_INSERT_IRQ, + DB1300_CF_EJECT_IRQ, + DB1300_AC97_IRQ, + DB1300_AC97_PEN_IRQ, + DB1300_SD1_INSERT_IRQ, + DB1300_SD1_EJECT_IRQ, + DB1300_OTG_VBUS_OC_IRQ, + DB1300_HOST_VBUS_OC_IRQ, +}; + +#define CASCADE_IRQ_MAX DB1300_HOST_VBUS_OC_IRQ + +#define CASCADE_IRQ (5 + GPINT_LINUX_IRQ_OFFSET) +#define CASCADE_IRQ_TYPE_STRING "DB1300 Cascade" + +/* + * Defines for au1xxx-ide + * See the CPLD/BCSR datasheet for details + */ +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_INT DB1300_IDE_IRQ +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) + +/* + * Mempool definitions + */ + +/* + * 24 MB is enough for 4 double-buffered overlays at 800x480@32bpp + */ +#define MEMPOOL_LCD_START (24 * MB) +#define MEMPOOL_LCD_SIZE (40 * MB) + +#define MEMPOOL_BSA_START (MEMPOOL_LCD_START + MEMPOOL_LCD_SIZE) +#define MEMPOOL_BSA_SIZE (64 * MB) + +/* + * MPE needs to start at the 128 MB boundary in case we want to tile it. + */ +#define MEMPOOL_MPE_START (MEMPOOL_BSA_START + MEMPOOL_BSA_SIZE) +#define MEMPOOL_MPE_SIZE (32 * MB) + +#define MEMPOOL_OGL_START (MEMPOOL_MPE_START + MEMPOOL_MPE_SIZE) +#define MEMPOOL_OGL_SIZE (64 * MB) + +/* + * Defines for CF/PCMCIA + */ +#define PCMCIA_NUM_SOCKS 1 +#define BCSR_PCMCIA_PC0VPP 0 +#define BCSR_PCMCIA_PC0VCC 0 +#define BCSR_PCMCIA_PC0DRVEN BCSR_CF_AUD_EN +#define BCSR_PCMCIA_PC0RST BCSR_CF_RESET +#define BCSR_PCMCIA_PC1VPP 0 +#define BCSR_PCMCIA_PC1VCC 0 +#define BCSR_PCMCIA_PC1DRVEN 0 +#define BCSR_PCMCIA_PC1RST 0 + +#define SET_VCC_VPP(VCC, VPP, SLOT) 0 + +/* + * PSC Physical Addresses + */ +#define PSC_SATURN_PHYS_ADDR 0x10A00000 +#define PSC_AC97_PHYS_ADDR 0x10A01000 +#define PSC_I2S_PHYS_ADDR 0x10A02000 +#define PSC_SMBUS_PHYS_ADDR 0x10A03000 + +#endif /* CONFIG_MIPS_DB1300 */ +#endif /* ASM_DB1300_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mips-boards/hmp10.h linux-2.6.29/arch/mips/include/asm/mips-boards/hmp10.h --- linux-2.6.29/arch/mips/include/asm/mips-boards/hmp10.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/arch/mips/include/asm/mips-boards/hmp10.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,15 @@ +#ifndef __ASM_HMP10_H +#define __ASM_HMP10_H + +#include +#include + +/* HMP10 IRQ assignments */ +#define HMP10_ETH_IRQ AU1000_GPIO_12 +#define AU1XXX_SMC9210_IRQ HMP10_ETH_IRQ +#define AU1XXX_SMC9210_PHYS_ADDR 0x19000000 + +#define NAND_CS 0 + +#endif + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/mipsregs.h linux-2.6.29/arch/mips/include/asm/mipsregs.h --- linux-2.6.29/arch/mips/include/asm/mipsregs.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/mipsregs.h 2009-05-29 11:43:37.000000000 -0400 @@ -717,8 +717,8 @@ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ else \ @@ -726,8 +726,8 @@ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source ", " #sel "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ local_irq_restore(__flags); \ @@ -1391,11 +1391,11 @@ static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ \ return res; \ } \ @@ -1403,24 +1403,24 @@ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int val) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ \ return res; \ } @@ -1484,14 +1484,15 @@ set_c0_##name(unsigned int set) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ local_irq_save(flags); \ omt = __dmt(); \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ @@ -1502,14 +1503,15 @@ clear_c0_##name(unsigned int clear) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ local_irq_save(flags); \ omt = __dmt(); \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ @@ -1517,9 +1519,10 @@ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int newbits) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ @@ -1527,9 +1530,9 @@ \ omt = __dmt(); \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (newbits & change); \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/sn/nmi.h linux-2.6.29/arch/mips/include/asm/sn/nmi.h --- linux-2.6.29/arch/mips/include/asm/sn/nmi.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/sn/nmi.h 2009-05-29 11:43:37.000000000 -0400 @@ -3,13 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * + * Derived from IRIX , Revision 1.5. + * * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. */ #ifndef __ASM_SN_NMI_H #define __ASM_SN_NMI_H -#ident "$Revision: 1.5 $" - #include /* diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/spinlock.h linux-2.6.29/arch/mips/include/asm/spinlock.h --- linux-2.6.29/arch/mips/include/asm/spinlock.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/spinlock.h 2009-05-29 11:43:37.000000000 -0400 @@ -76,7 +76,7 @@ "2: \n" " .subsection 2 \n" "4: andi %[ticket], %[ticket], 0x1fff \n" - "5: sll %[ticket], 5 \n" + " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" @@ -85,7 +85,7 @@ " andi %[ticket], %[ticket], 0x1fff \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" - " b 5b \n" + " b 4b \n" " subu %[ticket], %[ticket], 1 \n" " .previous \n" " .set pop \n" @@ -113,7 +113,7 @@ " ll %[ticket], %[ticket_ptr] \n" " \n" "4: andi %[ticket], %[ticket], 0x1fff \n" - "5: sll %[ticket], 5 \n" + " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" @@ -122,7 +122,7 @@ " andi %[ticket], %[ticket], 0x1fff \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" - " b 5b \n" + " b 4b \n" " subu %[ticket], %[ticket], 1 \n" " .previous \n" " .set pop \n" diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/time.h linux-2.6.29/arch/mips/include/asm/time.h --- linux-2.6.29/arch/mips/include/asm/time.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/time.h 2009-09-02 10:43:51.000000000 -0400 @@ -29,6 +29,9 @@ */ extern int rtc_mips_set_time(unsigned long); extern int rtc_mips_set_mmss(unsigned long); +struct timespec; +extern void save_time_delta(struct timespec *delta, struct timespec *rtc); +extern void restore_time_delta(struct timespec *delta, struct timespec *rtc); /* * board specific routines required by time_init(). @@ -57,7 +60,11 @@ static inline int mips_clockevent_init(void) { -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_MIPS_MT_SMTC + extern int smtc_clockevent_init(void); + + return smtc_clockevent_init(); +#elif defined(CONFIG_CEVT_R4K) return r4k_clockevent_init(); #else return -ENXIO; diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/include/asm/uaccess.h linux-2.6.29/arch/mips/include/asm/uaccess.h --- linux-2.6.29/arch/mips/include/asm/uaccess.h 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/include/asm/uaccess.h 2009-05-29 11:43:37.000000000 -0400 @@ -104,11 +104,21 @@ #define __access_mask get_fs().seg -#define __access_ok(addr, size, mask) \ - (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) +#define __access_ok(addr, size, mask) \ +({ \ + const volatile void __user *__up = addr; \ + unsigned long __addr = (unsigned long) __up; \ + unsigned long __size = size; \ + unsigned long __mask = mask; \ + unsigned long __ok; \ + \ + __ok = (signed long)(__mask & (__addr | (__addr + __size) | \ + __ua_size(__size))); \ + __ok == 0; \ +}) #define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size), __access_mask)) + likely(__access_ok((addr), (size), __access_mask)) /* * put_user: - Write a simple value into user space. diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/Kconfig linux-2.6.29/arch/mips/Kconfig --- linux-2.6.29/arch/mips/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/Kconfig 2009-08-21 19:14:45.000000000 -0400 @@ -21,6 +21,8 @@ config MACH_ALCHEMY bool "Alchemy processor based machines" + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_HIGHMEM config BASLER_EXCITE bool "Basler eXcite smart camera" @@ -1968,10 +1970,6 @@ endmenu -config RWSEM_GENERIC_SPINLOCK - bool - default y - config LOCKDEP_SUPPORT bool default y diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/cevt-smtc.c linux-2.6.29/arch/mips/kernel/cevt-smtc.c --- linux-2.6.29/arch/mips/kernel/cevt-smtc.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/cevt-smtc.c 2009-05-29 11:43:37.000000000 -0400 @@ -245,7 +245,7 @@ } -int __cpuinit mips_clockevent_init(void) +int __cpuinit smtc_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/cpu-probe.c linux-2.6.29/arch/mips/kernel/cpu-probe.c --- linux-2.6.29/arch/mips/kernel/cpu-probe.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/cpu-probe.c 2009-06-01 21:03:00.000000000 -0400 @@ -190,6 +190,7 @@ case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -820,6 +821,20 @@ } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_AU13XX; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI Core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -937,6 +952,11 @@ case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; + default: + c->cputype = CPU_UNKNOWN; } BUG_ON(!__cpu_name[cpu]); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/linux32.c linux-2.6.29/arch/mips/kernel/linux32.c --- linux-2.6.29/arch/mips/kernel/linux32.c 2009-09-21 11:21:45.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/linux32.c 2009-05-29 11:43:37.000000000 -0400 @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/scall64-n32.S linux-2.6.29/arch/mips/kernel/scall64-n32.S --- linux-2.6.29/arch/mips/kernel/scall64-n32.S 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/scall64-n32.S 2009-05-29 11:43:37.000000000 -0400 @@ -405,8 +405,8 @@ PTR sys_eventfd PTR sys_fallocate PTR sys_timerfd_create - PTR sys_timerfd_gettime /* 5285 */ - PTR sys_timerfd_settime + PTR compat_sys_timerfd_gettime /* 5285 */ + PTR compat_sys_timerfd_settime PTR sys_signalfd4 PTR sys_eventfd2 PTR sys_epoll_create1 diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/scall64-o32.S linux-2.6.29/arch/mips/kernel/scall64-o32.S --- linux-2.6.29/arch/mips/kernel/scall64-o32.S 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/scall64-o32.S 2009-05-29 11:43:37.000000000 -0400 @@ -525,8 +525,8 @@ PTR sys_eventfd PTR sys32_fallocate /* 4320 */ PTR sys_timerfd_create - PTR sys_timerfd_gettime - PTR sys_timerfd_settime + PTR compat_sys_timerfd_gettime + PTR compat_sys_timerfd_settime PTR compat_sys_signalfd4 PTR sys_eventfd2 /* 4325 */ PTR sys_epoll_create1 diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/time.c linux-2.6.29/arch/mips/kernel/time.c --- linux-2.6.29/arch/mips/kernel/time.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/time.c 2009-09-02 10:43:51.000000000 -0400 @@ -49,6 +49,40 @@ return rtc_mips_set_mmss(now.tv_sec); } + +/** + * save_time_delta - Save the offset between system time and RTC time + * @delta: pointer to timespec to store delta + * @rtc: pointer to timespec for current RTC time + * + * Return a delta between the system time and the RTC time, such + * that system time can be restored later with restore_time_delta() + */ +void save_time_delta(struct timespec *delta, struct timespec *rtc) +{ + set_normalized_timespec(delta, + xtime.tv_sec - rtc->tv_sec, + xtime.tv_nsec - rtc->tv_nsec); +} +EXPORT_SYMBOL(save_time_delta); + +/** + * restore_time_delta - Restore the current system time + * @delta: delta returned by save_time_delta() + * @rtc: pointer to timespec for current RTC time + */ +void restore_time_delta(struct timespec *delta, struct timespec *rtc) +{ + struct timespec ts; + + set_normalized_timespec(&ts, + delta->tv_sec + rtc->tv_sec, + delta->tv_nsec + rtc->tv_nsec); + + do_settimeofday(&ts); +} +EXPORT_SYMBOL(restore_time_delta); + static int null_perf_irq(void) { return 0; diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/traps.c linux-2.6.29/arch/mips/kernel/traps.c --- linux-2.6.29/arch/mips/kernel/traps.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/traps.c 2009-05-29 11:43:37.000000000 -0400 @@ -1520,7 +1520,9 @@ #endif /* CONFIG_MIPS_MT_SMTC */ if (cpu_has_veic || cpu_has_vint) { + unsigned long sr = set_c0_status(ST0_BEV); write_c0_ebase(ebase); + write_c0_status(sr); /* Setting vector spacing enables EI/VI mode */ change_c0_intctl(0x3e0, VECTORSPACING); } @@ -1602,8 +1604,6 @@ #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif - if (cpu_has_mips_r2) - uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1635,9 +1635,11 @@ return; /* Already done */ #endif - if (cpu_has_veic || cpu_has_vint) - ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else { + if (cpu_has_veic || cpu_has_vint) { + unsigned long size = 0x200 + VECTORSPACING*64; + ebase = (unsigned long) + __alloc_bootmem(size, 1 << fls(size), 0); + } else { ebase = CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/kernel/unaligned.c linux-2.6.29/arch/mips/kernel/unaligned.c --- linux-2.6.29/arch/mips/kernel/unaligned.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/kernel/unaligned.c 2009-05-29 11:43:37.000000000 -0400 @@ -482,19 +482,19 @@ return; die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGSEGV, current, 1); + force_sig(SIGSEGV, current); return; sigbus: die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGBUS, current, 1); + force_sig(SIGBUS, current); return; sigill: die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); - send_sig(SIGILL, current, 1); + force_sig(SIGILL, current); } asmlinkage void do_ade(struct pt_regs *regs) diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/Makefile linux-2.6.29/arch/mips/Makefile --- linux-2.6.29/arch/mips/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/Makefile 2009-08-21 19:14:45.000000000 -0400 @@ -14,8 +14,6 @@ KBUILD_DEFCONFIG := ip22_defconfig -cflags-y := -ffunction-sections - # # Select the object file format to substitute into the linker script. # @@ -50,6 +48,8 @@ endif endif +cflags-y := -ffunction-sections + ifdef CONFIG_32BIT ld-emul = $(32bit-emul) vmlinux-32 = vmlinux @@ -255,6 +255,19 @@ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# RMI Alchemy DBAu1300 development board +# +core-$(CONFIG_MIPS_DB1300) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + +# +# RMI Alchemy HMP10 board +# +core-$(CONFIG_MIPS_HMP10) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_HMP10) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_HMP10) += 0xffffffff80100000 + # # AMD Alchemy Bosporus eval board # @@ -472,12 +485,12 @@ # Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys # ifdef CONFIG_SGI_IP28 - ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n) - $(error gcc doesn't support needed option -mr10k-cache-barrier=1) + ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n) + $(error gcc doesn't support needed option -mr10k-cache-barrier=store) endif endif core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ -cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -I$(srctree)/arch/mips/include/asm/mach-ip28 +cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28 load-$(CONFIG_SGI_IP28) += 0xa800000020004000 # diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/mm/c-r4k.c linux-2.6.29/arch/mips/mm/c-r4k.c --- linux-2.6.29/arch/mips/mm/c-r4k.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/mm/c-r4k.c 2009-06-01 11:32:02.000000000 -0400 @@ -780,7 +780,7 @@ c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: @@ -1033,6 +1033,7 @@ case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } @@ -1047,7 +1048,7 @@ printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, - cpu_has_vtag_icache ? "VIVT" : "VIPT", + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", way_string[c->icache.ways], c->icache.linesz); printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/mm/dma-default.c linux-2.6.29/arch/mips/mm/dma-default.c --- linux-2.6.29/arch/mips/mm/dma-default.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/mm/dma-default.c 2009-08-17 09:11:44.000000000 -0400 @@ -178,6 +178,7 @@ EXPORT_SYMBOL(dma_unmap_single); +#ifndef CONFIG_MACH_ALCHEMY int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction) { @@ -197,6 +198,22 @@ return nents; } +#else +int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + int i; + + BUG_ON(direction == DMA_NONE); + + for (i = 0; i < nents; i++, sg++) { + sg->dma_address = dma_map_page(dev, sg_page(sg), sg->offset, + sg->length, direction); + } + + return nents; +} +#endif EXPORT_SYMBOL(dma_map_sg); @@ -225,7 +242,7 @@ if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { unsigned long addr; - addr = plat_dma_addr_to_phys(dma_address); + addr = dma_addr_to_virt(dma_address); dma_cache_wback_inv(addr, size); } diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/mm/highmem.c linux-2.6.29/arch/mips/mm/highmem.c --- linux-2.6.29/arch/mips/mm/highmem.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/mm/highmem.c 2009-08-17 09:11:44.000000000 -0400 @@ -1,7 +1,12 @@ #include #include +#include #include +static pte_t *kmap_pte; + +unsigned long highstart_pfn, highend_pfn; + void *__kmap(struct page *page) { void *addr; @@ -14,6 +19,7 @@ return addr; } +EXPORT_SYMBOL(__kmap); void __kunmap(struct page *page) { @@ -23,6 +29,7 @@ return; kunmap_high(page); } +EXPORT_SYMBOL(__kunmap); /* * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because @@ -49,11 +56,12 @@ if (!pte_none(*(kmap_pte-idx))) BUG(); #endif - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); + set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL)); local_flush_tlb_one((unsigned long)vaddr); return (void*) vaddr; } +EXPORT_SYMBOL(__kmap_atomic); void __kunmap_atomic(void *kvaddr, enum km_type type) { @@ -79,6 +87,7 @@ pagefault_enable(); } +EXPORT_SYMBOL(__kunmap_atomic); /* * This is the same as kmap_atomic() but can map memory that doesn't @@ -93,7 +102,7 @@ idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); + set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL)); flush_tlb_one(vaddr); return (void*) vaddr; @@ -112,7 +121,20 @@ return pte_page(*pte); } -EXPORT_SYMBOL(__kmap); -EXPORT_SYMBOL(__kunmap); -EXPORT_SYMBOL(__kmap_atomic); -EXPORT_SYMBOL(__kunmap_atomic); +#ifdef CONFIG_MACH_ALCHEMY +unsigned long kmap_atomic_phys(void *kvaddr) +{ + return (page_to_phys(kmap_atomic_to_page(kvaddr)) + ((unsigned long)kvaddr & (PAGE_SIZE-1))); +} + +EXPORT_SYMBOL(kmap_atomic_phys); +#endif + +void __init kmap_init(void) +{ + unsigned long kmap_vstart; + + /* cache the first kmap pte */ + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/mm/init.c linux-2.6.29/arch/mips/mm/init.c --- linux-2.6.29/arch/mips/mm/init.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/mm/init.c 2009-05-29 11:43:37.000000000 -0400 @@ -104,14 +104,6 @@ return 1UL << order; } -/* - * These are almost like kmap_atomic / kunmap_atmic except they take an - * additional address argument as the hint. - */ - -#define kmap_get_fixmap_pte(vaddr) \ - pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) - #ifdef CONFIG_MIPS_MT_SMTC static pte_t *kmap_coherent_pte; static void __init kmap_coherent_init(void) @@ -264,24 +256,6 @@ } } -#ifdef CONFIG_HIGHMEM -unsigned long highstart_pfn, highend_pfn; - -pte_t *kmap_pte; -pgprot_t kmap_prot; - -static void __init kmap_init(void) -{ - unsigned long kmap_vstart; - - /* cache the first kmap pte */ - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); - kmap_pte = kmap_get_fixmap_pte(kmap_vstart); - - kmap_prot = PAGE_KERNEL; -} -#endif /* CONFIG_HIGHMEM */ - void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/mm/tlbex.c linux-2.6.29/arch/mips/mm/tlbex.c --- linux-2.6.29/arch/mips/mm/tlbex.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/mm/tlbex.c 2009-06-01 11:32:02.000000000 -0400 @@ -299,6 +299,7 @@ case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: case CPU_PR4450: uasm_i_nop(p); tlbw(p); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/pmc-sierra/Kconfig linux-2.6.29/arch/mips/pmc-sierra/Kconfig --- linux-2.6.29/arch/mips/pmc-sierra/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/pmc-sierra/Kconfig 2009-05-29 11:43:37.000000000 -0400 @@ -36,18 +36,6 @@ endchoice -menu "Options for PMC-Sierra MSP chipsets" - depends on PMC_MSP - -config PMC_MSP_EMBEDDED_ROOTFS - bool "Root filesystem embedded in kernel image" - select MTD - select MTD_BLOCK - select MTD_PMC_MSP_RAMROOT - select MTD_RAM - -endmenu - config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_prom.c linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_prom.c --- linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_prom.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_prom.c 2009-05-29 11:43:37.000000000 -0400 @@ -40,12 +40,6 @@ #include #include #include -#ifdef CONFIG_CRAMFS -#include -#endif -#ifdef CONFIG_SQUASHFS -#include -#endif #include #include @@ -435,10 +429,6 @@ char *str; unsigned int memsize; unsigned int heaptop; -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT - void *ramroot_start; - unsigned long ramroot_size; -#endif int i; str = prom_getenv(memsz_env); @@ -506,19 +496,7 @@ i++; /* 3 */ mdesc[i].type = BOOT_MEM_RESERVED; mdesc[i].base = CPHYSADDR((u32)_text); -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT - if (get_ramroot(&ramroot_start, &ramroot_size)) { - /* - * Rootfs in RAM -- follows kernel - * Combine rootfs image with kernel block so a - * page (4k) isn't wasted between memory blocks - */ - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( - (u32)ramroot_start + ramroot_size)) - mdesc[i].base; - } else -#endif - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( - (u32)_end)) - mdesc[i].base; + mdesc[i].size = CPHYSADDR(PAGE_ALIGN((u32)_end)) - mdesc[i].base; /* Remainder of RAM -- under memsize */ i++; /* 5 */ @@ -528,39 +506,3 @@ return &mdesc[0]; } - -/* rootfs functions */ -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT -bool get_ramroot(void **start, unsigned long *size) -{ - extern char _end[]; - - /* Check for start following the end of the kernel */ - void *check_start = (void *)_end; - - /* Check for supported rootfs types */ -#ifdef CONFIG_CRAMFS - if (*(__u32 *)check_start == CRAMFS_MAGIC) { - /* Get CRAMFS size */ - *start = check_start; - *size = PAGE_ALIGN(((struct cramfs_super *) - check_start)->size); - - return true; - } -#endif -#ifdef CONFIG_SQUASHFS - if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) { - /* Get SQUASHFS size */ - *start = check_start; - *size = PAGE_ALIGN(((struct squashfs_super_block *) - check_start)->bytes_used); - - return true; - } -#endif - - return false; -} -EXPORT_SYMBOL(get_ramroot); -#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_setup.c --- linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2009-05-29 11:43:37.000000000 -0400 @@ -21,7 +21,6 @@ #if defined(CONFIG_PMC_MSP7120_GW) #include -#include #define MSP_BOARD_RESET_GPIO 9 #endif @@ -88,11 +87,8 @@ * as GPIO char driver may not be enabled and it would look up * data inRAM! */ - set_value_reg32(GPIO_CFG3_REG, - basic_mode_mask(MSP_BOARD_RESET_GPIO), - basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO)); - set_reg32(GPIO_DATA3_REG, - basic_data_mask(MSP_BOARD_RESET_GPIO)); + set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000); + set_reg32(GPIO_DATA3_REG, 8); /* * In case GPIO9 doesn't reset the board (jumper configurable!) diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_time.c linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_time.c --- linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_time.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/pmc-sierra/msp71xx/msp_time.c 2009-05-29 11:43:37.000000000 -0400 @@ -81,10 +81,7 @@ mips_hpt_frequency = cpu_rate/2; } -void __init plat_timer_setup(struct irqaction *irq) +unsigned int __init get_c0_compare_int(void) { -#ifdef CONFIG_IRQ_MSP_CIC - /* we are using the vpe0 counter for timer interrupts */ - setup_irq(MSP_INT_VPE0_TIMER, irq); -#endif + return MSP_INT_VPE0_TIMER; } diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/sibyte/bcm1480/irq.c linux-2.6.29/arch/mips/sibyte/bcm1480/irq.c --- linux-2.6.29/arch/mips/sibyte/bcm1480/irq.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/sibyte/bcm1480/irq.c 2009-05-29 11:43:37.000000000 -0400 @@ -113,7 +113,6 @@ { int i = 0, old_cpu, cpu, int_on, k; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; unsigned int irq_dirty; @@ -127,8 +126,7 @@ cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&bcm1480_imr_lock); + spin_lock_irqsave(&bcm1480_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = bcm1480_irq_owner[irq]; @@ -153,8 +151,7 @@ ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); } } - spin_unlock(&bcm1480_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); } #endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/sibyte/sb1250/irq.c linux-2.6.29/arch/mips/sibyte/sb1250/irq.c --- linux-2.6.29/arch/mips/sibyte/sb1250/irq.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/sibyte/sb1250/irq.c 2009-05-29 11:43:37.000000000 -0400 @@ -107,7 +107,6 @@ { int i = 0, old_cpu, cpu, int_on; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; i = cpumask_first(mask); @@ -121,8 +120,7 @@ cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&sb1250_imr_lock); + spin_lock_irqsave(&sb1250_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; @@ -144,8 +142,7 @@ ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); } - spin_unlock(&sb1250_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/arch/mips/txx9/rbtx4939/setup.c linux-2.6.29/arch/mips/txx9/rbtx4939/setup.c --- linux-2.6.29/arch/mips/txx9/rbtx4939/setup.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/arch/mips/txx9/rbtx4939/setup.c 2009-05-29 11:43:37.000000000 -0400 @@ -375,7 +375,7 @@ } struct txx9_board_vec rbtx4939_vec __initdata = { - .system = "Tothiba RBTX4939", + .system = "Toshiba RBTX4939", .prom_init = rbtx4939_prom_init, .mem_setup = rbtx4939_setup, .irq_setup = rbtx4939_irq_setup, diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/CHANGELOG.ALCHEMY linux-2.6.29/CHANGELOG.ALCHEMY --- linux-2.6.29/CHANGELOG.ALCHEMY 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/CHANGELOG.ALCHEMY 2009-09-02 10:43:51.000000000 -0400 @@ -0,0 +1,96 @@ +RMI Release Changelog: +2.6.29.4-rmi-126 08.26.2009 + +DB1300: More defconfig updates +ALL: Mempool updates including cacheable memory +ALL: Updated release_me.sh to reflect new versioning scheme .4-rmi. +ALL: Move MB and KB macros to a common header to avoid repetition +HMP10: Remove MB/KB macros. +HMP10: Enable DOS/VFAT modules. +ALL: Restore mempool sanity +DB1300: Increase LCD mempool for 1440x900 +DB1300: Fixes to the BSA driver that prevent playback hangs +ALL: Get MAC address from ROM, not random address +-------------------------------------------------------------------------------- +2.6.29-RMI-113 08.21.2009 + +DB1300: Update mempool sizes, locations and names +DB1300: Updated MAE drivers +DB1300: Restore mempool print on alloc/dealloc +DB1300: Enable panning and sync (double-buffering) in au1200fb +ALL: Change the export dir in release_me to make OpenEmbedded happy +DB1300: More prints in mempool.c to unhang video +-------------------------------------------------------------------------------- +2.6.29-RMI-81 07.09.2009 + +DB1300: Fix compiling USB without PM +DB1300: Fix spurious interrupts +DB1300: Save/restore the DMA select and GPIO states during suspend/resume +DB1300: Support CompactFlash +ALL: Fix for MMC resume. +HMP10: Added SMSC driver platform data. +HMP10: Enabling smsc91xx network driver. +DB1300: Added cause to spurious int printout +DB1300: Enable and debug I2C/SMBUS +DB1300: Enable I2S and fix a bug in the WM8731 codec +ALL: Removed some unneeded saves and restores during suspend +DB1300: Add OHCI support +-------------------------------------------------------------------------------- +2.6.29-RMI-67 06.30.2009 + +ALL: Mempool free on close +DB1300: Make mempool a platform_device (au-mempool) +DB1300: Corrected Makefile that was breaking the build +DB1300: Changed the order of operations to improve suspend stability +DB1300: Save and restore board (CPLD) registers +DB1300: Change to community SMSC9210 driver +DB1300: Reset MMC controller at startup +DB1300: Correct hard-coded boot line addition +DB1300: Fix touchscreen suspend/resume +DB1300: Defconfig update enabling power management by default +DB1300: Change defconfig to use community SMSC9210 driver +-------------------------------------------------------------------------------- +2.6.29-RMI-51 06.22.2009 + +HMP10: Added SMSC9210 Support +HMP10: Enable SCSI and USB Host Support +HMP10: Added Sound Support +HMP10: Added MMC Support. +DB1300: Initial AU13XX/DB1300 support +DB1300: New Au1300 interrupt controller +DB1300: UART support +DB1300: Peripheral resource declarations for USB, LCD, IDE and MMC +DB1300: Correct memory map and mempool support +DB1300: LCD Framebuffer support +DB1300: Removed db1300-specific init functions from LCD controller +ALL: Added RMI Alchemy logo, available for all Alchemy boards +DB1300: Initial DB1300 defcofnig file +DB1300: Add MMC/SD support for SD1 (slot) +DB1300: Enable basic idle power management +DB1300: Enable USB EHCI (2.0) +DB1300: Enable SMSC9210 Ethernet controller +ALL: Add a sysfs entry for Board. +ALL: Get wifi mac address from PROM +HMP10: Get Wifi MAC Address from EEPROM. +DB1300: Added more GPIO and IRQ configs +DB1300: Suppress some spurious interrupts +DB1300: Blink dots on timer ticks; one update per second +DB1300: AC97 audio and touchscreen support +DB1300: Added a button to the WM97XX touch driver +DB1300: Added VSS (power island) support. +DB1300: Media Acceleration Engine (MAE) drivers +DB1300: IDE support including MWDMA +DB1300: SD performance improvement +DB1300: Support rebooting +DB1300: Support board power off at shutdown +DB1300: Add a constant needed for reset. +DB1300: Basic suspend/resume support +DB1300: DBDMA suspend/resume support for Au1300 +DB1300: USB EHCI suspend/resume support +DB1300: Corrected sleep sequence +DB1300: Correctly support both backlight controls +DB1300: LCD driver build with CONFIG_PM and blanking +ALL: Change au1200fb to a platform_driver +ALL: au1200fb code cleanup for whitespace and types +DB1300: Suspend/resume implementation for au1200fb +-------------------------------------------------------------------------------- diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/i2c/busses/i2c-au1550.c linux-2.6.29/drivers/i2c/busses/i2c-au1550.c --- linux-2.6.29/drivers/i2c/busses/i2c-au1550.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/i2c/busses/i2c-au1550.c 2009-07-08 21:12:49.000000000 -0400 @@ -350,7 +350,7 @@ do { stat = sp->psc_smbstat; au_sync(); - } while ((stat & PSC_SMBSTAT_SR) == 0); + } while ((stat & PSC_SMBSTAT_DR) == 0); sp->psc_ctrl = PSC_CTRL_SUSPEND; au_sync(); @@ -397,7 +397,7 @@ } priv->psc_base = CKSEG1ADDR(r->start); - priv->xfer_timeout = 200; + priv->xfer_timeout = 2000; priv->ack_timeout = 200; priv->adap.nr = pdev->id; diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/i2c/busses/Kconfig linux-2.6.29/drivers/i2c/busses/Kconfig --- linux-2.6.29/drivers/i2c/busses/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/i2c/busses/Kconfig 2009-07-08 21:12:49.000000000 -0400 @@ -276,7 +276,7 @@ config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on SOC_AU1550 || SOC_AU1200 || SOC_AU13XX help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface. diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/ide/au1xxx-ide.c linux-2.6.29/drivers/ide/au1xxx-ide.c --- linux-2.6.29/drivers/ide/au1xxx-ide.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/ide/au1xxx-ide.c 2009-08-17 09:11:44.000000000 -0400 @@ -50,14 +50,22 @@ #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) +#ifdef CONFIG_HIGHMEM +#define AUIDE_GETPHYS_ADDR(addr) (void*) kmap_atomic_phys(addr) +#else +#define AUIDE_GETPHYS_ADDR(addr) (void*) virt_to_phys(addr) +#endif + void auide_insw(unsigned long port, void *addr, u32 count) { _auide_hwif *ahwif = &auide_hwif; chan_tab_t *ctp; au1x_ddma_desc_t *dp; + u32 flags = DDMA_FLAGS_NOIE | DDMA_FLAGS_PHYSADDR; + - if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, - DDMA_FLAGS_NOIE)) { + if(!put_dest_flags(ahwif->rx_chan, AUIDE_GETPHYS_ADDR(addr), count << 1, + flags)) { printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); return; } @@ -73,9 +81,11 @@ _auide_hwif *ahwif = &auide_hwif; chan_tab_t *ctp; au1x_ddma_desc_t *dp; + u32 flags = DDMA_FLAGS_NOIE | DDMA_FLAGS_PHYSADDR; - if(!put_source_flags(ahwif->tx_chan, (void*)addr, - count << 1, DDMA_FLAGS_NOIE)) { + + if(!put_source_flags(ahwif->tx_chan, AUIDE_GETPHYS_ADDR(addr), + count << 1, flags)) { printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); return; } @@ -101,6 +111,7 @@ static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) { +#ifndef CONFIG_MIPS_DB1300 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); /* set pio mode! */ @@ -159,10 +170,12 @@ au_writel(mem_sttime,MEM_STTIME2); au_writel(mem_stcfg,MEM_STCFG2); +#endif } static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) { +#ifndef CONFIG_MIPS_DB1300 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); switch(speed) { @@ -202,6 +215,7 @@ au_writel(mem_sttime,MEM_STTIME2); au_writel(mem_stcfg,MEM_STCFG2); +#endif } /* @@ -236,7 +250,7 @@ cur_len = sg_dma_len(sg); while (cur_len) { - u32 flags = DDMA_FLAGS_NOIE; + u32 flags = DDMA_FLAGS_PHYSADDR ; unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; if (++count >= PRD_ENTRIES) { @@ -247,13 +261,13 @@ /* Lets enable intr for the last descriptor only */ if (1==i) - flags = DDMA_FLAGS_IE; + flags |= DDMA_FLAGS_IE; else - flags = DDMA_FLAGS_NOIE; + flags |= DDMA_FLAGS_NOIE; if (iswrite) { if(!put_source_flags(ahwif->tx_chan, - (void*) sg_virt(sg), + (void*) sg_phys(sg), tc, flags)) { printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); @@ -261,7 +275,7 @@ } else { if(!put_dest_flags(ahwif->rx_chan, - (void*) sg_virt(sg), + (void*) sg_phys(sg), tc, flags)) { printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/ide/Kconfig linux-2.6.29/drivers/ide/Kconfig --- linux-2.6.29/drivers/ide/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/ide/Kconfig 2009-06-03 11:18:15.000000000 -0400 @@ -697,18 +697,18 @@ config BLK_DEV_IDE_AU1XXX bool "IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 + depends on SOC_AU1200 || SOC_AU13XX choice prompt "IDE Mode for AMD Alchemy Au1200" default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on (SOC_AU1200 || SOC_AU13XX) && BLK_DEV_IDE_AU1XXX config BLK_DEV_IDE_AU1XXX_PIO_DBDMA bool "PIO+DbDMA IDE for AMD Alchemy Au1200" config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on (SOC_AU1200 || SOC_AU13XX) && BLK_DEV_IDE_AU1XXX endchoice config BLK_DEV_IDE_TX4938 diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/input/keyboard/hmp10_keys.c linux-2.6.29/drivers/input/keyboard/hmp10_keys.c --- linux-2.6.29/drivers/input/keyboard/hmp10_keys.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/input/keyboard/hmp10_keys.c 2009-08-21 19:15:16.000000000 -0400 @@ -0,0 +1,193 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct hmp10_key { + int irq; + int key; + int gpio; +}; + +static struct hmp10_key hmp_keys[] = { + {AU1200_GPIO_202, KEY_S, 202}, /* MENU */ + {AU1200_GPIO_203, KEY_ESC, 203}, /* EXIT */ + {AU1200_GPIO_205, KEY_B, 205}, /* BACK */ + {AU1200_GPIO_206, KEY_P, 206}, /* PLAY */ + {AU1200_GPIO_207, KEY_F, 207}, /* FORWARD */ +}; + +struct hmp10_kp { + struct input_dev *input; +}; + +static irqreturn_t hmp10_keys_interrupt(int irq, void *dev_id) +{ + struct hmp10_kp *hmp10_kp = (struct hmp10_kp *)dev_id; + int i; + + for (i = 0; i < ARRAY_SIZE(hmp_keys); ++i) + { + if (hmp_keys[i].irq == irq) { + input_report_key(hmp10_kp->input, hmp_keys[i].key, + !au1xxx_gpio_get_value(hmp_keys[i].gpio)); + break; + } + } + + return IRQ_HANDLED; +} + +static void free_irqs(struct hmp10_kp *hmp10_kp) +{ + int i; + for (i = 0; i < ARRAY_SIZE(hmp_keys); ++i) + { + printk("Freeing irq %d\n", hmp_keys[i].irq); + free_irq(hmp_keys[i].irq, hmp10_kp); + } +} + + +static int __init hmp10_keys_probe(struct platform_device *pdev) +{ + struct hmp10_kp *hmp10_kp; + struct input_dev *input_dev; + int ret; + int i; + + hmp10_kp = kzalloc(sizeof(struct hmp10_kp), GFP_KERNEL); + input_dev = input_allocate_device(); + if (!hmp10_kp || !input_dev) { + kfree(hmp10_kp); + input_free_device(input_dev); + printk(KERN_ERR + "Failed to allocate input device or keys object\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, hmp10_kp); + + hmp10_kp->input = input_dev; + + __set_bit(EV_KEY, input_dev->evbit); + for (i = 0; i < ARRAY_SIZE(hmp_keys); ++i) + { + __set_bit(hmp_keys[i].key & KEY_MAX, input_dev->keybit); + } + + input_dev->name = "hmp10-keys"; + input_dev->phys = "hmp10-keys/input0"; + input_dev->dev.parent = &pdev->dev; + + input_dev->id.bustype = BUS_HOST; + input_dev->id.vendor = 0x0001; + input_dev->id.product = 0x0001; + input_dev->id.version = 0x0100; + + ret = input_register_device(hmp10_kp->input); + if (ret < 0) { + printk(KERN_ERR "Unable to register hmp10-keys input device"); + goto err; + } + + for (i = 0; i < ARRAY_SIZE(hmp_keys); ++i) + { + au1xxx_gpio_direction_input(hmp_keys[i].gpio); + + printk("Requesting irq %d\n", hmp_keys[i].irq); + if (request_irq(hmp_keys[i].irq, hmp10_keys_interrupt, 0, + "hmp10-keys", hmp10_kp) < 0) { + printk(KERN_ERR "Failed to register hmp10-keys " + "interrupt %d", hmp_keys[i].irq); + goto err; + } + } + + return 0; +err: + free_irqs(hmp10_kp); + + kfree(hmp10_kp); + input_free_device(input_dev); + + return -EINVAL; +} + +static int hmp10_keys_remove(struct platform_device *pdev) +{ + struct hmp10_kp *hmp10_kp = platform_get_drvdata(pdev); + + free_irqs(hmp10_kp); + input_unregister_device(hmp10_kp->input); + kfree(hmp10_kp); + + return 0; +} + +static struct platform_driver hmp10_keys_driver = { + .probe = hmp10_keys_probe, + .remove = hmp10_keys_remove, + .driver = { + .name = "hmp10-keys", + .owner = THIS_MODULE, + }, +}; + + +static int __devinit hmp10_keys_init(void) +{ + printk("HMP-10 Buttons Driver\n"); + return platform_driver_register(&hmp10_keys_driver); +} + +static void __exit hmp10_keys_exit(void) +{ + platform_driver_unregister(&hmp10_keys_driver); +} + +module_init(hmp10_keys_init); +module_exit(hmp10_keys_exit); + +MODULE_AUTHOR("Kevin Hickey"); +MODULE_DESCRIPTION("HMP10 Keys Driver"); +MODULE_LICENSE("GPL"); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/input/keyboard/Kconfig linux-2.6.29/drivers/input/keyboard/Kconfig --- linux-2.6.29/drivers/input/keyboard/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/input/keyboard/Kconfig 2009-08-17 09:11:44.000000000 -0400 @@ -259,6 +259,14 @@ To compile this driver as a module, choose M here: the module will be called omap-keypad. +config KEYBOARD_HMP + tristate "RMI HMP10 Buttons support" + depends on MIPS_HMP10 + help + Say Y here to use the navigation buttons connected to the HMP10 platform. + + To compile this driver as a module, choose M here. The + module will be called hmp10-keys. config KEYBOARD_PXA27x tristate "PXA27x/PXA3xx keypad support" depends on PXA27x || PXA3xx diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/input/keyboard/Makefile linux-2.6.29/drivers/input/keyboard/Makefile --- linux-2.6.29/drivers/input/keyboard/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/input/keyboard/Makefile 2009-08-17 09:11:44.000000000 -0400 @@ -19,6 +19,7 @@ obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o +obj-$(CONFIG_KEYBOARD_HMP) += hmp10_keys.o obj-$(CONFIG_KEYBOARD_PXA27x) += pxa27x_keypad.o obj-$(CONFIG_KEYBOARD_PXA930_ROTARY) += pxa930_rotary.o obj-$(CONFIG_KEYBOARD_AAED2000) += aaed2000_kbd.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c --- linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c 2009-09-02 10:43:51.000000000 -0400 @@ -69,15 +69,15 @@ * Documentation/input/input-programming.txt for more details. */ -static int abs_x[3] = {350, 3900, 5}; +static int abs_x[3] = {70, 3870, 20}; module_param_array(abs_x, int, NULL, 0); MODULE_PARM_DESC(abs_x, "Touchscreen absolute X min, max, fuzz"); -static int abs_y[3] = {320, 3750, 40}; +static int abs_y[3] = {127, 3970, 40}; module_param_array(abs_y, int, NULL, 0); MODULE_PARM_DESC(abs_y, "Touchscreen absolute Y min, max, fuzz"); -static int abs_p[3] = {0, 150, 4}; +static int abs_p[3] = {0, 150, 350}; module_param_array(abs_p, int, NULL, 0); MODULE_PARM_DESC(abs_p, "Touchscreen absolute Pressure min, max, fuzz"); @@ -406,10 +406,19 @@ if (rc & RC_PENUP) { if (wm->pen_is_down) { - wm->pen_is_down = 0; - dev_dbg(wm->dev, "pen up\n"); - input_report_abs(wm->input_dev, ABS_PRESSURE, 0); - input_sync(wm->input_dev); + /* + * KH (RMI): When polling, we often get false pen up + * signals so I added a threshold - 10 in a row (see + * assignment below) seems to be a good balance of + * hold and responsiveness. + */ + wm->pen_is_down--; + if (wm->pen_is_down == 0) { + dev_dbg(wm->dev, "pen up\n"); + input_report_abs(wm->input_dev, ABS_PRESSURE, 0); + input_report_key(wm->input_dev, BTN_TOUCH, 0); + input_sync(wm->input_dev); + } } else if (!(rc & RC_AGAIN)) { /* We need high frequency updates only while * pen is down, the user never will be able to @@ -430,11 +439,28 @@ "pen down: x=%x:%d, y=%x:%d, pressure=%x:%d\n", data.x >> 12, data.x & 0xfff, data.y >> 12, data.y & 0xfff, data.p >> 12, data.p & 0xfff); + +#ifdef CONFIG_MIPS_DB1300 + /* + * KH (RMI): The X-axis is connected backwards on DB1300 + */ + input_report_abs(wm->input_dev, ABS_X, 0xfff - (data.x & 0xfff)); +#else input_report_abs(wm->input_dev, ABS_X, data.x & 0xfff); +#endif + +#ifdef CONFIG_MIPS_HMP10 + /* + * KH (RMI): The Y-axis is connected backwards on HMP10 + */ + input_report_abs(wm->input_dev, ABS_Y, 0xfff - (data.y & 0xfff)); +#else input_report_abs(wm->input_dev, ABS_Y, data.y & 0xfff); +#endif input_report_abs(wm->input_dev, ABS_PRESSURE, data.p & 0xfff); + input_report_key(wm->input_dev, BTN_TOUCH, 1); input_sync(wm->input_dev); - wm->pen_is_down = 1; + wm->pen_is_down = 10; wm->ts_reader_interval = wm->ts_reader_min_interval; } else if (rc & RC_PENDOWN) { dev_dbg(wm->dev, "pen down\n"); @@ -638,6 +664,10 @@ abs_y[2], 0); input_set_abs_params(wm->input_dev, ABS_PRESSURE, abs_p[0], abs_p[1], abs_p[2], 0); + + set_bit(EV_KEY, wm->input_dev->evbit); + set_bit(BTN_TOUCH, wm->input_dev->keybit); + input_set_drvdata(wm->input_dev, wm); wm->input_dev->dev.parent = dev; ret = input_register_device(wm->input_dev); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/Kconfig linux-2.6.29/drivers/Kconfig --- linux-2.6.29/drivers/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/Kconfig 2009-08-13 23:07:03.000000000 -0400 @@ -16,6 +16,8 @@ source "drivers/block/Kconfig" +source "drivers/lba_nand/Kconfig" + # misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4 source "drivers/misc/Kconfig" diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/au1xxx_pal.c linux-2.6.29/drivers/lba_nand/au1xxx_pal.c --- linux-2.6.29/drivers/lba_nand/au1xxx_pal.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/au1xxx_pal.c 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,302 @@ +/** +***************************************************************************** + * Copyright 2008 RMI Corporation. All rights reserved. + + * Any transfer or redistribution of the source code, with or without + * modification, IS PROHIBITED, unless prior written consent was obtained. Any + * transfer or redistribution of the binary code for use on the RMI Alchemy Family + * , with or without modification, is permitted, provided that the following + * condition is met: + * + * Redistributions in binary form must reproduce the above copyright notice, + * + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution: + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + \file au1xx_pal.c + \brief Implementation of the PAL (Platform Access Layer) for the LBA NAND + driver on AU1xxx platforms + \author Kevin Hickey (khickey@RMICorp.com) +*/ +#include "au1xxx_pal.h" + +#include +#include +#include +#include +#include + +/* Persistent data declarations */ +static void __iomem *p_nand; + +static struct { + int ns_per_tick_times_10; + int ns_per_sys_clk_times_10; +} clock_times; + +/* Helper Functions */ + +void map_nand_controller( l_int32 *pstatus ) +{ + u32 mem_staddr; + u32 nand_phys; + + mem_staddr = 0x00000000; + if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) { + mem_staddr = au_readl(MEM_STADDR0); + } + else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1)) { + mem_staddr = au_readl(MEM_STADDR1); + } + else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2)) + mem_staddr = au_readl(MEM_STADDR2); + else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3)) + mem_staddr = au_readl(MEM_STADDR3); + + if ( mem_staddr == 0x00000000 ) { + PRINT( "ERROR with NAND Chip-Select; NAND chip not found.\n" ); + *pstatus = LBA_PERROR_OS_INIT; + return; + } + + nand_phys = (mem_staddr << 4) & 0xFFFC0000; + p_nand = (void __iomem *)ioremap(nand_phys, 0x1000); + if ( p_nand == NULL ) + { + *pstatus = LBA_PERROR_OS_INIT; + return; + } + + *pstatus = LBA_SUCCESS; + return; +} + +#ifdef INTERRUPT_SUPPORT +/* Interrupt handler */ +#define AU1XXX_NAND_INTERRUPT 23 +#define AU1XXX_NAND_INT_BIT (1 << AU1XXX_NAND_INTERRUPT) +DECLARE_WAIT_QUEUE_HEAD( busy_queue ); +static volatile int interrupt_flag; +spinlock_t interrupt_flag_lock = SPIN_LOCK_UNLOCKED; + +void clear_interrupt_flag( void ) +{ + spin_lock( &interrupt_flag_lock ); + interrupt_flag = 0; + spin_unlock( &interrupt_flag_lock ); +} + +void increment_interrupt_flag( void ) +{ + spin_lock( &interrupt_flag_lock ); + ++interrupt_flag; + spin_unlock( &interrupt_flag_lock ); +} + +void decrement_interrupt_flag( void ) +{ + spin_lock( &interrupt_flag_lock ); + --interrupt_flag; + spin_unlock( &interrupt_flag_lock ); +} + +void clear_interrupt_queue( void ) +{ + // wait up to 1000 jiffies for an interrupt + clear_interrupt_flag(); + wait_event_timeout( busy_queue, true, 1000 ); + + while ( interrupt_flag ) + { + clear_interrupt_flag(); + wait_event_timeout( busy_queue, true, 1000 ); + } + + clear_interrupt_flag(); +} + +static irqreturn_t handle_busy_interrupt( int irq, void *dev_id ) +{ + LBA_DEBUG( "In interrupt handler (irq=%d)\n", irq ); + + increment_interrupt_flag(); + + wake_up_interruptible( (&busy_queue) ); + return IRQ_HANDLED; +} + + +void enable_interrupts( l_int32 *pstatus ) +{ + u32 NAND_interrupt_bit = 1 << (AU1200_NAND_INT - AU1200_FIRST_INT); + u32 mem_stndctl = au_readl( MEM_STNDCTL ); + + LBA_DEBUG( "Enabling interrupt\n" ); + if ( request_irq( AU1200_NAND_INT, + handle_busy_interrupt, 0, "LBA NAND", NULL ) != 0 ) { + *pstatus = LBA_PERROR_OS_INIT; + return; + } + + mem_stndctl |= 1 << 8; + au_writel( mem_stndctl, MEM_STNDCTL ); + + au_writel( ( NAND_interrupt_bit ), IC0_CFG0SET ); + au_writel( ( NAND_interrupt_bit ), IC0_CFG1CLR ); + au_writel( ( NAND_interrupt_bit ), IC0_CFG2CLR ); + + au_writel( ( NAND_interrupt_bit ), IC0_SRCSET ); + au_writel( ( NAND_interrupt_bit ), IC0_RISINGCLR ); + au_writel( ( NAND_interrupt_bit ), IC0_WAKESET ); + au_writel( AU1XXX_NAND_INT_BIT, IC0_MASKSET ); + + clear_interrupt_queue(); +} +#endif //INTERRUPT_SUPPORT + +/* PAL Function definitions */ + +void pal_init_controller( l_int32 *pstatus ) +{ + LBA_DEBUG( "initializing.\n" ); + + map_nand_controller( pstatus ); + if ( *pstatus != LBA_SUCCESS ) { + return; + } + +#ifdef INTERRUPT_SUPPORT + enable_interrupts( pstatus ); + if ( *pstatus != LBA_SUCCESS ) { + return; + } +#endif //INTERRUPT_SUPPORT + + LBA_DEBUG( "initialization completed successfully\n" ); + *pstatus = LBA_SUCCESS; + +} + +void pal_close_controller(l_int32 *pstatus) +{ + LBA_DEBUG( "pal_close_controller\n" ); +#ifdef INTERRUPT_SUPPORT + free_irq( 31, NULL ); +#endif //INTERRUPT_SUPPORT + + if ( p_nand != NULL ) + { + iounmap( p_nand ); + } + + *pstatus = LBA_SUCCESS; +} + +void pal_send_data (l_uchar *pdata_buf,l_uint32 transfer_size) +{ + int i; + + for ( i = 0; i < transfer_size / 4; ++i ) + { + iowrite32( *( (u32*)pdata_buf ), p_nand + MEM_STNAND_DATA ); + pdata_buf += 4; + au_sync(); + } + + for ( i = 0; i < transfer_size % 4; ++i ) + { + iowrite8( *pdata_buf, p_nand + MEM_STNAND_DATA ); + } +} + +#define DAVID_NAND_READ +#ifdef DAVID_NAND_READ +void pal_receive_data(l_uchar *pdata_buf,l_uint32 transfer_size) +{ + int i; + + for ( i = 0; i < transfer_size ; ++i ) + { + *pdata_buf++ = ioread8( p_nand + MEM_STNAND_DATA ); + au_sync(); + } +} + +#else +void pal_receive_data (l_uchar *pdata_buf,l_uint32 transfer_size) +{ + int i; + + for ( i = 0; i < transfer_size / 4; ++i ) + { + *( (u32*)pdata_buf ) = ioread32( p_nand + MEM_STNAND_DATA ); + pdata_buf += 4; + au_sync(); + } + + for ( i = 0; i < transfer_size % 4; ++i ) + { + *pdata_buf = ioread8( p_nand + MEM_STNAND_DATA ); + } +} +#endif + +void pal_send_command(l_uchar command) +{ + LBA_DEBUG( "Sending command %d\n", (int)command ); + iowrite8( command, p_nand + MEM_STNAND_CMD ); + au_sync(); +} + +void pal_send_address (l_uchar *paddress, l_uint32 addr_count) +{ + int i; + LBA_DEBUG( "Sending address, %d bytes\n", (int)addr_count ); + for ( i = 0; i < addr_count; ++i ) + { + iowrite8( paddress[i], p_nand + MEM_STNAND_ADDR ); + au_sync(); + } +} + +void pal_get_busy_status (l_int32 *pstatus) +{ + u32 status; +#ifdef LBA_NAND_DEBUG + u32 before, after; + before = read_c0_count(); +#endif //LBA_NAND_DEBUG + +#ifdef INTERRUPT_SUPPORT + wait_event_interruptible_timeout( busy_queue, interrupt_flag > 0,1000); + decrement_interrupt_flag(); +#else + status = au_readl( MEM_STSTAT ); + au_sync(); + au_sync_udelay(50); + + while ( ( status & 0x00000001 ) == 0 ) + { + status = au_readl( MEM_STSTAT ); + au_sync_udelay( 1 ); + } +#endif // INTERRUPT_SUPPORT +#ifdef LBA_NAND_DEBUG + after = read_c0_count(); + printk( KERN_INFO "Busy for %d ticks or %d us\n", (after-before), + ( ( (after-before) * clock_times.ns_per_tick_times_10 ) ) / 10000 ); + // 10000 = 1000 for ns->us and 10 more for tick times 10 +#endif //LBA_NAND_DEBUG + *pstatus = LBA_SUCCESS; // Device is ready +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/au1xxx_pal.h linux-2.6.29/drivers/lba_nand/au1xxx_pal.h --- linux-2.6.29/drivers/lba_nand/au1xxx_pal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/au1xxx_pal.h 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,95 @@ +/** +***************************************************************************** + * Copyright 2008 RMI Corporation. All rights reserved. + + * Any transfer or redistribution of the source code, with or without + * modification, IS PROHIBITED, unless prior written consent was obtained. Any + * transfer or redistribution of the binary code for use on the RMI Alchemy Family + * , with or without modification, is permitted, provided that the following + * condition is met: + * + * Redistributions in binary form must reproduce the above copyright notice, + * + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution: + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + **************************************************************************** + \file au1xx_pal.c + \brief Declaration of the PAL (Platform Access Layer) for the LBA NAND + driver on AU1xxx platforms + \author Kevin Hickey (khickey@RMICorp.com) +*/ + +#ifndef AU1XXX_PAL_H +#define AU1XXX_PAL_H + +#include "lba_includes.h" + +#define PRINT(args...) \ + printk(KERN_INFO "au1xxx_pal: " args) + +union mem_stcfg { + struct { + u32 DTY :3; // Device type + u32 RO :1; // Read-only + u32 PM :1; // Page Mode + u32 BS :1; // Burst Size + u32 MBSb :1; // Must Be Set + u32 EW :1; + u32 TS :1; // Time Scale + u32 BE :1; // Endianness + u32 AV :1; // Address visible + u32 :1; // Reserved + u32 ALD :1; // Address Latch Disable + u32 DIV :3; // RCLK output clock divisor + u32 TA :1; // Tcsh application? + u32 BEB :2; // Byte Enable Behavior + u32 DE :1; // Deassert chip select + u32 S :1; // Synchronous mode + u32 AS :1; // Setup address before output enable + u32 NW :1; // NAND width - 0=16 bit; 1=8 bit + u32 :2; // Reserved + u32 AH :1; // Hold address after output enable + u32 Toecs :3; // + u32 Tcsoe :3; // + } bits; + u32 data; +}; + +#define MINIMUM_TH_IN_NS 60 // See databook +#define MINIMUM_TPUL_IN_NS 350 // See databook +#define MINIMUM_TSU_IN_NS 120 // See databook + +union mem_sttime1_bits { + // Each value is in system bus ticks; the CPU adds 1 tick when using NAND + struct { + u32 Th :4; // Global hold timing for Talh, Tclh, Tch, Tdh + u32 Tpul :4; // Global timing for Twp and Trp + u32 Tsu :4; // Global setup timing for Tcls, Tals, Tcs, Tds + u32 RESERVED :20; + } bits; + u32 data; +}; + + +// API as specified by Toshiba +void pal_init_controller(l_int32 *pstatus); +void pal_send_data (l_uchar *pdata_buf,l_uint32 transfer_size); +void pal_receive_data (l_uchar *pdata_buf,l_uint32 transfer_size); +void pal_send_command(l_uchar command); +void pal_send_address (l_uchar *paddress, l_uint32 addr_count); +void pal_get_busy_status (l_int32 *pstatus); +void pal_close_controller(l_int32 *pstatus); + + +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/imx31_pal.c linux-2.6.29/drivers/lba_nand/imx31_pal.c --- linux-2.6.29/drivers/lba_nand/imx31_pal.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/imx31_pal.c 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,590 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file imx31_pal.c + * \brief This source file contains the function definitions, + * interface implementation for the Platform Access + * Layer,PAL(Platform Specific) + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: imx31_pal.c,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + +/* HOST : IMX31 Multimedia Processor[ARM 1136JF-S Core] */ + +/* driver specific files */ +#include "lba_includes.h" + +/* Global variable to access Nand Flash controller Registers */ +volatile void *nfc_reg_base_logical_addr = NULL; + +/* Global variable to access Nand Flash controller Main Ram Buffers */ +volatile void *nfc_ram_buff_base_logical_addr = NULL; + +/* Global variable to access Nand Flash controller Spare Ram Buffers */ +volatile void *nfc_spare_buff_base_logical_addr = NULL; + +#ifdef INTERRUPT_SUPPORT +static wait_queue_head_t irq_wait_queue; +/* This flag is used for interrupt or polling mode identification */ +static l_uint32 use_irq = 0; +/* this will be called by kernel after interrupt */ +static irqreturn_t nfc_irq_handler(int irq, void *dev_id); +/* implementation for waiting for interrupt */ +static void wait_for_irq(void); +#endif + +/* PAL Function definitions */ + + +/*! \fn void pal_init_controller(l_int32 *pstatus) + * \brief This function initializes the NAND Flash + * controller of the target platform and mapping + * physical address to logical address. It also performs OS + * specific initialization with respect to Interrupt. This + * initialization is done if the configuration + * INTERRUPT_SUPPORT is defined. + * + * \calledby + * mal_lba_mdp_init(l_int32 *pstatus) + * \param pstatus + * LBA_SUCCESS -Initialization is + * successful
+ * error codes -Initialization is + * failed + * + * \return None + * \callgraph + */ + +void pal_init_controller(l_int32 *pstatus) +{ + l_uint32 nfc_reg = 0; +#ifdef INTERRUPT_SUPPORT + l_int32 err = 0; +#endif /* INTERRUPT_SUPPORT */ + + /* Variable to access clock module registers */ + volatile void *clk_base_logical_addr = NULL; + + *pstatus = LBA_SUCCESS; + + /* Mapping the clock control module memory space + * to virtual memory space + */ + clk_base_logical_addr = + (void __iomem *)ioremap(CLK_MODULE_BASE_ADDR, + NUM_BYTES_CLK_CTRL_MOD_REG); + if (NULL == clk_base_logical_addr) { + *pstatus = LBA_PERROR_IO_MEM_MAP; + goto error_check; + } + + nfc_ram_buff_base_logical_addr = + (void __iomem *) ioremap(NFC_MAIN_RAM_BUF_BASE_ADDR, + NUM_BYTES_NFC_MAIN_RAM_BUFFER); + /* Mapping of NAND flash controller main Ram buffer + * to virtual Memory space + */ + + if (NULL == nfc_ram_buff_base_logical_addr) { + *pstatus = LBA_PERROR_IO_MEM_MAP; + goto error_check; + } + + /* Mapping of NAND flash Controller Spare Ram buffer + * to virtual Memory space + */ + nfc_spare_buff_base_logical_addr = + (void __iomem *) ioremap(NFC_SPARE_RAM_BUF_BASE_ADDR, \ + NUM_BYTES_NFC_SPARE_RAM_BUFFER); + if (NULL == nfc_spare_buff_base_logical_addr) { + *pstatus = LBA_PERROR_IO_MEM_MAP; + goto error_check; + } + + /* Mapping of NAND flash Controller Ram buffer + * to virtual Memory space + */ + nfc_reg_base_logical_addr = + (void __iomem *) ioremap(NFC_REG_BASE_ADDR, + NUM_BYTES_NAND_CTRLER_REG); + if (NULL == nfc_reg_base_logical_addr) { + *pstatus = LBA_PERROR_IO_MEM_MAP; + goto error_check; + } + + /* + * Clock control module Initialization + */ + + /* Selecting the nand flash characteristics */ + nfc_reg = IMX31_READ_REG(((l_uchar *)clk_base_logical_addr + \ + RESET_CTRL_SRC_REG ) ); + nfc_reg = nfc_reg | (NAND_INTERFACE_8_BIT|NAND_PAGE_SIZE_512); + IMX31_WRITE_REG(((l_uchar *)clk_base_logical_addr + \ + RESET_CTRL_SRC_REG), \ + nfc_reg); + + /* Setting the NAND flash clock divider */ + nfc_reg = IMX31_READ_REG(((l_uchar *) clk_base_logical_addr + \ + POST_DIVIDER_REG0 ) ); + nfc_reg = (nfc_reg & NFC_CLOCK_DIVIDER_MASK) | NFC_CLOCK_DIVIDER; + IMX31_WRITE_REG(((l_uchar *)clk_base_logical_addr + \ + POST_DIVIDER_REG0),nfc_reg); + + /* Nand Flash controller initialization */ + + /* Selecting the Ram buffer for Read and write */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_RAM_BUFF_ADDR_REG ),\ + SELECT_RAM_BUFFER_4 ); + + /* unlock start block address */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_UNLOCK_START_BLK_ADDR_REG ),\ + UNLOCK_START_ADDR_IN_WRITE_PROT ); + + /* unlock end block address */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_UNLOCK_END_BLK_ADDR_REG ), + UNLOCK_END_ADDR_IN_WRITE_PROT ); + + + /* Unlock the blocks based on start and end block address*/ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_WRITE_PROTECT_REG ), + BLOCK_UNLOCKED_IN_WRITE_PROT ); + /* Disable all the operations and set nand status as ready */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_2_REG ),NAND_FLASH_READY ); + + /* Disable the interrupt,Bypass the ECC operation */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_1_REG ),\ + (NAND_FLASH_ECC_BYPASSED | + NAND_FLASH_MASK_INTERRUPT)); +#ifdef INTERRUPT_SUPPORT + + /* Initialize the interrupt */ + init_waitqueue_head(&irq_wait_queue); + err = request_irq(NAND_CONTROLLER_INTERRUPT_NUM, \ + nfc_irq_handler, 0, "lba", NULL); + + if (err) + use_irq = 0; + else + use_irq = 1; + +#endif /* INTERRUPT_SUPPORT */ + *pstatus = LBA_SUCCESS; +error_check: + if ( LBA_FAILURE == LBA_ERR_STATUS(*pstatus)) { + if (clk_base_logical_addr) { + iounmap((void *) CLK_MODULE_BASE_ADDR); + clk_base_logical_addr = NULL; + } + if (nfc_ram_buff_base_logical_addr) { + iounmap((void *) NFC_MAIN_RAM_BUF_BASE_ADDR); + nfc_ram_buff_base_logical_addr = NULL; + } + if (nfc_spare_buff_base_logical_addr) { + iounmap((void *)NFC_SPARE_RAM_BUF_BASE_ADDR); + nfc_spare_buff_base_logical_addr = NULL; + } + if (nfc_reg_base_logical_addr) { + iounmap((void *)NFC_REG_BASE_ADDR); + nfc_reg_base_logical_addr = NULL; + } + } +} + +/*! \fn void pal_send_command(l_uchar command) + * \brief This function is used to send command to the + * NAND flash + * + * \calledby + * mal_lba_read_id(l_uchar *pdevice_id, l_int32 *pstatus), + * etc + * \param command - Command to be sent to the NAND chip + * \return None + * \callgraph + */ + void pal_send_command(l_uchar command) + { + + l_int32 status = 0; + + /* write the command */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CMD_REG),command ); + + /* configure for command input */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_2_REG ),NAND_FLASH_COMMAND_INPUT); + pal_get_busy_status (&status); + + } + + +/*! \fn void pal_send_address (l_uchar *paddress, + * l_uint32 addr_count) + * \brief This function is used to send address to the + * NAND flash. + * + * \calledby + * mal_lba_read_id(l_uchar *pdevice_id, l_int32 *pstatus), + * etc. + * \param paddress - pointer to array of address bytes + * \param addr_count - number of address bytes to be + * sent. + * \return None + * \callgraph + */ + void pal_send_address (l_uchar *paddress,l_uint32 addr_count) + { + + l_uint32 loop = 0; + l_int32 status = LBA_SUCCESS; + + for (loop = 0; loop < addr_count; loop++) { + /* write the address */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_ADDR_REG ),*paddress ); + + /* configure for address input */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_2_REG ),\ + NAND_FLASH_ADDRESS_INPUT); + pal_get_busy_status (&status); + paddress++; + } + } + + +/*! \fn void pal_get_busy_status (l_int32 *pstatus) + * + * \brief This function returns the ready/busy status + * of NAND flash. Status of NAND is checked by + * polling controller status register. The poll + * for busy/ready status is performed by reading + * the status register for a maximum of + * '(DWORD)-1' number of times. The + * specified maximum time limit for a status + * change is one second (Please refer LBA NAND + * data sheet)since usage of system call is not + * possible and an exact software delay generation + * is not possible an approximation is used here + * + * \calledby + * mal_lba_read_id(l_uchar *pdevice_id, l_int32 *pstatus), + * etc + * \param pstatus - + * LBA_SUCCESS - NAND chip is ready.
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * \callgraph + */ +void pal_get_busy_status(l_int32 *pstatus) +{ + volatile l_uint32 loop_count = 0; + + *pstatus = LBA_PERROR_BUSY_PERIOD_EXCEED; + /* time out value for polling the busy * status */ + loop_count = ((l_uint32) - 1); + +#ifdef INTERRUPT_SUPPORT + if (!use_irq) { +#endif /* INTERRUPT_SUPPORT */ + while (loop_count--) { + if (((IMX31_NFC_READ_REG(((u_char *)nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_2_REG ))) & NAND_FLASH_READY) \ + == NAND_FLASH_READY) { + *pstatus = LBA_SUCCESS; + break; + } + } +#ifdef INTERRUPT_SUPPORT + } else { + wait_for_irq(); + *pstatus = LBA_SUCCESS; + } +#endif /* INTERRUPT_SUPPORT */ +} + +/*! \fn void pal_send_data (l_uchar *pdata_buf, + * l_uint32 transfer_size) + * + * \brief This function is used to send data to the NAND flash. + * This function sends data to nand if the data to be + * sent is 512 or multiples of 512. + * + * \calledby + * mal_lba_set_protocol_1(l_uchar data, l_int32 *pstatus) + * etc + * \param pdata_buf - pointer to data buffer to which + * the data is to be read for flash write. + * \param transfer_size - number of data bytes to be sent. It + * should be multiple of 512. + * + * \return None + * \callgraph + */ + void pal_send_data (l_uchar *pdata_buf,l_uint32 transfer_size) + { + + l_uint32 sec_count = 0; /* no of sectors to write */ + l_int32 status = 0; + l_uchar alignment =0; + l_uint16 spare_flag = FALSE; + l_uchar * buf_ptr=pdata_buf; + + sec_count = transfer_size/SECTOR_SIZE_512; + /* Checking whether the write call is PNP partition */ + if ((transfer_size % 2112) == 0) { + spare_flag = TRUE; + sec_count = NUM_SECTORS_2048_PAGE; + } + + while (sec_count--) { + + /* Write the data to RAM buffer */ + memcpy((void*)nfc_ram_buff_base_logical_addr,(void *)buf_ptr, + SECTOR_SIZE_512 - alignment); + buf_ptr+=SECTOR_SIZE_512; + + + /* If the Write call is for PNP + * then write the spare bytes given by host + */ + if (spare_flag) { + /* Write the data to spare area buffer in case of PNA + * write */ + + memcpy((void*)nfc_spare_buff_base_logical_addr, + (void *)buf_ptr, SPARE_SIZE); + buf_ptr+=SPARE_SIZE; + } + + + /* setting the configuration registers to write data to nand */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_2_REG), + NAND_FLASH_PAGE_INPUT); + pal_get_busy_status(&status); + + } + } + +/*! \fn void pal_receive_data (l_uchar *pdata_buf, + * l_uint32 transfer_size) + * + * \brief This function is used to receive data from the + * NAND flash. + * + * \calledby + * mal_lba_read_id(l_uchar *pdevice_id, l_int32 *pstatus), + * etc + * \param pdata_buf - pointer to data buffer to which the read + * data has to be filled + * \param transfer_size - number of data bytes to be read. Size + * of pdata_buf should be exactly same as + * transfer size + * + * \return None + * \callgraph + */ +void pal_receive_data (l_uchar *pdata_buf,l_uint32 transfer_size) +{ + l_int32 status = LBA_SUCCESS; + l_uint16 odd_bytes =0; + l_uint32 alignment =0; + l_uint32 sec_count = 0; + l_uint16 byte_count = HALF_WORDS_MAIN_RAM_BUFFER; + l_uint16 byte_read = 0; + l_uint16 spare_flag = FALSE; + volatile void *read_last_byte = NULL; + l_uchar * buffer_ptr=pdata_buf; + + /* Checking whether the read call is PNP partition */ + sec_count = transfer_size/512; + if (transfer_size % 2112 == 0){ + spare_flag = TRUE; + sec_count = NUM_SECTORS_2048_PAGE; + } + + /* If the number of bytes to read is less than 512 */ + if (sec_count == 0) { + sec_count += 1; + byte_count = (l_uint16)(transfer_size/2); + read_last_byte = (void *)(\ + ((l_uint16 *)nfc_ram_buff_base_logical_addr) + \ + byte_count); + } + + while(sec_count--) { + + /* setting the configuration registers to read data from nand */ + IMX31_NFC_WRITE_REG(((l_uchar *)nfc_reg_base_logical_addr + \ + NANDFC_CONFGI_2_REG ),\ + NAND_FLASH_PAGE_OUTPUT ); + + pal_get_busy_status(&status); + + if (transfer_size >=512 && + !((l_uint32)buffer_ptr & (sizeof(l_uint32) -1))) + { + memcpy((void *)buffer_ptr , + (void *)nfc_ram_buff_base_logical_addr ,SECTOR_SIZE_512); + + buffer_ptr+=SECTOR_SIZE_512; + + /* If the read call is for PNP + * then read the spare bytes to give to the host + */ + + if (spare_flag ==TRUE) + { + memcpy((void *)buffer_ptr, + (void *)nfc_spare_buff_base_logical_addr, + SPARE_SIZE - alignment); + buffer_ptr+=SPARE_SIZE; + } + + } + else{ + + /* Read the data from RAM buffer */ + for (byte_read = 0;byte_read < byte_count;byte_read++) { + + odd_bytes = IMX31_NFC_READ_REG(\ + ((l_uint16 *)nfc_ram_buff_base_logical_addr) +\ + byte_read); + *pdata_buf = (l_uchar) odd_bytes; + pdata_buf++; + *pdata_buf = (l_uchar)(odd_bytes >> BYTE_SHIFT_VALUE); + pdata_buf++; + } + if (spare_flag){ + for(byte_read = 0;byte_read>BYTE_SHIFT_VALUE); + pdata_buf++; + } + } + } + } + + /* read the last byte if transfer_size is not multiple of 2 */ + if (transfer_size & 1) { + odd_bytes = IMX31_NFC_READ_REG((l_uint16 *)read_last_byte); + *pdata_buf = (l_uchar) odd_bytes; + } + +} + +/*! \fn void pal_close_controller(l_int32 *pstatus); + * + * \brief This function is used to unmap the virtual memory + * \param l_int32 *pstatus - pointer to the status + * \return None + * \callgraph Called by mal_lba_mdp_close(l_int32 *pstatus); + */ + +void pal_close_controller(l_int32 *pstatus) +{ + /* unmap physical address if any */ + + if (nfc_ram_buff_base_logical_addr) { + iounmap((void *) NFC_MAIN_RAM_BUF_BASE_ADDR); + nfc_ram_buff_base_logical_addr = NULL; + } + if (nfc_spare_buff_base_logical_addr) { + iounmap((void *)NFC_SPARE_RAM_BUF_BASE_ADDR); + nfc_spare_buff_base_logical_addr = NULL; + } + if (nfc_reg_base_logical_addr) { + iounmap((void *)NFC_REG_BASE_ADDR); + nfc_reg_base_logical_addr = NULL; + } + +#ifdef INTERRUPT_SUPPORT + free_irq(NAND_CONTROLLER_INTERRUPT_NUM, NULL); +#endif /* INTERRUPT_SUPPORT */ + + *pstatus = LBA_SUCCESS; +} + +#ifdef INTERRUPT_SUPPORT + +/*! \fn static irqreturn_t nfc_irq_handler(int irq, void *dev_id); + * \brief: This function is the interrupt handler for the NAND + * controller. Interrupt handler just wakes up the threads + * waiting on the event queue once the basic operation is + * completed. + * \param int irq: interrupt request number(irq) + * void *dev_id: device identity + * \return irqreturn_t: irq return type + * \callgraph None + */ +static irqreturn_t nfc_irq_handler(int irq, void *dev_id) +{ + l_uint16 config1_reg =0; + + config1_reg = IMX31_NFC_READ_REG(\ + ((l_uchar *)nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_1_REG )) ; + + IMX31_NFC_WRITE_REG(((u_char *) nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_1_REG), config1_reg \ + | NAND_FLASH_MASK_INTERRUPT); + wake_up(&irq_wait_queue); + + return IRQ_RETVAL(1); +} + +/*! \fn static void wait_for_irq (void); + * + * \brief This function enables the NAND controller interrupt and + * waits on event queue for the basic operation to complete + * by checking the INT bit of config2 register. + * NOTE: This function will not wait on event if the + * configuration2(NANDFC_CONFIG_2_REG) Register is already set + * or basic operation is completed. + * \param None + * \return None + * \callgraph called by pal_get_busy_status(); + */ +static void wait_for_irq (void) +{ + l_uint16 config_reg =0; + + config_reg = IMX31_NFC_READ_REG(((l_uchar *) + nfc_reg_base_logical_addr + NANDFC_CONFGI_2_REG)); + if ((config_reg & NAND_FLASH_READY) == 0) { + /* Enable interrupt */ + config_reg = IMX31_NFC_READ_REG(((l_uchar *) + nfc_reg_base_logical_addr + NANDFC_CONFGI_1_REG)); + IMX31_NFC_WRITE_REG(((u_char *) nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_1_REG), \ + config_reg & (~NAND_FLASH_MASK_INTERRUPT)); + wait_event(irq_wait_queue, (IMX31_NFC_READ_REG(((l_uchar *) + nfc_reg_base_logical_addr + NANDFC_CONFGI_2_REG)) \ + & NAND_FLASH_READY)); + config_reg = IMX31_NFC_READ_REG(\ + ((l_uchar *)nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_1_REG )) ; + IMX31_NFC_WRITE_REG((((l_uchar *) nfc_reg_base_logical_addr \ + + NANDFC_CONFGI_1_REG)),\ + config_reg &= (~NAND_FLASH_READY)); + } +} + +#endif /* INTERRUPT_SUPPORT */ + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/imx31_pal.h linux-2.6.29/drivers/lba_nand/imx31_pal.h --- linux-2.6.29/drivers/lba_nand/imx31_pal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/imx31_pal.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file imx31_pal.h + * \brief This header file contains the Macros,structure ,and + * function declaration for the Platform Access Layer, + * PAL(Platform Specific) + * $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: imx31_pal.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + +/* HOST : IMX31 Multimedia Processor[ARM 1136JF-S Core] */ + +/* include files for macro definitions */ +#include "lba_config.h" /* required for INTERRUPT_SUPPORT macro */ + +#ifndef IMX31_PAL_H_ +#define IMX31_PAL_H_ + +#if LBA_GENERATE_DOXYGEN +/** + * @defgroup H_1 LBA-NAND Driver API specifications + * This contains API specification for LBA-NAND driver on Linux 2.6.22 + * for IMX31. + * + * + * @addtogroup H_1_1 Exported interfaces + * @ingroup H_1 + * This section contains explanation about functions, typedefs + * and macros exported by the LBA-NAND driver to be used by application. + */ + +#endif /* LBA_GENERATE_DOXYGEN */ + +/* Configuration related files */ +#include "lba_config.h" +#include "lba_types.h" + +/* OS specific files */ +#if LBA_LINUX +#include +#endif /* LBA_LINUX */ + +/* Global variable to access Nand Flash controller Registers */ +extern volatile void *nfc_reg_base_logical_addr; + +/* Global variable to access Nand Flash controller Main Ram Buffers */ +extern volatile void *nfc_ram_buff_base_logical_addr; + +/* Global variable to access Nand Flash controller Spare Ram Buffers */ +extern volatile void *nfc_spare_buff_base_logical_addr; + +/* + * NOTE: + * The micro second count and mill second count is calculated depending + * on the Operating clock frequency of target platform. + * + * Each iteration of a "for" loop consists of approximately two + * instructions, i.e, two processor clock cycles (in cached operation) + * 1 clock = 3.7nano-sec @ 266MHz + * If all instructions hit,it takes 2clocks(7.4 nano-sec) per loop + * So, Micro second count = (1 micro-sec / 7.4 nano-sec) = 135 times + * For Millisecond count = (1 milli-sec)/ 7.4 nano-sec = 135135 times + */ +#define MICRO_SECOND_COUNT 135 +#define MILLISECOND_COUNT 135135 + +#define MICRO_SECOND_DELAY(micro_second) { \ + volatile l_uint32 tick_count;\ + for (tick_count = 0; \ + tick_count < (MICRO_SECOND_COUNT * (micro_second)); \ + tick_count++); \ + } + + +/* Number of Bytes to be Mapped for virtual Memory Space */ +#define NUM_BYTES_CLK_CTRL_MOD_REG 20 +#define NUM_BYTES_NAND_CTRLER_REG 28 +#define NUM_BYTES_NFC_MAIN_RAM_BUFFER 512 +#define NUM_BYTES_NFC_SPARE_RAM_BUFFER 16 + +/* + * Clock Module regsiters + */ +#define CLK_MODULE_BASE_ADDR 0x53F80000 +#define POST_DIVIDER_REG0 0x0004 +#define RESET_CTRL_SRC_REG 0x000C + +/* + * Clock Module register Bit field + */ +#define NAND_INTERFACE_8_BIT 0 +#define NAND_INTERFACE_16_BIT (1 << 31) +#define NAND_PAGE_SIZE_512 0 +#define NAND_PAGE_SIZE_2048 (1 << 30) +#define NFC_CLOCK_DIVIDER_MASK (0xFFFFF8FFUL) +#define NFC_CLOCK_DIVIDER (5<<8) + +/* + * Nand flash registers address + */ +#define NFC_MAIN_RAM_BUF_BASE_ADDR NANDFC_MAIN_AREA_BUF3 +#define NFC_SPARE_RAM_BUF_BASE_ADDR NANDFC_SPARE_AREA_BUF3 +#define NFC_REG_BASE_ADDR 0xB8000E00 + +#define NANDFC_MAIN_AREA_BUF0 0xB8000000 +#define NANDFC_MAIN_AREA_BUF1 0xB8000200 +#define NANDFC_MAIN_AREA_BUF2 0xB8000400 +#define NANDFC_MAIN_AREA_BUF3 0xB8000600 +#define NANDFC_SPARE_AREA_BUF0 0xB8000800 +#define NANDFC_SPARE_AREA_BUF1 0xB8000810 +#define NANDFC_SPARE_AREA_BUF2 0xB8000820 +#define NANDFC_SPARE_AREA_BUF3 0xB8000830 + +#define NANDFC_BUFF_SIZE_REG 0x00 +#define NANDFC_RAM_BUFF_ADDR_REG 0x04 +#define NANDFC_ADDR_REG 0x06 +#define NANDFC_CMD_REG 0x08 +#define NANDFC_BUFF_LOCK_CTRL_REG 0x0A +#define NANDFC_WRITE_PROTECT_REG 0x12 +#define NANDFC_UNLOCK_START_BLK_ADDR_REG 0x14 +#define NANDFC_UNLOCK_END_BLK_ADDR_REG 0x16 +#define NANDFC_WRITE_PROTECT_STATUS_REG 0x18 +#define NANDFC_CONFGI_1_REG 0x1A +#define NANDFC_CONFGI_2_REG 0x1C + +/* + * Data Values for Nand flash controller registers + */ +#define SELECT_RAM_BUFFER_1 0 +#define SELECT_RAM_BUFFER_2 1 +#define SELECT_RAM_BUFFER_3 2 +#define SELECT_RAM_BUFFER_4 3 +#define UNLOCK_START_ADDR_IN_WRITE_PROT 0 +#define UNLOCK_END_ADDR_IN_WRITE_PROT 0xFFFF +#define BLOCK_UNLOCKED_IN_WRITE_PROT 4 +#define NAND_FLASH_READY 0x8000 +#define NAND_FLASH_MASK_INTERRUPT 0x0010 +#define NAND_FLASH_ECC_BYPASSED 0 +#define NAND_FLASH_ECC_ENABLED 0x0008 +#define NAND_FLASH_COMMAND_INPUT 1 +#define NAND_FLASH_ADDRESS_INPUT 2 +#define NAND_FLASH_PAGE_OUTPUT 8 +#define NAND_FLASH_PAGE_INPUT 4 + +/* + * Data Values for Logic + */ +#define BYTE_SHIFT_VALUE 8 +#define SECTOR_SIZE_512 512 +#define HALF_WORDS_MAIN_RAM_BUFFER 256 +#define NUM_SECTORS_2048_PAGE 4 +#define HALF_WORDS_SPARE_BUFFER 8 +#define SPARE_SIZE 16 + +/* define the nand controller interrupt number + * + * Note: This is BSP specific interrurt number + * change this number according the platform BSP + */ +#ifdef INTERRUPT_SUPPORT +#define NAND_CONTROLLER_INTERRUPT_NUM 33 +#endif /* INTERRUPT_SUPPORT */ + +/* + * Register access macros + */ + +/* 32 bit read and write access */ +#define IMX31_READ_REG(port) \ + *((volatile l_uint32 *)(port)) +#define IMX31_WRITE_REG(port, value) \ + *((volatile l_uint32 *)(port)) = (value) + +/* 16 bit read and write access */ +#define IMX31_NFC_READ_REG(port) \ + *((volatile l_uint16 *)(port)) +#define IMX31_NFC_WRITE_REG(port, value) \ + *((volatile l_uint16 *)(port)) = (value) + + + +/** + * @ingroup H_1_1 + * @addtogroup H_1_1_1 LBA-NAND Driver PAL layer API set + * This section contains explanation about APIs + * exported by the LBA-NAND driver to be used by MAL layer functions. + * @{ + */ +void pal_init_controller(l_int32 *pstatus); +void pal_send_data (l_uchar *pdata_buf,l_uint32 transfer_size); +void pal_receive_data (l_uchar *pdata_buf,l_uint32 transfer_size); +void pal_send_command(l_uchar command); +void pal_send_address (l_uchar *paddress, l_uint32 addr_count); +void pal_get_busy_status (l_int32 *pstatus); +void pal_close_controller(l_int32 *pstatus); +/** + * @} + */ + +#endif /* IMX31_PAL_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/Kconfig linux-2.6.29/drivers/lba_nand/Kconfig --- linux-2.6.29/drivers/lba_nand/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/Kconfig 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,31 @@ +# Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. +# +# file: Kconfig +# brief: This file makes LBA-NAND support in kernel configuration +# and describes LBA-NAND subsystem configuration +# $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ +# $Id: Kconfig,v 1.3 2008/04/03 15:03:14 rowen Exp $ +# +# + + +menuconfig LBA_NAND + tristate "LBA_NAND support" + default n + ---help--- + LBA-NAND is a logical block device used for storage media + and manufactured by TOSHIBA. It has an internal NAND controller + which takes care of bad block management, error correction, + wear levelling, logical to physical address mapping. The driver + does not have to perform complicated NAND flash management. + +if LBA_NAND +config LBA_DEBUG_MSG + bool "LBA-NAND driver debugging messages" + default n + help + Say Y here if you want the LBA-NAND driver to produce a bunch of + debug messages to the system log. Select this if you are having a + problem with LBA-NAND support and want to see more of what is + going on. +endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_config.h linux-2.6.29/drivers/lba_nand/lba_config.h --- linux-2.6.29/drivers/lba_nand/lba_config.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_config.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_config.h + * \brief This header file contains the Macros that can be enabled + * for particular configuration + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_config.h,v 1.4 2008/04/03 15:03:14 rowen Exp $ + * + */ + + +#ifndef LBA_CONFIG_H_ +#define LBA_CONFIG_H_ + +#include "lba_types.h" + +/* This macro is used for generating API document disable + * this macro for compilation by making it 0 */ +#define LBA_GENERATE_DOXYGEN 0 +/* enables interrupt handling */ +#define INTERRUPT_SUPPORT + +/* Enables error checking based on NAND controller ready/ busy pin. + * It will also check for ready/busy bit of primary status also + */ +#define READYPIN_WAIT_CHECK_ERROR_PRIMARY 0 + +/* Compiles driver code for LINUX operating system */ +#define LBA_LINUX 1 + +/* This macro converts TEXT to plain statement*/ +#if LBA_LINUX +#define TEXT(x) x +#endif /*LBA_LINUX */ + +/* + * Comment out this macro if error information are not required.Note + * that the MACRO DEBUG is not used here because it may be required to + * have these debug strings for release build as well. + */ +#define LBA_ENABLE_ERR_STRINGS 1 +#endif /* LBA_CONFIG_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_error.h linux-2.6.29/drivers/lba_nand/lba_error.h --- linux-2.6.29/drivers/lba_nand/lba_error.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_error.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_error.h + * \brief This file contains error codes to be used in the LBA + * driver. + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_error.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + +#ifndef LBA_ERROR_H_ +#define LBA_ERROR_H_ + +#include "lba_config.h" + + +#define LBA_SUCCESS 1 +#define LBA_FAILURE 0 + +/* MAL error codes */ + +/* + MAL error code values are designed to be in the following range + -1 to -255. + */ + +#define LBA_MERROR_MODE_CHANGE_MDA -1 +#define LBA_MERROR_MODE_CHANGE_VFP -2 +#define LBA_MERROR_MODE_CHANGE_PNP -3 +#define LBA_MERROR_CHG_SIZE_VFP -4 +#define LBA_MERROR_READ_SECTOR -5 +#define LBA_MERROR_READ_TYPE -6 +#define LBA_MERROR_WRITE_SECTOR -7 +#define LBA_MERROR_WRITE_TYPE -8 +#define LBA_MERROR_READ_PAGE -9 +#define LBA_MERROR_WRITE_PAGE -10 +#define LBA_MERROR_PROTOCOL1_SET -11 +#define LBA_MERROR_PROTOCOL2_SET -12 +#define LBA_MERROR_EXIT_HIGH_SPEED -13 +#define LBA_MERROR_ENTER_HIGH_SPEED -14 +#define LBA_MERROR_EXIT_LOW_POWER -15 +#define LBA_MERROR_ENTER_LOW_POWER -16 +#define LBA_MERROR_SET_PASSWORD -17 +#define LBA_MERROR_SET_BUSY_TIME -18 +#define LBA_MERROR_FLUSH_CACHE -19 +#define LBA_MERROR_TERMINATE_RW -20 +#define LBA_MERROR_READ_RETRANSFER -21 +#define LBA_MERROR_DEVICE_INIT -22 +#define LBA_MERROR_PRIMARY_READY -23 +#define LBA_MERROR_READ_CONFIGURATION -24 + + +/* PAL error codes */ +#define LBA_PERROR_DEVICE_FAILURE -(1 << 8) +#define LBA_PERROR_IO_MEM_MAP -(2 << 8) +#define LBA_PERROR_BUSY_PERIOD_EXCEED -(3 << 8) +#define LBA_PERROR_OS_INIT -(4 << 8) + + +#define LBA_ERR_STATUS(x) ( ((x) <= 0)? LBA_FAILURE : LBA_SUCCESS) + +#endif /* LBA_ERROR_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_includes.h linux-2.6.29/drivers/lba_nand/lba_includes.h --- linux-2.6.29/drivers/lba_nand/lba_includes.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_includes.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_includes.h + * \brief This file contains includes files related to PAL and + * MAL layer and also OS specific files. + * $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_includes.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + +#ifndef LBA_INCLUDES_H_ +#define LBA_INCLUDES_H_ + + + +/* LBA NAND driver specific files */ +#include "lba_types.h" +#include "imx31_pal.h" +#include "lba_config.h" +#include "lba_error.h" +#include "lba_mal.h" + +/* OS specific files for NAND driver */ +#if LBA_LINUX +#include /* linux types definition */ +#include /* block device macros */ +#include /* file system related macros */ +#include /* HDIO macros */ +#include /* thread handling */ +#ifdef INTERRUPT_SUPPORT +#include /* interrupt related handling */ +#endif /* INTERRUPT_SUPPORT */ +#endif /* LBA_LINUX */ + +#ifdef LBA_DEBUG_MSG +#define LBA_DEBUG(fmt, args...) printk(KERN_INFO fmt, ## args) +#else /* LBA_NAND_DEBUG */ +#define LBA_DEBUG(fmt, args...) +#endif /* LBA_NAND_DEBUG */ + + +#endif /* LBA_INCLUDES_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_mal.c linux-2.6.29/drivers/lba_nand/lba_mal.c --- linux-2.6.29/drivers/lba_nand/lba_mal.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_mal.c 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,822 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_mal.c + * \brief This source file contains the interface + * implementation for the Media Access Layer, + * MAL + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_mal.c,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ +/* LBA-NAND flash chip: THGVN0G4D1DTG00 2GB 2.7V to 3.6V (TOSHIBA) */ + +/* PAL, MAL and OS specifics files */ +#include "lba_includes.h" +#include +#include + +/* Element for sector multiple */ +static l_uchar g_sector_multiple = CURRENT_SECTOR_MULTIPLE; + +/* Element for denoting the Read Type */ +static l_uchar g_read_type = CURRENT_READ_TYPE; + +/* Element for denoting the write type */ +static l_uchar g_write_type = CURRENT_WRITE_TYPE; + +/* Media Access Layer Function definition */ + +/*! \fn void mal_lba_mdp_init(l_int32 *pstatus) + * \brief This function used to the initialize the + * LBA NAND Chip + * + * \calledby + * DSK_Init(LPCTSTR pContext, LPCVOID lpvBusContext) + * \param pstatus - + * LBA_SUCCESS - NAND chip is + * initialized.
+ * Error Codes - Appropriate error codes will + * be returned. + * + * \return None + * + * \callgraph + */ +int pnp_read(char *dest, int size, int page_num ) +{ + l_int32 status; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + char buff[2112]; + + + memset (buff, 0, sizeof(buff)); + mal_lba_reboot(); + au_sync_delay(10); + mal_lba_pnr_to_bcm(); + au_sync_delay(10); + + addr_byte[2] = (l_uchar)page_num; + addr_byte[4] = 0x08; + pal_send_command(READ_MODE); + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + pal_send_command(READ_START); + pal_get_busy_status(&status); + + /* get the 2112 bytes. 2048 +64 */ + pal_receive_data(buff, 2112); + //dump_data(buff); + memcpy(dest, buff, size); + return 0; +} + + +void mal_lba_reboot() +{ + l_int32 status; + pal_send_command(LBA_CMD_REBOOT); + pal_get_busy_status(&status); + return; +} +void mal_lba_pnr_to_bcm() +{ + l_int32 status; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + pal_send_command(READ_MODE); + addr_byte[3] = CHANGE_TO_BCM; + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + pal_send_command(READ_START); + pal_get_busy_status(&status); +} + + + +void mal_lba_mdp_init(l_int32 *pstatus) +{ + + /* Initialize NAND Flash Memory Controller */ + pal_init_controller(pstatus); + if (LBA_FAILURE == LBA_ERR_STATUS(*pstatus)) { + *pstatus |= LBA_MERROR_DEVICE_INIT; + return; + } + + /* Wait for LBA NAND to get Stable */ + LBA_NAND_RESET_TIME(RESET_TIME); + mal_lba_reboot(); + mdelay( 100 ); + + /* Check if the LBA NAND is ready */ + //pal_get_busy_status(pstatus); + + /* Change the mode to MDP */ + mal_lba_change_mode_to_mdp(pstatus); + mal_set_to_fastest_mode(); + if (LBA_FAILURE == LBA_ERR_STATUS(*pstatus)) { + pal_close_controller(pstatus); + return; + } +} + + +void mal_lba_set_config(l_int32 *pstatus) +{ + l_uchar protocol_data_1 = 0; + l_uchar protocol_data_2 = 0; + + mal_lba_change_mode_to_mdp(pstatus); + + protocol_data_1 = (l_uchar)( CURRENT_SECTOR_MULTIPLE | ECC_DISABLE << 6 ); + + /* Set the protocol in LBA NAND */ + mal_lba_set_protocol_1(protocol_data_1,pstatus); + if (LBA_FAILURE == LBA_ERR_STATUS(*pstatus)) { + return; + } + + /* + * Configure LBA NAND for by protocol_2 configuration + * Write Type = TYPE B + * Read Type = TYPE B + * + */ + protocol_data_2 = (l_uchar)(CURRENT_READ_TYPE | + CURRENT_WRITE_TYPE << 2 ); + + /* Set the protocol in LBA NAND */ + mal_lba_set_protocol_2(protocol_data_2, pstatus); + + if (LBA_FAILURE == LBA_ERR_STATUS(*pstatus)) { + return; + } +} + +/*! \fn void mal_lba_read_id (l_uchar *pdevice_id, + * l_int32 *pstatus) + * \brief This function used to the get the device ID + * LBA NAND Chip + * + * \calledby + * None + * \param pdevice_id - Pointer to an array of 5 bytes + * to store read ID information + * + * \param pstatus- + * LBA_SUCCESS - Read LBA NAND chip ID
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph +*/ +void mal_lba_read_id (l_uchar *pdevice_id, l_int32 *pstatus) +{ + l_uchar address_byte = 0 ; + + pal_send_command(ID_READ_LBA_NAND); + pal_send_address(&address_byte,ID_READ_ADDRESS_BYTES); + + /* Wait until Chip gets ready */ + //pal_get_busy_status (pstatus); + mdelay( 100 ); + pal_receive_data(pdevice_id,ID_READ_DATA_BYTES); +} + + +/*! \fn void mal_lba_read_status_primary (l_uchar *plba_data, + * l_int32 *pstatus ) + * \brief This function is used to the get the primary +n * status such transfer pass or fail,ready + * busy or pass, operation is pass + * or fail of the LBA NAND + * + * \calledby + * mal_lba_enter_power_save_mode(l_int32 *pstatus) etc + * \param plba_data - pointer to a variable to store + * the primary status of the LBA + * NAND + * \param pstatus - + * LBA_SUCCESS - successfully read + * primary status
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_read_status_primary (l_uchar *plba_data, l_int32 *pstatus) +{ + + pal_send_command(PRIMARY_STATUS_READ); + + /* Minimum time to wait is 10 ns */ + + /* Wait for 1 microsecond */ + MICRO_SECOND_DELAY(1); + /* wait until Chip gets ready */ + pal_get_busy_status(pstatus); + pal_receive_data(plba_data , 1); + + +#if READYPIN_WAIT_CHECK_ERROR_PRIMARY + if (!(*plba_data & ERROR_READY_MASK)) { + *pstatus = LBA_MERROR_PRIMARY_READY; + return; + } +#endif /* READYPIN_WAIT_CHECK_ERROR_PRIMARY */ + +} + + + +/*! \fn void mal_lba_change_mode_to_mdp(l_int32 *pstatus) + * \brief This function used to the change the + * LBA NAND from PNR,VFA,PNA mode to MDA mode to access + * the MDP + * + * \calledby + * mal_lba_mdp_init(l_int32 *pstatus), etc + * \param pstatus + * LBA_SUCCESS - Mode changed to MDP
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_change_mode_to_mdp(l_int32 *pstatus) +{ + + pal_send_command(CHANGE_TO_MDP); + + /* wait till LBA NAND gets ready */ + /* wait until Chip gets ready */ + pal_get_busy_status(pstatus); +} + + +/*! \fn void mal_lba_change_mode_to_vfp(l_uint32 password, + * l_int32 *pstatus) + * \brief This function used to the change the + * LBA NAND accessing mode from MDA, PNA to VFA to access + * VFP. + * + * \calledby + * None + * \param password - password to enter VFP partition + * if password is not set before default + * password( 0xFFFF) should be used + * \param pstatus - + * LBA_SUCCESS - Mode is + * changed successfully
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_change_mode_to_vfp(l_uint32 password, + l_int32 *pstatus) +{ + l_uchar primary_status = 0; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {CHANGE_TO_VFP,0,0,0,0}; + + /* Extracting the password information*/ + addr_byte[1] = (l_uchar)(password & MASK_BYTE); + addr_byte[2] = (l_uchar)((password >> BYTE_SHIFT) & MASK_BYTE); + + pal_send_command(READ_MODE); + + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(SET_CONFIGURATION); + + /* wait till LBA NAND gets ready */ + pal_get_busy_status (pstatus); + //mal_lba_read_status_primary(&primary_status, pstatus); + if (LBA_FAILURE == LBA_ERR_STATUS( *pstatus) || + (primary_status & ERROR_STATUS_MASK)) { + *pstatus |= LBA_MERROR_MODE_CHANGE_VFP; + return; + } +} + +/*! \fn void mal_lba_get_mdp_unit(l_uchar *pnum_sector, + l_int32 *pstatus) + * \brief This function used to get the size of MDP + * Partition in LBA NAND Chip + * + * \calledby + * DSK_Init( LPCTSTR pContext, LPCVOID lpvBusContext) + * \param pnum_sector - Pointer to 5 byte character array + * to store the information about the MDP + * size in number of sector. + * ( 1 Sector = 512 Bytes) + * + * \param pstatus - + * LBA_SUCCESS - MDP size returned + * successfully.
+ * Error Codes - Appropriate error codes will + * be returned. + * + * \return None + * + * \callgraph + */ +void mal_lba_get_mdp_unit(l_uchar *pnum_sector, l_int32 *pstatus) +{ + l_uint32 count = 0; + + /* To store the size of MDP partition */ + l_uchar mdp_size_info[MDP_SIZE_INFO_BYTES] = {0,0,0,0,0}; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {GET_MDP_SIZE,0,0,0,0}; + + pal_send_command(READ_MODE); + + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(SET_CONFIGURATION); + + + /* wait till LBA NAND gets ready */ + pal_get_busy_status (pstatus); + pal_receive_data(&mdp_size_info[0],5); + + /* Exrtracting the number of sectors */ + for (count = 0;count < MDP_SIZE_INFO_BYTES; count++) { + *pnum_sector = mdp_size_info[(MDP_SIZE_INFO_BYTES -1) - count]; + pnum_sector ++; + } +} + +void mal_set_to_fastest_mode() +{ + l_int32 pstatus; + + /* To store the size of MDP partition */ + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {EXIT_POWER_SAVE_MODE,0,0,0,0}; + pal_send_command(READ_MODE); + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + pal_send_command(SET_CONFIGURATION); + + /* wait till LBA NAND gets ready */ + pal_get_busy_status (&pstatus); + printk( KERN_INFO "LBA: Disabled power save mode\n" ); + + addr_byte[0] = ENTER_HIGH_SPEED; + pal_send_command(READ_MODE); + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + pal_send_command(SET_CONFIGURATION); + + // wait till LBA NAND gets ready + pal_get_busy_status (&pstatus); + printk( KERN_INFO "LBA: Enabled high speed mode\n" ); +} + +/*! \fn void mal_lba_get_vfp_unit(l_uint32 *pnum_sector, +* l_int32 *pstatus) + * \brief This function used to get the size of VFP + * Partition in LBA NAND Chip + * + * \calledby + * DSK_Init( LPCTSTR pContext, LPCVOID lpvBusContext ); + * \param pnum_sector - Pointer to array to store the + * information about the VFP size + * \param pstatus - + * LBA_SUCCESS - VFP size returned + * successfully
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_get_vfp_unit(l_uint32 *pnum_sector, l_int32 *pstatus) +{ + + /* To store the size of VFP partition */ + l_uchar vfp_size_info[2] = {0x00,0x00}; + + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {GET_VFP_SIZE,0,0,0,0}; + + pal_send_command(READ_MODE); + + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(SET_CONFIGURATION); + + pal_get_busy_status (pstatus); + pal_receive_data(&vfp_size_info[0],2); + + *pnum_sector = 0x0000; + /* Extracting the number of sectors */ + + *pnum_sector = (l_uint32)(vfp_size_info[1] | + (vfp_size_info[0] << BYTE_SHIFT)); + if (*pnum_sector == 0x0000) + *pnum_sector = (l_uint32)MAX_VFP_SIZE; +} + + +/*! \fn void mal_lba_set_protocol_1(l_uchar data, + * l_int32 *pstatus) + * \brief This function used to the set the + * protocol_1 for the LBA NAND Chip + * + * \calledby + * mal_lba_mdp_init(l_int32 *pstatus) + * \param data - holds the protocol data + * \param pstatus - + * LBA_SUCCESS - protocol 1 is + * set in hardware
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_set_protocol_1(l_uchar data,l_int32 *pstatus) +{ + + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] ={SET_PROTOCOL_1,data,0,0,0}; + /* check for input parameters for setting the protocol 1 */ + + if( ((data & ECC_MASK) == ECC_RESERVED) || + !(((data & SECTOR_MULTIPLE_MASK) == SECTOR_MULTIPLE_1) || + ((data & SECTOR_MULTIPLE_MASK) == SECTOR_MULTIPLE_4) || + ((data & SECTOR_MULTIPLE_MASK) == SECTOR_MULTIPLE_8) ) + ) { + *pstatus = LBA_MERROR_PROTOCOL1_SET; + return; + } + + + pal_send_command(READ_MODE); + + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(SET_CONFIGURATION); + + /* Wait till LBA NAND gets ready */ + pal_get_busy_status(pstatus); + + + /* Populating the global variables for sector multipe */ + /* + * Sector multiple set in hardware represents + * below data + * 1 - sector multiple 1 + * 2 - sector multiple 4 + * 4 - sector multiple 8 + * If the same data is maintained, an extra + * multiplication with 2 is required for calculating + * number of iterations in lba_mal_write/read_sectors() + * To avoid that multiplication over head, its being + * done here in Initialization. + */ + + if ((data & SECTOR_MULTIPLE_MASK) > SECTOR_MULTIPLE_1) { + g_sector_multiple = ((data & + SECTOR_MULTIPLE_MASK)* 2); + } else { + g_sector_multiple = SECTOR_MULTIPLE_1; + } +} + + +/*! \fn void mal_lba_set_protocol_2(l_uchar data, + * l_int32 *pstatus) + * \brief This function is used to the set the protocol_2 + * for the LBA NAND Chip + * + * \calledby + * mal_lba_mdp_init(l_int32 *pstatus) + * \param data - protocol data to be set to chip + * \param pstatus - + * LBA_SUCCESS - protocol 2 is + * set in hardware
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_set_protocol_2(l_uchar data, l_int32 *pstatus) +{ + + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {SET_PROTOCOL_2, + data,0,0,0}; + /* check for the input parameter */ + if (((data & READ_TYPE_MASK) == READ_TYPE_RESERVED) || + ( (data & ~(READ_TYPE_MASK | WRITE_TYPE_MASK)) != 0) + ) { + *pstatus = LBA_MERROR_PROTOCOL2_SET; + return; + } + + pal_send_command(READ_MODE); + + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(SET_CONFIGURATION); + + /* wait till LBA NAND gets ready */ + pal_get_busy_status (pstatus); + g_read_type = (data & READ_TYPE_MASK); + g_write_type = ((data & WRITE_TYPE_MASK))>> 2; +} + +/*! \fn void mal_lba_flush_cache (l_int32 *pstatus) + * \brief This function used to the flush the + * cache in LBA NAND Chip to do the final + * operations + * + * \calledby + * DSK_PowerDown(DWORD hDeviceContext ) + * \param pstatus - + * LBA_SUCCESS - protocol 2 is + * set in hardware
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_flush_cache (l_int32 *pstatus) +{ + pal_send_command(FLUSH_CACHE); + + /* wait until LBA NAND gets ready */ + pal_get_busy_status (pstatus); +} + + +/*! \fn void mal_lba_read_sector(l_uchar *pdata_buf, + * l_uint32 sector_count,l_uint32 sector_addr, + * l_int32 *pstatus) + * \brief This function is used to the read the data + * from LBA NAND Chip in terms of sectors + * + * \calledby + * DSK_IOControl( DWORD dwOpenContext,DWORD dwIoControlCode, + * PBYTE pbInBuf, + * DWORD dwInBufSize, + * PBYTE pbOutBuf, + * DWORD dwOutBufSize, + * PDWORD pdwBytesReturned ); + * \param pdata_buf - Pointer to the buffer to which + * the data has to be read + * \param sector_count - Number of sectors to be read + * \param sector_addr - Start Sector address + * + * \param pstatus - + * LBA_SUCCESS - Read is success
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ + +void mal_lba_read_sector(l_uchar *pdata_buf, l_uint32 sector_count, + l_uint32 sector_addr, l_int32 *pstatus) +{ + l_uint32 count = 0; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + l_uchar dummy_addr[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + + l_uint32 max_transfer_size = SECTOR_SIZE_512 * g_sector_multiple; + l_uint32 actual_size = SECTOR_SIZE_512 * sector_count; + l_uint32 temp_sector_count = 0; + l_uint32 data_size = max_transfer_size; + + /* Extracting the address bytes based on input */ + do + { + temp_sector_count = sector_count; + if(temp_sector_count > MAX_SECTOR_COUNT) + { + temp_sector_count = MAX_SECTOR_COUNT; + } + actual_size = temp_sector_count * SECTOR_SIZE_512; + for (count = 0;count < TOTAL_ADDRESS_BYTES;count++) { + if (count> + (BYTE_SHIFT * count)) & MASK_BYTE); + } + else { + addr_byte[count] = (l_uchar)((sector_addr >> + (BYTE_SHIFT *(count - SECTOR_COUNT_BYTES)))& + MASK_BYTE); + } + } + + /* Initiating the read operation */ + pal_send_command(READ_MODE); + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + pal_send_command(READ_START); + pal_get_busy_status(pstatus);/* wait until Chip gets ready */ + + + do { + /* + Check if the number of bytes to be read is more than + the number of bytes that can be read within a single + read operation + */ + if (actual_size < max_transfer_size) { + data_size = actual_size; + } + + pal_receive_data(pdata_buf,data_size); + actual_size -= data_size; + if (actual_size == 0) { + break; + } + + pdata_buf += data_size; /* update the data buffer */ + + switch(g_read_type) { + + case READ_TYPE_B: + /* Initiating the further read operation */ + pal_send_command(READ_CONTINUE); + + /* wait until Chip gets ready */ + pal_get_busy_status (pstatus); + + break; + + case READ_TYPE_A: + /* Initiating the further read operation */ + pal_send_command(READ_MODE); + + pal_send_address(&dummy_addr[0], + TOTAL_ADDRESS_BYTES); + + pal_send_command(READ_START); + + /* wait until LBA NAND gets ready */ + pal_get_busy_status (pstatus); + break; + + case READ_TYPE_C : + /* wait until Chip gets ready */ + pal_get_busy_status (pstatus); + break; + + default: + *pstatus |= LBA_MERROR_READ_TYPE; + break; + + } /* switch() */ + + } while(1); + sector_count -= temp_sector_count; + }while (sector_count); +} + +/*! \fn void mal_lba_write_sector(l_uchar *pdata_buf, + * l_uint32 sector_count, l_uint32 sector_addr, + * l_int32 *pstatus) + * \brief This function used to the write the data to + * LBA NAND Chip + * + * \calledby + * DSK_IOControl( DWORD dwOpenContext, DWORD dwIoControlCode, + * PBYTE pbInBuf, + * DWORD dwInBufSize, + * PBYTE pbOutBuf, + * DWORD dwOutBufSize, + * PDWORD pdwBytesReturned ); + * \param pdata_buf - Pointer to the buffer which + * contains the data to be written + * \param sector_count - Number of sectors to write + * \param sector_addr - Start Sector address + * + * \param pstatus - + * LBA_SUCCESS - Write is success
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ + void mal_lba_write_sector(l_uchar *pdata_buf, l_uint32 sector_count, + l_uint32 sector_addr, l_int32 *pstatus) + { + l_uint32 count; + l_uchar addr_byte[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + l_uchar dummy_addr[TOTAL_ADDRESS_BYTES] = {0,0,0,0,0}; + l_uint32 temp_sector_count = 0; + l_uint32 max_transfer_size = SECTOR_SIZE_512 * g_sector_multiple; + l_uint32 actual_size = 0; + l_uint32 data_size = max_transfer_size; + + /* Extracting the address bytes based on input */ + do + { + temp_sector_count = sector_count; + if(temp_sector_count > MAX_SECTOR_COUNT ) + { + temp_sector_count = MAX_SECTOR_COUNT; + } + actual_size = temp_sector_count * SECTOR_SIZE_512; + for (count = 0; count < TOTAL_ADDRESS_BYTES; count++) + { + if (count < SECTOR_COUNT_BYTES) { + addr_byte[count] = (l_uchar)((temp_sector_count >> + (BYTE_SHIFT * count)) & MASK_BYTE); + } + else { + addr_byte[count] = (l_uchar)((sector_addr >> + (BYTE_SHIFT * (count - SECTOR_COUNT_BYTES)))\ + & MASK_BYTE); + } + } + + /* Initiating the write operation */ + pal_send_command(SERIAL_DATA_INPUT); + pal_send_address(&addr_byte[0],TOTAL_ADDRESS_BYTES); + + while(actual_size != 0) + { + /* + Calculating the number of bytes to be written + between each Busy cycle with respect to the sector multiple + */ + if (actual_size < max_transfer_size) { + data_size = actual_size; + } + + pal_send_data (pdata_buf, data_size); + + switch(g_write_type) { + + case WRITE_TYPE_B: + + /* Write operation continued for Write Type B */ + if (actual_size > max_transfer_size) { + pal_send_command(WRITE_CONTINUE); + } + else { + pal_send_command(AUTO_PROGRAM); + } + + /* wait until Chip gets ready */ + pal_get_busy_status (pstatus); + + /* update the data buffer pointer */ + pdata_buf += data_size; + actual_size -= data_size; + + if (actual_size != 0) { + /* Initiating the further write operation */ + pal_send_command(SERIAL_DATA_INPUT); + } + break; + + case WRITE_TYPE_A: + + pal_send_command(AUTO_PROGRAM); + + /* wait until Chip gets ready */ + pal_get_busy_status (pstatus); + /* update the data buffer pointer */ + pdata_buf += data_size; + actual_size -= data_size; + + if (actual_size != 0) { + /* Initiating the further write operation */ + pal_send_command(SERIAL_DATA_INPUT); + pal_send_address(&dummy_addr[0], + TOTAL_ADDRESS_BYTES); + } + break; + + default: + *pstatus |= LBA_MERROR_WRITE_TYPE; + break; + } /* switch */ + } /* while */ + sector_count -= temp_sector_count; + }while(sector_count); +} + + +/*! \fn void mal_lba_mdp_close(l_int32 *pstatus) + * \brief This function used to close the nand controller + * and to free the virtual memory + * \param pstatus - + * LBA_SUCCESS -password changed successfully
+ * Error Codes - Appropriate error codes will + * be returned. + * \return None + * + * \callgraph + */ +void mal_lba_mdp_close(l_int32 *pstatus) +{ + pal_close_controller(pstatus); +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_mal.h linux-2.6.29/drivers/lba_nand/lba_mal.h --- linux-2.6.29/drivers/lba_nand/lba_mal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_mal.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_mal.h + * \brief This header file contains the structure and + * function declaration for the Media Access Layer, + * MAL(LBA NAND Specific ) + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_mal.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + + /* LBA NAND Flash Chip : THGVN0G4D1DTG00 2GB 2.7 V - 3.6 V(Toshiba) */ + +#ifndef MAL_H_ +#define MAL_H_ + +#include "lba_types.h" +#include "lba_config.h" + +/* LBA NAND Commands */ + +/* Global variable for LBA NAND protocol */ +#define TRUE 1 +#define FALSE 0 + +/* Macro to generate delay required for LBA nand reset */ +#define LBA_NAND_RESET_TIME(milli_second) { \ + volatile l_uint32 tick_count;\ + for (tick_count = 0; \ + tick_count < (MILLISECOND_COUNT * (milli_second)); \ + tick_count++); \ + } + +/* Global macro for sector multiple */ +#define CURRENT_SECTOR_MULTIPLE SECTOR_MULTIPLE_1 + +/* Global macro for default Read type */ +#define CURRENT_READ_TYPE READ_TYPE_B + +/* Global macro for default Write type */ +#define CURRENT_WRITE_TYPE WRITE_TYPE_B + +/* Macros - Commands LBA NAND */ + +#define READ_MODE (0x00) +#define READ_START (0x30) +#define READ_CONTINUE (0xF8) +#define SERIAL_DATA_INPUT (0x80) +#define AUTO_PROGRAM (0x10) +#define WRITE_CONTINUE (0x15) +#define READ_RETRANSFER (0x31) +#define CHANGE_TO_MDP (0xFC) +#define CHANGE_TO_BCM (0xFC) +#define SET_CONFIGURATION (0x57) +#define ERASE_MODE (0x60) +#define AUTO_BLOCK_ERASE (0xD0) +#define RESET (0xFF) +#define ID_READ_SLC_NAND (0x90) +#define ID_READ_LBA_NAND (0x92) +#define PRIMARY_STATUS_READ (0x70) +#define SECONDARY_STATUS_READ (0x71) +#define TERMINATE_READ_WRITE (0xFB) +#define FLUSH_CACHE (0xF9) +#define SET_PASSWORD (0x21) +#define LBA_CMD_REBOOT (0xFD) + + +/* Macros - Address fields of LBA NAND */ + +#define CHANGE_TO_PNA (0xBF) +#define CHANGE_TO_VFP (0xBE) +#define CHANGE_VFP_SIZE (0x22) +#define GET_VFP_SIZE (0xB5) +#define GET_MDP_SIZE (0xB0) +#define SET_PROTOCOL_1 (0xA2) +#define GET_PROTOCOL_1 (0xB2) +#define SET_PROTOCOL_2 (0xA3) +#define GET_PROTOCOL_2 (0xB3) +#define SET_MIN_BUSY_TIME (0xA4) +#define GET_MIN_BUSY_TIME (0xB4) +#define ENTER_POWER_SAVE_MODE (0xBA) +#define EXIT_POWER_SAVE_MODE (0xBB) +#define ENTER_HIGH_SPEED (0xBC) +#define EXIT_HIGH_SPEED (0xBD) +#define GET_ADDRESS_INFO (0xB6) +#define DUMMY_ADDRESS_BYTE (0x00) +#define DEFAULT_PASSWORD (0xFFFF) + +/* Macros - Data fields of LBA NAND */ + +#define SECTOR_SIZE_512 512 +#define SECTOR_SIZE_528 528 +#define SECTOR_DATA_PNP 2048 +#define SPARE_DATA_PNP 64 +#define NUM_SPARE_BYTES 16 +#define TRANSFER_UNIT_PNP 2112 +#define SECTOR_MULTIPLE_MASK 0x1F +#define SECTOR_MULTIPLE_1 1 +#define SECTOR_MULTIPLE_4 2 +#define SECTOR_MULTIPLE_8 4 +#define READ_WRITE_FAIL 7 +#define READ_TYPE_A 0 +#define READ_TYPE_B 2 +#define READ_TYPE_C 3 +#define READ_TYPE_RESERVED 0x01 +#define WRITE_TYPE_A 0 +#define WRITE_TYPE_B 1 +#define TRANSFER_SIZE_MASK 0x20 +#define TRANSFER_SIZE_512 0 +#define TRANSFER_SIZE_528 1 +#define ECC_MASK 0xC0 +#define ECC_RESERVED 0x40 +#define ECC_DISABLE 0 + +#ifdef LBANAND_REV_0961 +#define CRC_ENABLE +#endif /* LBANAND_REV_0961 */ + +#define ECC_CHECK_ENABLE 2 +#define ECC_CHECK_CORRECT 3 + +/* Macros - For logic */ + +#define SECTOR_COUNT_BYTES 2 +#define SECTOR_ADDRESS_BYTES 3 +#define MAX_SECTOR_COUNT 65535 +#define ID_READ_ADDRESS_BYTES 1 +#define ID_READ_DATA_BYTES 5 +#define MDP_SIZE_INFO_BYTES 5 +#define TOTAL_ADDRESS_BYTES 5 +#define BYTE_SHIFT 8 + +#ifdef LBANAND_REV_0961 +#define ERROR_STATUS_MASK 7 +#else /* LBANAND_REV_0961 */ +#define ERROR_STATUS_MASK 5 +#endif /* LBANAND_REV_0961 */ + +#define ERROR_READY_MASK 0x40 +#define MAX_VFP_SIZE 65536 +#define MODE_BIT_MASK 0x06 +#define PNR_MODE 0 +#define PNP_MAINTAINANCE_MODE 2 +#define VFA_MODE 4 +#define MDA_MODE 6 +#define MASK_BYTE 0xFF +#define MASK_NIBBLE 0x0F +#define HIGH_SPEED_WRITE_MASK 8 +#define POWER_SAVE_MODE_MASK 1 +#define MICRO_SECOND_DELAY_COUNT 154 +#define RESET_TIME 500 +#define MIN_VFP_SECTOR_SIZE 16384 +#define MAX_VFP_SECTOR_SIZE 65536 +#define SECTOR_MULTIPLE_MASK 0x1F +#define READ_TYPE_MASK 0x03 +#define WRITE_TYPE_MASK 0x04 + +/* Macros for Busy time level */ +#define TIME_LEVEL_0 0 +#define TIME_LEVEL_1 1 +#define TIME_LEVEL_2 2 +#define TIME_LEVEL_3 4 +#define TIME_LEVEL_4 8 +#define TIME_LEVEL_5 16 +#define TIME_LEVEL_6 32 +#define TIME_LEVEL_7 64 +#define TIME_LEVEL_8 128 +#define TIME_LEVEL_9 129 +#define TIME_LEVEL_10 130 +#define TIME_LEVEL_11 134 + +/** + * @ingroup H_1_1 + * @addtogroup H_1_1_2 LBA-NAND Driver MAL layer API set + * This section contains explanation about APIs + * exported by the LBA-NAND driver to be used by OS layer or by + * MAL layer itself. + * @{ + */ +/* MAL Layer function declarations */ +void mal_lba_mdp_init(l_int32 *pstatus); +void mal_lba_set_config(l_int32 *pstatus); +void mal_lba_mdp_close(l_int32 *pstatus); +void mal_lba_read_id (l_uchar *pdevice_id, l_int32 *pstatus); + +void mal_lba_change_mode_to_mdp (l_int32 *pstatus); +void mal_lba_change_mode_to_vfp(l_uint32 password,l_int32 *pstatus); +void mal_lba_get_mdp_unit(l_uchar *pnum_sector, l_int32 *pstatus); +void mal_lba_get_vfp_unit(l_uint32 *pnum_sector, l_int32 *pstatus); +void mal_lba_read_status_primary(l_uchar *plba_status,l_int32 *pstatus); +void mal_lba_set_protocol_1(l_uchar data, l_int32 *pstatus); +void mal_lba_set_protocol_2(l_uchar data, l_int32 *pstatus); +void mal_lba_read_sector(l_uchar *pdata_buf, l_uint32 sector_count, + l_uint32 sector_addr,l_int32 *pstatus); +void mal_lba_write_sector(l_uchar *pdata_buf, l_uint32 sector_count, + l_uint32 sector_addr,l_int32 *pstatus); +void mal_lba_flush_cache (l_int32 *pstatus); +void mal_lba_reboot(void); +void mal_lba_pnr_to_bcm(void); + +void mal_lba_print_min_busy_time( void ); +void mal_set_to_fastest_mode( void ); +/** + * @} + */ +#endif /* MAL_H_ */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_nand.h linux-2.6.29/drivers/lba_nand/lba_nand.h --- linux-2.6.29/drivers/lba_nand/lba_nand.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_nand.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2007 - 2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_nand.h + * \brief This header file contains the LBA-NAND driver OS + * specific structures and function declarations + * + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_nand.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + +#ifndef LBA_NAND_H +#define LBA_NAND_H + +#include +#include + +/* driver major number */ +#define LBA_NAND_MAJOR 0 +/* maximum number of partions */ +#define LBA_NAND_MINORS 16 +/* Device sector size */ +#define LBA_NAND_SECTOR_SIZE 512 +/* flie system sector size */ +#define KERNEL_SECTOR_SIZE_BYTES 512 +/* size in bytes */ +#define DEVICE_MANUFACTURER_ID_SIZE 5 + + +/* structure contains manufacturer code and name */ +struct nand_manufacturers +{ + char id[DEVICE_MANUFACTURER_ID_SIZE]; + char name[20]; +}; + +/* LBA-NAND specific information structure */ + +struct lba_nand_info +{ + /* add the LBA NAND Related information here */ + struct nand_manufacturers nand_manufacturer; + u_int32_t sector_size; + u_int32_t nsectors; /* LBA-NAND device size in sectors */ + struct module *owner; + void *priv; +}; + +/* control structure for LBA-NAND driver */ + +struct lba_nand_blk_dev +{ + int count; /* number of time open is called */ + struct mutex dev_lock;/* Lock to access LBA-NAND device*/ + spinlock_t q_lock; /* locking kernel structure */ + struct request_queue *req_queue; /* The device request queue */ + struct gendisk *gen_disk; /* The gendisk structure */ + struct task_struct *thread; /* read/write thread */ + struct lba_nand_info *lba_nand; /* device info */ +}; + +/* IOCTL input argumnet structure */ + +struct lba_nand_raw +{ + int flags;/* type of R/W (can be used later)*/ + void __user *user_data; + uint64_t num_sect; + uint64_t start_sect; +}; +#ifdef LBA_ENABLE_ERR_STRINGS + +/* Define error strings/messages */ +static u_char const *lba_err_pal_ptr[] = { + TEXT(""), TEXT("DEVICE FAILURE"), + TEXT("IO TO MEMORY MAPPING"), + TEXT("BUSY WAIT PERIOD EXCEEDED"), + TEXT("OS SPECIFIC INITIALIZATION FAILED") +}; + +static u_char const *lba_err_mal_ptr[] = { + TEXT(""), TEXT("MDA MODE CHANGE FAILURE"), + TEXT("VFP MODE CHANGE FAILURE"), + TEXT("PNP MODE CHANGE FAILURE"), TEXT("VFP SIZE CHANGE FAILURE"), + TEXT("READ SECTOR FAILURE"), TEXT("IMPROPER READ TYPE"), + TEXT("WRITE SECTOR FAILURE"),TEXT("IMPROPER WRITE TYPE"), + TEXT("READ PAGE FAILURE"), + TEXT("WRITE PAGE FAILURE"), TEXT("PROTOCOL1 SET FAILURE"), + TEXT("PROTOCOL2_SET FAILURE"),TEXT("EXIT HIGH SPEED FAILURE"), + TEXT(" ENTER HIGH SPEED FAILURE"),TEXT("EXIT LOW POWER FAILURE"), + TEXT("ENTER LOW POWER FAILURE "), TEXT("SET PASSWORD FAILURE"), + TEXT("SET MINIMUM BUSY TIME"), TEXT("CACHE FLUSH FAILURE"), + TEXT("TERMINATE READ WRITE FAILURE"), + TEXT("READ RETRANSFER FAILURE"), + TEXT("DEVICE INITIALIZATION FAILURE"), + TEXT(" READY BIT OF PRIMARY STATUS FAILURE"), + TEXT("READ CONFIGURATION FAILURE") +}; + + +#define GET_PAL_ERR_STR(error_code) \ +( lba_err_pal_ptr[((error_code) * -1) >> 8]) +#define GET_MAL_ERR_STR(error_code) \ +( lba_err_mal_ptr[((error_code) * -1) & 0xff]) + +#else /* LBA_ENABLE_ERR_STRINGS */ + +#define GET_PAL_ERR_STR(error_code) TEXT("") +#define GET_MAL_ERR_STR(error_code) TEXT("") + +#endif /* LBA_ENABLE_ERR_STRINGS */ + +/* ioctl shoud be unique number*/ +#define LBANAND_READ_VFP _IOR(2, 0x10, struct lba_nand_raw) +#define LBANAND_WRITE_VFP _IOW(2, 0x11, struct lba_nand_raw) + + +/* function prototypes for lba-nand block driver operations */ + +static int lba_nand_open(struct inode *idx_node, struct file *file_ptr); +static int lba_nand_release(struct inode *idx_node, struct file *file_ptr); +static int lba_nand_ioctl(struct inode *idx_node, struct file *file_ptr, + unsigned int ioctl_num, unsigned long data_ptr); +static int lba_nand_getgeo(struct block_device *blk_dev, \ + struct hd_geometry *hd_geo); + +#endif /* LBA_NAND_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_nand_main.c linux-2.6.29/drivers/lba_nand/lba_nand_main.c --- linux-2.6.29/drivers/lba_nand/lba_nand_main.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_nand_main.c 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,976 @@ +/* + * Copyright (C) 2007 - 2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_nand.c + * \brief This source file contains the Block Driver OS + * specific interface implementation for the LBA-NAND device + * + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_nand.c,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ +/* Linux kernel 2.6.22 */ + +/* following header files are included for Linux Block Driver */ + +#include "lba_includes.h" /* LBA-NAND device and OS specific files */ +#include /* LBA-NAND driver specific types */ +#include + +/* Block device operations structure contains pointer to + * driver interface functions + */ + +static struct block_device_operations lba_nand_fops = +{ + .owner = THIS_MODULE, + .open = lba_nand_open, + .release = lba_nand_release, + .ioctl = lba_nand_ioctl, + .getgeo = lba_nand_getgeo, + .media_changed = NULL, + .revalidate_disk = NULL, +}; + +static int nand_flash_ioctl(struct inode *idx_node, \ + struct file *file_ptr, unsigned int ioctl_num,\ + unsigned long data_ptr); +static int nand_flash_open(struct inode *idx_node, struct file *file_ptr); +static const struct file_operations nand_flash_fops = { + .owner = THIS_MODULE, + .ioctl = nand_flash_ioctl, + .open = nand_flash_open, +}; + +enum au1xx_nand_ops{ + LBANAND_READ_MDP, + LBANAND_WRITE_MDP, + LBANAND_RAW_READ_VFP, + LBANAND_RAW_WRITE_VFP, + LBANAND_INFO +}; + +struct lbanand_info{ + uint64_t num_mdp_sec; + uint64_t num_vfp_sec; +}; + + +/* variable to hold the size of VFP in sectors */ +static unsigned long g_vfp_size = 0; +/* pointer to hold LBA-NAND device information */ +static struct lba_nand_blk_dev *lba_dev = NULL; +/* variable used to hold MAJOR number of LBA-NAND driver */ +static uint32_t lba_major = 0; + +/* Function prototypes for static functions */ + +static int lba_nand_transfer(unsigned long start_sector, \ + unsigned long nsector, unsigned char *buffer,\ + int write); +static int lba_nand_device_init(struct lba_nand_blk_dev *dev); +static int lba_blktrans_thread(void *arg); +static void lba_nand_do_request(struct request_queue *req_q); + +/* Block driver operations function definitions */ + +/*! \fn static int __init lba_nand_init(void) + * \brief This is the initialization function used to initialize the + * LBA-NAND Chip and LBA-NAND block driver. + * + * If the function succeeds then LBA-NAND device is available + * to the kernel. If this function fails due to some reason + * then the driver will not be available for the kernel. + * On failure this function returns appropriate error code + * and frees all the allocated resourses.This function + * initializes file operations structure and request processing + * queue required for data transfers to/from the LBA-NAND chip. + * + * Note: Currently driver allocates dynamic major number but static + * major number can be used instead. Static major number can be + * defined in /rpm/BUILD/linux-2.6.22/ + * include/linux/lba_nand.h file + * + * \param none + * \return 0 on success or appropriate error code on failure + * to the kernel + * + * \callgraph This function is called at the time of booting + */ +#define TOSHIBA_NAND_CHAR_MAJOR 96 + +static int __init lba_nand_init(void) +{ + int error = 0; + int drive = 0; + long int status = LBA_SUCCESS; + + printk( KERN_INFO "LBA-NAND initializing... \n" ); + + /* Allocate dynamic major number */ + lba_major = register_blkdev(0, "lbanand"); + if (lba_major <= 0) { + printk(KERN_ERR "lba-nand: unable to register\n"); + return -EBUSY; + } + printk("Registered with major = %d \n", lba_major); + + if (register_chrdev(TOSHIBA_NAND_CHAR_MAJOR, "au1xx_nand", &nand_flash_fops)) { + printk(KERN_NOTICE "Can't allocate major number %d for Memory Technology Devices.\n", + TOSHIBA_NAND_CHAR_MAJOR); + return -EAGAIN; + } + + /* Allocate memory for LBA-NAND device structure and private data */ + lba_dev = kmalloc(sizeof(struct lba_nand_blk_dev) + + sizeof(struct lba_nand_info), GFP_KERNEL); + if (!lba_dev) { + printk(KERN_ERR "Unable to allocate LBA-NAND device"\ + " structure.\n"); + error = -ENOMEM; + goto lba_out_error; + } + + /* Initialize structures */ + memset((char *)lba_dev, 0, sizeof(struct lba_nand_blk_dev) + + sizeof(struct lba_nand_info)); + lba_dev->lba_nand = (struct lba_nand_info *) ((char *) lba_dev + + sizeof(struct lba_nand_blk_dev)); + + /* Initialize mutex and spin lock*/ + mutex_init(&lba_dev->dev_lock); + spin_lock_init(&lba_dev->q_lock); + + /* Initialize the Request queue */ + lba_dev->req_queue = blk_init_queue(lba_nand_do_request, + &lba_dev->q_lock); + if (lba_dev->req_queue == NULL) { + printk(KERN_ERR "Unable to initialize the request " \ + "queue\r\n"); + error = -ENOMEM; + goto lba_out_error; + } + + /* set hardware sector size in the queue */ + blk_queue_hardsect_size(lba_dev->req_queue, LBA_NAND_SECTOR_SIZE); + + lba_dev->thread = kthread_run(lba_blktrans_thread, \ + lba_dev->req_queue, "%s", "LBA-NAND"); + if (IS_ERR(lba_dev->thread)) { + error = PTR_ERR((lba_dev->thread)); + goto lba_out_error; + } + + /* Allocate and initialize the gendisk structure */ + lba_dev->gen_disk = alloc_disk(LBA_NAND_MINORS); + if (!lba_dev->gen_disk) { + printk (KERN_ERR "alloc_disk failure\n"); + error = -ENOMEM; + goto lba_out_error; + } + lba_dev->gen_disk->major = lba_major; + lba_dev->gen_disk->first_minor = drive * LBA_NAND_MINORS; + lba_dev->gen_disk->minors = LBA_NAND_MINORS; + + sprintf(lba_dev->gen_disk->disk_name, "lbanand%d", drive); + /* Initialize file operations structure */ + lba_dev->gen_disk->fops = &lba_nand_fops; + lba_dev->gen_disk->queue = lba_dev->req_queue; + + /* Get pointer to private data */ + /* Link the private data with the LBA-NAND structure */ + + lba_dev->gen_disk->private_data = lba_dev; + + /* Call hardware control function to initialize the iMX31-NAND + * controller and LBA-NAND chip initialize the lba_dev + */ + if (lba_nand_device_init(lba_dev)) { + error = -ENXIO; + goto lba_out_error; + } + + /* set the device capacity */ + set_capacity(lba_dev->gen_disk, lba_dev->lba_nand->nsectors \ + * (LBA_NAND_SECTOR_SIZE / KERNEL_SECTOR_SIZE_BYTES)); + /* At this point the disk is available to the kernel and + * should never fail from this onwards + */ + add_disk(lba_dev->gen_disk); + printk( KERN_INFO " success.\n" ); + return error; + +lba_out_error: + printk(KERN_INFO "failed\n"); + if (lba_major > 0) + unregister_blkdev(lba_major, "lbanand"); + /* Clean up the kernel thread */ + if (lba_dev->thread) + kthread_stop(lba_dev->thread); + if (lba_dev->gen_disk) { + del_gendisk(lba_dev->gen_disk); + put_disk(lba_dev->gen_disk); + } + if (lba_dev) + kfree (lba_dev); + /* uninitialize device specific memory */ + mal_lba_mdp_close(&status); + mal_lba_reboot(); + return error; + +} + +/*! \fn static void __exit lba_nand_cleanup(void) + * \brief This function is used to close and + * unregister the lba-nand driver + * from linux kernel + * + * \param none + * \return none + * + * \callgraph This function is automatilly called by the kernel + */ +static void __exit lba_nand_cleanup(void) +{ + long int status = 0; + + mutex_lock(&lba_dev->dev_lock); + + /* perform device specific de-initialization */ + mal_lba_mdp_close(&status); + /*Reset the LBA-NAND device.*/ + mal_lba_reboot(); + + kthread_stop(lba_dev->thread); + unregister_blkdev(lba_major, "lbanand"); + + unregister_chrdev(TOSHIBA_NAND_CHAR_MAJOR, "au1xx_nand"); + + del_gendisk(lba_dev->gen_disk); + put_disk(lba_dev->gen_disk); + blk_cleanup_queue(lba_dev->req_queue); + /* stops thread created by driver */ + + mutex_unlock(&lba_dev->dev_lock); + + /* Free the LBA-NAND device structure */ + if(lba_dev) + kfree(lba_dev); +} + +void verify_id_signature( uint8_t* device_id, long int* status ) +{ + printk( "ID Bytes: %2.2X %2.2X %2.2X %2.2X %2.2X\n", device_id[0], + device_id[1], device_id[2], device_id[3], device_id[4] ); + if ( device_id[3] != 0x55 || device_id[4] != 0xAA ) + { + printk( KERN_ERR "LBA-NAND ID Signature check failure.\n" ); + printk( KERN_ERR "ID Bytes: %2.2X %2.2X %2.2X %2.2X %2.2X\n", device_id[0], + device_id[1], device_id[2], device_id[3], device_id[4] ); + *status = LBA_PERROR_DEVICE_FAILURE; + return; + } + + // Only Toshiba brand LBA-NAND devices are currently supported + if ( device_id[0] != 0x98 ) + { + printk( KERN_ERR "Not a supported LBA-NAND device\n" ); + *status = LBA_PERROR_DEVICE_FAILURE; + return; + } + + if ( device_id[1] != 0x21 ) + { + printk( KERN_ERR "Not an LBA-NAND device\n" ); + *status = LBA_PERROR_DEVICE_FAILURE; + return; + } +} + +/*! \fn static int lba_nand_device_init( + * struct lba_nand_blk_dev *dev) + * \brief This function is used to initialize the NAND controller + * and LBA-NAND device + * + * \param dev: lba_nand_blk_dev structure + * \return 0: success, -1: failure + * + * \callgraph This function is called by lba_nand_init + */ +static int lba_nand_device_init(struct lba_nand_blk_dev *dev) +{ + uint8_t device_id[DEVICE_MANUFACTURER_ID_SIZE] = {0}; + long int status = 0; + uint8_t mdp_size[MDP_SIZE_INFO_BYTES]; + + mal_lba_mdp_init(&status); + + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "Failed to initialize device "\ + "Reason:%s,%s\r\n",GET_MAL_ERR_STR(status),\ + GET_PAL_ERR_STR(status)); + return -1; + } + + mal_lba_read_id(device_id, &status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "Failed to get device-id" "device Reason:" + "%s, %s\r\n", GET_MAL_ERR_STR(status), + GET_PAL_ERR_STR(status)); + return -1; + } + + verify_id_signature( device_id, &status ); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "Failed to verify ID signature: " "Reason:" + "%s, %s\r\n", GET_MAL_ERR_STR(status), + GET_PAL_ERR_STR(status)); + return -1; + } + + /* Get MDP size */ + mal_lba_get_mdp_unit(mdp_size, &status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "Failed to get mdp size " "device Reason: " + "%s,%s\r\n", GET_MAL_ERR_STR(status), + GET_PAL_ERR_STR(status)); + return -1; + } + + /* converting array of 5 bytes in number format the size cannot + * go beyond 3 bytes (for 2/4/8 GB) */ + dev->lba_nand->nsectors = mdp_size[4] | (mdp_size[3] << BYTE_SHIFT)\ + | (mdp_size[2] << (BYTE_SHIFT * 2)) \ + | (mdp_size[1] << (BYTE_SHIFT * 3)); + + /* get the VFP size info for sanity check in VFP read and write */ + mal_lba_get_vfp_unit(&g_vfp_size, &status); + + printk("Number of sectors MDP = 0x%lx and g_vfp_size = 0x%lx \n ", dev->lba_nand->nsectors, g_vfp_size); + + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "Failed to get vfp size " + "device Reason: %s,%s\r\n",GET_MAL_ERR_STR(status), + GET_PAL_ERR_STR(status)); + return -1; + } + + + /* add the LBA-NAND Related information here */ + /* copy the NAND-ID into nand_manufacturer structure */ + memcpy(dev->lba_nand->nand_manufacturer.id, device_id, + DEVICE_MANUFACTURER_ID_SIZE); + strcpy(dev->lba_nand->nand_manufacturer.name, "TOSHIBA"); + /* sector size in bytes */ + dev->lba_nand->sector_size = SECTOR_SIZE_512; + dev->lba_nand->owner = THIS_MODULE; + dev->lba_nand->priv = NULL; /* for future additions */ + + + return 0; +} + +/*! \fn static int lba_nand_open(struct inode *idx_node, + * struct file *file_ptr); + * \brief This function is used to open the lba-nand device + * + * \param idx_node: index node(inode) structure + * file_ptr: file structure pointer + * \return returns 0 currently + * + * \callgraph This function is called by the kernel when + * the device is opened + */ + +static int nand_flash_open(struct inode *idx_node, struct file *file_ptr) +{ + LBA_DEBUG(KERN_INFO "nand_flash_open() called"); + return 0; + +} + +static int lba_nand_open(struct block_device *block, fmode_t mode) +{ + struct lba_nand_blk_dev *dev_info = block->bd_disk->private_data; + l_uint32 status; + + LBA_DEBUG(KERN_INFO "lba_nand_open() called"); + /* incrementing the count for reference */ + mutex_lock(&dev_info->dev_lock); + mal_lba_set_config(&status); + dev_info->count++; + mutex_unlock(&dev_info->dev_lock); + + return 0; +} + +/*! \fn static int lba_nand_release(struct inode *idx_node, + struct file *file_ptr); + * \brief This function is used to open the lba-nand device + * + * \param idx_node: index node(inode) structure + * file_ptr: file structure pointer + * \return returns 0 + * + * \callgraph This function is called by the kernel when the device + * is closed + */ +static int lba_nand_release(struct gendisk* disk, fmode_t mode) +{ + struct lba_nand_blk_dev *dev_info = disk->private_data; + + LBA_DEBUG("lba_nand_release()\r\n"); + + mutex_lock(&dev_info->dev_lock); + dev_info->count--; + mutex_unlock(&dev_info->dev_lock); + + return 0; +} + +/*! \fn static int lba_nand_ioctl(struct inode *idx_node, + * struct file *file_ptr, unsigned int ioctl_num, + * unsigned long data_ptr); + * \brief This function is used to control the lba-nand + * device from the user space + * + * \param idx_node: index node(inode) structure + * file_ptr: file structure pointer + * ioctl_num: IOCTL command for the lba-nand driver + * data_ptr: this parameter is both I/O + * i.e. based on the command input + * \return returns 0 on success or appropriate kernel error code + * + * \callgraph This function is called by the kernel on behalf + * of the user request to ioctl() system call + */ + +static inline void dump_data(void *addr) +{ + int idx; + int *p = (int *)addr; + for(idx=0; idx< (512/4); idx++ ){ + printk( "addr idx line %x = 0x%x\n", idx*4 , *p ); + p++; + } + return; +} + +static int nand_flash_ioctl(struct inode *idx_node, \ + struct file *file_ptr, unsigned int ioctl_num,\ + unsigned long data_ptr) +{ + int retval = 0; + switch (ioctl_num) { + case LBANAND_READ_MDP: + { + uint32_t size = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl(case IOCTL_READ_MDP:) \n"); + if (copy_from_user( &data, (void __user *) data_ptr, sizeof(data))){ + printk("Failed to copy from user \n"); + return -EFAULT; + } + + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + //printk("lba_nand_transfer startsec = 0x%llx , data.num_sect = 0x%llx \n", data.start_sect, data.num_sect); + retval = lba_nand_transfer(data.start_sect, data.num_sect, kernel_data, 0); + //dump_data(kernel_data); + + if(!retval){ + printk("Failed to read sector \n"); + kfree(kernel_data); + return retval; + } + if (copy_to_user(data.user_data, kernel_data, size)){ + printk("Failed to copy into user for = %d bytes \n", size); + kfree(kernel_data); + return -EFAULT; + } + + kfree(kernel_data); + } + + break; + + case LBANAND_WRITE_MDP: + { + uint32_t size = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl case IOCTL_WRITE_MDP \n"); + if (copy_from_user( &data, (void __user *) data_ptr, sizeof(data))){ + printk("Failed to get data form user from location %p \n", (void __user *) data_ptr); + return -EFAULT; + } + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + + if (copy_from_user(kernel_data, data.user_data, size)){ + printk("Failed to get user data form user from location %p \n", data.user_data ); + return -EFAULT; + } + + retval = lba_nand_transfer(data.start_sect, data.num_sect, kernel_data, 1); + + if(!retval){ + printk("Failed to Write sector \n"); + kfree(kernel_data); + return retval; + } + kfree(kernel_data); + } + break; + + case LBANAND_RAW_READ_VFP: + { + long int status = LBA_SUCCESS; + uint32_t size = 0, error = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl(case IOCTL_READ_VFP:) \n"); + if (copy_from_user( &data, (void __user *) data_ptr, sizeof(data))) + return -EFAULT; + if ((data.start_sect + data.num_sect) > g_vfp_size) + return -EFAULT; + + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + + mutex_lock(&lba_dev->dev_lock); + + mal_lba_change_mode_to_vfp(DEFAULT_PASSWORD, &status); + if (LBA_SUCCESS == LBA_ERR_STATUS(status)) { + mal_lba_read_sector(kernel_data, data.num_sect, data.start_sect, &status); + //dump_data(kernel_data); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() read failed\n"); + error = 1; + } else { + if (copy_to_user(data.user_data, kernel_data, size)) + error = 1; + } + } else { + printk(KERN_ERR "lbanand ioctl unable to enter VFP"); + error = 1; + } + mal_lba_change_mode_to_mdp(&status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() unable to enter" \ + "MDA mode\r\n"); + error = 1; + } + mutex_unlock(&lba_dev->dev_lock); + kfree(kernel_data); + return error ? -EFAULT : 0; + } + break; + + case LBANAND_RAW_WRITE_VFP: + { + long int status = LBA_SUCCESS; + uint32_t error = 0, size = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl case IOCTL_WRITE_VFP \n"); + + if (copy_from_user( &data, (void __user *) data_ptr, sizeof(data))) + return -EFAULT; + if ((data.start_sect + data.num_sect) > g_vfp_size) + return -EFAULT; + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + if (copy_from_user(kernel_data, data.user_data, size)) + return -EFAULT; + + mutex_lock(&lba_dev->dev_lock); + + mal_lba_change_mode_to_vfp(DEFAULT_PASSWORD, &status); + if (LBA_SUCCESS == LBA_ERR_STATUS(status)) { + //dump_data(kernel_data); + mal_lba_write_sector(kernel_data, data.num_sect, data.start_sect, &status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() write failed\r\n"); + error = 1; + } + } + else { + printk(KERN_ERR "lbanand ioctl unable to enter VFP"); + error = 1; + } + mal_lba_change_mode_to_mdp(&status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() unable to enter MDA mode\r\n"); + error = 1; + } + mutex_unlock(&lba_dev->dev_lock); + kfree(kernel_data); + return error ? -EFAULT : 0; + } + break; + + case LBANAND_INFO: + { + uint8_t mdp_size[MDP_SIZE_INFO_BYTES]; + long int status = 0; + uint32_t num_sec; + struct lbanand_info data; + + mutex_lock(&lba_dev->dev_lock); + mal_lba_get_mdp_unit(mdp_size, &status); + mutex_unlock(&lba_dev->dev_lock); + + num_sec = mdp_size[4] | (mdp_size[3] << BYTE_SHIFT)\ + | (mdp_size[2] << (BYTE_SHIFT * 2)) \ + | (mdp_size[1] << (BYTE_SHIFT * 3)); + data.num_mdp_sec = num_sec; + data.num_vfp_sec = g_vfp_size; + if (copy_to_user( (void __user *) data_ptr, &data, sizeof(struct lbanand_info))){ + printk("Failed to copy to user \n"); + return -EFAULT; + } + + } + break; + + + default: + printk("Unknown IOCTL \n"); + break; + } + return retval; +} + +static int lba_nand_ioctl(struct block_device *block, fmode_t mode, + unsigned int ioctl_num, unsigned long data_ptr) +{ + struct lba_nand_blk_dev *dev_info = block->bd_disk->private_data; + struct hd_geometry hd_geo; + + + switch (ioctl_num) { + + case BLKFLSBUF: /* flush buffer cache */ + { + long int status = LBA_SUCCESS; + LBA_DEBUG(KERN_WARNING "lba_nand_ioctl(case BLKFLSBUF)\n"); + mal_lba_flush_cache(&status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) + return -EFAULT; + else + return 0; + } + break; + + case BLKGETSIZE64: + { + u_int64_t size = 0; + printk( "IOCTL: BLKGETSIZE64: " ); + size = dev_info->lba_nand->nsectors \ + * dev_info->lba_nand->sector_size; + if (!copy_to_user((void __user *) data_ptr, &size, \ + sizeof(size))) + return -EFAULT; + } + return 0; + break; + + case HDIO_GETGEO: + /* copy the geometry information */ + hd_geo.cylinders = 16065; + hd_geo.heads = 255; + hd_geo.sectors = dev_info->lba_nand->nsectors + * (LBA_NAND_SECTOR_SIZE / KERNEL_SECTOR_SIZE_BYTES); + hd_geo.start = 0; + if (!copy_to_user((void __user *) data_ptr, &hd_geo, \ + sizeof(hd_geo))) + return -EFAULT; + else + return 0; + break; + + case LBANAND_READ_VFP: + { + long int status = LBA_SUCCESS; + uint32_t size = 0, error = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl(case IOCTL_READ_VFP:)"); + if (!copy_from_user((void __user *) data_ptr, &data,\ + sizeof(data))) + return -EFAULT; + if ((data.start_sect + data.num_sect) > g_vfp_size) + return -EFAULT; + + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + mutex_lock(&dev_info->dev_lock); + + mal_lba_change_mode_to_vfp(DEFAULT_PASSWORD, &status); + if (LBA_SUCCESS == LBA_ERR_STATUS(status)) { + mal_lba_read_sector(kernel_data, data.num_sect, + data.start_sect, &status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() read failed\n"); + error = 1; + } else { + if (!copy_to_user((void __user *)data.user_data, + kernel_data, size)) + error = 1; + } + } else { + printk(KERN_ERR "lbanand ioctl unable to enter VFP"); + error = 1; + } + mal_lba_change_mode_to_mdp(&status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() unable to enter" \ + "MDA mode\r\n"); + error = 1; + } + mutex_unlock(&dev_info->dev_lock); + kfree(kernel_data); + return error ? -EFAULT : 0; + } + break; + + case LBANAND_WRITE_VFP: + { + long int status = LBA_SUCCESS; + uint32_t error = 0, size = 0; + struct lba_nand_raw data = {0}; + void *kernel_data = NULL; + + LBA_DEBUG(KERN_INFO "lba_nand_ioctl case IOCTL_WRITE_VFP"); + + if (!copy_from_user((void __user *) data_ptr, &data,\ + sizeof(data))) + return -EFAULT; + if ((data.start_sect + data.num_sect) > g_vfp_size) + return -EFAULT; + size = data.num_sect * LBA_NAND_SECTOR_SIZE; + kernel_data = kmalloc(size, GFP_USER); + if (!kernel_data) + return -ENOMEM; + if (!copy_from_user(kernel_data, \ + (void __user *)data.user_data, size)) + return -EFAULT; + + mutex_lock(&dev_info->dev_lock); + mal_lba_change_mode_to_vfp(DEFAULT_PASSWORD, &status); + if (LBA_SUCCESS == LBA_ERR_STATUS(status)) { + mal_lba_write_sector(kernel_data, data.num_sect, + data.start_sect, &status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() "\ + "write failed\r\n"); + error = 1; + } + } + else { + printk(KERN_ERR "lbanand ioctl unable to enter VFP"); + error = 1; + } + mal_lba_change_mode_to_mdp(&status); + if (LBA_FAILURE == LBA_ERR_STATUS(status)) { + printk(KERN_ERR "lbanand ioctl() unable to enter" + "MDA mode\r\n"); + error = 1; + } + mutex_unlock(&dev_info->dev_lock); + kfree(kernel_data); + return error ? -EFAULT : 0; + } + break; + + default: + printk( "Unsupported IOCTL\n" ); + /* LBA_DEBUG(KERN_ERR "lba_nand_ioctl(case:default val = %x)\n", + ioctl_num); */ + /* return blk_ioctl(idx_node->i_rdev, ioctl_num, data_ptr); */ + break; + } + return -ENOTTY; /* unknown command */ +} + +/*! \fn static int lba_nand_getgeo(struct block_device *blk_dev, + * struct hd_geometry *hd_geo); + * \brief This function is used to query the geometry of the + * lba-nand device + * + * \param bdev: block device structure + * hd_geo: pointer to geometry structure + * \return returns 0 + * \callgraph This function is called by the kernel automatically + */ +static int lba_nand_getgeo(struct block_device *blk_dev, + struct hd_geometry *hd_geo) +{ + /* dereference the bd pointer and assign the device info */ + struct lba_nand_blk_dev *dev_info = blk_dev->bd_disk->private_data; + + LBA_DEBUG(KERN_INFO "lba_nand_getgeo()\n"); + + /* copy the information to geo structure */ + hd_geo->cylinders = 16065; + hd_geo->heads = 255; + hd_geo->sectors = dev_info->lba_nand->nsectors \ + * (LBA_NAND_SECTOR_SIZE / KERNEL_SECTOR_SIZE_BYTES); + hd_geo->start = 0; + + return 0; +} + +/*! \fn static int lba_blktrans_thread(void *arg); + * \brief This function is the Linux kernel thread used to + * process the LBA-NAND transaction requests. Thread will + * disable the interrupt and checks the request queue, if + * there is no request on the queue it relinquishes + * the control and sleeps until wakeup call from the + * reuqest processing functiion. + * \param arg: This is the pointer to the request queue + * structure passed at thread creation time + * + * \return 0: on success, memory error on failure + * \callgraph This function is scheduled by kernel automatically + * based on block requests + */ +static int lba_blktrans_thread(void *arg) +{ + struct request_queue *req_q = arg; + struct request *cur_req = NULL; + int err = 0; + + LBA_DEBUG(KERN_INFO "lba_blktrans_thread()\n"); + + if (req_q == NULL) { + LBA_DEBUG(KERN_INFO "error:lba_blktrans_thread() request queue " + "is NULL\r\n"); + return PTR_ERR((req_q)); + } + + spin_lock_irq(&lba_dev->q_lock); + while (!kthread_should_stop()) { + cur_req = elv_next_request(req_q); + if (!cur_req) { + set_current_state(TASK_INTERRUPTIBLE); + spin_unlock_irq(&lba_dev->q_lock); + schedule(); + spin_lock_irq(&lba_dev->q_lock); + continue; + } + + if (! blk_fs_request(cur_req)) { + LBA_DEBUG(KERN_NOTICE "Skip non-fs request\n"); + end_request(cur_req, 0); + continue; + } +#ifdef INTERRUPT_SUPPORT + spin_unlock_irq(&lba_dev->q_lock); +#endif + err = lba_nand_transfer(cur_req->sector, \ + cur_req->current_nr_sectors, cur_req->buffer, \ + rq_data_dir(cur_req)); + +#ifdef INTERRUPT_SUPPORT + spin_lock_irq(&lba_dev->q_lock); +#endif + end_request(cur_req, err); + } + spin_unlock_irq(&lba_dev->q_lock); + + return 0; +} + +/*! \fn static void lba_nand_transfer(unsigned long start_sector, + * unsigned long nsector, unsigned char *buffer, int write); + * \brief This function is used to transfer the data to/from + * LBA-NAND device + * + * \param start_sector:start sector number to be read/written + * nsector: number of sectors to be read from or written + * to buffer: memory data buffer to be + * read / written + * write: flag to indicate whether to read or write + * operation + * 0: read operation, 1: write operation + * \return This function returns 1 for success and 0 on failure + * \callgraph This function is called by kernel thread + * lba_blktrans_thread() + */ + +static int lba_nand_transfer(unsigned long start_sector, \ + unsigned long nsector, \ + unsigned char *buffer, int write) +{ + long int status = LBA_SUCCESS; + int error = 1; /* 0 is for failure condition */ + + LBA_DEBUG(KERN_INFO "lba_nand_transfer()\n"); + + if ((start_sector + nsector) > lba_dev->lba_nand->nsectors) { + printk(KERN_ERR "Beyond-end write (%ld %ld)\n",start_sector, + nsector); + return error; + } + mutex_lock(&lba_dev->dev_lock); + if (write) { + /* Call to MAL layer */ + mal_lba_write_sector(buffer, nsector, start_sector, &status); + /* check for the errors*/ + if (LBA_FAILURE == LBA_ERR_STATUS(status)) + { + printk(KERN_ERR "lba_nand_transfer() failed to write\n"); + error = 0; + } + } + else { + /* Call to MAL layer */ + mal_lba_read_sector(buffer, nsector, start_sector, &status); + /* check for the errors*/ + if (LBA_FAILURE == LBA_ERR_STATUS(status)) + { + printk(KERN_ERR "lba_nand_transfer() failed to read\n"); + error = 0; + } + + } + mutex_unlock(&lba_dev->dev_lock); + return error; +} + + + +/*! \fn static void lba_nand_do_request(request_queue *req_q); + * \brief This function is used for request processing + * + * \param req_q: pointer to block device request structure which + * contains pointer to device data structure. + * \return none + * \callgraph This function is called by the kernel + */ +static void lba_nand_do_request(struct request_queue *req_q) +{ + wake_up_process(lba_dev->thread); +} + +module_init(lba_nand_init); +module_exit(lba_nand_cleanup); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/lba_types.h linux-2.6.29/drivers/lba_nand/lba_types.h --- linux-2.6.29/drivers/lba_nand/lba_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/lba_types.h 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. + * + *! \file lba_types.h + * \brief This source file contains definitions of the data tyes + * used in the implementation of the Media Access Layer + * MAL and Platform Specific Layer.The data types are + * pre-fixed by a 'l' to signify that the data type is + * defined for LBA NAND + ** $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ + * $Id: lba_types.h,v 1.3 2008/04/03 15:03:14 rowen Exp $ + * + */ + + +#ifndef LBA_TYPES_H +#define LBA_TYPES_H + +typedef unsigned long int l_uint32; +typedef long int l_int32; +typedef unsigned short l_uint16; +typedef unsigned char l_uchar; + +#endif /* LBA_TYPES_H */ + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/lba_nand/Makefile linux-2.6.29/drivers/lba_nand/Makefile --- linux-2.6.29/drivers/lba_nand/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/lba_nand/Makefile 2009-05-29 16:11:37.000000000 -0400 @@ -0,0 +1,14 @@ +# Copyright (C) 2007-2008 TOSHIBA Corporation, All Rights Reserved. +# +# file: Makefile +# brief: This file describes the rules for building the LBA-NAND driver +# $Name: ALPHA_1_0_2_LBA_Linux_IMX31 $ +# $Id: Makefile,v 1.3 2008/04/03 15:03:14 rowen Exp $ +# + + +lba_nand-objs := lba_nand_main.o lba_mal.o au1xxx_pal.o +obj-$(CONFIG_LBA_NAND) += lba_nand.o +ifeq ($(CONFIG_LBA_DEBUG_MSG),y) +EXTRA_CFLAGS += -DLBA_DEBUG_MSG +endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/Makefile linux-2.6.29/drivers/Makefile --- linux-2.6.29/drivers/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/Makefile 2009-08-13 23:07:03.000000000 -0400 @@ -50,6 +50,7 @@ obj-y += cdrom/ obj-y += auxdisplay/ obj-$(CONFIG_MTD) += mtd/ +obj-$(CONFIG_LBA_NAND) += lba_nand/ obj-$(CONFIG_SPI) += spi/ obj-$(CONFIG_PCCARD) += pcmcia/ obj-$(CONFIG_DIO) += dio/ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/au1x00.h linux-2.6.29/drivers/media/alchemy/au1x00.h --- linux-2.6.29/drivers/media/alchemy/au1x00.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/au1x00.h 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,4710 @@ +/********************************************************************* + * + * Copyright: + * Advanced Micro Devices, AMD. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or +// * otherwise under any patents or trademarks of AMD. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, AMD + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * AMD assumes no responsibility for the maintenance and support + * of this software. + ********************************************************************/ + +/* + * File: au1x00.h + * + * Purpose: Definitions for Au1x00 integrated peripherals + * + * Notes: Authoritative description of Au1x00 peripherals + * + * Date: 26-Feb-2004 + * + * Modifications: + * + */ + +#ifndef _AU1X00_H +#define _AU1X00_H + +/***********************************************************************/ + +/* + * CP0 registers + */ +#define CP0_Index $0 +#define CP0_Random $1 +#define CP0_EntryLo0 $2 +#define CP0_EntryLo1 $3 +#define CP0_Context $4 +#define CP0_PageMask $5 +#define CP0_Wired $6 +#define CP0_BadVAddr $8 +#define CP0_Count $9 +#define CP0_EntryHi $10 +#define CP0_Compare $11 +#define CP0_Status $12 +#define CP0_Cause $13 +#define CP0_EPC $14 +#define CP0_PRId $15 +#define CP0_Config $16 +#define CP0_Config0 $16 +#define CP0_Config1 $16,1 +#define CP0_LLAddr $17 +#define CP0_WatchLo $18 +#define CP0_IWatchLo $18,1 +#define CP0_WatchHi $19 +#define CP0_IWatchHi $19,1 +#define CP0_Scratch $22 +#define CP0_Debug $23 +#define CP0_DEPC $24 +#define CP0_PerfCnt $25 +#define CP0_PerfCtrl $25,1 +#define CP0_DTag $28 +#define CP0_DData $28,1 +#define CP0_ITag $29 +#define CP0_IData $29,1 +#define CP0_ErrorEPC $30 +#define CP0_DESave $31 + +#define CP0_PRID_REV 0x0000000F +#define CP0_PRID_IMP 0x000000F0 +#define CP0_SR_IE 0x00000001 + +/***********************************************************************/ + +/* + * AC97 Register Offsets + */ +#define AC97_CONFIG (0x0000) +#define AC97_STATUS (0x0004) +#define AC97_DATA (0x0008) +#define AC97_CMMD (0x000C) +#define AC97_CMMDRESP (0x000C) +#define AC97_ENABLE (0x0010) + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 config; + uint32 status; + uint32 data; + uint32 cmmd; +#define cmmdresp cmmd + uint32 enable; + +} AU1X00_AC97; +#endif + +/* + * Register content definitions + */ +#define AC97_CONFIG_RC (0x3FF<<13) +#define AC97_CONFIG_XS (0x3FF<<3) +#define AC97_CONFIG_SG (1<<2) +#define AC97_CONFIG_SN (1<<1) +#define AC97_CONFIG_RS (1<<0) +#define AC97_CONFIG_XS_N(N) (N<<3) + +#define AC97_STATUS_XU (1<<11) +#define AC97_STATUS_XO (1<<10) +#define AC97_STATUS_RU (1<<9) +#define AC97_STATUS_RO (1<<8) +#define AC97_STATUS_RD (1<<7) +#define AC97_STATUS_CP (1<<6) +#define AC97_STATUS_TE (1<<4) +#define AC97_STATUS_TF (1<<3) +#define AC97_STATUS_RE (1<<1) +#define AC97_STATUS_RF (1<<0) + +#define AC97_CMMD_WRITEDATA (0xFFFF<<16) +#define AC97_CMMD_RW (1<<7) +#define AC97_CMMD_INDEX (0x3F<<0) +#define AC97_CMMD_WRITEDATA_N(N) (N<<16) +#define AC97_CMMD_RW_RD (1<<7) +#define AC97_CMMD_RW_WR (0<<7) +#define AC97_CMMD_INDEX_N(N) (N<<0) + +#define AC97_ENABLE_D (1<<1) +#define AC97_ENABLE_CE (1<<0) + +/********************************************************************/ + +/* + * DMA Register Offsets (from DMA module) + */ + +#define DMA_MODEREAD (0x0000) +#define DMA_MODESET (0x0000) +#define DMA_MODECLR (0x0004) +#define DMA_PERADDR (0x0008) +#define DMA_BUF0ADDR (0x000C) +#define DMA_BUF0SIZE (0x0010) +#define DMA_BUF1ADDR (0x0014) +#define DMA_BUF1SIZE (0x0018) + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 moderead; +#define modeset moderead + uint32 modeclr; + uint32 peraddr; + uint32 buf0addr; + uint32 buf0size; + uint32 buf1addr; + uint32 buf1size; + uint32 reserved[57]; +} AU1X00_DMA; +#endif + +/* + * DMA_MODESET/DMA_MODECLR register content definitions + */ +#define DMA_MODE_DAH (15<<20) +#define DMA_MODE_DID (15<<16) +#define DMA_MODE_DS (1<<15) +#define DMA_MODE_BE (1<<13) +#define DMA_MODE_DR (1<<12) +#define DMA_MODE_TS (1<<11) +#define DMA_MODE_DW (3<<9) +#define DMA_MODE_DW_8 (0<<9) +#define DMA_MODE_DW_16 (1<<9) +#define DMA_MODE_DW_32 (2<<9) +#define DMA_MODE_NC (1<<8) +#define DMA_MODE_IE (1<<7) +#define DMA_MODE_H (1<<6) +#define DMA_MODE_G (1<<5) +#define DMA_MODE_AB (1<<4) +#define DMA_MODE_D1 (1<<3) +#define DMA_MODE_BE1 (1<<2) +#define DMA_MODE_D0 (1<<1) +#define DMA_MODE_BE0 (1<<0) +#define DMA_MODE_DAH_N(N) (N<<20) +#define DMA_MODE_DID_N(N) (N<<16) + +// DMA Device IDs when DMA_MODE_DS==0 +#define DMA_MODE_DID_UART0_TX 0 +#define DMA_MODE_DID_UART0_RX 1 +#define DMA_MODE_DID_GP04 2 +#define DMA_MODE_DID_GP05 3 +#define DMA_MODE_DID_AC97_TX 4 +#define DMA_MODE_DID_AC97_RX 5 +#define DMA_MODE_DID_UART3_TX 6 +#define DMA_MODE_DID_UART3_RX 7 +#define DMA_MODE_DID_USB_EP0_RX 8 +#define DMA_MODE_DID_USB_EP0_TX 9 +#define DMA_MODE_DID_USB_EP1_TX 10 +#define DMA_MODE_DID_USB_EP2_TX 11 +#define DMA_MODE_DID_USB_EP3_RX 12 +#define DMA_MODE_DID_USB_EP4_RX 13 +#define DMA_MODE_DID_I2S_TX 14 +#define DMA_MODE_DID_I2S_RX 15 + +// DMA Device IDs when DMA_MODE_DS==1 +#define DMA_MODE_DID_SD0_TX 0 +#define DMA_MODE_DID_SD0_RX 1 +#define DMA_MODE_DID_SD1_TX 2 +#define DMA_MODE_DID_SD1_RX 3 + +/* + * DMA_BUFSIZE register content definitions + */ +#define DMA_BUFSIZE_BAH (15<<15) +#define DMA_BUFSIZE_COUNT (65535<<0) +#define DMA_BUFSIZE_BAH_N(N) (N<<15) +#define DMA_BUFSIZE_COUNT_N(N) (N<<0) + +#define NUM_DMA_CHANNELS 8 + + +/***********************************************************************/ + +/* + * GPIO2 Register Offsets + */ + +#define GPIO2_DIR 0x0000 +#define GPIO2_OUTPUT 0x0008 +#define GPIO2_PINSTATE 0x000C +#define GPIO2_INTEN 0x0010 +#define GPIO2_ENABLE 0x0014 + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 dir; + uint32 reserved; + uint32 output; + uint32 pinstate; + uint32 inten; + uint32 enable; + +} AU1X00_GPIO2; +#endif + +/* + * Register content definitions + */ +#define GPIO2_GPIO200 0x0001 +#define GPIO2_GPIO201 0x0002 +#define GPIO2_GPIO202 0x0004 +#define GPIO2_GPIO203 0x0008 +#define GPIO2_GPIO204 0x0010 +#define GPIO2_GPIO205 0x0020 +#define GPIO2_GPIO206 0x0040 +#define GPIO2_GPIO207 0x0080 +#define GPIO2_GPIO208 0x0100 +#define GPIO2_GPIO209 0x0200 +#define GPIO2_GPIO210 0x0400 +#define GPIO2_GPIO211 0x0800 +#define GPIO2_GPIO212 0x1000 +#define GPIO2_GPIO213 0x2000 +#define GPIO2_GPIO214 0x4000 +#define GPIO2_GPIO215 0x8000 + +#define GPIO2_ENABLE_MR 0x0002 +#define GPIO2_ENABLE_CE 0x0001 + +#define GPIO2_DIR_DATA (0) +#define GPIO2_DIR_DATA_MSK (0xFFFF<>2]; + uint32 cfg0rd; +#define cfg0set cfg0rd + uint32 cfg0clr; + uint32 cfg1rd; +#define cfg1set cfg1rd + uint32 cfg1clr; + uint32 cfg2rd; +#define cfg2set cfg2rd + uint32 cfg2clr; +#define req0int cfg2clr + uint32 srcrd; +#define srcset srcrd + uint32 srcclr; +#define req1int srcclr + uint32 assignrd; +#define assignset assignrd + uint32 assignclr; + uint32 wakerd; +#define wakeset wakerd + uint32 wakeclr; + uint32 maskrd; +#define maskset maskrd + uint32 maskclr; + uint32 risingrd; +#define risingclr risingrd + uint32 fallingrd; +#define fallingclr fallingrd + uint32 testbit; + +} AU1X00_IC; +#endif + +/***********************************************************************/ + +/* + * IrDA Register Offsets + */ + +#define IR_RNGPTRSTAT (0x0000) +#define IR_RNGBSADRH (0x0004) +#define IR_RNGBSADRL (0x0008) +#define IR_RINGSIZE (0x000C) +#define IR_RNGPROMPT (0x0010) +#define IR_RNGADRCMP (0x0014) +#define IR_INTCLEAR (0x0018) +#define IR_CONFIG1 (0x0020) +#define IR_SIRFLAGS (0x0024) +#define IR_STATUSEN (0x0028) +#define IR_RDPHYCFG (0x002C) +#define IR_WRPHYCFG (0x0030) +#define IR_MAXPKTLEN (0x0034) +#define IR_RXBYTECNT (0x0038) +#define IR_CONFIG2 (0x003C) +#define IR_ENABLE (0x0040) + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 rngptrstat; + uint32 rngbsadrh; + uint32 rngbsadrl; + uint32 ringsize; + uint32 rngprompt; + uint32 rngadrcmp; + uint32 intclear; + uint32 reserved; + uint32 config1; + uint32 sirflags; + uint32 statusen; + uint32 rdphycfg; + uint32 wrphycfg; + uint32 maxpktlen; + uint32 rxbytecnt; + uint32 config2; + uint32 enable; + +} AU1X00_IRDA; +#endif + +/* + * Register content definitions + */ + +#define IR_RNGPTRSTAT_TRPI (63<<8) +#define IR_RNGPTRSTAT_RRPI (63<<0) + +#define IR_RINGSIZE_TRBS_S (12) +#define IR_RINGSIZE_TRBS_N(N) ((N)<>12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) + +/* + * MEM_SDREFCFG register content definitions + */ +#define MEM_SDREFCFG_TRC (15<<28) +#define MEM_SDREFCFG_TRPM (3<<26) +#define MEM_SDREFCFG_E (1<<25) +#define MEM_SDREFCFG_RE (0x1ffffff<<0) +#define MEM_SDREFCFG_TRC_N(N) ((N)<>4) +#define MEM_STADDR_CSMASK_N(N) ((N)&(0x3FFF<<18)>>18) + +/* + * * MEM_STTIME register definitions for use with + * * NAND. + * */ +#define MEM_STTIME_TSU (15<<8) +#define MEM_STTIME_TPUL (15<<4) +#define MEM_STTIME_TH (15<<0) +#define MEM_STTIME_TSU_N(N) (N<<8) +#define MEM_STTIME_TPUL_N(N) (N<<4) +#define MEM_STTIME_TH_N(N) (N<<0) + +#define MEM_STADDR_E (1<<28) +#define MEM_STADDR_CSBA (0x3FFF<<14) +#define MEM_STADDR_CSMASK (0x3FFF<<0) +#define MEM_STADDR_CSBA_N(N) ((N)&(0x3FFF<<18)>>4) +#define MEM_STADDR_CSMASK_N(N) ((N)&(0x3FFF<<18)>>18) + +#define MEM_STALTIME_TAH (7<<6) +#define MEM_STALTIME_TLW (7<<3) +#define MEM_STALTIME_TASU (7<<0) +#define MEM_STALTIME_TAH_N(N) (N<<6) +#define MEM_STALTIME_TLW_N(N) (N<<3) +#define MEM_STALTIME_TASU_N(N) (N<<0) + +#define MEM_STNDCTRL_ECR (1<<28) +#define MEM_STNDCTRL_WFRD (1<<26) +#define MEM_STNDCTRL_WFRI (1<<25) +#define MEM_STNDCTRL_FFDM (1<<24) +#define MEM_STNDCTRL_NEIM (1<<23) +#define MEM_STNDCTRL_FIM (1<<22) +#define MEM_STNDCTRL_SNIM (1<<21) +#define MEM_STNDCTRL_DFIM (1<<20) +#define MEM_STNDCTRL_DFS (1<<19) +#define MEM_STNDCTRL_RECE (1<<17) +#define MEM_STNDCTRL_ECE (1<<16) +#define MEM_STNDCTRL_IE (1<<8) +#define MEM_STNDCTRL_CS3O (1<<7) +#define MEM_STNDCTRL_CS2O (1<<6) +#define MEM_STNDCTRL_CS1O (1<<5) +#define MEM_STNDCTRL_CS0O (1<<4) +#define MEM_STNDCTRL_BOOT (1<<0) + +#define MEM_STSTAT_RFNE (1<<23) +#define MEM_STSTAT_RFF (1<<22) +#define MEM_STSTAT_SN (1<<21) +#define MEM_STSTAT_DF (1<<20) +#define MEM_STSTAT_NEC (31<<8) +#define MEM_STSTAT_PWT (1<<5) +#define MEM_STSTAT_EWT (1<<4) +#define MEM_STSTAT_BOOT (3<<1) +#define MEM_STSTAT_BSY (1<<0) + +/***********************************************************************/ + +/* + * SYStem Register Offsets + */ + +/* Clocks */ +#define SYS_FREQCTRL0 (0x0020) +#define SYS_FREQCTRL1 (0x0024) +#define SYS_CLKSRC (0x0028) +#define SYS_CPUPLL (0x0060) +#define SYS_AUXPLL (0x0064) +#define SYS_AUXPLL2 (0x0068) + +/* TOY & RTC */ +#define SYS_TOYTRIM (0x0000) +#define SYS_TOYWRITE (0x0004) +#define SYS_TOYMATCH0 (0x0008) +#define SYS_TOYMATCH1 (0x000C) +#define SYS_TOYMATCH2 (0x0010) +#define SYS_CNTRCTRL (0x0014) +#define SYS_TOYREAD (0x0040) +#define SYS_RTCTRIM (0x0044) +#define SYS_RTCWRITE (0x0048) +#define SYS_RTCMATCH0 (0x004C) +#define SYS_RTCMATCH1 (0x0050) +#define SYS_RTCMATCH2 (0x0054) +#define SYS_RTCREAD (0x0058) + +/* GPIO */ +#define SYS_PINFUNC (0x002C) +#define SYS_TRIOUTRD (0x0100) +#define SYS_TRIOUTCLR (0x0100) +#define SYS_OUTPUTRD (0x0108) +#define SYS_OUTPUTSET (0x0108) +#define SYS_OUTPUTCLR (0x010C) +#define SYS_PINSTATERD (0x0110) +#define SYS_PININPUTEN (0x0110) + +/* Power Management */ +#define SYS_SCRATCH0 (0x0018) +#define SYS_SCRATCH1 (0x001C) +#define SYS_SCRATCH2 (0x002C) +#define SYS_SCRATCH3 (0x0030) +#define SYS_WAKEMSK (0x0034) +#define SYS_ENDIAN (0x0038) +#define SYS_POWERCTRL (0x003C) +#define SYS_WAKESRC (0x005C) +#define SYS_SLPPWR (0x0078) +#define SYS_SLEEP (0x007C) + +#ifndef ASSEMBLER +typedef volatile struct +{ + /* 0x0000 */ uint32 toytrim; + /* 0x0004 */ uint32 toywrite; + /* 0x0008 */ uint32 toymatch0; + /* 0x000C */ uint32 toymatch1; + /* 0x0010 */ uint32 toymatch2; + /* 0x0014 */ uint32 cntrctrl; + /* 0x0018 */ uint32 scratch0; + /* 0x001C */ uint32 scratch1; + /* 0x0020 */ uint32 freqctrl0; + /* 0x0024 */ uint32 freqctrl1; + /* 0x0028 */ uint32 clksrc; + union + { + /* 0x002C */ uint32 pinfunc; // pre Au13xx + /* 0x002C */ uint32 scratch2; // Au13xx + }; + union + { + /* 0x0030 */ uint32 reserved0; // pre Au13xx + /* 0x0030 */ uint32 scratch3; // Au13xx + }; + /* 0x0034 */ uint32 wakemsk; + /* 0x0038 */ uint32 endian; + /* 0x003C */ uint32 powerctrl; + /* 0x0040 */ uint32 toyread; + /* 0x0044 */ uint32 rtctrim; + /* 0x0048 */ uint32 rtcwrite; + /* 0x004C */ uint32 rtcmatch0; + /* 0x0050 */ uint32 rtcmatch1; + /* 0x0054 */ uint32 rtcmatch2; + /* 0x0058 */ uint32 rtcread; + /* 0x005C */ uint32 wakesrc; + /* 0x0060 */ uint32 cpupll; + /* 0x0064 */ uint32 auxpll; + union + { + /* 0x0068 */ uint32 reserved1; // pre Au13xx + /* 0x0068 */ uint32 auxpll2; // Au13xx + }; + /* 0x006C */ uint32 reserved2; + /* 0x0070 */ uint32 reserved3; + /* 0x0074 */ uint32 reserved4; + /* 0x0078 */ uint32 slppwr; + /* 0x007C */ uint32 sleep; + /* 0x0080 */ uint32 reserved5[32]; + /* 0x0100 */ uint32 trioutrd; +#define trioutclr trioutrd + /* 0x0104 */ uint32 reserved6; + /* 0x0108 */ uint32 outputrd; +#define outputset outputrd + /* 0x010C */ uint32 outputclr; + /* 0x0110 */ uint32 pinstaterd; +#define pininputen pinstaterd + +} AU1X00_SYS; +#endif + +/* + * Register content definitions + */ + +/* Clocks */ +#define SYS_FREQCTRL0_SCALE (1<<30) +#define SYS_FREQCTRL0_FRDIV2 (255<<22) +#define SYS_FREQCTRL0_FE2 (1<<21) +#define SYS_FREQCTRL0_FS2 (1<<20) +#define SYS_FREQCTRL0_FRDIV1 (255<<12) +#define SYS_FREQCTRL0_FE1 (1<<11) +#define SYS_FREQCTRL0_FS1 (1<<10) +#define SYS_FREQCTRL0_FRDIV0 (255<<2) +#define SYS_FREQCTRL0_FE0 (1<<1) +#define SYS_FREQCTRL0_FS0 (1<<0) +#define SYS_FREQCTRL0_FRDIV2_N(N) ((N/2)-1<<22) +#define SYS_FREQCTRL0_FRDIV1_N(N) ((N/2)-1<<12) +#define SYS_FREQCTRL0_FRDIV0_N(N) ((N/2)-1<<2) + +#define SYS_FREQCTRL1_SCALE (1<<30) +#define SYS_FREQCTRL1_FRDIV5 (255<<22) +#define SYS_FREQCTRL1_FE5 (1<<21) +#define SYS_FREQCTRL1_FS5 (1<<20) +#define SYS_FREQCTRL1_FRDIV4 (255<<12) +#define SYS_FREQCTRL1_FE4 (1<<11) +#define SYS_FREQCTRL1_FS4 (1<<10) +#define SYS_FREQCTRL1_FRDIV3 (255<<2) +#define SYS_FREQCTRL1_FE3 (1<<1) +#define SYS_FREQCTRL1_FS3 (1<<0) +#define SYS_FREQCTRL1_FRDIV5_N(N) ((N/2)-1<<22) +#define SYS_FREQCTRL1_FRDIV4_N(N) ((N/2)-1<<12) +#define SYS_FREQCTRL1_FRDIV3_N(N) ((N/2)-1<<2) + +#define SYS_CLKSRC_ME1 (7<<27) +#define SYS_CLKSRC_DE1 (1<<26) +#define SYS_CLKSRC_CE1 (1<<25) +#define SYS_CLKSRC_ME0 (7<<22) +#define SYS_CLKSRC_DE0 (1<<21) +#define SYS_CLKSRC_CE0 (1<<20) +#define SYS_CLKSRC_MI2 (7<<17) +#define SYS_CLKSRC_DI2 (1<<16) +#define SYS_CLKSRC_CI2 (1<<15) +#define SYS_CLKSRC_MUH (7<<12) +#define SYS_CLKSRC_DUH (1<<11) +#define SYS_CLKSRC_CUH (1<<10) +#define SYS_CLKSRC_MUD (7<<7) +#define SYS_CLKSRC_DUD (1<<6) +#define SYS_CLKSRC_CUD (1<<5) +#define SYS_CLKSRC_MIR (7<<2) +#define SYS_CLKSRC_DIR (1<<1) +#define SYS_CLKSRC_CIR (1<<0) +#define SYS_CLKSRC_ME1_N(N) (N<<27) +#define SYS_CLKSRC_ME0_N(N) (N<<22) +#define SYS_CLKSRC_MI2_N(N) (N<<17) +#define SYS_CLKSRC_MUH_N(N) (N<<12) +#define SYS_CLKSRC_MUD_N(N) (N<<7) +#define SYS_CLKSRC_MIR_N(N) (N<<2) +#define SYS_CLKSRC_MUX_RES (0) +#define SYS_CLKSRC_MUX_AUX (1) +#define SYS_CLKSRC_MUX_FREQ0 (2) +#define SYS_CLKSRC_MUX_FREQ1 (3) +#define SYS_CLKSRC_MUX_FREQ2 (4) +#define SYS_CLKSRC_MUX_FREQ3 (5) +#define SYS_CLKSRC_MUX_FREQ4 (6) +#define SYS_CLKSRC_MUX_FREQ5 (7) +#ifdef AU13XX +#undef SYS_CLKSRC_ME1_N +#undef SYS_CLKSRC_ME0_N +#define SYS_CLKSRC_ME5_N(N) (N<<27) +#define SYS_CLKSRC_MD5_N(N) (N<<25) +#define SYS_CLKSRC_ME4_N(N) (N<<22) +#define SYS_CLKSRC_MD4_N(N) (N<<20) +#define SYS_CLKSRC_ME3_N(N) (N<<17) +#define SYS_CLKSRC_MD3_N(N) (N<<15) +#define SYS_CLKSRC_ME2_N(N) (N<<12) +#define SYS_CLKSRC_MD2_N(N) (N<<10) +#define SYS_CLKSRC_ME1_N(N) (N<<7) +#define SYS_CLKSRC_MD1_N(N) (N<<5) +#define SYS_CLKSRC_ME0_N(N) (N<<2) +#define SYS_CLKSRC_MD0_N(N) (N<<0) +#endif + + +#define SYS_CPUPLL_PLL (63<<0) + +#define SYS_AUXPLL_PLL (63<<0) +#define SYS_AUXPLL2_PLL (63<<0) + +/* TOY & RTC */ +#define SYS_CNTRCTRL_ERS (1<<23) +#define SYS_CNTRCTRL_RTS (1<<20) +#define SYS_CNTRCTRL_RM2 (1<<19) +#define SYS_CNTRCTRL_RM1 (1<<18) +#define SYS_CNTRCTRL_RM0 (1<<17) +#define SYS_CNTRCTRL_RS (1<<16) +#define SYS_CNTRCTRL_BP (1<<14) +#define SYS_CNTRCTRL_REN (1<<13) +#define SYS_CNTRCTRL_BRT (1<<12) +#define SYS_CNTRCTRL_TEN (1<<11) +#define SYS_CNTRCTRL_BTT (1<<10) +#define SYS_CNTRCTRL_EO (1<<8) +#define SYS_CNTRCTRL_ETS (1<<7) +#define SYS_CNTRCTRL_32S (1<<5) +#define SYS_CNTRCTRL_TTS (1<<4) +#define SYS_CNTRCTRL_TM2 (1<<3) +#define SYS_CNTRCTRL_TM1 (1<<2) +#define SYS_CNTRCTRL_TM0 (1<<1) +#define SYS_CNTRCTRL_TS (1<<0) + +#define SYS_CLKCTRL_AT (1<<31) +#define SYS_CLKCTRL_CS (1<<8) +#define SYS_CLKCTRL_AE (1<<7) +#define SYS_CLKCTRL_A2E (1<<6) +#define SYS_CLKCTRL_KT (63<<0) + +/* GPIO */ +#define GPIO_0 (1 << 0) // GPIO 0 +#define GPIO_1 (1 << 1) // GPIO 1 +#define GPIO_2 (1 << 2) // GPIO 2 +#define GPIO_3 (1 << 3) // GPIO 3 +#define GPIO_4 (1 << 4) // GPIO 4 +#define GPIO_5 (1 << 5) // GPIO 5 +#define GPIO_6 (1 << 6) // GPIO 6 +#define GPIO_7 (1 << 7) // GPIO 7 +#define GPIO_8 (1 << 8) // GPIO 8 +#define GPIO_9 (1 << 9) // GPIO 9 +#define GPIO_10 (1 << 10) // GPIO 10 +#define GPIO_11 (1 << 11) // GPIO 11 +#define GPIO_12 (1 << 12) // GPIO 12 +#define GPIO_13 (1 << 13) // GPIO 13 +#define GPIO_14 (1 << 14) // GPIO 14 +#define GPIO_15 (1 << 15) // GPIO 15 +#define GPIO_16 (1 << 16) // GPIO 16 +#define GPIO_17 (1 << 17) // GPIO 17 +#define GPIO_18 (1 << 18) // GPIO 18 +#define GPIO_19 (1 << 19) // GPIO 19 +#define GPIO_20 (1 << 20) // GPIO 20 +#define GPIO_21 (1 << 21) // GPIO 21 +#define GPIO_22 (1 << 22) // GPIO 22 +#define GPIO_23 (1 << 23) // GPIO 23 +#define GPIO_24 (1 << 24) // GPIO 24 +#define GPIO_25 (1 << 25) // GPIO 25 +#define GPIO_26 (1 << 26) // GPIO 26 +#define GPIO_27 (1 << 27) // GPIO 27 +#define GPIO_28 (1 << 28) // GPIO 28 +#define GPIO_29 (1 << 29) // GPIO 29 +#define GPIO_30 (1 << 30) // GPIO 30 +#define GPIO_31 (1 << 31) // GPIO 31 + +/* + * Register content definitions + */ +#if defined( AU1550 ) + +#define SYS_PINFUNC_S0 (1<<0) +#define SYS_PINFUNC_S1 (1<<1) +#define SYS_PINFUNC_MBS1 (1<<2) +#define SYS_PINFUNC_U0 (1<<3) +#define SYS_PINFUNC_NI2 (1<<4) +#define SYS_PINFUNC_MBS2 (1<<5) +#define SYS_PINFUNC_U3 (1<<7) +#define SYS_PINFUNC_EX0 (1<<9) +#define SYS_PINFUNC_EX1 (1<<10) +#define SYS_PINFUNC_U1T (1<<12) /* 0= U1Txdata Drives GPIO[21] */ +#define SYS_PINFUNC_U1R (1<<13) /* 0= U1RTS Drives GPIO[22] */ +#define SYS_PINFUNC_U3T (1<<14) /* 0= U3Txdata Drives GPIO[23] */ +#define SYS_PINFUNC_USB (1<<15) +#define SYS_PINFUNC_CS (1<<16) +#define SYS_PINFUNC_PSC2 (17) + #define SYS_PINFUNC_PSC2_GPIO (0x7<>30)&0x3) +#define LCD_WINCTRL1_PO_00 (0<<22) +#define LCD_WINCTRL1_PO_01 (1<<22) +#define LCD_WINCTRL1_PO_10 (2<<22) +#define LCD_WINCTRL1_PO_11 (3<<22) +#define LCD_WINCTRL1_PO_N(N) (N<<22) + +/* lcd windows control 2 */ +#define LCD_WINCTRL2_CKMODE (3<<24) +#define LCD_WINCTRL2_DBM (1<<23) +#define LCD_WINCTRL2_RAM (3<<21) +#define LCD_WINCTRL2_BX (0x1FFF<<8) +#define LCD_WINCTRL2_SCX (0xF<<4) +#define LCD_WINCTRL2_SCY (0xF<<0) +#define LCD_WINCTRL2_RAM_NONE (0<<21) +#define LCD_WINCTRL2_RAM_PALETTE (1<<21) +#define LCD_WINCTRL2_RAM_GAMMA (2<<21) +#define LCD_WINCTRL2_RAM_BUFFER (3<<21) +#define LCD_WINCTRL2_RAM_N(N) (N<<21) +#define LCD_WINCTRL2_CKMODE_00 (0<<24) +#define LCD_WINCTRL2_CKMODE_01 (1<<24) +#define LCD_WINCTRL2_CKMODE_10 (2<<24) +#define LCD_WINCTRL2_CKMODE_11 (3<<24) +#define LCD_WINCTRL2_CKMODE_N(N) (N<<24) +#define LCD_WINCTRL2_BX_N(N) ((N)<<8) +#define LCD_WINCTRL2_SCX_1 (0<<4) +#define LCD_WINCTRL2_SCX_2 (1<<4) +#define LCD_WINCTRL2_SCX_4 (2<<4) +#define LCD_WINCTRL2_SCX_N(N) (N<<4) +#define LCD_WINCTRL2_SCY_1 (0<<0) +#define LCD_WINCTRL2_SCY_2 (1<<0) +#define LCD_WINCTRL2_SCY_4 (2<<0) +#define LCD_WINCTRL2_SCY_N(N) (N<<0) + +/* lcd windows buffer control */ +#define LCD_WINBUFCTRL_DB (1<<1) +#define LCD_WINBUFCTRL_DBN (1<<0) + +/* lcd_intstatus, lcd_intenable */ +#define LCD_INT_IFO (0xF<<14) +#define LCD_INT_IFU (0xF<<10) +#define LCD_INT_IFU0 (1<<10) +#define LCD_INT_IFU1 (1<<11) +#define LCD_INT_IFU2 (1<<12) +#define LCD_INT_IFU3 (1<<13) +#define LCD_INT_OFO (1<<9) +#define LCD_INT_OFU (1<<8) +#define LCD_INT_WAIT (1<<3) +#define LCD_INT_SD (1<<2) +#define LCD_INT_SA (1<<1) +#define LCD_INT_SS (1<<0) + +/* lcd_horztiming */ +#define LCD_HORZTIMING_HND2 (0x1FF<<18) +#define LCD_HORZTIMING_HND1 (0x1FF<<9) +#define LCD_HORZTIMING_HPW (0x1FF<<0) +#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18) +#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9) +#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0) + +/* lcd_verttiming */ +#define LCD_VERTTIMING_VND2 (0x1FF<<18) +#define LCD_VERTTIMING_VND1 (0x1FF<<9) +#define LCD_VERTTIMING_VPW (0x1FF<<0) +#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18) +#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9) +#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0) + +/* lcd_clkcontrol */ +#define LCD_CLKCONTROL_EXT (1<<22) +#define LCD_CLKCONTROL_DELAY (3<<20) +#define LCD_CLKCONTROL_CDD (1<<19) +#define LCD_CLKCONTROL_IB (1<<18) +#define LCD_CLKCONTROL_IC (1<<17) +#define LCD_CLKCONTROL_IH (1<<16) +#define LCD_CLKCONTROL_IV (1<<15) +#define LCD_CLKCONTROL_BF (0x1F<<10) +#define LCD_CLKCONTROL_PCD (0x3FF<<0) +#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10) +#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0) + +/* lcd_pwmdiv */ +#define LCD_PWMDIV_EN (1<<31) +#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0) +#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0) + +/* lcd_pwmhi */ +#define LCD_PWMHI_PWMHI1 (0xFFFF<<16) +#define LCD_PWMHI_PWMHI0 (0xFFFF<<0) +#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16) +#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0) + +/* lcd_hwccon */ +#define LCD_HWCCON_EN (1<<0) + +/* lcd_cursorpos */ +#define LCD_CURSORPOS_HWCXOFF (0x1F<<27) +#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16) +#define LCD_CURSORPOS_HWCYOFF (0x1F<<11) +#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0) +#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27) +#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16) +#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11) +#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0) + +/* lcd_cursorcolor */ +#define LCD_CURSORCOLOR_HWCA (0xFF<<24) +#define LCD_CURSORCOLOR_HWCR (0xFF<<16) +#define LCD_CURSORCOLOR_HWCG (0xFF<<8) +#define LCD_CURSORCOLOR_HWCB (0xFF<<0) +#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24) +#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16) +#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8) +#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0) + +/* lcd_fifoctrl */ +#define LCD_FIFOCTRL_F3IF (1<<29) +#define LCD_FIFOCTRL_F3REQ (0x1F<<24) +#define LCD_FIFOCTRL_F2IF (1<<29) +#define LCD_FIFOCTRL_F2REQ (0x1F<<16) +#define LCD_FIFOCTRL_F1IF (1<<29) +#define LCD_FIFOCTRL_F1REQ (0x1F<<8) +#define LCD_FIFOCTRL_F0IF (1<<29) +#define LCD_FIFOCTRL_F0REQ (0x1F<<0) +#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24) +#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16) +#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8) +#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0) + +/* lcd_outmask */ +#define LCD_OUTMASK_MASK (0x00FFFFFF) + +#endif /* AU1200 */ + +/*############################################################################################## +##### Au1200 Software Counter Block Register Definitions ##### +##############################################################################################*/ +#define SWCNT_CONTROL 0x0000 +#define SWCNT_COUNT 0x0004 +#define SWCNT_MATCH 0x0008 +#define SWCNT_INTSTAT 0x000C + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 control; //0x10C + uint32 count; //0x110 + uint32 match; //0x114 + uint32 intstat; //0x118 +} AU1200_SWCNT; +#endif + +/* swcnt_control */ +#define SWCNT_CONTROL_EN (1<<0) +#define SWCNT_CONTROL_IE (1<<1) + +/* swcnt_count */ +#define SWCNT_COUNT_COUNT (0x03FFFFFF<<0) +#define SWCNT_COUNT_COUNT_N(n) ((n&0x03FFFFFF)<<0) + +/* swcnt_match */ +#define SWCNT_MATCH_MATCH (0x03FFFFFF<<0) +#define SWCNT_MATCH_MATCH_N(n) ((n&0x03FFFFFF)<<0) + +/* swcnt_intstat */ +#define SWCNT_INTSTAT_INT (1<<0) + +/* +################################################################################################ +##### AES Block Register Definitions ##### +################################################################################################ +*/ +#define AES_STATUS 0x0000 +#define AES_INDATA 0x0004 +#define AES_OUTDATA 0x0008 +#define AES_INTCAUSE 0x000C +#define AES_CONFIG 0x0010 + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 status; /* 0x00 */ + uint32 indata; /* 0x04 */ + uint32 outdata; /* 0x08 */ + uint32 intcause; /* 0x0C */ + uint32 config; /* 0x10 */ +} AU1200_AES; +#endif + + +#define AES_STATUS_PS (1<<0) /* AES Process start/stop */ +#define AES_STATUS_IE (1<<1) /* Interrupt Enable */ +#define AES_STATUS_CR_N(n) ((n&0x03)<<2) /* clock ratio/divider */ +#define AES_STATUS_OUT (1<<4) /* TX FIFO ready (at least 16 bytes) */ +#define AES_STATUS_IN (1<<5) /* RX FIFO ready (at least 16 bytes) */ + +#define AES_INT_RDY (1<<0) /* En/Decryption Completion */ +#define AES_INT_OVR (1<<1) /* Input data FIFO underflow */ +#define AES_INT_UND (1<<2) /* Output data FIFO overflow */ + +#define AES_CONFIG_ED (1<<0) /* En/Decryption Select */ +#define AES_CONFIG_IKG (1<<1) /* Internal Key Generation */ +#define AES_CONFIG_RPK (1<<2) /* Software Replay Key */ +#define AES_CONFIG_RK (1<<3) /* Internal reuse key */ +#define AES_CONFIG_UC (1<<4) /* Undefined block count */ +#define AES_CONFIG_OP_N(n) ((n&0x03)<<5) /* Mode of operation */ + +/* +################################################################################################ +##### AU1200 CIM Block Register Definitions ##### +################################################################################################ +*/ + +#define CIM_ENABLE 0x00000000 +#define CIM_CONFIG 0x00000004 +#define CIM_CAPTURE 0x00000010 +#define CIM_STAT 0x00000014 +#define CIM_INTEN 0x00000018 +#define CIM_INSTAT 0x0000001C +#define CIM_FIFOA 0x00000020 +#define CIM_FIFOB 0x00000040 +#define CIM_FIFOC 0x00000060 + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 enable; /* 00 */ + uint32 config; /* 04 */ + uint32 rsv0[2]; + uint32 capture; /* 10 */ + uint32 stat; /* 14 */ + uint32 inten; /* 18 */ + uint32 instat; /* 1C */ + uint32 fifoa; /* 20 */ + uint32 reserved1[7]; + uint32 fifob; /* 40 */ + uint32 reserved2[7]; + uint32 fifoc; /* 60 */ +} AU1200_CIM; +#endif + +#define CIM_ENABLE_EN (1<<0) /* enable/disable/reset the block*/ + +/* CIM Configuration Register */ + +#define CIM_CONFIG_PM (1<<0) +#define CIM_CONFIG_CLK (1<<1) +#define CIM_CONFIG_LS (1<<2) +#define CIM_CONFIG_FS (1<<3) +#define CIM_CONFIG_DPS (3<<6) +#define CIM_CONFIG_DPS_N(n) ((n&0x03)<<6) +#define CIM_CONFIG_BAY (3<<8) +#define CIM_CONFIG_BAY_N(n) ((n&0x03)<<8) +#define CIM_CONFIG_LEN_N(n) ((n&0x0f)<<10) +#define CIM_CONFIG_BYT (1<<14) +#define CIM_CONFIG_SF (1<<15) +#define CIM_CONFIG_FSEL (3<<16) +#define CIM_CONFIG_FS_N(n) ((n&0x03)<<16) +#define CIM_CONFIG_SI (1<<18) + +/* CIM Capture Control Register */ + +#define CIM_CAPTURE_VCE (1<<0) +#define CIM_CAPTURE_SCE (1<<1) +#define CIM_CAPTURE_CLR (1<<2) + +/* CIM Status Register */ + +#define CIM_STATUS_VC (1<<0) +#define CIM_STATUS_SC (1<<1) +#define CIM_STATUS_AF (1<<2) +#define CIM_STATUS_AE (1<<3) +#define CIM_STATUS_AR (1<<4) +#define CIM_STATUS_BF (1<<5) +#define CIM_STATUS_BE (1<<6) +#define CIM_STATUS_BR (1<<7) +#define CIM_STATUS_CF (1<<8) +#define CIM_STATUS_CE (1<<9) +#define CIM_STATUS_CR (1<<10) + +/* Interrupt Status Rgister */ + +#define CIM_INSTAT_CD (1<<0) +#define CIM_INSTAT_FD (1<<1) +#define CIM_INSTAT_UFA (1<<2) +#define CIM_INSTAT_OFA (1<<3) +#define CIM_INSTAT_UFB (1<<4) +#define CIM_INSTAT_OFB (1<<5) +#define CIM_INSTAT_UFC (1<<6) +#define CIM_INSTAT_OFC (1<<7) +#define CIM_INSTAT_ERR (1<<8) + + +/* +################################################################################################ +##### AU1200 MAE Front End Register Definitions ##### +################################################################################################ +*/ +#define MAEFE_MAX_MACROBLOCKS 1620 /* 720x576 */ +#define MAEFE_MAX_WORDS_PER_MB (4/*hdr*/+10/*mv*/+32/*y0*/+32/*y1*/+32/*y2*/+32/*y3*/+32/*cb*/+32/*cr*/) /* 4:2:0, intentionally exclude weighting matrices */ +#define MAEFE_MAX_WORDS_PER_WM (16) + +#define MAEFE_CONFIG 0x0000 +#define MAEFE_CURY 0x0004 +#define MAEFE_FREFY 0x0008 +#define MAEFE_BREFY 0x000C +#define MAEFE_CURCB 0x0010 +#define MAEFE_FREFCB 0x0014 +#define MAEFE_BREFCB 0x0018 +#define MAEFE_CURCR 0x001C +#define MAEFE_FREFCR 0x0020 +#define MAEFE_BREFCR 0x0024 +#define MAEFE_PICTSIZE 0x0028 +#define MAEFE_INTENSCOMP 0x002C + +#define MAEFE_FREFBOTY 0x0038 +#define MAEFE_FREFBOTCB 0x003C +#define MAEFE_FREFBOTCR 0x0040 +#define MAEFE_BREFBOTY 0x0044 +#define MAEFE_BREFBOTCB 0x0048 +#define MAEFE_BREFBOTCR 0x004C +#define MAEFE_INTSTAT 0x0050 +#define MAEFE_INTENABLE 0x0054 +#define MAEFE_SCRATCHPAD 0x0058 +#define MAEFE_WMV9PQUANT 0x005C + +#define MAEFE_DMADSCR 0x1004 +#define MAEFE_DMADBELL 0x1008 + +#ifndef ASSEMBLER +typedef volatile struct { + uint32 config; + uint32 cury; + uint32 frefy; + uint32 brefy; + uint32 curcb; + uint32 frefcb; + uint32 brefcb; + uint32 curcr; + uint32 frefcr; + uint32 brefcr; + uint32 pictsize; + uint32 intenscomp; + uint32 reserved0[2]; + uint32 frefboty; + uint32 frefbotcb; + uint32 frefbotcr; + uint32 brefboty; + uint32 brefbotcb; + uint32 brefbotcr; + uint32 intstat; + uint32 intenable; + uint32 scratchpad; + uint32 wmv9pquant; + uint32 reserved[0x3e9]; + //uint8 reserved1[(MAEFE_DMADSCR - MAEFE_WMV9PQUANT) - 4]; + uint32 dmadscr; + uint32 dmadbell; +} AU1200_MAEFE; +#endif + +#define MAEFE_CONFIG_BC_BITPOS 26 +#define MAEFE_CONFIG_IQMUL1_BITPOS 24 +#define MAEFE_CONFIG_PLMB_BITPOS 18 +#define MAEFE_CONFIG_COD_BITPOS 17 +#define MAEFE_CONFIG_MIS_BITPOS 16 +#define MAEFE_CONFIG_LOOP_BITPOS 13 +#define MAEFE_CONFIG_SMOO_BITPOS 12 +#define MAEFE_CONFIG_SATIQ_BITPOS 11 +#define MAEFE_CONFIG_PLMB_INTRA 0 +#define MAEFE_CONFIG_PLMB_FORWARD 1 +#define MAEFE_CONFIG_PLMB_BACKWARD 2 +#define MAEFE_CONFIG_PLMB_BIDIRECTIONAL 3 + +#define MAEFE_PICTSIZE_HEIGHT_BITPOS 16 +#define MAEFE_PICTSIZE_LINESZ_BITPOS 0 + +#define MAE_HDR0_BB_BITPOS 31 +#define MAE_HDR0_IQMUL2_BITPOS 22 +#define MAE_HDR0_WTCHGMSK_BITPOS 18 +#define MAE_HDR0_IQADD1_BITPOS 12 +#define MAE_HDR0_DCLUMA_BITPOS 6 +#define MAE_HDR0_DCCHROMA_BITPOS 0 +#define MAE_HDR0_WTCHGMSK_INTERC (1<<21) +#define MAE_HDR0_WTCHGMSK_INTERY (1<<20) +#define MAE_HDR0_WTCHGMSK_INTRAC (1<<19) +#define MAE_HDR0_WTCHGMSK_INTRAY (1<<18) + +#define MAE_HDR1_CBP_BITPOS 12 +#define MAE_HDR1_IQDIV3_BITPOS 9 +#define MAE_HDR1_IQADD2_BITPOS 0 +#define MAE_HDR1_CBP_Y0_BITPOS 19 +#define MAE_HDR1_CBP_Y1_BITPOS 18 +#define MAE_HDR1_CBP_Y2_BITPOS 17 +#define MAE_HDR1_CBP_Y3_BITPOS 16 +#define MAE_HDR1_CBP_CB0_BITPOS 15 +#define MAE_HDR1_CBP_CR0_BITPOS 14 +#define MAE_HDR1_CBP_CB1_BITPOS 13 +#define MAE_HDR1_CBP_CR1_BITPOS 12 +#define MAE_HDR1_CBP_Y0 (1<<19) +#define MAE_HDR1_CBP_Y1 (1<<18) +#define MAE_HDR1_CBP_Y2 (1<<17) +#define MAE_HDR1_CBP_Y3 (1<<16) +#define MAE_HDR1_CBP_CB0 (1<<15) +#define MAE_HDR1_CBP_CR0 (1<<14) +#define MAE_HDR1_CBP_CB1 (1<<13) +#define MAE_HDR1_CBP_CR1 (1<<12) + +#define MAE_HDR2_MBMODE_BITPOS 16 +#define MAE_HDR2_XFORMSIZE_BITPOS 0 +#define MAE_HDR2_MBMODE_INTRA 0 +#define MAE_HDR2_MBMODE_FORWARD 1 +#define MAE_HDR2_MBMODE_BACKWARD 2 +#define MAE_HDR2_MBMODE_BIDIRECTIONAL 3 +#define MAE_HDR2_MBMODE_Y0(MBMODE) (MBMODE<<30) +#define MAE_HDR2_MBMODE_Y1(MBMODE) (MBMODE<<28) +#define MAE_HDR2_MBMODE_Y2(MBMODE) (MBMODE<<26) +#define MAE_HDR2_MBMODE_Y3(MBMODE) (MBMODE<<24) +#define MAE_HDR2_MBMODE_CB0(MBMODE) (MBMODE<<22) +#define MAE_HDR2_MBMODE_CR0(MBMODE) (MBMODE<<20) +#define MAE_HDR2_MBMODE_CB1(MBMODE) (MBMODE<<18) +#define MAE_HDR2_MBMODE_CR1(MBMODE) (MBMODE<<16) +#define MAE_HDR2_XFORMSIZE_8x8 0 +#define MAE_HDR2_XFORMSIZE_8x4 1 +#define MAE_HDR2_XFORMSIZE_4x8 2 +#define MAE_HDR2_XFORMSIZE_4x4 3 +#define MAE_HDR2_XFORMSIZE_Y0(XFORMSIZE) (XFORMSIZE<<14) +#define MAE_HDR2_XFORMSIZE_Y1(XFORMSIZE) (XFORMSIZE<<12) +#define MAE_HDR2_XFORMSIZE_Y2(XFORMSIZE) (XFORMSIZE<<10) +#define MAE_HDR2_XFORMSIZE_Y3(XFORMSIZE) (XFORMSIZE<<8) +#define MAE_HDR2_XFORMSIZE_CB0(XFORMSIZE) (XFORMSIZE<<6) +#define MAE_HDR2_XFORMSIZE_CR0(XFORMSIZE) (XFORMSIZE<<4) +#define MAE_HDR2_XFORMSIZE_CB1(XFORMSIZE) (XFORMSIZE<<2) +#define MAE_HDR2_XFORMSIZE_CR1(XFORMSIZE) (XFORMSIZE<<0) + +#define MAE_HDR3_RND_BITPOS 30 +#define MAE_HDR3_PS_BITPOS 29 +#define MAE_HDR3_DCT_BITPOS 28 +#define MAE_HDR3_FP_BITPOS 27 +#define MAE_HDR3_FT_BITPOS 26 +#define MAE_HDR3_FB_BITPOS 25 +#define MAE_HDR3_BT_BITPOS 24 +#define MAE_HDR3_BB_BITPOS 23 +#define MAE_HDR3_MBTYPE_BITPOS 20 +#define MAE_HDR3_PRECY_BITPOS 18 +#define MAE_HDR3_PRECUV_BITPOS 16 +#define MAE_HDR3_XPOS_BITPOS 8 +#define MAE_HDR3_YPOS_BITPOS 0 +#define MAE_HDR3_MBTYPE_16x16 0 +#define MAE_HDR3_MBTYPE_16x8 2 +#define MAE_HDR3_MBTYPE_8x8 3 +#define MAE_HDR3_PRECY_FULLPEL 0 +#define MAE_HDR3_PRECY_QPEL2 1 +#define MAE_HDR3_PRECY_HPEL 2 +#define MAE_HDR3_PRECY_QPELM 3 +#define MAE_HDR3_PRECUV_FULLPEL 0 +#define MAE_HDR3_PRECUV_HPELM 1 +#define MAE_HDR3_PRECUV_HPELB 2 +#define MAE_HDR3_PRECUV_QPEL 3 + +typedef volatile struct +{ + uint32 dscrword0; + uint32 dscrword1; +} maefe_descriptor; +#define MAEFE_DSCRWORD0_V (1 << 31) + +/* +################################################################################################ +##### AU1200 MAE Back End Register Definitions ##### +################################################################################################ +*/ +/* SCF Registers */ +#define MAEBE_SCFHSR 0x0000 +#define MAEBE_SCFVSR 0x0004 +#define MAEBE_SCFDISABLE 0x0008 +#define MAEBE_SCFHALUT 0x0100 +#define MAEBE_SCFVALUT 0x0180 +#define MAEBE_SCFHBLUT 0x0200 +#define MAEBE_SFCVBLUT 0x0280 +#define MAEBE_SCFHCLUT 0x0300 +#define MAEBE_SCFVCLUT 0x0380 + +/* CSC Registers */ +#define MAEBE_CSCXCFFA 0x0400 +#define MAEBE_CSCXCFFB 0x0404 +#define MAEBE_CSCXCFFC 0x0408 +#define MAEBE_CSCYCFFA 0x040C +#define MAEBE_CSCYCFFB 0x0410 +#define MAEBE_CSCYCFFC 0x0414 +#define MAEBE_CSCZCFFA 0x0418 +#define MAEBE_CSCZCFFB 0x041C +#define MAEBE_CSCZCFFC 0x0420 +#define MAEBE_CSCXOFF 0x0424 +#define MAEBE_CSCYOFF 0x0428 +#define MAEBE_CSCZOFF 0x042C +#define MAEBE_CSCALPHA 0x0430 + +/* SRC Registers */ +#define MAEBE_SRCCFG 0x0500 +#define MAEBE_SRCFHW 0x0504 +#define MAEBE_SRCAADDR 0x0508 +#define MAEBE_SRCASTR 0x050C +#define MAEBE_SRCBADDR 0x0510 +#define MAEBE_SRCBSTR 0x0514 +#define MAEBE_SRCCADDR 0x0518 +#define MAEBE_SRCCSTR 0x051C + +/* DST Registers */ +#define MAEBE_DSTCFG 0x0600 +#define MAEBE_DSTHEIGHT 0x0604 +#define MAEBE_DSTADDR 0x0608 +#define MAEBE_DSTSTR 0x060C + +/* CTL Registers */ +#define MAEBE_CTLENABLE 0x0700 +#define MAEBE_CTLFPC 0x0704 +#define MAEBE_CTLSTAT 0x0708 +#define MAEBE_CTLINTENABLE 0x070C +#define MAEBE_CTLINTSTAT 0x0710 + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 scfhsr; // 0x0000 + uint32 scfvsr; // 0x0004 + uint32 scfdisable; // 0x0008 + uint32 reserved0[((MAEBE_SCFHALUT - MAEBE_SCFDISABLE) - 4)/sizeof(uint32)]; // 0x000C 0xF4 + uint32 scfhalut[32]; // 0x0100 + uint32 scfvalut[32]; // 0x0180 + uint32 scfhblut[32]; // 0x0200 + uint32 scfvblut[32]; // 0x0280 + uint32 scfhclut[32]; // 0x0300 + uint32 scfvclut[32]; // 0x0380 + + uint32 cscxcffa; // 0x0400 + uint32 cscxcffb; // 0x0404 + uint32 cscxcffc; // 0x0408 + uint32 cscycffa; // 0x040C + uint32 cscycffb; // 0x0410 + uint32 cscycffc; // 0x0414 + uint32 csczcffa; // 0x0418 + uint32 csczcffb; // 0x041C + uint32 csczcffc; // 0x0420 + uint32 cscxoff; // 0x0424 + uint32 cscyoff; // 0x0428 + uint32 csczoff; // 0x042C + uint32 cscalpha; // 0x0430 + + uint8 reserved1[(MAEBE_SRCCFG - MAEBE_CSCALPHA) - 4]; // 0x0434 +0xCC + uint32 srccfg; // 0x0500 + uint32 srcfhw; // 0x0504 + uint32 srcaaddr; // 0x0508 + uint32 srcastr; // 0x050C + uint32 srcbaddr; // 0x0510 + uint32 srcbstr; // 0x0514 + uint32 srccaddr; // 0x0518 + uint32 srccstr; // 0x051C + + uint8 reserved2[(MAEBE_DSTCFG - MAEBE_SRCCSTR) - 4]; // 0x0520 +0xE0 + uint32 dstcfg; // 0x0600 + uint32 dstheight; // 0x0604 + uint32 dstaddr; // 0x0608 + uint32 dststr; // 0x060C + + uint8 reserved3[(MAEBE_CTLENABLE - MAEBE_DSTSTR) - 4]; // 0x0610 +0xF0 + uint32 ctlenable; // 0x0700 + uint32 ctlfpc; // 0x0704 + uint32 ctlstat; // 0x0708 + uint32 ctlintenable; // 0x070C + uint32 ctlintstat; // 0x0710 +} AU1200_MAEBE; +#endif + +#define MAEBE_CTLENABLE_EN (1 << 0) + +#define MAEBE_CTLFPC_FRST (1 << 1) +#define MAEBE_CTLFPC_STR (1 << 0) + +#define MAEBE_CTLSTAT_FP (1 << 1) +#define MAEBE_CTLSTAT_FB (1 << 0) + +#define MAEBE_CTLINTSTAT_FC (1 << 0) + +#define MAEBE_SRCCFG_ICM (1 << 0) // Au1300 +#define MAEBE_SRCCFG_ILCE (1 << 1) // Au1300 +#define MAEBE_SRCCFG_IF (3 << 2) +#define MAEBE_SRCCFG_IF_420 (0 << 2) +#define MAEBE_SRCCFG_IF_422 (1 << 2) +#define MAEBE_SRCCFG_IF_411 (2 << 2) +#define MAEBE_SRCCFG_IF_444 (3 << 2) +#define MAEBE_SRCCFG_ILM (3 << 4) +#define MAEBE_SRCCFG_ILM_UYVY (0 << 4) +#define MAEBE_SRCCFG_ILM_VYUY (1 << 4) +#define MAEBE_SRCCFG_ILM_YUYV (2 << 4) +#define MAEBE_SRCCFG_ILM_YVYU (3 << 4) +#define MAEBE_SRCCFG_ILE (1 << 6) +#define MAEBE_SRCCFG_BM (3 << 7) +#define MAEBE_SRCCFG_BM_RG_GB (0 << 7) +#define MAEBE_SRCCFG_BM_GR_BG (1 << 7) +#define MAEBE_SRCCFG_BM_BG_GR (2 << 7) +#define MAEBE_SRCCFG_BM_GB_RG (3 << 7) +#define MAEBE_SRCCFG_BYE (1 << 9) +#define MAEBE_SRCCFG_EF (1 << 10) + +#define MAEBE_DSTCFG_EF_SHIFT (1) +#define MAEBE_DSTCFG_OF_SHIFT (2) +#define MAEBE_DSTCFG_BGR_SHIFT (4) +#define MAEBE_DSTCFG_ROT_SHIFT (5) +#define MAEBE_DSTCFG_R_SHIFT (7) +#define MAEBE_DSTCFG_EF (1 << MAEBE_DSTCFG_EF_SHIFT) +#define MAEBE_DSTCFG_OF (3 << MAEBE_DSTCFG_OF_SHIFT) +#define MAEBE_DSTCFG_BGR (1 << MAEBE_DSTCFG_BGR_SHIFT) +#define MAEBE_DSTCFG_ROT (3 << MAEBE_DSTCFG_ROT_SHIFT) +#define MAEBE_DSTCFG_R (1 << MAEBE_DSTCFG_R_SHIFT) + +#define MAEBE_SCFHSR_SRI_N(N) (N<<16) +#define MAEBE_SCFVSR_SRI_N(N) (N<<16) + +/***********************************************************************/ +/***********************************************************************/ +/***********************************************************************/ +/***********************************************************************/ + +/* + * Physical base addresses for integrated peripherals + */ + +#ifdef AU1000 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define IRDA_PHYS_ADDR 0x10300000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MAC1_PHYS_ADDR 0x10510000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART2_PHYS_ADDR 0x11300000 +#define UART3_PHYS_ADDR 0x11400000 +#define SSI0_PHYS_ADDR 0x11600000 +#define SSI1_PHYS_ADDR 0x11680000 +#define SYS_PHYS_ADDR 0x11900000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#endif + +/********************************************************************/ + +#ifdef AU1500 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define PCI_PHYS_ADDR 0x14005000 +#define MAC0_PHYS_ADDR 0x11500000 +#define MAC1_PHYS_ADDR 0x11510000 +#define MACEN_PHYS_ADDR 0x11520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART3_PHYS_ADDR 0x11400000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define PCI_MEM_PHYS_ADDR 0x400000000 +#define PCI_IO_PHYS_ADDR 0x500000000 +#define PCI_CONFIG0_PHYS_ADDR 0x600000000 +#define PCI_CONFIG1_PHYS_ADDR 0x680000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#endif + +/********************************************************************/ + +#ifdef AU1100 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10680000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define IRDA_PHYS_ADDR 0x10300000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART3_PHYS_ADDR 0x11400000 +#define SSI0_PHYS_ADDR 0x11600000 +#define SSI1_PHYS_ADDR 0x11680000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define LCD_PHYS_ADDR 0x15000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#endif + +/***********************************************************************/ + +#ifdef AU1550 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define USBH_PHYS_ADDR 0x14020000 +#define USBD_PHYS_ADDR 0x10200000 +#define PCI_PHYS_ADDR 0x14005000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MAC1_PHYS_ADDR 0x10510000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART3_PHYS_ADDR 0x11400000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define DDMA_PHYS_ADDR 0x14002000 +#define PE_PHYS_ADDR 0x14008000 +#define PSC0_PHYS_ADDR 0x11A00000 +#define PSC1_PHYS_ADDR 0x11B00000 +#define PSC2_PHYS_ADDR 0x10A00000 +#define PSC3_PHYS_ADDR 0x10B00000 +#define PCI_MEM_PHYS_ADDR 0x400000000 +#define PCI_IO_PHYS_ADDR 0x500000000 +#define PCI_CONFIG0_PHYS_ADDR 0x600000000 +#define PCI_CONFIG1_PHYS_ADDR 0x680000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#endif + +/***********************************************************************/ + +#ifdef AU1200 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define AES_PHYS_ADDR 0x10300000 +#define CIM_PHYS_ADDR 0x14004000 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define USBM_PHYS_ADDR 0x14020000 +#define USBH_PHYS_ADDR 0x14020100 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define DDMA_PHYS_ADDR 0x14002000 +#define PSC0_PHYS_ADDR 0x11A00000 +#define PSC1_PHYS_ADDR 0x11B00000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10680000 +#define LCD_PHYS_ADDR 0x15000000 +#define SWCNT_PHYS_ADDR 0x1110010C +#define MAEFE_PHYS_ADDR 0x14012000 +#define MAEBE_PHYS_ADDR 0x14010000 +#endif + +/***********************************************************************/ + +#ifdef AU13XX +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define AES_PHYS_ADDR 0x10300000 +#define CIM_PHYS_ADDR 0x14004000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART2_PHYS_ADDR 0x11300000 +#define SYS_PHYS_ADDR 0x11900000 +#define VSS_PHYS_ADDR 0x11003000 +#define DDMA_PHYS_ADDR 0x14002000 +#define PSC0_PHYS_ADDR 0x11A00000 +#define PSC1_PHYS_ADDR 0x11B00000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10680000 +#define LCD_PHYS_ADDR 0x15000000 +#define MAEBE_PHYS_ADDR 0x14010000 +#endif + +#endif /* _AU1X00_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/bsa.h linux-2.6.29/drivers/media/alchemy/bsa.h --- linux-2.6.29/drivers/media/alchemy/bsa.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/bsa.h 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,847 @@ +/********************************************************************** +* Copyright 2008 RMI Corp. All Rights Reserved. +* +* Unless otherwise designated in writing, this software and any related +* documentation are the confidential proprietary information of RMI +* Corp. +* +* THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +* UNLESS OTHERWISE NOTED IN WRITING, EXPRESS OR IMPLIED WARRANTY OF ANY +* KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE AND IN NO +* EVENT SHALL RMI COPR. OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES +* WHATSOEVER. +* +* RMI Corp. does not assume any responsibility for any errors which may +* appear in the Materials nor any responsibility to support or update +* the Materials. RMI Corp. retains the right to modify the Materials +* at any time, without notice, and is not obligated to provide such +* modified Materials to you. RMI Corp. is not obligated to furnish, +* support, or make any further information available to you. +***********************************************************************/ + +/* Generated: monet 13192, Tue Aug 18 16:03:36 CDT 2009 */ + +#ifndef __bsa_h__ +#define __bsa_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +////////////////////////////////////////////////////////////////////// + +// Absolute maximum number of macroblocks per picture the BSA can handle +#define MAX_PICWIDTHINMBS (1280/16) +#define MAX_PICHEIGHTINMBS (720/16) +#define MAX_PICSIZEINMBS (MAX_PICWIDTHINMBS*MAX_PICHEIGHTINMBS) + +// Absolute maximum values per macroblock +#define PMM_BYTES_PER_MB (16) +#define COEFF_BYTES_PER_MB ((13589/*bits*/+7)/8) +#define MV_BYTES_PER_MB ((8827/*bits*/+7)/8) +#define NEIGH_BYTES_PER_MB ((76/*dwords*/*8)) + +#define IRAM_SIZE 12800 // 12.5KB +#define DRAM_SIZE 12288 // 12.0KB + +////////////////////////////////////////////////////////////////////// + +#ifndef ASSEMBLER +typedef volatile union +{ + unsigned int _word; // 32-bit Au1 accesses + unsigned short _hword[2]; // 16-bit SCB accesses + unsigned char _byte[4]; + +#define WD32 _word +#define LO16 _hword[0] // SCB is EL +#define HI16 _hword[1] + +} bsaReg; +#endif + +#define HI16_MASK(X) (((X)>>16)&0x0000FFFF) +#define LO16_MASK(X) (((X)>> 0)&0x0000FFFF) + +////////////////////////////////////////////////////////////////////// + +#define CABAC_RESET 0 // 0x0000 +#define CABAC_INIT 4 // 0x0004 +#define CABAC_CODIRANGE 8 // 0x0008 +#define CABAC_CODIOFFSET 12 // 0x000C +#define CABAC_SLICEINFO 16 // 0x0010 +#define CABAC_MBINFO 20 // 0x0014 +#define CABAC_CBP 24 // 0x0018 +#define CABAC_SUBMBINFO 28 // 0x001C +#define CABAC_MFDF 32 // 0x0020 + +#ifndef ASSEMBLER +typedef volatile struct +{ + bsaReg reset; + bsaReg init; + bsaReg codIRange; + bsaReg codIOffset; + bsaReg sliceinfo; + bsaReg mbinfo; + bsaReg cbp; + bsaReg submbinfo; + bsaReg mfdf; + bsaReg _pad[16-9]; + +} bsa_cabac_t; +#endif + +#define CABAC_SLICEINFO_CIPF_BITPOS 0 +#define CABAC_SLICEINFO_SDP_BITPOS 1 +#define CABAC_SLICEINFO_ST_BITPOS 2 +#define CABAC_SLICEINFO_MFF_BITPOS 5 +#define CABAC_SLICEINFO_FPF_BITPOS 6 +#define CABAC_SLICEINFO_CIPF (1< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#include +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int + +#define AU13XX +#include "au1x00.h" +#include "maeioctl.h" +#include "bsa.h" + +#define AU1300_MAE_BSA_INT 94 + +#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg) + +#define MAEBSA_NAME "au13xx_maebsa" +#define MAEBSA_MAJOR 241 +#define VERSION "1.0" +// mknod /dev/maebsa c 241 0 + +static struct maebsa_state { + volatile int irq; + volatile uint32 endOfifo0PhysAddr; + volatile uint32 endOfifo1PhysAddr; + volatile uint32 endMailbox0; + volatile uint32 endMailbox1; + volatile uint32 endMailbox2; + volatile uint32 endMailbox3; + volatile uint32 endBitcounter; + volatile uint32 endMipsCounter; + wait_queue_head_t wait; + volatile int status; + +} maebsa_state; + +////////////////////////////////////////////////////////////////////// +static void +maebsa_reset (int reset) +{ + AU13XX_VSSCTRL *vss = (AU13XX_VSSCTRL *)(0xA0000000|VSS_PHYS_ADDR); + volatile uint32 junk; + + if (reset) + { + vss->bsa.clkrst = 3; + } + else + { + vss->bsa.clkrst = 2; + } + + // Read-back to force write to go out, provides more time when cycling reset + junk = vss->bsa.clkrst; +} + +////////////////////////////////////////////////////////////////////// +static void +maebsa_power (int up) +{ + AU13XX_VSSCTRL *vss = (AU13XX_VSSCTRL *)(0xA0000000|VSS_PHYS_ADDR); + + if (up) + { + maebsa_reset(1); + + vss->bsa.gate = 0x01fffffe; + vss->bsa.ftr = 1; + vss->bsa.ftr = 3; + vss->bsa.ftr = 7; + vss->bsa.ftr = 0xf; + + vss->bsa.gate = 0x01fffffF; + + maebsa_reset(0); + + vss->bsa.ftr = 0x1f; + } + else + { + vss->bsa.ftr = 0xF; + vss->bsa.gate = 0; + vss->bsa.clkrst = 2; + vss->bsa.clkrst = 1; + vss->bsa.ftr = 0; + } +} + +////////////////////////////////////////////////////////////////////// +static void +maebsa_transaction (mae_bsa_request_t *tr) +{ + bsa_t *bsa = (bsa_t *)(0xA0000000|BSA_PHYS_ADDR); + int timeout, OK = 1; + + maebsa_reset(0); + + tr->bsaStatus = 0; // Initialize to error status + tr->begMipsCounter = read_c0_count(); + + //if (tr->flags & MAEBSA_FLAGS_DCWB) dma_cache_wback((unsigned long)tr, 16*1024); // writeback ENTIRE dcache + + // Sanity checks + if (tr->iramPhysAddr == 0x00000000) OK = 0; + if (tr->dramPhysAddr == 0x00000000) OK = 0; + if (tr->pmmPhysAddr == 0x00000000) OK = 0; + if (tr->ofifo0StartPhysAddr == 0x00000000) OK = 0; + if (tr->ofifo1StartPhysAddr == 0x00000000) OK = 0; + if (tr->ofifo0EndPhysAddr == 0x00000000) OK = 0; + if (tr->ofifo1EndPhysAddr == 0x00000000) OK = 0; + if (tr->neighPhysAddr == 0x00000000) OK = 0; + if (tr->descPhysAddr == 0x00000000) OK = 0; + if (tr->numEntries == 0) OK = 0; + if (!OK) + { + printk("Problem with BSA request\n"); + return; + } + + // Configure OFIFOs + bsa->regs.ofifo0.addr.WD32 = tr->ofifo0StartPhysAddr; + bsa->regs.ofifo0.endaddr.WD32 = tr->ofifo0EndPhysAddr; + bsa->regs.ofifo1.addr.WD32 = tr->ofifo1StartPhysAddr; + bsa->regs.ofifo1.endaddr.WD32 = tr->ofifo1EndPhysAddr; + bsa->regs.ofifo0.control.WD32 = OFIFO_CONTROL_S | tr->ofifo0Control; + bsa->regs.ofifo1.control.WD32 = OFIFO_CONTROL_S | tr->ofifo1Control; + + // Configure Parsed Macroblock Map + bsa->regs.scb.mailbox0.WD32 = tr->pmmPhysAddr; + + // Load IRAM (using GPDMA) + bsa->regs.gpdma.ramaddr.WD32 = 0x00008000; + bsa->regs.gpdma.memaddr.WD32 = tr->iramPhysAddr; + bsa->regs.gpdma.numwords.WD32 = tr->iramSize; + bsa->regs.gpdma.control.WD32 = GPDMA_CONTROL_DIRECTION_M2R|GPDMA_CONTROL_START|tr->gpdmaControl; + // Wait for it to finish + timeout = 0x00100000; + do + { + if (bsa->regs.gpdma.status.WD32 & GPDMA_STATUS_TC) + break; + } while (--timeout > 0); + if (timeout == 0) { OK = 0; printk("error: IRAM load failed\n"); } + + // Load DRAM (using GPDMA) + bsa->regs.gpdma.ramaddr.WD32 = 0x00000000; + bsa->regs.gpdma.memaddr.WD32 = tr->dramPhysAddr; + bsa->regs.gpdma.numwords.WD32 = tr->dramSize; + bsa->regs.gpdma.control.WD32 = GPDMA_CONTROL_DIRECTION_M2R|GPDMA_CONTROL_START|tr->gpdmaControl; + // Wait for it to finish + timeout = 0x00100000; + do + { + if (bsa->regs.gpdma.status.WD32 & GPDMA_STATUS_TC) + break; + } while (--timeout > 0); + if (timeout == 0) { OK = 0; printk("error: DRAM load failed\n"); } + + // Configure IFIFO + bsa->regs.ififo.control.WD32 = tr->ififoControl; + bsa->regs.ififo.pattern.WD32 = tr->ififoPattern; + bsa->regs.ififo.numentries.WD32 = 0; + bsa->regs.ififo.listaddr.WD32 = tr->descPhysAddr; + bsa->regs.ififo.numentries.WD32 = tr->numEntries; + + // Configure Neighbor + bsa->regs.neigh.spaddr.WD32 = tr->neighPhysAddr; + + // Configure SCB + bsa->regs.scb.status.WD32 = 0; + bsa->regs.scb.mailbox1.WD32 = tr->mailbox1; + bsa->regs.scb.mailbox2.WD32 = tr->mailbox2; + bsa->regs.scb.mailbox3.WD32 = tr->mailbox3; + bsa->regs.scb.watchdog.WD32 = tr->watchdog; + bsa->regs.scb.status.WD32 = 0; + bsa->regs.scb.mask.WD32 = tr->irqMask; + bsa->regs.scb.addr.WD32 = tr->initPC; + + if (OK) + { +#if 1 + bsa->regs.scb.go.WD32 = SCB_GO_GO; + + // Now block waiting for BSA to finish + interruptible_sleep_on(&maebsa_state.wait); +#else + // Now block waiting for BSA to finish - solves race of BSA IRQ occuring before + // kernel has a chance to put process to sleep (think a few byte slice finishing really fast) + wait_event_interruptible(maebsa_state.wait, (!(bsa->regs.scb.go.WD32 = SCB_GO_GO)) ); +#endif + } + + // Provide feedback from BSA run + tr->bsaStatus = maebsa_state.status; + tr->endOfifo0PhysAddr = maebsa_state.endOfifo0PhysAddr; + tr->endOfifo1PhysAddr = maebsa_state.endOfifo1PhysAddr; + tr->endMailbox0 = maebsa_state.endMailbox0; + tr->endMailbox1 = maebsa_state.endMailbox1; + tr->endMailbox2 = maebsa_state.endMailbox2; + tr->endMailbox3 = maebsa_state.endMailbox3; + tr->endBitcounter = maebsa_state.endBitcounter; + + tr->endMipsCounter = maebsa_state.endMipsCounter; +} + +////////////////////////////////////////////////////////////////////// +irqreturn_t maebsa_handler(int irq, void *dev_id) +{ + bsa_t *bsa = (bsa_t *)(0xA0000000|BSA_PHYS_ADDR); + + //disable_irq(maebsa_state.irq); + + maebsa_state.status = bsa->regs.scb.status.WD32; + maebsa_state.endOfifo0PhysAddr = bsa->regs.ofifo0.addr.WD32; + maebsa_state.endOfifo1PhysAddr = bsa->regs.ofifo1.addr.WD32; + maebsa_state.endMailbox0 = bsa->regs.scb.mailbox0.WD32; + maebsa_state.endMailbox1 = bsa->regs.scb.mailbox1.WD32; + maebsa_state.endMailbox2 = bsa->regs.scb.mailbox2.WD32; + maebsa_state.endMailbox3 = bsa->regs.scb.mailbox3.WD32; + maebsa_state.endBitcounter = bsa->regs.ififo.bitcounter.WD32; + maebsa_state.endMipsCounter = read_c0_count(); + bsa->regs.scb.status.WD32 = 0; // ack interrupts + + //maebsa_reset(1); // especially if error + + wake_up_interruptible(&maebsa_state.wait); + + //enable_irq(maebsa_state.irq); + + if (maebsa_state.status != SCB_STATUS_DONE) + { + // Cycle reset, just in case... + maebsa_reset(1); + maebsa_reset(0); + } + + return IRQ_HANDLED; +} + +////////////////////////////////////////////////////////////////////// +static int +maebsa_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + mae_bsa_request_t *usr = (mae_bsa_request_t *)arg; + + switch (cmd) + { + case MAEBSA_IOCTL_SUBMIT_BUFFER: + maebsa_transaction(usr); + break; + default: + printk("error with maebsa request %d\n", cmd); + break; + } + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maebsa_open(struct inode *inode, struct file *file) +{ + // FIX!!! only allow a single open!!!! + + // cycle reset + maebsa_reset(1); + maebsa_reset(0); + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maebsa_release(struct inode *inode, struct file *file) +{ + maebsa_reset(1); + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static struct file_operations maebsa_fops = +{ + owner: THIS_MODULE, + open: maebsa_open, + ioctl: maebsa_ioctl, + release: maebsa_release, +}; + +////////////////////////////////////////////////////////////////////// +static int __init +maebsa_init(void) +{ + int rcode = 0; + maebsa_state.irq = AU1300_MAE_BSA_INT; + if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)) + maebsa_state.irq += 8; + + init_waitqueue_head(&maebsa_state.wait); + + // POWER CLOCKS RESET + maebsa_power(1); + + /* Register Device*/ + rcode = register_chrdev(MAEBSA_MAJOR, MAEBSA_NAME, &maebsa_fops); + if ( rcode < 0 ) + printk("\n Could not register MAE BSA device\n"); + else + { + printk("Au13XX MAEBSA driver registered Sucessfully v%s\n", VERSION); + + if ( (rcode=request_irq(maebsa_state.irq, maebsa_handler, + IRQF_SHARED, MAEBSA_NAME, (void *)&maebsa_state )) ) + { + printk("MAEBSA: Could not get IRQ %d", maebsa_state.irq); + } + } + + return rcode; +} + +////////////////////////////////////////////////////////////////////// +static void __exit +maebsa_exit(void) +{ + /*Unregister Device*/ + unregister_chrdev(MAEBSA_MAJOR, MAEBSA_NAME); + free_irq(maebsa_state.irq, (void *)&maebsa_state); + + maebsa_power(0); +} + +////////////////////////////////////////////////////////////////////// + +MODULE_AUTHOR("Eric DeVolder"); +MODULE_DESCRIPTION("Au13XX MAE BSA Driver"); +MODULE_LICENSE("GPL"); +module_init(maebsa_init); +module_exit(maebsa_exit); + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/maeioctl.h linux-2.6.29/drivers/media/alchemy/maeioctl.h --- linux-2.6.29/drivers/media/alchemy/maeioctl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/maeioctl.h 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,299 @@ + +/* + * Common header file for MAE + */ + +#ifndef _MAEIOCTL_H +#define _MAEIOCTL_H + +// Interface for talking to Linux drivers +// NOTE: Linux drivers directly include this file... + +////////////////////////////////////////////////////////////////////// +typedef struct +{ + uint32 physAddr; + uint32 physSize; + uint32 flags; +#define MAEMEM_FLAGS_CACHEABLE 0x1 + uint32 lcdwin0phys; + uint32 lcdwin1phys; + uint32 lcdwin2phys; + uint32 lcdwin3phys; + uint32 counterFreq; +} mae_mem_request_t; + +////////////////////////////////////////////////////////////////////// + +// lifted from drivers/video/au1200fb.c +#define AU1200_LCD_FB_IOCTL 0x46FF + +#define AU1200_LCD_SET_SCREEN 1 +#define AU1200_LCD_GET_SCREEN 2 +#define AU1200_LCD_SET_WINDOW 3 +#define AU1200_LCD_GET_WINDOW 4 +#define AU1200_LCD_SET_PANEL 5 +#define AU1200_LCD_GET_PANEL 6 + +#define SCREEN_SIZE (1<< 1) +#define SCREEN_BACKCOLOR (1<< 2) +#define SCREEN_BRIGHTNESS (1<< 3) +#define SCREEN_COLORKEY (1<< 4) +#define SCREEN_MASK (1<< 5) +typedef struct au1200_lcd_global_regs_t +{ + unsigned int flags; + unsigned int xsize; + unsigned int ysize; + unsigned int backcolor; + unsigned int brightness; + unsigned int colorkey; + unsigned int mask; + unsigned int panel_choice; + char panel_desc[80]; + +} au1200_lcd_global_regs_t; + +#define WIN_POSITION (1<< 0) +#define WIN_ALPHA_COLOR (1<< 1) +#define WIN_ALPHA_MODE (1<< 2) +#define WIN_PRIORITY (1<< 3) +#define WIN_CHANNEL (1<< 4) +#define WIN_BUFFER_FORMAT (1<< 5) +#define WIN_COLOR_ORDER (1<< 6) +#define WIN_PIXEL_ORDER (1<< 7) +#define WIN_SIZE (1<< 8) +#define WIN_COLORKEY_MODE (1<< 9) +#define WIN_DOUBLE_BUFFER_MODE (1<< 10) +#define WIN_RAM_ARRAY_MODE (1<< 11) +#define WIN_BUFFER_SCALE (1<< 12) +#define WIN_ENABLE (1<< 13) + +typedef struct au1200_lcd_window_regs_t +{ + unsigned int flags; + unsigned int xpos; + unsigned int ypos; + unsigned int alpha_color; + unsigned int alpha_mode; + unsigned int priority; + unsigned int channel; + unsigned int buffer_format; + unsigned int color_order; + unsigned int pixel_order; + unsigned int xsize; + unsigned int ysize; + unsigned int colorkey_mode; + unsigned int double_buffer_mode; + unsigned int ram_array_mode; + unsigned int xscale; + unsigned int yscale; + unsigned int enable; +} au1200_lcd_window_regs_t; + +typedef struct au1200_lcd_iodata_t +{ + + unsigned int subcmd; + au1200_lcd_global_regs_t global; + au1200_lcd_window_regs_t window; + +} au1200_lcd_iodata_t; + +typedef struct +{ + int window; + int buffer; + uint32 physAddr; +} mae_lcd_request_t; + +////////////////////////////////////////////////////////////////////// + +typedef volatile struct +{ + uint32 flags; +#define MAEFE_FLAGS_DCWB 0x1 +#define MAEFE_FLAGS_DCWBINV 0x2 + + uint32 config; + uint32 cury; + uint32 frefy; + uint32 brefy; + uint32 curcb; + uint32 frefcb; + uint32 brefcb; + uint32 curcr; + uint32 frefcr; + uint32 brefcr; + uint32 pictsize; + uint32 intenscomp; + uint32 frefboty; + uint32 frefbotcb; + uint32 frefbotcr; + uint32 brefboty; + uint32 brefbotcb; + uint32 brefbotcr; + uint32 intstat; + uint32 intenable; + uint32 scratchpad; + uint32 wmv9pquant; + uint32 dmadscr; + uint32 dmadbell; + + // returned by driver + uint32 begMipsCounter; + uint32 endMipsCounter; + +} mae_fe_request_t; + +#define MAEFE_IOCTL_SET_CONFIG 1 +#define MAEFE_IOCTL_SUBMIT_MBDATA 2 +#define MAEFE_IOCTL_SUBMIT_MBDATA_WITH_WAIT 3 + +////////////////////////////////////////////////////////////////////// +typedef struct +{ + uint32 flags; +#define MAEBSA_FLAGS_DCWB 0x1 +#define MAEBSA_FLAGS_DCWBINV 0x2 + + uint32 watchdog; + uint32 initPC; + uint32 irqMask; + uint32 mailbox1; + uint32 mailbox2; + uint32 mailbox3; + uint32 gpdmaControl; + uint32 iramPhysAddr; + uint32 iramSize; + uint32 dramPhysAddr; + uint32 dramSize; + uint32 neighPhysAddr; + uint32 neighSize; + uint32 ofifo0StartPhysAddr; + uint32 ofifo0EndPhysAddr; + uint32 ofifo0Control; + uint32 ofifo1StartPhysAddr; + uint32 ofifo1EndPhysAddr; + uint32 ofifo1Control; + uint32 pmmPhysAddr; + uint32 descPhysAddr; + uint32 numEntries; + uint32 ififoControl; + uint32 ififoPattern; + + // returned by driver + uint32 bsaStatus; + uint32 endOfifo0PhysAddr; + uint32 endOfifo1PhysAddr; + uint32 endMailbox0; + uint32 endMailbox1; + uint32 endMailbox2; + uint32 endMailbox3; + uint32 endBitcounter; + uint32 begMipsCounter; + uint32 endMipsCounter; + +} mae_bsa_request_t; +#define MAEBSA_IOCTL_SUBMIT_BUFFER 1 + +////////////////////////////////////////////////////////////////////// +typedef struct +{ + uint32 flags; +#define MAEMPE_FLAGS_DCWB 0x01 +#define MAEMPE_FLAGS_DCWBINV 0x02 + + uint32 cfg1; + uint32 cfg2; + uint32 cfg3; + uint32 cfg4; + uint32 cfg5; + uint32 cfg6; + uint32 cfg7; + uint32 cfg8; + uint32 cfg9; + uint32 cfg10; + uint32 cfg11; + uint32 cfg12; + uint32 cfg13; + uint32 cfg14; + uint32 cfg15; + uint32 cfg18; + + // returned by driver + uint32 begMipsCounter; + uint32 endMipsCounter; + +} mae_mpe_request_t; +#define MAEMPE_IOCTL_SUBMIT_BUFFER 2 + +////////////////////////////////////////////////////////////////////// +typedef struct +{ + uint32 flags; +#define MAEBE_FLAGS_DCWB 0x01 +#define MAEBE_FLAGS_DCWBINV 0x02 +#define MAEBE_FLAGS_CACHEABLE 0x04 + + uint32 scfhsr; + uint32 scfvsr; + uint32 scfdisable; + uint32 scfhalut[32]; + uint32 scfvalut[32]; + uint32 scfhblut[32]; + uint32 scfvblut[32]; + uint32 scfhclut[32]; + uint32 scfvclut[32]; + + uint32 cscxcffa; + uint32 cscxcffb; + uint32 cscxcffc; + uint32 cscycffa; + uint32 cscycffb; + uint32 cscycffc; + uint32 csczcffa; + uint32 csczcffb; + uint32 csczcffc; + uint32 cscxoff; + uint32 cscyoff; + uint32 csczoff; + uint32 cscalpha; + + uint32 srccfg; + uint32 srcfhw; + uint32 srcaaddr; + uint32 srcastr; + uint32 srcbaddr; + uint32 srcbstr; + uint32 srccaddr; + uint32 srccstr; + + uint32 dstcfg; + uint32 dstheight; + uint32 dstaddr; + uint32 dststr; + + uint32 ctlenable; + uint32 ctlfpc; + uint32 ctlstat; + uint32 ctlintenable; + uint32 ctlintstat; + + // returned by driver + uint32 memPhysAddr; + uint32 memPhysSize; + uint32 counterFreq; + uint32 begMipsCounter; + uint32 endMipsCounter; + +} mae_be_request_t; + +#define MAEBE_IOCTL_INITIALIZE 1 +#define MAEBE_IOCTL_SUBMIT_PICTURE 2 +#define MAEBE_IOCTL_SUBMIT_PICTURE_WITH_WAIT 3 + +////////////////////////////////////////////////////////////////////// + +#endif // _MAEIOCTL_H + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/maeite.c linux-2.6.29/drivers/media/alchemy/maeite.c --- linux-2.6.29/drivers/media/alchemy/maeite.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/maeite.c 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,396 @@ +/* + * maeite.c + * + * Copyright 2007 Eric DeVolder + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#include +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int + +#if defined(CONFIG_AU12XX_MAE) || defined(CONFIG_AU12XX_MAE_MODULE) +#define AU1200 +#define AU1200_MAE_BE_INT 4 // FIX!!! from asm/mach-au1x00/au1000.h +#define MAEBE_NAME "au12xx_maebe" +#define MAEBE_MAJOR 240 +// mknod /dev/maebe c 240 0 +#endif + +#if defined(CONFIG_AU13XX_MAE2) || defined(CONFIG_AU13XX_MAE2_MODULE) +#define AU13XX +#define AU1200_MAE_BE_INT 92 +#define MAEBE_NAME "au13xx_maeite" +#define MAEBE_MAJOR 243 +// mknod /dev/maeite c 243 0 +#endif + +#include "au1x00.h" +#include "maeioctl.h" + +#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg) + +#define VERSION "1.0" + +#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) + +#if defined(CONFIG_AU12XX_MAE) || defined(CONFIG_AU12XX_MAE_MODULE) +INT_MODULE_PARM(base, 80); +INT_MODULE_PARM(size, 16); +#endif + +#if defined(CONFIG_AU13XX_MAE2) || defined(CONFIG_AU13XX_MAE2_MODULE) +INT_MODULE_PARM(base, 128); +INT_MODULE_PARM(size, 32); +#endif + +////////////////////////////////////////////////////////////////////// +static struct maebe_state { + int mmapped; + int irq; + int cached; + uint32 endMipsCounter; + dma_addr_t physAddr; + unsigned int physSize; + wait_queue_head_t wait; + +} maebe_state; + +////////////////////////////////////////////////////////////////////// +static void +be_init (void) +{ + // Initialize MAEBE + AU1200_MAEBE * const be = (AU1200_MAEBE *)(0xA0000000|MAEBE_PHYS_ADDR); + + be->ctlenable = MAEBE_CTLENABLE_EN; // enable clocks to BE + be->ctlfpc = MAEBE_CTLFPC_FRST; // reset the BE +} + +////////////////////////////////////////////////////////////////////// +static void +be_deinit (void) +{ + AU1200_MAEBE * const be = (AU1200_MAEBE *)(0xA0000000|MAEBE_PHYS_ADDR); + + be->ctlenable = 0; // disable clocks +} + +////////////////////////////////////////////////////////////////////// +static void +be_submit (mae_be_request_t *tr, int wait) +{ + AU1200_MAEBE * const be = (AU1200_MAEBE *)(0xA0000000|MAEBE_PHYS_ADDR); + int i; + + tr->begMipsCounter = read_c0_count(); + + if (tr->flags & MAEBE_FLAGS_DCWB) dma_cache_wback((unsigned long)tr, 16*1024); // writeback ENTIRE dcache + + be->ctlfpc = MAEBE_CTLFPC_FRST; // reset for next transaction + + for (i = 0; i < 32; ++i) + { + be->scfhalut[i] = tr->scfhalut[i]; + be->scfvalut[i] = tr->scfvalut[i]; + be->scfhblut[i] = tr->scfhblut[i]; + be->scfvblut[i] = tr->scfvblut[i]; + be->scfhclut[i] = tr->scfhclut[i]; + be->scfvclut[i] = tr->scfvclut[i]; + } + + be->cscxcffa = tr->cscxcffa; + be->cscxcffb = tr->cscxcffb; + be->cscxcffc = tr->cscxcffc; + be->cscycffa = tr->cscycffa; + be->cscycffb = tr->cscycffb; + be->cscycffc = tr->cscycffc; + be->csczcffa = tr->csczcffa; + be->csczcffb = tr->csczcffb; + be->csczcffc = tr->csczcffc; + be->cscxoff = tr->cscxoff; + be->cscyoff = tr->cscyoff; + be->csczoff = tr->csczoff; +// FIX!!! missing cscalpha + + be->scfhsr = tr->scfhsr; + be->scfvsr = tr->scfvsr; + be->scfdisable = tr->scfdisable; + + be->srccfg = tr->srccfg; + be->srcfhw = tr->srcfhw; + be->srcaaddr = tr->srcaaddr; + be->srcbaddr = tr->srcbaddr; + be->srccaddr = tr->srccaddr; + be->srcastr = tr->srcastr; + be->srcbstr = tr->srcbstr; + be->srccstr = tr->srccstr; + + be->dstaddr = tr->dstaddr; + be->dststr = tr->dststr; + be->dstheight = tr->dstheight; + be->dstcfg = tr->dstcfg; + + be->ctlintstat = ~0; + be->ctlintenable = MAEBE_CTLINTSTAT_FC; + +#if 1 + be->ctlfpc = MAEBE_CTLFPC_STR; // This starts the transaction; potential RACE!!!!! + interruptible_sleep_on(&maebe_state.wait); +#else + // This does not work properly; I think FC glitches + wait_event_interruptible(maebe_state.wait, (!(be->ctlfpc = MAEBE_CTLFPC_STR)) ); +#endif + + tr->endMipsCounter = maebe_state.endMipsCounter; +} + +////////////////////////////////////////////////////////////////////// +irqreturn_t maebe_handler(int irq, void *dev_id +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) + , struct pt_regs *regs +#endif +) +{ + AU1200_MAEBE * const be = (AU1200_MAEBE *)(0xA0000000|MAEBE_PHYS_ADDR); + + //disable_irq(maebe_state.irq); + + maebe_state.endMipsCounter = read_c0_count(); + be->ctlintstat = ~0; // ack interrupts + wake_up_interruptible(&maebe_state.wait); + + //enable_irq(maebe_state.irq); + + return IRQ_HANDLED; +} + +////////////////////////////////////////////////////////////////////// +static int +maebe_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + AU1X00_SYS * const sys = (AU1X00_SYS *)(0xA0000000|SYS_PHYS_ADDR); + mae_be_request_t *usr = (mae_be_request_t *)arg; // FIX ideally need to copy_from_user(), but not necessary on mips + + switch (cmd) + { + case MAEBE_IOCTL_INITIALIZE: + maebe_state.cached = usr->flags & MAEBE_FLAGS_CACHEABLE; + usr->memPhysAddr = maebe_state.physAddr; + usr->memPhysSize = maebe_state.physSize; + usr->counterFreq = sys->cpupll * 12000000; + break; + case MAEBE_IOCTL_SUBMIT_PICTURE: // FIX!!!! whats the point of a non-blocking call??? + be_submit(usr, 0); + break; + case MAEBE_IOCTL_SUBMIT_PICTURE_WITH_WAIT: + be_submit(usr, 1); + break; + default: + printk("error with maebe request %d\n", cmd); + break; + } + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maebe_mmap(struct file* file, struct vm_area_struct *vma) +{ + uint32 physAddr, physSize; + unsigned int len; + unsigned long start=0, off; + + physAddr = maebe_state.physAddr; + physSize = maebe_state.physSize; + ++maebe_state.mmapped; + + if (physAddr == 0 || physSize == 0) + return -EINVAL; + + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + { + printk(" Error vma->vm_pgoff > !OUL PAGE_SHIFT \n"); + return -EINVAL; + } + + start = physAddr & PAGE_MASK; + len = PAGE_ALIGN((start & ~PAGE_MASK) + physSize); + off = vma->vm_pgoff << PAGE_SHIFT; + + if ((vma->vm_end - vma->vm_start + off) > len) + { + printk(" Error vma->vm_end-vma->vm_start\n"); + return -EINVAL; + } + + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)) + if (maebe_state.cached) + { + pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; + pgprot_val(vma->vm_page_prot) |= _page_cachable_default; + } + else + { + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + pgprot_val(vma->vm_page_prot) |= _CACHE_MASK; /* CCA=7 */ + } +#else + pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; + pgprot_val(vma->vm_page_prot) |= PAGE_CACHABLE_DEFAULT; +#endif + + /* This is an IO map - tell maydump to skip this VMA */ + vma->vm_flags |= VM_IO; + + if ( +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)) + io_remap_pfn_range(vma,vma->vm_start, off >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot) +#else + io_remap_page_range(vma,vma->vm_start, off, + vma->vm_end - vma->vm_start, + vma->vm_page_prot) +#endif + ) + { + return -EAGAIN; + } + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maebe_open(struct inode *inode, struct file *file) +{ + maebe_state.mmapped = 0; + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maebe_release(struct inode *inode, struct file *file) +{ + maebe_state.mmapped = 0; + return 0; +} + +////////////////////////////////////////////////////////////////////// +static struct file_operations maebe_fops = +{ + owner: THIS_MODULE, + open: maebe_open, + ioctl: maebe_ioctl, + mmap: maebe_mmap, + release: maebe_release, +}; + +////////////////////////////////////////////////////////////////////// +static int __init +maebe_init(void) +{ + int rcode = 0; + + maebe_state.mmapped = 0; + maebe_state.physAddr = (uint32)base * (1024 * 1024); + maebe_state.physSize = (uint32)size * (1024 * 1024); + printk("MAEBE: physAddr %08X, physSize %08X\n", maebe_state.physAddr, maebe_state.physSize); + + maebe_state.irq = AU1200_MAE_BE_INT; + if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)) + maebe_state.irq += 8; + + init_waitqueue_head(&maebe_state.wait); + + /* Register Device*/ + rcode = register_chrdev(MAEBE_MAJOR, MAEBE_NAME, &maebe_fops); + if ( rcode < 0 ) + printk("\n Could not register MAEBE device\n"); + else + { + printk("Au12XX MAEBE driver registered Sucessfully v%s\n", VERSION); + if ( (rcode=request_irq(maebe_state.irq, maebe_handler, +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) + SA_SHIRQ | SA_INTERRUPT, +#else + IRQF_SHARED, +#endif + MAEBE_NAME, (void *)&maebe_state )) ) + { + printk("MAEBE: Could not get IRQ %d", maebe_state.irq); + } + else + be_init(); + } + + return rcode; +} + +////////////////////////////////////////////////////////////////////// +static void __exit +maebe_exit(void) +{ + be_deinit(); + unregister_chrdev(MAEBE_MAJOR, MAEBE_NAME); + free_irq(maebe_state.irq, (void *)&maebe_state); +} + +MODULE_AUTHOR("Eric DeVolder"); +MODULE_DESCRIPTION("Au12XX MAE Back End Driver"); +MODULE_LICENSE("GPL"); +module_init(maebe_init); +module_exit(maebe_exit); + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/maempe.c linux-2.6.29/drivers/media/alchemy/maempe.c --- linux-2.6.29/drivers/media/alchemy/maempe.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/maempe.c 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,290 @@ +/* + * maempe.c + * + * Copyright 2007 Eric DeVolder + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#include +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int + +#define AU13XX +#include "au1x00.h" +#include "maeioctl.h" +#include "mpe.h" + +#define AU1300_MAE_MPE_INT 93 + +#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg) + +#define MAEMPE_NAME "au13xx_maempe" +#define MAEMPE_MAJOR 242 +#define VERSION "1.0" +// mknod /dev/maempe c 242 0 + +#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) +INT_MODULE_PARM(pri0, 0x45617238); // hw default +INT_MODULE_PARM(pri1, 0x09000000); // hw default + +static struct maempe_state { + int irq; + uint32 endMipsCounter; + wait_queue_head_t wait; + +} maempe_state; + +////////////////////////////////////////////////////////////////////// +static void +maempe_reset (int reset) +{ + AU13XX_VSSCTRL *vss = (AU13XX_VSSCTRL *)(0xA0000000|VSS_PHYS_ADDR); + + if (reset) + { + vss->mpe.clkrst = 3; + } + else + { + vss->mpe.clkrst = 2; + + *(volatile uint32 *)0xB4016C0C = pri0; // mae_dma_pri0 + *(volatile uint32 *)0xB4016C10 = pri1; // mae_dma_pri1 + } +} + +////////////////////////////////////////////////////////////////////// +static void +maempe_power (int up) +{ + AU13XX_VSSCTRL *vss = (AU13XX_VSSCTRL *)(0xA0000000|VSS_PHYS_ADDR); + + if (up) + { + maempe_reset(1); + + vss->mpe.gate = 0x01fffffe; + vss->mpe.ftr = 1; + vss->mpe.ftr = 3; + vss->mpe.ftr = 7; + vss->mpe.ftr = 0xf; + + vss->mpe.gate = 0x01fffffF; + + maempe_reset(0); + + vss->mpe.ftr = 0x1f; + } + else + { + vss->mpe.ftr = 0xF; + vss->mpe.gate = 0; + vss->mpe.clkrst = 2; + vss->mpe.clkrst = 1; + vss->mpe.ftr = 0; + } +} + +////////////////////////////////////////////////////////////////////// +static void +maempe_transaction (mae_mpe_request_t *tr) +{ + mpe_t *mpe = (mpe_t *)(0xA0000000|MPE_PHYS_ADDR); + + tr->begMipsCounter = read_c0_count(); + + if (tr->flags & MAEMPE_FLAGS_DCWB) dma_cache_wback((unsigned long)tr, 16*1024); // writeback ENTIRE dcache + +#define WRREG(REG) { /*printk( #REG ": %08X\n", tr->REG);*/ mpe->REG = tr->REG; /*printk(#REG ": %08X\n", mpe->REG);*/ } + + // Write the registers + WRREG(cfg1); + WRREG(cfg2); + WRREG(cfg3); + WRREG(cfg4); + WRREG(cfg5); + WRREG(cfg6); + WRREG(cfg7); + WRREG(cfg8); + WRREG(cfg9); + WRREG(cfg10); + WRREG(cfg11); + WRREG(cfg12); + WRREG(cfg13); + WRREG(cfg14); + WRREG(cfg15); + WRREG(cfg18); + + mpe->cfg19 = 1; // interrupt mask enable + +#if 1 + mpe->cfg0 = MPE_CFG0_START; // start MPE, FIX!!! potential RACE!! + interruptible_sleep_on(&maempe_state.wait); +#else + wait_event_interruptible(maempe_state.wait, (!(mpe->cfg0 = MPE_CFG0_START)) ); +#endif + + tr->endMipsCounter = maempe_state.endMipsCounter; +} + +////////////////////////////////////////////////////////////////////// +irqreturn_t maempe_handler(int irq, void *dev_id) +{ + //disable_irq(maempe_state.irq); + + maempe_state.endMipsCounter = read_c0_count(); + + // Edge interrupt, no need to ack + wake_up_interruptible(&maempe_state.wait); + + //enable_irq(maempe_state.irq); + + return IRQ_HANDLED; +} + +////////////////////////////////////////////////////////////////////// +static int +maempe_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + mae_mpe_request_t *usr = (mae_mpe_request_t *)arg; + + switch (cmd) + { + case MAEMPE_IOCTL_SUBMIT_BUFFER: + maempe_transaction(usr); + break; + default: + printk("error with maempe request %d\n", cmd); + break; + } + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maempe_open(struct inode *inode, struct file *file) +{ + // FIX!!! only allow a single open!!!! + + // Cycle reset + maempe_reset(1); + maempe_reset(0); + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static int +maempe_release(struct inode *inode, struct file *file) +{ + maempe_reset(1); + + return 0; +} + +////////////////////////////////////////////////////////////////////// +static struct file_operations maempe_fops = +{ + owner: THIS_MODULE, + open: maempe_open, + ioctl: maempe_ioctl, + release: maempe_release, +}; + +////////////////////////////////////////////////////////////////////// +static int __init +maempe_init(void) +{ + int rcode = 0; + maempe_state.irq = AU1300_MAE_MPE_INT; + if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)) + maempe_state.irq += 8; + + init_waitqueue_head(&maempe_state.wait); + + // POWER CLOCKS RESET + maempe_power(1); + + /* Register Device*/ + rcode = register_chrdev(MAEMPE_MAJOR, MAEMPE_NAME, &maempe_fops); + if ( rcode < 0 ) + printk("\n Could not register MAE MPE device\n"); + else + { + printk("Au13XX MAEMPE driver registered Sucessfully v%s\n", VERSION); + + if ( (rcode=request_irq(maempe_state.irq, maempe_handler, + IRQF_SHARED, MAEMPE_NAME, (void *)&maempe_state )) ) + { + printk("MAEMPE: Could not get IRQ %d", maempe_state.irq); + } + } + + printk("mae_dma: pri0 %08X, pri1 %08X\n", pri0, pri1); + + return rcode; +} + +////////////////////////////////////////////////////////////////////// +static void __exit +maempe_exit(void) +{ + /*Unregister Device*/ + unregister_chrdev(MAEMPE_MAJOR, MAEMPE_NAME); + free_irq(maempe_state.irq, (void *)&maempe_state); + + maempe_power(0); +} + +////////////////////////////////////////////////////////////////////// + +MODULE_AUTHOR("Eric DeVolder"); +MODULE_DESCRIPTION("Au13XX MAE MPE Driver"); +MODULE_LICENSE("GPL"); +module_init(maempe_init); +module_exit(maempe_exit); + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/Makefile linux-2.6.29/drivers/media/alchemy/Makefile --- linux-2.6.29/drivers/media/alchemy/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/Makefile 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,7 @@ +# +# Makefile for Alchemy MAE device drivers +# + +obj-$(CONFIG_ALCHEMY_MAE_ITE) += maeite.o +obj-$(CONFIG_ALCHEMY_MAE_BSA) += maebsa.o +obj-$(CONFIG_ALCHEMY_MAE_MPE) += maempe.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/alchemy/mpe.h linux-2.6.29/drivers/media/alchemy/mpe.h --- linux-2.6.29/drivers/media/alchemy/mpe.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/media/alchemy/mpe.h 2009-09-02 10:21:37.000000000 -0400 @@ -0,0 +1,126 @@ + +#ifndef __mpe_h__ +#define __mpe_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +////////////////////////////////////////////////////////////////////// + +#define MPE_CFG0 0x0000 +#define MPE_CFG1 0x0004 +#define MPE_CFG2 0x0008 +#define MPE_CFG3 0x000C +#define MPE_CFG4 0x0010 +#define MPE_CFG5 0x0014 +#define MPE_CFG6 0x0018 +#define MPE_CFG7 0x001C +#define MPE_CFG8 0x0020 +#define MPE_CFG9 0x0024 +#define MPE_CFG10 0x0028 +#define MPE_CFG11 0x002C +#define MPE_CFG12 0x0030 +#define MPE_CFG13 0x0034 +#define MPE_CFG14 0x0038 +#define MPE_CFG15 0x003C +#define MPE_CFG16 0x0040 +#define MPE_CFG17 0x0044 +#define MPE_CFG18 0x0048 + +#ifndef ASSEMBLER +typedef volatile struct +{ + uint32 cfg0; + uint32 cfg1; + uint32 cfg2; + uint32 cfg3; + uint32 cfg4; + uint32 cfg5; + uint32 cfg6; + uint32 cfg7; + uint32 cfg8; + uint32 cfg9; + uint32 cfg10; + uint32 cfg11; + uint32 cfg12; + uint32 cfg13; + uint32 cfg14; + uint32 cfg15; + uint32 cfg16; + uint32 cfg17; + uint32 cfg18; + uint32 cfg19; + +} mpe_t; +#endif + +#define MPE_CFG0_START (1<<0) + +#define MPE_CFG4_MEMORYSTRIDE(X) ((X)<<0) + +#define MPE_CFG5_PICSIZEVERT(X) ((X)<<9) +#define MPE_CFG5_PICSIZEHORIZ(X) ((X)<<0) + +#define MPE_CFG6_ODDEN (1<<21) +#define MPE_CFG6_IQADD1 (1<<20) +#define MPE_CFG6_IQMUL1 (1<<19) +#define MPE_CFG6_CHROMAQP(X) (((X)&0x1F)<<14) +#define MPE_CFG6_PICINITQP(X) (((X)&0x3F)<<8) +#define MPE_CFG6_PICINITQS(X) (((X)&0x3F)<<2) +#define MPE_CFG6_MMCEN (1<<1) +#define MPE_CFG6_SATEN (1<<0) + +#define MPE_CFG7_DYNAMICAPRONEN (1<<11) +#define MPE_CFG7_APRONMODE_DISABLE (0<<8) +#define MPE_CFG7_APRONMODE_FRAME (1<<8) +#define MPE_CFG7_APRONMODE_FIELD (2<<8) +#define MPE_CFG7_APRONMODE_FIXED (3<<8) +#define MPE_CFG7_APRONFIXEDVALUE(X) ((X)<<0) + +#define MPE_CFG8_VC1MAINPROFILE (1<<10) +#define MPE_CFG8_CONINTRAPREDFLAG(X) (X<<9) +#define MPE_CFG8_PICTURETYPE_PROGRESSIVE_FRAME (0<<7) +#define MPE_CFG8_PICTURETYPE_INTERLACED_FRAME (2<<7) +#define MPE_CFG8_PICTURETYPE_INTERLACED_FIELD (3<<7) +#define MPE_CFG8_CODECTYPE_MPEG1_MPEG2 (0<<3) +#define MPE_CFG8_CODECTYPE_MPEG4 (1<<3) +#define MPE_CFG8_CODECTYPE_VC1_WMV9_SIMPLE_MAIN (2<<3) +#define MPE_CFG8_CODECTYPE_VC1_WMV9_ADVANCED (3<<3) +#define MPE_CFG8_CODECTYPE_H264_CABAC (4<<3) +#define MPE_CFG8_CODECTYPE_H264_CAVLC (5<<3) +#define MPE_CFG8_CODECTYPE_JPEG (7<<3) +#define MPE_CFG8_BLOCKCOUNT_420 (0<<1) +#define MPE_CFG8_BLOCKCOUNT_422 (1<<1) +#define MPE_CFG8_BLOCKCOUNT_444 (2<<1) +#define MPE_CFG8_BLOCKCOUNT_411 (3<<1) +#define MPE_CFG8_QUANTTYPE(X) (X<<0) + +#define MPE_CFG9_CONDOVER(X) ((X)<<17) +#define MPE_CFG9_VC1ICOMPEN (1<<16) +#define MPE_CFG9_VC1LUMSCALE(X) (((X)&0x3F)<<10) +#define MPE_CFG9_VC1LUMSHIFT(X) (((X)&0x3F)<<4) +#define MPE_CFG9_ILFILTEN (1<<3) +#define MPE_CFG9_LOOP (1<<2) +#define MPE_CFG9_OVERLAP (1<<0) + +#define MPE_CFG12_SCRATCHPADSIZE(X) ((X)<<0) + +#define MAE2_LUMA_APRON_HEIGHT 48 +#define MAE2_LUMA_APRON_WIDTH 24 +#define MAE2_CHROMA_APRON_HEIGHT 24 +#define MAE2_CHROMA_APRON_WIDTH 24 + +// Base addresses from the Au1 perspective +#define MPE_PHYS_ADDR 0x14014000 + +#define SCRATCH_BYTES_PER_MB (372*4) + +////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +#endif // __mpe_h__ + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/Kconfig linux-2.6.29/drivers/media/Kconfig --- linux-2.6.29/drivers/media/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/media/Kconfig 2009-06-03 10:57:38.000000000 -0400 @@ -136,4 +136,13 @@ module will be called dabusb. endif # DAB +# +# Alchemy MAE drivers +# +menu "Alchemy MAE" + depends on SOC_AU13XX + +source "drivers/media/alchemy/Kconfig" +endmenu + endmenu diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/media/Makefile linux-2.6.29/drivers/media/Makefile --- linux-2.6.29/drivers/media/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/media/Makefile 2009-06-03 10:57:38.000000000 -0400 @@ -2,7 +2,7 @@ # Makefile for the kernel multimedia device drivers. # -obj-y += common/ video/ +obj-y += common/ video/ alchemy/ obj-$(CONFIG_VIDEO_DEV) += radio/ obj-$(CONFIG_DVB_CORE) += dvb/ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/misc/Kconfig linux-2.6.29/drivers/misc/Kconfig --- linux-2.6.29/drivers/misc/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/misc/Kconfig 2009-09-02 10:43:51.000000000 -0400 @@ -12,6 +12,9 @@ If you say N, all options in this submenu will be skipped and disabled. if MISC_DEVICES +config ANDROID_PMEM + bool "Android pmem allocator" + default y config ATMEL_PWM tristate "Atmel AT32/AT91 PWM support" diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/misc/Makefile linux-2.6.29/drivers/misc/Makefile --- linux-2.6.29/drivers/misc/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/misc/Makefile 2009-09-02 10:43:51.000000000 -0400 @@ -12,6 +12,7 @@ obj-$(CONFIG_TIFM_CORE) += tifm_core.o obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o obj-$(CONFIG_PHANTOM) += phantom.o +obj-$(CONFIG_ANDROID_PMEM) += pmem.o obj-$(CONFIG_SGI_IOC4) += ioc4.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o obj-$(CONFIG_KGDB_TESTS) += kgdbts.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/misc/pmem.c linux-2.6.29/drivers/misc/pmem.c --- linux-2.6.29/drivers/misc/pmem.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/misc/pmem.c 2009-09-04 09:36:38.000000000 -0400 @@ -0,0 +1,1349 @@ +/* drivers/android/pmem.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMEM_MAX_DEVICES 10 +#define PMEM_MAX_ORDER 128 +#define PMEM_MIN_ALLOC PAGE_SIZE + +#define PMEM_DEBUG 1 + +/* indicates that a refernce to this file has been taken via get_pmem_file, + * the file should not be released until put_pmem_file is called */ +#define PMEM_FLAGS_BUSY 0x1 +/* indicates that this is a suballocation of a larger master range */ +#define PMEM_FLAGS_CONNECTED 0x1 << 1 +/* indicates this is a master and not a sub allocation and that it is mmaped */ +#define PMEM_FLAGS_MASTERMAP 0x1 << 2 +/* submap and unsubmap flags indicate: + * 00: subregion has never been mmaped + * 10: subregion has been mmaped, reference to the mm was taken + * 11: subretion has ben released, refernece to the mm still held + * 01: subretion has been released, reference to the mm has been released + */ +#define PMEM_FLAGS_SUBMAP 0x1 << 3 +#define PMEM_FLAGS_UNSUBMAP 0x1 << 4 + + +struct pmem_data { + /* in alloc mode: an index into the bitmap + * in no_alloc mode: the size of the allocation */ + int index; + /* see flags above for descriptions */ + unsigned int flags; + /* protects this data field, if the mm_mmap sem will be held at the + * same time as this sem, the mm sem must be taken first (as this is + * the order for vma_open and vma_close ops */ + struct rw_semaphore sem; + /* info about the mmaping process */ + struct vm_area_struct *vma; + /* task struct of the mapping process */ + struct task_struct *task; + /* process id of teh mapping process */ + pid_t pid; + /* file descriptor of the master */ + int master_fd; + /* file struct of the master */ + struct file *master_file; + /* a list of currently available regions if this is a suballocation */ + struct list_head region_list; + /* a linked list of data so we can access them for debugging */ + struct list_head list; +#if PMEM_DEBUG + int ref; +#endif +}; + +struct pmem_bits { + unsigned allocated:1; /* 1 if allocated, 0 if free */ + unsigned order:7; /* size of the region in pmem space */ +}; + +struct pmem_region_node { + struct pmem_region region; + struct list_head list; +}; + +#define PMEM_DEBUG_MSGS 0 +#if PMEM_DEBUG_MSGS +#define DLOG(fmt,args...) \ + do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \ + ##args); } \ + while (0) +#else +#define DLOG(x...) do {} while (0) +#endif + +struct pmem_info { + struct miscdevice dev; + /* physical start address of the remaped pmem space */ + unsigned long base; + /* vitual start address of the remaped pmem space */ + unsigned char __iomem *vbase; + /* total size of the pmem space */ + unsigned long size; + /* number of entries in the pmem space */ + unsigned long num_entries; + /* pfn of the garbage page in memory */ + unsigned long garbage_pfn; + /* index of the garbage page in the pmem space */ + int garbage_index; + /* the bitmap for the region indicating which entries are allocated + * and which are free */ + struct pmem_bits *bitmap; + /* indicates the region should not be managed with an allocator */ + unsigned no_allocator; + /* indicates maps of this region should be cached, if a mix of + * cached and uncached is desired, set this and open the device with + * O_SYNC to get an uncached region */ + unsigned cached; + unsigned buffered; + /* in no_allocator mode the first mapper gets the whole space and sets + * this flag */ + unsigned allocated; + /* for debugging, creates a list of pmem file structs, the + * data_list_sem should be taken before pmem_data->sem if both are + * needed */ + struct semaphore data_list_sem; + struct list_head data_list; + /* pmem_sem protects the bitmap array + * a write lock should be held when modifying entries in bitmap + * a read lock should be held when reading data from bits or + * dereferencing a pointer into bitmap + * + * pmem_data->sem protects the pmem data of a particular file + * Many of the function that require the pmem_data->sem have a non- + * locking version for when the caller is already holding that sem. + * + * IF YOU TAKE BOTH LOCKS TAKE THEM IN THIS ORDER: + * down(pmem_data->sem) => down(bitmap_sem) + */ + struct rw_semaphore bitmap_sem; + + long (*ioctl)(struct file *, unsigned int, unsigned long); + int (*release)(struct inode *, struct file *); +}; + +static struct pmem_info pmem[PMEM_MAX_DEVICES]; +static int id_count; + +#define PMEM_IS_FREE(id, index) !(pmem[id].bitmap[index].allocated) +#define PMEM_ORDER(id, index) pmem[id].bitmap[index].order +#define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index))) +#define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index))) +#define PMEM_OFFSET(index) (index * PMEM_MIN_ALLOC) +#define PMEM_START_ADDR(id, index) (PMEM_OFFSET(index) + pmem[id].base) +#define PMEM_LEN(id, index) ((1 << PMEM_ORDER(id, index)) * PMEM_MIN_ALLOC) +#define PMEM_END_ADDR(id, index) (PMEM_START_ADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_START_VADDR(id, index) (PMEM_OFFSET(id, index) + pmem[id].vbase) +#define PMEM_END_VADDR(id, index) (PMEM_START_VADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_REVOKED(data) (data->flags & PMEM_FLAGS_REVOKED) +#define PMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK))) +#define PMEM_IS_SUBMAP(data) ((data->flags & PMEM_FLAGS_SUBMAP) && \ + (!(data->flags & PMEM_FLAGS_UNSUBMAP))) + +static int pmem_release(struct inode *, struct file *); +static int pmem_mmap(struct file *, struct vm_area_struct *); +static int pmem_open(struct inode *, struct file *); +static long pmem_ioctl(struct file *, unsigned int, unsigned long); + +struct file_operations pmem_fops = { + .release = pmem_release, + .mmap = pmem_mmap, + .open = pmem_open, + .unlocked_ioctl = pmem_ioctl, +}; + +static int get_id(struct file *file) +{ + return MINOR(file->f_dentry->d_inode->i_rdev); +} + +int is_pmem_file(struct file *file) +{ + int id; + + if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode)) + return 0; + id = get_id(file); + if (unlikely(id >= PMEM_MAX_DEVICES)) + return 0; + if (unlikely(file->f_dentry->d_inode->i_rdev != + MKDEV(MISC_MAJOR, pmem[id].dev.minor))) + return 0; + return 1; +} + +static int has_allocation(struct file *file) +{ + struct pmem_data *data; + /* check is_pmem_file first if not accessed via pmem_file_ops */ + + if (unlikely(!file->private_data)) + return 0; + data = (struct pmem_data *)file->private_data; + if (unlikely(data->index < 0)) + return 0; + return 1; +} + +static int is_master_owner(struct file *file) +{ + struct file *master_file; + struct pmem_data *data; + int put_needed, ret = 0; + + if (!is_pmem_file(file) || !has_allocation(file)) + return 0; + data = (struct pmem_data *)file->private_data; + if (PMEM_FLAGS_MASTERMAP & data->flags) + return 1; + master_file = fget_light(data->master_fd, &put_needed); + if (master_file && data->master_file == master_file) + ret = 1; + fput_light(master_file, put_needed); + return ret; +} + +static int pmem_free(int id, int index) +{ + /* caller should hold the write lock on pmem_sem! */ + int buddy, curr = index; + DLOG("index %d\n", index); + + if (pmem[id].no_allocator) { + pmem[id].allocated = 0; + return 0; + } + /* clean up the bitmap, merging any buddies */ + pmem[id].bitmap[curr].allocated = 0; + /* find a slots buddy Buddy# = Slot# ^ (1 << order) + * if the buddy is also free merge them + * repeat until the buddy is not free or end of the bitmap is reached + */ + do { + buddy = PMEM_BUDDY_INDEX(id, curr); + if (PMEM_IS_FREE(id, buddy) && + PMEM_ORDER(id, buddy) == PMEM_ORDER(id, curr)) { + PMEM_ORDER(id, buddy)++; + PMEM_ORDER(id, curr)++; + curr = min(buddy, curr); + } else { + break; + } + } while (curr < pmem[id].num_entries); + + return 0; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data); + +static int pmem_release(struct inode *inode, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + int id = get_id(file), ret = 0; + + + down(&pmem[id].data_list_sem); + /* if this file is a master, revoke all the memory in the connected + * files */ + if (PMEM_FLAGS_MASTERMAP & data->flags) { + struct pmem_data *sub_data; + list_for_each(elt, &pmem[id].data_list) { + sub_data = list_entry(elt, struct pmem_data, list); + down_read(&sub_data->sem); + if (PMEM_IS_SUBMAP(sub_data) && + file == sub_data->master_file) { + up_read(&sub_data->sem); + pmem_revoke(file, sub_data); + } else + up_read(&sub_data->sem); + } + } + list_del(&data->list); + up(&pmem[id].data_list_sem); + + + down_write(&data->sem); + + /* if its not a conencted file and it has an allocation, free it */ + if (!(PMEM_FLAGS_CONNECTED & data->flags) && has_allocation(file)) { + down_write(&pmem[id].bitmap_sem); + ret = pmem_free(id, data->index); + up_write(&pmem[id].bitmap_sem); + } + + /* if this file is a submap (mapped, connected file), downref the + * task struct */ + if (PMEM_FLAGS_SUBMAP & data->flags) + if (data->task) { + put_task_struct(data->task); + data->task = NULL; + } + + file->private_data = NULL; + + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + list_del(elt); + kfree(region_node); + } + BUG_ON(!list_empty(&data->region_list)); + + up_write(&data->sem); + kfree(data); + if (pmem[id].release) + ret = pmem[id].release(inode, file); + + return ret; +} + +static int pmem_open(struct inode *inode, struct file *file) +{ + struct pmem_data *data; + int id = get_id(file); + int ret = 0; + + DLOG("current %u file %p(%d)\n", current->pid, file, file_count(file)); + /* setup file->private_data to indicate its unmapped */ + /* you can only open a pmem device one time */ + if (file->private_data != NULL) + return -1; + data = kmalloc(sizeof(struct pmem_data), GFP_KERNEL); + if (!data) { + printk("pmem: unable to allocate memory for pmem metadata."); + return -1; + } + data->flags = 0; + data->index = -1; + data->task = NULL; + data->vma = NULL; + data->pid = 0; + data->master_file = NULL; +#if PMEM_DEBUG + data->ref = 0; +#endif + INIT_LIST_HEAD(&data->region_list); + init_rwsem(&data->sem); + + file->private_data = data; + INIT_LIST_HEAD(&data->list); + + down(&pmem[id].data_list_sem); + list_add(&data->list, &pmem[id].data_list); + up(&pmem[id].data_list_sem); + return ret; +} + +static unsigned long pmem_order(unsigned long len) +{ + int i; + + len = (len + PMEM_MIN_ALLOC - 1)/PMEM_MIN_ALLOC; + len--; + for (i = 0; i < sizeof(len)*8; i++) + if (len >> i == 0) + break; + return i; +} + +static int pmem_allocate(int id, unsigned long len) +{ + /* caller should hold the write lock on pmem_sem! */ + /* return the corresponding pdata[] entry */ + int curr = 0; + int end = pmem[id].num_entries; + int best_fit = -1; + unsigned long order = pmem_order(len); + + if (pmem[id].no_allocator) { + DLOG("no allocator"); + if ((len > pmem[id].size) || pmem[id].allocated) + return -1; + pmem[id].allocated = 1; + return len; + } + + if (order > PMEM_MAX_ORDER) + return -1; + DLOG("order %lx\n", order); + + /* look through the bitmap: + * if you find a free slot of the correct order use it + * otherwise, use the best fit (smallest with size > order) slot + */ + while (curr < end) { + if (PMEM_IS_FREE(id, curr)) { + if (PMEM_ORDER(id, curr) == (unsigned char)order) { + /* set the not free bit and clear others */ + best_fit = curr; + break; + } + if (PMEM_ORDER(id, curr) > (unsigned char)order && + (best_fit < 0 || + PMEM_ORDER(id, curr) < PMEM_ORDER(id, best_fit))) + best_fit = curr; + } + curr = PMEM_NEXT_INDEX(id, curr); + } + + /* if best_fit < 0, there are no suitable slots, + * return an error + */ + if (best_fit < 0) { + printk("pmem: no space left to allocate!\n"); + return -1; + } + + /* now partition the best fit: + * split the slot into 2 buddies of order - 1 + * repeat until the slot is of the correct order + */ + while (PMEM_ORDER(id, best_fit) > (unsigned char)order) { + int buddy; + PMEM_ORDER(id, best_fit) -= 1; + buddy = PMEM_BUDDY_INDEX(id, best_fit); + PMEM_ORDER(id, buddy) = PMEM_ORDER(id, best_fit); + } + pmem[id].bitmap[best_fit].allocated = 1; + return best_fit; +} + +static pgprot_t phys_mem_access_prot(struct file *file, pgprot_t vma_prot) +{ + int id = get_id(file); +#ifdef pgprot_noncached + if (pmem[id].cached == 0 || file->f_flags & O_SYNC) + return pgprot_noncached(vma_prot); +#endif +#ifdef pgprot_ext_buffered + else if (pmem[id].buffered) + return pgprot_ext_buffered(vma_prot); +#endif + return vma_prot; +} + +static unsigned long pmem_start_addr(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return PMEM_START_ADDR(id, 0); + else + return PMEM_START_ADDR(id, data->index); + +} + +static void *pmem_start_vaddr(int id, struct pmem_data *data) +{ + return pmem_start_addr(id, data) - pmem[id].base + pmem[id].vbase; +} + +static unsigned long pmem_len(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return data->index; + else + return PMEM_LEN(id, data->index); +} + +static int pmem_map_garbage(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int i, garbage_pages = len >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP | VM_SHARED | VM_WRITE; + for (i = 0; i < garbage_pages; i++) { + if (vm_insert_pfn(vma, vma->vm_start + offset + (i * PAGE_SIZE), + pmem[id].garbage_pfn)) + return -EAGAIN; + } + return 0; +} + +static int pmem_unmap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int garbage_pages; + DLOG("unmap offset %lx len %lx\n", offset, len); + + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + + garbage_pages = len >> PAGE_SHIFT; + zap_page_range(vma, vma->vm_start + offset, len, NULL); + pmem_map_garbage(id, vma, data, offset, len); + return 0; +} + +static int pmem_map_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + DLOG("map offset %lx len %lx\n", offset, len); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_start)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_end)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(offset)); + + if (io_remap_pfn_range(vma, vma->vm_start + offset, + (pmem_start_addr(id, data) + offset) >> PAGE_SHIFT, + len, vma->vm_page_prot)) { + return -EAGAIN; + } + return 0; +} + +static int pmem_remap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + /* hold the mm semp for the vma you are modifying when you call this */ + BUG_ON(!vma); + zap_page_range(vma, vma->vm_start + offset, len, NULL); + return pmem_map_pfn_range(id, vma, data, offset, len); +} + +static void pmem_vma_open(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + int id = get_id(file); + /* this should never be called as we don't support copying pmem + * ranges via fork */ + BUG_ON(!has_allocation(file)); + down_write(&data->sem); + /* remap the garbage pages, forkers don't get access to the data */ + pmem_unmap_pfn_range(id, vma, data, 0, vma->vm_start - vma->vm_end); + up_write(&data->sem); +} + +static void pmem_vma_close(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + + DLOG("current %u ppid %u file %p count %d\n", current->pid, + current->parent->pid, file, file_count(file)); + if (unlikely(!is_pmem_file(file) || !has_allocation(file))) { + printk(KERN_WARNING "pmem: something is very wrong, you are " + "closing a vm backing an allocation that doesn't " + "exist!\n"); + return; + } + down_write(&data->sem); + if (data->vma == vma) { + data->vma = NULL; + if ((data->flags & PMEM_FLAGS_CONNECTED) && + (data->flags & PMEM_FLAGS_SUBMAP)) + data->flags |= PMEM_FLAGS_UNSUBMAP; + } + /* the kernel is going to free this vma now anyway */ + up_write(&data->sem); +} + +static struct vm_operations_struct vm_ops = { + .open = pmem_vma_open, + .close = pmem_vma_close, +}; + +static int pmem_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pmem_data *data; + int index; + unsigned long vma_size = vma->vm_end - vma->vm_start; + int ret = 0, id = get_id(file); + + if (vma->vm_pgoff || !PMEM_IS_PAGE_ALIGNED(vma_size)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: mmaps must be at offset zero, aligned" + " and a multiple of pages_size.\n"); +#endif + return -EINVAL; + } + + data = (struct pmem_data *)file->private_data; + down_write(&data->sem); + /* check this file isn't already mmaped, for submaps check this file + * has never been mmaped */ + if ((data->flags & PMEM_FLAGS_MASTERMAP) || + (data->flags & PMEM_FLAGS_SUBMAP) || + (data->flags & PMEM_FLAGS_UNSUBMAP)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: you can only mmap a pmem file once, " + "this file is already mmaped. %x\n", data->flags); +#endif + ret = -EINVAL; + goto error; + } + /* if file->private_data == unalloced, alloc*/ + if (data && data->index == -1) { + down_write(&pmem[id].bitmap_sem); + index = pmem_allocate(id, vma->vm_end - vma->vm_start); + up_write(&pmem[id].bitmap_sem); + data->index = index; + } + /* either no space was available or an error occured */ + if (!has_allocation(file)) { + ret = -EINVAL; + printk("pmem: could not find allocation for map.\n"); + goto error; + } + + if (pmem_len(id, data) < vma_size) { +#if PMEM_DEBUG + printk(KERN_WARNING "pmem: mmap size [%lu] does not match" + "size of backing region [%lu].\n", vma_size, + pmem_len(id, data)); +#endif + ret = -EINVAL; + goto error; + } + + vma->vm_pgoff = pmem_start_addr(id, data) >> PAGE_SHIFT; + vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_page_prot); + + if (data->flags & PMEM_FLAGS_CONNECTED) { + struct pmem_region_node *region_node; + struct list_head *elt; + if (pmem_map_garbage(id, vma, data, 0, vma_size)) { + printk("pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + DLOG("remapping file: %p %lx %lx\n", file, + region_node->region.offset, + region_node->region.len); + if (pmem_remap_pfn_range(id, vma, data, + region_node->region.offset, + region_node->region.len)) { + ret = -EAGAIN; + goto error; + } + } + data->flags |= PMEM_FLAGS_SUBMAP; + get_task_struct(current->group_leader); + data->task = current->group_leader; + data->vma = vma; +#if PMEM_DEBUG + data->pid = current->pid; +#endif + DLOG("submmapped file %p vma %p pid %u\n", file, vma, + current->pid); + } else { + if (pmem_map_pfn_range(id, vma, data, 0, vma_size)) { + printk(KERN_INFO "pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + data->flags |= PMEM_FLAGS_MASTERMAP; + data->pid = current->pid; + } + vma->vm_ops = &vm_ops; +error: + up_write(&data->sem); + return ret; +} + +/* the following are the api for accessing pmem regions by other drivers + * from inside the kernel */ +int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *len) +{ + struct pmem_data *data; + if (!is_pmem_file(file) || !has_allocation(file)) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from invalid" + "file.\n"); +#endif + return -1; + } + data = (struct pmem_data *)file->private_data; + down_read(&data->sem); + if (data->vma) { + *start = data->vma->vm_start; + *len = data->vma->vm_end - data->vma->vm_start; + } else { + *start = 0; + *len = 0; + } + up_read(&data->sem); + return 0; +} + +int get_pmem_addr(struct file *file, unsigned long *start, + unsigned long *vstart, unsigned long *len) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file) || !has_allocation(file)) { + return -1; + } + + data = (struct pmem_data *)file->private_data; + if (data->index == -1) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from file with no " + "allocation.\n"); + return -1; +#endif + } + id = get_id(file); + + down_read(&data->sem); + *start = pmem_start_addr(id, data); + *len = pmem_len(id, data); + *vstart = (unsigned long)pmem_start_vaddr(id, data); + up_read(&data->sem); +#if PMEM_DEBUG + down_write(&data->sem); + data->ref++; + up_write(&data->sem); +#endif + return 0; +} + +int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart, + unsigned long *len, struct file **filp) +{ + struct file *file; + + file = fget(fd); + if (unlikely(file == NULL)) { + printk(KERN_INFO "pmem: requested data from file descriptor " + "that doesn't exist."); + return -1; + } + + if (get_pmem_addr(file, start, vstart, len)) + goto end; + + if (filp) + *filp = file; + return 0; +end: + fput(file); + return -1; +} + +void put_pmem_file(struct file *file) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file)) + return; + id = get_id(file); + data = (struct pmem_data *)file->private_data; +#if PMEM_DEBUG + down_write(&data->sem); + if (data->ref == 0) { + printk("pmem: pmem_put > pmem_get %s (pid %d)\n", + pmem[id].dev.name, data->pid); + BUG(); + } + data->ref--; + up_write(&data->sem); +#endif + fput(file); +} + +void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len) +{ + struct pmem_data *data; + int id; + void *vaddr; + struct pmem_region_node *region_node; + struct list_head *elt; + void *flush_start, *flush_end; + + if (!is_pmem_file(file) || !has_allocation(file)) { + return; + } + + id = get_id(file); + data = (struct pmem_data *)file->private_data; + if (!pmem[id].cached) + return; + + down_read(&data->sem); + vaddr = pmem_start_vaddr(id, data); + /* if this isn't a submmapped file, flush the whole thing */ + if (unlikely(!(data->flags & PMEM_FLAGS_CONNECTED))) { +#ifdef __arm__ + /* This uses the wrong API - should be dma_flush_range() */ + dmac_flush_range(vaddr, vaddr + pmem_len(id, data)); +#endif +#ifdef __mips__ + /* This uses the wrong API - should be ??? */ + dma_cache_wback_inv(vaddr, vaddr + pmem_len(id, data)); +#endif + goto end; + } + /* otherwise, flush the region of the file we are drawing */ + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + if ((offset >= region_node->region.offset) && + ((offset + len) <= (region_node->region.offset + + region_node->region.len))) { + flush_start = vaddr + region_node->region.offset; + flush_end = flush_start + region_node->region.len; +#ifdef __arm__ + /* This uses the wrong API - should be dma_flush_range() */ + dmac_flush_range(flush_start, flush_end); +#endif +#ifdef __mips__ + /* This uses the wrong API - should be ??? */ + dma_cache_wback_inv(vaddr, vaddr + pmem_len(id, data)); +#endif + break; + } + } +end: + up_read(&data->sem); +} + +static int pmem_connect(unsigned long connect, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_data *src_data; + struct file *src_file; + int ret = 0, put_needed; + + down_write(&data->sem); + /* retrieve the src file and check it is a pmem file with an alloc */ + src_file = fget_light(connect, &put_needed); + DLOG("connect %p to %p\n", file, src_file); + if (!src_file) { + printk("pmem: src file not found!\n"); + ret = -EINVAL; + goto err_no_file; + } + if (unlikely(!is_pmem_file(src_file) || !has_allocation(src_file))) { + printk(KERN_INFO "pmem: src file is not a pmem file or has no " + "alloc!\n"); + ret = -EINVAL; + goto err_bad_file; + } + src_data = (struct pmem_data *)src_file->private_data; + + if (has_allocation(file) && (data->index != src_data->index)) { + printk("pmem: file is already mapped but doesn't match this" + " src_file!\n"); + ret = -EINVAL; + goto err_bad_file; + } + data->index = src_data->index; + data->flags |= PMEM_FLAGS_CONNECTED; + data->master_fd = connect; + data->master_file = src_file; + +err_bad_file: + fput_light(src_file, put_needed); +err_no_file: + up_write(&data->sem); + return ret; +} + +static void pmem_unlock_data_and_mm(struct pmem_data *data, + struct mm_struct *mm) +{ + up_write(&data->sem); + if (mm != NULL) { + up_write(&mm->mmap_sem); + mmput(mm); + } +} + +static int pmem_lock_data_and_mm(struct file *file, struct pmem_data *data, + struct mm_struct **locked_mm) +{ + int ret = 0; + struct mm_struct *mm = NULL; + *locked_mm = NULL; +lock_mm: + down_read(&data->sem); + if (PMEM_IS_SUBMAP(data)) { + mm = get_task_mm(data->task); + if (!mm) { +#if PMEM_DEBUG + printk("pmem: can't remap task is gone!\n"); +#endif + up_read(&data->sem); + return -1; + } + } + up_read(&data->sem); + + if (mm) + down_write(&mm->mmap_sem); + + down_write(&data->sem); + /* check that the file didn't get mmaped before we could take the + * data sem, this should be safe b/c you can only submap each file + * once */ + if (PMEM_IS_SUBMAP(data) && !mm) { + pmem_unlock_data_and_mm(data, mm); + up_write(&data->sem); + goto lock_mm; + } + /* now check that vma.mm is still there, it could have been + * deleted by vma_close before we could get the data->sem */ + if ((data->flags & PMEM_FLAGS_UNSUBMAP) && (mm != NULL)) { + /* might as well release this */ + if (data->flags & PMEM_FLAGS_SUBMAP) { + put_task_struct(data->task); + data->task = NULL; + /* lower the submap flag to show the mm is gone */ + data->flags &= ~(PMEM_FLAGS_SUBMAP); + } + pmem_unlock_data_and_mm(data, mm); + return -1; + } + *locked_mm = mm; + return ret; +} + +int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation) +{ + int ret; + struct pmem_region_node *region_node; + struct mm_struct *mm = NULL; + struct list_head *elt, *elt2; + int id = get_id(file); + struct pmem_data *data = (struct pmem_data *)file->private_data; + + /* pmem region must be aligned on a page boundry */ + if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) || + !PMEM_IS_PAGE_ALIGNED(region->len))) { +#if PMEM_DEBUG + printk("pmem: request for unaligned pmem suballocation " + "%lx %lx\n", region->offset, region->len); +#endif + return -EINVAL; + } + + /* if userspace requests a region of len 0, there's nothing to do */ + if (region->len == 0) + return 0; + + /* lock the mm and data */ + ret = pmem_lock_data_and_mm(file, data, &mm); + if (ret) + return 0; + + /* only the owner of the master file can remap the client fds + * that back in it */ + if (!is_master_owner(file)) { +#if PMEM_DEBUG + printk("pmem: remap requested from non-master process\n"); +#endif + ret = -EINVAL; + goto err; + } + + /* check that the requested range is within the src allocation */ + if (unlikely((region->offset > pmem_len(id, data)) || + (region->len > pmem_len(id, data)) || + (region->offset + region->len > pmem_len(id, data)))) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: suballoc doesn't fit in src_file!\n"); +#endif + ret = -EINVAL; + goto err; + } + + if (operation == PMEM_MAP) { + region_node = kmalloc(sizeof(struct pmem_region_node), + GFP_KERNEL); + if (!region_node) { + ret = -ENOMEM; +#if PMEM_DEBUG + printk(KERN_INFO "No space to allocate metadata!"); +#endif + goto err; + } + region_node->region = *region; + list_add(®ion_node->list, &data->region_list); + } else if (operation == PMEM_UNMAP) { + int found = 0; + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + if (region->len == 0 || + (region_node->region.offset == region->offset && + region_node->region.len == region->len)) { + list_del(elt); + kfree(region_node); + found = 1; + } + } + if (!found) { +#if PMEM_DEBUG + printk("pmem: Unmap region does not map any mapped " + "region!"); +#endif + ret = -EINVAL; + goto err; + } + } + + if (data->vma && PMEM_IS_SUBMAP(data)) { + if (operation == PMEM_MAP) + ret = pmem_remap_pfn_range(id, data->vma, data, + region->offset, region->len); + else if (operation == PMEM_UNMAP) + ret = pmem_unmap_pfn_range(id, data->vma, data, + region->offset, region->len); + } + +err: + pmem_unlock_data_and_mm(data, mm); + return ret; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data) +{ + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + struct mm_struct *mm = NULL; + int id = get_id(file); + int ret = 0; + + data->master_file = NULL; + ret = pmem_lock_data_and_mm(file, data, &mm); + /* if lock_data_and_mm fails either the task that mapped the fd, or + * the vma that mapped it have already gone away, nothing more + * needs to be done */ + if (ret) + return; + /* unmap everything */ + /* delete the regions and region list nothing is mapped any more */ + if (data->vma) + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + pmem_unmap_pfn_range(id, data->vma, data, + region_node->region.offset, + region_node->region.len); + list_del(elt); + kfree(region_node); + } + /* delete the master file */ + pmem_unlock_data_and_mm(data, mm); +} + +static void pmem_get_size(struct pmem_region *region, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + int id = get_id(file); + + if (!has_allocation(file)) { + region->offset = 0; + region->len = 0; + return; + } else { + region->offset = pmem_start_addr(id, data); + region->len = pmem_len(id, data); + } + DLOG("offset %lx len %lx\n", region->offset, region->len); +} + + +static long pmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct pmem_data *data; + int id = get_id(file); + + switch (cmd) { + case PMEM_GET_PHYS: + { + struct pmem_region region; + DLOG("get_phys\n"); + if (!has_allocation(file)) { + region.offset = 0; + region.len = 0; + } else { + data = (struct pmem_data *)file->private_data; + region.offset = pmem_start_addr(id, data); + region.len = pmem_len(id, data); + } + printk(KERN_INFO "pmem: request for physical address of pmem region " + "from process %d.\n", current->pid); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_MAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_MAP); + } + break; + case PMEM_UNMAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_UNMAP); + break; + } + case PMEM_GET_SIZE: + { + struct pmem_region region; + DLOG("get_size\n"); + pmem_get_size(®ion, file); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_GET_TOTAL_SIZE: + { + struct pmem_region region; + DLOG("get total size\n"); + region.offset = 0; + get_id(file); + region.len = pmem[id].size; + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_ALLOCATE: + { + if (has_allocation(file)) + return -EINVAL; + data = (struct pmem_data *)file->private_data; + data->index = pmem_allocate(id, arg); + break; + } + case PMEM_CONNECT: + DLOG("connect\n"); + return pmem_connect(arg, file); + break; + default: + if (pmem[id].ioctl) + return pmem[id].ioctl(file, cmd, arg); + return -EINVAL; + } + return 0; +} + +#if PMEM_DEBUG +static ssize_t debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t debug_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct list_head *elt, *elt2; + struct pmem_data *data; + struct pmem_region_node *region_node; + int id = (int)file->private_data; + const int debug_bufmax = 4096; + static char buffer[4096]; + int n = 0; + + DLOG("debug open\n"); + n = scnprintf(buffer, debug_bufmax, + "pid #: mapped regions (offset, len) (offset,len)...\n"); + + down(&pmem[id].data_list_sem); + list_for_each(elt, &pmem[id].data_list) { + data = list_entry(elt, struct pmem_data, list); + down_read(&data->sem); + n += scnprintf(buffer + n, debug_bufmax - n, "pid %u:", + data->pid); + list_for_each(elt2, &data->region_list) { + region_node = list_entry(elt2, struct pmem_region_node, + list); + n += scnprintf(buffer + n, debug_bufmax - n, + "(%lx,%lx) ", + region_node->region.offset, + region_node->region.len); + } + n += scnprintf(buffer + n, debug_bufmax - n, "\n"); + up_read(&data->sem); + } + up(&pmem[id].data_list_sem); + + n++; + buffer[n] = 0; + return simple_read_from_buffer(buf, count, ppos, buffer, n); +} + +static struct file_operations debug_fops = { + .read = debug_read, + .open = debug_open, +}; +#endif + +#if 0 +static struct miscdevice pmem_dev = { + .name = "pmem", + .fops = &pmem_fops, +}; +#endif + +int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)) +{ + int err = 0; + int i, index = 0; + int id = id_count; + id_count++; + + pmem[id].no_allocator = pdata->no_allocator; + pmem[id].cached = pdata->cached; + pmem[id].buffered = pdata->buffered; + pmem[id].base = pdata->start; + pmem[id].size = pdata->size; + pmem[id].ioctl = ioctl; + pmem[id].release = release; + init_rwsem(&pmem[id].bitmap_sem); + init_MUTEX(&pmem[id].data_list_sem); + INIT_LIST_HEAD(&pmem[id].data_list); + pmem[id].dev.name = pdata->name; + pmem[id].dev.minor = id; + pmem[id].dev.fops = &pmem_fops; + printk(KERN_INFO "%s: %d init\n", pdata->name, pdata->cached); + + err = misc_register(&pmem[id].dev); + if (err) { + printk(KERN_ALERT "Unable to register pmem driver!\n"); + goto err_cant_register_device; + } + pmem[id].num_entries = pmem[id].size / PMEM_MIN_ALLOC; + + pmem[id].bitmap = kmalloc(pmem[id].num_entries * + sizeof(struct pmem_bits), GFP_KERNEL); + if (!pmem[id].bitmap) + goto err_no_mem_for_metadata; + + memset(pmem[id].bitmap, 0, sizeof(struct pmem_bits) * + pmem[id].num_entries); + + for (i = sizeof(pmem[id].num_entries) * 8 - 1; i >= 0; i--) { + if ((pmem[id].num_entries) & 1<name, S_IFREG | S_IRUGO, NULL, (void *)id, + &debug_fops); +#endif + return 0; +error_cant_remap: + kfree(pmem[id].bitmap); +err_no_mem_for_metadata: + misc_deregister(&pmem[id].dev); +err_cant_register_device: + return -1; +} + +static int pmem_probe(struct platform_device *pdev) +{ + struct android_pmem_platform_data *pdata; + + if (!pdev || !pdev->dev.platform_data) { + printk(KERN_ALERT "Unable to probe pmem!\n"); + return -1; + } + pdata = pdev->dev.platform_data; + return pmem_setup(pdata, NULL, NULL); +} + + +static int pmem_remove(struct platform_device *pdev) +{ + int id = pdev->id; + __free_page(pfn_to_page(pmem[id].garbage_pfn)); + misc_deregister(&pmem[id].dev); + return 0; +} + +static struct platform_driver pmem_driver = { + .probe = pmem_probe, + .remove = pmem_remove, + .driver = { .name = "android_pmem" } +}; + + +static int __init pmem_init(void) +{ + return platform_driver_register(&pmem_driver); +} + +static void __exit pmem_exit(void) +{ + platform_driver_unregister(&pmem_driver); +} + +module_init(pmem_init); +module_exit(pmem_exit); + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/mmc/host/au1xmmc.c linux-2.6.29/drivers/mmc/host/au1xmmc.c --- linux-2.6.29/drivers/mmc/host/au1xmmc.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/mmc/host/au1xmmc.c 2009-08-17 09:11:44.000000000 -0400 @@ -41,11 +41,15 @@ #include #include #include +#include +#include + #include #include #include #include +#include "au1xmmc.h" #define DRIVER_NAME "au1xxx-mmc" @@ -59,8 +63,6 @@ #define DBG(fmt, idx, args...) do {} while (0) #endif -/* Hardware definitions */ -#define AU1XMMC_DESCRIPTOR_COUNT 1 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ #ifdef CONFIG_SOC_AU1100 @@ -69,15 +71,10 @@ #define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff #endif -#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ - MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ - MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) /* This gives us a hard value for the stop command that we can write directly * to the command register. */ -#define STOP_CMD \ - (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) /* This is the set of interrupts that we configure by default. */ #define AU1XMMC_INTERRUPTS \ @@ -87,40 +84,7 @@ /* The poll event (looking for insert/remove events runs twice a second. */ #define AU1XMMC_DETECT_TIMEOUT (HZ/2) -struct au1xmmc_host { - struct mmc_host *mmc; - struct mmc_request *mrq; - u32 flags; - u32 iobase; - u32 clock; - u32 bus_width; - u32 power_mode; - - int status; - - struct { - int len; - int dir; - } dma; - - struct { - int index; - int offset; - int len; - } pio; - - u32 tx_chan; - u32 rx_chan; - - int irq; - - struct tasklet_struct finish_task; - struct tasklet_struct data_task; - struct au1xmmc_platform_data *platdata; - struct platform_device *pdev; - struct resource *ioarea; -}; /* Status flags used by the host structure */ #define HOST_F_XMIT 0x0001 @@ -147,21 +111,25 @@ #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) -#define DMA_CHANNEL(h) \ - (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { - u32 val = au_readl(HOST_CONFIG(host)); - val |= mask; - au_writel(val, HOST_CONFIG(host)); - au_sync(); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&host->lock, flags); + val = au_readl(HOST_CONFIG(host)); + val |= mask; + au_writel(val, HOST_CONFIG(host)); + au_sync(); + spin_unlock_irqrestore(&host->lock, flags); } static inline void FLUSH_FIFO(struct au1xmmc_host *host) { - u32 val = au_readl(HOST_CONFIG2(host)); - + u32 val; + + val = au_readl(HOST_CONFIG2(host)); au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); au_sync_delay(1); @@ -174,12 +142,34 @@ static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) { - u32 val = au_readl(HOST_CONFIG(host)); - val &= ~mask; - au_writel(val, HOST_CONFIG(host)); - au_sync(); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&host->lock, flags); + val = au_readl(HOST_CONFIG(host)); + val &= ~mask; + au_writel(val, HOST_CONFIG(host)); + au_sync(); + spin_unlock_irqrestore(&host->lock, flags); +} + +static void IRQ_CLEAR(struct au1xmmc_host *host, u32 mask) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&host->lock,flags); + val = au_readl(HOST_STATUS(host)); + // Leave Level Triggered bit alone + val &= SD_INT_LT_MASK; + val |= (mask & SD_INT_ET_MASK); + if(val) { + au_writel(val, HOST_STATUS(host)); + } + spin_unlock_irqrestore(&host->lock,flags); } + static inline void SEND_STOP(struct au1xmmc_host *host) { u32 config2; @@ -249,13 +239,21 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, struct mmc_command *cmd, struct mmc_data *data) { - u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); + u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); + u32 blkSizeRegister; + u32 IOAbort = 0; // request is an IO Abort + static u32 lastCmd53 = 0; + u32 tmp = 0; + u32 i = 0; switch (mmc_resp_type(cmd)) { case MMC_RSP_NONE: break; case MMC_RSP_R1: - mmccmd |= SD_CMD_RT_1; + if ((cmd->opcode == SD_IO_RW_EXTENDED) || (cmd->opcode == SD_IO_RW_DIRECT)) + mmccmd |= SD_CMD_RT_5; + else + mmccmd |= SD_CMD_RT_1; break; case MMC_RSP_R1B: mmccmd |= SD_CMD_RT_1B; @@ -265,26 +263,120 @@ break; case MMC_RSP_R3: mmccmd |= SD_CMD_RT_3; - break; + break; default: printk(KERN_INFO "au1xmmc: unhandled response type %02x\n", mmc_resp_type(cmd)); return -EINVAL; } - if (data) { - if (data->flags & MMC_DATA_READ) { - if (data->blocks > 1) - mmccmd |= SD_CMD_CT_4; - else - mmccmd |= SD_CMD_CT_2; - } else if (data->flags & MMC_DATA_WRITE) { - if (data->blocks > 1) - mmccmd |= SD_CMD_CT_3; - else - mmccmd |= SD_CMD_CT_1; - } - } + if (data) { + if (cmd->opcode == SD_IO_RW_EXTENDED) { + if (IO_RW_EXTENDED_BLOCK_MODE(cmd->arg)) { + if (0 == IO_RW_EXTENDED_COUNT(cmd->arg)) { + if (data->flags & MMC_DATA_WRITE) + mmccmd |= SD_CMD_CT_3; + else + mmccmd |= SD_CMD_CT_4; + } + else { + if (data->flags & MMC_DATA_WRITE) + mmccmd |= SD_CMD_CT_5; + else + mmccmd |= SD_CMD_CT_6; + } + } + else { + if (data->flags & MMC_DATA_WRITE) + mmccmd |= SD_CMD_CT_1; + else + mmccmd |= SD_CMD_CT_2; + } + } + else { + if (data->flags & MMC_DATA_WRITE) { + if (data->blocks > 1) { + mmccmd |= SD_CMD_CT_3; + } + else + mmccmd |= SD_CMD_CT_1; + } else { + if (data->blocks > 1) { + mmccmd |= SD_CMD_CT_4; + } + else + mmccmd |= SD_CMD_CT_2; + } + + } + } + else if ((cmd->opcode == SD_IO_RW_DIRECT) && + (SDIO_CCCR_ABORT == IO_RW_DIRECT_ADDR_ARG(cmd->arg))) { + mmccmd |= SD_CMD_CT_8; + IOAbort = 1; + } + + if (( MMC_STOP_TRANSMISSION != cmd->opcode) && (!IOAbort)) { + //if the previous command is command 53 and the data busy bit is on, + // there is a chance that the clock may be frozen. Set DF to 1 to get + // the clock back. + if (lastCmd53 && (au_readl(HOST_STATUS(host)) & SD_STATUS_DB )) { + // printk("Set DF to 1 to get\n"); + tmp = au_readl(HOST_CONFIG2(host)); + tmp |= SD_CONFIG2_DF; + au_writel(tmp , HOST_CONFIG2(host)); + } + i = 0; + while(i < HOSTCMD_TIMEOUT) { + if (!((au_readl(HOST_STATUS(host))) & SD_STATUS_DB)) { + break; + } + au_sync_udelay(100); + i++; + } + if (i == HOSTCMD_TIMEOUT) { + printk("Clock frozen. DB bit not cleared !!!"); + return -1; + } + } + + if (data) { + // Ensure the block count & block size are both within the range. + if (data->blocks > AU1XXX_MAX_BLKCOUNT || + data->blksz > AU1XXX_MAX_BLKSIZE) { + printk("invalid block size\n"); + return -1; + } + // Set block size and count + blkSizeRegister = SD_BLKSIZE_BC_N(data->blocks); // Macro does -1 for us + blkSizeRegister |= SD_BLKSIZE_BS_N(data->blksz); // Macro does -1 for us + au_writel(blkSizeRegister, HOST_BLKSIZE(host)); + + // enable clock freezing + tmp = au_readl(HOST_CONFIG2(host)); + tmp &= ~SD_CONFIG2_DF; + tmp |= SD_CONFIG2_FF; + au_writel(tmp , HOST_CONFIG2(host)); + } + + // for Stop Transmission and IO Abort disable clock freezing to + // get the state machine running again to send command + + if ((SD_IO_RW_DIRECT == cmd->opcode && (SDIO_CCCR_ABORT == IO_RW_DIRECT_ADDR_ARG(cmd->opcode)))) { + tmp = au_readl(HOST_CONFIG2(host)); + tmp |= SD_CONFIG2_DF; + au_writel(tmp , HOST_CONFIG2(host)); + } + + IRQ_CLEAR(host,SD_STATUS_SC | SD_STATUS_RC | SD_STATUS_WC | + SD_STATUS_RAT | + SD_STATUS_DD ); + + // enable response done and response timeout interrupts + IRQ_ON(host, SD_STATUS_CR | SD_STATUS_RAT); + + + lastCmd53 = (cmd->opcode == SD_IO_RW_EXTENDED); au_writel(cmd->arg, HOST_CMDARG(host)); au_sync(); @@ -296,14 +388,18 @@ au_sync(); /* Wait for the command to go on the line */ - while (au_readl(HOST_CMD(host)) & SD_CMD_GO) - /* nop */; + + while(1) { + if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO)) + break; + } /* Wait for the command to come back */ + if (wait) { u32 status = au_readl(HOST_STATUS(host)); - while (!(status & SD_STATUS_CR)) + while(!(status & SD_STATUS_CR)) status = au_readl(HOST_STATUS(host)); /* Clear the CR status */ @@ -331,9 +427,11 @@ if (status == 0) status = au_readl(HOST_STATUS(host)); +#if 0 /* The transaction is really over when the SD_STATUS_DB bit is clear */ while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) status = au_readl(HOST_STATUS(host)); +#endif data->error = 0; dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); @@ -353,7 +451,7 @@ if (!data->error) { if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **)chan); @@ -424,7 +522,7 @@ } if (host->pio.len == 0) { - IRQ_OFF(host, SD_CONFIG_TH); + IRQ_OFF(host, STATUS_DATA_OUT); if (host->flags & HOST_F_STOP) SEND_STOP(host); @@ -570,21 +668,28 @@ host->status = HOST_S_DATA; if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ u32 channel = DMA_CHANNEL(host); /* Start the DMA as soon as the buffer gets something in it */ if (host->flags & HOST_F_RECV) { - u32 mask = SD_STATUS_DB | SD_STATUS_NE; + u32 mask = SD_STATUS_NE; while((status & mask) != mask) status = au_readl(HOST_STATUS(host)); } au1xxx_dbdma_start(channel); + }else { + if (host->flags & HOST_F_XMIT) { + IRQ_ON(host, SD_STATUS_TE | SD_STATUS_DT); + } + else { + IRQ_ON(host, SD_STATUS_NE | SD_STATUS_DT); + } + } #endif - } } static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) @@ -630,10 +735,10 @@ if (host->dma.len == 0) return -ETIMEDOUT; - au_writel(data->blksz - 1, HOST_BLKSIZE(host)); + //au_writel(data->blksz - 1, HOST_BLKSIZE(host)); if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ int i; u32 channel = DMA_CHANNEL(host); @@ -703,7 +808,7 @@ } if (mrq->data) { - FLUSH_FIFO(host); +// FLUSH_FIFO(host); ret = au1xmmc_prepare_data(host, mrq->data); } @@ -742,7 +847,7 @@ au_sync(); /* Configure interrupts */ - au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); + au_writel(SD_CONFIG_I, HOST_CONFIG(host)); au_sync(); } @@ -754,7 +859,7 @@ if (ios->power_mode == MMC_POWER_OFF) au1xmmc_set_power(host, 0); - else if (ios->power_mode == MMC_POWER_ON) { + else if ((ios->power_mode == MMC_POWER_ON) || (ios->power_mode == MMC_POWER_UP)) { au1xmmc_set_power(host, 1); } @@ -776,9 +881,6 @@ au_sync(); } -#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) -#define STATUS_DATA_IN (SD_STATUS_NE) -#define STATUS_DATA_OUT (SD_STATUS_TH) static irqreturn_t au1xmmc_irq(int irq, void *dev_id) { @@ -816,20 +918,22 @@ } } #endif - else if (status & SD_STATUS_CR) { + if (status & SD_STATUS_CR) { if (host->status == HOST_S_CMD) au1xmmc_cmd_complete(host, status); - } else if (!(host->flags & HOST_F_DMA)) { + } + if (!(host->flags & HOST_F_DMA)&& (host->status == HOST_S_DATA)) { if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) au1xmmc_send_pio(host); else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) au1xmmc_receive_pio(host); + } - } else if (status & 0x203F3C70) { + /*} else if (status & 0x203F3C70) { DBG("Unhandled status %8.8x\n", host->pdev->id, status); - } + }*/ au_writel(status, HOST_STATUS(host)); au_sync(); @@ -837,7 +941,7 @@ return IRQ_HANDLED; } -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* 8bit memory DMA device */ static dbdev_tab_t au1xmmc_mem_dbdev = { .dev_id = DSCR_CMD0_ALWAYS, @@ -943,7 +1047,7 @@ struct au1xmmc_host *host; struct resource *r; int ret; - + static int i = 0; mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); if (!mmc) { dev_err(&pdev->dev, "no memory for mmc_host\n"); @@ -951,6 +1055,8 @@ goto out0; } + printk("Probing for MMC \n"); + host = mmc_priv(mmc); host->mmc = mmc; host->platdata = pdev->dev.platform_data; @@ -962,7 +1068,6 @@ dev_err(&pdev->dev, "no mmio defined\n"); goto out1; } - host->ioarea = request_mem_region(r->start, r->end - r->start + 1, pdev->name); if (!host->ioarea) { @@ -976,6 +1081,15 @@ goto out2; } + au_writel(0, HOST_CONFIG(host)); + au_sync(); + + au_writel(~0, HOST_STATUS(host)); + au_sync(); + + au_writel(0, HOST_ENABLE(host)); + au_sync_delay(1); + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!r) { dev_err(&pdev->dev, "no IRQ defined\n"); @@ -994,16 +1108,20 @@ mmc->ops = &au1xmmc_ops; mmc->f_min = 450000; - mmc->f_max = 24000000; + mmc->f_max = 25000000; + + mmc->max_blk_size = AU1XXX_MAX_BLKSIZE; + mmc->max_blk_count = AU1XXX_MAX_BLKCOUNT; + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; - mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; + mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + mmc->max_hw_segs = AU1XMMC_DESCRIPTOR_COUNT; - mmc->max_blk_size = 2048; - mmc->max_blk_count = 512; mmc->ocr_avail = AU1XMMC_OCR; - mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + printk("Probing for MMC %s\n",mmc_hostname(mmc)); + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; host->status = HOST_S_IDLE; @@ -1023,7 +1141,7 @@ tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, (unsigned long)host); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) ret = au1xmmc_dbdma_init(host); if (ret) printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); @@ -1054,7 +1172,7 @@ printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" " (mode=%s)\n", pdev->id, host->iobase, host->flags & HOST_F_DMA ? "dma" : "pio"); - + i++; return 0; /* all ok */ out6: @@ -1068,7 +1186,7 @@ au_writel(0, HOST_CONFIG2(host)); au_sync(); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xmmc_dbdma_shutdown(host); #endif @@ -1096,6 +1214,7 @@ struct au1xmmc_host *host = platform_get_drvdata(pdev); if (host) { + cancel_delayed_work(&host->mmc->detect); mmc_remove_host(host->mmc); #ifdef CONFIG_LEDS_CLASS @@ -1115,7 +1234,7 @@ tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xmmc_dbdma_shutdown(host); #endif au1xmmc_set_power(host, 0); @@ -1140,6 +1259,7 @@ ret = mmc_suspend_host(host->mmc, state); if (ret) return ret; + cancel_delayed_work(&host->mmc->detect); au_writel(0, HOST_CONFIG2(host)); au_writel(0, HOST_CONFIG(host)); @@ -1173,10 +1293,9 @@ .owner = THIS_MODULE, }, }; - static int __init au1xmmc_init(void) { -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride * of 8 bits. And since devices are shared, we need to create * our own to avoid freaking out other devices. @@ -1190,7 +1309,7 @@ static void __exit au1xmmc_exit(void) { -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) if (memid) au1xxx_ddma_del_device(memid); #endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/mmc/host/au1xmmc.h linux-2.6.29/drivers/mmc/host/au1xmmc.h --- linux-2.6.29/drivers/mmc/host/au1xmmc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/mmc/host/au1xmmc.h 2009-06-04 13:45:43.000000000 -0400 @@ -0,0 +1,148 @@ +#ifndef _AU1XMMC_H_ +#define _AU1XMMC_H_ + +/* Hardware definitions */ + +#define AU1XXX_MAX_BLKCOUNT 512 +#define AU1XXX_MAX_BLKSIZE 2048 + +#define AU1XMMC_DESCRIPTOR_COUNT 1 + +#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) + +/* Easy access macros */ + +#define HOST_STATUS(h) ((h)->iobase + SD_STATUS) +#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) +#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) +#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) +#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) +#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) +#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) +#define HOST_CMD(h) ((h)->iobase + SD_CMD) +#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) +#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) +#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) + +#define DMA_CHANNEL(h) \ + ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) + +/* This gives us a hard value for the stop command that we can write directly + * to the command register + */ + +#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO) + +/* This is the set of interrupts that we configure by default */ + +#if 0 +#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \ + SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) +#endif + +#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \ + SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) + +#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) +#define STATUS_DATA_IN (SD_STATUS_NE) +#define STATUS_DATA_OUT (SD_STATUS_TH | SD_CONFIG_TE) + + +// These are the Level Triggered sources. +// // The corresponding status bit is cleared when triggering condition is cleared. + +#define SD_INT_LT_MASK (SD_CONFIG_SI | \ + SD_CONFIG_RF | \ + SD_CONFIG_RA | \ + SD_CONFIG_RH | \ + SD_CONFIG_TA | \ + SD_CONFIG_TE | \ + SD_CONFIG_TH | \ + SD_CONFIG_I | \ + SD_CONFIG_NE) + +// These are the Edge Triggered sources. +// // Write '1' to clear the corresponding status bit. + +#define SD_INT_ET_MASK (SD_CONFIG_CD | \ + SD_CONFIG_WC | \ + SD_CONFIG_RC | \ + SD_CONFIG_SC | \ + SD_CONFIG_DT | \ + SD_CONFIG_DD | \ + SD_CONFIG_RAT| \ + SD_CONFIG_CR | \ + SD_CONFIG_RO | \ + SD_CONFIG_RU | \ + SD_CONFIG_TO | \ + SD_CONFIG_TU) + + +/* The poll event (looking for insert/remove events runs twice a second */ +#define AU1XMMC_DETECT_TIMEOUT (HZ/2) + + +/* Status flags used by the host structure */ + +#define HOST_F_XMIT 0x0001 +#define HOST_F_RECV 0x0002 +#define HOST_F_DMA 0x0010 +#define HOST_F_ACTIVE 0x0100 +#define HOST_F_STOP 0x1000 + +#define HOST_S_IDLE 0x0001 +#define HOST_S_CMD 0x0002 +#define HOST_S_DATA 0x0003 +#define HOST_S_STOP 0x0004 + +#define SD_CMD_CT_8 8 + + // macros to decode IO RW arguments +#define IO_RW_DIRECT_ADDR_ARG(Arg) (((Arg)>>9)&0x1FFFF) +#define IO_RW_EXTENDED_BLOCK_MODE(Arg) (((Arg)>>27)&1) +#define IO_RW_EXTENDED_COUNT(Arg) ((Arg)&0x1FF) + +#define SD_BLKSIZE_BC_N(N) ((N-1)<<16) +#define SD_BLKSIZE_BS_N(N) ((N-1)<<0) + + +#define HOSTCMD_TIMEOUT 10000 + +struct au1xmmc_host { + struct mmc_host *mmc; + struct mmc_request *mrq; + + u32 flags; + u32 iobase; + u32 clock; + u32 bus_width; + u32 power_mode; + + int status; + + struct { + int len; + int dir; + } dma; + + struct { + int index; + int offset; + int len; + } pio; + + u32 tx_chan; + u32 rx_chan; + + int irq; + + struct tasklet_struct finish_task; + struct tasklet_struct data_task; + struct au1xmmc_platform_data *platdata; + struct platform_device *pdev; + struct resource *ioarea; + spinlock_t lock; +}; +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/mmc/host/Kconfig linux-2.6.29/drivers/mmc/host/Kconfig --- linux-2.6.29/drivers/mmc/host/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/mmc/host/Kconfig 2009-06-01 16:13:46.000000000 -0400 @@ -99,7 +99,7 @@ config MMC_AU1X tristate "Alchemy AU1XX0 MMC Card Interface support" - depends on SOC_AU1200 + depends on SOC_AU1200 || SOC_AU13XX help This selects the AMD Alchemy(R) Multimedia card interface. If you have a Alchemy platform with a MMC slot, say Y or M here. diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/mtd/nand/au1550nd.c linux-2.6.29/drivers/mtd/nand/au1550nd.c --- linux-2.6.29/drivers/mtd/nand/au1550nd.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/mtd/nand/au1550nd.c 2009-07-15 10:25:21.000000000 -0400 @@ -1,8 +1,10 @@ -/* - * drivers/mtd/nand/au1550nd.c - * + /* * Copyright (C) 2004 Embedded Edge, LLC * + * 2009-03-11 David specified for K9K8G08 (HMP10 project) + * + * $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $ + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -13,9 +15,10 @@ #include #include #include -#include +#include #include #include +#include #include #include @@ -32,14 +35,19 @@ * Define partitions for flash device */ static const struct mtd_partition partition_info[] = { +#if 0 { - .name = "NAND FS 0", - .offset = 0, - .size = 8 * 1024 * 1024}, + .name = "NAND BOOT", + .offset = 0, + .size = 64 *128*1024 + }, +#endif { - .name = "NAND FS 1", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL} + .name = "NAND FS", + .offset = 0x800000, + // UPTO (512 -1 )MB. The last 1 MB is reserved for YAMON + .size = (0x1f800000 - 0x100000) + }, }; /** @@ -66,6 +74,8 @@ static void au_write_byte(struct mtd_info *mtd, u_char byte) { struct nand_chip *this = mtd->priv; + + writeb(byte, this->IO_ADDR_W); au_sync(); } @@ -241,68 +251,6 @@ return 0; } -/* Select the chip by setting nCE to low */ -#define NAND_CTL_SETNCE 1 -/* Deselect the chip by setting nCE to high */ -#define NAND_CTL_CLRNCE 2 -/* Select the command latch by setting CLE to high */ -#define NAND_CTL_SETCLE 3 -/* Deselect the command latch by setting CLE to low */ -#define NAND_CTL_CLRCLE 4 -/* Select the address latch by setting ALE to high */ -#define NAND_CTL_SETALE 5 -/* Deselect the address latch by setting ALE to low */ -#define NAND_CTL_CLRALE 6 - -static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) -{ - register struct nand_chip *this = mtd->priv; - - switch (cmd) { - - case NAND_CTL_SETCLE: - this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; - break; - - case NAND_CTL_CLRCLE: - this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; - break; - - case NAND_CTL_SETALE: - this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; - break; - - case NAND_CTL_CLRALE: - this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; - /* FIXME: Nobody knows why this is necessary, - * but it works only that way */ - udelay(1); - break; - - case NAND_CTL_SETNCE: - /* assert (force assert) chip enable */ - au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); - break; - - case NAND_CTL_CLRNCE: - /* deassert chip enable */ - au_writel(0, MEM_STNDCTL); - break; - } - - this->IO_ADDR_R = this->IO_ADDR_W; - - /* Drain the writebuffer */ - au_sync(); -} - -int au1550_device_ready(struct mtd_info *mtd) -{ - int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; - au_sync(); - return ret; -} - /** * au1550_select_chip - control -CE line * Forbid driving -CE manually permitting the NAND controller to do this. @@ -319,125 +267,49 @@ { } -/** - * au1550_command - Send command to NAND device - * @mtd: MTD device structure - * @command: the command to be sent - * @column: the column address for this command, -1 if none - * @page_addr: the page address for this command, -1 if none - */ -static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) -{ - register struct nand_chip *this = mtd->priv; - int ce_override = 0, i; - ulong flags; - - /* Begin command latch cycle */ - au1550_hwcontrol(mtd, NAND_CTL_SETCLE); - /* - * Write out the command to the device. - */ - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->writesize) { - /* OOB area */ - column -= mtd->writesize; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - au1550_write_byte(mtd, readcmd); - } - au1550_write_byte(mtd, command); - - /* Set ALE and clear CLE to start address cycle */ - au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); - - if (column != -1 || page_addr != -1) { - au1550_hwcontrol(mtd, NAND_CTL_SETALE); - - /* Serially input address */ - if (column != -1) { - /* Adjust columns for 16 bit buswidth */ - if (this->options & NAND_BUSWIDTH_16) - column >>= 1; - au1550_write_byte(mtd, column); - } - if (page_addr != -1) { - au1550_write_byte(mtd, (u8)(page_addr & 0xff)); - - if (command == NAND_CMD_READ0 || - command == NAND_CMD_READ1 || - command == NAND_CMD_READOOB) { - /* - * NAND controller will release -CE after - * the last address byte is written, so we'll - * have to forcibly assert it. No interrupts - * are allowed while we do this as we don't - * want the NOR flash or PCMCIA drivers to - * steal our precious bytes of data... - */ - ce_override = 1; - local_irq_save(flags); - au1550_hwcontrol(mtd, NAND_CTL_SETNCE); - } - - au1550_write_byte(mtd, (u8)(page_addr >> 8)); - - /* One more address cycle for devices > 32MiB */ - if (this->chipsize > (32 << 20)) - au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); - } - /* Latch in address */ - au1550_hwcontrol(mtd, NAND_CTL_CLRALE); - } - - /* - * Program and erase have their own busy handlers. - * Status and sequential in need no delay. - */ - switch (command) { - - case NAND_CMD_PAGEPROG: - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - case NAND_CMD_SEQIN: - case NAND_CMD_STATUS: - return; - - case NAND_CMD_RESET: - break; - - case NAND_CMD_READ0: - case NAND_CMD_READ1: - case NAND_CMD_READOOB: - /* Check if we're really driving -CE low (just in case) */ - if (unlikely(!ce_override)) - break; - - /* Apply a short delay always to ensure that we do wait tWB. */ - ndelay(100); - /* Wait for a chip to become ready... */ - for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) - udelay(1); - - /* Release -CE and re-enable interrupts. */ - au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); - local_irq_restore(flags); - return; - } - /* Apply this short delay always to ensure that we do wait tWB. */ - ndelay(100); +static void au1550_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + register struct nand_chip *this = mtd->priv; + if (ctrl & NAND_CTRL_CHANGE) { - while(!this->dev_ready(mtd)); + if(ctrl&NAND_NCE) + { + this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; + } + + if((ctrl&(NAND_ALE|NAND_CLE|NAND_NCE))==0) + { + this->IO_ADDR_W = p_nand+MEM_STNAND_DATA; + } + + if(ctrl&NAND_CLE) + { + this->IO_ADDR_W = p_nand+MEM_STNAND_CMD; + goto exit; + } + + if(ctrl&NAND_ALE) + { + this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; + goto exit; + } + + } +exit: + + this->IO_ADDR_R = this->IO_ADDR_W; + if (cmd != NAND_CMD_NONE) { + au1550_write_byte(mtd,cmd); + au_sync(); + } } - +int au1550_device_ready(struct mtd_info *mtd) +{ + int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; + au_sync(); + return ret; +} /* * Main initialization routine */ @@ -467,7 +339,6 @@ au1550_mtd->priv = this; au1550_mtd->owner = THIS_MODULE; - /* MEM_STNDCTL: disable ints, disable nand boot */ au_writel(0, MEM_STNDCTL); @@ -556,8 +427,8 @@ /* Set address of hardware control function */ this->dev_ready = au1550_device_ready; - this->select_chip = au1550_select_chip; - this->cmdfunc = au1550_command; + this->cmd_ctrl = au1550_hwcontrol; + this->select_chip = au1550_select_chip; /* 30 us command delay time */ this->chip_delay = 30; @@ -601,6 +472,8 @@ */ static void __exit au1550_cleanup(void) { + struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1]; + /* Release resources, unregister device */ nand_release(au1550_mtd); diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/Kconfig linux-2.6.29/drivers/net/Kconfig --- linux-2.6.29/drivers/net/Kconfig 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/net/Kconfig 2009-07-08 21:12:49.000000000 -0400 @@ -981,7 +981,7 @@ config SMSC911X tristate "SMSC LAN911x/LAN921x families embedded ethernet support" - depends on ARM || SUPERH + depends on ARM || SUPERH || SOC_AU13XX || MIPS_HMP10 select CRC32 select MII select PHYLIB @@ -993,6 +993,12 @@ . The module will be called smsc911x. +config SMSC9210 + tristate "SMSC 9210 support (DEPRECATED)" + depends on SOC_AU1X00 + help + TODO + config NET_VENDOR_RACAL bool "Racal-Interlan (Micom) NI cards" depends on ISA @@ -2321,6 +2327,13 @@ Some boards that use the Discovery chipset are the Momenco Ocelot C and Jaguar ATX and Pegasos II. +config TITAN_GE + bool "PMC-Sierra TITAN Gigabit Ethernet Support" + depends on PMC_YOSEMITE + help + This enables support for the the integrated ethernet of + PMC-Sierra's Titan SoC. + config QLA3XXX tristate "QLogic QLA3XXX Network Driver Support" depends on PCI diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/Makefile linux-2.6.29/drivers/net/Makefile --- linux-2.6.29/drivers/net/Makefile 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/net/Makefile 2009-05-29 12:24:25.000000000 -0400 @@ -59,6 +59,7 @@ obj-$(CONFIG_TLAN) += tlan.o obj-$(CONFIG_EPIC100) += epic100.o obj-$(CONFIG_SMSC9420) += smsc9420.o +obj-$(CONFIG_SMSC9210) += smsc9210/ obj-$(CONFIG_SIS190) += sis190.o obj-$(CONFIG_SIS900) += sis900.o obj-$(CONFIG_R6040) += r6040.o @@ -135,6 +136,8 @@ obj-$(CONFIG_QLA3XXX) += qla3xxx.o obj-$(CONFIG_QLGE) += qlge/ +obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o + obj-$(CONFIG_PPP) += ppp_generic.o obj-$(CONFIG_PPP_ASYNC) += ppp_async.o obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc911x.c linux-2.6.29/drivers/net/smsc911x.c --- linux-2.6.29/drivers/net/smsc911x.c 2009-03-23 19:12:14.000000000 -0400 +++ linux-2.6.29/drivers/net/smsc911x.c 2009-09-02 10:21:37.000000000 -0400 @@ -1890,6 +1890,9 @@ return 0; } +#if (defined(CONFIG_MIPS_HMP10) || defined(CONFIG_MIPS_HMP5) || defined(CONFIG_MIPS_DB1300)) +extern int prom_get_ethernet_addr(char *ethernet_addr); +#endif static int __devinit smsc911x_drv_probe(struct platform_device *pdev) { @@ -2001,6 +2004,11 @@ } spin_lock_irq(&pdata->mac_lock); +#if (defined(CONFIG_MIPS_HMP10) || defined(CONFIG_MIPS_HMP5) || defined(CONFIG_MIPS_DB1300)) + prom_get_ethernet_addr(dev->dev_addr); + printk("Got ethernet addr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X from prom\n", + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5] ); +#endif /* Check if mac address has been specified when bringing interface up */ if (is_valid_ether_addr(dev->dev_addr)) { diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/ioctl_118.h linux-2.6.29/drivers/net/smsc9210/ioctl_118.h --- linux-2.6.29/drivers/net/smsc9210/ioctl_118.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/ioctl_118.h 2009-05-29 12:24:25.000000000 -0400 @@ -0,0 +1,298 @@ +/*************************************************************************** + + * + + * Copyright (C) 2004-2005 SMSC + + * + + * This program is free software; you can redistribute it and/or + + * modify it under the terms of the GNU General Public License + + * as published by the Free Software Foundation; either version 2 + + * of the License, or (at your option) any later version. + + * + + * This program is distributed in the hope that it will be useful, + + * but WITHOUT ANY WARRANTY; without even the implied warranty of + + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + * GNU General Public License for more details. + + * + + * You should have received a copy of the GNU General Public License + + * along with this program; if not, write to the Free Software + + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + * + + *************************************************************************** + + * File: ioctl_118.h + + */ + + + +#ifndef IOCTL_118_H + +#define IOCTL_118_H + + + +#define DRIVER_VERSION (0x00000155UL) + + + +#define SMSC9118_DRIVER_SIGNATURE (0x82745BACUL+DRIVER_VERSION) + +#define SMSC9118_APP_SIGNATURE (0x987BEF28UL+DRIVER_VERSION) + + + +#define SMSC9118_IOCTL (SIOCDEVPRIVATE + 0xB) + + + +#define COMMAND_BASE (0x974FB832UL) + + + +#define COMMAND_GET_SIGNATURE (COMMAND_BASE+0) + + + +#define COMMAND_LAN_GET_REG (COMMAND_BASE+1) + +#define COMMAND_LAN_SET_REG (COMMAND_BASE+2) + + + +#define COMMAND_MAC_GET_REG (COMMAND_BASE+3) + +#define COMMAND_MAC_SET_REG (COMMAND_BASE+4) + + + +#define COMMAND_PHY_GET_REG (COMMAND_BASE+5) + +#define COMMAND_PHY_SET_REG (COMMAND_BASE+6) + + + +#define COMMAND_DUMP_LAN_REGS (COMMAND_BASE+7) + +#define LAN_REG_ID_REV (0) + +#define LAN_REG_INT_CFG (1) + +#define LAN_REG_INT_STS (2) + +#define LAN_REG_INT_EN (3) + +#define LAN_REG_BYTE_TEST (4) + +#define LAN_REG_FIFO_INT (5) + +#define LAN_REG_RX_CFG (6) + +#define LAN_REG_TX_CFG (7) + +#define LAN_REG_HW_CFG (8) + +#define LAN_REG_RX_DP_CTRL (9) + +#define LAN_REG_RX_FIFO_INF (10) + +#define LAN_REG_TX_FIFO_INF (11) + +#define LAN_REG_PMT_CTRL (12) + +#define LAN_REG_GPIO_CFG (13) + +#define LAN_REG_GPT_CFG (14) + +#define LAN_REG_GPT_CNT (15) + +#define LAN_REG_FPGA_REV (16) + +#define LAN_REG_WORD_SWAP (17) + +#define LAN_REG_FREE_RUN (18) + +#define LAN_REG_RX_DROP (19) + +#define LAN_REG_MAC_CSR_CMD (21) + +#define LAN_REG_MAC_CSR_DATA (22) + +#define LAN_REG_AFC_CFG (23) + +#define LAN_REG_E2P_CMD (24) + +#define LAN_REG_E2P_DATA (25) + + + +#define COMMAND_DUMP_MAC_REGS (COMMAND_BASE+8) + +#define MAC_REG_MAC_CR (0) + +#define MAC_REG_ADDRH (1) + +#define MAC_REG_ADDRL (2) + +#define MAC_REG_HASHH (3) + +#define MAC_REG_HASHL (4) + +#define MAC_REG_MII_ACC (5) + +#define MAC_REG_MII_DATA (6) + +#define MAC_REG_FLOW (7) + +#define MAC_REG_VLAN1 (8) + +#define MAC_REG_VLAN2 (9) + +#define MAC_REG_WUFF (10) + +#define MAC_REG_WUCSR (11) + + + +#define COMMAND_DUMP_PHY_REGS (COMMAND_BASE+9) + +#define PHY_REG_0 (0) + +#define PHY_REG_1 (1) + +#define PHY_REG_2 (2) + +#define PHY_REG_3 (3) + +#define PHY_REG_4 (4) + +#define PHY_REG_5 (5) + +#define PHY_REG_6 (6) + +#define PHY_REG_16 (7) + +#define PHY_REG_17 (8) + +#define PHY_REG_18 (9) + +#define PHY_REG_20 (10) + +#define PHY_REG_21 (11) + +#define PHY_REG_22 (12) + +#define PHY_REG_23 (13) + +#define PHY_REG_27 (14) + +#define PHY_REG_28 (15) + +#define PHY_REG_29 (16) + +#define PHY_REG_30 (17) + +#define PHY_REG_31 (18) + + + +#define COMMAND_DUMP_EEPROM (COMMAND_BASE+10) + + + +#define COMMAND_GET_MAC_ADDRESS (COMMAND_BASE+11) + +#define COMMAND_SET_MAC_ADDRESS (COMMAND_BASE+12) + +#define COMMAND_LOAD_MAC_ADDRESS (COMMAND_BASE+13) + +#define COMMAND_SAVE_MAC_ADDRESS (COMMAND_BASE+14) + +#define COMMAND_SET_DEBUG_MODE (COMMAND_BASE+15) + + + +#define COMMAND_SET_POWER_MODE (COMMAND_BASE+16) + +#define COMMAND_GET_POWER_MODE (COMMAND_BASE+17) + + + +#define COMMAND_SET_LINK_MODE (COMMAND_BASE+18) + +#define COMMAND_GET_LINK_MODE (COMMAND_BASE+19) + +#define COMMAND_GET_CONFIGURATION (COMMAND_BASE+20) + +#define COMMAND_DUMP_TEMP (COMMAND_BASE+21) + +#define COMMAND_READ_BYTE (COMMAND_BASE+22) + +#define COMMAND_READ_WORD (COMMAND_BASE+23) + +#define COMMAND_READ_DWORD (COMMAND_BASE+24) + +#define COMMAND_WRITE_BYTE (COMMAND_BASE+25) + +#define COMMAND_WRITE_WORD (COMMAND_BASE+26) + +#define COMMAND_WRITE_DWORD (COMMAND_BASE+27) + +#define COMMAND_CHECK_LINK (COMMAND_BASE+28) + + + +//the following codes are intended for cmd9118 only + +// they are not intended to have any use in the driver + +#define COMMAND_RUN_SERVER (COMMAND_BASE+29) + +#define COMMAND_RUN_TUNER (COMMAND_BASE+30) + + + +#define COMMAND_GET_FLOW_PARAMS (COMMAND_BASE+31) + +#define COMMAND_SET_FLOW_PARAMS (COMMAND_BASE+32) + +#define COMMAND_SET_AMDIX_STS (COMMAND_BASE+33) + +#define COMMAND_GET_AMDIX_STS (COMMAND_BASE+34) + +typedef struct _SMSC9118_IOCTL_DATA { + + unsigned long dwSignature; + + unsigned long dwCommand; + + unsigned long Data[0x60]; + + char Strng1[30]; + + char Strng2[10]; + +} SMSC9118_IOCTL_DATA, *PSMSC9118_IOCTL_DATA; + + + +#endif + + + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/Makefile linux-2.6.29/drivers/net/smsc9210/Makefile --- linux-2.6.29/drivers/net/smsc9210/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/Makefile 2009-05-29 12:24:25.000000000 -0400 @@ -0,0 +1,9 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey +# + +obj-$(CONFIG_SMSC9210) += smsc9210.o + +smsc9210-objs := smsc9210_main.o platform_alchemy.o + diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/platform_alchemy.c linux-2.6.29/drivers/net/smsc9210/platform_alchemy.c --- linux-2.6.29/drivers/net/smsc9210/platform_alchemy.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/platform_alchemy.c 2009-09-03 17:27:50.000000000 -0400 @@ -0,0 +1,89 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include "platform_alchemy.h" + +u32 Platform_Initialize(PPLATFORM_DATA pd, u32 lan_base, u32 bus_width) +{ + return BASE_ADDRESS; +} + + +/* + * Ignores the passed in irq in favor of the one we know to be correct... + */ +bool Platform_RequestIRQ(PPLATFORM_DATA pd, + u32 irq, + irqreturn_t (*pIsr)(int irq,void *dev_id), + void* dev_id ) +{ + int retval = request_irq(PLATFORM_IRQ, pIsr, 0, "SMSC 9210 Ethernet", dev_id); + pd->irq_dev_id = dev_id; + + return retval == 0 ? true : false; +} + +void Platform_FreeIRQ(PPLATFORM_DATA pd) +{ + free_irq(PLATFORM_IRQ, pd->irq_dev_id); +} + +void Platform_WriteFifo(u32 lan_base, u32 *buf, u32 count) +{ + int i; + for(i = 0; i < count; ++i) + { + au_writel(*buf, (u32*)(lan_base+0x20)); + au_sync(); + ++buf; + } +} + +void Platform_ReadFifo(u32 lan_base, u32 *buf, u32 count) +{ + int i; + for(i = 0; i < count; ++i) + { + *buf = au_readl((u32*)lan_base); + ++buf; + } + +} + +void Platform_GetFlowControlParameters(PPLATFORM_DATA pd, PFLOW_CONTROL_PARAMETERS fcp, bool useDma) +{ + /* + * Borrowed from xscale_linux.c in the 16-bit PIO 8210 section + */ + memset(fcp,0,sizeof(FLOW_CONTROL_PARAMETERS)); + fcp->BurstPeriod=100; + fcp->IntDeas=0; + fcp->MaxThroughput=0x74378UL; + fcp->MaxPacketCount=0x13AUL; + fcp->PacketCost=0x02UL; + fcp->BurstPeriod=0x76UL; + fcp->IntDeas=0x18UL; +} diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/platform_alchemy.h linux-2.6.29/drivers/net/smsc9210/platform_alchemy.h --- linux-2.6.29/drivers/net/smsc9210/platform_alchemy.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/platform_alchemy.h 2009-06-24 14:14:51.000000000 -0400 @@ -0,0 +1,120 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef PLATFORM_ALCHEMY_H +#define PLATFORM_ALCHEMY_H + +#include +#include + +#if defined(CONFIG_MIPS_DB1200) +#include +#define PLATFORM_IRQ DB1200_DC_INT +#elif defined(CONFIG_MIPS_HMP10) +#include +#define PLATFORM_IRQ HMP10_ETH_IRQ +#elif defined(CONFIG_MIPS_HMP5) +#include +#define PLATFORM_IRQ HMP5_ETH_IRQ +#elif defined(CONFIG_MIPS_DB1300) +#include +#define PLATFORM_IRQ DB1300_ETHERNET_IRQ +#endif + +#include "smsc9210.h" +/* + * Make the IRQ a push-pull; on DB1300 there is no pull up so open-drain will + * always be low. + */ +#define PLATFORM_IRQ_POL 0 +#define PLATFORM_IRQ_TYPE 1 +#define PLATFORM_CACHE_LINE_BYTES 0 +#define PLATFORM_RX_DMA TRANSFER_PIO +#define PLATFORM_TX_DMA TRANSFER_PIO +#define PLATFORM_DMA_THRESHOLD 0 +#define PLATFORM_NAME "Alchemy" + +#ifdef CONFIG_MIPS_DB1200 +#define BASE_ADDRESS 0xBA000000 +#else +#define BASE_ADDRESS 0xB9000000 +#endif + +typedef struct { + void *irq_dev_id; +} PLATFORM_DATA, *PPLATFORM_DATA; + +u32 Platform_Initialize(PPLATFORM_DATA pd, u32 lan_base, u32 bus_width); + +static void Platform_CleanUp(PPLATFORM_DATA pd) { } +static u32 Platform_CurrentIRQ(PPLATFORM_DATA pd) +{ + return PLATFORM_IRQ; +} + +static inline void Platform_SetRegDW(u32 lan_base, u32 offset, u32 val) +{ + au_writel(val, (lan_base + offset)); +} + +static inline u32 Platform_GetRegDW(u32 lan_base, u32 offset) +{ + return au_readl(lan_base + offset); +} + +bool Platform_RequestIRQ(PPLATFORM_DATA pd, + u32 irq, + irqreturn_t (*pIsr)(int irq, void *dev_id), + void* dev_id ); + +void Platform_FreeIRQ(PPLATFORM_DATA pd); +void Platform_GetFlowControlParameters(PPLATFORM_DATA pd, PFLOW_CONTROL_PARAMETERS fcp, bool useDma); +void Platform_WriteFifo(u32 lan_base, u32 *buf, u32 count); +void Platform_ReadFifo(u32 lan_base, u32 *buf, u32 count); + +/* * We're not supporting DMA at this time, so degenerate all functions to return + * errors. + */ +static inline bool Platform_IsValidDmaChannel(u32 chan) { return false; } +static inline bool Platform_DmaInitialize(PPLATFORM_DATA pd, u32 chan) { return false; } +static inline bool Platform_DmaDisable(PPLATFORM_DATA pd, u32 chan) { return false; } +static inline void Platform_CacheInvalidate(PPLATFORM_DATA pd, const void *const sa, + const u32 len) { } +static inline void Platform_CachePurge(PPLATFORM_DATA pd, const void *const sa, + const u32 len) { } +static inline u32 Platform_RequestDmaChannel(PPLATFORM_DATA pd) { return TRANSFER_PIO; } +static inline void Platform_ReleaseDmaChannel(PPLATFORM_DATA pd, u32 chan) { } +static inline bool Platform_DmaStartXfer(PPLATFORM_DATA pd, const DMA_XFER * const pDmaXfer) +{ + return false; +} +static inline u32 Platform_DmaGetDwCnt(PPLATFORM_DATA platformData, const u32 dwDmaCh) +{ + return 0; +} +static inline void Platform_DmaComplete(PPLATFORM_DATA platformData, const u32 dwDmaCh) { } + + +#endif /* PLATFORM_ALCHEMY_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/smsc9210.h linux-2.6.29/drivers/net/smsc9210/smsc9210.h --- linux-2.6.29/drivers/net/smsc9210/smsc9210.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/smsc9210.h 2009-05-29 12:24:25.000000000 -0400 @@ -0,0 +1,23 @@ +#ifndef SMSC9210_H +#define SMSC9210_H + +#define TRANSFER_PIO (256UL) + +typedef struct _DMA_XFER +{ + u32 dwLanReg; + u32 *pdwBuf; + u32 dwDmaCh; + u32 dwDwCnt; + bool fMemWr; +} DMA_XFER; + +typedef struct _FLOW_CONTROL_PARAMETERS +{ + u32 MaxThroughput; + u32 MaxPacketCount; + u32 PacketCost; + u32 BurstPeriod; + u32 IntDeas; +} FLOW_CONTROL_PARAMETERS, *PFLOW_CONTROL_PARAMETERS; +#endif /* SMSC9210_H */ diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/smsc9210/smsc9210_main.c linux-2.6.29/drivers/net/smsc9210/smsc9210_main.c --- linux-2.6.29/drivers/net/smsc9210/smsc9210_main.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/smsc9210/smsc9210_main.c 2009-06-24 15:05:21.000000000 -0400 @@ -0,0 +1,7201 @@ +/*************************************************************************** + * + * Copyright (C) 2004-2005 SMSC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + *************************************************************************** + * File: smsc9118.c + * see readme.txt for programmers guide + */ + + +//#define UseScatterGather +//#define UseTxCsum +//#define UseRxCsum + +#define USE_DEBUG + +#ifndef __KERNEL__ +# define __KERNEL__ +#endif + +#ifdef USING_LINT +#include "lint.h" +#else //not USING_LINT +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "smsc9210.h" + +#endif //not USING_LINT + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +typedef void irqreturn_t; +#define IRQ_NONE +#define IRQ_HANDLED +#define IRQ_RETVAL(x) +#else +#define LINUX_2_6_OR_NEWER +#endif + +#ifdef USE_DEBUG +static u32 debug_mode=0x7UL; +#else +static u32 debug_mode=0x0UL; +#endif + +#ifdef USE_DEBUG +//select debug modes +#define USE_WARNING +#define USE_TRACE +#define USE_ASSERT +#endif //USE_DEBUG + +#define USE_LED1_WORK_AROUND // 10/100 LED link-state inversion +#define USE_PHY_WORK_AROUND // output polarity inversion + +typedef long TIME_SPAN; +#define MAX_TIME_SPAN ((TIME_SPAN)(0x7FFFFFFFUL)) +typedef unsigned short WORD; +typedef unsigned char BYTE; +//typedef unsigned char bool; +#define true ((bool)1) +#define false ((bool)0) + +//unsigned char testbuff[1600]={0}; +//u32 * p= NULL; + + +#define HIBYTE(word) ((BYTE)(((WORD)(word))>>8)) +#define LOBYTE(word) ((BYTE)(((WORD)(word))&0x00FFU)) +#define HIWORD(dWord) ((WORD)(((u32)(dWord))>>16)) +#define LOWORD(dWord) ((WORD)(((u32)(dWord))&0x0000FFFFUL)) + +#define TRANSFER_PIO (256UL) +#define TRANSFER_REQUEST_DMA (255UL) +//these are values that can be assigned to +//PLATFORM_RX_DMA +//PLATFORM_TX_DMA +// in addition to any specific dma channel + +/******************************************************* + * Macro: SMSC_TRACE + * Description: + * This macro is used like printf. + * It can be used anywhere you want to display information + * For any release version it should not be left in + * performance sensitive Tx and Rx code paths. + * To use this macro define USE_TRACE and set bit 0 of debug_mode + *******************************************************/ +#ifdef USING_LINT +extern void SMSC_TRACE(const char * a, ...); +#else //not USING_LINT +#ifdef USE_TRACE +#ifndef USE_WARNING +#define USE_WARNING +#endif +# define SMSC_TRACE(msg,args...) \ + if(debug_mode&0x01UL) { \ + printk("SMSC: " msg "\n", ## args); \ + } +#else +# define SMSC_TRACE(msg,args...) +#endif +#endif //not USING_LINT + +/******************************************************* + * Macro: SMSC_WARNING + * Description: + * This macro is used like printf. + * It can be used anywhere you want to display warning information + * For any release version it should not be left in + * performance sensitive Tx and Rx code paths. + * To use this macro define USE_TRACE or + * USE_WARNING and set bit 1 of debug_mode + *******************************************************/ + + +#ifdef USING_LINT +extern void SMSC_WARNING(const char * a, ...); +#else //not USING_LINT +#ifdef USE_WARNING +#ifndef USE_ASSERT +#define USE_ASSERT +#endif +# define SMSC_WARNING(msg, args...) \ + if(debug_mode&0x02UL) { \ + printk("SMSC_WARNING: " msg "\n",## args); \ + } +#else +# define SMSC_WARNING(msg, args...) +#endif +#endif //not USING_LINT + + +/******************************************************* + * Macro: SMSC_ASSERT + * Description: + * This macro is used to test assumptions made when coding. + * It can be used anywhere, but is intended only for situations + * where a failure is fatal. + * If code execution where allowed to continue it is assumed that + * only further unrecoverable errors would occur and so this macro + * includes an infinite loop to prevent further corruption. + * Assertions are only intended for use during developement to + * insure consistency of logic through out the driver. + * A driver should not be released if assertion failures are + * still occuring. + * To use this macro define USE_TRACE or USE_WARNING or + * USE_ASSERT + *******************************************************/ +#ifdef USING_LINT +extern void SMSC_ASSERT(bool condition); +#else //not USING_LINT +#ifdef USE_ASSERT +# define SMSC_ASSERT(condition) \ + if(!(condition)) { \ + printk("SMSC_ASSERTION_FAILURE: File=" __FILE__ ", Line=%d\n",__LINE__); \ + while(1); \ + } +#else +# define SMSC_ASSERT(condition) +#endif +#endif //not USING_LINT + +//Below are the register offsets and bit definitions +// of the Lan9118 memory space +#define RX_DATA_FIFO (0x00UL) +#define TX_DATA_FIFO (0x20UL) +#define TX_CMD_A_INT_ON_COMP_ (0x80000000UL) +#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000UL) +#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000UL) +#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000UL) +#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000UL) +#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000UL) +#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000UL) +#define TX_CMD_A_INT_LAST_SEG_ (0x00001000UL) +#define TX_CMD_A_BUF_SIZE_ (0x000007FFUL) +#define TX_CMD_B_PKT_TAG_ (0xFFFF0000UL) +#define TX_CMD_B_CSUM_ENABLE (0x00004000UL) +#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000UL) +#define TX_CMD_B_DISABLE_PADDING_ (0x00001000UL) +#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FFUL) + +#define RX_STATUS_FIFO (0x40UL) +#define RX_STS_ES_ (0x00008000UL) +#define RX_STS_MCAST_ (0x00000400UL) +#define RX_STATUS_FIFO_PEEK (0x44UL) +#define TX_STATUS_FIFO (0x48UL) +#define TX_STATUS_FIFO_PEEK (0x4CUL) +#define ID_REV (0x50UL) +#define ID_REV_CHIP_ID_ (0xFFFF0000UL) // RO +#define ID_REV_REV_ID_ (0x0000FFFFUL) // RO + +#define INT_CFG (0x54UL) +#define INT_CFG_INT_DEAS_ (0xFF000000UL) // R/W +#define INT_CFG_IRQ_INT_ (0x00001000UL) // RO +#define INT_CFG_IRQ_EN_ (0x00000100UL) // R/W +#define INT_CFG_IRQ_POL_ (0x00000010UL) // R/W Not Affected by SW Reset +#define INT_CFG_IRQ_TYPE_ (0x00000001UL) // R/W Not Affected by SW Reset + +#define INT_STS (0x58UL) +#define INT_STS_SW_INT_ (0x80000000UL) // R/WC +#define INT_STS_TXSTOP_INT_ (0x02000000UL) // R/WC +#define INT_STS_RXSTOP_INT_ (0x01000000UL) // R/WC +#define INT_STS_RXDFH_INT_ (0x00800000UL) // R/WC +#define INT_STS_RXDF_INT_ (0x00400000UL) // R/WC +#define INT_STS_TX_IOC_ (0x00200000UL) // R/WC +#define INT_STS_RXD_INT_ (0x00100000UL) // R/WC +#define INT_STS_GPT_INT_ (0x00080000UL) // R/WC +#define INT_STS_PHY_INT_ (0x00040000UL) // RO +#define INT_STS_PME_INT_ (0x00020000UL) // R/WC +#define INT_STS_TXSO_ (0x00010000UL) // R/WC +#define INT_STS_RWT_ (0x00008000UL) // R/WC +#define INT_STS_RXE_ (0x00004000UL) // R/WC +#define INT_STS_TXE_ (0x00002000UL) // R/WC +#define INT_STS_ERX_ (0x00001000UL) // R/WC +#define INT_STS_TDFU_ (0x00000800UL) // R/WC +#define INT_STS_TDFO_ (0x00000400UL) // R/WC +#define INT_STS_TDFA_ (0x00000200UL) // R/WC +#define INT_STS_TSFF_ (0x00000100UL) // R/WC +#define INT_STS_TSFL_ (0x00000080UL) // R/WC +#define INT_STS_RDFO_ (0x00000040UL) // R/WC +#define INT_STS_RDFL_ (0x00000020UL) // R/WC +#define INT_STS_RSFF_ (0x00000010UL) // R/WC +#define INT_STS_RSFL_ (0x00000008UL) // R/WC +#define INT_STS_GPIO2_INT_ (0x00000004UL) // R/WC +#define INT_STS_GPIO1_INT_ (0x00000002UL) // R/WC +#define INT_STS_GPIO0_INT_ (0x00000001UL) // R/WC + +#define INT_EN (0x5CUL) +#define INT_EN_SW_INT_EN_ (0x80000000UL) // R/W +#define INT_EN_TXSTOP_INT_EN_ (0x02000000UL) // R/W +#define INT_EN_RXSTOP_INT_EN_ (0x01000000UL) // R/W +#define INT_EN_RXDFH_INT_EN_ (0x00800000UL) // R/W +#define INT_EN_RXDF_INT_EN_ (0x00400000UL) // R/W +#define INT_EN_TIOC_INT_EN_ (0x00200000UL) // R/W +#define INT_EN_RXD_INT_EN_ (0x00100000UL) // R/W +#define INT_EN_GPT_INT_EN_ (0x00080000UL) // R/W +#define INT_EN_PHY_INT_EN_ (0x00040000UL) // R/W +#define INT_EN_PME_INT_EN_ (0x00020000UL) // R/W +#define INT_EN_TXSO_EN_ (0x00010000UL) // R/W +#define INT_EN_RWT_EN_ (0x00008000UL) // R/W +#define INT_EN_RXE_EN_ (0x00004000UL) // R/W +#define INT_EN_TXE_EN_ (0x00002000UL) // R/W +#define INT_EN_ERX_EN_ (0x00001000UL) // R/W +#define INT_EN_TDFU_EN_ (0x00000800UL) // R/W +#define INT_EN_TDFO_EN_ (0x00000400UL) // R/W +#define INT_EN_TDFA_EN_ (0x00000200UL) // R/W +#define INT_EN_TSFF_EN_ (0x00000100UL) // R/W +#define INT_EN_TSFL_EN_ (0x00000080UL) // R/W +#define INT_EN_RDFO_EN_ (0x00000040UL) // R/W +#define INT_EN_RDFL_EN_ (0x00000020UL) // R/W +#define INT_EN_RSFF_EN_ (0x00000010UL) // R/W +#define INT_EN_RSFL_EN_ (0x00000008UL) // R/W +#define INT_EN_GPIO2_INT_ (0x00000004UL) // R/W +#define INT_EN_GPIO1_INT_ (0x00000002UL) // R/W +#define INT_EN_GPIO0_INT_ (0x00000001UL) // R/W + +#define BYTE_TEST (0x64UL) +#define FIFO_INT (0x68UL) +#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000UL) // R/W +#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000UL) // R/W +#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00UL) // R/W +#define FIFO_INT_RX_STS_LEVEL_ (0x000000FFUL) // R/W + +#define RX_CFG (0x6CUL) +#define RX_CFG_RX_END_ALGN_ (0xC0000000UL) // R/W +#define RX_CFG_RX_END_ALGN4_ (0x00000000UL) // R/W +#define RX_CFG_RX_END_ALGN16_ (0x40000000UL) // R/W +#define RX_CFG_RX_END_ALGN32_ (0x80000000UL) // R/W +#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000UL) // R/W +#define RX_CFG_RX_DUMP_ (0x00008000UL) // R/W +#define RX_CFG_RXDOFF_ (0x00001F00UL) // R/W +#define RX_CFG_RXDOFF_2_ (0x00000200UL) //Rx data offset is 2 +#define RX_CFG_RXDOFF_18_ (0x00001200UL) //Rx data offset is 0x12 +#define RX_CFG_RXBAD_ (0x00000001UL) // R/W + +#define TX_CFG (0x70UL) +#define TX_CFG_TX_DMA_LVL_ (0xE0000000UL) // R/W +#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000UL) // R/W Self Clearing +#define TX_CFG_TXS_DUMP_ (0x00008000UL) // Self Clearing +#define TX_CFG_TXD_DUMP_ (0x00004000UL) // Self Clearing +#define TX_CFG_TXSAO_ (0x00000004UL) // R/W +#define TX_CFG_TX_ON_ (0x00000002UL) // R/W +#define TX_CFG_STOP_TX_ (0x00000001UL) // Self Clearing + +#define HW_CFG (0x74UL) +#define HW_CFG_AMDIX_EN_STRAP_STS_ (0x01000000UL) +#define HW_CFG_TTM_ (0x00200000UL) // R/W +#define HW_CFG_SF_ (0x00100000UL) // R/W +#define HW_CFG_TX_FIF_SZ_ (0x000F0000UL) // R/W +#define HW_CFG_TR_ (0x00003000UL) // R/W +#define HW_CFG_PHY_CLK_SEL_ (0x00000060UL) // R/W +#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000UL) // R/W +#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020UL) // R/W +#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040UL) // R/W +#define HW_CFG_SMI_SEL_ (0x00000010UL) // R/W +#define HW_CFG_EXT_PHY_DET_ (0x00000008UL) // RO +#define HW_CFG_EXT_PHY_EN_ (0x00000004UL) // R/W +#define HW_CFG_32_16_BIT_MODE_ (0x00000004UL) // RO +#define HW_CFG_SRST_TO_ (0x00000002UL) // RO +#define HW_CFG_SRST_ (0x00000001UL) // Self Clearing + +#define RX_DP_CTRL (0x78UL) +#define RX_DP_CTRL_RX_FFWD_ (0x00000FFFUL) // R/W +#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000UL) // RO + +#define RX_FIFO_INF (0x7CUL) +#define RX_FIFO_INF_RXSUSED_ (0x00FF0000UL) // RO +#define RX_FIFO_INF_RXDUSED_ (0x0000FFFFUL) // RO + +#define TX_FIFO_INF (0x80UL) +#define TX_FIFO_INF_TSUSED_ (0x00FF0000UL) // RO +#define TX_FIFO_INF_TSFREE_ (0x00FF0000UL) // RO +#define TX_FIFO_INF_TDFREE_ (0x0000FFFFUL) // RO + +#define PMT_CTRL (0x84UL) +#define PMT_CTRL_PM_MODE_ (0x00018000UL) // Self Clearing +#define PMT_CTRL_PHY_RST_ (0x00000400UL) // Self Clearing +#define PMT_CTRL_WOL_EN_ (0x00000200UL) // R/W +#define PMT_CTRL_ED_EN_ (0x00000100UL) // R/W +#define PMT_CTRL_PME_TYPE_ (0x00000040UL) // R/W Not Affected by SW Reset +#define PMT_CTRL_WUPS_ (0x00000030UL) // R/WC +#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000UL) // R/WC +#define PMT_CTRL_WUPS_ED_ (0x00000010UL) // R/WC +#define PMT_CTRL_WUPS_WOL_ (0x00000020UL) // R/WC +#define PMT_CTRL_WUPS_MULTI_ (0x00000030UL) // R/WC +#define PMT_CTRL_PME_IND_ (0x00000008UL) // R/W +#define PMT_CTRL_PME_POL_ (0x00000004UL) // R/W +#define PMT_CTRL_PME_EN_ (0x00000002UL) // R/W Not Affected by SW Reset +#define PMT_CTRL_READY_ (0x00000001UL) // RO + +#define GPIO_CFG (0x88UL) +#define GPIO_CFG_LED3_EN_ (0x40000000UL) // R/W +#define GPIO_CFG_LED2_EN_ (0x20000000UL) // R/W +#define GPIO_CFG_LED1_EN_ (0x10000000UL) // R/W +#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000UL) // R/W +#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000UL) // R/W +#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000UL) // R/W +#define GPIO_CFG_EEPR_EN_ (0x00E00000UL) // R/W +#define GPIO_CFG_GPIOBUF2_ (0x00040000UL) // R/W +#define GPIO_CFG_GPIOBUF1_ (0x00020000UL) // R/W +#define GPIO_CFG_GPIOBUF0_ (0x00010000UL) // R/W +#define GPIO_CFG_GPIODIR2_ (0x00000400UL) // R/W +#define GPIO_CFG_GPIODIR1_ (0x00000200UL) // R/W +#define GPIO_CFG_GPIODIR0_ (0x00000100UL) // R/W +#define GPIO_CFG_GPIOD4_ (0x00000020UL) // R/W +#define GPIO_CFG_GPIOD3_ (0x00000010UL) // R/W +#define GPIO_CFG_GPIOD2_ (0x00000004UL) // R/W +#define GPIO_CFG_GPIOD1_ (0x00000002UL) // R/W +#define GPIO_CFG_GPIOD0_ (0x00000001UL) // R/W + +#define GPT_CFG (0x8CUL) +#define GPT_CFG_TIMER_EN_ (0x20000000UL) // R/W +#define GPT_CFG_GPT_LOAD_ (0x0000FFFFUL) // R/W + +#define GPT_CNT (0x90UL) +#define GPT_CNT_GPT_CNT_ (0x0000FFFFUL) // RO + +#define FPGA_REV (0x94UL) +#define FPGA_REV_FPGA_REV_ (0x0000FFFFUL) // RO + +#define WORD_SWAP (0x98UL) +#define FREE_RUN (0x9CUL) +#define RX_DROP (0xA0UL) +#define MAC_CSR_CMD (0xA4UL) +#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000UL) // Self Clearing +#define MAC_CSR_CMD_R_NOT_W_ (0x40000000UL) // R/W +#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FFUL) // R/W + +#define MAC_CSR_DATA (0xA8UL) +#define AFC_CFG (0xACUL) +#define AFC_CFG_AFC_HI_ (0x00FF0000UL) // R/W +#define AFC_CFG_AFC_LO_ (0x0000FF00UL) // R/W +#define AFC_CFG_BACK_DUR_ (0x000000F0UL) // R/W +#define AFC_CFG_FCMULT_ (0x00000008UL) // R/W +#define AFC_CFG_FCBRD_ (0x00000004UL) // R/W +#define AFC_CFG_FCADD_ (0x00000002UL) // R/W +#define AFC_CFG_FCANY_ (0x00000001UL) // R/W + +#define E2P_CMD (0xB0UL) +#define E2P_CMD_EPC_BUSY_ (0x80000000UL) // Self Clearing +#define E2P_CMD_EPC_CMD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) // R/W +#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) // R +#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) // RO +#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) // R/W + +#define E2P_DATA (0xB4UL) +#define E2P_DATA_EEPROM_DATA_ (0x000000FFUL) // R/W +//end of lan register offsets and bit definitions + +#define LAN_REGISTER_EXTENT (0x00002000UL) + +//The following describes the synchronization policies used in this driver. +//Register Name Policy +//RX_DATA_FIFO Only used by the Rx Thread, Rx_ProcessPackets +//TX_DATA_FIFO Only used by the Tx Thread, Tx_SendSkb +//RX_STATUS_FIFO Only used by the Rx Thread, Rx_ProcessPackets +//RX_STATUS_FIFO_PEEK Not used. +//TX_STATUS_FIFO Used in Tx_CompleteTx in Tx_UpdateTxCounters. +// protected by TxCounterLock +//TX_STATUS_FIFO_PEEK Not used. +//ID_REV Read only +//INT_CFG Set in Lan_Initialize, +// protected by IntEnableLock +//INT_STS Sharable, +//INT_EN Initialized at startup, +// Used in Rx_ProcessPackets +// otherwise protected by IntEnableLock +//BYTE_TEST Read Only +//FIFO_INT Initialized at startup, +// During run time only accessed by +// Tx_HandleInterrupt, and Tx_SendSkb and done in a safe manner +//RX_CFG Used during initialization +// During runtime only used by Rx Thread +//TX_CFG Only used during initialization +//HW_CFG Only used during initialization +//RX_DP_CTRL Only used in Rx Thread, in Rx_FastForward +//RX_FIFO_INF Read Only, Only used in Rx Thread, in Rx_PopRxStatus +//TX_FIFO_INF Read Only, Only used in Tx Thread, in Tx_GetTxStatusCount, Tx_SendSkb, Tx_CompleteTx +//PMT_CTRL Not Used +//GPIO_CFG used during initialization, in Lan_Initialize +// used for debugging +// used during EEPROM access. +// safe enough to not require a lock +//GPT_CFG protected by GpTimerLock +//GPT_CNT Not Used +//WORD_SWAP Not Used +//FREE_RUN Read only +//RX_DROP Used in Rx Interrupt Handler, +// and get_stats. +// safe enough to not require a lock. +//MAC_CSR_CMD Protected by MacPhyLock +//MAC_CSR_DATA Protected by MacPhyLock +// Because the two previous MAC_CSR_ registers are protected +// All MAC, and PHY registers are protected as well. +//AFC_CFG Used during initialization, in Lan_Initialize +// During run time, used in timer call back, in Phy_UpdateLinkMode +//E2P_CMD Used during initialization, in Lan_Initialize +// Used in EEPROM functions +//E2P_DATA Used in EEPROM functions + +#include "platform_alchemy.h" + +#define Lan_GetRegDW(dwOffset) \ + Platform_GetRegDW(privateData->dwLanBase,dwOffset) + +#define Lan_SetRegDW(dwOffset,dwVal) \ + Platform_SetRegDW(privateData->dwLanBase,dwOffset,dwVal) + +#define Lan_ClrBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(privateData->dwLanBase, \ + dwOffset,Platform_GetRegDW(privateData->dwLanBase, \ + dwOffset)&(~dwBits)) + +#define Lan_SetBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(privateData->dwLanBase, \ + dwOffset,Platform_GetRegDW(privateData->dwLanBase, \ + dwOffset)|dwBits); + +#define LINK_OFF (0x00UL) +#define LINK_SPEED_10HD (0x01UL) +#define LINK_SPEED_10FD (0x02UL) +#define LINK_SPEED_100HD (0x04UL) +#define LINK_SPEED_100FD (0x08UL) +#define LINK_SYMMETRIC_PAUSE (0x10UL) +#define LINK_ASYMMETRIC_PAUSE (0x20UL) +#define LINK_AUTO_NEGOTIATE (0x40UL) + +typedef unsigned long VL_KEY; +typedef struct _VERIFIABLE_LOCK { + spinlock_t Lock; + VL_KEY KeyCode; +} VERIFIABLE_LOCK, * PVERIFIABLE_LOCK; + +void Vl_InitLock(PVERIFIABLE_LOCK pVl); +bool Vl_CheckLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode); +VL_KEY Vl_WaitForLock(PVERIFIABLE_LOCK pVl,unsigned long *pdwIntFlags); +void Vl_ReleaseLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode,unsigned long *pdwIntFlags); + +typedef struct _PRIVATE_DATA { + u32 dwLanBase; + u32 dwIdRev; + u32 dwFpgaRev; + struct net_device *dev; + u32 dwGeneration;//used to decide which workarounds apply + bool UseScatterGather; + bool UseTxCsum; + bool UseRxCsum; + + + spinlock_t IntEnableLock; + bool LanInitialized; + VERIFIABLE_LOCK MacPhyLock; + bool ExtPhy; // + + u32 dwTxDmaCh; + bool TxDmaChReserved; + DMA_XFER TxDmaXfer; + u32 dwTxDmaThreshold; + u32 dwTxQueueDisableMask; + struct sk_buff *TxSkb; + spinlock_t TxSkbLock; + spinlock_t TxQueueLock; + spinlock_t TxCounterLock; + bool TxInitialized; + + + + // BYTE bCoalesceBuf[1600]; + + + + // struct sk_buff *TxSkbPending; + + + u32 dwRxDmaCh; + struct sk_buff *RxSkb; + bool RxDmaChReserved; + u32 dwRxDmaThreshold; + bool RxCongested; + u32 dwRxOffCount; + bool RxOverrun; + u32 RxOverrunCount; + u32 RxStatusDWReadCount; + u32 RxDataDWReadCount; + u32 RxPacketReadCount; + u32 RxFastForwardCount; + u32 RxPioReadCount; + u32 RxDmaReadCount; + u32 RxCongestedCount; + u32 RxDumpCount; + u32 LastReasonForReleasingCPU; + u32 LastRxStatus1; + u32 LastRxStatus2; + u32 LastRxStatus3; + u32 LastIntStatus1; + u32 LastIntStatus2; + u32 LastIntStatus3; + u32 RxUnloadProgress; + u32 RxUnloadPacketProgress; + u32 RxMaxDataFifoSize; + // bool RxVLanPkt; + + //NAPI + int RxWorkLimit; + int RxPacketsReceived; + // bool RxDone; + + + u32 RxFlowCurrentThroughput; + u32 RxFlowCurrentPacketCount; + u32 RxFlowCurrentWorkLoad; + bool MeasuringRxThroughput; + u32 RxFlowMeasuredMaxThroughput; + u32 RxFlowMeasuredMaxPacketCount; + + //RX_FLOW_ACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must exceed + // RxFlowMaxWorkLoad in order to activate flow control +#define RX_FLOW_ACTIVATION (4UL) + + //RX_FLOW_DEACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must reduce + // from RxFlowMaxWorkLoad in order to deactivate flow control +#define RX_FLOW_DEACTIVATION (25UL) + u32 RxFlowMaxWorkLoad; + + FLOW_CONTROL_PARAMETERS RxFlowParameters; + + u32 RxFlowBurstWorkLoad; + u32 RxFlowBurstMaxWorkLoad; + bool RxFlowControlActive; + bool RxFlowBurstActive; + u32 RxInterrupts; + +#define GPT_SCHEDULE_DEPTH (3) + void *GptFunction[GPT_SCHEDULE_DEPTH]; + u32 GptCallTime[GPT_SCHEDULE_DEPTH]; + u32 Gpt_scheduled_slot_index; + spinlock_t GpTimerLock; + + bool Running; + struct net_device_stats stats; + + u32 dwPhyAddress; + u32 dwPhyId; +#ifdef USE_LED1_WORK_AROUND + u32 NotUsingExtPhy; +#endif + BYTE bPhyModel; + BYTE bPhyRev; + u32 dwLinkSpeed; + u32 dwLinkSettings; + u32 dwRemoteFaultCount; + struct timer_list LinkPollingTimer; + bool StopLinkPolling; + WORD wLastADV; + WORD wLastADVatRestart; +#ifdef USE_PHY_WORK_AROUND +#define MIN_PACKET_SIZE (64) + u32 dwTxStartMargen; + BYTE LoopBackTxPacket[MIN_PACKET_SIZE]; + u32 dwTxEndMargen; + u32 dwRxStartMargen; + BYTE LoopBackRxPacket[MIN_PACKET_SIZE]; + u32 dwRxEndMargen; + u32 dwResetCount; +#endif + + bool SoftwareInterruptSignal; + + PLATFORM_DATA PlatformData; + +#define SMSC_IF_NAME_SIZE (10) + char ifName[SMSC_IF_NAME_SIZE]; + + /* for Rx Multicast work around */ + volatile u32 HashLo; + volatile u32 HashHi; + volatile bool MulticastUpdatePending; + volatile u32 set_bits_mask; + volatile u32 clear_bits_mask; + +} PRIVATE_DATA, *PPRIVATE_DATA; + + +/* + **************************************************************************** + **************************************************************************** + * MAC Control and Status Register (Indirect Address) + * Offset (through the MAC_CSR CMD and DATA port) + **************************************************************************** + **************************************************************************** + * + */ +#define MAC_CR (0x01UL) // R/W + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL_ (0x80000000UL) +#define MAC_CR_HBDIS_ (0x10000000UL) +#define MAC_CR_RCVOWN_ (0x00800000UL) +#define MAC_CR_LOOPBK_ (0x00200000UL) +#define MAC_CR_FDPX_ (0x00100000UL) +#define MAC_CR_MCPAS_ (0x00080000UL) +#define MAC_CR_PRMS_ (0x00040000UL) +#define MAC_CR_INVFILT_ (0x00020000UL) +#define MAC_CR_PASSBAD_ (0x00010000UL) +#define MAC_CR_HFILT_ (0x00008000UL) +#define MAC_CR_HPFILT_ (0x00002000UL) +#define MAC_CR_LCOLL_ (0x00001000UL) +#define MAC_CR_BCAST_ (0x00000800UL) +#define MAC_CR_DISRTY_ (0x00000400UL) +#define MAC_CR_PADSTR_ (0x00000100UL) +#define MAC_CR_BOLMT_MASK_ (0x000000C0UL) +#define MAC_CR_DFCHK_ (0x00000020UL) +#define MAC_CR_TXEN_ (0x00000008UL) +#define MAC_CR_RXEN_ (0x00000004UL) + +#define ADDRH (0x02UL) // R/W mask 0x0000FFFFUL +#define ADDRL (0x03UL) // R/W mask 0xFFFFFFFFUL +#define HASHH (0x04UL) // R/W +#define HASHL (0x05UL) // R/W + +#define MII_ACC (0x06UL) // R/W +#define MII_ACC_PHY_ADDR_ (0x0000F800UL) +#define MII_ACC_MIIRINDA_ (0x000007C0UL) +#define MII_ACC_MII_WRITE_ (0x00000002UL) +#define MII_ACC_MII_BUSY_ (0x00000001UL) + +#define MII_DATA (0x07UL) // R/W mask 0x0000FFFFUL + +#define FLOW (0x08UL) // R/W +#define FLOW_FCPT_ (0xFFFF0000UL) +#define FLOW_FCPASS_ (0x00000004UL) +#define FLOW_FCEN_ (0x00000002UL) +#define FLOW_FCBSY_ (0x00000001UL) + +#define VLAN1 (0x09UL) // R/W mask 0x0000FFFFUL +#define VLAN2 (0x0AUL) // R/W mask 0x0000FFFFUL + +#define WUFF (0x0BUL) // WO + +#define WUCSR (0x0CUL) // R/W +#define WUCSR_GUE_ (0x00000200UL) +#define WUCSR_WUFR_ (0x00000040UL) +#define WUCSR_MPR_ (0x00000020UL) +#define WUCSR_WAKE_EN_ (0x00000004UL) +#define WUCSR_MPEN_ (0x00000002UL) + +#define COE_CR 0xDUL +#define TX_COE_EN 0x00010000UL +#define RX_COE_MODE 0x00000002UL +#define RX_COE_EN 0x00000001UL + + +bool Mac_Initialize(PPRIVATE_DATA privateData); +static bool MacNotBusy(PPRIVATE_DATA privateData,VL_KEY keyCode); +u32 Mac_GetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,VL_KEY keyCode); +void Mac_SetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,u32 dwVal,VL_KEY keyCode); + +/* + **************************************************************************** + * Chip Specific MII Defines + **************************************************************************** + * + * Phy register offsets and bit definitions + * + */ +#define LAN9118_PHY_ID (0x00C0001C) + +#define PHY_BCR ((u32)0U) +#define PHY_BCR_RESET_ ((WORD)0x8000U) +#define PHY_BCR_LOOPBACK_ ((WORD)0x4000U) +#define PHY_BCR_SPEED_SELECT_ ((WORD)0x2000U) +#define PHY_BCR_AUTO_NEG_ENABLE_ ((WORD)0x1000U) +#define PHY_BCR_RESTART_AUTO_NEG_ ((WORD)0x0200U) +#define PHY_BCR_DUPLEX_MODE_ ((WORD)0x0100U) + +#define PHY_BSR ((u32)1U) +#define PHY_BSR_LINK_STATUS_ ((WORD)0x0004U) +#define PHY_BSR_REMOTE_FAULT_ ((WORD)0x0010U) +#define PHY_BSR_AUTO_NEG_COMP_ ((WORD)0x0020U) + +#define PHY_ID_1 ((u32)2U) +#define PHY_ID_2 ((u32)3U) + +#define PHY_ANEG_ADV ((u32)4U) +#define PHY_ANEG_ADV_PAUSE_ ((WORD)0x0C00) +#define PHY_ANEG_ADV_ASYMP_ ((WORD)0x0800) +#define PHY_ANEG_ADV_SYMP_ ((WORD)0x0400) +#define PHY_ANEG_ADV_10H_ ((WORD)0x20) +#define PHY_ANEG_ADV_10F_ ((WORD)0x40) +#define PHY_ANEG_ADV_100H_ ((WORD)0x80) +#define PHY_ANEG_ADV_100F_ ((WORD)0x100) +#define PHY_ANEG_ADV_SPEED_ ((WORD)0x1E0) + +#define PHY_ANEG_LPA ((u32)5U) +#define PHY_ANEG_LPA_ASYMP_ ((WORD)0x0800) +#define PHY_ANEG_LPA_SYMP_ ((WORD)0x0400) +#define PHY_ANEG_LPA_100FDX_ ((WORD)0x0100) +#define PHY_ANEG_LPA_100HDX_ ((WORD)0x0080) +#define PHY_ANEG_LPA_10FDX_ ((WORD)0x0040) +#define PHY_ANEG_LPA_10HDX_ ((WORD)0x0020) + +#define PHY_MODE_CTRL_STS ((u32)17) // Mode Control/Status Register +#define MODE_CTRL_STS_FASTRIP_ ((WORD)0x4000U) +#define MODE_CTRL_STS_EDPWRDOWN_ ((WORD)0x2000U) +#define MODE_CTRL_STS_LOWSQEN_ ((WORD)0x0800U) +#define MODE_CTRL_STS_MDPREBP_ ((WORD)0x0400U) +#define MODE_CTRL_STS_FARLOOPBACK_ ((WORD)0x0200U) +#define MODE_CTRL_STS_FASTEST_ ((WORD)0x0100U) +#define MODE_CTRL_STS_REFCLKEN_ ((WORD)0x0010U) +#define MODE_CTRL_STS_PHYADBP_ ((WORD)0x0008U) +#define MODE_CTRL_STS_FORCE_G_LINK_ ((WORD)0x0004U) +#define MODE_CTRL_STS_ENERGYON_ ((WORD)0x0002U) + +#define SPECIAL_CTRL_STS ((u32)27) +#define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((WORD)0x8000U) +#define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((WORD)0x4000U) +#define SPECIAL_CTRL_STS_AMDIX_STATE_ ((WORD)0x2000U) + +#define PHY_INT_SRC ((u32)29) +#define PHY_INT_SRC_ENERGY_ON_ ((WORD)0x0080U) +#define PHY_INT_SRC_ANEG_COMP_ ((WORD)0x0040U) +#define PHY_INT_SRC_REMOTE_FAULT_ ((WORD)0x0020U) +#define PHY_INT_SRC_LINK_DOWN_ ((WORD)0x0010U) + +#define PHY_INT_MASK ((u32)30) +#define PHY_INT_MASK_ENERGY_ON_ ((WORD)0x0080U) +#define PHY_INT_MASK_ANEG_COMP_ ((WORD)0x0040U) +#define PHY_INT_MASK_REMOTE_FAULT_ ((WORD)0x0020U) +#define PHY_INT_MASK_LINK_DOWN_ ((WORD)0x0010U) + +#define PHY_SPECIAL ((u32)31) +#define PHY_SPECIAL_SPD_ ((WORD)0x001CU) +#define PHY_SPECIAL_SPD_10HALF_ ((WORD)0x0004U) +#define PHY_SPECIAL_SPD_10FULL_ ((WORD)0x0014U) +#define PHY_SPECIAL_SPD_100HALF_ ((WORD)0x0008U) +#define PHY_SPECIAL_SPD_100FULL_ ((WORD)0x0018U) + +#define AMDIX_DISABLE_STRAIGHT ((WORD)0x0U) +#define AMDIX_DISABLE_CROSSOVER ((WORD)0x01U) +#define AMDIX_ENABLE ((WORD)0x02U) + +bool Phy_Initialize( + PPRIVATE_DATA privateData, + u32 dwPhyAddress, + u32 dwLinkMode); +void Phy_SetLink(PPRIVATE_DATA privateData, + u32 dwLinkRequest); +WORD Phy_GetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + VL_KEY keyCode); +void Phy_SetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + WORD wVal, + VL_KEY keyCode); +void Phy_UpdateLinkMode( + PPRIVATE_DATA privateData); +void Phy_GetLinkMode( + PPRIVATE_DATA privateData, + VL_KEY keyCode); +void Phy_CheckLink(unsigned long ptr); +void Phy_SetAutoMdixSts(PPRIVATE_DATA privateData, + WORD wAutoMdixSts); +void Phy_GetAutoMdixSts(PPRIVATE_DATA privateData); + + + + + +TIME_SPAN Gpt_FreeRunCompare(u32 time1,u32 time2); +void Gpt_ScheduleInterrupt(PPRIVATE_DATA privateData,TIME_SPAN timeSpan); +void Gpt_CancelInterrupt(PPRIVATE_DATA privateData); +void Gpt_CancelCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData)); +void Gpt_ScheduleCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData), + u32 callBackTime);//100uS units relative to now +bool Gpt_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts); +void GptCB_RxCompleteMulticast(PPRIVATE_DATA privateData); +void GptCB_RestartBurst(PPRIVATE_DATA privateData); +void GptCB_MeasureRxThroughput(PPRIVATE_DATA privateData); + +void Tx_Initialize( + PPRIVATE_DATA privateData, + u32 dwTxDmaCh, + u32 dwTxDmaThreshold); +void Tx_SendSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb); +bool Tx_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts); + +void Tx_StopQueue( + PPRIVATE_DATA privateData,u32 dwSource); +void Tx_WakeQueue( + PPRIVATE_DATA privateData,u32 dwSource); + +static u32 Tx_GetTxStatusCount( + PPRIVATE_DATA privateData); +static u32 Tx_CompleteTx( + PPRIVATE_DATA privateData); +void Tx_UpdateTxCounters( + PPRIVATE_DATA privateData); + +void Tx_CompleteDma( + PPRIVATE_DATA privateData); + +void CalculateTxChecksumOffset( + struct sk_buff *skb, + int *csum_start_offset); + +void rkdump(unsigned char *p, unsigned short len); + +void Rx_Initialize( + PPRIVATE_DATA privateData, + u32 dwRxDmaCh, + u32 dwDmaThreshold); + +void Rx_CompleteMulticastUpdate (PPRIVATE_DATA privateData); +static void Rx_HandleOverrun(PPRIVATE_DATA privateData); +static void Rx_HandOffSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb); +static u32 Rx_PopRxStatus( + PPRIVATE_DATA privateData); +void Rx_CountErrors(PPRIVATE_DATA privateData,u32 dwRxStatus); +void Rx_FastForward(PPRIVATE_DATA privateData,u32 dwDwordCount); +void Rx_ProcessPackets(PPRIVATE_DATA privateData); +void Rx_BeginMulticastUpdate (PPRIVATE_DATA privateData); + +unsigned long Rx_TaskletParameter=0; + +void Rx_ProcessPacketsTasklet(unsigned long data); +DECLARE_TASKLET(Rx_Tasklet,Rx_ProcessPacketsTasklet,0); + +#ifdef LINUX_2_6_OR_NEWER +int Smsc9118_rx_poll(struct net_device *dev,int * budget); +#endif + +bool RxStop_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts); +bool Rx_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts); +static u32 Rx_Hash(BYTE addr[6]); + +void Rx_SetMulticastList( + struct net_device *dev); +void Rx_ReceiverOff( + PPRIVATE_DATA privateData); +void Rx_ReceiverOn( + PPRIVATE_DATA privateData, VL_KEY callerKeyCode); + + +void Eeprom_EnableAccess(PPRIVATE_DATA privateData); +void Eeprom_DisableAccess(PPRIVATE_DATA privateData); + +bool Eeprom_IsMacAddressLoaded(PPRIVATE_DATA privateData); +bool Eeprom_IsBusy(PPRIVATE_DATA privateData); +bool Eeprom_Timeout(PPRIVATE_DATA privateData); + +bool Eeprom_ReadLocation( + PPRIVATE_DATA privateData,BYTE address, BYTE * data); +bool Eeprom_EnableEraseAndWrite( + PPRIVATE_DATA privateData); +bool Eeprom_DisableEraseAndWrite( + PPRIVATE_DATA privateData); +bool Eeprom_WriteLocation( + PPRIVATE_DATA privateData,BYTE address,BYTE data); +bool Eeprom_EraseAll( + PPRIVATE_DATA privateData); +bool Eeprom_Reload( + PPRIVATE_DATA privateData); + +bool Eeprom_SaveMacAddress( + PPRIVATE_DATA privateData, + u32 dwHi16,u32 dwLo32); +extern int smsc_prom_get_ethernet_mac_addr(char *addr); + + +#define OLD_REGISTERS(privData) (((privData->dwIdRev)==0x01180000UL)&& \ + ((privData->dwFpgaRev)>=0x01)&& \ + ((privData->dwFpgaRev)<=0x25)) + +extern volatile u32 g_GpioSetting; +#define GP_0 (0x01UL) +#define GP_1 (0x02UL) +#define GP_2 (0x04UL) +#define GP_3 (0x08UL) +#define GP_4 (0x10UL) +#define GP_OFF (0x00UL) +#define GP_ISR GP_OFF +#define GP_RX GP_OFF +#define GP_TX GP_OFF +#define GP_BEGIN_MULTICAST_UPDATE GP_OFF +#define GP_COMPLETE_MULTICAST_UPDATE GP_OFF + +#define SET_GPIO(gpioBit) \ + if(debug_mode&0x04UL) { \ + g_GpioSetting|=gpioBit; \ + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); \ + } + +#define CLEAR_GPIO(gpioBit) \ + if(debug_mode&0x04UL) { \ + g_GpioSetting&=(~gpioBit); \ + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); \ + } + +#define PULSE_GPIO(gpioBit,count) \ + if(debug_mode&0x04UL) { \ + u32 pulseNum=0; \ + /*make first pulse longer */ \ + SET_GPIO(gpioBit); \ + while(pulseNum init_module()"); + SMSC_TRACE("Compiled: %s, %s",__DATE__,__TIME__); + SMSC_TRACE("Platform: %s",PLATFORM_NAME); + SMSC_TRACE("Driver Parameters"); + + if(lan_base==0UL) { + SMSC_TRACE(" lan_base = 0x%08X, driver will decide",lan_base); + } else { + SMSC_TRACE(" lan_base = 0x%08X",lan_base); + } + if((bus_width==16UL)||(bus_width==32UL)) { + SMSC_TRACE(" bus_width = %d",bus_width); + } else { + SMSC_TRACE(" bus_width = %d, driver will autodetect",bus_width); + } + if(link_mode>0x7FUL) { + SMSC_WARNING(" link_mode = %d, Unknown",link_mode); + link_mode=0x7FUL; + SMSC_WARNING(" resetting link_mode to %d, 100FD,100HD,10FD,10HD,ASYMP,SYMP,ANEG",link_mode); + } else if(link_mode==0UL) { + SMSC_TRACE(" link_mode = %d, LINK_OFF",link_mode); + } else { + SMSC_TRACE(" link_mode = 0x%X, %s,%s,%s,%s,%s,%s,%s", + link_mode, + (link_mode&LINK_SPEED_10HD)?"10HD":"", + (link_mode&LINK_SPEED_10FD)?"10FD":"", + (link_mode&LINK_SPEED_100HD)?"100HD":"", + (link_mode&LINK_SPEED_100FD)?"100FD":"", + (link_mode&LINK_ASYMMETRIC_PAUSE)?"ASYMP":"", + (link_mode&LINK_SYMMETRIC_PAUSE)?"SYMP":"", + (link_mode&LINK_AUTO_NEGOTIATE)?"ANEG":""); + } + SMSC_TRACE( " irq = %d",irq); + if(int_deas!=0xFFFFFFFFUL) { + if(int_deas>0xFFUL) { + SMSC_WARNING(" int_deas = %d, too high",int_deas); + int_deas=0xFFFFFFFFUL; + SMSC_WARNING(" resetting int_deas to %d",int_deas); + } + } + if(int_deas==0xFFFFFFFFUL) { + SMSC_TRACE( " int_deas = 0x%08X, use platform default",int_deas); + } else { + SMSC_TRACE( " int_deas = %d, %duS",int_deas,(unsigned int)(10UL*int_deas)); + } + if(irq_pol) { + SMSC_TRACE(" irq_pol = %d, IRQ output is active high",irq_pol); + } else { + SMSC_TRACE(" irq_pol = %d, IRQ output is active low",irq_pol); + } + if(irq_type) { + SMSC_TRACE(" irq_type = %d, IRQ output is Push-Pull driver",irq_type); + } else { + SMSC_TRACE(" irq_type = %d, IRQ output is Open-Drain buffer",irq_type); + } + if(rx_dma0x000E0000UL) { + SMSC_WARNING("tx_fif_sz = 0x%08X is too high",tx_fif_sz); + tx_fif_sz=0x000E0000UL; + SMSC_WARNING(" resetting tx_fif_sz to 0x%08X",tx_fif_sz); + } + if(tx_fif_sz<0x00020000UL) { + SMSC_WARNING("tx_fif_sz = 0x%08X is too low",tx_fif_sz); + tx_fif_sz=0x00020000UL; + SMSC_WARNING(" resetting tx_fif_sz to 0x%08X",tx_fif_sz); + } + SMSC_TRACE( " tx_fif_sz = 0x%08X",tx_fif_sz); + if(afc_cfg==0xFFFFFFFFUL) { + SMSC_TRACE(" afc_cfg = 0x%08X, driver will decide",afc_cfg); + } else { + if(afc_cfg&0xFF000000UL) { + SMSC_WARNING("afc_cfg = 0x%08X is invalid",afc_cfg); + afc_cfg&=0xFFFFFFFFUL; + SMSC_WARNING(" resetting to afc_cfg = 0x%08X, driver will decide",afc_cfg); + } else { + SMSC_TRACE( + " afc_cfg = 0x%08X",afc_cfg); + } + } + if(rx_mode==PROCESSING_MODE_TASKLET) { + SMSC_TRACE(" rx_mode = 0x%08X, Tasklets enabled",rx_mode); + } else if(rx_mode==PROCESSING_MODE_NAPI) { +#ifndef LINUX_2_6_OR_NEWER + SMSC_WARNING(" rx_mode = 0x%08X requires Linux 2.6 or newer", rx_mode); + rx_mode=PROCESSING_MODE_TASKLET; + SMSC_WARNING(" resetting to rx_mode = 0x%08X, Tasklets enabled", rx_mode); +#else + SMSC_TRACE(" rx_mode = 0x%08X, NAPI enabled",rx_mode); +#endif + } else { + SMSC_TRACE(" rx_mode = 0, use ISR"); + } + + if(phy_addr==0xFFFFFFFFUL) { + SMSC_TRACE(" phy_addr = 0xFFFFFFFF, Use internal phy"); + } else if(phy_addr<=31UL) { + SMSC_TRACE(" phy_addr = 0x%08X, use this address for external phy",phy_addr); + } else { + SMSC_TRACE(" phy_addr = 0x%08X, auto detect external phy",phy_addr); + } + if(max_throughput) { + SMSC_TRACE(" max_throughput = 0x%08X, Use platform default",max_throughput); + } else { + SMSC_TRACE(" max_throughput = 0x%08X",max_throughput); + } + if(max_packet_count) { + SMSC_TRACE(" max_packet_count = 0x%08X, Use platform default",max_packet_count); + } else { + SMSC_TRACE(" max_packet_count = 0x%08X",max_packet_count); + } + if(packet_cost) { + SMSC_TRACE(" packet_cost = 0x%08X, Use platform default",packet_cost); + } else { + SMSC_TRACE(" packet_cost = 0x%08X",packet_cost); + } + if(burst_period) { + SMSC_TRACE(" burst_period = 0x%08X, Use platform default",burst_period); + } else { + SMSC_TRACE(" burst_period = 0x%08X",burst_period); + } + if(max_work_load) { + SMSC_TRACE(" max_work_load = 0x%08X, Use platform default",max_work_load); + } else { + SMSC_TRACE(" max_work_load = 0x%08X",max_work_load); + } + + SMSC9118 = alloc_netdev_mq(0, "eth%d", Smsc9118_init, 1); + SMSC_TRACE(" alloc_netdev complete. SMSC9118 = 0x%08X\n", (u32)SMSC9118); + result=register_netdev(SMSC9118); + if(result) { + SMSC_WARNING("error %i registering device",result); + } else { + device_present=1; + SMSC_TRACE(" Interface Name = \"%s\"",SMSC9118->name); + } + result=result;//make lint happy + SMSC_TRACE("<-- init_module()"); + return device_present ? 0 : -ENODEV; +} + +void Smsc9118_cleanup_module(void) +{ + SMSC_TRACE("--> cleanup_module()"); + if(SMSC9118->ml_priv!=NULL) { + PPRIVATE_DATA privateData=(PPRIVATE_DATA)SMSC9118->ml_priv; + PPLATFORM_DATA platformData=(PPLATFORM_DATA)&(privateData->PlatformData); + Platform_CleanUp(platformData); + release_mem_region( + privateData->dwLanBase, + LAN_REGISTER_EXTENT); + printk("Freeing the IRQ \n"); + Platform_FreeIRQ(&(privateData->PlatformData)); + unregister_netdev(SMSC9118); + kfree(SMSC9118->ml_priv); + SMSC9118->ml_priv=NULL; + } + SMSC_TRACE("<-- cleanup_module()"); +} + +void Smsc9118_init(struct net_device *dev) +{ + u32 dwLanBase=0UL; + u32 dwIdRev=0UL; + u32 dwFpgaRev=0UL; + // WORD SpecialCtrlSts=0U; + PPRIVATE_DATA privateData=NULL; + PPLATFORM_DATA platformData=NULL; + bool platformInitialized=false; + int result=-ENODEV; + + int i; + bool acquired_mem_region=false; + bool acquired_isr=false; + + SMSC_TRACE("-->Smsc9118_init(dev=0x%08X)",(u32)dev); + + if(dev==NULL) { + SMSC_WARNING("Smsc9118_init(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + + if(dev->ml_priv!=NULL) { + SMSC_WARNING("dev->ml_priv!=NULL, going to overwrite pointer"); + } + dev->ml_priv=kmalloc(sizeof(PRIVATE_DATA),GFP_KERNEL); + if(dev->ml_priv==NULL) { + SMSC_WARNING("Unable to allocate PRIVATE_DATA"); + result=-ENOMEM; + goto DONE; + } + memset(dev->ml_priv,0,sizeof(PRIVATE_DATA)); + privateData=(PPRIVATE_DATA)(dev->ml_priv); + platformData=&(privateData->PlatformData); + + dwLanBase=Platform_Initialize( + platformData, + lan_base,bus_width); + + if(dwLanBase==0UL) { + SMSC_WARNING("dwLanBase==0x00000000"); + result=-ENODEV; + goto DONE; + } + platformInitialized=true; + SMSC_TRACE("dwLanBase=0x%08X",dwLanBase); + + if(check_mem_region(dwLanBase,LAN_REGISTER_EXTENT)!=0) { + SMSC_WARNING(" Memory Region specified (0x%08X to 0x%08X) is not available.", + dwLanBase,(u32)(dwLanBase+LAN_REGISTER_EXTENT-1UL)); + result=-ENOMEM; + goto DONE; + } + + privateData->dwLanBase=dwLanBase; + dwIdRev=Lan_GetRegDW(ID_REV); + if(HIWORD(dwIdRev)==LOWORD(dwIdRev)) { + //this may mean the chip is set for 32 bit + // while the bus is reading as 16 bit +UNKNOWN_CHIP: + SMSC_WARNING(" LAN9118 Family NOT Identified, dwIdRev==0x%08X",dwIdRev); + result=-ENODEV; + goto DONE; + } + switch(dwIdRev&0xFFFF0000UL) { + + case 0x93120000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 1UL: + SMSC_TRACE(" Hydra identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" Hydra identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + + case 0x01180000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9118 Beacon identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=0; + break; + case 1UL: + SMSC_TRACE(" LAN9118 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9118 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9118 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01170000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9117 Beacon identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=0; + break; + case 1UL: + SMSC_TRACE(" LAN9117 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9117 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9117 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01160000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + goto UNKNOWN_CHIP; + case 1UL: + SMSC_TRACE(" LAN9116 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9116 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9116 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01150000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + goto UNKNOWN_CHIP; + case 1UL: + SMSC_TRACE(" LAN9115 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9115 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9115 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x118A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9218 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9218 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x117A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9217 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9217 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x116A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9216 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9216 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x115A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9215 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9215 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + + case 0x92100000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9210 Boylston Lite identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9210 Boylston Lite identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x92110000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9211 Boylston Lite identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9211 Boylston Lite identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x215A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9215A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9215A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x216A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9216A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9216A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x217A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9217A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9217A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + + case 0x218A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9218A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9218A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + default: + //This is used for the new unkonw chip before we formally add them in the driver + if (id_reg==dwIdRev) { + if (Csum_Support) { + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + } else { + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + } + + SMSC_TRACE(" New Chip identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=5; + + } else { + + SMSC_WARNING("unknow chip, dwIdRev==0x%08X",dwIdRev); + + }; break; + + + } + + //printk("dwGeneration = %d\n", privateData->dwGeneration); + + dwFpgaRev=Lan_GetRegDW(FPGA_REV); + SMSC_TRACE(" FPGA_REV == 0x%08X",dwFpgaRev); + + + ether_setup(dev); + dev->open= Smsc9118_open; + dev->stop= Smsc9118_stop; + dev->hard_start_xmit= Smsc9118_hard_start_xmit; + dev->get_stats= Smsc9118_get_stats; + dev->do_ioctl= Smsc9118_do_ioctl; + dev->set_multicast_list=Smsc9118_set_multicast_list; + dev->flags|=IFF_MULTICAST; +#ifdef LINUX_2_6_OR_NEWER + /* + if (rx_mode==PROCESSING_MODE_NAPI) { + dev->poll=Smsc9118_rx_poll; + dev->weight=napi_weight; + } + */ +#endif + if(privateData->UseScatterGather) { + + if(privateData->UseTxCsum) + dev->features = (NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST); + else + dev->features = (NETIF_F_SG | NETIF_F_FRAGLIST); // Kernel will turn off SG in this case. + } + + else { + + if(privateData->UseTxCsum) + dev->features = (NETIF_F_HW_CSUM); + else + dev->features = 0; + } + + if(dev==NULL) { + SMSC_WARNING("Smsc9118_open(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_open(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + platformData=&(privateData->PlatformData); + + for (i = 0; i < GPT_SCHEDULE_DEPTH; i++) { + privateData->GptFunction [i] = NULL; + } + privateData->Gpt_scheduled_slot_index = GPT_SCHEDULE_DEPTH; + + //get memory region + if(check_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT)!=0) + { + SMSC_WARNING("Device memory is already in use."); + result=-ENOMEM; + goto DONE; + } + request_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT,"SMSC_LAN9118"); + acquired_mem_region=true; + + //initialize the LAN9118 + { + u32 dwIntCfg=0; + if(irq_pol) { + dwIntCfg|=INT_CFG_IRQ_POL_; + } + if(irq_type) { + dwIntCfg|=INT_CFG_IRQ_TYPE_; + } + if(!Lan_Initialize(privateData,dwIntCfg,tx_fif_sz,afc_cfg)) + { + SMSC_WARNING("Failed Lan_Initialize"); + result=-ENODEV; + goto DONE; + } + } + + if(!Platform_RequestIRQ(platformData,irq,Smsc9118_ISR,privateData)) { + result=-ENODEV; + goto DONE; + } + acquired_isr=true; + + //must now test the IRQ connection to the ISR + SMSC_TRACE("Testing ISR using IRQ %d",Platform_CurrentIRQ(platformData)); + { + u32 dwTimeOut=1000000; + Lan_SignalSoftwareInterrupt(privateData); + SMSC_TRACE("privateData=%08X", (u32)privateData); + do { + udelay(10); + dwTimeOut--; + } while((dwTimeOut)&&(!(privateData->SoftwareInterruptSignal))); + if(!(privateData->SoftwareInterruptSignal)) { + SMSC_WARNING("ISR failed signaling test"); + result=-ENODEV; + goto DONE; + } + } + SMSC_TRACE("ISR passed test using IRQ %d",Platform_CurrentIRQ(platformData)); + + if(!Mac_Initialize(privateData)) { + SMSC_WARNING("Failed Mac_Initialize"); + result=-ENODEV; + goto DONE; + } + {//get mac address + u32 dwHigh16=0; + u32 dwLow32=0; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(mac_addr_hi16==0xFFFFFFFF) { + dwHigh16=Mac_GetRegDW(privateData,ADDRH,keyCode); + dwLow32=Mac_GetRegDW(privateData,ADDRL,keyCode); + if((dwHigh16==0x0000FFFFUL)&&(dwLow32==0xFFFFFFFF)) + { + dwHigh16=0x00000070UL; + dwLow32=0x110F8000UL; + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + SMSC_TRACE("Mac Address is set by default to 0x%04X%08X", + dwHigh16,dwLow32); + } else { + SMSC_TRACE("Mac Address is read from LAN9118 as 0x%04X%08X", + dwHigh16,dwLow32); + } + } else { + //SMSC_ASSERT((mac_addr_hi16&0xFFFF8000UL)==0); + dwHigh16=mac_addr_hi16; + dwLow32=mac_addr_lo32; + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + SMSC_TRACE("Mac Address is set by parameter to 0x%04X%08X", + dwHigh16,dwLow32); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + dev->dev_addr[0]=LOBYTE(LOWORD(dwLow32)); + dev->dev_addr[1]=HIBYTE(LOWORD(dwLow32)); + dev->dev_addr[2]=LOBYTE(HIWORD(dwLow32)); + dev->dev_addr[3]=HIBYTE(HIWORD(dwLow32)); + dev->dev_addr[4]=LOBYTE(LOWORD(dwHigh16)); + dev->dev_addr[5]=HIBYTE(LOWORD(dwHigh16)); + } + + privateData->dwIdRev=dwIdRev; + privateData->dwFpgaRev=dwFpgaRev&(0x000000FFUL); + privateData->dev=dev; + + sprintf(privateData->ifName,"%s","eth1"); + SMSC_TRACE("privateData->ifName = %s\n", privateData->ifName); + result=0; + +DONE: + if(result!=0) { + if(dev!=NULL) { + if(dev->ml_priv!=NULL) { + if(platformInitialized) { + Platform_CleanUp(platformData); + } + kfree(dev->ml_priv); + dev->ml_priv=NULL; + } + } + } + SMSC_TRACE("<--Smsc9118_init(), result=%d",result); +} + +int Smsc9118_open(struct net_device *dev) +{ + int result=-ENODEV; + PPRIVATE_DATA privateData=NULL; + PPLATFORM_DATA platformData=NULL; + bool acquired_mem_region=false; + bool acquired_isr=false; + SMSC_TRACE("-->Smsc9118_open(dev=0x%08X)",(u32)dev); + if(dev==NULL) { + SMSC_WARNING("Smsc9118_open(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_open(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + platformData=&(privateData->PlatformData); + + privateData->MulticastUpdatePending = false; +#ifdef USE_PHY_WORK_AROUND + netif_carrier_off(dev); + if(!Phy_Initialize( + privateData, + phy_addr, + link_mode)) + { + SMSC_WARNING("Failed to initialize Phy"); + result=-ENODEV; + goto DONE; + } +#endif + + { + u32 dwRxDmaCh=rx_dma; + u32 dwTxDmaCh=tx_dma; + privateData->RxDmaChReserved=false; + + + if(rx_dma==TRANSFER_REQUEST_DMA) { + dwRxDmaCh=Platform_RequestDmaChannel(&(privateData->PlatformData)); + SMSC_ASSERT(dwRxDmaCh!=TRANSFER_REQUEST_DMA); + if(dwRxDmaChRxDmaChReserved=true; + } + } + privateData->TxDmaChReserved=false; + if(tx_dma==TRANSFER_REQUEST_DMA) { + dwTxDmaCh=Platform_RequestDmaChannel(&(privateData->PlatformData)); + SMSC_ASSERT(dwTxDmaCh!=TRANSFER_REQUEST_DMA); + if(dwTxDmaChTxDmaChReserved=true; + } + } + Tx_Initialize(privateData,dwTxDmaCh,dma_threshold); + Rx_Initialize(privateData,dwRxDmaCh,dma_threshold); + + } + +#ifndef LINUX_2_6_OR_NEWER + MOD_INC_USE_COUNT; +#endif + privateData->Running=true; + netif_start_queue(dev); + Tx_StopQueue(privateData,0x01UL); + + + spin_lock_init(&(privateData->GpTimerLock)); + Lan_EnableIRQ(privateData); + Lan_EnableInterrupt(privateData,INT_EN_GPT_INT_EN_); + +#ifndef USE_PHY_WORK_AROUND + netif_carrier_off(dev); + if(!Phy_Initialize( + privateData, + phy_addr, + link_mode)) + { + SMSC_WARNING("Failed to initialize Phy"); + result=-ENODEV; + goto DONE; + } +#endif + privateData->StopLinkPolling=false; + + result=0; + +DONE: + if(result!=0) { +#ifndef LINUX_2_6_OR_NEWER + MOD_DEC_USE_COUNT; +#endif + if(privateData!=NULL) { + if(privateData->TxDmaChReserved) { + Platform_ReleaseDmaChannel(platformData, + privateData->dwTxDmaCh); + privateData->TxDmaChReserved=false; + } + if(privateData->RxDmaChReserved) { + Platform_ReleaseDmaChannel(platformData, + privateData->dwRxDmaCh); + privateData->RxDmaChReserved=false; + } + if(acquired_isr) { + Platform_FreeIRQ(platformData); + } + if(acquired_mem_region) { + release_mem_region( + privateData->dwLanBase, + LAN_REGISTER_EXTENT); + } + } + } + SMSC_TRACE("<--Smsc9118_open, result=%d",result); + return result; +} + +int Smsc9118_stop(struct net_device *dev) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + SMSC_TRACE("-->Smsc9118_stop(dev=0x%08X)",(u32)dev); + if(dev==NULL) { + SMSC_WARNING("Smsc9118_stop(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_stop(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + + privateData->StopLinkPolling=true; + + Rx_ReceiverOff(privateData); + del_timer_sync(&(privateData->LinkPollingTimer)); + + Lan_DisableInterrupt(privateData,INT_EN_GPT_INT_EN_); + + Tx_UpdateTxCounters(privateData); + privateData->Running=false; + Lan_DisableIRQ(privateData); + + Tx_CompleteDma(privateData); + + Tx_StopQueue(privateData,0x01UL); + +#ifndef LINUX_2_6_OR_NEWER + MOD_DEC_USE_COUNT; +#endif + + if(privateData->TxDmaChReserved) { + Platform_ReleaseDmaChannel( + &(privateData->PlatformData), + privateData->dwTxDmaCh); + privateData->TxDmaChReserved=false; + } + if(privateData->RxDmaChReserved) { + Platform_ReleaseDmaChannel( + &(privateData->PlatformData), + privateData->dwRxDmaCh); + privateData->RxDmaChReserved=false; + } + +#if 0 + Platform_FreeIRQ(&(privateData->PlatformData)); + release_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT); + + { + const u32 dwLanBase=privateData->dwLanBase; + const u32 dwIdRev=privateData->dwIdRev; + const u32 dwFpgaRev=privateData->dwFpgaRev; + struct net_device * const tempDev=privateData->dev; + char ifName[SMSC_IF_NAME_SIZE]; + PLATFORM_DATA platformDataBackup; + memcpy(ifName,privateData->ifName,SMSC_IF_NAME_SIZE); + memcpy(&platformDataBackup,&(privateData->PlatformData),sizeof(PLATFORM_DATA)); + + memset(privateData,0,sizeof(PRIVATE_DATA)); + + privateData->dwLanBase=dwLanBase; + privateData->dwIdRev=dwIdRev; + privateData->dwFpgaRev=dwFpgaRev; + privateData->dev=tempDev; + memcpy(privateData->ifName,ifName,SMSC_IF_NAME_SIZE); + memcpy(&(privateData->PlatformData),&platformDataBackup,sizeof(PLATFORM_DATA)); + } +#endif + +DONE: + SMSC_TRACE("<--Smsc9118_stop, result=%d",result); + return result; +} + +int Smsc9118_hard_start_xmit( + struct sk_buff *skb, struct net_device * const dev) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + //SMSC_TRACE("-->Smsc9118_hard_start_xmit(skb=0x%08X,dev=0x%08X)",(u32)skb,(u32)dev); + if(skb==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(skb==NULL)"); + result=-EFAULT; + goto DONE; + } + if(dev==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + if(dev->ml_priv==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(dev->ml_priv==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + // SET_GPIO(GP_TX); + + Tx_SendSkb(privateData,skb); + + // CLEAR_GPIO(GP_TX); +DONE: + //SMSC_TRACE("<--Smsc9118_hard_start_xmit, result=%d",result); + return result; +} + +struct net_device_stats * Smsc9118_get_stats(struct net_device * const dev) +{ + PPRIVATE_DATA privateData=NULL; + if(dev==NULL) { + SMSC_WARNING("Smsc9118_get_stats(dev==NULL)"); + return NULL; + } + if(dev->ml_priv==NULL) { + // SMSC_WARNING("Smsc9118_get_stats(dev->ml_priv==NULL)"); + return NULL; + } + + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData->Running) { + privateData->stats.rx_dropped+=Lan_GetRegDW(RX_DROP); + Tx_UpdateTxCounters(privateData); + } + return &(privateData->stats); +} + +void Smsc9118_set_multicast_list(struct net_device *dev) +{ + SMSC_ASSERT(dev!=NULL); + Rx_SetMulticastList(dev); +} + + +int Smsc9118_do_ioctl( + struct net_device *dev, + struct ifreq *ifr, + int cmd) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + void *userAddr=NULL; + + // bool success=false; + + SMSC_TRACE("-->Smsc9118_do_ioctl"); + SMSC_TRACE("cmd=%d,SIOCGMIIPHY=%d,SIOCDEVPRIVATE=%d", + cmd,SIOCGMIIPHY,SIOCDEVPRIVATE); + + + if(dev==NULL) { + SMSC_WARNING("dev==NULL"); + result=-EFAULT; + goto DONE; + } + if(dev->ml_priv==NULL) { + SMSC_WARNING("dev->ml_priv==NULL"); + result=-EFAULT; + goto DONE; + } + privateData=((PPRIVATE_DATA)dev->ml_priv); + if(ifr==NULL) { + SMSC_WARNING("ifr==NULL"); + result=-EFAULT; + goto DONE; + } + userAddr=ifr->ifr_data; + + + if(privateData->LanInitialized) { + // standard MII IOC's + struct mii_ioctl_data * const data= + (struct mii_ioctl_data *) & ifr->ifr_data; + switch(cmd) { + case SIOCGMIIPHY: + + case SIOCDEVPRIVATE: + data->phy_id=1; + SMSC_TRACE("SIOCGMIIPHY: phy_id set to 0x%04X",data->phy_id); + break; + case SIOCGMIIREG: + case SIOCDEVPRIVATE+1: + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + data->val_out=Phy_GetRegW( + privateData,data->reg_num,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + SMSC_TRACE("SIOCGMIIREG: phy_id=0x%04X, reg_num=0x%04X, val_out set to 0x%04X", + data->phy_id,data->reg_num,data->val_out); + break; + case SIOCSMIIREG: + case SIOCDEVPRIVATE+2: + SMSC_TRACE("SIOCSMIIREG: phy_id=0x%04X, reg_num=0x%04X, val_in=0x%04X", + data->phy_id,data->reg_num,data->val_in); + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW( + privateData,data->reg_num,((WORD)(data->val_in)),keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + break; + + case SIOCETHTOOL: + result=Smsc9118_ethtool_ioctl(privateData,userAddr); + break; + case SMSC9118_IOCTL: + result=Smsc9118_private_ioctl(privateData,userAddr); + break; + + default: + result=-EOPNOTSUPP; + break;//make lint happy + } + } + +DONE: + + return result; +} + + + +int Smsc9118_private_ioctl(PPRIVATE_DATA privateData,void *useraddr) +{ + + + bool success=false; + int result=-EFAULT; + SMSC9118_IOCTL_DATA ioctlData; + + if(useraddr==NULL) { + SMSC_WARNING("useraddr==NULL"); + result=-EFAULT; + goto DONE; + } + + if(copy_from_user(&ioctlData,useraddr,sizeof(ioctlData))) { + SMSC_WARNING("copy_from_user failed"); + result=-EFAULT; + goto DONE; + } + + if(ioctlData.dwSignature!=SMSC9118_APP_SIGNATURE) { + SMSC_WARNING("invalid application signature"); + result=-EFAULT; + goto DONE; + } + + switch(ioctlData.dwCommand) { + case COMMAND_GET_SIGNATURE: + success=true; + break; + case COMMAND_GET_FLOW_PARAMS: + ioctlData.Data[0]=privateData->RxFlowMeasuredMaxThroughput; + ioctlData.Data[1]=privateData->RxFlowMeasuredMaxPacketCount; + ioctlData.Data[2]=privateData->RxFlowParameters.MaxThroughput; + ioctlData.Data[3]=privateData->RxFlowParameters.MaxPacketCount; + ioctlData.Data[4]=privateData->RxFlowParameters.PacketCost; + ioctlData.Data[5]=privateData->RxFlowParameters.BurstPeriod; + ioctlData.Data[6]=privateData->RxFlowMaxWorkLoad; + ioctlData.Data[7]=Lan_GetRegDW(INT_CFG)>>24; + privateData->RxFlowMeasuredMaxThroughput=0; + privateData->RxFlowMeasuredMaxPacketCount=0; + success=true; + break; + case COMMAND_SET_FLOW_PARAMS: + if(!(privateData->RxFlowControlActive)) { + privateData->RxFlowParameters.MaxThroughput=ioctlData.Data[2]; + privateData->RxFlowParameters.MaxPacketCount=ioctlData.Data[3]; + privateData->RxFlowParameters.PacketCost=ioctlData.Data[4]; + privateData->RxFlowParameters.BurstPeriod=ioctlData.Data[5]; + if(ioctlData.Data[6]==0xFFFFFFFFUL) { + privateData->RxFlowMaxWorkLoad= + privateData->RxFlowParameters.MaxThroughput+ + (privateData->RxFlowParameters.MaxPacketCount* + privateData->RxFlowParameters.PacketCost); + } else { + privateData->RxFlowMaxWorkLoad=ioctlData.Data[6]; + } + Lan_SetIntDeas(privateData,ioctlData.Data[7]); + privateData->RxFlowBurstMaxWorkLoad= + (privateData->RxFlowMaxWorkLoad* + privateData->RxFlowParameters.BurstPeriod)/1000; + success=true; + };break; + case COMMAND_GET_CONFIGURATION: + ioctlData.Data[0]=DRIVER_VERSION; + ioctlData.Data[1]=lan_base; + ioctlData.Data[2]=bus_width; + ioctlData.Data[3]=link_mode; + ioctlData.Data[4]=irq; + ioctlData.Data[5]=int_deas; + ioctlData.Data[6]=irq_pol; + ioctlData.Data[7]=irq_type; + ioctlData.Data[8]=rx_dma; + ioctlData.Data[9]=tx_dma; + ioctlData.Data[10]=dma_threshold; + ioctlData.Data[11]=mac_addr_hi16; + ioctlData.Data[12]=mac_addr_lo32; + ioctlData.Data[13]=debug_mode; + ioctlData.Data[14]=tx_fif_sz; + ioctlData.Data[15]=afc_cfg; + ioctlData.Data[16]=rx_mode; + ioctlData.Data[17]=max_throughput; + ioctlData.Data[18]=max_packet_count; + ioctlData.Data[19]=packet_cost; + ioctlData.Data[20]=burst_period; + ioctlData.Data[21]=max_work_load; + ioctlData.Data[22]=privateData->dwIdRev; + ioctlData.Data[23]=privateData->dwFpgaRev; + ioctlData.Data[24]=1; + ioctlData.Data[25]=privateData->dwPhyId; + ioctlData.Data[26]=privateData->bPhyModel; + ioctlData.Data[27]=privateData->bPhyRev; + ioctlData.Data[28]=privateData->dwLinkSpeed; + ioctlData.Data[29]=privateData->RxFlowMeasuredMaxThroughput; + ioctlData.Data[30]=privateData->RxFlowMeasuredMaxPacketCount; + ioctlData.Data[31]=privateData->RxFlowParameters.MaxThroughput; + ioctlData.Data[32]=privateData->RxFlowParameters.MaxPacketCount; + ioctlData.Data[33]=privateData->RxFlowParameters.PacketCost; + ioctlData.Data[34]=privateData->RxFlowParameters.BurstPeriod; + ioctlData.Data[35]=privateData->RxFlowMaxWorkLoad; + sprintf(ioctlData.Strng1,"%s, %s",__DATE__,__TIME__); + sprintf(ioctlData.Strng2,"%s",privateData->ifName); + privateData->RxFlowMeasuredMaxThroughput=0; + privateData->RxFlowMeasuredMaxPacketCount=0; + success=true; + break; + case COMMAND_LAN_GET_REG: + if((ioctlData.Data[0]dwLanBase+ + ioctlData.Data[0]))); + success=true; + } else { + SMSC_WARNING("Reading LAN9118 Mem Map Failed"); + goto MEM_MAP_ACCESS_FAILED; + } + break; + case COMMAND_LAN_SET_REG: + if((ioctlData.Data[0]dwLanBase+ + ioctlData.Data[0])))=ioctlData.Data[1]; + success=true; + } else { + SMSC_WARNING("Reading LAN9118 Mem Map Failed"); +MEM_MAP_ACCESS_FAILED: + SMSC_WARNING(" Invalid offset == 0x%08X",(u32)(ioctlData.Data[0])); + if(ioctlData.Data[0]>=LAN_REGISTER_EXTENT) { + SMSC_WARNING(" Out of range"); + } + if(ioctlData.Data[0]&0x3UL) { + SMSC_WARNING(" Not u32 aligned"); + } + } + break; + case COMMAND_MAC_GET_REG: + if((ioctlData.Data[0]<=0xC)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[1]= + Mac_GetRegDW(privateData,ioctlData.Data[0],keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Reading Mac Register Failed"); + goto MAC_ACCESS_FAILURE; + } + break; + case COMMAND_MAC_SET_REG: + if((ioctlData.Data[0]<=0xC)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW( + privateData, + ioctlData.Data[0], + ioctlData.Data[1], + keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Writing Mac Register Failed"); +MAC_ACCESS_FAILURE: + if(!(privateData->LanInitialized)) { + + SMSC_WARNING(" LAN Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + if(!(ioctlData.Data[0]<=0xC)) { + SMSC_WARNING(" Invalid index == 0x%08X",(u32)(ioctlData.Data[0])); + } + } + break; + case COMMAND_PHY_GET_REG: + if((ioctlData.Data[0]<32)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[1]=((u32) + Phy_GetRegW(privateData,ioctlData.Data[0],keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Reading Phy Register Failed"); + goto PHY_ACCESS_FAILURE; + } + break; + case COMMAND_PHY_SET_REG: + if((ioctlData.Data[0]<32)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW( + privateData, + ioctlData.Data[0], + ((WORD)(ioctlData.Data[1])), + keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Writing Phy Register Failed"); +PHY_ACCESS_FAILURE: + if(!(privateData->LanInitialized)) { + SMSC_WARNING(" Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + if(!(ioctlData.Data[0]<32)) { + SMSC_WARNING(" Invalid index == 0x%d",(u32)(ioctlData.Data[0])); + } + } + break; + // case COMMAND_DUMP_TEMP: + // { + // u32 c=0; + // for(c=0;c<0x40;c++) + // ioctlData.Data[c]=privateData->temp[c]; + // } + // success=true; + // break; + case COMMAND_DUMP_LAN_REGS: + ioctlData.Data[LAN_REG_ID_REV]=Lan_GetRegDW(ID_REV); + ioctlData.Data[LAN_REG_INT_CFG]=Lan_GetRegDW(INT_CFG); + ioctlData.Data[LAN_REG_INT_STS]=Lan_GetRegDW(INT_STS); + ioctlData.Data[LAN_REG_INT_EN]=Lan_GetRegDW(INT_EN); + ioctlData.Data[LAN_REG_BYTE_TEST]=Lan_GetRegDW(BYTE_TEST); + ioctlData.Data[LAN_REG_FIFO_INT]=Lan_GetRegDW(FIFO_INT); + ioctlData.Data[LAN_REG_RX_CFG]=Lan_GetRegDW(RX_CFG); + ioctlData.Data[LAN_REG_TX_CFG]=Lan_GetRegDW(TX_CFG); + ioctlData.Data[LAN_REG_HW_CFG]=Lan_GetRegDW(HW_CFG); + ioctlData.Data[LAN_REG_RX_DP_CTRL]=Lan_GetRegDW(RX_DP_CTRL); + ioctlData.Data[LAN_REG_RX_FIFO_INF]=Lan_GetRegDW(RX_FIFO_INF); + ioctlData.Data[LAN_REG_TX_FIFO_INF]=Lan_GetRegDW(TX_FIFO_INF); + ioctlData.Data[LAN_REG_PMT_CTRL]=Lan_GetRegDW(PMT_CTRL); + ioctlData.Data[LAN_REG_GPIO_CFG]=Lan_GetRegDW(GPIO_CFG); + ioctlData.Data[LAN_REG_GPT_CFG]=Lan_GetRegDW(GPT_CFG); + ioctlData.Data[LAN_REG_GPT_CNT]=Lan_GetRegDW(GPT_CNT); + ioctlData.Data[LAN_REG_FPGA_REV]=Lan_GetRegDW(FPGA_REV); + ioctlData.Data[LAN_REG_WORD_SWAP]=Lan_GetRegDW(WORD_SWAP); + ioctlData.Data[LAN_REG_FREE_RUN]=Lan_GetRegDW(FREE_RUN); + ioctlData.Data[LAN_REG_RX_DROP]=Lan_GetRegDW(RX_DROP); + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[LAN_REG_MAC_CSR_CMD]=Lan_GetRegDW(MAC_CSR_CMD); + ioctlData.Data[LAN_REG_MAC_CSR_DATA]=Lan_GetRegDW(MAC_CSR_DATA); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } else { + ioctlData.Data[LAN_REG_MAC_CSR_CMD]=Lan_GetRegDW(MAC_CSR_CMD); + ioctlData.Data[LAN_REG_MAC_CSR_DATA]=Lan_GetRegDW(MAC_CSR_DATA); + } + ioctlData.Data[LAN_REG_AFC_CFG]=Lan_GetRegDW(AFC_CFG); + ioctlData.Data[LAN_REG_E2P_CMD]=Lan_GetRegDW(E2P_CMD); + ioctlData.Data[LAN_REG_E2P_DATA]=Lan_GetRegDW(E2P_DATA); + success=true; + break; + case COMMAND_DUMP_MAC_REGS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[MAC_REG_MAC_CR]=Mac_GetRegDW(privateData,MAC_CR,keyCode); + ioctlData.Data[MAC_REG_ADDRH]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[MAC_REG_ADDRL]=Mac_GetRegDW(privateData,ADDRL,keyCode); + ioctlData.Data[MAC_REG_HASHH]=Mac_GetRegDW(privateData,HASHH,keyCode); + ioctlData.Data[MAC_REG_HASHL]=Mac_GetRegDW(privateData,HASHL,keyCode); + ioctlData.Data[MAC_REG_MII_ACC]=Mac_GetRegDW(privateData,MII_ACC,keyCode); + ioctlData.Data[MAC_REG_MII_DATA]=Mac_GetRegDW(privateData,MII_DATA,keyCode); + ioctlData.Data[MAC_REG_FLOW]=Mac_GetRegDW(privateData,FLOW,keyCode); + ioctlData.Data[MAC_REG_VLAN1]=Mac_GetRegDW(privateData,VLAN1,keyCode); + ioctlData.Data[MAC_REG_VLAN2]=Mac_GetRegDW(privateData,VLAN2,keyCode); + ioctlData.Data[MAC_REG_WUFF]=Mac_GetRegDW(privateData,WUFF,keyCode); + ioctlData.Data[MAC_REG_WUCSR]=Mac_GetRegDW(privateData,WUCSR,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Mac Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + case COMMAND_DUMP_PHY_REGS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[PHY_REG_0]=Phy_GetRegW(privateData,0,keyCode); + ioctlData.Data[PHY_REG_1]=Phy_GetRegW(privateData,1,keyCode); + ioctlData.Data[PHY_REG_2]=Phy_GetRegW(privateData,2,keyCode); + ioctlData.Data[PHY_REG_3]=Phy_GetRegW(privateData,3,keyCode); + ioctlData.Data[PHY_REG_4]=Phy_GetRegW(privateData,4,keyCode); + ioctlData.Data[PHY_REG_5]=Phy_GetRegW(privateData,5,keyCode); + ioctlData.Data[PHY_REG_6]=Phy_GetRegW(privateData,6,keyCode); + ioctlData.Data[PHY_REG_16]=Phy_GetRegW(privateData,16,keyCode); + ioctlData.Data[PHY_REG_17]=Phy_GetRegW(privateData,17,keyCode); + ioctlData.Data[PHY_REG_18]=Phy_GetRegW(privateData,18,keyCode); + ioctlData.Data[PHY_REG_20]=Phy_GetRegW(privateData,20,keyCode); + ioctlData.Data[PHY_REG_21]=Phy_GetRegW(privateData,21,keyCode); + ioctlData.Data[PHY_REG_22]=Phy_GetRegW(privateData,22,keyCode); + ioctlData.Data[PHY_REG_23]=Phy_GetRegW(privateData,23,keyCode); + ioctlData.Data[PHY_REG_27]=Phy_GetRegW(privateData,27,keyCode); + ioctlData.Data[PHY_REG_28]=Phy_GetRegW(privateData,28,keyCode); + ioctlData.Data[PHY_REG_29]=Phy_GetRegW(privateData,29,keyCode); + ioctlData.Data[PHY_REG_30]=Phy_GetRegW(privateData,30,keyCode); + ioctlData.Data[PHY_REG_31]=Phy_GetRegW(privateData,31,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Phy Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + case COMMAND_DUMP_EEPROM: + { + BYTE data=0; + BYTE index=0; + Eeprom_EnableAccess(privateData); + success=true; + for(index=0;index<8;index++) { + if(Eeprom_ReadLocation(privateData,index,&data)) { + ioctlData.Data[index]=(u32)data; + } else { + success=false; + break; + } + } + Eeprom_DisableAccess(privateData); + };break; + case COMMAND_GET_MAC_ADDRESS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[0]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[1]=Mac_GetRegDW(privateData,ADDRL,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + + case COMMAND_SET_MAC_ADDRESS: + if(privateData->LanInitialized) + { + u32 dwLow32=ioctlData.Data[1]; + u32 dwHigh16=ioctlData.Data[0]; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_LOAD_MAC_ADDRESS: + if(privateData->LanInitialized) { + Eeprom_EnableAccess(privateData); + if(Eeprom_Reload(privateData)) { + if(Eeprom_IsMacAddressLoaded(privateData)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[0]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[1]=Mac_GetRegDW(privateData,ADDRL,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Failed to Load Mac Address(1)"); + } + } else { + SMSC_WARNING("Failed to Load Mac Address(2)"); + } + Eeprom_DisableAccess(privateData); + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_SAVE_MAC_ADDRESS: + if(privateData->LanInitialized) { + if(Eeprom_SaveMacAddress(privateData, + ioctlData.Data[0],ioctlData.Data[1])) { + success=true; + } + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_SET_DEBUG_MODE: + debug_mode=ioctlData.Data[0]; + if(debug_mode&0x04UL) { + if(OLD_REGISTERS(privateData)) + { + g_GpioSetting=0x00270700UL; + } else { + g_GpioSetting=0x00670700UL; + } + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } else { + Lan_SetRegDW(GPIO_CFG,0x70070000); + } + success=true; + break; + case COMMAND_SET_LINK_MODE: + link_mode=(ioctlData.Data[0]&0x7FUL); + if(privateData->LanInitialized) { + Phy_SetLink(privateData,link_mode); + } + success=true; + break; + case COMMAND_GET_LINK_MODE: + ioctlData.Data[0]=link_mode; + success=true; + break; + case COMMAND_CHECK_LINK: + Phy_UpdateLinkMode(privateData); + success=true; + break; + case COMMAND_READ_BYTE: + ioctlData.Data[1]=(*((volatile BYTE *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_READ_WORD: + ioctlData.Data[1]=(*((volatile WORD *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_READ_DWORD: + ioctlData.Data[1]=(*((volatile u32 *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_WRITE_BYTE: + (*((volatile BYTE *)(ioctlData.Data[0])))= + ((BYTE)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_WRITE_WORD: + (*((volatile WORD *)(ioctlData.Data[0])))= + ((WORD)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_WRITE_DWORD: + (*((volatile u32 *)(ioctlData.Data[0])))= + ((u32)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_SET_AMDIX_STS: + AutoMdix=(ioctlData.Data[0]); + if(privateData->LanInitialized) { + Phy_SetAutoMdixSts(privateData,AutoMdix); + } + success=true; + break; + case COMMAND_GET_AMDIX_STS: + ioctlData.Data[0]=AutoMdix; + if(privateData->LanInitialized) { + Phy_GetAutoMdixSts(privateData); + } + success=true; + break; + + default:return -EOPNOTSUPP; + } + +DONE: + if(success) { + ioctlData.dwSignature=SMSC9118_DRIVER_SIGNATURE; + if(copy_to_user(useraddr, &ioctlData, sizeof(ioctlData))) { + SMSC_WARNING("copy_to_user failed"); + result=-EFAULT; + } + result=0; + } + // SMSC_TRACE("<--Smsc9118_do_ioctl"); + return result; + +} + + + +int Smsc9118_ethtool_ioctl(PPRIVATE_DATA privateData, void * userAddr) +{ + int result=-EFAULT; + u32 ethcmd=0; + if(copy_from_user(ðcmd,userAddr,sizeof(ethcmd))) + { + result=-EFAULT; + goto DONE; + } + switch(ethcmd) { + case ETHTOOL_GSET:// Get settings. + // SMSC_TRACE("ETHTOOL_GSET"); + { + struct ethtool_cmd settings={ETHTOOL_GSET}; + settings.supported= + SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_MII; + settings.advertising=ADVERTISED_MII; + if(privateData->dwLinkSettings & LINK_SPEED_10HD) + settings.advertising|=ADVERTISED_10baseT_Half; + if(privateData->dwLinkSettings & LINK_SPEED_10FD) + settings.advertising|=ADVERTISED_10baseT_Full; + if(privateData->dwLinkSettings & LINK_SPEED_100HD) + settings.advertising|=ADVERTISED_100baseT_Half; + if(privateData->dwLinkSettings & LINK_SPEED_100FD) + settings.advertising|=ADVERTISED_100baseT_Full; + if(privateData->dwLinkSettings & LINK_AUTO_NEGOTIATE) { + settings.advertising|=ADVERTISED_Autoneg; + settings.autoneg=AUTONEG_ENABLE; + } else settings.autoneg=AUTONEG_DISABLE; + if(privateData->dwLinkSpeed & (LINK_SPEED_100HD|LINK_SPEED_100FD)) + settings.speed=SPEED_100; + else settings.speed=SPEED_10; + if(privateData->dwLinkSpeed & (LINK_SPEED_10FD|LINK_SPEED_100FD)) + settings.duplex=DUPLEX_FULL; + else settings.duplex=DUPLEX_HALF; + settings.port=PORT_MII; + settings.phy_address=(u8)privateData->dwPhyAddress; + settings.transceiver=XCVR_INTERNAL; + settings.maxtxpkt=0; + settings.maxrxpkt=0; + if(copy_to_user(userAddr,&settings,sizeof(settings))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SSET:// Set settings. + // SMSC_TRACE("ETHTOOL_SSET"); + { + struct ethtool_cmd settings; + u16 speed=0; + u8 duplex=0; + u8 autoneg=0; + if(copy_from_user(&settings,userAddr,sizeof(settings))) { + result=-EFAULT; + goto DONE; + } + if(privateData->dwLinkSettings&LINK_AUTO_NEGOTIATE) { + autoneg=AUTONEG_ENABLE; + } else { + autoneg=AUTONEG_DISABLE; + } + if(privateData->dwLinkSpeed&(LINK_SPEED_100HD|LINK_SPEED_100FD)) + { + speed=SPEED_100; + } else { + speed=SPEED_10; + } + if(privateData->dwLinkSpeed&(LINK_SPEED_10FD|LINK_SPEED_100FD)) + { + duplex=DUPLEX_FULL; + } else { + duplex=DUPLEX_HALF; + } + if((settings.speed!=100)&&(settings.speed!=10)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.duplex!=DUPLEX_FULL)&&(settings.duplex!=DUPLEX_HALF)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.autoneg!=AUTONEG_ENABLE)&&(settings.autoneg!=AUTONEG_DISABLE)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.autoneg!=autoneg)|| + (settings.speed!=speed)|| + (settings.duplex!=duplex)) + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(settings.autoneg==AUTONEG_ENABLE) { + + + + WORD wAdvertisement=Phy_GetRegW(privateData,PHY_ANEG_ADV,keyCode); + wAdvertisement&=(~PHY_ANEG_ADV_SPEED_); + if(settings.speed==SPEED_100) { + if(settings.duplex==DUPLEX_FULL) { + wAdvertisement|=PHY_ANEG_ADV_100F_; + } else { + wAdvertisement|=PHY_ANEG_ADV_100H_; + } + } else { + if(settings.duplex==DUPLEX_FULL) { + wAdvertisement|=PHY_ANEG_ADV_10F_; + } else { + wAdvertisement|=PHY_ANEG_ADV_10H_; + } + } + + + + Phy_SetRegW(privateData,PHY_ANEG_ADV,wAdvertisement,keyCode); + Phy_SetRegW(privateData,PHY_BCR, + (PHY_BCR_AUTO_NEG_ENABLE_|PHY_BCR_RESTART_AUTO_NEG_),keyCode); + + + } else { + WORD wBcr=Phy_GetRegW(privateData,PHY_BCR,keyCode); + if(settings.speed==SPEED_100) { + wBcr|=PHY_BCR_SPEED_SELECT_; + } else { + wBcr&=(~PHY_BCR_SPEED_SELECT_); + } + if(settings.duplex==DUPLEX_FULL) { + wBcr|=PHY_BCR_DUPLEX_MODE_; + } else { + wBcr&=(~PHY_BCR_DUPLEX_MODE_); + } + Phy_SetRegW(privateData,PHY_BCR,wBcr,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + result=0; + } + break; + case ETHTOOL_GDRVINFO:// Get driver info. + // SMSC_TRACE("ETHTOOL_GDRVINFO"); + { + struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO}; + strcpy(info.driver,"Smsc9131_eth"); + memset(&info.version,0,sizeof(info.version)); + memset(&info.fw_version,0,sizeof(info.fw_version)); + sprintf(info.fw_version,"%u",(privateData->dwIdRev)&0xFFFF); + memset(&info.bus_info,0,sizeof(info.bus_info)); + memset(&info.reserved1,0,sizeof(info.reserved1)); + memset(&info.reserved2,0,sizeof(info.reserved2)); +#ifdef LINUX_2_6_OR_NEWER + info.n_stats=0; + info.testinfo_len=0; +#endif + info.eedump_len=0; + info.regdump_len=0; + if(copy_to_user(userAddr,&info,sizeof(info))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_GREGS:// Get NIC registers. + // SMSC_TRACE("ETHTOOL_GREGS"); + result=-EOPNOTSUPP; + break; + /* + case ETHTOOL_GWOL:// Get wake-on-lan options. + SMSC_TRACE("ETHTOOL_GWOL"); + { + struct ethtool_wolinfo wol_info={ETHTOOL_GWOL}; + //wol_info.supported=true; + wol_info.supported=(WAKE_PHY | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_MAGIC); + wol_info.wolopts= privateData->WolWakeupOpts; + memset(&wol_info.sopass,0,sizeof(wol_info.sopass)); + if(copy_to_user(userAddr,&wol_info,sizeof(wol_info))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SWOL:// Set wake-on-lan options. + SMSC_TRACE("ETHTOOL_SWOL"); + { + unsigned long dwIntFlags=0; + struct ethtool_wolinfo wol_info; + if(copy_from_user(&wol_info,userAddr,sizeof(wol_info))) + { + result=-EFAULT; + } else { + SMSC_TRACE(DBG_IOCTL,"WOL OPTS = 0x%x", wol_info.wolopts); + spin_lock_irqsave(&(privateData->PhyLock),dwIntFlags); + privateData->WolWakeupOpts = wol_info.wolopts; + spin_unlock_irqrestore(&(privateData->PhyLock),dwIntFlags); + result=0; + } + } + break; + */ + case ETHTOOL_GMSGLVL:// Get driver message level + // SMSC_TRACE("ETHTOOL_GMSGLVL"); + { + struct ethtool_value msgLevel={ETHTOOL_GMSGLVL}; + msgLevel.data=debug_mode; + if(copy_to_user(userAddr, &msgLevel,sizeof(msgLevel))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SMSGLVL:// Set driver msg level. + // SMSC_TRACE("ETHTOOL_SMSGLVL"); + { + struct ethtool_value msgLevel; + if(copy_from_user(&msgLevel,userAddr,sizeof(msgLevel))) + { + result=-EFAULT; + } else { + debug_mode=msgLevel.data; + result=0; + } + } + break; + case ETHTOOL_NWAY_RST:// Restart autonegotiation. + // SMSC_TRACE("ETHTOOL_NWAY_RST"); + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW(privateData,PHY_BCR, + (PHY_BCR_AUTO_NEG_ENABLE_|PHY_BCR_RESTART_AUTO_NEG_),keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + result=0; + } + break; + case ETHTOOL_GLINK:// Get link status (ethtool_value) + // SMSC_TRACE("ETHTOOL_GLINK"); + { + struct ethtool_value linkStatus={ETHTOOL_GLINK}; + if(privateData->dwLinkSpeed!=LINK_OFF) { + linkStatus.data=1; + } else { + linkStatus.data=0; + } + if(copy_to_user(userAddr,&linkStatus,sizeof(linkStatus))) + { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_GEEPROM:// Get EEPROM data + // SMSC_TRACE("ETHTOOL_GEEPROM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SEEPROM:// Set EEPROM data. + // SMSC_TRACE("ETHTOOL_SEEPROM"); + result=-EOPNOTSUPP; + break; + +#ifdef LINUX_2_6_OR_NEWER + + case ETHTOOL_GCOALESCE:// Get coalesce config + // SMSC_TRACE("ETHTOOL_GCOALESCE"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SCOALESCE:// Set coalesce config. + // SMSC_TRACE("ETHTOOL_SCOALESCE"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GRINGPARAM:// Get ring parameters + // SMSC_TRACE("ETHTOOL_GRINGPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SRINGPARAM:// Set ring parameters. + // SMSC_TRACE("ETHTOOL_SRINGPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GPAUSEPARAM:// Get pause parameters + // SMSC_TRACE("ETHTOOL_GPAUSEPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SPAUSEPARAM:// Set pause parameters. + // SMSC_TRACE("ETHTOOL_SPAUSEPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GRXCSUM:// Get RX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GRXCSUM"); + { + struct ethtool_value rxCsum={ETHTOOL_GRXCSUM}; + rxCsum.data=0; + if(copy_to_user(userAddr,&rxCsum,sizeof(rxCsum))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SRXCSUM:// Set RX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_SRXCSUM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GTXCSUM:// Get TX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GTXCSUM"); + { + struct ethtool_value txCsum={ETHTOOL_GTXCSUM}; + txCsum.data=0; + if(copy_to_user(userAddr,&txCsum,sizeof(txCsum))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_STXCSUM:// Set TX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_STXCSUM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSG:// Get scatter-gather enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GSG"); + { + struct ethtool_value sg={ETHTOOL_GSG}; + sg.data=0; + if(copy_to_user(userAddr,&sg,sizeof(sg))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SSG:// Set scatter-gather enable (ethtool_value). + // SMSC_TRACE("ETHTOOL_SSG"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_TEST:// execute NIC self-test. + // SMSC_TRACE("ETHTOOL_TEST"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSTRINGS:// get specified string set + // SMSC_TRACE("ETHTOOL_GSTRINGS"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_PHYS_ID:// identify the NIC + // SMSC_TRACE("ETHTOOL_PHYS_ID"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSTATS:// get NIC-specific statistics + // SMSC_TRACE("ETHTOOL_GSTATS"); + result=-EOPNOTSUPP; + break; + + case ETHTOOL_GTSO:// Get TSO enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GTSO"); + { + struct ethtool_value tso={ETHTOOL_GTSO}; + tso.data=0; + if(copy_to_user(userAddr,&tso,sizeof(tso))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_STSO:// Set TSO enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_STS0"); + result=-EOPNOTSUPP; + break; +#endif + default: + // SMSC_WARNING("unknown ethcmd=0x%08X",ethcmd); + result=-EOPNOTSUPP; + break; + } +DONE: + return result; +} + + +//returns time1-time2; +TIME_SPAN Gpt_FreeRunCompare(u32 time1,u32 time2) +{ + return ((TIME_SPAN)(time1-time2)); +} +void Gpt_ScheduleInterrupt(PPRIVATE_DATA privateData,TIME_SPAN timeSpan) +{ + u32 timerValue=0; + if(timeSpan<0) timeSpan=0; + timerValue=(u32)timeSpan; + if((timerValue%2500)>=1250) { + timerValue=(timerValue/2500)+1; + } else { + timerValue=(timerValue/2500); + } + if(timerValue>0x0000FFFFUL) { + timerValue=0x0000FFFF; + } + Lan_SetRegDW(GPT_CFG,(timerValue|GPT_CFG_TIMER_EN_)); + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); +} + +void Gpt_CancelInterrupt(PPRIVATE_DATA privateData) +{ + Lan_SetRegDW(GPT_CFG,0UL); + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); +} + +void Gpt_ScheduleCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData), + u32 callBackTime) +{ + u32 slot_index=GPT_SCHEDULE_DEPTH; + bool result=false; + if((callBackFunction!=NULL)&&(callBackTime!=0)) { + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock_irqsave(&privateData->GpTimerLock,dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + TIME_SPAN timeSpan=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]==NULL) { + if(!result) { + result=true; + //lint -save + //lint -e611 //suspicious cast + privateData->GptFunction[index]=(void *)callBackFunction; + //lint -restore_ + privateData->GptCallTime[index]=currentTime+(2500*callBackTime); + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>timeSpan) { + nextCallTime=timeSpan; + rescheduleRequired=true; + slot_index = index; + } + } + } else { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>=timeSpan) { + nextCallTime=timeSpan; + rescheduleRequired=false; + } + } + } + if(rescheduleRequired) { + privateData->Gpt_scheduled_slot_index = slot_index; + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + } + if(!result) { + SMSC_WARNING("Gpt_ScheduleCallBack: Failed"); + } +} + +void Gpt_CancelCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData)) +{ + bool result=false; + if(callBackFunction!=NULL) { + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + TIME_SPAN timeSpan=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]==callBackFunction) { + result=true; + //lint -save + //lint -e611 //suspicious cast + privateData->GptFunction[index]=(void *)NULL; + // cancelled time will not need a + // re-scheduled + + // re-scheduled is done at other + // non-null slots + } + else if(privateData->GptFunction[index]!=NULL) { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + // if this scheduled time is earlier + // than current scheduled time + // AND not a duplicated one + if(nextCallTime>=timeSpan && privateData->Gpt_scheduled_slot_index != index) { + nextCallTime=timeSpan; + rescheduleRequired=true; + privateData->Gpt_scheduled_slot_index = index; + } + } + } + if(rescheduleRequired) { + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + else if (privateData->Gpt_scheduled_slot_index==GPT_SCHEDULE_DEPTH) { + Gpt_CancelInterrupt(privateData); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + } + if(!result) { + SMSC_WARNING("Gpt_CancelCallBack: Failed"); + } +} + +bool Gpt_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts) +{ + SMSC_ASSERT(privateData!=NULL); + if(dwIntSts&INT_STS_GPT_INT_) + { + unsigned long dwIntFlags=0; + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN timeSpan=MAX_TIME_SPAN; + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]!=NULL) { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(timeSpan<1250) { + void (*callBackFunction)(PPRIVATE_DATA privateData); + callBackFunction=privateData->GptFunction[index]; + privateData->GptFunction[index]=NULL; + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + privateData->Gpt_scheduled_slot_index = GPT_SCHEDULE_DEPTH; + callBackFunction(privateData); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + } + } + } + for(index=0;indexGptFunction[index]!=NULL) { + rescheduleRequired=true; + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>timeSpan) { + nextCallTime=timeSpan; + privateData->Gpt_scheduled_slot_index = index; + } + } + } + if(rescheduleRequired) { + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + return true; + } + return false; +} + +void GptCB_RxCompleteMulticast(PPRIVATE_DATA privateData) +{ + Rx_CompleteMulticastUpdate (privateData); +} + +void GptCB_RestartBurst(PPRIVATE_DATA privateData) +{ + if(privateData->RxFlowControlActive) { + privateData->RxFlowBurstActive=true; + if(privateData->RxFlowBurstWorkLoad>privateData->RxFlowBurstMaxWorkLoad) { + privateData->RxFlowBurstWorkLoad-=privateData->RxFlowBurstMaxWorkLoad; + } else { + privateData->RxFlowBurstWorkLoad=0; + } + Gpt_ScheduleCallBack(privateData,GptCB_RestartBurst, + privateData->RxFlowParameters.BurstPeriod); + } + Lan_EnableInterrupt(privateData,privateData->RxInterrupts); +} + +void GptCB_MeasureRxThroughput(PPRIVATE_DATA privateData) +{ + if(privateData->RxFlowMeasuredMaxThroughputRxFlowCurrentThroughput) { + privateData->RxFlowMeasuredMaxThroughput=privateData->RxFlowCurrentThroughput; + } + if(privateData->RxFlowMeasuredMaxPacketCountRxFlowCurrentPacketCount) { + privateData->RxFlowMeasuredMaxPacketCount=privateData->RxFlowCurrentPacketCount; + } + if(privateData->RxFlowCurrentThroughput!=0) { + if(privateData->RxFlowMaxWorkLoad!=0) { + if(!(privateData->RxFlowControlActive)) { + u32 activationLevel= + (privateData->RxFlowMaxWorkLoad*(100+RX_FLOW_ACTIVATION))/100; + if(privateData->RxFlowCurrentWorkLoad>=activationLevel) { + privateData->RxFlowControlActive=true; + privateData->RxFlowBurstActive=true; + privateData->RxFlowBurstWorkLoad=0; + Gpt_ScheduleCallBack(privateData,GptCB_RestartBurst, + privateData->RxFlowParameters.BurstPeriod); + //SET_GPIO(GP_TX); + } + } else { + u32 deactivationLevel= + (privateData->RxFlowMaxWorkLoad*(100-RX_FLOW_DEACTIVATION))/100; + if(privateData->RxFlowCurrentWorkLoad<=deactivationLevel) { + privateData->RxFlowControlActive=false; + //CLEAR_GPIO(GP_TX); + } + } + } + privateData->RxFlowCurrentThroughput=0; + privateData->RxFlowCurrentPacketCount=0; + privateData->RxFlowCurrentWorkLoad=0; + Gpt_ScheduleCallBack(privateData,GptCB_MeasureRxThroughput,1000); + } else { + if(privateData->RxFlowMaxWorkLoad!=0) { + if(privateData->RxFlowControlActive) { + privateData->RxFlowControlActive=false; + //CLEAR_GPIO(GP_TX); + } + } + privateData->MeasuringRxThroughput=false; + } +} + +irqreturn_t Smsc9118_ISR(int Irq, void *dev_id) +{ + u32 dwIntCfg=0; + u32 dwIntSts=0; + u32 dwIntEn=0; + u32 dwIntBits=0; + PPRIVATE_DATA privateData=(PPRIVATE_DATA)dev_id; + bool serviced=false; + + Irq=Irq;//make lint happy + + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_ISR(privateData==NULL)"); + goto DONE; + } + if(privateData->dwLanBase==0) { + SMSC_WARNING("Smsc9118_ISR(dwLanBase==0)"); + goto DONE; + } + SET_GPIO(GP_ISR); + dwIntCfg=Lan_GetRegDW(INT_CFG); + if((dwIntCfg&0x00001100)!=0x00001100) { + SMSC_TRACE("In ISR, not my interrupt, dwIntCfg=0x%08X", + dwIntCfg); + goto ALMOST_DONE; + } + + { + /* + * KH: Neither is true for 9210 + u32 reservedBits; + if(OLD_REGISTERS(privateData)) { + reservedBits=0x00FFEEEEUL; + } else { + reservedBits=0x00FFCEEEUL; + } + */ + /* + reservedBits = 0x00FF8EEEUL; + if(dwIntCfg&reservedBits) { + SMSC_WARNING("In ISR, reserved bits are high.\n"); + SMSC_TRACE("(reserved=0x%08X int=0x%08X)\n", reservedBits, dwIntCfg); + //this could mean surprise removal + goto ALMOST_DONE; + } + */ + } + + dwIntSts=Lan_GetRegDW(INT_STS); + dwIntEn=Lan_GetRegDW(INT_EN); + dwIntBits=dwIntSts&dwIntEn; + //SMSC_TRACE("dwIntBits= 0x%x8l \n", dwIntBits); + privateData->LastIntStatus3=privateData->LastIntStatus2; + privateData->LastIntStatus2=privateData->LastIntStatus1; + privateData->LastIntStatus1=dwIntBits; + if(Lan_HandleSoftwareInterrupt(privateData,dwIntBits)) { + serviced=true; + } + if(Gpt_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + if(Tx_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + if(RxStop_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + + if(Rx_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + if(!serviced) { + SMSC_WARNING("unserviced interrupt dwIntCfg=0x%08X,dwIntSts=0x%08X,dwIntEn=0x%08X,dwIntBits=0x%08X", + dwIntCfg,dwIntSts,dwIntEn,dwIntBits); + } + +ALMOST_DONE: + CLEAR_GPIO(GP_ISR); +DONE: + return IRQ_RETVAL(serviced); +} + +#ifdef USE_PHY_WORK_AROUND +bool Phy_Reset(PPRIVATE_DATA privateData,VL_KEY keyCode) +{ + bool result=false; + WORD wTemp=0; + u32 dwLoopCount=100000; + SMSC_TRACE("Performing PHY BCR Reset"); + Phy_SetRegW(privateData,PHY_BCR,PHY_BCR_RESET_,keyCode); + do { + udelay(10); + wTemp=Phy_GetRegW(privateData,PHY_BCR,keyCode); + dwLoopCount--; + } while((dwLoopCount>0)&&(wTemp&PHY_BCR_RESET_)); + if(wTemp&PHY_BCR_RESET_) { + SMSC_WARNING("Phy Reset failed to complete."); + goto DONE; + } + //extra delay required because the phy may not be completed with its reset + // when PHY_BCR_RESET_ is cleared. + // They say 256 uS is enough delay but I'm using 500 here to be safe + udelay(500); + result=true; +DONE: + return result; +} + +u32 Phy_LBT_GetTxStatus(PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + if(result!=0x00800000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } else { + result&=TX_FIFO_INF_TSUSED_; + if(result!=0x00000000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } + return result; +} + +u32 Phy_LBT_GetRxStatus(PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(RX_FIFO_INF); + if(result&0x00FF0000UL) { + //Rx status is available, read it + result=Lan_GetRegDW(RX_STATUS_FIFO); + } else { + result=0; + } + return result; +} + +bool Phy_TransmitTestPacket(PPRIVATE_DATA privateData) +{ + bool result=false; + u32 dwLoopCount=0; + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + u32 dwStatus=0; + + //write Tx Packet to 118 + dwTxCmdA= + ((((u32)(privateData->LoopBackTxPacket))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ | + ((u32)(MIN_PACKET_SIZE)); + dwTxCmdB= + (((u32)(MIN_PACKET_SIZE))<<16) | + ((u32)(MIN_PACKET_SIZE)); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(privateData->LoopBackTxPacket))&0xFFFFFFFCUL), + (((u32)(MIN_PACKET_SIZE))+3+ + (((u32)(privateData->LoopBackTxPacket))&0x03UL))>>2); + + //wait till transmit is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetTxStatus(privateData))==0)) { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Transmit during Packet Test"); + goto DONE; + } + if(dwStatus&0x00008000UL) { + SMSC_WARNING("Transmit encountered errors during Packet Test"); + goto DONE; + } +DONE: + return result; +} + +bool Phy_CheckLoopBackPacket(PPRIVATE_DATA privateData) + +{ + bool result=false; + u32 tryCount=0; + u32 dwLoopCount=0; + for(tryCount=0;tryCount<10;tryCount++) + { + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + u32 dwStatus=0; + u32 dwPacketLength=0; + + //zero-out Rx Packet memory + memset(privateData->LoopBackRxPacket,0,MIN_PACKET_SIZE); + + //write Tx Packet to 118 + dwTxCmdA= + ((((u32)(privateData->LoopBackTxPacket))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ | + ((u32)(MIN_PACKET_SIZE)); + dwTxCmdB= + (((u32)(MIN_PACKET_SIZE))<<16) | + ((u32)(MIN_PACKET_SIZE)); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(privateData->LoopBackTxPacket))&0xFFFFFFFCUL), + (((u32)(MIN_PACKET_SIZE))+3+ + (((u32)(privateData->LoopBackTxPacket))&0x03UL))>>2); + + //wait till transmit is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetTxStatus(privateData))==0)) { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Transmit during Loop Back Test"); + continue; + } + if(dwStatus&0x00008000UL) { + SMSC_WARNING("Transmit encountered errors during Loop Back Test"); + continue; + } + + //wait till receive is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetRxStatus(privateData))==0)) + { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Receive during Loop Back Test"); + continue; + } + if(dwStatus&RX_STS_ES_) + { + SMSC_WARNING("Receive encountered errors during Loop Back Test"); + continue; + } + + dwPacketLength=((dwStatus&0x3FFF0000UL)>>16); + + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(privateData->LoopBackRxPacket)), + (dwPacketLength+3+(((u32)(privateData->LoopBackRxPacket))&0x03UL))>>2); + + if(dwPacketLength!=(MIN_PACKET_SIZE+4)) { + SMSC_WARNING("Unexpected packet size during loop back test, size=%d, will retry",dwPacketLength); + } else { + u32 byteIndex=0; + bool foundMissMatch=false; + for(byteIndex=0;byteIndexLoopBackTxPacket[byteIndex]!=privateData->LoopBackRxPacket[byteIndex]) + { + foundMissMatch=true; + break; + } + } + if(!foundMissMatch) { + SMSC_TRACE("Successfully Verified Loop Back Packet"); + result=true; + goto DONE; + } else { + SMSC_WARNING("Data miss match during loop back test, will retry."); + } + } + } +DONE: + return result; +} + +bool Phy_LoopBackTest(PPRIVATE_DATA privateData) +{ + bool result=false; + u32 byteIndex=0; + u32 tryCount=0; + // u32 failed=0; + //Initialize Tx Packet + for(byteIndex=0;byteIndex<6;byteIndex++) { + //use broadcast destination address + privateData->LoopBackTxPacket[byteIndex]=(BYTE)0xFF; + } + for(byteIndex=6;byteIndex<12;byteIndex++) { + //use incrementing source address + privateData->LoopBackTxPacket[byteIndex]=(BYTE)byteIndex; + } + //Set length type field + privateData->LoopBackTxPacket[12]=0x00; + privateData->LoopBackTxPacket[13]=0x00; + for(byteIndex=14;byteIndexLoopBackTxPacket[byteIndex]=(BYTE)byteIndex; + } + //TRY_AGAIN: + { + u32 dwRegVal=Lan_GetRegDW(HW_CFG); + dwRegVal&=(HW_CFG_TX_FIF_SZ_|0x00000FFFUL); + dwRegVal|=HW_CFG_SF_; + Lan_SetRegDW(HW_CFG,dwRegVal); + } + Lan_SetRegDW(TX_CFG,TX_CFG_TX_ON_); + + Lan_SetRegDW(RX_CFG,(((u32)(privateData->LoopBackRxPacket))&0x03)<<8); + + { + + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + //Set Phy to 10/FD, no ANEG, + Phy_SetRegW(privateData,PHY_BCR,0x0100,keyCode); + + //enable MAC Tx/Rx, FD + Mac_SetRegDW(privateData,MAC_CR,MAC_CR_FDPX_|MAC_CR_TXEN_|MAC_CR_RXEN_,keyCode); + + // Phy_TransmitTestPacket(privateData); + + //set Phy to loopback mode + Phy_SetRegW(privateData,PHY_BCR,0x4100,keyCode); + + for(tryCount=0;tryCount<10;tryCount++) { + if(Phy_CheckLoopBackPacket(privateData)) + { + result=true; + goto DONE; + } + privateData->dwResetCount++; + //disable MAC rx + Mac_SetRegDW(privateData,MAC_CR,0UL,keyCode); + Phy_Reset(privateData,keyCode); + + //Set Phy to 10/FD, no ANEG, and Loopbackmode + Phy_SetRegW(privateData,PHY_BCR,0x4100,keyCode); + + //enable MAC Tx/Rx, FD + Mac_SetRegDW(privateData,MAC_CR,MAC_CR_FDPX_|MAC_CR_TXEN_|MAC_CR_RXEN_,keyCode); + } + // if(failed<2) { + // if(tryCount>=10) { + // u32 timeOut=10000; + // Lan_ShowRegs(privateData); + // SMSC_TRACE("Performing full reset"); + // privateData->Lan9118->HW_CFG=HW_CFG_SRST_; + // while((timeOut>0)&&(privateData->Lan9118->HW_CFG&HW_CFG_SRST_)) { + // udelay(1); + // timeOut--; + // } + // failed++; + // goto TRY_AGAIN; + // } + // } +DONE: + //disable MAC + Mac_SetRegDW(privateData,MAC_CR,0UL,keyCode); + //Cancel Phy loopback mode + Phy_SetRegW(privateData,PHY_BCR,0U,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + Lan_SetRegDW(TX_CFG,0UL); + Lan_SetRegDW(RX_CFG,0UL); + + return result; +} + +#endif //USE_PHY_WORK_AROUND +void Phy_SetLink(PPRIVATE_DATA privateData, + u32 dwLinkRequest) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwLinkRequest&LINK_AUTO_NEGOTIATE) { + WORD wTemp; + wTemp=Phy_GetRegW(privateData, + PHY_ANEG_ADV,keyCode); + wTemp&=~PHY_ANEG_ADV_PAUSE_; + if(dwLinkRequest&LINK_ASYMMETRIC_PAUSE) { + wTemp|=PHY_ANEG_ADV_ASYMP_; + } + if(dwLinkRequest&LINK_SYMMETRIC_PAUSE) { + wTemp|=PHY_ANEG_ADV_SYMP_; + } + wTemp&=~PHY_ANEG_ADV_SPEED_; + if(dwLinkRequest&LINK_SPEED_10HD) { + wTemp|=PHY_ANEG_ADV_10H_; + } + if(dwLinkRequest&LINK_SPEED_10FD) { + wTemp|=PHY_ANEG_ADV_10F_; + } + if(dwLinkRequest&LINK_SPEED_100HD) { + wTemp|=PHY_ANEG_ADV_100H_; + } + if(dwLinkRequest&LINK_SPEED_100FD) { + wTemp|=PHY_ANEG_ADV_100F_; + } + Phy_SetRegW(privateData,PHY_ANEG_ADV,wTemp,keyCode); + + // begin to establish link + privateData->dwRemoteFaultCount=0; + Phy_SetRegW(privateData, + PHY_BCR, + PHY_BCR_AUTO_NEG_ENABLE_| + PHY_BCR_RESTART_AUTO_NEG_, + keyCode); + } else { + WORD wTemp=0; + if(dwLinkRequest&(LINK_SPEED_100FD)) { + dwLinkRequest=LINK_SPEED_100FD; + } else if(dwLinkRequest&(LINK_SPEED_100HD)) { + dwLinkRequest=LINK_SPEED_100HD; + } else if(dwLinkRequest&(LINK_SPEED_10FD)) { + dwLinkRequest=LINK_SPEED_10FD; + } else if(dwLinkRequest&(LINK_SPEED_10HD)) { + dwLinkRequest=LINK_SPEED_10HD; + } + if(dwLinkRequest&(LINK_SPEED_10FD|LINK_SPEED_100FD)) { + wTemp|=PHY_BCR_DUPLEX_MODE_; + } + if(dwLinkRequest&(LINK_SPEED_100HD|LINK_SPEED_100FD)) { + wTemp|=PHY_BCR_SPEED_SELECT_; + } + Phy_SetRegW(privateData,PHY_BCR,wTemp,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Phy_SetAutoMdixSts(PPRIVATE_DATA privateData, + WORD wAutoMdixSts) +{ + WORD SpecialCtrlSts=0U; + + if (((privateData->dwGeneration)>2) && (!(privateData->ExtPhy))) + { + if (wAutoMdixSts > 2) + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + SpecialCtrlSts = (SpecialCtrlSts&0x1FFF); + Phy_SetRegW(privateData, SPECIAL_CTRL_STS,SpecialCtrlSts,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (Lan_GetRegDW(HW_CFG) & HW_CFG_AMDIX_EN_STRAP_STS_) { + SMSC_TRACE("Auto-MDIX Enable by default!!!"); + } + else { + SMSC_TRACE("Auto-MDIX Disable by default!!!"); + } + } + else + { + + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + SpecialCtrlSts = (((wAutoMdixSts+4) << 13) | (SpecialCtrlSts&0x1FFF)); + Phy_SetRegW(privateData, SPECIAL_CTRL_STS,SpecialCtrlSts,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (wAutoMdixSts & AMDIX_ENABLE) { + SMSC_TRACE("Override Strap, Enable Auto-MDIX "); + } else if (wAutoMdixSts & AMDIX_DISABLE_CROSSOVER) { + SMSC_TRACE("Override Strap, Disable Auto-MDIX, CrossOver Cable"); + } else { + SMSC_TRACE("Override Strap, Disable Auto-MDIX, Straight Cable"); + } + + } + } + + else { + SMSC_TRACE("This chip or PHY doesn't support HP AMDIX!!!"); + } + +} + +void Phy_GetAutoMdixSts(PPRIVATE_DATA privateData) +{ + + + WORD SpecialCtrlSts=0U; + unsigned long dwIntFlags=0; + + if (((privateData->dwGeneration)>2) && (!(privateData->ExtPhy))) + { + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (SpecialCtrlSts & SPECIAL_CTRL_STS_OVRRD_AMDIX_) { + + if (SpecialCtrlSts & SPECIAL_CTRL_STS_AMDIX_ENABLE_) { + SMSC_TRACE("AutoMdix Status: Override Strap, Enable Auto Mdix"); + } + else if (SpecialCtrlSts & SPECIAL_CTRL_STS_AMDIX_STATE_) { + + SMSC_TRACE("AutoMdix Status: Override Strap, Disable Auto Mdix, CrossOver Cable"); + + } else { + + SMSC_TRACE("AutoMdix Status: Override Strap, Disable Auto Mdix, Straight Cable"); + } + + } + else { + if (Lan_GetRegDW(HW_CFG) & HW_CFG_AMDIX_EN_STRAP_STS_) { + SMSC_TRACE("AutoMdix Status: Enable by default!!!"); + } + else { + SMSC_TRACE("AutoMdix Status: Disable by default!!!"); + } + } + + } + else { + SMSC_TRACE("This chip or PHY doesn't support HP AMDIX!!!"); + } + +} + + +bool Phy_Initialize( + PPRIVATE_DATA privateData, + u32 dwPhyAddr, + u32 dwLinkRequest) +{ + bool result=false; + u32 dwTemp=0; + WORD wTemp=0; + u32 dwLoopCount=0; + // WORD SpecialCtrlSts=0U; + + SMSC_TRACE("-->Phy_Initialize"); + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + SMSC_ASSERT(dwLinkRequest<=0x7FUL); + privateData->ExtPhy=false; + + if(dwPhyAddr!=0xFFFFFFFFUL) { + switch(privateData->dwIdRev&0xFFFF0000) { + case 0x117A0000UL: + case 0x115A0000UL: + goto EXTERNAL_PHY_SUPPORTED; + case 0x01170000UL: + case 0x01150000UL: + if(privateData->dwIdRev&0x0000FFFF) { + u32 dwHwCfg=0; +EXTERNAL_PHY_SUPPORTED: + dwHwCfg=Lan_GetRegDW(HW_CFG); + if(dwHwCfg&HW_CFG_EXT_PHY_DET_) { + //External phy is requested, supported, and detected + //Attempt to switch + //NOTE: Assuming Rx and Tx are stopped + // because Phy_Initialize is called before + // Rx_Initialize and Tx_Initialize + WORD wPhyId1=0; + WORD wPhyId2=0; + + //Disable phy clocks to the mac + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to acutally stop + + dwHwCfg|=HW_CFG_EXT_PHY_EN_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_EXT_PHY_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually start + + dwHwCfg|=HW_CFG_SMI_SEL_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwPhyAddr<=31) { + //only check the phy address specified + privateData->dwPhyAddress=dwPhyAddr; + wPhyId1=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + wPhyId2=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + } else { + //auto detect phy + u32 address=0; + for(address=0;address<=31;address++) { + privateData->dwPhyAddress=address; + wPhyId1=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + wPhyId2=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + if((wPhyId1!=0xFFFFU)||(wPhyId2!=0xFFFFU)) { + SMSC_TRACE("Detected Phy at address = 0x%02X = %d", + address,address); + break; + } + } + if(address>=32) { + SMSC_WARNING("Failed to auto detect external phy"); + } + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + if((wPhyId1==0xFFFFU)&&(wPhyId2==0xFFFFU)) { + SMSC_WARNING("External Phy is not accessable"); + SMSC_WARNING(" using internal phy instead"); + //revert back to interal phy settings. + + //Disable phy clocks to the mac + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually stop + + dwHwCfg&=(~HW_CFG_EXT_PHY_EN_); + Lan_SetRegDW(HW_CFG,dwHwCfg); + + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_INT_PHY_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually start + + dwHwCfg&=(~HW_CFG_SMI_SEL_); + Lan_SetRegDW(HW_CFG,dwHwCfg); + goto USE_INTERNAL_PHY; + } else { + SMSC_TRACE("Successfully switched to external phy"); + privateData->ExtPhy=true; +#ifdef USE_LED1_WORK_AROUND + privateData->NotUsingExtPhy=0; +#endif + } + } else { + SMSC_WARNING("No External Phy Detected"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + } + } else { + SMSC_WARNING("External Phy is not supported"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + };break; + default: + SMSC_WARNING("External Phy is not supported"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + } + } else { +USE_INTERNAL_PHY: + + privateData->dwPhyAddress=1; + privateData->ExtPhy=false; +#ifdef USE_LED1_WORK_AROUND + if(privateData->dwGeneration<=2) { + privateData->NotUsingExtPhy=1; + } else { + //Generation 3 or higher has the LED problem fixed + // to disable the workaround pretend the phy is external + privateData->NotUsingExtPhy=0; + } +#endif + + Phy_SetAutoMdixSts(privateData,AutoMdix); + } + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + dwTemp=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + privateData->bPhyRev=((BYTE)(dwTemp&(0x0FUL))); + privateData->bPhyModel=((BYTE)((dwTemp>>4)&(0x3FUL))); + privateData->dwPhyId=((dwTemp&(0xFC00UL))<<8); + dwTemp=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + privateData->dwPhyId|=((dwTemp&(0x0000FFFFUL))<<2); + + SMSC_TRACE("dwPhyId==0x%08X,bPhyModel==0x%02X,bPhyRev==0x%02X", + privateData->dwPhyId, + privateData->bPhyModel, + privateData->bPhyRev); + + privateData->dwLinkSpeed=LINK_OFF; + privateData->dwLinkSettings=LINK_OFF; + //reset the PHY + Phy_SetRegW(privateData,PHY_BCR,PHY_BCR_RESET_,keyCode); + dwLoopCount=100000; + do { + + udelay(10); + wTemp=Phy_GetRegW(privateData,PHY_BCR,keyCode); + dwLoopCount--; + } while((dwLoopCount>0) && (wTemp&PHY_BCR_RESET_)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + if(wTemp&PHY_BCR_RESET_) { + SMSC_WARNING("PHY reset failed to complete."); + goto DONE; + } + +#ifdef USE_PHY_WORK_AROUND + if(privateData->dwGeneration<=2) { + // printk("phy_LoopBackTest\n"); + if(!Phy_LoopBackTest(privateData)) { + SMSC_WARNING("Failed Loop back test"); + goto DONE; + } else { + SMSC_TRACE("Passed Loop Back Test"); + } + } +#endif + + Phy_SetLink(privateData,dwLinkRequest); + + init_timer(&(privateData->LinkPollingTimer)); + privateData->LinkPollingTimer.function=Phy_CheckLink; + privateData->LinkPollingTimer.data=(unsigned long)privateData; + privateData->LinkPollingTimer.expires=jiffies+HZ; + add_timer(&(privateData->LinkPollingTimer)); + + result=true; +DONE: + SMSC_TRACE("<--Phy_Initialize, result=%s",result?"true":"false"); + return result; +} + +WORD Phy_GetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + VL_KEY keyCode) +{ + u32 dwAddr=0; + int i=0; + WORD result=0xFFFFU; + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + + // confirm MII not busy + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) != 0UL) + { + SMSC_WARNING("MII is busy in Phy_GetRegW???"); + result=0; + goto DONE; + } + + // set the address, index & direction (read from PHY) + dwAddr = ((privateData->dwPhyAddress&0x1FUL)<<11) | ((dwRegIndex & 0x1FUL)<<6); + Mac_SetRegDW(privateData, MII_ACC, dwAddr,keyCode); + + // wait for read to complete w/ timeout + for(i=0;i<100;i++) { + // see if MII is finished yet + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) == 0UL) + { + // get the read data from the MAC & return i + result=((WORD)Mac_GetRegDW(privateData, MII_DATA,keyCode)); + goto DONE; + } + } + SMSC_WARNING("timeout waiting for MII write to finish"); + +DONE: + return result; +} + +void Phy_SetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex,WORD wVal, + VL_KEY keyCode) +{ + u32 dwAddr=0; + int i=0; + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + + if(dwRegIndex==0) { + if((wVal&0x1200)==0x1200) { + privateData->wLastADVatRestart=privateData->wLastADV; + } + } + if(dwRegIndex==4) { + privateData->wLastADV=wVal; + } + + // confirm MII not busy + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) != 0UL) + { + SMSC_WARNING("MII is busy in Phy_SetRegW???"); + goto DONE; + } + + // put the data to write in the MAC + Mac_SetRegDW(privateData, MII_DATA, (u32)wVal,keyCode); + + // set the address, index & direction (write to PHY) + dwAddr = ((privateData->dwPhyAddress&0x1FUL)<<11) | ((dwRegIndex & 0x1FUL)<<6) | MII_ACC_MII_WRITE_; + Mac_SetRegDW(privateData, MII_ACC, dwAddr,keyCode); + + // wait for write to complete w/ timeout + for(i=0;i<100;i++) { + // see if MII is finished yet + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) == 0UL) + { + goto DONE; + } + } + SMSC_WARNING("timeout waiting for MII write to finish"); +DONE: + return; +} + +void Phy_UpdateLinkMode(PPRIVATE_DATA privateData) +{ + u32 dwOldLinkSpeed=privateData->dwLinkSpeed; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + Phy_GetLinkMode(privateData,keyCode); + + if(dwOldLinkSpeed!=(privateData->dwLinkSpeed)) { + if(privateData->dwLinkSpeed!=LINK_OFF) { + u32 dwRegVal=0; + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + SMSC_TRACE("Link is now UP at 10Mbps HD"); + break; + case LINK_SPEED_10FD: + SMSC_TRACE("Link is now UP at 10Mbps FD"); + break; + case LINK_SPEED_100HD: + SMSC_TRACE("Link is now UP at 100Mbps HD"); + break; + case LINK_SPEED_100FD: + SMSC_TRACE("Link is now UP at 100Mbps FD"); + break; + default: + SMSC_WARNING("Link is now UP at Unknown Link Speed, dwLinkSpeed=0x%08X", + privateData->dwLinkSpeed); + break; + } + + dwRegVal=Mac_GetRegDW(privateData,MAC_CR,keyCode); + dwRegVal&=~(MAC_CR_FDPX_|MAC_CR_RCVOWN_); + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + dwRegVal|=MAC_CR_RCVOWN_; + break; + case LINK_SPEED_10FD: + case LINK_SPEED_100FD: + dwRegVal|=MAC_CR_FDPX_; + break; + default:break;//make lint happy + } + + Mac_SetRegDW(privateData, + MAC_CR,dwRegVal,keyCode); + + if(privateData->dwLinkSettings&LINK_AUTO_NEGOTIATE) { + WORD linkPartner=0; + WORD localLink=0; + localLink=Phy_GetRegW(privateData,4,keyCode); + linkPartner=Phy_GetRegW(privateData,5,keyCode); + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10FD: + case LINK_SPEED_100FD: + if(((localLink&linkPartner)&((WORD)0x0400U)) != ((WORD)0U)) { + //Enable PAUSE receive and transmit + Mac_SetRegDW(privateData,FLOW,0xFFFF0002UL,keyCode); + Lan_SetBitsDW(AFC_CFG,(afc_cfg&0x0000000FUL)); + } else if(((localLink&((WORD)0x0C00U))==((WORD)0x0C00U)) && + ((linkPartner&((WORD)0x0C00U))==((WORD)0x0800U))) + { + //Enable PAUSE receive, disable PAUSE transmit + Mac_SetRegDW(privateData,FLOW,0xFFFF0002UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + } else { + //Disable PAUSE receive and transmit + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + };break; + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_SetBitsDW(AFC_CFG,0x0000000FUL); + break; + default:break;//make lint happy + } + SMSC_TRACE("LAN9118: %s,%s,%s,%s,%s,%s", + (localLink&PHY_ANEG_ADV_ASYMP_)?"ASYMP":" ", + (localLink&PHY_ANEG_ADV_SYMP_)?"SYMP ":" ", + (localLink&PHY_ANEG_ADV_100F_)?"100FD":" ", + (localLink&PHY_ANEG_ADV_100H_)?"100HD":" ", + (localLink&PHY_ANEG_ADV_10F_)?"10FD ":" ", + (localLink&PHY_ANEG_ADV_10H_)?"10HD ":" "); + + SMSC_TRACE("Partner: %s,%s,%s,%s,%s,%s", + (linkPartner&PHY_ANEG_LPA_ASYMP_)?"ASYMP":" ", + (linkPartner&PHY_ANEG_LPA_SYMP_)?"SYMP ":" ", + (linkPartner&PHY_ANEG_LPA_100FDX_)?"100FD":" ", + (linkPartner&PHY_ANEG_LPA_100HDX_)?"100HD":" ", + (linkPartner&PHY_ANEG_LPA_10FDX_)?"10FD ":" ", + (linkPartner&PHY_ANEG_LPA_10HDX_)?"10HD ":" "); + } else { + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + Mac_SetRegDW(privateData,FLOW,0x0UL,keyCode); + Lan_SetBitsDW(AFC_CFG,0x0000000FUL); + break; + default: + Mac_SetRegDW(privateData,FLOW,0x0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + break; + } + } + netif_carrier_on(privateData->dev); + Tx_WakeQueue(privateData,0x01); +#ifdef USE_LED1_WORK_AROUND + if ((g_GpioSettingOriginal & GPIO_CFG_LED1_EN_) && + privateData->NotUsingExtPhy) + { + // Restore orginal GPIO configuration + g_GpioSetting = g_GpioSettingOriginal; + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +#endif // USE_LED1_WORK_AROUND + } else { + SMSC_TRACE("Link is now DOWN"); + Tx_StopQueue(privateData,0x01); + netif_carrier_off(privateData->dev); + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); +#ifdef USE_LED1_WORK_AROUND + // Check global setting that LED1 usage is 10/100 indicator + // g_GpioSetting = Lan_GetRegDW(GPIO_CFG); + if ((g_GpioSetting & GPIO_CFG_LED1_EN_) && + privateData->NotUsingExtPhy) + { + //Force 10/100 LED off, after saving orginal GPIO configuration + g_GpioSettingOriginal = g_GpioSetting; + + g_GpioSetting &= ~GPIO_CFG_LED1_EN_; + g_GpioSetting |= + (GPIO_CFG_GPIOBUF0_|GPIO_CFG_GPIODIR0_|GPIO_CFG_GPIOD0_); + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +#endif // USE_LED1_WORK_AROUND + } + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Phy_CheckLink(unsigned long ptr) +{ + PPRIVATE_DATA privateData=(PPRIVATE_DATA)ptr; + if(privateData==NULL) { + SMSC_WARNING("Phy_CheckLink(ptr==0)"); + return; + } + + //must call this twice + Phy_UpdateLinkMode(privateData); + Phy_UpdateLinkMode(privateData); + + if(!(privateData->StopLinkPolling)) { + privateData->LinkPollingTimer.expires=jiffies+HZ; + add_timer(&(privateData->LinkPollingTimer)); + } +} + +void Phy_GetLinkMode( + PPRIVATE_DATA privateData, + VL_KEY keyCode) +{ + u32 result=LINK_OFF; + WORD wRegVal=0; + WORD wRegBSR=Phy_GetRegW( + privateData, + PHY_BSR,keyCode); + privateData->dwLinkSettings=LINK_OFF; + if(wRegBSR&PHY_BSR_LINK_STATUS_) { + wRegVal=Phy_GetRegW( + privateData, + PHY_BCR,keyCode); + if(wRegVal&PHY_BCR_AUTO_NEG_ENABLE_) { + u32 linkSettings=LINK_AUTO_NEGOTIATE; + WORD wRegADV=privateData->wLastADVatRestart; + // Phy_GetRegW( + // privateData, + // PHY_ANEG_ADV,keyCode); + WORD wRegLPA=Phy_GetRegW( + privateData, + PHY_ANEG_LPA,keyCode); + if(wRegADV&PHY_ANEG_ADV_ASYMP_) { + linkSettings|=LINK_ASYMMETRIC_PAUSE; + } + if(wRegADV&PHY_ANEG_ADV_SYMP_) { + linkSettings|=LINK_SYMMETRIC_PAUSE; + } + if(wRegADV&PHY_ANEG_LPA_100FDX_) { + linkSettings|=LINK_SPEED_100FD; + } + if(wRegADV&PHY_ANEG_LPA_100HDX_) { + linkSettings|=LINK_SPEED_100HD; + } + if(wRegADV&PHY_ANEG_LPA_10FDX_) { + linkSettings|=LINK_SPEED_10FD; + } + if(wRegADV&PHY_ANEG_LPA_10HDX_) { + linkSettings|=LINK_SPEED_10HD; + } + privateData->dwLinkSettings=linkSettings; + wRegLPA&=wRegADV; + if(wRegLPA&PHY_ANEG_LPA_100FDX_) { + result=LINK_SPEED_100FD; + } else if(wRegLPA&PHY_ANEG_LPA_100HDX_) { + result=LINK_SPEED_100HD; + } else if(wRegLPA&PHY_ANEG_LPA_10FDX_) { + result=LINK_SPEED_10FD; + } else if(wRegLPA&PHY_ANEG_LPA_10HDX_) { + result=LINK_SPEED_10HD; + } + } else { + if(wRegVal&PHY_BCR_SPEED_SELECT_) { + if(wRegVal&PHY_BCR_DUPLEX_MODE_) { + privateData->dwLinkSettings=result=LINK_SPEED_100FD; + } else { + privateData->dwLinkSettings=result=LINK_SPEED_100HD; + } + } else { + if(wRegVal&PHY_BCR_DUPLEX_MODE_) { + privateData->dwLinkSettings=result=LINK_SPEED_10FD; + } else { + privateData->dwLinkSettings=result=LINK_SPEED_10HD; + } + } + } + } + privateData->dwLinkSpeed=result; +} + +extern int smsc_prom_get_ethernet_mac_addr(char *addr); + +bool Mac_Initialize(PPRIVATE_DATA privateData) +{ + unsigned char ea[6]; + int result; + u32 dwHigh16, dwLow32; + unsigned long dwIntFlags = 0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + SMSC_ASSERT(privateData!=NULL); +#if ( defined(CONFIG_MIPS_HMP10) || defined(CONFIG_MIPS_HMP5)) + result = smsc_prom_get_ethernet_mac_addr(ea); +#else + result = prom_get_ethernet_addr(ea); +#endif + + if (result == 0) { + SMSC_TRACE("Got ethernet addr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X from prom\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5] ); + dwHigh16 = (ea[5] << 8) | ea[4]; + Mac_SetRegDW(privateData, ADDRH, dwHigh16, keyCode); + dwLow32 = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; + Mac_SetRegDW(privateData, ADDRL, dwLow32, keyCode); + } else { + SMSC_TRACE("Failed to get ethernet addr from prom\n"); + return false; + } + + return true; +} + +static bool MacNotBusy(PPRIVATE_DATA privateData, VL_KEY keyCode) +{ + int i=0; + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + // wait for MAC not busy, w/ timeout + for(i=0;i<40;i++) + { + if((Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_)==(0UL)) { + return true; + } + } + SMSC_WARNING("timeout waiting for MAC not BUSY. MAC_CSR_CMD = 0x%08X", + Lan_GetRegDW(MAC_CSR_CMD)); + return false; +} + +u32 Mac_GetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,VL_KEY keyCode) +{ + u32 result=0xFFFFFFFFUL; + u32 dwTemp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + SMSC_ASSERT(privateData->dwLanBase!=0); + + // wait until not busy + if (Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_) + { + SMSC_WARNING("Mac_GetRegDW() failed, MAC already busy at entry"); + goto DONE; + } + + // send the MAC Cmd w/ offset + Lan_SetRegDW(MAC_CSR_CMD, + ((dwRegOffset & 0x000000FFUL) | + MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); + dwTemp=Lan_GetRegDW(BYTE_TEST);//to flush previous write + dwTemp=dwTemp; + + // wait for the read to happen, w/ timeout + if (!MacNotBusy(privateData,keyCode)) + { + SMSC_WARNING("Mac_GetRegDW() failed, waiting for MAC not busy after read"); + goto DONE; + } else { + // finally, return the read data + result=Lan_GetRegDW(MAC_CSR_DATA); + } +DONE: + return result; +} + +void Mac_SetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,u32 dwVal,VL_KEY keyCode) +{ + u32 dwTemp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + SMSC_ASSERT(privateData->dwLanBase!=0); + + if (Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_) + { + SMSC_WARNING("Mac_SetRegDW() failed, MAC already busy at entry"); + goto DONE; + } + + // send the data to write + Lan_SetRegDW(MAC_CSR_DATA,dwVal); + + // do the actual write + Lan_SetRegDW(MAC_CSR_CMD,((dwRegOffset & 0x000000FFUL) | MAC_CSR_CMD_CSR_BUSY_)); + dwTemp=Lan_GetRegDW(BYTE_TEST);//force flush of previous write + dwTemp=dwTemp; + + // wait for the write to complete, w/ timeout + if (!MacNotBusy(privateData,keyCode)) + { + SMSC_WARNING("Mac_SetRegDW() failed, waiting for MAC not busy after write"); + } +DONE: + return; +} + +#define TX_FIFO_LOW_THRESHOLD (1600) +//#define Tx_Max_Fragments (86) //every fragment needs 6 bytes overhead. 1514+2(alignment)+6*86=2032 < 2036 + +void Tx_Initialize( + PPRIVATE_DATA privateData, + u32 dwTxDmaCh, + u32 dwDmaThreshold) +{ + u32 dwRegVal=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + + dwRegVal=Lan_GetRegDW(HW_CFG); + dwRegVal&=(HW_CFG_TX_FIF_SZ_|0x00000FFFUL); + dwRegVal|=HW_CFG_SF_; + Lan_SetRegDW(HW_CFG,dwRegVal); + + + if(privateData->UseTxCsum) + + //Set TX COE + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwCoeCr=Mac_GetRegDW(privateData,COE_CR,keyCode); + dwCoeCr|=(TX_COE_EN); + Mac_SetRegDW(privateData,COE_CR,dwCoeCr,keyCode); + //printk("COE_CR = 0x%08x\n", Mac_GetRegDW(privateData,COE_CR,keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + + + + Lan_SetTDFL(privateData,0xFF); + Lan_EnableInterrupt(privateData,INT_EN_TDFA_EN_); + + privateData->dwTxDmaThreshold=dwDmaThreshold; + privateData->dwTxDmaCh=dwTxDmaCh; + if(dwTxDmaCh>=TRANSFER_PIO) { + SMSC_TRACE("Tx will use PIO"); + } else { + SMSC_TRACE("Tx will use DMA channel %d",dwTxDmaCh); + SMSC_ASSERT(Platform_IsValidDmaChannel(dwTxDmaCh)); + if(!Platform_DmaInitialize( + &(privateData->PlatformData), + dwTxDmaCh)) + { + SMSC_WARNING("Failed Platform_DmaInitialize, dwTxDmaCh=%u",dwTxDmaCh); + } + privateData->TxDmaXfer.dwLanReg=privateData->dwLanBase+TX_DATA_FIFO; + privateData->TxDmaXfer.pdwBuf=NULL;//this will be reset per dma request + privateData->TxDmaXfer.dwDmaCh=privateData->dwTxDmaCh; + privateData->TxDmaXfer.dwDwCnt=0;//this will be reset per dma request + privateData->TxDmaXfer.fMemWr=false; + } + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + dwMacCr|=(MAC_CR_TXEN_|MAC_CR_HBDIS_); + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + Lan_SetRegDW(TX_CFG,TX_CFG_TX_ON_); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + privateData->TxSkb=NULL; + spin_lock_init(&(privateData->TxSkbLock)); + privateData->dwTxQueueDisableMask=0; + spin_lock_init(&(privateData->TxQueueLock)); + spin_lock_init(&(privateData->TxCounterLock)); + privateData->TxInitialized=true; + +} + +bool Tx_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts) +{ + SMSC_ASSERT(privateData!=NULL); + if(dwIntSts&INT_STS_TDFA_) + { + Lan_SetTDFL(privateData,0xFF); + Lan_SetRegDW(INT_STS,INT_STS_TDFA_); + Tx_WakeQueue(privateData,0x02UL); + return true; + } + return false; +} + +void Tx_StopQueue( + PPRIVATE_DATA privateData,u32 dwSource) +{ + unsigned long intFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dev!=NULL); + SMSC_ASSERT(privateData->TxInitialized); + spin_lock_irqsave(&(privateData->TxQueueLock),intFlags); + if(privateData->dwTxQueueDisableMask==0) { + netif_stop_queue(privateData->dev); + } + privateData->dwTxQueueDisableMask|=dwSource; + spin_unlock_irqrestore(&(privateData->TxQueueLock),intFlags); +} + +void Tx_WakeQueue( + PPRIVATE_DATA privateData,u32 dwSource) +{ + unsigned long intFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dev!=NULL); + SMSC_ASSERT(privateData->TxInitialized); + spin_lock_irqsave(&(privateData->TxQueueLock),intFlags); + privateData->dwTxQueueDisableMask&=(~dwSource); + if(privateData->dwTxQueueDisableMask==0) { + netif_wake_queue(privateData->dev); + } + spin_unlock_irqrestore(&(privateData->TxQueueLock),intFlags); +} + +static u32 Tx_GetTxStatusCount( + PPRIVATE_DATA privateData) +{ + u32 result=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + result>>=16; + if(result>0x80) { + SMSC_WARNING("TX_FIFO_INF_TSFREE_>0x80"); + result=0x80; + } + result=0x80-result; + } else { + result&=TX_FIFO_INF_TSUSED_; + result>>=16; + } + return result; +} + + + +void Tx_SendSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb) +{ + u32 dwFreeSpace=0; + unsigned int i=0, TxFrag=0, skbFragCnt = skb_shinfo(skb)->nr_frags + 1; + + //if (skbFragCnt>1) + // printk("skbFrsgCnt = (%d)\n", skbFragCnt); + + // if (privateData->UseTxCsum) { + int Chsum_start_offset=0; + u32 dwTxCsumPreamble=0; + // } + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + + if(privateData->UseTxCsum){ + + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + //printk("ip summed!\n"); + TxFrag = skbFragCnt + 1; + } + else + { + TxFrag = skbFragCnt; + } + } + else { + TxFrag = skbFragCnt; + } + TxFrag = skbFragCnt; + + + if (privateData->UseTxCsum) { + + if (skb->ip_summed == CHECKSUM_PARTIAL) + { + CalculateTxChecksumOffset( + skb, + &Chsum_start_offset); + + + dwTxCsumPreamble=(((WORD) (Chsum_start_offset + skb->csum)) << 16) | ((WORD) Chsum_start_offset); + + + } + } + + //printk("Tx skb->len = 0x%08x\n", (u32) skb->len); + + + + if(privateData->dwTxDmaCh>=TRANSFER_PIO) + { + //Use PIO only + + //printk("Tx using pio only\n"); + + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + + + dwTxCmdA=TX_CMD_A_INT_FIRST_SEG_ |((u32)sizeof(u32)) ; + + dwTxCmdB= + (((u32)(skb->len+4))<<16) | TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + + + } + } + + if (skbFragCnt == 1){ + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + + dwTxCmdA =((((u32)(skb->data))&0x03UL)<<16) | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | TX_CMD_A_INT_FIRST_SEG_ | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + + //printk("dwTxCmdA = 0x%08x\n", (u32) dwTxCmdA); + //printk("dwTxCmdB = 0x%08x\n", (u32) dwTxCmdB); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + + // rkdump(skb->data, skb->len); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)(skb->len))+3+ + (((u32)(skb->data))&0x03UL))>>2); + + //printk("Tx skb->len2 = 0x%08x\n", (u32) skb->len); + dwFreeSpace-=(skb->len+32); + dev_kfree_skb(skb); + + } + + else { + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) |TX_CMD_A_INT_FIRST_SEG_ | + ((u32)((skb->len)-(skb->data_len))); + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + //printk("first frag. \n"); + //rkdump(skb->data, ((skb->len)-(skb->data_len))); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)((skb->len)-(skb->data_len)))+3+ + (((u32)(skb->data))&0x03UL))>>2); + // dwFreeSpace-=((skb->len-skb->data_len)+32); + + + for(i=1;ifrags[i - 1]; + void *frag_addr = page_address(frag->page) + frag->page_offset; + + + dwTxCmdA= + ((((u32)(frag_addr))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)(frag->size)); + + + if (i==(skbFragCnt-1)){ + dwTxCmdA |= TX_CMD_A_INT_LAST_SEG_ ; + } + + if(skb->ip_summed == CHECKSUM_PARTIAL) { + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else { + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + } + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + //printk("i= %d\n", i); + //rkdump(frag_addr, frag->size); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(frag_addr))&0xFFFFFFFCUL), + (((u32)(frag->size))+3+ + (((u32)(frag_addr))&0x03UL))>>2); + // dwFreeSpace-=(frag->size+8); + + } + + dwFreeSpace-=skb->len+12*TxFrag+16; + dev_kfree_skb(skb); + } + + } + + + else + { + //Use DMA and PIO + + //printk("Tx using dma!!\n"); + + u32 dwDmaCh=privateData->dwTxDmaCh; + PPLATFORM_DATA platformData=&(privateData->PlatformData); + SMSC_ASSERT(TX_FIFO_LOW_THRESHOLD>(skb->len+32)); + + if(((skb->len)>=(privateData->dwTxDmaThreshold)) && (skbFragCnt == 1)) + { + + //printk("Tx using dma!!\n"); + // if(privateData->UseTxCsum) { + u32 dwTxCmdA1=0; + u32 dwTxCmdB1=0; + // } + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + if(privateData->UseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + + { + + + dwTxCmdA1= + TX_CMD_A_INT_FIRST_SEG_ | + ((u32)sizeof(u32));//buffer length + + dwTxCmdB1= + (((u32)(skb->len+4))<<16) |TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + } + } + + if (skbFragCnt == 1){ + + dwTxCmdA = +#if (PLATFORM_CACHE_LINE_BYTES == 16) + (0x01UL<<24)|//16 byte end alignment +#endif +#if (PLATFORM_CACHE_LINE_BYTES == 32) + (0x02UL<<24)|//32 byte end alignment +#endif + ((((u32)(skb->data))&(PLATFORM_CACHE_LINE_BYTES-1))<<16) |//16 Byte start alignment + TX_CMD_A_INT_LAST_SEG_ | + ((u32)(skb->len));//buffer length + + if(skb->ip_summed != CHECKSUM_PARTIAL) + dwTxCmdA |= TX_CMD_A_INT_FIRST_SEG_; + + if (skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + } + + + + privateData->TxDmaXfer.pdwBuf= + (u32 *)(((u32)(skb->data))& + (~(PLATFORM_CACHE_LINE_BYTES-1))); + privateData->TxDmaXfer.dwDwCnt= + ((((u32)(skb->len))+ + (PLATFORM_CACHE_LINE_BYTES-1)+ + (((u32)(skb->data))& + (PLATFORM_CACHE_LINE_BYTES-1)))& + (~(PLATFORM_CACHE_LINE_BYTES-1)))>>2; + Platform_CachePurge( + platformData, + privateData->TxDmaXfer.pdwBuf, + (privateData->TxDmaXfer.dwDwCnt)<<2); + + spin_lock(&(privateData->TxSkbLock)); + { + if(privateData->TxSkb) + Platform_DmaComplete(platformData,dwDmaCh); + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + + { + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA1); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB1); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + } + } + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + if(!Platform_DmaStartXfer(platformData,&(privateData->TxDmaXfer))) + { + SMSC_WARNING("Failed Platform_DmaStartXfer"); + } + + dwFreeSpace-=(skb->len+32); + if(privateData->TxSkb) + dev_kfree_skb(privateData->TxSkb); + + privateData->TxSkb=skb; + } + spin_unlock(&(privateData->TxSkbLock)); + + } + + + + } + + else + { + + + //Use PIO + + //printk("skb->len (%d)\n", skb->len); + //printk("Tx using pio\n"); + + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + spin_lock(&(privateData->TxSkbLock)); + if(privateData->TxSkb) { + Platform_DmaComplete(platformData,dwDmaCh); + dev_kfree_skb(privateData->TxSkb); + privateData->TxSkb=NULL; + } + spin_unlock(&(privateData->TxSkbLock)); + + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + + dwTxCmdA=TX_CMD_A_INT_FIRST_SEG_ |((u32)sizeof(u32)) ; + + + dwTxCmdB= + (((u32)(skb->len+4))<<16) |TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + //printk("dwTxCmdA = 0x%08x\n", (u32) dwTxCmdA); + //printk("dwTxCmdB = 0x%08x\n", (u32) dwTxCmdB); + //printk("dwTxCsumPreamble = 0x%08x\n", (u32) dwTxCsumPreamble); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + + } + + } + + if (skbFragCnt == 1){ + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | TX_CMD_A_INT_FIRST_SEG_ | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + + } + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)(skb->len))+3+ + (((u32)(skb->data))&0x03UL))>>2); + dwFreeSpace-=(skb->len+32); + dev_kfree_skb(skb); + } + + else { + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) |TX_CMD_A_INT_FIRST_SEG_ | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + + //printk("first frag. \n"); + //rkdump(skb->data, ((skb->len)-(skb->data_len))); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)((skb->len)-(skb->data_len)))+3+ + (((u32)(skb->data))&0x03UL))>>2); + // dwFreeSpace-=((skb->len-skb->data_len)+32); + + + for(i=1;ifrags[i - 1]; + void *frag_addr = page_address(frag->page) + frag->page_offset; + + + dwTxCmdA= + ((((u32)(frag_addr))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)(frag->size)); + + + if (i==(skbFragCnt-1)){ + dwTxCmdA |= TX_CMD_A_INT_LAST_SEG_ ; + } + + if (skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + } + + //printk("i= %d\n", i); + //rkdump(frag_addr, frag->size); + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(frag_addr))&0xFFFFFFFCUL), + (((u32)(frag->size))+3+ + (((u32)(frag_addr))&0x03UL))>>2); + // dwFreeSpace-=(frag->size+8); + + } + + dwFreeSpace-=skb->len+12*TxFrag+16; + dev_kfree_skb(skb); + + } + + } + + } + + //printk("finish.\n"); + + + if(Tx_GetTxStatusCount(privateData)>=30) + { + Tx_UpdateTxCounters(privateData); + } + + if(dwFreeSpacedwLanBase!=0); + SMSC_ASSERT(privateData->TxInitialized==true); + result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + if(result!=0x00800000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } else { + result&=TX_FIFO_INF_TSUSED_; + if(result!=0x00000000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } + return result; +} + +void Tx_UpdateTxCounters( + PPRIVATE_DATA privateData) +{ + + u32 dwTxStatus=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock(&(privateData->TxCounterLock)); + while((dwTxStatus=Tx_CompleteTx(privateData))!=0) + { + if(dwTxStatus&0x80000000UL) { + SMSC_WARNING("Packet tag reserved bit is high"); + privateData->stats.tx_errors++; + } else if(dwTxStatus&0x00007080UL) { + SMSC_WARNING("Tx Status reserved bits are high"); + privateData->stats.tx_errors++; + } else { + if(dwTxStatus&0x00008000UL) { + privateData->stats.tx_errors++; + } else { + privateData->stats.tx_packets++; + privateData->stats.tx_bytes+=(dwTxStatus>>16); + } + if(dwTxStatus&0x00000100UL) { + privateData->stats.collisions+=16; + privateData->stats.tx_aborted_errors+=1; + } else { + privateData->stats.collisions+= + ((dwTxStatus>>3)&0xFUL); + } + if(dwTxStatus&0x00000800UL) { + privateData->stats.tx_carrier_errors+=1; + } + if(dwTxStatus&0x00000200UL) { + privateData->stats.collisions++; + privateData->stats.tx_aborted_errors++; + } + } + } + spin_unlock(&(privateData->TxCounterLock)); +} + +void Tx_CompleteDma( + PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + + spin_lock(&(privateData->TxSkbLock)); + if(privateData->TxSkb) { + Platform_DmaComplete( + &(privateData->PlatformData), + privateData->dwTxDmaCh); + dev_kfree_skb(privateData->TxSkb); + privateData->TxSkb=NULL; + } + spin_unlock(&(privateData->TxSkbLock)); +} + + +void CalculateTxChecksumOffset( + struct sk_buff *skb, + int *csum_start_offset + ) +{ + unsigned int skbFragCnt; + + skbFragCnt = skb_shinfo(skb)->nr_frags + 1; + *csum_start_offset = skb->csum_offset; +} + + + + +void rkdump(unsigned char *p, unsigned short len) +{ + int i; + + for(i=0; idwRxDmaCh=dwRxDmaCh; + if(dwRxDmaCh>=TRANSFER_PIO) { + SMSC_TRACE("Rx will use PIO"); + Platform_GetFlowControlParameters( + &(privateData->PlatformData), + &(privateData->RxFlowParameters), + false); + } else { + SMSC_TRACE("Rx will use DMA Channel %d",dwRxDmaCh); + SMSC_ASSERT(Platform_IsValidDmaChannel(dwRxDmaCh)); + if(!Platform_DmaInitialize( + &(privateData->PlatformData), + dwRxDmaCh)) + { + SMSC_WARNING("Failed Platform_DmaInitialize, dwRxDmaCh=%u",dwRxDmaCh); + } + Platform_GetFlowControlParameters( + &(privateData->PlatformData), + &(privateData->RxFlowParameters), + true); + } + if(max_throughput!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.MaxThroughput=max_throughput; + } + if(max_packet_count!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.MaxPacketCount=max_packet_count; + } + if(packet_cost!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.PacketCost=packet_cost; + } + if(burst_period!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.BurstPeriod=burst_period; + } + if(privateData->RxFlowParameters.BurstPeriod==0) { + SMSC_WARNING("burst_period of 0 is not allowed"); + SMSC_WARNING(" resetting burst_period to 100"); + privateData->RxFlowParameters.BurstPeriod=100; + } + if(max_work_load!=0xFFFFFFFFUL) { + privateData->RxFlowMaxWorkLoad=max_work_load; + } else { + privateData->RxFlowMaxWorkLoad= + privateData->RxFlowParameters.MaxThroughput+ + (privateData->RxFlowParameters.MaxPacketCount* + privateData->RxFlowParameters.PacketCost); + } + privateData->RxFlowBurstMaxWorkLoad= + (privateData->RxFlowMaxWorkLoad* + privateData->RxFlowParameters.BurstPeriod)/1000; + if(int_deas!=0xFFFFFFFFUL) { + Lan_SetIntDeas(privateData,int_deas); + } else { + Lan_SetIntDeas(privateData,privateData->RxFlowParameters.IntDeas); + } + + + //Set RX COE + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW(privateData,VLAN1,ETH_P_8021Q,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + // privateData->RxVLanPkt=true; + + } + + + if (privateData->UseRxCsum) { + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwCoeCr=Mac_GetRegDW(privateData,COE_CR,keyCode); + dwCoeCr|=(RX_COE_EN | RX_COE_MODE); + Mac_SetRegDW(privateData,COE_CR,dwCoeCr,keyCode); + //printk("COE_CR2 = 0x%08x\n", Mac_GetRegDW(privateData,COE_CR,keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + + + } + + + + //initially the receiver is off + // a following link up detection will turn the receiver on + privateData->dwRxOffCount=1; + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_); + Rx_ReceiverOn(privateData, 0); + + privateData->dwRxDmaThreshold=dwDmaThreshold; + Lan_SetRDFL(privateData,0x01); + Lan_SetRSFL(privateData,0x00); + privateData->RxInterrupts=INT_EN_RSFL_EN_; + privateData->RxInterrupts|=INT_EN_RXE_EN_; + if(privateData->dwGeneration==0) { + privateData->RxInterrupts|=INT_EN_RDFL_EN_; + } else { + privateData->RxInterrupts|=INT_EN_RDFO_EN_; + } + privateData->RxInterrupts|=INT_EN_RXDFH_INT_EN_; + Lan_EnableInterrupt(privateData,privateData->RxInterrupts); + +} + +static void Rx_HandleOverrun(PPRIVATE_DATA privateData) +{ + if(privateData->dwGeneration==0) { + if(privateData->RxOverrun==false) { + Rx_ReceiverOff(privateData); + privateData->RxUnloadProgress= + (((((privateData->LastRxStatus1)&0x3FFF0000UL)>>16)+2+3)&0xFFFFFFFCUL); + if(privateData->dwRxDmaChRxUnloadProgress+= + (((((privateData->LastRxStatus2)&0x3FFF0000UL)>>16)+2+3)&0xFFFFFFFCUL); + } + privateData->RxUnloadPacketProgress=0; + privateData->RxOverrun=true; + privateData->RxOverrunCount++; + } + } else { + privateData->RxOverrunCount++; + } +} + +static void Rx_HandOffSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb) +{ + int result=0; + + skb->dev=privateData->dev; + skb->protocol= eth_type_trans(skb,privateData->dev); + + // #ifdef UseRxCsum + // WORD wHwCsum = 0; + // #endif + + //printk(" Handoff skb->len = 0x%08x\n",(u32) skb->len); + if (privateData->UseRxCsum) { + + WORD wHwCsum = *(WORD *)(skb->tail +4); + skb->csum = wHwCsum; + //printk(" HW csum = 0x%04x\n", skb->csum); + + } + + + if (privateData->UseRxCsum) + + skb->ip_summed = CHECKSUM_PARTIAL; + + else + skb->ip_summed = CHECKSUM_NONE; +#ifdef LINUX_2_6_OR_NEWER + if(rx_mode==PROCESSING_MODE_NAPI) { + result=netif_receive_skb(skb); + privateData->RxWorkLimit--; + privateData->RxPacketsReceived++; + if(privateData->RxWorkLimit<=0) { + privateData->RxCongested=true; + } + + } else { + result=netif_rx(skb);//hand off the Received packet to higher layer + } +#else + result=netif_rx(skb); +#endif + + // result=netif_rx(skb); + + switch(result) + { + case NET_RX_SUCCESS: + break; + case NET_RX_CN_LOW: + case NET_RX_CN_MOD: + case NET_RX_CN_HIGH: + case NET_RX_DROP: + privateData->RxCongested=true; + privateData->RxCongestedCount++; + break; + default: + privateData->RxCongested=true; + privateData->RxCongestedCount++; + SMSC_WARNING("Unknown return value from netif_rx, result=%d",result); + break; + } +} + +void Rx_CompleteMulticastUpdate (PPRIVATE_DATA privateData) +{ + u32 local_MACCR; + VL_KEY keyCode=0; + unsigned long dwIntFlags=0; + + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if (privateData->MulticastUpdatePending) { + SET_GPIO(GP_COMPLETE_MULTICAST_UPDATE); + Mac_SetRegDW(privateData,HASHH,privateData->HashHi,keyCode); + Mac_SetRegDW(privateData,HASHL,privateData->HashLo,keyCode); + local_MACCR = Mac_GetRegDW(privateData,MAC_CR,keyCode); + local_MACCR |= privateData->set_bits_mask; + local_MACCR &= ~(privateData->clear_bits_mask); + Mac_SetRegDW(privateData,MAC_CR,local_MACCR,keyCode); + Rx_ReceiverOn(privateData, keyCode); + privateData->MulticastUpdatePending = false; + CLEAR_GPIO(GP_COMPLETE_MULTICAST_UPDATE); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Rx_BeginMulticastUpdate (PPRIVATE_DATA privateData) +{ + u32 startTime, currentTime; + u32 timeout; + unsigned long flags; + + SET_GPIO(GP_BEGIN_MULTICAST_UPDATE); + + //NOTE: we can't rely on privateData->dwLinkSpeed because + // it updates only once per second and may be out dated. + + local_irq_save(flags); + Rx_ReceiverOff(privateData); + if(privateData->dwGeneration>0) { + //since this is concord or later there is no + // overrun processing that might turn off the receiver. + // there for we can rely on RxStop Int. + + //if the speed is 100Mb then lets poll rx stop to get the + // quickest response. + timeout = 200UL; + while ((timeout)&&(!(Lan_GetRegDW(INT_STS)&(INT_STS_RXSTOP_INT_)))) { + // wait 1 uSec + startTime=Lan_GetRegDW(FREE_RUN); + while (1) { + currentTime=Lan_GetRegDW(FREE_RUN); + if (currentTime-startTime >= 25UL) + break; + } + timeout--; + } + if(timeout==0) { + //this is probably a 10Mb link, therefore prepare + // interrupt for update later. + Lan_EnableInterrupt(privateData,INT_EN_RXSTOP_INT_EN_); + + // if this is a 10Mbps half duplex connection + // then Rx stop is only 99.6% reliable + // Therefor we must schedule Gpt callback as + // back up + + // using 18*(100uS) because we already waited 200uS + Gpt_ScheduleCallBack(privateData,GptCB_RxCompleteMulticast, 18UL); + } else { + //Rx is stopped + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_);//clear interrupt signal + Rx_CompleteMulticastUpdate(privateData); + } + } else { + // for generation 0 we can't rely on Rx stop because + // the receiver may have already been stopped due to + // overflow processing + + // for the same reason we can't just wait 200uS and + // check stopped status there for we must rely on GP timer + // and we must assume a worse case of 10Mb speed + + Gpt_ScheduleCallBack(privateData,GptCB_RxCompleteMulticast, 20UL); + } + local_irq_restore (flags); + CLEAR_GPIO(GP_BEGIN_MULTICAST_UPDATE); +} + +static u32 Rx_PopRxStatus( + PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(RX_FIFO_INF); + if((privateData->RxCongested==false)|| + ((privateData->RxCongested==true)&&((result&0x00FF0000UL)==0UL))) + { + if(result&0x00FF0000UL) { + u32 dwIntSts=Lan_GetRegDW(INT_STS); + if(privateData->dwGeneration==0) { + if(dwIntSts&INT_STS_RDFL_) { + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_HandleOverrun(privateData); + } + } else { + if(dwIntSts&INT_STS_RDFO_) { + Lan_SetRegDW(INT_STS,INT_STS_RDFO_); + Rx_HandleOverrun(privateData); + } + } + if((privateData->RxFlowControlActive==false)|| + ((privateData->RxFlowControlActive==true)&& + (privateData->RxFlowBurstActive==true))) + { + //Rx status is available, read it + result=Lan_GetRegDW(RX_STATUS_FIFO); + privateData->RxStatusDWReadCount++; + privateData->LastRxStatus3= + privateData->LastRxStatus2; + privateData->LastRxStatus2= + privateData->LastRxStatus1; + privateData->LastRxStatus1=result; + + if(privateData->RxOverrun) { + u32 dwPacketLength=((result&0x3FFF0000UL)>>16); + u32 dwByteCount=((dwPacketLength+2+3)&0xFFFFFFFCUL); + if((privateData->RxUnloadProgress+dwByteCount)>= + ((privateData->RxMaxDataFifoSize)-16)) + { + //This is the packet that crosses the corruption point + // so just ignore it and complete the overrun processing. + result=0; + goto FINISH_OVERRUN_PROCESSING; + } + privateData->RxUnloadProgress+=dwByteCount; + privateData->RxUnloadPacketProgress++; + } + + privateData->RxFlowCurrentThroughput+= + ((((result&0x3FFF0000UL)>>16)-4UL)); + privateData->RxFlowCurrentPacketCount++; + privateData->RxFlowCurrentWorkLoad+= + ((((result&0x3FFF0000UL)>>16)-4UL)+privateData->RxFlowParameters.PacketCost); + if(privateData->RxFlowControlActive) { + privateData->RxFlowBurstWorkLoad+= + ((((result&0x3FFF0000UL)>>16)-4UL)+privateData->RxFlowParameters.PacketCost); + if(privateData->RxFlowBurstWorkLoad>= + privateData->RxFlowBurstMaxWorkLoad) + { + privateData->RxFlowBurstActive=false; + Lan_DisableInterrupt(privateData,privateData->RxInterrupts); + } + } + } else { + result=0; + } + } + else + { + if(privateData->RxOverrun) { + u32 timeOut; + u32 temp; +FINISH_OVERRUN_PROCESSING: + temp=0; + { + timeOut=2000; + while((timeOut>0)&&(!(Lan_GetRegDW(INT_STS)&(INT_STS_RXSTOP_INT_)))) { + udelay(1); + timeOut--; + } + if(timeOut==0) { + // privateData->RxStopTimeOutCount++; + // PULSE_GPIO(GP_TX,1); + SMSC_WARNING("Timed out waiting for Rx to Stop\n"); + } + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_); + } + + if(privateData->dwRxDmaChRxSkb) { + Platform_DmaComplete( + &(privateData->PlatformData), + privateData->dwRxDmaCh); + + Rx_HandOffSkb(privateData,privateData->RxSkb); + privateData->RxSkb=NULL; + } + } + + temp=Lan_GetRegDW(RX_CFG); + Lan_SetRegDW(RX_CFG,(temp&0x3FFFFFFFUL)); + timeOut=10000000; + Lan_SetBitsDW(RX_CFG,RX_CFG_RX_DUMP_); + while((timeOut>0)&&(Lan_GetRegDW(RX_CFG)&(RX_CFG_RX_DUMP_))) { + udelay(1); + timeOut--; + } + if(timeOut==0) { + SMSC_WARNING("Timed out waiting for Rx Dump to complete\n"); + } + Lan_SetRegDW(RX_CFG,temp); + + privateData->RxDumpCount++; + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_ReceiverOn(privateData, 0); + privateData->RxOverrun=false; + } + result=0; + privateData->LastReasonForReleasingCPU=1;//Status FIFO Empty + } + } else { + //disable and reenable the INT_EN + // This will allow the deassertion interval to begin + u32 temp=Lan_GetRegDW(INT_EN); + Lan_SetRegDW(INT_EN,0); + Lan_SetRegDW(INT_EN,temp); + result=0; + privateData->LastReasonForReleasingCPU=2;//High Congestion + } + return result; +} + +void Rx_CountErrors(PPRIVATE_DATA privateData,u32 dwRxStatus) +{ + bool crcError=false; + if(dwRxStatus&0x00008000UL) { + privateData->stats.rx_errors++; + if(dwRxStatus&0x00000002UL) { + privateData->stats.rx_crc_errors++; + crcError=true; + } + } + if(!crcError) { + if((dwRxStatus&0x00001020UL)==0x00001020UL) { + //Frame type indicates length, and length error is set + privateData->stats.rx_length_errors++; + } + if(dwRxStatus&RX_STS_MCAST_) { + privateData->stats.multicast++; + } + } +} + +void Rx_FastForward(PPRIVATE_DATA privateData,u32 dwDwordCount) +{ + privateData->RxFastForwardCount++; + if((dwDwordCount>=4) + && ( + (((privateData->dwIdRev&0x0000FFFFUL)==0x00000000UL) + && (privateData->dwFpgaRev>=0x36)) + || + ((privateData->dwIdRev&0x0000FFFFUL)!=0UL) + ) + ) + { + u32 dwTimeOut=500; + Lan_SetRegDW(RX_DP_CTRL,(dwDwordCount|RX_DP_CTRL_FFWD_BUSY_)); + while((dwTimeOut)&&(Lan_GetRegDW(RX_DP_CTRL)& + RX_DP_CTRL_FFWD_BUSY_)) + { + udelay(1); + dwTimeOut--; + } + if(dwTimeOut==0) { + + SMSC_WARNING("timed out waiting for RX FFWD to finish, RX_DP_CTRL=0x%08X", + Lan_GetRegDW(RX_DP_CTRL)); + } + } else { + while(dwDwordCount) { + u32 dwTemp=Lan_GetRegDW(RX_DATA_FIFO); + dwTemp=dwTemp; + dwDwordCount--; + } + } +} + +//Rx_ReceiverOff, and Rx_ReceiverOn use a reference counter +// because they are used in both the Rx code and the link management count +void Rx_ReceiverOff(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(privateData->dwRxOffCount==0) { + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + if(!(dwMacCr&MAC_CR_RXEN_)) { + SMSC_WARNING("Rx_ReceiverOff: Receiver is already Off"); + } + dwMacCr&=(~MAC_CR_RXEN_); + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + //CLEAR_GPIO(GP_RX); + } + privateData->dwRxOffCount++; + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +//Rx_ReceiverOff, and Rx_ReceiverOn use a reference counter +// because they are used in both the Rx code and the link management count +void Rx_ReceiverOn(PPRIVATE_DATA privateData, VL_KEY callerKeyCode) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=0; + + if (callerKeyCode == 0) { + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + } + else { + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),callerKeyCode)); + keyCode = callerKeyCode; + } + if(privateData->dwRxOffCount>0) { + privateData->dwRxOffCount--; + if(privateData->dwRxOffCount==0) { + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + if(dwMacCr&MAC_CR_RXEN_) { + SMSC_WARNING("Rx_ReceiverOn: Receiver is already on"); + } + dwMacCr|=MAC_CR_RXEN_; + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + //SET_GPIO(GP_RX); + } + } else { + SMSC_ASSERT(false); + } + if (callerKeyCode == 0) { + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } +} + +void Rx_ProcessPackets(PPRIVATE_DATA privateData) +{ + u32 dwRxStatus=0; + PPLATFORM_DATA platformData=NULL; + + /* +#ifdef UseRxCsum +WORD wHwCsum = 0; +#endif +*/ + + // SET_GPIO(GP_RX); + + privateData->RxCongested=false; + platformData=&(privateData->PlatformData); + if(privateData->dwRxDmaCh>=TRANSFER_PIO) { + //Use PIO only + + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_); + while((dwRxStatus=Rx_PopRxStatus(privateData))!=0) + { + u32 dwPacketLength=((dwRxStatus&0x3FFF0000UL)>>16); + + //printk("dwPacketLength = 0x%08x\n", (u32) dwPacketLength); + //printk("dwRxStatus = 0x%08x\n", (u32) dwRxStatus); + + Rx_CountErrors(privateData,dwRxStatus); + + + if((dwRxStatus&RX_STS_ES_)==0) + //||(((dwRxStatus&0x00001080)==0x00001080)&&(privateData->RxVLanPkt==true))) + { + struct sk_buff *skb=NULL; + skb=dev_alloc_skb(dwPacketLength+2); + if(skb!=NULL) { + skb->data=skb->head; + skb->tail=skb->head; + skb_reserve(skb,2); // align IP on 16B boundary + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + //update counters + privateData->stats.rx_packets++; + + + if (privateData->UseRxCsum) + { + privateData->stats.rx_bytes+=(dwPacketLength-4-2); + + } + else + { + privateData->stats.rx_bytes+=(dwPacketLength-4); + } + + + privateData->RxPacketReadCount++; + privateData->RxPioReadCount++; + privateData->RxDataDWReadCount+= + (dwPacketLength+2+3)>>2; + + + + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(skb->head)), + (dwPacketLength+2+3)>>2); + + + //printk("Rx skb->len = 0x%08x\n", (u32) skb->len); + + Rx_HandOffSkb(privateData,skb); + continue; + } else { + SMSC_WARNING("Unable to allocate sk_buff for RX Packet, in PIO path"); + privateData->stats.rx_dropped++; + } + } + //if we get here then the packet is to be read + // out of the fifo and discarded + //printk("fast forward\n"); + dwPacketLength+=(2+3); + dwPacketLength>>=2; + Rx_FastForward(privateData,dwPacketLength); + } + } + else { + + //Use DMA and PIO + u32 dwDmaCh=privateData->dwRxDmaCh; + //struct sk_buff *dmaSkb=NULL;//use privateData->RxDmaSkb + DMA_XFER dmaXfer; + dmaXfer.dwLanReg=privateData->dwLanBase+RX_DATA_FIFO; + dmaXfer.pdwBuf=NULL;// this will be reset per dma request + dmaXfer.dwDmaCh=dwDmaCh; + dmaXfer.dwDwCnt=0;// this will be reset per dma request + dmaXfer.fMemWr=true; + while((dwRxStatus=Rx_PopRxStatus(privateData))!=0) + { + u32 dwPacketLength; +RUN_AGAIN: + Rx_CountErrors(privateData,dwRxStatus); + dwPacketLength=((dwRxStatus&0x3FFF0000UL)>>16); + + + if((dwRxStatus&RX_STS_ES_)==0) + { + struct sk_buff *skb=dev_alloc_skb(dwPacketLength+2*PLATFORM_CACHE_LINE_BYTES); + if(skb!=NULL) + { + skb->data=skb->head; + skb->tail=skb->head; + + //align IP on cache line boundary + privateData->stats.rx_packets++; + privateData->stats.rx_bytes+=(dwPacketLength-4UL); + if(dwPacketLength>=privateData->dwRxDmaThreshold) + { + //use DMA + //printk("Rx using DMA\n"); + u32 dwDwordCount; + skb_reserve(skb,PLATFORM_CACHE_LINE_BYTES-14); + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + + // skb_put(skb,dwPacketLength-4UL); + dwDwordCount=((dwPacketLength+ + (PLATFORM_CACHE_LINE_BYTES-14)+ + PLATFORM_CACHE_LINE_BYTES-1)& + (~(PLATFORM_CACHE_LINE_BYTES-1)))>>2; + Platform_CacheInvalidate( + platformData, + skb->head,dwDwordCount<<2); + dmaXfer.pdwBuf=(u32 *)(skb->head); + dmaXfer.dwDwCnt=dwDwordCount; + privateData->RxDataDWReadCount+=dwDwordCount; + privateData->RxPacketReadCount++; + privateData->RxDmaReadCount++; + if(privateData->RxSkb) + Platform_DmaComplete(platformData,dwDmaCh); + + //set end alignment and offset + switch(PLATFORM_CACHE_LINE_BYTES) + { + //case 4: Lan_SetRegDW(RX_CFG,0x00000200UL);break; + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + case 16:Lan_SetRegDW(RX_CFG, RX_CFG_RX_END_ALGN16_ |RX_CFG_RXDOFF_2_ );break; + case 32:Lan_SetRegDW(RX_CFG, RX_CFG_RX_END_ALGN32_ |RX_CFG_RXDOFF_18_);break; + default:SMSC_ASSERT(false); + } + if(!Platform_DmaStartXfer(platformData,&dmaXfer)) { + SMSC_WARNING("Failed Platform_DmaStartXfer"); + } + + + + + if(privateData->RxSkb) { + + Rx_HandOffSkb(privateData,privateData->RxSkb); + } + privateData->RxSkb=skb; + } + else + { + //use PIO + + // printk("Rx using PIO\n"); + if(privateData->RxSkb) { + Platform_DmaComplete(platformData,dwDmaCh); + Rx_HandOffSkb(privateData,privateData->RxSkb); + } + + privateData->RxSkb=skb; + + skb_reserve(skb,2); + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + + // skb_put(skb,dwPacketLength-4UL); + //set end alignment and offset + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG, RX_CFG_RXDOFF_2_);//4 byte end alignment + privateData->RxPacketReadCount++; + privateData->RxPioReadCount++; + privateData->RxDataDWReadCount+= + ((dwPacketLength+2+3)>>2); + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(skb->head)), + (dwPacketLength+2+3)>>2); + + + + } + continue; + } + else + { + SMSC_WARNING("Unable to allocate sk_buff for RX Packet, in DMA path"); + privateData->stats.rx_dropped++; + } + } + //if we get here then the packet is to be read + // out of the fifo and discarded + if(privateData->RxSkb) Platform_DmaComplete(platformData,dwDmaCh); + //delay returning the dmaSkb to OS till later + dwPacketLength+=(2+3); + dwPacketLength>>=2; + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_);//4 byte end alignment + Rx_FastForward(privateData,dwPacketLength); + } + if(privateData->RxSkb) { + //while waiting for dma to complete, + // check if another packet arrives + u32 dwTimeOut=1000000; + while((Platform_DmaGetDwCnt(platformData,dwDmaCh))&& + (dwTimeOut)) + { + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + udelay(1); + dwTimeOut--; + } + if(dwTimeOut==0) { + SMSC_WARNING("Timed out while waiting for final Dma to complete"); + } + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + + + Rx_HandOffSkb(privateData,privateData->RxSkb); + privateData->RxSkb=NULL; + + //check one last time for another packet. + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + } + } + Lan_SetRegDW(INT_STS,INT_STS_RSFL_); + // CLEAR_GPIO(GP_RX); +} + +void Rx_ProcessPacketsTasklet(unsigned long data) +{ + PPRIVATE_DATA privateData=(PPRIVATE_DATA)Rx_TaskletParameter; + data=data;//make lint happy + if(privateData==NULL) { + SMSC_WARNING("Rx_ProcessPacketsTasklet(privateData==NULL)"); + return; + } + Rx_ProcessPackets(privateData); + Lan_EnableIRQ(privateData); +} + +#ifdef LINUX_2_6_OR_NEWER +/* +int Smsc9118_rx_poll(struct net_device *dev,int * budget) +{ + int result=0; + int limit=0; + + PPRIVATE_DATA privateData=NULL; + SMSC_ASSERT(dev!=NULL); + SMSC_ASSERT(budget!=NULL); + privateData=((PPRIVATE_DATA)(dev->ml_priv)); + SMSC_ASSERT(privateData!=NULL); + + privateData->RxWorkLimit=dev->quota; + if((privateData->RxWorkLimit)>(*budget)) { + privateData->RxWorkLimit=(*budget); + } + + limit=privateData->RxWorkLimit; + + privateData->RxPacketsReceived=0; + // privateData->RxDone=false; + Rx_ProcessPackets(privateData); + + dev->quota-=privateData->RxPacketsReceived; + (*budget)-=privateData->RxPacketsReceived; + + if(privateData->RxPacketsReceived < limit) { + netif_rx_complete(dev); + Lan_EnableIRQ(privateData); + } else { + result=1; + } + + return result; +} +*/ +#endif + + + + + +bool Rx_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + + privateData->LastReasonForReleasingCPU=0; + + if(dwIntSts&INT_STS_RXE_) { + SMSC_TRACE("Rx_HandleInterrupt: RXE signalled"); + privateData->stats.rx_errors++; + Lan_SetRegDW(INT_STS,INT_STS_RXE_); + result=true; + } + + if(dwIntSts&INT_STS_RXDFH_INT_) { + privateData->stats.rx_dropped+=Lan_GetRegDW(RX_DROP); + Lan_SetRegDW(INT_STS,INT_STS_RXDFH_INT_); + result=true; + } + + if(privateData->dwGeneration==0) { + if(dwIntSts&(INT_STS_RDFL_)) { + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_HandleOverrun(privateData); + result=true; + } + } else { + if(dwIntSts&(INT_STS_RDFO_)) { + Lan_SetRegDW(INT_STS,INT_STS_RDFO_); + Rx_HandleOverrun(privateData); + result=true; + } + } + + if((!(dwIntSts&INT_STS_RSFL_))&&(privateData->RxOverrun==false)) { + return result; + } + result=true; + + if(privateData->MeasuringRxThroughput==false) { + privateData->MeasuringRxThroughput=true; + Gpt_ScheduleCallBack(privateData,GptCB_MeasureRxThroughput,1000); + privateData->RxFlowCurrentThroughput=0; + privateData->RxFlowCurrentPacketCount=0; + privateData->RxFlowCurrentWorkLoad=0; + } + + +#ifdef LINUX_2_6_OR_NEWER + if(rx_mode==PROCESSING_MODE_TASKLET) { + Lan_DisableIRQ(privateData); + Rx_TaskletParameter=(unsigned long)privateData; + tasklet_schedule(&Rx_Tasklet); + }else if (rx_mode==PROCESSING_MODE_NAPI) { + /* + Lan_DisableIRQ(privateData); + netif_rx_schedule(privateData->dev); + */ + }else { + Rx_ProcessPackets(privateData); + } +#else + if(rx_mode==PROCESSING_MODE_TASKLET) { + Lan_DisableIRQ(privateData); + Rx_TaskletParameter=(unsigned long)privateData; + tasklet_schedule(&Rx_Tasklet); + }else { + Rx_ProcessPackets(privateData); + } +#endif + + return result; +} + +bool RxStop_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + + if(dwIntSts&INT_STS_RXSTOP_INT_) { + result=true; + Gpt_CancelCallBack (privateData, GptCB_RxCompleteMulticast); + Rx_CompleteMulticastUpdate (privateData); + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_); + Lan_DisableInterrupt(privateData,INT_EN_RXSTOP_INT_EN_); + } + return result; +} + +//returns hash bit number for given MAC address +//example: +// 01 00 5E 00 00 01 -> returns bit number 31 +static u32 Rx_Hash(BYTE addr[6]) +{ + int i; + u32 crc=0xFFFFFFFFUL; + u32 poly=0xEDB88320UL; + u32 result=0; + for(i=0;i<6;i++) + { + int bit; + u32 data=((u32)addr[i]); + for(bit=0;bit<8;bit++) + { + u32 p = (crc^((u32)data))&1UL; + crc >>= 1; + if(p!=0) crc ^= poly; + data >>=1; + } + } + result=((crc&0x01UL)<<5)| + ((crc&0x02UL)<<3)| + ((crc&0x04UL)<<1)| + ((crc&0x08UL)>>1)| + ((crc&0x10UL)>>3)| + ((crc&0x20UL)>>5); + return result; +} + +void Rx_SetMulticastList( + struct net_device *dev) +{ + PPRIVATE_DATA privateData=NULL; + VL_KEY keyCode=0; + unsigned long dwIntFlags=0; + SMSC_ASSERT(dev!=NULL); + + privateData=((PPRIVATE_DATA)(dev->ml_priv)); + SMSC_ASSERT(privateData!=NULL); + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + if(dev->flags & IFF_PROMISC) { + // SMSC_TRACE("Promiscuous Mode Enabled"); + privateData->set_bits_mask = MAC_CR_PRMS_; + privateData->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + goto PREPARE; + } + + if(dev->flags & IFF_ALLMULTI) { + // SMSC_TRACE("Receive all Multicast Enabled"); + privateData->set_bits_mask = MAC_CR_MCPAS_; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); + + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + goto PREPARE; + } + + + if(dev->mc_count>0) { + u32 dwHashH=0; + u32 dwHashL=0; + u32 dwCount=0; + struct dev_mc_list *mc_list=dev->mc_list; + + privateData->set_bits_mask = MAC_CR_HPFILT_; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); + + while(mc_list!=NULL) { + dwCount++; + if((mc_list->dmi_addrlen)==6) { + u32 dwMask=0x01UL; + u32 dwBitNum=Rx_Hash(mc_list->dmi_addr); + // SMSC_TRACE("Multicast: enable dwBitNum=%d,addr=%02X %02X %02X %02X %02X %02X", + // dwBitNum, + // ((BYTE *)(mc_list->dmi_addr))[0], + // ((BYTE *)(mc_list->dmi_addr))[1], + // ((BYTE *)(mc_list->dmi_addr))[2], + // ((BYTE *)(mc_list->dmi_addr))[3], + // ((BYTE *)(mc_list->dmi_addr))[4], + // ((BYTE *)(mc_list->dmi_addr))[5]); + dwMask<<=(dwBitNum&0x1FUL); + if(dwBitNum&0x20UL) { + dwHashH|=dwMask; + } else { + dwHashL|=dwMask; + } + } else { + SMSC_WARNING("dmi_addrlen!=6"); + } + mc_list=mc_list->next; + } + if(dwCount!=((u32)(dev->mc_count))) { + SMSC_WARNING("dwCount!=dev->mc_count"); + } + // SMSC_TRACE("Multicast: HASHH=0x%08X,HASHL=0x%08X",dwHashH,dwHashL); + privateData->HashHi = dwHashH; + privateData->HashLo = dwHashL; + } + else + { + privateData->set_bits_mask = 0L; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + + // SMSC_TRACE("Receive own packets only."); + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + } + +PREPARE: + if(privateData->dwGeneration<=1) { + if (privateData->MulticastUpdatePending == false) { + privateData->MulticastUpdatePending = true; + // prepare to signal software interrupt + Lan_SignalSoftwareInterrupt(privateData); + } + else { + // Rx_CompleteMulticastUpdate has not yet been called + // therefore these latest settings will be used instead + } + } else { + u32 local_MACCR; + Mac_SetRegDW(privateData,HASHH,privateData->HashHi,keyCode); + Mac_SetRegDW(privateData,HASHL,privateData->HashLo,keyCode); + local_MACCR = Mac_GetRegDW(privateData,MAC_CR,keyCode); + local_MACCR |= privateData->set_bits_mask; + local_MACCR &= ~(privateData->clear_bits_mask); + Mac_SetRegDW(privateData,MAC_CR,local_MACCR,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + return; +} + +void Eeprom_EnableAccess(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + if(debug_mode&0x04UL) { + Lan_SetRegDW(GPIO_CFG,(g_GpioSetting&0xFF0FFFFFUL)); + } else { + Lan_ClrBitsDW(GPIO_CFG,0x00F00000UL); + } + udelay(100); +} + +void Eeprom_DisableAccess(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + if(debug_mode&0x04UL) { + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +} + +bool Eeprom_IsMacAddressLoaded(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_MAC_ADDR_LOADED_)?true:false; +} + +bool Eeprom_IsBusy(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_EPC_BUSY_)?true:false; +} + +bool Eeprom_Timeout(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_EPC_TIMEOUT_)?true:false; +} + +bool Eeprom_ReadLocation( + PPRIVATE_DATA privateData, + BYTE address, BYTE * data) +{ + u32 timeout=100000; + u32 temp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(data!=NULL); + if((temp=Lan_GetRegDW(E2P_CMD))&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_ReadLocation: Busy at start, E2P_CMD=0x%08X",temp); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_READ_|((u32)address))); + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + (*data)=(BYTE)(Lan_GetRegDW(E2P_DATA)); + return true; +} + +bool Eeprom_EnableEraseAndWrite( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_EnableEraseAndWrite: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_EWEN_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_DisableEraseAndWrite( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_DisableEraseAndWrite: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_EWDS_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_WriteLocation( + PPRIVATE_DATA privateData,BYTE address,BYTE data) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_WriteLocation: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_DATA,((u32)data)); + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_WRITE_|((u32)address))); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_EraseAll( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_EraseAll: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_ERAL_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_Reload( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_Reload: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_RELOAD_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_SaveMacAddress( + PPRIVATE_DATA privateData, + u32 dwHi16,u32 dwLo32) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + Eeprom_EnableAccess(privateData); + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_EraseAll(privateData)) goto DONE; + if(privateData->dwGeneration==0) { + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,0,0xA5)) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,1,LOBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,2,HIBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,3,LOBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,4,HIBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,5,LOBYTE(LOWORD(dwHi16)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,6,HIBYTE(LOWORD(dwHi16)))) goto DONE; + } else { + if(!Eeprom_WriteLocation(privateData,0,0xA5)) goto DONE; + if(!Eeprom_WriteLocation(privateData,1,LOBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,2,HIBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,3,LOBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,4,HIBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,5,LOBYTE(LOWORD(dwHi16)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,6,HIBYTE(LOWORD(dwHi16)))) goto DONE; + } + if(!Eeprom_DisableEraseAndWrite(privateData)) goto DONE; + + if(!Eeprom_Reload(privateData)) goto DONE; + if(!Eeprom_IsMacAddressLoaded(privateData)) goto DONE; + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwHi16!=Mac_GetRegDW(privateData,ADDRH,keyCode)) goto DONE; + if(dwLo32!=Mac_GetRegDW(privateData,ADDRL,keyCode)) goto DONE; + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + result=true; +DONE: + Eeprom_DisableAccess(privateData); + return result; +} + +volatile u32 g_GpioSetting=0x00000000UL; +#ifdef USE_LED1_WORK_AROUND +volatile u32 g_GpioSettingOriginal=0x00000000UL; +#endif + +bool Lan_Initialize( + PPRIVATE_DATA privateData, + u32 dwIntCfg, + u32 dwTxFifSz, + u32 dwAfcCfg) +{ + bool result=false; + u32 dwTimeOut=0; + u32 dwTemp=0; + u32 dwResetCount=3; + + SMSC_TRACE("-->Lan_Initialize(dwIntCfg=0x%08X)",dwIntCfg); + SMSC_ASSERT(privateData!=NULL); + + //Reset the LAN9118 + if(privateData->dwGeneration>0) { + dwResetCount=1; + } + while(dwResetCount>0) { + Lan_SetRegDW(HW_CFG,HW_CFG_SRST_); + dwTimeOut=1000000; + do { + udelay(10); + dwTemp=Lan_GetRegDW(HW_CFG); + dwTimeOut--; + } while((dwTimeOut>0)&&(dwTemp&HW_CFG_SRST_)); + if(dwTemp&HW_CFG_SRST_) { + SMSC_WARNING(" Failed to complete reset."); + goto DONE; + } + dwResetCount--; + } + + SMSC_ASSERT(dwTxFifSz>=0x00020000UL); + SMSC_ASSERT(dwTxFifSz<=0x000E0000UL); + SMSC_ASSERT((dwTxFifSz&(~HW_CFG_TX_FIF_SZ_))==0); + Lan_SetRegDW(HW_CFG,dwTxFifSz); + privateData->RxMaxDataFifoSize=0; + switch(dwTxFifSz>>16) { + case 2:privateData->RxMaxDataFifoSize=13440;break; + case 3:privateData->RxMaxDataFifoSize=12480;break; + case 4:privateData->RxMaxDataFifoSize=11520;break; + case 5:privateData->RxMaxDataFifoSize=10560;break; + case 6:privateData->RxMaxDataFifoSize=9600;break; + case 7:privateData->RxMaxDataFifoSize=8640;break; + case 8:privateData->RxMaxDataFifoSize=7680;break; + case 9:privateData->RxMaxDataFifoSize=6720;break; + case 10:privateData->RxMaxDataFifoSize=5760;break; + case 11:privateData->RxMaxDataFifoSize=4800;break; + case 12:privateData->RxMaxDataFifoSize=3840;break; + case 13:privateData->RxMaxDataFifoSize=2880;break; + case 14:privateData->RxMaxDataFifoSize=1920;break; + default:SMSC_ASSERT(false);break; + } + + if(dwAfcCfg==0xFFFFFFFF) { + switch(dwTxFifSz) { + + //AFC_HI is about ((Rx Data Fifo Size)*2/3)/64 + //AFC_LO is AFC_HI/2 + //BACK_DUR is about 5uS*(AFC_LO) rounded down + case 0x00020000UL://13440 Rx Data Fifo Size + dwAfcCfg=0x008C46AF;break; + case 0x00030000UL://12480 Rx Data Fifo Size + dwAfcCfg=0x0082419F;break; + case 0x00040000UL://11520 Rx Data Fifo Size + + dwAfcCfg=0x00783C9F;break; + case 0x00050000UL://10560 Rx Data Fifo Size + // dwAfcCfg=0x006E378F;break; + dwAfcCfg=0x006E374F;break; + case 0x00060000UL:// 9600 Rx Data Fifo Size + dwAfcCfg=0x0064328F;break; + case 0x00070000UL:// 8640 Rx Data Fifo Size + dwAfcCfg=0x005A2D7F;break; + case 0x00080000UL:// 7680 Rx Data Fifo Size + dwAfcCfg=0x0050287F;break; + case 0x00090000UL:// 6720 Rx Data Fifo Size + dwAfcCfg=0x0046236F;break; + case 0x000A0000UL:// 5760 Rx Data Fifo Size + dwAfcCfg=0x003C1E6F;break; + case 0x000B0000UL:// 4800 Rx Data Fifo Size + dwAfcCfg=0x0032195F;break; + + //AFC_HI is ~1520 bytes less than RX Data Fifo Size + //AFC_LO is AFC_HI/2 + //BACK_DUR is about 5uS*(AFC_LO) rounded down + case 0x000C0000UL:// 3840 Rx Data Fifo Size + dwAfcCfg=0x0024124F;break; + case 0x000D0000UL:// 2880 Rx Data Fifo Size + dwAfcCfg=0x0015073F;break; + case 0x000E0000UL:// 1920 Rx Data Fifo Size + dwAfcCfg=0x0006032F;break; + default:SMSC_ASSERT(false);break; + } + } + Lan_SetRegDW(AFC_CFG,(dwAfcCfg&0xFFFFFFF0UL)); + + //make sure EEPROM has finished loading before setting GPIO_CFG + dwTimeOut=1000; + while((dwTimeOut>0)&&(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) { + udelay(5); + dwTimeOut--; + } + if(dwTimeOut==0) { + SMSC_WARNING("Lan_Initialize: Timed out waiting for EEPROM busy bit to clear\n"); + } + + if(debug_mode&0x04UL) { + if(OLD_REGISTERS(privateData)) + { + g_GpioSetting=0x00270700UL; + } else { + g_GpioSetting=0x00670700UL; + } + } else { + g_GpioSetting = 0x70070000UL; + } + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + + //initialize interrupts + Lan_SetRegDW(INT_EN,0); + Lan_SetRegDW(INT_STS,0xFFFFFFFFUL); + dwIntCfg|=INT_CFG_IRQ_EN_; + Lan_SetRegDW(INT_CFG,dwIntCfg); + + Vl_InitLock(&(privateData->MacPhyLock)); + spin_lock_init(&(privateData->IntEnableLock)); + privateData->LanInitialized=true; + + result=true; + +DONE: + SMSC_TRACE("<--Lan_Initialize"); + return result; +} + +void Lan_EnableInterrupt(PPRIVATE_DATA privateData,u32 dwIntEnMask) +{ + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + Lan_SetBitsDW(INT_EN,dwIntEnMask); + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_DisableInterrupt(PPRIVATE_DATA privateData,u32 dwIntEnMask) +{ + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + Lan_ClrBitsDW(INT_EN,dwIntEnMask); + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +//Spin locks for the following functions have been commented out +// because at this time they are not necessary. +//These function are +// Lan_SetTDFL +// Lan_SetTSFL +// Lan_SetRDFL +// Lan_SetRSFL +//Both the Rx and Tx side of the driver use the FIFO_INT, +// but the Rx side only touches is during initialization, +// so it is sufficient that Tx side simple preserve the Rx setting + +void Lan_SetTDFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0x00FFFFFFUL; + temp|=((u32)level)<<24; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetTSFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFF00FFFFUL; + temp|=((u32)level)<<16; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetRDFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFFFF00FFUL; + temp|=((u32)level)<<8; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetRSFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFFFFFF00UL; + temp|=((u32)level); + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_EnableIRQ(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_SetBitsDW(INT_CFG,INT_CFG_IRQ_EN_); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_DisableIRQ(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_ClrBitsDW(INT_CFG,INT_CFG_IRQ_EN_); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetIntDeas(PPRIVATE_DATA privateData, u32 dwIntDeas) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_ClrBitsDW(INT_CFG,INT_CFG_INT_DEAS_); + Lan_SetBitsDW(INT_CFG,(dwIntDeas<<24)); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SignalSoftwareInterrupt(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + privateData->SoftwareInterruptSignal=false; + Lan_EnableInterrupt(privateData,INT_EN_SW_INT_EN_); +} + +bool Lan_HandleSoftwareInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + if(dwIntSts&INT_STS_SW_INT_) { + SMSC_TRACE("Got SW Interrupt (privateData=%08X)", (u32)privateData); + SMSC_ASSERT(privateData!=NULL); + Lan_DisableInterrupt(privateData,INT_EN_SW_INT_EN_); + Lan_SetRegDW(INT_STS,INT_STS_SW_INT_); + privateData->SoftwareInterruptSignal=true; + if (privateData->MulticastUpdatePending) { + Rx_BeginMulticastUpdate (privateData); + } + return true; + } + return false; +} + +typedef struct _SHOW_REG +{ + char szName[20]; + u32 dwOffset; +} SHOW_REG; +/* +FUNCTION: Lan_ShowRegs +This function is used to display the registers. +Except the phy. +*/ +void Lan_ShowRegs(PPRIVATE_DATA privateData) +{ + // Make these const struct's static to keep them off the stack. + // Otherwise, gcc will try to use _memcpy() to initialize them, + // which will *NOT* work in our RunTime environment. + static const SHOW_REG sysCsr[] = { + { "ID_REV", 0x50UL }, + { "INT_CFG", 0x54UL }, + { "INT_STS", 0x58UL }, + { "INT_EN", 0x5CUL }, + { "DMA_CFG", 0x60UL }, + { "BYTE_TEST", 0x64UL }, + { "FIFO_INT", 0x68UL }, + { "RX_CFG", 0x6CUL }, + { "TX_CFG", 0x70UL }, + { "HW_CFG", 0x74UL }, + { "RX_DP_CTRL", 0x78UL }, + { "RX_FIFO_INF", 0x7CUL }, + { "TX_FIFO_INF", 0x80UL }, + { "PMT_CTRL", 0x84UL }, + { "GPIO_CFG", 0x88UL }, + { "GPT_CFG", 0x8CUL }, + { "GPT_CNT", 0x90UL }, + { "FPGA_REV", 0x94UL }, + { "WORD_SWAP", 0x98UL }, + { "FREE_RUN", 0x9CUL }, + { "RX_DROP", 0xA0UL }, + { "MAC_CSR_CMD", 0xA4UL }, + { "MAC_CSR_DATA", 0xA8UL }, + { "AFC_CFG", 0xACUL }, + { "E2P_CMD", 0xB0UL }, + { "E2P_DATA", 0xB4UL }, + { "TEST_REG_A", 0xC0UL }}; + + static const SHOW_REG macCsr[] = { + { "MAC_CR", MAC_CR }, + { "ADDRH", ADDRH }, + { "ADDRL", ADDRL }, + { "HASHH", HASHH }, + { "HASHL", HASHL }, + { "MII_ACC", MII_ACC }, + { "MII_DATA", MII_DATA }, + { "FLOW", FLOW }, + { "VLAN1", VLAN1 }, + { "VLAN2", VLAN2 }, + { "WUFF", WUFF }, + { "WUCSR", WUCSR }}; + + int i, iNumSysRegs, iNumMacRegs; + u32 dwOldMacCmdReg, dwOldMacDataReg; + + iNumSysRegs = (int)(sizeof(sysCsr) / sizeof(SHOW_REG)); + iNumMacRegs = (int)(sizeof(macCsr) / sizeof(SHOW_REG)); + + // preserve MAC cmd/data reg's + dwOldMacCmdReg = Lan_GetRegDW(MAC_CSR_CMD); + dwOldMacDataReg = Lan_GetRegDW(MAC_CSR_DATA); + + SMSC_TRACE(""); + SMSC_TRACE(" LAN91C118 CSR's"); + SMSC_TRACE(" SYS CSR's MAC CSR's"); + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + for (i=0; idwLanBase+sysCsr[i].dwOffset)), + macCsr[i].szName, + macCsr[i].dwOffset, + Mac_GetRegDW(privateData,macCsr[i].dwOffset,keyCode)); + + // restore original mac cmd/data reg's after each usage + Lan_SetRegDW(MAC_CSR_CMD,dwOldMacCmdReg); + Lan_SetRegDW(MAC_CSR_DATA,dwOldMacDataReg); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + for (i=iNumMacRegs; idwLanBase+sysCsr[i].dwOffset))); + } +} + +void Vl_InitLock(PVERIFIABLE_LOCK pVl) +{ + SMSC_ASSERT(pVl!=NULL); + spin_lock_init(&(pVl->Lock)); + pVl->KeyCode=0; +} + +bool Vl_CheckLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode) +{ + bool result=false; + SMSC_ASSERT(pVl!=NULL); + if(keyCode==pVl->KeyCode) + result=true; + return result; +} + +VL_KEY Vl_WaitForLock(PVERIFIABLE_LOCK pVl,unsigned long *pdwIntFlags) +{ + VL_KEY result=0; + SMSC_ASSERT(pVl!=NULL); + spin_lock_irqsave( + &(pVl->Lock), + (*pdwIntFlags)); + pVl->KeyCode++; + if(pVl->KeyCode>0x80000000UL) { + pVl->KeyCode=1; + } + result=pVl->KeyCode; + return result; +} + +void Vl_ReleaseLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode,unsigned long *pdwIntFlags) +{ + SMSC_ASSERT(pVl!=NULL); + SMSC_ASSERT(pVl->KeyCode==keyCode); + spin_unlock_irqrestore(&(pVl->Lock),(*pdwIntFlags)); +} + +#ifndef USING_LINT +module_init(Smsc9118_init_module); +module_exit(Smsc9118_cleanup_module); +#endif diff -Naur --exclude=.gitignore --exclude=android.config linux-2.6.29/drivers/net/titan_ge.c linux-2.6.29/drivers/net/titan_ge.c --- linux-2.6.29/drivers/net/titan_ge.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.29/drivers/net/titan_ge.c 2009-05-29 11:43:39.000000000 -0400 @@ -0,0 +1,2069 @@ +/* + * drivers/net/titan_ge.c - Driver for Titan ethernet ports + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author : Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * The MAC unit of the Titan consists of the following: + * + * -> XDMA Engine to move data to from the memory to the MAC packet FIFO + * -> FIFO is where the incoming and outgoing data is placed + * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes + * the data into the FIFO for Rx + * -> TMAC is the outgoing MAC interface and RMAC is the incoming. + * -> AFX is the address filtering block + * -> GMII block to communicate with the PHY + * + * Rx will look like the following: + * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory + * +