diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c
index 31f2f560e..df1501bcf 100644
--- a/plat/imx/imx8m/ddr/clock.c
+++ b/plat/imx/imx8m/ddr/clock.c
@@ -104,6 +104,9 @@ void dram_pll_init(unsigned int drate)
 	case 1600:
 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3);
 		break;
+	case 1336:
+		mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 3);
+		break;
 	case 1066:
 		mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3);
 		break;
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 179b6226f..f906fab74 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -117,9 +117,6 @@ static const struct imx_rdc_cfg rdc[] = {
 	RDC_MDAn(RDC_MDA_M4, DID1),
 
 	/* peripherals domain permission */
-	RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
-	RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
-	RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W),
 
 	/* memory region */
 
@@ -190,8 +187,10 @@ static void bl31_tzc380_setup(void)
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
+#if VAR_ENABLE_IMX_UART
 	unsigned int console_base = IMX_BOOT_UART_BASE;
 	static console_t console;
+#endif
 	int i;
 
 	/* Enable CSU NS access permission */
@@ -205,6 +204,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	imx_csu_init(csu_cfg);
 
+#if VAR_ENABLE_IMX_UART
 	if (console_base == 0U) {
 		console_base = imx8m_uart_get_base();
 	}
@@ -213,6 +213,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		IMX_CONSOLE_BAUDRATE, &console);
 	/* This console is only used for boot stage */
 	console_set_scope(&console, CONSOLE_FLAG_BOOT);
+#endif
 
 	imx8m_caam_init();
 
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index e72166408..92072f0ec 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -160,8 +160,6 @@
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
-#define SNVS_LPCR_LPTA_EN		BIT(1)
-#define SNVS_LPCR_LPWUI_EN		BIT(3)
 #define SNVS_LPCR_DP_EN			BIT(5)
 #define SNVS_LPCR_TOP			BIT(6)
 
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index 312eb32d1..96dd27a4c 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -109,9 +109,7 @@ static const struct imx_rdc_cfg rdc[] = {
 	RDC_MDAn(RDC_MDA_M7, DID1),
 
 	/* peripherals domain permission */
-	RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
-	RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
-	RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R),
+	RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R | D1W),
 
 	/* memory region */
 	RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff),
@@ -185,8 +183,10 @@ static void bl31_tzc380_setup(void)
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
+#if VAR_ENABLE_IMX_UART
 	unsigned int console_base = IMX_BOOT_UART_BASE;
 	static console_t console;
+#endif
 	unsigned int val;
 	int i;
 
@@ -213,6 +213,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
 	mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
 
+#if VAR_ENABLE_IMX_UART
 	if (console_base == 0U) {
 		console_base = imx8m_uart_get_base();
 	}
@@ -221,6 +222,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		IMX_CONSOLE_BAUDRATE, &console);
 	/* This console is only used for boot stage */
 	console_set_scope(&console, CONSOLE_FLAG_BOOT);
+#endif
 
 	imx8m_caam_init();
 
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index 52f1d7087..5dbba33ae 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -135,8 +135,6 @@
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
-#define SNVS_LPCR_LPTA_EN		BIT(1)
-#define SNVS_LPCR_LPWUI_EN		BIT(3)
 #define SNVS_LPCR_DP_EN			BIT(5)
 #define SNVS_LPCR_TOP			BIT(6)
 
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index 1eefdaa81..74a5900e5 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -210,8 +210,10 @@ static void bl31_tzc380_setup(void)
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
+#if VAR_ENABLE_IMX_UART
 	unsigned int console_base = IMX_BOOT_UART_BASE;
 	static console_t console;
+#endif
 	unsigned int val;
 	unsigned int i;
 
@@ -231,6 +233,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
 	mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
 
+#if VAR_ENABLE_IMX_UART
 	if (console_base == 0U) {
 		console_base = imx8m_uart_get_base();
 	}
@@ -239,6 +242,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		IMX_CONSOLE_BAUDRATE, &console);
 	/* This console is only used for boot stage */
 	console_set_scope(&console, CONSOLE_FLAG_BOOT);
+#endif
 
 	imx8m_caam_init();
 
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 13d5b7ef6..7a3b7becd 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -174,8 +174,6 @@
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
-#define SNVS_LPCR_LPTA_EN		BIT(1)
-#define SNVS_LPCR_LPWUI_EN		BIT(3)
 #define SNVS_LPCR_DP_EN			BIT(5)
 #define SNVS_LPCR_TOP			BIT(6)
 
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 6744b7943..bc5f2ceff 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -129,8 +129,6 @@
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
-#define SNVS_LPCR_LPTA_EN		BIT(1)
-#define SNVS_LPCR_LPWUI_EN		BIT(3)
 #define SNVS_LPCR_DP_EN			BIT(5)
 #define SNVS_LPCR_TOP			BIT(6)
 
diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h
index 719c39063..d759ea4e3 100644
--- a/plat/imx/imx8m/include/dram.h
+++ b/plat/imx/imx8m/include/dram.h
@@ -35,6 +35,8 @@ struct dram_cfg_param {
 };
 
 struct dram_timing_info {
+	/* ddrphy firmware offset */
+	unsigned int ddrphy_fw_offset;
 	/* umctl2 config */
 	struct dram_cfg_param *ddrc_cfg;
 	unsigned int ddrc_cfg_num;
diff --git a/plat/imx/imx9/include/dram.h b/plat/imx/imx9/include/dram.h
index ccb9ef3bb..4f5696e29 100644
--- a/plat/imx/imx9/include/dram.h
+++ b/plat/imx/imx9/include/dram.h
@@ -37,6 +37,8 @@ struct dram_fsp_cfg{
 };
 
 struct dram_timing_info {
+	/* ddrphy firmware offset */
+	unsigned int ddrphy_fw_offset;
 	/* umctl2 config */
 	struct dram_cfg_param *ddrc_cfg;
 	unsigned int ddrc_cfg_num;
diff --git a/plat/imx/imx95/imx95_bl31_setup.c b/plat/imx/imx95/imx95_bl31_setup.c
index 175a78a20..e3e54477f 100644
--- a/plat/imx/imx95/imx95_bl31_setup.c
+++ b/plat/imx/imx95/imx95_bl31_setup.c
@@ -108,6 +108,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 void bl31_plat_arch_setup(void)
 {
 	/* Assign all the GPIO pins to non-secure world by default */
+	mmio_write_32(GPIO1_BASE + 0x10, 0xffff7fff);
+	mmio_write_32(GPIO1_BASE + 0x14, 0x3);
+	mmio_write_32(GPIO1_BASE + 0x18, 0xffff7fff);
+	mmio_write_32(GPIO1_BASE + 0x1c, 0x3);
+
 	mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff);
 	mmio_write_32(GPIO2_BASE + 0x14, 0x3);
 	mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff);