diff -rNdup gdb-6.6.orig/gdb/config/xtensa/linux.mh gdb-6.6/gdb/config/xtensa/linux.mh
--- gdb-6.6.orig/gdb/config/xtensa/linux.mh 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/config/xtensa/linux.mh 2008-01-08 18:43:25.066004000 -0800
@@ -0,0 +1,7 @@
+# Host: Xtensa, running GNU/Linux.
+
+NAT_FILE=nm-linux.h
+NATDEPFILES= inf-ptrace.o fork-child.o xtensa-linux-nat.o gcore.o \
+ linux-thread-db.o proc-service.o linux-nat.o linux-fork.o
+
+LOADLIBES = -ldl -rdynamic
diff -rNdup gdb-6.6.orig/gdb/config/xtensa/linux.mt gdb-6.6/gdb/config/xtensa/linux.mt
--- gdb-6.6.orig/gdb/config/xtensa/linux.mt 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/config/xtensa/linux.mt 2008-01-08 18:43:33.736323000 -0800
@@ -0,0 +1,4 @@
+# Target: Xtensa based machine running GNU/Linux
+
+TDEPFILES= xtensa-tdep.o xtensa-config.o xtensa-linux-tdep.o \
+ corelow.o solib.o solib-svr4.o solib-legacy.o symfile-mem.o
diff -rNdup gdb-6.6.orig/gdb/config/xtensa/nm-linux.h gdb-6.6/gdb/config/xtensa/nm-linux.h
--- gdb-6.6.orig/gdb/config/xtensa/nm-linux.h 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/config/xtensa/nm-linux.h 2008-01-08 18:43:45.967087000 -0800
@@ -0,0 +1,37 @@
+/* Xtensa native-dependent macros for GDB, the GNU debugger.
+ Copyright 2007 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+#ifndef NM_XTENSA_LINUX_H
+
+#include "config/nm-linux.h"
+
+#define NM_LINUX_H
+
+/* Return sizeof user struct to callers in less machine dependent routines */
+
+#define KERNEL_U_SIZE kernel_u_size()
+extern int kernel_u_size (void);
+
+/* This is the amount to subtract from u.u_ar0
+ to get the offset in the core file of the register values. */
+#define KERNEL_U_ADDR 0x0
+
+#define FETCH_INFERIOR_REGISTERS
+
+#endif /* #ifndef NM_XTENSA_LINUX_H */
diff -rNdup gdb-6.6.orig/gdb/configure.tgt gdb-6.6/gdb/configure.tgt
--- gdb-6.6.orig/gdb/configure.tgt 2006-11-24 12:11:07.000000000 -0800
+++ gdb-6.6/gdb/configure.tgt 2008-01-08 18:44:15.256768000 -0800
@@ -230,6 +230,9 @@ x86_64-*-netbsd* | x86_64-*-knetbsd*-gnu
gdb_target=nbsd64 ;;
x86_64-*-openbsd*) gdb_target=obsd64 ;;
+xtensa*-*-linux*) gdb_target=linux
+ build_gdbserver=yes
+ ;;
xtensa*) gdb_target=xtensa ;;
esac
diff -rNdup gdb-6.6.orig/gdb/gdbserver/configure.srv gdb-6.6/gdb/gdbserver/configure.srv
--- gdb-6.6.orig/gdb/gdbserver/configure.srv 2006-11-24 12:11:07.000000000 -0800
+++ gdb-6.6/gdb/gdbserver/configure.srv 2008-01-08 19:03:45.298557000 -0800
@@ -114,6 +114,10 @@ case "${target}" in
srv_linux_usrregs=yes
srv_linux_thread_db=yes
;;
+ xtensa-*-linux*) srv_regobj=reg-xtensa.o
+ srv_tgtobj="linux-low.o linux-xtensa-low.o"
+ srv_linux_regsets=yes
+ ;;
*) echo "Error: target not supported by gdbserver."
exit 1
;;
diff -rNdup gdb-6.6.orig/gdb/gdbserver/linux-xtensa-low.c gdb-6.6/gdb/gdbserver/linux-xtensa-low.c
--- gdb-6.6.orig/gdb/gdbserver/linux-xtensa-low.c 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/gdbserver/linux-xtensa-low.c 2008-01-08 18:44:45.978010000 -0800
@@ -0,0 +1,204 @@
+/* GNU/Linux/Xtensa specific low level interface, for the remote server for GDB.
+ Copyright 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see . */
+
+
+#include "server.h"
+#include "linux-low.h"
+
+#include
+#include
+
+#ifdef HAVE_LINUX_ELF_H
+#include
+#endif
+
+#include
+
+static void
+xtensa_fill_gregset (void *buf)
+{
+ xtensa_gregset_t* rset = buf;
+ int ar0_regnum;
+ char *ptr;
+ int i;
+
+ /* Take care of ar0 ... arN. */
+
+ ar0_regnum = find_regno ("ar0");
+ ptr = (char *)(rset->a);
+
+ for (i = ar0_regnum; i < ar0_regnum + XCHAL_NUM_AREGS; i++)
+ {
+ collect_register (i, ptr);
+ ptr += register_size(i);
+ }
+
+ /* Loop registers. */
+
+#if XCHAL_HAVE_LOOP
+ collect_register_by_name ("lbeg", (char*)(&rset->lbeg));
+ collect_register_by_name ("lend", (char*)(&rset->lend));
+ collect_register_by_name ("lcount", (char*)(&rset->lcount));
+#endif
+
+ /* SAR */
+
+ collect_register_by_name ("sar", (char*)(&rset->sar));
+
+ /* PC, PS, WB, and WS. */
+
+ collect_register_by_name ("pc", (char*)(&rset->pc));
+ collect_register_by_name ("ps", (char*)(&rset->ps));
+ i = 0 ;
+ collect_register (find_regno ("windowbase"),(char*)&i);
+ collect_register_by_name ("windowstart", (char*)(&rset->windowstart));
+}
+
+static void
+xtensa_store_gregset (const void *buf)
+{
+ const xtensa_gregset_t* rset = buf;
+ int ar0_regnum;
+ char *ptr;
+ int i;
+
+ /* Take care of ar0 ... arN. */
+
+ ar0_regnum = find_regno ("ar0");
+ ptr = (char *)(rset->a);
+
+ for (i = ar0_regnum; i < ar0_regnum + XCHAL_NUM_AREGS; i++)
+ {
+ supply_register (i, ptr);
+ ptr += register_size(i);
+ }
+
+ /* Loop registers. */
+
+#if XCHAL_HAVE_LOOP
+ supply_register_by_name ("lbeg", (char*)(&rset->lbeg));
+ supply_register_by_name ("lend", (char*)(&rset->lend));
+ supply_register_by_name ("lcount", (char*)(&rset->lcount));
+#endif
+
+ /* SAR */
+
+ supply_register_by_name ("sar", (char*)(&rset->sar));
+
+ /* PC, PS, WB, and WS. */
+
+ supply_register_by_name ("pc", (char*)(&rset->pc));
+ supply_register_by_name ("ps", (char*)(&rset->ps));
+ i = 0 ;
+ supply_register (find_regno ("windowbase"),(char*)&i);
+ supply_register_by_name ("windowstart",
+ (char*)(&rset->windowstart));
+}
+
+static void
+xtensa_fill_xtregset (void *buf)
+{
+ const xtensa_regtable_t *ptr;
+
+ /* fprintf(stderr, "=== 0x%x\n", buf); */
+ for (ptr = xtensa_regmap_table; ptr->name; ptr++)
+ {
+ /* fprintf (stderr, " collect %s = 0x%x at %d [0x%x]", ptr->name, *(int *)((char*)buf + ptr->ptrace_offset), ptr->ptrace_offset, (unsigned)((char*)buf + ptr->ptrace_offset)); */
+ collect_register_by_name (ptr->name,
+ (char*)buf + ptr->ptrace_offset);
+ /* fprintf (stderr, " => 0x%x\n", *(int *)((char*)buf + ptr->ptrace_offset)); */
+ }
+ /* fprintf (stderr, "---------------------------\n"); */
+}
+
+static void
+xtensa_store_xtregset (const void *buf)
+{
+ const xtensa_regtable_t *ptr;
+
+ for (ptr = xtensa_regmap_table; ptr->name; ptr++)
+ {
+ /* fprintf (stderr, " supply %s = 0x%x at %d", ptr->name, *(int *)((char*)buf + ptr->ptrace_offset), ptr->ptrace_offset); */
+ supply_register_by_name (ptr->name,
+ (char*)buf + ptr->ptrace_offset);
+ /* fprintf (stderr, " => 0x%x\n", *(int *)((char*)buf + ptr->ptrace_offset)); */
+ }
+ /* fprintf (stderr, "---------------------------\n"); */
+}
+
+struct regset_info target_regsets[] = {
+ { PTRACE_GETREGS, PTRACE_SETREGS, sizeof (elf_gregset_t),
+ GENERAL_REGS,
+ xtensa_fill_gregset, xtensa_store_gregset },
+ { PTRACE_GETXTREGS, PTRACE_SETXTREGS, XTENSA_ELF_XTREG_SIZE,
+ EXTENDED_REGS,
+ xtensa_fill_xtregset, xtensa_store_xtregset },
+ { 0, 0, -1, -1, NULL, NULL }
+};
+
+#if XCHAL_HAVE_BE
+#define XTENSA_BREAKPOINT {0xd2,0x0f}
+#else
+#define XTENSA_BREAKPOINT {0x2d,0xf0}
+#endif
+
+static const unsigned char xtensa_breakpoint[] = XTENSA_BREAKPOINT;
+#define xtensa_breakpoint_len 2
+
+static CORE_ADDR
+xtensa_get_pc (void)
+{
+ unsigned long pc;
+
+ collect_register_by_name ("pc", &pc);
+ return pc;
+}
+
+static void
+xtensa_set_pc (CORE_ADDR pc)
+{
+ unsigned long newpc = pc;
+ supply_register_by_name ("pc", &newpc);
+}
+
+static int
+xtensa_breakpoint_at (CORE_ADDR where)
+{
+ unsigned long insn;
+
+ (*the_target->read_memory) (where, (unsigned char *) &insn,
+ xtensa_breakpoint_len);
+ return memcmp((char *)&insn, xtensa_breakpoint, xtensa_breakpoint_len) == 0;
+}
+
+struct linux_target_ops the_low_target = {
+ 0, /* xtensa_num_regs - NA */
+ 0, /* xtensa_regmap, NA */
+ 0, /* xtensa_cannot_fetch_register, - NA */
+ 0, /* xtensa_cannot_store_register, - NA */
+ xtensa_get_pc,
+ xtensa_set_pc,
+ xtensa_breakpoint,
+ xtensa_breakpoint_len,
+ NULL, /* xtensa_reinsert_addr NA ??? */
+ 0,
+ xtensa_breakpoint_at,
+};
+
+
+
diff -rNdup gdb-6.6.orig/gdb/gdbserver/Makefile.in gdb-6.6/gdb/gdbserver/Makefile.in
--- gdb-6.6.orig/gdb/gdbserver/Makefile.in 2006-11-24 12:11:07.000000000 -0800
+++ gdb-6.6/gdb/gdbserver/Makefile.in 2008-01-08 18:44:55.806181000 -0800
@@ -127,7 +127,8 @@ SFILES= $(srcdir)/gdbreplay.c $(srcdir)/
$(srcdir)/linux-m68k-low.c $(srcdir)/linux-mips-low.c \
$(srcdir)/linux-ppc-low.c $(srcdir)/linux-ppc64-low.c \
$(srcdir)/linux-s390-low.c \
- $(srcdir)/linux-sh-low.c $(srcdir)/linux-x86-64-low.c
+ $(srcdir)/linux-sh-low.c $(srcdir)/linux-x86-64-low.c \
+ $(srcdir)/linux-xtensa-low.c
DEPFILES = @GDBSERVER_DEPFILES@
@@ -206,7 +207,7 @@ clean:
rm -f gdbserver gdbreplay core make.log
rm -f reg-arm.c reg-i386.c reg-ia64.c reg-m32r.c reg-m68k.c reg-mips.c
rm -f reg-ppc.c reg-sh.c reg-spu.c reg-x86-64.c reg-i386-linux.c
- rm -f reg-cris.c reg-crisv32.c reg-x86-64-linux.c
+ rm -f reg-cris.c reg-crisv32.c reg-x86-64-linux.c reg-xtensa.c
maintainer-clean realclean distclean: clean
rm -f nm.h tm.h xm.h config.status config.h stamp-h config.log
@@ -286,6 +287,7 @@ linux-s390-low.o: linux-s390-low.c $(lin
linux-sh-low.o: linux-sh-low.c $(linux_low_h) $(server_h)
linux-x86-64-low.o: linux-x86-64-low.c $(linux_low_h) $(server_h) \
$(gdb_proc_service_h)
+linux-xtensa-low.o: linux-xtensa-low.c $(linux_low_h) $(server_h)
win32-i386-low.o: win32-i386-low.c $(server_h) $(regdef_h) $(regcache_h)
@@ -342,5 +344,8 @@ reg-x86-64.c : $(srcdir)/../regformats/r
reg-x86-64-linux.o : reg-x86-64-linux.c $(regdef_h)
reg-x86-64-linux.c : $(srcdir)/../regformats/reg-x86-64-linux.dat $(regdat_sh)
sh $(regdat_sh) $(srcdir)/../regformats/reg-x86-64-linux.dat reg-x86-64-linux.c
+reg-xtensa.o : reg-xtensa.c $(regdef_h)
+reg-xtensa.c : $(srcdir)/../regformats/reg-xtensa.dat $(regdat_sh)
+ sh $(regdat_sh) $(srcdir)/../regformats/reg-xtensa.dat reg-xtensa.c
# This is the end of "Makefile.in".
diff -rNdup gdb-6.6.orig/gdb/Makefile.in gdb-6.6/gdb/Makefile.in
--- gdb-6.6.orig/gdb/Makefile.in 2006-11-24 11:54:14.000000000 -0800
+++ gdb-6.6/gdb/Makefile.in 2008-01-08 18:45:04.865107000 -0800
@@ -1504,7 +1504,8 @@ ALLDEPFILES = \
win32-nat.c \
xcoffread.c xcoffsolib.c \
xstormy16-tdep.c \
- xtensa-tdep.c xtensa-config.c
+ xtensa-tdep.c xtensa-config.c \
+ xtensa-linux-tdep.c xtensa-linux-nat.c
# Some files need explicit build rules (due to -Werror problems) or due
# to sub-directory fun 'n' games.
@@ -2876,9 +2877,12 @@ xstormy16-tdep.o: xstormy16-tdep.c $(def
$(gdbcmd_h) $(gdbcore_h) $(value_h) $(dis_asm_h) $(inferior_h) \
$(gdb_string_h) $(gdb_assert_h) $(arch_utils_h) $(floatformat_h) \
$(regcache_h) $(doublest_h) $(osabi_h) $(objfiles_h)
-xtensa-linux-tdep.o: xtensa-linux-tdep.c $(defs_h) $(inferior_h) \
- $(gdbcore_h) $(regcache_h) $(osabi_h) $(gdb_string_h) \
- $(xtensa_tdep_h) $(xtensa_linux_tdep_h)
+xtensa-linux-nat.o: xtensa-linux-nat.c $(defs_h) $(gdb_string_h) $(frame_h) \
+ $(inferior_h) $(gdbcore_h) $(regcache_h) $(gdb_assert_h) \
+ $(gdb_wait_h) $(gregset_h) $(ppc_tdep_h) $(target_h) \
+ $(linux_nat_h) $(xtensa_tdep_h)
+xtensa-linux-tdep.o: xtensa-linux-tdep.c $(defs_h) $(osabi_h) $(solib_svr4_h) \
+ $(symtab_h) $(xtensa_tdep_h)
xtensa-tdep.o: xtensa-tdep.c $(defs_h) $(doublest_h) $(frame_h) \
$(frame_unwind_h) $(frame_base_h) $(inferior_h) $(symtab_h) \
$(value_h) $(gdbcmd_h) $(gdbcore_h) $(dis_asm_h) $(symfile_h) \
diff -rNdup gdb-6.6.orig/gdb/xtensa-linux-nat.c gdb-6.6/gdb/xtensa-linux-nat.c
--- gdb-6.6.orig/gdb/xtensa-linux-nat.c 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/xtensa-linux-nat.c 2008-01-08 18:45:17.784180000 -0800
@@ -0,0 +1,298 @@
+/* Xtensa GNU/Linux native support.
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see . */
+
+#include "defs.h"
+#include "gdb_string.h"
+#include "frame.h"
+#include "inferior.h"
+#include "gdbcore.h"
+#include "regcache.h"
+#include "gdb_assert.h"
+#include "target.h"
+#include "linux-nat.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "gdb_wait.h"
+#include
+#include
+#include
+
+/* Prototypes for supply_gregset etc. */
+#include "gregset.h"
+#include "xtensa-tdep.h"
+#include "gdbserver/xtensa-regmap.c"
+
+int
+get_thread_id (ptid_t ptid)
+{
+ int tid = TIDGET (ptid);
+ if (0 == tid)
+ tid = PIDGET (ptid);
+ return tid;
+}
+#define GET_THREAD_ID(PTID) get_thread_id (PTID)
+
+static xtensa_elf_greg_t always_zero = (xtensa_elf_greg_t)0;
+
+void
+fill_gregset (gdb_gregset_t *gregsetp, int regnum)
+{
+ int i;
+ xtensa_elf_gregset_t *regs = (xtensa_elf_gregset_t *) gregsetp;
+
+ if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1)
+ regcache_raw_collect (current_regcache,
+ gdbarch_pc_regnum (current_gdbarch), ®s->pc);
+ if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1)
+ regcache_raw_collect (current_regcache,
+ gdbarch_ps_regnum (current_gdbarch), ®s->ps);
+ if (regnum == WB_REGNUM || regnum == -1)
+ /* In Xtensa GNU/Linux ptrace, windowbase is always 0. */
+ regcache_raw_collect (current_regcache, WB_REGNUM, &always_zero);
+ if (regnum == WS_REGNUM || regnum == -1)
+ regcache_raw_collect (current_regcache, WS_REGNUM, ®s->windowstart);
+ if (regnum == LBEG_REGNUM || regnum == -1)
+ regcache_raw_collect (current_regcache, LBEG_REGNUM, ®s->lbeg);
+ if (regnum == LEND_REGNUM || regnum == -1)
+ regcache_raw_collect (current_regcache, LEND_REGNUM, ®s->lend);
+ if (regnum == LCOUNT_REGNUM || regnum == -1)
+ regcache_raw_collect (current_regcache, LCOUNT_REGNUM, ®s->lcount);
+ if (regnum == SAR_REGNUM || regnum == -1)
+ regcache_raw_collect (current_regcache, SAR_REGNUM, ®s->sar);
+
+ if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
+ regcache_raw_collect (current_regcache, regnum, ®s->ar[regnum - AR_BASE]);
+ else if (regnum == -1)
+ {
+ for (i = 0; i < NUM_AREGS; ++i)
+ regcache_raw_collect (current_regcache, AR_BASE + i, ®s->ar[i]);
+ }
+}
+
+void
+supply_gregset (gdb_gregset_t *gregsetp)
+{
+ int i;
+ xtensa_elf_gregset_t *regs = (xtensa_elf_gregset_t *) gregsetp;
+
+ regcache_raw_supply (current_regcache,
+ gdbarch_pc_regnum (current_gdbarch), ®s->pc);
+ regcache_raw_supply (current_regcache,
+ gdbarch_ps_regnum (current_gdbarch), ®s->ps);
+ /* In Xtensa GNU/Linux ptrace, windowbase is always 0. */
+ regcache_raw_supply (current_regcache, WB_REGNUM, &always_zero);
+ regcache_raw_supply (current_regcache, WS_REGNUM, ®s->windowstart);
+ regcache_raw_supply (current_regcache, LBEG_REGNUM, ®s->lbeg);
+ regcache_raw_supply (current_regcache, LEND_REGNUM, ®s->lend);
+ regcache_raw_supply (current_regcache, LCOUNT_REGNUM, ®s->lcount);
+ regcache_raw_supply (current_regcache, SAR_REGNUM, ®s->sar);
+
+ for (i = 0; i < NUM_AREGS; ++i)
+ regcache_raw_supply (current_regcache, AR_BASE + i, ®s->ar[i]);
+}
+
+void
+fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
+{
+ return;
+}
+
+void
+supply_fpregset (gdb_fpregset_t *fpregsetp)
+{
+ return;
+}
+
+/* Fetch general-purpose register(s) from process/thread TID
+ and store value(s) in GDB's register array. */
+
+static void
+fetch_gregs (int regnum)
+{
+ int tid = GET_THREAD_ID (inferior_ptid);
+ xtensa_elf_gregset_t regs;
+ int areg;
+
+ if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0)
+ {
+ warning (_("Couldn't get registers"));
+ return;
+ }
+
+ if (regnum == -1)
+ {
+ /* Fetch all registers. */
+
+ supply_gregset ((gdb_gregset_t*)®s);
+ }
+ else
+ {
+ if (regnum == gdbarch_pc_regnum (current_gdbarch))
+ regcache_raw_supply (current_regcache,
+ gdbarch_pc_regnum (current_gdbarch), ®s.pc);
+ if (regnum == gdbarch_ps_regnum (current_gdbarch))
+ regcache_raw_supply (current_regcache,
+ gdbarch_ps_regnum (current_gdbarch), ®s.ps);
+ if (regnum == WB_REGNUM)
+ /* In Xtensa GNU/Linux ptrace, windowbase is always 0. */
+ regcache_raw_supply (current_regcache, WB_REGNUM, &always_zero);
+ if (regnum == WS_REGNUM)
+ regcache_raw_supply (current_regcache, WS_REGNUM, ®s.windowstart);
+ if (regnum == LBEG_REGNUM)
+ regcache_raw_supply (current_regcache, LBEG_REGNUM, ®s.lbeg);
+ if (regnum == LEND_REGNUM)
+ regcache_raw_supply (current_regcache, LEND_REGNUM, ®s.lend);
+ if (regnum == LCOUNT_REGNUM)
+ regcache_raw_supply (current_regcache, LCOUNT_REGNUM, ®s.lcount);
+ if (regnum == SAR_REGNUM)
+ regcache_raw_supply (current_regcache, SAR_REGNUM, ®s.sar);
+ if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
+ regcache_raw_supply (current_regcache, regnum, ®s.ar[regnum - AR_BASE]);
+ }
+}
+
+/* Store all valid general-purpose registers in GDB's register
+ array into the process/thread specified by TID. */
+
+static void
+store_gregs (int regnum)
+{
+ int tid = GET_THREAD_ID (inferior_ptid);
+ xtensa_elf_gregset_t regs;
+ int areg;
+
+ if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0)
+ {
+ warning (_("Couldn't get registers"));
+ return;
+ }
+
+ fill_gregset ((gdb_gregset_t*)®s, regnum);
+
+ if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0)
+ {
+ warning (_("Couldn't write registers"));
+ return;
+ }
+}
+
+static int xtreg_lo;
+static int xtreg_high;
+
+/* Fetch extended (TIE) registers. */
+
+static void
+fetch_xtregs (int regnum)
+{
+ int tid = GET_THREAD_ID (inferior_ptid);
+ const xtensa_regtable_t *ptr;
+ char xtregs [XTENSA_ELF_XTREG_SIZE];
+
+ if (ptrace (PTRACE_GETXTREGS, tid, 0, (long)&xtregs) < 0)
+ perror_with_name (_("Couldn't get xtended (TIE) registers"));
+
+ for (ptr = xtensa_regmap_table; ptr->name; ptr++)
+ if (regnum == ptr->gdb_regnum || regnum == -1)
+ regcache_raw_supply (current_regcache, ptr->gdb_regnum,
+ xtregs + ptr->ptrace_offset);
+}
+
+/* Store extended (TIE) registers. */
+
+static void
+store_xtregs (int regnum)
+{
+ int tid = GET_THREAD_ID (inferior_ptid);
+ const xtensa_regtable_t *ptr;
+ char xtregs [XTENSA_ELF_XTREG_SIZE];
+
+ if (ptrace (PTRACE_GETXTREGS, tid, 0, (long)&xtregs) < 0)
+ perror_with_name (_("Couldn't get extended (TIE) registers"));
+
+ for (ptr = xtensa_regmap_table; ptr->name; ptr++)
+ if (regnum == ptr->gdb_regnum || regnum == -1)
+ regcache_raw_collect (current_regcache, ptr->gdb_regnum,
+ xtregs + ptr->ptrace_offset);
+
+ if (ptrace (PTRACE_SETXTREGS, tid, 0, (long)&xtregs) < 0)
+ perror_with_name (_("Couldn't write extended (TIE) registers"));
+}
+
+void
+xtensa_linux_fetch_inferior_registers (int regnum)
+{
+
+ if (regnum == -1)
+ {
+ fetch_gregs (regnum);
+ fetch_xtregs (regnum);
+ }
+ else if ((regnum < xtreg_lo) || (regnum > xtreg_high))
+ fetch_gregs (regnum);
+ else
+ fetch_xtregs (regnum);
+}
+
+void
+xtensa_linux_store_inferior_registers (int regnum)
+{
+ if (regnum == -1)
+ {
+ store_gregs (regnum);
+ store_xtregs (regnum);
+ }
+ else if ((regnum < xtreg_lo) || (regnum > xtreg_high))
+ store_gregs (regnum);
+ else
+ store_xtregs (regnum);
+}
+
+void _initialize_xtensa_linux_nat (void);
+
+void
+_initialize_xtensa_linux_nat (void)
+{
+ struct target_ops *t;
+ const xtensa_regtable_t *ptr;
+
+ /* Calculate the register number range for extended registers. */
+ xtreg_lo = 1000000000;
+ xtreg_high = -1;
+ for (ptr = xtensa_regmap_table; ptr->name; ptr++)
+ {
+ if (ptr->gdb_regnum < xtreg_lo)
+ xtreg_lo = ptr->gdb_regnum;
+ if (ptr->gdb_regnum > xtreg_high)
+ xtreg_high = ptr->gdb_regnum;
+ }
+
+ /* Fill in the generic GNU/Linux methods. */
+ t = linux_target ();
+
+ /* Add our register access methods. */
+ t->to_fetch_registers = xtensa_linux_fetch_inferior_registers;
+ t->to_store_registers = xtensa_linux_store_inferior_registers;
+
+ linux_nat_add_target (t);
+}
diff -rNdup gdb-6.6.orig/gdb/xtensa-linux-tdep.c gdb-6.6/gdb/xtensa-linux-tdep.c
--- gdb-6.6.orig/gdb/xtensa-linux-tdep.c 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/gdb/xtensa-linux-tdep.c 2008-01-08 18:45:23.115835000 -0800
@@ -0,0 +1,40 @@
+/* Target-dependent code for GNU/Linux on Xtensa processors.
+
+ Copyright 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see . */
+
+#include "defs.h"
+#include "osabi.h"
+
+#include "solib-svr4.h"
+#include "symtab.h"
+
+/* OS specific initialization of gdbarch. */
+
+static void
+xtensa_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+{
+ set_solib_svr4_fetch_link_map_offsets
+ (gdbarch, svr4_ilp32_fetch_link_map_offsets);
+}
+
+void
+_initialize_xtensa_linux_tdep (void)
+{
+ gdbarch_register_osabi (bfd_arch_xtensa, 0, GDB_OSABI_LINUX,
+ xtensa_linux_init_abi);
+}
diff -rNdup gdb-6.6.orig/gdb/xtensa-tdep.c gdb-6.6/gdb/xtensa-tdep.c
--- gdb-6.6.orig/gdb/xtensa-tdep.c 2006-11-14 13:53:59.000000000 -0800
+++ gdb-6.6/gdb/xtensa-tdep.c 2008-01-08 18:45:27.670283000 -0800
@@ -1,12 +1,12 @@
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -15,9 +15,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
+ along with this program. If not, see . */
#include "defs.h"
#include "frame.h"
@@ -51,7 +49,9 @@
#include "gdbcmd.h"
#include "gdb_assert.h"
+#include "xtensa-isa.h"
#include "xtensa-tdep.h"
+#include "xtensa-config.h"
static int xtensa_debug_level = 0;
@@ -74,32 +74,31 @@ static int xtensa_debug_level = 0;
/* According to the ABI, the SP must be aligned to 16-byte boundaries. */
-
#define SP_ALIGNMENT 16
-/* We use a6 through a11 for passing arguments to a function called by GDB. */
-
-#define ARGS_FIRST_REG A6_REGNUM
-#define ARGS_NUM_REGS 6
-#define REGISTER_SIZE 4
-
+/* On Windowed ABI, we use a6 through a11 for passing arguments
+ to a function called by GDB because CALL4 is used. */
+#define ARGS_FIRST_REG A6_REGNUM
+#define ARGS_NUM_REGS 6
+#define REGISTER_SIZE 4
-/* Extract the call size from the return address or ps register. */
-#define PS_CALLINC_SHIFT 16
-#define PS_CALLINC_MASK 0x00030000
-#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
-#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
+/* Extract the call size from the return address or PS register. */
+#define PS_CALLINC_SHIFT 16
+#define PS_CALLINC_MASK 0x00030000
+#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
+#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
/* Convert a live Ax register number to the corresponding Areg number. */
-
#define AREG_NUMBER(r, wb) \
- ((((r) - A0_REGNUM + (((wb) & WB_MASK)<> 2; /* 0, 4, 8, 12 */
+ winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
}
else
{
if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
- winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12 */
+ winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
}
return winsize;
}
@@ -176,19 +175,26 @@ extract_call_winsize (CORE_ADDR pc)
/* REGISTER INFORMATION */
/* Returns the name of a register. */
-
static const char *
xtensa_register_name (int regnum)
{
/* Return the name stored in the register map. */
- if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
+ if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
+ + gdbarch_num_pseudo_regs (current_gdbarch))
return REGMAP[regnum].name;
- /* Invalid register number. */
internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
return 0;
}
+static unsigned long
+xtensa_read_register (int regnum)
+{
+ ULONGEST value;
+
+ regcache_raw_read_unsigned (current_regcache, regnum, &value);
+ return (unsigned long) value;
+}
/* Return the type of a register. Create a new type, if necessary. */
@@ -207,23 +213,24 @@ xtensa_register_type (struct gdbarch *gd
|| (regnum >= A0_BASE && regnum < A0_BASE + 16))
return builtin_type_int;
- if (regnum == PC_REGNUM || regnum == A1_REGNUM)
+ if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == A1_REGNUM)
return lookup_pointer_type (builtin_type_void);
/* Return the stored type for all other registers. */
- else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
+ else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
+ + gdbarch_num_pseudo_regs (current_gdbarch))
{
xtensa_register_t* reg = ®MAP[regnum];
- /* Set ctype for this register (only the first time we ask for it). */
+ /* Set ctype for this register (only the first time). */
if (reg->ctype == 0)
{
struct ctype_cache *tp;
int size = reg->byte_size;
- /* We always use the memory representation, even if the register
- width is smaller. */
+ /* We always use the memory representation,
+ even if the register width is smaller. */
switch (size)
{
case 1:
@@ -271,13 +278,12 @@ xtensa_register_type (struct gdbarch *gd
return reg->ctype;
}
- /* Invalid register number. */
internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
return 0;
}
-/* Returns the 'local' register number for stubs, dwarf2, etc.
+/* Return the 'local' register number for stubs, dwarf2, etc.
The debugging information enumerates registers starting from 0 for A0
to n for An. So, we only have to add the base number for A0. */
@@ -289,29 +295,29 @@ xtensa_reg_to_regnum (int regnum)
if (regnum >= 0 && regnum < 16)
return A0_BASE + regnum;
- for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
+ for (i = 0;
+ i < gdbarch_num_regs (current_gdbarch)
+ + gdbarch_num_pseudo_regs (current_gdbarch);
+ i++)
if (regnum == REGMAP[i].target_number)
return i;
- /* Invalid register number. */
internal_error (__FILE__, __LINE__,
_("invalid dwarf/stabs register number %d"), regnum);
return 0;
}
-/* Handle the special case of masked registers. */
-
-/* Write the bits of a masked register to the various registers that
- are combined into this register. Only the masked areas of these
- registers are modified; the other fields are untouched.
- (Note: The size of masked registers is always less or equal 32 bits.) */
+/* Write the bits of a masked register to the various registers.
+ Only the masked areas of these registers are modified; the other
+ fields are untouched. The size of masked registers is always less
+ than or equal to 32 bits. */
static void
-xtensa_register_write_masked (xtensa_register_t *reg, unsigned char *buffer)
+xtensa_register_write_masked (struct regcache *regcache,
+ xtensa_register_t *reg, const gdb_byte *buffer)
{
unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
-
const xtensa_mask_t *mask = reg->mask;
int shift = 0; /* Shift for next mask (mod 32). */
@@ -327,7 +333,7 @@ xtensa_register_write_masked (xtensa_reg
DEBUGTRACE ("xtensa_register_write_masked ()\n");
/* Copy the masked register to host byte-order. */
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
for (i = 0; i < bytesize; i++)
{
mem >>= 8;
@@ -377,23 +383,25 @@ xtensa_register_write_masked (xtensa_reg
if (r >= 0 && size > 0)
{
/* Don't overwrite the unmasked areas. */
+ ULONGEST old_val;
+ regcache_cooked_read_unsigned (regcache, r, &old_val);
m = 0xffffffff >> (32 - size) << start;
regval <<= start;
- regval = (regval & m) | (read_register (r) & ~m);
- write_register (r, regval);
+ regval = (regval & m) | (old_val & ~m);
+ regcache_cooked_write_unsigned (regcache, r, regval);
}
}
}
-/* Read the masked areas of the registers and assemble it into a single
- register. */
+/* Read a tie state or mapped registers. Read the masked areas
+ of the registers and assemble them into a single value. */
static void
-xtensa_register_read_masked (xtensa_register_t *reg, unsigned char *buffer)
+xtensa_register_read_masked (struct regcache *regcache,
+ xtensa_register_t *reg, gdb_byte *buffer)
{
unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
-
const xtensa_mask_t *mask = reg->mask;
int shift = 0;
@@ -413,7 +421,15 @@ xtensa_register_read_masked (xtensa_regi
for (i = 0; i < mask->count; i++)
{
int r = mask->mask[i].reg_num;
- regval = (r >= 0) ? read_register (r) : 0;
+ if (r >= 0)
+ {
+ ULONGEST val;
+ regcache_cooked_read_unsigned (regcache, r, &val);
+ regval = (unsigned int) val;
+ }
+ else
+ regval = 0;
+
start = mask->mask[i].bit_start;
size = mask->mask[i].bit_size;
@@ -447,7 +463,7 @@ xtensa_register_read_masked (xtensa_regi
ptr = value;
mem = *ptr;
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
for (i = 0; i < bytesize; i++)
{
if ((i & 3) == 0)
@@ -477,31 +493,42 @@ xtensa_pseudo_register_read (struct gdba
DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
regnum, xtensa_register_name (regnum));
- /* Check if it is FP (renumber it in this case -> A0...A15). */
- if (regnum == FP_ALIAS)
- error (_("trying to read FP"));
-
- /* Read aliases a0..a15. */
- if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
+ /* Read aliases a0..a15, if this is a Windowed ABI. */
+ if (ISA_USE_WINDOWED_REGISTERS
+ && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
{
- char *buf = (char *) alloca (MAX_REGISTER_SIZE);
+ gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
regcache_raw_read (regcache, WB_REGNUM, buf);
regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
}
- /* We can always read 'regular' registers. */
- if (regnum >= 0 && regnum < NUM_REGS)
+ /* We can always read non-pseudo registers. */
+ if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
regcache_raw_read (regcache, regnum, buffer);
+
+ /* MAXIM : Temporary hack !!
+ We did not find out how to deal with priveleged registers yet.
+ Let' treat them as pseudo-registers, but we cannot read/write them.
+ */
+ else if (regnum < A0_BASE)
+ {
+ buffer[0] = (gdb_byte)0;
+ buffer[1] = (gdb_byte)0;
+ buffer[2] = (gdb_byte)0;
+ buffer[3] = (gdb_byte)0;
+ }
/* Pseudo registers. */
- else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
+ else if (regnum >= 0
+ && regnum < gdbarch_num_regs (current_gdbarch)
+ + gdbarch_num_pseudo_regs (current_gdbarch))
{
xtensa_register_t *reg = ®MAP[regnum];
xtensa_register_type_t type = reg->type;
int flags = XTENSA_TARGET_FLAGS;
- /* Can we read Unknown or Unmapped registers? */
+ /* We cannot read Unknown or Unmapped registers. */
if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
{
if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
@@ -533,14 +560,13 @@ xtensa_pseudo_register_read (struct gdba
/* We can always read mapped registers. */
else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
{
- xtensa_register_read_masked (reg, (unsigned char *) buffer);
+ xtensa_register_read_masked (regcache, reg, buffer);
return;
}
/* Assume that we can read the register. */
regcache_raw_read (regcache, regnum, buffer);
}
-
else
internal_error (__FILE__, __LINE__,
_("invalid register number %d"), regnum);
@@ -558,14 +584,11 @@ xtensa_pseudo_register_write (struct gdb
DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
regnum, xtensa_register_name (regnum));
- /* Check if this is FP. */
- if (regnum == FP_ALIAS)
- error (_("trying to write FP"));
-
- /* Renumber register, if aliase a0..a15. */
- if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
+ /* Renumber register, if aliase a0..a15 on Windowed ABI. */
+ if (ISA_USE_WINDOWED_REGISTERS
+ && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
{
- char *buf = (char *) alloca (MAX_REGISTER_SIZE);
+ gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
unsigned int wb;
regcache_raw_read (regcache, WB_REGNUM, buf);
@@ -574,18 +597,28 @@ xtensa_pseudo_register_write (struct gdb
/* We can always write 'core' registers.
Note: We might have converted Ax->ARy. */
- if (regnum >= 0 && regnum < NUM_REGS)
+ if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
regcache_raw_write (regcache, regnum, buffer);
+ /* MAXIM : Temporary hack !!
+ We did not find out how to deal with priveleged registers yet.
+ Let' treat them as pseudo-registers, but we cannot read/write them.
+ */
+ else if (regnum < A0_BASE)
+ {
+ return;
+ }
/* Pseudo registers. */
- else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
+ else if (regnum >= 0
+ && regnum < gdbarch_num_regs (current_gdbarch)
+ + gdbarch_num_pseudo_regs (current_gdbarch))
{
xtensa_register_t *reg = ®MAP[regnum];
xtensa_register_type_t type = reg->type;
int flags = XTENSA_TARGET_FLAGS;
- /* On most targets, we can't write registers of type "Unknown"
- or "Unmapped". */
+ /* On most targets, we cannot write registers
+ of type "Unknown" or "Unmapped". */
if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
{
if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
@@ -608,7 +641,6 @@ xtensa_pseudo_register_write (struct gdb
/* On some targets (esp. simulators), we can always write
the register. */
-
else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
{
warning (_("cannot write register"));
@@ -619,23 +651,22 @@ xtensa_pseudo_register_write (struct gdb
/* We can always write mapped registers. */
else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
{
- xtensa_register_write_masked (reg, (unsigned char *) buffer);
+ xtensa_register_write_masked (regcache, reg, buffer);
return;
}
/* Assume that we can write the register. */
regcache_raw_write (regcache, regnum, buffer);
}
-
else
internal_error (__FILE__, __LINE__,
_("invalid register number %d"), regnum);
}
-
static struct reggroup *xtensa_ar_reggroup;
static struct reggroup *xtensa_user_reggroup;
static struct reggroup *xtensa_vectra_reggroup;
+static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
static void
xtensa_init_reggroups (void)
@@ -643,25 +674,51 @@ xtensa_init_reggroups (void)
xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
-}
+ xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
+ xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
+ xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
+ xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
+ xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
+ xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
+ xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
+ xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
+}
static void
xtensa_add_reggroups (struct gdbarch *gdbarch)
{
+ int i;
+
+ /* Predefined groups. */
reggroup_add (gdbarch, all_reggroup);
reggroup_add (gdbarch, save_reggroup);
reggroup_add (gdbarch, restore_reggroup);
reggroup_add (gdbarch, system_reggroup);
- reggroup_add (gdbarch, vector_reggroup); /* vectra */
- reggroup_add (gdbarch, general_reggroup); /* core */
- reggroup_add (gdbarch, float_reggroup); /* float */
+ reggroup_add (gdbarch, vector_reggroup);
+ reggroup_add (gdbarch, general_reggroup);
+ reggroup_add (gdbarch, float_reggroup);
- reggroup_add (gdbarch, xtensa_ar_reggroup); /* ar */
- reggroup_add (gdbarch, xtensa_user_reggroup); /* user */
- reggroup_add (gdbarch, xtensa_vectra_reggroup); /* vectra */
+ /* Xtensa-specific groups. */
+ reggroup_add (gdbarch, xtensa_ar_reggroup);
+ reggroup_add (gdbarch, xtensa_user_reggroup);
+ reggroup_add (gdbarch, xtensa_vectra_reggroup);
+
+ for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
+ reggroup_add (gdbarch, xtensa_cp[i]);
}
+static int
+xtensa_coprocessor_register_group (struct reggroup *group)
+{
+ int i;
+
+ for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
+ if (group == xtensa_cp[i])
+ return i;
+
+ return -1;
+}
#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
| XTENSA_REGISTER_FLAGS_WRITABLE \
@@ -678,6 +735,7 @@ xtensa_register_reggroup_p (struct gdbar
xtensa_register_t* reg = ®MAP[regnum];
xtensa_register_type_t type = reg->type;
xtensa_register_group_t rg = reg->group;
+ int cp_number;
/* First, skip registers that are not visible to this target
(unknown and unmapped registers when not using ISS). */
@@ -701,18 +759,20 @@ xtensa_register_reggroup_p (struct gdbar
if (group == vector_reggroup || group == xtensa_vectra_reggroup)
return rg & xtRegisterGroupVectra;
if (group == save_reggroup || group == restore_reggroup)
- return (regnum < NUM_REGS
+ return (regnum < gdbarch_num_regs (current_gdbarch)
&& (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
+ if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
+ return rg & (xtRegisterGroupCP0 << cp_number);
else
return 1;
}
-/* CORE FILE SUPPORT */
-
/* Supply register REGNUM from the buffer specified by GREGS and LEN
in the general-purpose register set REGSET to register cache
- REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+ REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
+
+static xtensa_elf_greg_t windowbase_always_zero = (xtensa_elf_greg_t)0;
static void
xtensa_supply_gregset (const struct regset *regset,
@@ -726,12 +786,16 @@ xtensa_supply_gregset (const struct regs
DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
- if (regnum == PC_REGNUM || regnum == -1)
- regcache_raw_supply (rc, PC_REGNUM, (char *) ®s->pc);
- if (regnum == PS_REGNUM || regnum == -1)
- regcache_raw_supply (rc, PS_REGNUM, (char *) ®s->ps);
+ if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1)
+ regcache_raw_supply (rc,
+ gdbarch_pc_regnum (current_gdbarch),
+ (char *) ®s->pc);
+ if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1)
+ regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch),
+ (char *) ®s->ps);
if (regnum == WB_REGNUM || regnum == -1)
- regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase);
+ /* In Xtensa GNU/Linux ptrace, windowbase is always 0. */
+ regcache_raw_supply (rc, WB_REGNUM, (char *) &windowbase_always_zero);
if (regnum == WS_REGNUM || regnum == -1)
regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart);
if (regnum == LBEG_REGNUM || regnum == -1)
@@ -742,10 +806,7 @@ xtensa_supply_gregset (const struct regs
regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount);
if (regnum == SAR_REGNUM || regnum == -1)
regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar);
- if (regnum == EXCCAUSE_REGNUM || regnum == -1)
- regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause);
- if (regnum == EXCVADDR_REGNUM || regnum == -1)
- regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr);
+
if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]);
else if (regnum == -1)
@@ -766,8 +827,8 @@ xtensa_gregset =
};
-/* Return the appropriate register set for the core section identified
- by SECT_NAME and SECT_SIZE. */
+/* Return the appropriate register set for the core
+ section identified by SECT_NAME and SECT_SIZE. */
static const struct regset *
xtensa_regset_from_core_section (struct gdbarch *core_arch,
@@ -786,29 +847,82 @@ xtensa_regset_from_core_section (struct
}
-/* F R A M E */
-
-/* We currently don't support the call0-abi, so we have at max. 12 registers
- saved on the stack. */
+/* Handling frames. */
-#define XTENSA_NUM_SAVED_AREGS 12
+/* Number of registers to save in case of Windowed ABI. */
+#define XTENSA_NUM_SAVED_AREGS 12
-typedef struct xtensa_frame_cache
+/* Frame cache part for Windowed ABI. */
+typedef struct xtensa_windowed_frame_cache
{
- CORE_ADDR base;
- CORE_ADDR pc;
- CORE_ADDR ra; /* The raw return address; use to compute call_inc. */
- CORE_ADDR ps;
int wb; /* Base for this frame; -1 if not in regfile. */
int callsize; /* Call size to next frame. */
int ws;
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
- CORE_ADDR prev_sp;
+} xtensa_windowed_frame_cache_t;
+
+/* Call0 ABI Definitions. */
+
+#define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
+#define C0_NREGS 16 /* Number of A-registers to track. */
+#define C0_CLESV 12 /* Callee-saved registers are here and up. */
+#define C0_SP 1 /* Register used as SP. */
+#define C0_FP 15 /* Register used as FP. */
+#define C0_RA 0 /* Register used as return address. */
+#define C0_ARGS 2 /* Register used as first arg/retval. */
+#define C0_NARGS 6 /* Number of A-regs for args/retvals. */
+
+/* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
+ A-register where the current content of the reg came from (in terms
+ of an original reg and a constant). Negative values of c0_rt[n].fp_reg
+ mean that the orignal content of the register was saved to the stack.
+ c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
+ know where SP will end up until the entire prologue has been analyzed. */
+
+#define C0_CONST -1 /* fr_reg value if register contains a constant. */
+#define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
+#define C0_NOSTK -1 /* to_stk value if register has not been stored. */
+
+extern xtensa_isa xtensa_default_isa;
+
+typedef struct xtensa_c0reg
+{
+ int fr_reg; /* original register from which register content
+ is derived, or C0_CONST, or C0_INEXP. */
+ int fr_ofs; /* constant offset from reg, or immediate value. */
+ int to_stk; /* offset from original SP to register (4-byte aligned),
+ or C0_NOSTK if register has not been saved. */
+} xtensa_c0reg_t;
+
+
+/* Frame cache part for Call0 ABI. */
+typedef struct xtensa_call0_frame_cache
+{
+ int c0_frmsz; /* Stack frame size. */
+ int c0_hasfp; /* Current frame uses frame pointer. */
+ int fp_regnum; /* A-register used as FP. */
+ int c0_fp; /* Actual value of frame pointer. */
+ xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
+} xtensa_call0_frame_cache_t;
+
+typedef struct xtensa_frame_cache
+{
+ CORE_ADDR base; /* Stack pointer of the next frame. */
+ CORE_ADDR pc; /* PC at the entry point to the function. */
+ CORE_ADDR ra; /* The raw return address. */
+ CORE_ADDR ps; /* The PS register of the frame. */
+ CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
+ int call0; /* It's a call0 framework (else windowed). */
+ union
+ {
+ xtensa_windowed_frame_cache_t wd; /* call0 == false. */
+ xtensa_call0_frame_cache_t c0; /* call0 == true. */
+ };
} xtensa_frame_cache_t;
static struct xtensa_frame_cache *
-xtensa_alloc_frame_cache (void)
+xtensa_alloc_frame_cache (int windowed)
{
xtensa_frame_cache_t *cache;
int i;
@@ -820,14 +934,31 @@ xtensa_alloc_frame_cache (void)
cache->base = 0;
cache->pc = 0;
cache->ra = 0;
- cache->wb = 0;
cache->ps = 0;
- cache->callsize = -1;
cache->prev_sp = 0;
+ cache->call0 = !windowed;
+ if (cache->call0)
+ {
+ cache->c0.c0_frmsz = -1;
+ cache->c0.c0_hasfp = 0;
+ cache->c0.fp_regnum = -1;
+ cache->c0.c0_fp = -1;
- for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
- cache->aregs[i] = -1;
+ for (i = 0; i < C0_NREGS; i++)
+ {
+ cache->c0.c0_rt[i].fr_reg = i;
+ cache->c0.c0_rt[i].fr_ofs = 0;
+ cache->c0.c0_rt[i].to_stk = C0_NOSTK;
+ }
+ }
+ else
+ {
+ cache->wd.wb = 0;
+ cache->wd.callsize = -1;
+ for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
+ cache->wd.aregs[i] = -1;
+ }
return cache;
}
@@ -842,11 +973,11 @@ xtensa_frame_align (struct gdbarch *gdba
static CORE_ADDR
xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- char buf[8];
+ gdb_byte buf[8];
DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
- frame_unwind_register (next_frame, PC_REGNUM, buf);
+ frame_unwind_register (next_frame, gdbarch_pc_regnum (current_gdbarch), buf);
DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
extract_typed_address (buf, builtin_type_void_func_ptr));
@@ -859,140 +990,150 @@ static struct frame_id
xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
CORE_ADDR pc, fp;
- char buf[4];
- /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
+ /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
pc = frame_pc_unwind (next_frame);
- frame_unwind_register (next_frame, A1_REGNUM, buf);
- fp = extract_unsigned_integer (buf, 4);
+ fp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
/* Make dummy frame ID unique by adding a constant. */
- return frame_id_build (fp+SP_ALIGNMENT, pc);
+ return frame_id_build (fp + SP_ALIGNMENT, pc);
}
+/* The key values to identify the frame using "cache" are
+
+ cache->base = SP of this frame;
+ cache->pc = entry-PC (entry point of the frame function);
+ cache->prev_sp = SP of the previous frame.
+*/
+
+static void
+call0_frame_cache (struct frame_info *next_frame,
+ xtensa_frame_cache_t *cache,
+ CORE_ADDR pc);
static struct xtensa_frame_cache *
xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
{
xtensa_frame_cache_t *cache;
- char buf[4];
CORE_ADDR ra, wb, ws, pc, sp, ps;
+ unsigned int ps_regnum = gdbarch_ps_regnum (current_gdbarch);
char op1;
+ int windowed;
DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
- /* Already cached? */
if (*this_cache)
return *this_cache;
+ windowed = windowing_enabled (xtensa_read_register (ps_regnum));
+
/* Get pristine xtensa-frame. */
- cache = xtensa_alloc_frame_cache ();
+ cache = xtensa_alloc_frame_cache (windowed);
*this_cache = cache;
- /* Get windowbase, windowstart, ps, and pc. */
- wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM);
- ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM);
- ps = frame_unwind_register_unsigned (next_frame, PS_REGNUM);
- pc = frame_unwind_register_unsigned (next_frame, PC_REGNUM);
-
- op1 = read_memory_integer (pc, 1);
- if (XTENSA_IS_ENTRY (op1) || !windowing_enabled (read_register (PS_REGNUM)))
- {
- int callinc = CALLINC (frame_unwind_register_unsigned (next_frame,
- PS_REGNUM));
- ra = frame_unwind_register_unsigned (next_frame,
- A0_REGNUM + callinc * 4);
-
- DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
- (int)pc, callinc);
-
- /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
- cache->callsize = 0;
- cache->wb = wb;
- cache->ws = ws;
- cache->prev_sp = read_register (A1_REGNUM);
- }
- else
- {
- ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM);
- cache->callsize = WINSIZE (ra);
- cache->wb = (wb - (cache->callsize / 4)) & ((NUM_AREGS / 4) - 1);
- cache->ws = ws & ~(1 << wb);
- }
-
- cache->pc = ((frame_func_unwind (next_frame) & 0xc0000000)
- | (ra & 0x3fffffff));
- cache->ps = (ps & ~PS_CALLINC_MASK) | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
-
-
- /* Note: We could also calculate the location on stack when we actually
- access the register. However, this approach, saving the location
- in the cache frame, is probably easier to support the call0 ABI. */
+ pc = frame_unwind_register_unsigned (next_frame,
+ gdbarch_pc_regnum (current_gdbarch));
- if (cache->ws == 0)
+ if (windowed)
{
- int i;
-
- /* Set A0...A3. */
- sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16;
+ /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
+ wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM);
+ ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM);
+ ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
- for (i = 0; i < 4; i++, sp += 4)
+ op1 = read_memory_integer (pc, 1);
+ if (XTENSA_IS_ENTRY (op1))
{
- cache->aregs[i] = sp;
+ int callinc = CALLINC (ps);
+ ra = frame_unwind_register_unsigned (next_frame,
+ A0_REGNUM + callinc * 4);
+
+ DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
+ (int)pc, callinc);
+
+ /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
+ cache->wd.callsize = 0;
+ cache->wd.wb = wb;
+ cache->wd.ws = ws;
+ cache->prev_sp = frame_unwind_register_unsigned (next_frame,
+ A1_REGNUM);
+ }
+ else
+ {
+ ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM);
+ cache->wd.callsize = WINSIZE (ra);
+ cache->wd.wb = (wb - cache->wd.callsize / 4) & (NUM_AREGS / 4 - 1);
+ cache->wd.ws = ws & ~(1 << wb);
}
- if (cache->callsize > 4)
+ cache->pc = frame_func_unwind (next_frame);
+ cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
+ cache->ps = (ps & ~PS_CALLINC_MASK)
+ | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
+
+ if (cache->wd.ws == 0)
{
- /* Set A4...A7/A11. */
+ int i;
- sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
- sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
- sp -= cache->callsize * 4;
+ /* Set A0...A3. */
+ sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16;
+
+ for (i = 0; i < 4; i++, sp += 4)
+ {
+ cache->wd.aregs[i] = sp;
+ }
- for ( /* i=4 */ ; i < cache->callsize; i++, sp += 4)
+ if (cache->wd.callsize > 4)
{
- cache->aregs[i] = sp;
+ /* Set A4...A7/A11. */
+ /* Read an SP of the previous frame. */
+ sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
+ sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
+ sp -= cache->wd.callsize * 4;
+
+ for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
+ {
+ cache->wd.aregs[i] = sp;
+ }
}
}
- }
- if (cache->prev_sp == 0)
- {
- if (cache->ws == 0)
- {
- /* Register window overflow already happened.
- We can read caller's frame SP from the proper spill loction. */
- cache->prev_sp =
- read_memory_integer (cache->aregs[1],
- register_size (current_gdbarch,
- A1_REGNUM));
- }
- else
+ if ((cache->prev_sp == 0) && ( ra != 0 ))
+ /* If RA is equal to 0 this frame is an outermost frame. Leave
+ cache->prev_sp unchanged marking the boundary of the frame stack. */
{
- /* Read caller's frame SP directly from the previous window. */
-
- int regnum = AREG_NUMBER (A1_REGNUM, cache->wb);
+ if (cache->wd.ws == 0)
+ {
+ /* Register window overflow already happened.
+ We can read caller's SP from the proper spill loction. */
+ cache->prev_sp =
+ read_memory_integer (cache->wd.aregs[1],
+ register_size (current_gdbarch,
+ A1_REGNUM));
+ }
+ else
+ {
+ /* Read caller's frame SP directly from the previous window. */
+ int regnum = AREG_NUMBER (A1_REGNUM, cache->wd.wb);
- cache->prev_sp = read_register (regnum);
+ cache->prev_sp = xtensa_read_register (regnum);
+ }
}
}
+ else /* Call0 framework. */
+ {
+ call0_frame_cache (next_frame, cache, pc);
+ }
cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM);
- DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, "
- "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n",
- (unsigned int) cache->base, (unsigned int) cache->wb,
- cache->ws, cache->callsize, (unsigned int) cache->pc,
- (unsigned int) cache->ps, (unsigned int) cache->prev_sp);
-
return cache;
}
-
static void
xtensa_frame_this_id (struct frame_info *next_frame,
void **this_cache,
@@ -1000,6 +1141,7 @@ xtensa_frame_this_id (struct frame_info
{
struct xtensa_frame_cache *cache =
xtensa_frame_cache (next_frame, this_cache);
+ struct frame_id id;
DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n",
(unsigned int) next_frame, (unsigned int) *this_cache);
@@ -1007,9 +1149,62 @@ xtensa_frame_this_id (struct frame_info
if (cache->prev_sp == 0)
return;
- (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
+ id = frame_id_build (cache->prev_sp, cache->pc);
+ if (frame_id_eq (id, get_frame_id(next_frame)))
+ {
+ warning(_("\
+Frame stack is corrupted. That could happen because of \
+setting register(s) from GDB or stopping execution \
+inside exception handler. Frame backtracing has stopped. \
+It can make some GDB commands work inappropriately.\n"));
+ cache->prev_sp = 0;
+ return;
+ }
+ (*this_id) = id;
}
+static int
+call0_frame_get_reg_at_entry (struct frame_info *next_frame,
+ struct xtensa_frame_cache *cache,
+ int regnum,
+ CORE_ADDR *addrp,
+ enum lval_type *lval,
+ gdb_byte *valuep)
+{
+ CORE_ADDR fp, spe;
+ int stkofs;
+ int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
+ ? regnum - AR_BASE : regnum;
+
+ /* Determine stack pointer on entry to this function, based on FP. */
+ spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
+
+ /* If register was saved to the stack frame in the prologue, retrieve it. */
+ stkofs = cache->c0.c0_rt[reg].to_stk;
+ if (stkofs != C0_NOSTK)
+ {
+ *lval = lval_memory;
+ *addrp = spe + stkofs;
+
+ if (valuep)
+ read_memory (*addrp, valuep, register_size (current_gdbarch, regnum));
+
+ return 1;
+ }
+
+ /* If not callee-saved or if known to have been overwritten, give up. */
+ if (reg < C0_CLESV
+ || cache->c0.c0_rt[reg].fr_reg != reg
+ || cache->c0.c0_rt[reg].fr_ofs != 0)
+ return 0;
+
+ if (get_frame_type (next_frame) != NORMAL_FRAME)
+ /* TODO: Do we need a special case for DUMMY_FRAME here? */
+ return 0;
+
+ return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
+ cache, regnum, addrp, lval, valuep);
+}
static void
xtensa_frame_prev_register (struct frame_info *next_frame,
@@ -1029,22 +1224,29 @@ xtensa_frame_prev_register (struct frame
DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, "
"*this 0x%08x, regnum %d (%s), ...)\n",
(unsigned int) next_frame,
- *this_cache? (unsigned int) *this_cache : 0, regnum,
+ *this_cache ? (unsigned int) *this_cache : 0, regnum,
xtensa_register_name (regnum));
- if (regnum == WS_REGNUM)
+ if (regnum ==gdbarch_pc_regnum (current_gdbarch))
+ saved_reg = cache->ra;
+ else if (regnum == A1_REGNUM)
+ saved_reg = cache->prev_sp;
+ else if (!cache->call0)
{
- if (cache->ws != 0)
- saved_reg = cache->ws;
+ if (regnum == WS_REGNUM)
+ {
+ if (cache->wd.ws != 0)
+ saved_reg = cache->wd.ws;
+ else
+ saved_reg = 1 << cache->wd.wb;
+ }
+ else if (regnum == WB_REGNUM)
+ saved_reg = cache->wd.wb;
+ else if (regnum == gdbarch_ps_regnum (current_gdbarch))
+ saved_reg = cache->ps;
else
- saved_reg = 1 << cache->wb;
+ done = 0;
}
- else if (regnum == WB_REGNUM)
- saved_reg = cache->wb;
- else if (regnum == PC_REGNUM)
- saved_reg = cache->pc;
- else if (regnum == PS_REGNUM)
- saved_reg = cache->ps;
else
done = 0;
@@ -1060,35 +1262,69 @@ xtensa_frame_prev_register (struct frame
return;
}
- /* Convert Ax register numbers to ARx register numbers. */
- if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
- regnum = AREG_NUMBER (regnum, cache->wb);
-
- /* Check if ARx register has been saved to stack. */
- if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS))
+ if (!cache->call0) /* Windowed ABI. */
{
- int areg = regnum - AR_BASE - (cache->wb * 4);
+ /* Convert A-register numbers to AR-register numbers. */
+ if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
+ regnum = AREG_NUMBER (regnum, cache->wd.wb);
- if (areg >= 0
- && areg < XTENSA_NUM_SAVED_AREGS
- && cache->aregs[areg] != -1)
- {
- *optimizedp = 0;
- *lvalp = lval_memory;
- *addrp = cache->aregs[areg];
- *realnump = -1;
+ /* Check if AR-register has been saved to stack. */
+ if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS))
+ {
+ int areg = regnum - AR_BASE - (cache->wd.wb * 4);
- if (valuep)
- read_memory (*addrp, valuep,
- register_size (current_gdbarch, regnum));
+ if (areg >= 0
+ && areg < XTENSA_NUM_SAVED_AREGS
+ && cache->wd.aregs[areg] != -1)
+ {
+ *optimizedp = 0;
+ *lvalp = lval_memory;
+ *addrp = cache->wd.aregs[areg];
+ *realnump = -1;
- DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
- return;
+ if (valuep)
+ read_memory (*addrp, valuep,
+ register_size (current_gdbarch, regnum));
+
+ DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
+ return;
+ }
}
}
+ else /* Call0 ABI. */
+ {
+ int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
+ ? regnum - AR_BASE : regnum;
- /* Note: All other registers have been either saved to the dummy stack
- or are still alive in the processor. */
+ if (reg < C0_NREGS)
+ {
+ CORE_ADDR spe;
+ int stkofs;
+
+ /* If register was saved in the prologue, retrieve it. */
+ stkofs = cache->c0.c0_rt[reg].to_stk;
+ if (stkofs != C0_NOSTK)
+ {
+ /* Determine SP on entry based on FP. */
+ spe = cache->c0.c0_fp
+ - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
+ *optimizedp = 0;
+ *lvalp = lval_memory;
+ *addrp = spe + stkofs;
+ *realnump = -1;
+
+ if (valuep)
+ read_memory (*addrp, valuep,
+ register_size (current_gdbarch, regnum));
+
+ DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
+ return;
+ }
+ }
+ }
+
+ /* All other registers have been either saved to
+ the stack or are still alive in the processor. */
*optimizedp = 0;
*lvalp = lval_register;
@@ -1147,23 +1383,32 @@ xtensa_extract_return_value (struct type
gdb_assert(len > 0);
- /* First, we have to find the caller window in the register file. */
- regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc);
- callsize = extract_call_winsize (pc);
+ if (CALL_ABI != CallAbiCall0Only)
+ {
+ /* First, we have to find the caller window in the register file. */
+ regcache_raw_read_unsigned (regcache,
+ gdbarch_pc_regnum (current_gdbarch), &pc);
+ callsize = extract_call_winsize (pc);
- /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */
- if (len > (callsize > 8 ? 8 : 16))
- internal_error (__FILE__, __LINE__,
- _("cannot extract return value of %d bytes long"), len);
+ /* On Xtensa, we can return up to 4 words (or 2 for call12). */
+ if (len > (callsize > 8 ? 8 : 16))
+ internal_error (__FILE__, __LINE__,
+ _("cannot extract return value of %d bytes long"), len);
- /* Get the register offset of the return register (A2) in the caller
- window. */
- regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
- areg = AREG_NUMBER(A2_REGNUM + callsize, wb);
+ /* Get the register offset of the return
+ register (A2) in the caller window. */
+ regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
+ areg = AREG_NUMBER(A2_REGNUM + callsize, wb);
+ }
+ else
+ {
+ /* No windowing hardware - Call0 ABI. */
+ areg = A0_REGNUM + C0_ARGS;
+ }
DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
- if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
offset = 4 - len;
for (; len > 0; len -= 4, areg++, valbuf += 4)
@@ -1190,23 +1435,30 @@ xtensa_store_return_value (struct type *
DEBUGTRACE ("xtensa_store_return_value (...)\n");
- regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
- regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc);
- callsize = extract_call_winsize (pc);
+ if (CALL_ABI != CallAbiCall0Only)
+ {
+ regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
+ regcache_raw_read_unsigned (regcache,
+ gdbarch_pc_regnum (current_gdbarch), &pc);
+ callsize = extract_call_winsize (pc);
- if (len > (callsize > 8 ? 8 : 16))
- internal_error (__FILE__, __LINE__,
- _("unimplemented for this length: %d"),
- TYPE_LENGTH (type));
+ if (len > (callsize > 8 ? 8 : 16))
+ internal_error (__FILE__, __LINE__,
+ _("unimplemented for this length: %d"),
+ TYPE_LENGTH (type));
+ areg = AREG_NUMBER (A2_REGNUM + callsize, wb);
- DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
+ DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
callsize, (int) wb);
+ }
+ else
+ {
+ areg = A0_REGNUM + C0_ARGS;
+ }
- if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
offset = 4 - len;
- areg = AREG_NUMBER (A2_REGNUM + callsize, wb);
-
for (; len > 0; len -= 4, areg++, valbuf += 4)
{
if (len < 4)
@@ -1217,14 +1469,14 @@ xtensa_store_return_value (struct type *
}
-enum return_value_convention
+static enum return_value_convention
xtensa_return_value (struct gdbarch *gdbarch,
struct type *valtype,
struct regcache *regcache,
gdb_byte *readbuf,
const gdb_byte *writebuf)
{
- /* Note: Structures up to 16 bytes are returned in registers. */
+ /* Structures up to 16 bytes are returned in registers. */
int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
|| TYPE_CODE (valtype) == TYPE_CODE_UNION
@@ -1265,7 +1517,7 @@ xtensa_push_dummy_call (struct gdbarch *
{
int i;
int size, onstack_size;
- char *buf = (char *) alloca (16);
+ gdb_byte *buf = (gdb_byte *) alloca (16);
CORE_ADDR ra, ps;
struct argument_info
{
@@ -1350,7 +1602,8 @@ xtensa_push_dummy_call (struct gdbarch *
arg_type = builtin_type_long;
arg = value_cast (arg_type, arg);
}
- info->align = TYPE_LENGTH (builtin_type_long);
+ /* Aligment is equal to the type length for the basic types. */
+ info->align = TYPE_LENGTH (arg_type);
break;
case TYPE_CODE_FLT:
@@ -1374,7 +1627,7 @@ xtensa_push_dummy_call (struct gdbarch *
size = (size + info->align - 1) & ~(info->align - 1);
onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
- if (size + info->length > REGISTER_SIZE * ARGS_NUM_REGS)
+ if (size + info->length > REGISTER_SIZE * ARG_NOF)
{
info->onstack = 1;
info->u.offset = onstack_size;
@@ -1383,7 +1636,7 @@ xtensa_push_dummy_call (struct gdbarch *
else
{
info->onstack = 0;
- info->u.regno = ARGS_FIRST_REG + size / REGISTER_SIZE;
+ info->u.regno = ARG_1ST + size / REGISTER_SIZE;
}
size += info->length;
}
@@ -1391,8 +1644,8 @@ xtensa_push_dummy_call (struct gdbarch *
/* Adjust the stack pointer and align it. */
sp = align_down (sp - onstack_size, SP_ALIGNMENT);
- /* Simulate MOVSP. */
- if (sp != osp)
+ /* Simulate MOVSP, if Windowed ABI. */
+ if ((CALL_ABI != CallAbiCall0Only) && (sp != osp))
{
read_memory (osp - 16, buf, 16);
write_memory (sp - 16, buf, 16);
@@ -1403,7 +1656,7 @@ xtensa_push_dummy_call (struct gdbarch *
if (struct_return)
{
store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
- regcache_cooked_write (regcache, ARGS_FIRST_REG, buf);
+ regcache_cooked_write (regcache, ARG_1ST, buf);
}
for (i = 0; i < nargs; i++)
@@ -1419,7 +1672,8 @@ xtensa_push_dummy_call (struct gdbarch *
word in big-endian mode and require a shift. This only
applies for structures smaller than one word. */
- if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (n < REGISTER_SIZE
+ && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
offset += (REGISTER_SIZE - n);
write_memory (offset, info->contents, info->length);
@@ -1437,7 +1691,8 @@ xtensa_push_dummy_call (struct gdbarch *
than REGISTER_SIZE; for larger odd-sized structures the excess
will be left-aligned in the register on both endiannesses. */
- if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (n < REGISTER_SIZE
+ && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
{
ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
@@ -1452,10 +1707,8 @@ xtensa_push_dummy_call (struct gdbarch *
else
while (n > 0)
{
- /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/
regcache_cooked_write (regcache, r, cp);
- /* write_register (r, v); */
cp += REGISTER_SIZE;
n -= REGISTER_SIZE;
r++;
@@ -1463,16 +1716,25 @@ xtensa_push_dummy_call (struct gdbarch *
}
}
-
/* Set the return address of dummy frame to the dummy address.
- Note: The return address for the current function (in A0) is
+ The return address for the current function (in A0) is
saved in the dummy frame, so we can savely overwrite A0 here. */
- ra = (bp_addr & 0x3fffffff) | 0x40000000;
- regcache_raw_read (regcache, PS_REGNUM, buf);
- ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
- regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra);
- regcache_cooked_write_unsigned (regcache, PS_REGNUM, ps | 0x00010000);
+ if (CALL_ABI != CallAbiCall0Only)
+ {
+ ra = (bp_addr & 0x3fffffff) | 0x40000000;
+ regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf);
+ ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
+ regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra);
+ regcache_cooked_write_unsigned (regcache,
+ gdbarch_ps_regnum (current_gdbarch),
+ ps | 0x00010000);
+ }
+ else
+ {
+ /* Simulate CALL0: write RA into A0 register. */
+ regcache_cooked_write_unsigned (regcache, A0_REGNUM, bp_addr);
+ }
/* Set new stack pointer and return it. */
regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp);
@@ -1490,19 +1752,19 @@ xtensa_push_dummy_call (struct gdbarch *
#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
-const unsigned char *
+static const unsigned char *
xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
{
- static char big_breakpoint[] = BIG_BREAKPOINT;
- static char little_breakpoint[] = LITTLE_BREAKPOINT;
- static char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
- static char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
+ static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
+ static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
+ static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
+ static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
if (ISA_USE_DENSITY_INSTRUCTIONS)
{
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
{
*lenptr = sizeof (density_big_breakpoint);
return density_big_breakpoint;
@@ -1515,7 +1777,7 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pc
}
else
{
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
{
*lenptr = sizeof (big_breakpoint);
return big_breakpoint;
@@ -1528,13 +1790,548 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pc
}
}
+/* Call0 ABI support routines. */
-/* Return the pc of the first real instruction. We assume that this
- machine uses register windows.
+/* Call0 opcode class. Opcodes are preclassified according to what they
+ mean for Call0 prologue analysis, and their number of significant operands.
+ The purpose of this is to simplify prologue analysis by separating
+ instruction decoding (libisa) from the semantics of prologue analysis. */
+
+typedef enum {
+ c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
+ c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
+ c0opc_flow, /* Flow control insn. */
+ c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
+ c0opc_break, /* Debugger software breakpoints. */
+ c0opc_add, /* Adding two registers. */
+ c0opc_addi, /* Adding a register and an immediate. */
+ c0opc_sub, /* Subtracting a register from a register. */
+ c0opc_mov, /* Moving a register to a register. */
+ c0opc_movi, /* Moving an immediate to a register. */
+ c0opc_l32r, /* Loading a literal. */
+ c0opc_s32i, /* Storing word at fixed offset from a base register. */
+ c0opc_NrOf /* Number of opcode classifications. */
+} xtensa_insn_kind;
+
+
+/* Classify an opcode based on what it means for Call0 prologue analysis. */
+
+static xtensa_insn_kind
+call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
+{
+ const char *opcname;
+ xtensa_insn_kind opclass = c0opc_uninteresting;
+
+ DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
+
+ /* Get opcode name and handle special classifications. */
+
+ opcname = xtensa_opcode_name (isa, opc);
+
+ if (opcname == NULL
+ || strcasecmp (opcname, "ill") == 0
+ || strcasecmp (opcname, "ill.n") == 0)
+ opclass = c0opc_illegal;
+ else if (strcasecmp (opcname, "break") == 0
+ || strcasecmp (opcname, "break.n") == 0)
+ opclass = c0opc_break;
+ else if (strcasecmp (opcname, "entry") == 0)
+ opclass = c0opc_entry;
+ else if (xtensa_opcode_is_branch (isa, opc) > 0
+ || xtensa_opcode_is_jump (isa, opc) > 0
+ || xtensa_opcode_is_loop (isa, opc) > 0
+ || xtensa_opcode_is_call (isa, opc) > 0
+ || strcasecmp (opcname, "simcall") == 0
+ || strcasecmp (opcname, "syscall") == 0)
+ opclass = c0opc_flow;
+
+ /* Also, classify specific opcodes that need to be tracked. */
+ else if (strcasecmp (opcname, "add") == 0
+ || strcasecmp (opcname, "add.n") == 0)
+ opclass = c0opc_add;
+ else if (strcasecmp (opcname, "addi") == 0
+ || strcasecmp (opcname, "addi.n") == 0
+ || strcasecmp (opcname, "addmi") == 0)
+ opclass = c0opc_addi;
+ else if (strcasecmp (opcname, "sub") == 0)
+ opclass = c0opc_sub;
+ else if (strcasecmp (opcname, "mov.n") == 0
+ || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
+ opclass = c0opc_mov;
+ else if (strcasecmp (opcname, "movi") == 0
+ || strcasecmp (opcname, "movi.n") == 0)
+ opclass = c0opc_movi;
+ else if (strcasecmp (opcname, "l32r") == 0)
+ opclass = c0opc_l32r;
+ else if (strcasecmp (opcname, "s32i") == 0
+ || strcasecmp (opcname, "s32i.n") == 0)
+ opclass = c0opc_s32i;
+
+ return opclass;
+}
+
+/* Tracks register movement/mutation for a given operation, which may
+ be within a bundle. Updates the destination register tracking info
+ accordingly. The pc is needed only for pc-relative load instructions
+ (eg. l32r). The SP register number is needed to identify stores to
+ the stack frame. */
+
+static void
+call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
+ xtensa_insn_kind opclass, int nods, unsigned odv[],
+ CORE_ADDR pc, int spreg)
+{
+ unsigned litbase, litaddr, litval;
+
+ switch (opclass)
+ {
+ case c0opc_addi:
+ /* 3 operands: dst, src, imm. */
+ gdb_assert (nods == 3);
+ dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
+ break;
+ case c0opc_add:
+ /* 3 operands: dst, src1, src2. */
+ gdb_assert (nods == 3);
+ if (src[odv[1]].fr_reg == C0_CONST)
+ {
+ dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
+ }
+ else if (src[odv[2]].fr_reg == C0_CONST)
+ {
+ dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
+ }
+ else dst[odv[0]].fr_reg = C0_INEXP;
+ break;
+ case c0opc_sub:
+ /* 3 operands: dst, src1, src2. */
+ gdb_assert (nods == 3);
+ if (src[odv[2]].fr_reg == C0_CONST)
+ {
+ dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
+ }
+ else dst[odv[0]].fr_reg = C0_INEXP;
+ break;
+ case c0opc_mov:
+ /* 2 operands: dst, src [, src]. */
+ gdb_assert (nods == 2);
+ dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
+ break;
+ case c0opc_movi:
+ /* 2 operands: dst, imm. */
+ gdb_assert (nods == 2);
+ dst[odv[0]].fr_reg = C0_CONST;
+ dst[odv[0]].fr_ofs = odv[1];
+ break;
+ case c0opc_l32r:
+ /* 2 operands: dst, literal offset. */
+ gdb_assert (nods == 2);
+ /* litbase = xtensa_get_litbase (pc); can be also used. */
+ litbase = (LITBASE_REGNUM == -1)
+ ? 0 : xtensa_read_register (LITBASE_REGNUM);
+ litaddr = litbase & 1
+ ? (litbase & ~1) + (signed)odv[1]
+ : (pc + 3 + (signed)odv[1]) & ~3;
+ litval = read_memory_integer(litaddr, 4);
+ dst[odv[0]].fr_reg = C0_CONST;
+ dst[odv[0]].fr_ofs = litval;
+ break;
+ case c0opc_s32i:
+ /* 3 operands: value, base, offset. */
+ gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
+ if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
+ && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
+ && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
+ && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
+ && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
+ {
+ /* ISA encoding guarantees alignment. But, check it anyway. */
+ gdb_assert ((odv[2] & 3) == 0);
+ dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
+ }
+ break;
+ default:
+ gdb_assert (0);
+ }
+}
+
+/* Analyze prologue of the function at start address to determine if it uses
+ the Call0 ABI, and if so track register moves and linear modifications
+ in the prologue up to the PC or just beyond the prologue, whichever is first.
+ An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
+ The prologue may overlap non-prologue instructions but is guaranteed to end
+ by the first flow-control instruction (jump, branch, call or return).
+ Since an optimized function may move information around and change the
+ stack frame arbitrarily during the prologue, the information is guaranteed
+ valid only at the point in the function indicated by the PC.
+ May be used to skip the prologue or identify the ABI, w/o tracking.
+
+ Returns: Address of first instruction after prologue, or PC (whichever
+ is first), or 0, if decoding failed (in libisa).
+ Input args:
+ start Start address of function/prologue.
+ pc Program counter to stop at. Use 0 to continue to end of prologue.
+ If 0, avoids infinite run-on in corrupt code memory by bounding
+ the scan to the end of the function if that can be determined.
+ nregs Number of general registers to track (size of rt[] array).
+ InOut args:
+ rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
+ If NULL, registers are not tracked.
+ Output args:
+ call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
+ (more accurately, non-zero until 'entry' insn is encountered).
+
+ Note that these may produce useful results even if decoding fails
+ because they begin with default assumptions that analysis may change. */
+
+static CORE_ADDR
+call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
+ int nregs, xtensa_c0reg_t rt[], int *call0)
+{
+ CORE_ADDR ia; /* Current insn address in prologue. */
+ CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
+ CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
+ #define BSZ 32 /* Instruction buffer size. */
+ char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
+ xtensa_isa isa; /* libisa ISA handle. */
+ xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
+ xtensa_format ifmt; /* libisa instruction format. */
+ int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
+ xtensa_opcode opc; /* Opcode in current slot. */
+ xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
+ int nods; /* Opcode number of operands. */
+ unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
+ xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
+ int j; /* General loop counter. */
+ int fail = 0; /* Set non-zero and exit, if decoding fails. */
+ CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
+ CORE_ADDR end_pc; /* The PC for the lust function insn. */
+
+ struct symtab_and_line prologue_sal;
+
+ DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
+ (int)start, (int)pc);
+
+ /* Try to limit the scan to the end of the function if a non-zero pc
+ arg was not supplied to avoid probing beyond the end of valid memory.
+ If memory is full of garbage that classifies as c0opc_uninteresting.
+ If this fails (eg. if no symbols) pc ends up 0 as it was.
+ Intialize the Call0 frame and register tracking info.
+ Assume it's Call0 until an 'entry' instruction is encountered.
+ Assume we may be in the prologue until we hit a flow control instr. */
+
+ rtmp = NULL;
+ body_pc = INT_MAX;
+ end_pc = 0;
+
+ /* Find out, if we have an information about the prologue from DWARF. */
+ prologue_sal = find_pc_line (start, 0);
+ if (prologue_sal.line != 0) /* Found debug info. */
+ body_pc = prologue_sal.end;
+
+ /* If we are going to analyze the prologue in general without knowing about
+ the current PC, make the best assumtion for the end of the prologue. */
+ if (pc == 0)
+ {
+ find_pc_partial_function (start, 0, NULL, &end_pc);
+ body_pc = min (end_pc, body_pc);
+ }
+ else
+ body_pc = min (pc, body_pc);
+
+ if (call0 != NULL)
+ *call0 = 1;
+
+ if (rt != NULL)
+ {
+ rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
+ /* rt is already initialized in xtensa_alloc_frame_cache(). */
+ }
+ else nregs = 0;
+
+ isa = xtensa_default_isa;
+ gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
+ ins = xtensa_insnbuf_alloc (isa);
+ slot = xtensa_insnbuf_alloc (isa);
+
+ for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
+ {
+ /* (Re)fill instruction buffer from memory if necessary, but do not
+ read memory beyond PC to be sure we stay within text section
+ (this protection only works if a non-zero pc is supplied). */
+
+ if (ia + xtensa_isa_maxlength (isa) > bt)
+ {
+ ba = ia;
+ bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
+ read_memory (ba, ibuf, bt - ba);
+ }
+
+ /* Decode format information. */
+
+ xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
+ ifmt = xtensa_format_decode (isa, ins);
+ if (ifmt == XTENSA_UNDEFINED)
+ {
+ fail = 1;
+ goto done;
+ }
+ ilen = xtensa_format_length (isa, ifmt);
+ if (ilen == XTENSA_UNDEFINED)
+ {
+ fail = 1;
+ goto done;
+ }
+ islots = xtensa_format_num_slots (isa, ifmt);
+ if (islots == XTENSA_UNDEFINED)
+ {
+ fail = 1;
+ goto done;
+ }
+
+ /* Analyze a bundle or a single instruction, using a snapshot of
+ the register tracking info as input for the entire bundle so that
+ register changes do not take effect within this bundle. */
+
+ for (j = 0; j < nregs; ++j)
+ rtmp[j] = rt[j];
+
+ for (is = 0; is < islots; ++is)
+ {
+ /* Decode a slot and classify the opcode. */
+
+ fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
+ if (fail)
+ goto done;
+
+ opc = xtensa_opcode_decode (isa, ifmt, is, slot);
+ DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
+ (unsigned)ia, opc);
+ if (opc == XTENSA_UNDEFINED)
+ opclass = c0opc_illegal;
+ else
+ opclass = call0_classify_opcode (isa, opc);
+
+ /* Decide whether to track this opcode, ignore it, or bail out. */
+
+ switch (opclass)
+ {
+ case c0opc_illegal:
+ case c0opc_break:
+ fail = 1;
+ goto done;
+
+ case c0opc_uninteresting:
+ continue;
+
+ case c0opc_flow:
+ goto done;
+
+ case c0opc_entry:
+ if (call0 != NULL)
+ *call0 = 0;
+ ia += ilen; /* Skip over 'entry' insn. */
+ goto done;
+
+ default:
+ if (call0 != NULL)
+ *call0 = 1;
+ }
+
+ /* Only expected opcodes should get this far. */
+ if (rt == NULL)
+ continue;
+
+ /* Extract and decode the operands. */
+ nods = xtensa_opcode_num_operands (isa, opc);
+ if (nods == XTENSA_UNDEFINED)
+ {
+ fail = 1;
+ goto done;
+ }
+
+ for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
+ {
+ fail = xtensa_operand_get_field (isa, opc, j, ifmt,
+ is, slot, &odv[j]);
+ if (fail)
+ goto done;
+
+ fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
+ if (fail)
+ goto done;
+ }
+
+ /* Check operands to verify use of 'mov' assembler macro. */
+ if (opclass == c0opc_mov && nods == 3)
+ {
+ if (odv[2] == odv[1])
+ nods = 2;
+ else
+ {
+ opclass = c0opc_uninteresting;
+ continue;
+ }
+ }
+
+ /* Track register movement and modification for this operation. */
+ call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
+ }
+ }
+done:
+ DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
+ (unsigned)ia, fail ? "failed" : "succeeded");
+ xtensa_insnbuf_free(isa, slot);
+ xtensa_insnbuf_free(isa, ins);
+ return fail ? 0 : ia;
+}
+
+/* Initialize frame cache for the current frame. The "next_frame" is the next
+ one relative to current frame. "cache" is the pointer to the data structure
+ we have to initialize. "pc" is curretnt PC. */
+
+static void
+call0_frame_cache (struct frame_info *next_frame,
+ xtensa_frame_cache_t *cache, CORE_ADDR pc)
+{
+ CORE_ADDR start_pc; /* The beginning of the function. */
+ CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
+ CORE_ADDR sp, fp, ra;
+ int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
+
+ /* Find the beginning of the prologue of the function containing the PC
+ and analyze it up to the PC or the end of the prologue. */
+
+ if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
+ {
+ body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
+ &cache->c0.c0_rt[0],
+ &cache->call0);
+ }
+
+ sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
+ fp = sp; /* Assume FP == SP until proven otherwise. */
+
+ /* Get the frame information and FP (if used) at the current PC.
+ If PC is in the prologue, the prologue analysis is more reliable
+ than DWARF info. We don't not know for sure if PC is in the prologue,
+ but we know no calls have yet taken place, so we can almost
+ certainly rely on the prologue analysis. */
+
+ if (body_pc <= pc)
+ {
+ /* Prologue analysis was successful up to the PC.
+ It includes the cases when PC == START_PC. */
+ c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
+ /* c0_hasfp == true means there is a frame pointer because
+ we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
+ was derived from SP. Otherwise, it would be C0_FP. */
+ fp_regnum = c0_hasfp ? C0_FP : C0_SP;
+ c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
+ fp_regnum += A0_BASE;
+ }
+ else /* No data from the prologue analysis. */
+ {
+ c0_hasfp = 0;
+ fp_regnum = A0_BASE + C0_SP;
+ c0_frmsz = 0;
+ start_pc = pc;
+ }
+
+ prev_sp = fp + c0_frmsz;
+
+ /* Frame size from debug info or prologue tracking does not account for
+ alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
+ if (c0_hasfp)
+ {
+ fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
+
+ /* Recalculate previous SP. */
+ prev_sp = fp + c0_frmsz;
+ /* Update the stack frame size. */
+ c0_frmsz += fp - sp;
+ }
+
+ /* Get the return address (RA) from the stack if saved,
+ or try to get it from a register. */
+
+ to_stk = cache->c0.c0_rt[C0_RA].to_stk;
+ if (to_stk != C0_NOSTK)
+ ra = (CORE_ADDR)
+ read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
+
+ else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
+ && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
+ {
+ /* Special case for terminating backtrace at a function that wants to
+ be seen as the outermost. Such a function will clear it's RA (A0)
+ register to 0 in the prologue instead of saving its original value. */
+ ra = 0;
+ }
+ else
+ {
+ /* RA was copied to another register or (before any function call) may
+ still be in the original RA register. This is not always reliable:
+ even in a leaf function, register tracking stops after prologue, and
+ even in prologue, non-prologue instructions (not tracked) may overwrite
+ RA or any register it was copied to. If likely in prologue or before
+ any call, use retracking info and hope for the best (compiler should
+ have saved RA in stack if not in a leaf function). If not in prologue,
+ too bad. */
+
+ int i;
+ for (i = 0;
+ (i < C0_NREGS) &&
+ (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
+ ++i);
+ if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
+ i = C0_RA;
+ if (i < C0_NREGS) /* Read from the next_frame. */
+ {
+ ra = frame_unwind_register_unsigned (next_frame,
+ A0_REGNUM + cache->c0.c0_rt[i].fr_reg);
+ }
+ else ra = 0;
+ }
+
+ cache->pc = start_pc;
+ cache->ra = ra;
+ /* RA == 0 marks the outermost frame. Do not go past it. */
+ cache->prev_sp = (ra != 0) ? prev_sp : 0;
+ cache->c0.fp_regnum = fp_regnum;
+ cache->c0.c0_frmsz = c0_frmsz;
+ cache->c0.c0_hasfp = c0_hasfp;
+ cache->c0.c0_fp = fp;
+}
+
+
+/* Skip function prologue.
+
+ Return the pc of the first instruction after prologue. GDB calls this to
+ find the address of the first line of the function or (if there is no line
+ number information) to skip the prologue for planting breakpoints on
+ function entries. Use debug info (if present) or prologue analysis to skip
+ the prologue to achieve reliable debugging behavior. For windowed ABI,
+ only the 'entry' instruction is skipped. It is not strictly necessary to
+ skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
+ backtrace at any point in the prologue, however certain potential hazards
+ are avoided and a more "normal" debugging experience is ensured by
+ skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
+ For example, if we don't skip the prologue:
+ - Some args may not yet have been saved to the stack where the debug
+ info expects to find them (true anyway when only 'entry' is skipped);
+ - Software breakpoints ('break' instrs) may not have been unplanted
+ when the prologue analysis is done on initializing the frame cache,
+ and breaks in the prologue will throw off the analysis.
If we have debug info ( line-number info, in particular ) we simply skip
the code associated with the first function line effectively skipping
- the prologue code. It works even in cases like
+ the prologue code. It works even in cases like
int main()
{ int local_var = 1;
@@ -1546,41 +2343,49 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pc
section to make sure there is a boundary between the prologue code and
the rest of the function.
- If there is no debug info, we need to analyze the code. */
+ If there is no debug info, we need to analyze the code. */
+
+/* #define DONT_SKIP_PROLOGUE */
CORE_ADDR
xtensa_skip_prologue (CORE_ADDR start_pc)
{
+ struct symtab_and_line prologue_sal;
+ CORE_ADDR body_pc;
+
DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
- if (ISA_USE_WINDOWED_REGISTERS)
+#if DONT_SKIP_PROLOGUE
+ return start_pc;
+#endif
+
+ /* Try to find first body line from debug info. */
+
+ prologue_sal = find_pc_line (start_pc, 0);
+ if (prologue_sal.line != 0) /* Found debug info. */
{
- unsigned char op1;
- struct symtab_and_line prologue_sal;
+ /* In Call0, it is possible to have a function with only one instruction
+ ('ret') resulting from a 1-line optimized function that does nothing.
+ In that case, prologue_sal.end may actually point to the start of the
+ next function in the text section, causing a breakpoint to be set at
+ the wrong place. Check if the end address is in a different function,
+ and if so return the start PC. We know we have symbol info. */
- op1 = read_memory_integer (start_pc, 1);
- if (!XTENSA_IS_ENTRY (op1))
+ CORE_ADDR end_func;
+
+ find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
+ if (end_func != start_pc)
return start_pc;
- prologue_sal = find_pc_line (start_pc, 0);
- if (prologue_sal.line != 0)
- return prologue_sal.end;
- else
- return start_pc + XTENSA_ENTRY_LENGTH;
- }
- else
- {
- internal_error (__FILE__, __LINE__,
- _("non-windowed configurations are not supported"));
- return start_pc;
+ return prologue_sal.end;
}
-}
-
-/* CONFIGURATION CHECK */
+ /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
+ body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
+ return body_pc != 0 ? body_pc : start_pc;
+}
/* Verify the current configuration. */
-
static void
xtensa_verify_config (struct gdbarch *gdbarch)
{
@@ -1596,22 +2401,29 @@ xtensa_verify_config (struct gdbarch *gd
/* Verify that we got a reasonable number of AREGS. */
if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
- fprintf_unfiltered (log, "\n\tnum_aregs: Number of AR registers (%d) "
- "is not a power of two!", tdep->num_aregs);
+ fprintf_unfiltered (log, _("\
+\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
+ tdep->num_aregs);
/* Verify that certain registers exist. */
+
if (tdep->pc_regnum == -1)
- fprintf_unfiltered (log, "\n\tpc_regnum: No PC register");
- if (tdep->ps_regnum == -1)
- fprintf_unfiltered (log, "\n\tps_regnum: No PS register");
- if (tdep->wb_regnum == -1)
- fprintf_unfiltered (log, "\n\twb_regnum: No WB register");
- if (tdep->ws_regnum == -1)
- fprintf_unfiltered (log, "\n\tws_regnum: No WS register");
- if (tdep->ar_base == -1)
- fprintf_unfiltered (log, "\n\tar_base: No AR registers");
+ fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
+ if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
+ fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
+
+ if (tdep->isa_use_windowed_registers)
+ {
+ if (tdep->wb_regnum == -1)
+ fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
+ if (tdep->ws_regnum == -1)
+ fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
+ if (tdep->ar_base == -1)
+ fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
+ }
+
if (tdep->a0_base == -1)
- fprintf_unfiltered (log, "\n\ta0_base: No Ax registers");
+ fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
buf = ui_file_xstrdup (log, &dummy);
make_cleanup (xfree, buf);
@@ -1622,8 +2434,84 @@ xtensa_verify_config (struct gdbarch *gd
}
+/* Derive specific register numbers from the array of registers. */
+
+void
+xtensa_derive_tdep (struct gdbarch_tdep *tdep)
+{
+ xtensa_register_t* rmap;
+ int n, max_size = 4;
+
+ tdep->num_regs = 0;
+ tdep->num_nopriv_regs = 0;
+
+#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */
+ for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
+ {
+ /* Target numbers match XTENSA_DBREGN_xxx macros in . */
+ if (rmap->target_number == 0x0020) /* pc */
+ tdep->pc_regnum = n;
+ else if (rmap->target_number == 0x0100) /* ar0 .. ar63 */
+ tdep->ar_base = n;
+ else if (rmap->target_number == 0x0000) /* a0 .. a15 */
+ tdep->a0_base = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) /* windowbase */
+ tdep->wb_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) /* windowstart */
+ tdep->ws_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) /* debugcause */
+ tdep->debugcause_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) /* exccause */
+ tdep->exccause_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) /* excvaddr */
+ tdep->excvaddr_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) /* lbeg */
+ tdep->lbeg_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) /* lend */
+ tdep->lend_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) /* lcount */
+ tdep->lcount_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) /* sar */
+ tdep->sar_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) /* litbase */
+ tdep->litbase_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) /* ps */
+ tdep->ps_regnum = n;
+#if 0
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) /* interrupt */
+ tdep->interrupt_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) /* interrupt2 */
+ tdep->interrupt2_regnum = n;
+ else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) /* cpenable */
+ tdep->cpenable_regnum = n;
+#endif
+
+ if (rmap->byte_size > max_size)
+ max_size = rmap->byte_size;
+ if (rmap->mask != 0 && tdep->num_regs == 0)
+ tdep->num_regs = n;
+ /* if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
+ && tdep->num_nopriv_regs == 0)
+ tdep->num_nopriv_regs = n;
+ */
+ if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
+ && tdep->num_regs == 0)
+ tdep->num_regs = n;
+ }
+
+ /* Number of pseudo registers. */
+ /* n++; we don't need to skip over frame pointer like we didi before. */
+ tdep->num_pseudo_regs = n - tdep->num_regs;
+
+ /* Empirically determined maximum sizes. */
+ tdep->max_register_raw_size = max_size;
+ tdep->max_register_virtual_size = max_size;
+}
+
/* Module "constructor" function. */
+extern struct gdbarch_tdep xtensa_tdep;
+
static struct gdbarch *
xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
@@ -1634,15 +2522,16 @@ xtensa_gdbarch_init (struct gdbarch_info
DEBUGTRACE ("gdbarch_init()\n");
/* We have to set the byte order before we call gdbarch_alloc. */
- info.byte_order = xtensa_config_byte_order (&info);
+ info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
- tdep = xtensa_config_tdep (&info);
+ tdep = &xtensa_tdep;
gdbarch = gdbarch_alloc (&info, tdep);
+ xtensa_derive_tdep (tdep);
/* Verify our configuration. */
xtensa_verify_config (gdbarch);
- /* Pseudo-Register read/write */
+ /* Pseudo-Register read/write. */
set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
@@ -1708,16 +2597,12 @@ xtensa_gdbarch_init (struct gdbarch_info
return gdbarch;
}
-
-/* Dump xtensa tdep structure. */
-
static void
xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
{
error (_("xtensa_dump_tdep(): not implemented"));
}
-
void
_initialize_xtensa_tdep (void)
{
diff -rNdup gdb-6.6.orig/gdb/xtensa-tdep.h gdb-6.6/gdb/xtensa-tdep.h
--- gdb-6.6.orig/gdb/xtensa-tdep.h 2006-11-14 13:53:59.000000000 -0800
+++ gdb-6.6/gdb/xtensa-tdep.h 2008-01-08 18:45:32.416524000 -0800
@@ -1,12 +1,12 @@
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -15,9 +15,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
+ along with this program. If not, see . */
/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
@@ -44,6 +42,8 @@ typedef enum
/* Xtensa register group. */
+#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
+
typedef enum
{
xtRegisterGroupUnknown = 0,
@@ -58,6 +58,17 @@ typedef enum
xtRegisterGroupFloat = 0x0400, /* Floating Point. */
xtRegisterGroupVectra = 0x0800, /* Vectra. */
xtRegisterGroupSystem = 0x1000, /* System. */
+
+ xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
+ xtRegisterGroupCP0 = 0x01000000, /* CP0. */
+ xtRegisterGroupCP1 = 0x02000000, /* CP1. */
+ xtRegisterGroupCP2 = 0x04000000, /* CP2. */
+ xtRegisterGroupCP3 = 0x08000000, /* CP3. */
+ xtRegisterGroupCP4 = 0x10000000, /* CP4. */
+ xtRegisterGroupCP5 = 0x20000000, /* CP5. */
+ xtRegisterGroupCP6 = 0x40000000, /* CP6. */
+ xtRegisterGroupCP7 = 0x80000000, /* CP7. */
+
} xtensa_register_group_t;
@@ -77,39 +88,32 @@ typedef unsigned long xtensa_elf_greg_t;
typedef struct
{
- xtensa_elf_greg_t xchal_config_id0;
- xtensa_elf_greg_t xchal_config_id1;
- xtensa_elf_greg_t cpux;
- xtensa_elf_greg_t cpuy;
xtensa_elf_greg_t pc;
xtensa_elf_greg_t ps;
- xtensa_elf_greg_t exccause;
- xtensa_elf_greg_t excvaddr;
- xtensa_elf_greg_t windowbase;
- xtensa_elf_greg_t windowstart;
xtensa_elf_greg_t lbeg;
xtensa_elf_greg_t lend;
xtensa_elf_greg_t lcount;
xtensa_elf_greg_t sar;
- xtensa_elf_greg_t syscall;
- xtensa_elf_greg_t ar[0]; /* variable size (per config). */
+ xtensa_elf_greg_t windowstart;
+ xtensa_elf_greg_t reserved[9+48];
+ xtensa_elf_greg_t ar[64];
} xtensa_elf_gregset_t;
-#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
-#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
-
+#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) / sizeof (xtensa_elf_greg_t))
/* Mask. */
typedef struct
{
+ int reg_num;
+ int bit_start;
+ int bit_size;
+} xtensa_reg_mask_t;
+
+typedef struct
+{
int count;
- struct
- {
- int reg_num;
- int bit_start;
- int bit_size;
- } mask[0];
+ xtensa_reg_mask_t *mask;
} xtensa_mask_t;
@@ -129,14 +133,20 @@ typedef struct
unsigned int target_number; /* Register target number. */
int flags; /* Flags. */
+ int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
const xtensa_mask_t *mask; /* Register is a compilation of other regs. */
const char *fetch; /* Instruction sequence to fetch register. */
const char *store; /* Instruction sequence to store register. */
} xtensa_register_t;
+/* For xtensa-config.c to expand to the structure above. */
+#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
+ {#name, ofs, ty, ((gr)|((xtRegisterGroupNCP>>2)<<(cp+2))), \
+ ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
+#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
-#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001
+#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
@@ -185,7 +195,8 @@ struct gdbarch_tdep
xtensa_register_t* regmap;
- unsigned int num_regs; /* Number of registers in regmap. */
+ unsigned int num_regs; /* Number of registers in register map. */
+ unsigned int num_nopriv_regs; /* Number of non-privileged registers. */
unsigned int num_pseudo_regs; /* Number of pseudo registers. */
unsigned int num_aregs; /* Size of register file. */
unsigned int num_contexts;
@@ -216,6 +227,65 @@ struct gdbarch_tdep
unsigned long *gregmap;
};
+/* Macro to instantiate a gdbarch_tdep structure. */
+
+#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
+ { \
+ .target_flags = 0, \
+ .spill_location = -1, \
+ .spill_size = (spillsz), \
+ .unused = 0, \
+ .call_abi = 0, \
+ .debug_interrupt_level = XCHAL_DEBUGLEVEL, \
+ .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
+ .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
+ .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
+ .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
+ .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
+ .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
+ .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
+ .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
+ .debug_num_ibreaks = XCHAL_NUM_IBREAK, \
+ .debug_num_dbreaks = XCHAL_NUM_DBREAK, \
+ .regmap = rmap, \
+ .num_regs = 0, \
+ .num_nopriv_regs = 0, \
+ .num_pseudo_regs = 0, \
+ .num_aregs = XCHAL_NUM_AREGS, \
+ .num_contexts = XCHAL_NUM_CONTEXTS, \
+ .ar_base = -1, \
+ .a0_base = -1, \
+ .wb_regnum = -1, \
+ .ws_regnum = -1, \
+ .pc_regnum = -1, \
+ .ps_regnum = -1, \
+ .lbeg_regnum = -1, \
+ .lend_regnum = -1, \
+ .lcount_regnum = -1, \
+ .sar_regnum = -1, \
+ .litbase_regnum = -1, \
+ .interrupt_regnum = -1, \
+ .interrupt2_regnum = -1, \
+ .cpenable_regnum = -1, \
+ .debugcause_regnum = -1, \
+ .exccause_regnum = -1, \
+ .excvaddr_regnum = -1, \
+ .max_register_raw_size = 0, \
+ .max_register_virtual_size = 0, \
+ .fp_layout = 0, \
+ .fp_layout_bytes = 0, \
+ .gregmap = 0, \
+ }
+#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
+ struct gdbarch_tdep xtensa_tdep = \
+ XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
+
+#ifndef XCHAL_NUM_CONTEXTS
+#define XCHAL_NUM_CONTEXTS 0
+#endif
+#ifndef XCHAL_HAVE_EXCEPTIONS
+#define XCHAL_HAVE_EXCEPTIONS 1
+#endif
/* Define macros to access some of the gdbarch entries. */
#define XTENSA_TARGET_FLAGS \
@@ -262,7 +332,6 @@ struct gdbarch_tdep
#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes)
#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base)
#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base)
-#define FP_ALIAS (NUM_REGS + NUM_PSEUDO_REGS)
#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi)
#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts)
diff -rNdup gdb-6.6.orig/include/xtensa-regmap.h gdb-6.6/include/xtensa-regmap.h
--- gdb-6.6.orig/include/xtensa-regmap.h 1969-12-31 16:00:00.000000000 -0800
+++ gdb-6.6/include/xtensa-regmap.h 2008-01-08 19:01:36.806170000 -0800
@@ -0,0 +1,37 @@
+/* Xtensa-specific coprocessor register mapping table.
+ Copyright 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#ifndef XTENSA_REGMAP_H
+#define XTENSA_REGMAP_H
+
+typedef struct {
+ int gdb_regnum;
+ int gdb_offset;
+ int ptrace_cp_offset;
+ int ptrace_offset;
+ int size;
+ int coproc;
+ int dbnum;
+ char* name;
+} xtensa_regtable_t;
+
+extern const xtensa_regtable_t xtensa_regmap_table[];
+
+#endif /* XTENSA_REGMAP_H */